Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 10, .max = 22 },
 172         .m2 = { .min = 5, .max = 9 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         unsigned long flags;
 420         u32 val = 0;
 421
 422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO idle wait timed out\n");
 425                 goto out_unlock;
 426         }
 427
 428         I915_WRITE(DPIO_REG, reg);
 429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 430                    DPIO_BYTE);
 431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 432                 DRM_ERROR("DPIO read wait timed out\n");
 433                 goto out_unlock;
 434         }
 435         val = I915_READ(DPIO_DATA);
 436
 437 out_unlock:
 438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 439         return val;
 440 }
 441
 442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 443                              u32 val)
 444 {
 445         unsigned long flags;
 446
 447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 449                 DRM_ERROR("DPIO idle wait timed out\n");
 450                 goto out_unlock;
 451         }
 452
 453         I915_WRITE(DPIO_DATA, val);
 454         I915_WRITE(DPIO_REG, reg);
 455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 456                    DPIO_BYTE);
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 458                 DRM_ERROR("DPIO write wait timed out\n");
 459
 460 out_unlock:
 461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 462 }
 463
 464 static void vlv_init_dpio(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         /* Reset the DPIO config */
 469         I915_WRITE(DPIO_CTL, 0);
 470         POSTING_READ(DPIO_CTL);
 471         I915_WRITE(DPIO_CTL, 1);
 472         POSTING_READ(DPIO_CTL);
 473 }
 474
 475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 476 {
 477         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 478         return 1;
 479 }
 480
 481 static const struct dmi_system_id intel_dual_link_lvds[] = {
 482         {
 483                 .callback = intel_dual_link_lvds_callback,
 484                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 485                 .matches = {
 486                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 487                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 488                 },
 489         },
 490         { }     /* terminating entry */
 491 };
 492
 493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 494                               unsigned int reg)
 495 {
 496         unsigned int val;
 497
 498         /* use the module option value if specified */
 499         if (i915_lvds_channel_mode > 0)
 500                 return i915_lvds_channel_mode == 2;
 501
 502         if (dmi_check_system(intel_dual_link_lvds))
 503                 return true;
 504
 505         if (dev_priv->lvds_val)
 506                 val = dev_priv->lvds_val;
 507         else {
 508                 /* BIOS should set the proper LVDS register value at boot, but
 509                  * in reality, it doesn't set the value when the lid is closed;
 510                  * we need to check "the value to be set" in VBT when LVDS
 511                  * register is uninitialized.
 512                  */
 513                 val = I915_READ(reg);
 514                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 515                         val = dev_priv->bios_lvds_val;
 516                 dev_priv->lvds_val = val;
 517         }
 518         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 519 }
 520
 521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 522                                                 int refclk)
 523 {
 524         struct drm_device *dev = crtc->dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         const intel_limit_t *limit;
 527
 528         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 529                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 530                         /* LVDS dual channel */
 531                         if (refclk == 100000)
 532                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 533                         else
 534                                 limit = &intel_limits_ironlake_dual_lvds;
 535                 } else {
 536                         if (refclk == 100000)
 537                                 limit = &intel_limits_ironlake_single_lvds_100m;
 538                         else
 539                                 limit = &intel_limits_ironlake_single_lvds;
 540                 }
 541         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 542                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 543                 limit = &intel_limits_ironlake_display_port;
 544         else
 545                 limit = &intel_limits_ironlake_dac;
 546
 547         return limit;
 548 }
 549
 550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         const intel_limit_t *limit;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 if (is_dual_link_lvds(dev_priv, LVDS))
 558                         /* LVDS with dual channel */
 559                         limit = &intel_limits_g4x_dual_channel_lvds;
 560                 else
 561                         /* LVDS with dual channel */
 562                         limit = &intel_limits_g4x_single_channel_lvds;
 563         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 564                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 565                 limit = &intel_limits_g4x_hdmi;
 566         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 567                 limit = &intel_limits_g4x_sdvo;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 569                 limit = &intel_limits_g4x_display_port;
 570         } else /* The option is for other outputs */
 571                 limit = &intel_limits_i9xx_sdvo;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 577 {
 578         struct drm_device *dev = crtc->dev;
 579         const intel_limit_t *limit;
 580
 581         if (HAS_PCH_SPLIT(dev))
 582                 limit = intel_ironlake_limit(crtc, refclk);
 583         else if (IS_G4X(dev)) {
 584                 limit = intel_g4x_limit(crtc);
 585         } else if (IS_PINEVIEW(dev)) {
 586                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 587                         limit = &intel_limits_pineview_lvds;
 588                 else
 589                         limit = &intel_limits_pineview_sdvo;
 590         } else if (IS_VALLEYVIEW(dev)) {
 591                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 592                         limit = &intel_limits_vlv_dac;
 593                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 594                         limit = &intel_limits_vlv_hdmi;
 595                 else
 596                         limit = &intel_limits_vlv_dp;
 597         } else if (!IS_GEN2(dev)) {
 598                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 599                         limit = &intel_limits_i9xx_lvds;
 600                 else
 601                         limit = &intel_limits_i9xx_sdvo;
 602         } else {
 603                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 604                         limit = &intel_limits_i8xx_lvds;
 605                 else
 606                         limit = &intel_limits_i8xx_dvo;
 607         }
 608         return limit;
 609 }
 610
 611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 612 static void pineview_clock(int refclk, intel_clock_t *clock)
 613 {
 614         clock->m = clock->m2 + 2;
 615         clock->p = clock->p1 * clock->p2;
 616         clock->vco = refclk * clock->m / clock->n;
 617         clock->dot = clock->vco / clock->p;
 618 }
 619
 620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 621 {
 622         if (IS_PINEVIEW(dev)) {
 623                 pineview_clock(refclk, clock);
 624                 return;
 625         }
 626         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 627         clock->p = clock->p1 * clock->p2;
 628         clock->vco = refclk * clock->m / (clock->n + 2);
 629         clock->dot = clock->vco / clock->p;
 630 }
 631
 632 /**
 633  * Returns whether any output on the specified pipe is of the specified type
 634  */
 635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct intel_encoder *encoder;
 639
 640         for_each_encoder_on_crtc(dev, crtc, encoder)
 641                 if (encoder->type == type)
 642                         return true;
 643
 644         return false;
 645 }
 646
 647 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 648 /**
 649  * Returns whether the given set of divisors are valid for a given refclk with
 650  * the given connectors.
 651  */
 652
 653 static bool intel_PLL_is_valid(struct drm_device *dev,
 654                                const intel_limit_t *limit,
 655                                const intel_clock_t *clock)
 656 {
 657         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 658                 INTELPllInvalid("p1 out of range\n");
 659         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 660                 INTELPllInvalid("p out of range\n");
 661         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 662                 INTELPllInvalid("m2 out of range\n");
 663         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 664                 INTELPllInvalid("m1 out of range\n");
 665         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 666                 INTELPllInvalid("m1 <= m2\n");
 667         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 668                 INTELPllInvalid("m out of range\n");
 669         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 670                 INTELPllInvalid("n out of range\n");
 671         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 672                 INTELPllInvalid("vco out of range\n");
 673         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 674          * connector, etc., rather than just a single range.
 675          */
 676         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 677                 INTELPllInvalid("dot out of range\n");
 678
 679         return true;
 680 }
 681
 682 static bool
 683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                     int target, int refclk, intel_clock_t *match_clock,
 685                     intel_clock_t *best_clock)
 686
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         intel_clock_t clock;
 691         int err = target;
 692
 693         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 694             (I915_READ(LVDS)) != 0) {
 695                 /*
 696                  * For LVDS, if the panel is on, just rely on its current
 697                  * settings for dual-channel.  We haven't figured out how to
 698                  * reliably set up different single/dual channel state, if we
 699                  * even can.
 700                  */
 701                 if (is_dual_link_lvds(dev_priv, LVDS))
 702                         clock.p2 = limit->p2.p2_fast;
 703                 else
 704                         clock.p2 = limit->p2.p2_slow;
 705         } else {
 706                 if (target < limit->p2.dot_limit)
 707                         clock.p2 = limit->p2.p2_slow;
 708                 else
 709                         clock.p2 = limit->p2.p2_fast;
 710         }
 711
 712         memset(best_clock, 0, sizeof(*best_clock));
 713
 714         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 715              clock.m1++) {
 716                 for (clock.m2 = limit->m2.min;
 717                      clock.m2 <= limit->m2.max; clock.m2++) {
 718                         /* m1 is always 0 in Pineview */
 719                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 720                                 break;
 721                         for (clock.n = limit->n.min;
 722                              clock.n <= limit->n.max; clock.n++) {
 723                                 for (clock.p1 = limit->p1.min;
 724                                         clock.p1 <= limit->p1.max; clock.p1++) {
 725                                         int this_err;
 726
 727                                         intel_clock(dev, refclk, &clock);
 728                                         if (!intel_PLL_is_valid(dev, limit,
 729                                                                 &clock))
 730                                                 continue;
 731                                         if (match_clock &&
 732                                             clock.p != match_clock->p)
 733                                                 continue;
 734
 735                                         this_err = abs(clock.dot - target);
 736                                         if (this_err < err) {
 737                                                 *best_clock = clock;
 738                                                 err = this_err;
 739                                         }
 740                                 }
 741                         }
 742                 }
 743         }
 744
 745         return (err != target);
 746 }
 747
 748 static bool
 749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 750                         int target, int refclk, intel_clock_t *match_clock,
 751                         intel_clock_t *best_clock)
 752 {
 753         struct drm_device *dev = crtc->dev;
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         intel_clock_t clock;
 756         int max_n;
 757         bool found;
 758         /* approximately equals target * 0.00585 */
 759         int err_most = (target >> 8) + (target >> 9);
 760         found = false;
 761
 762         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 763                 int lvds_reg;
 764
 765                 if (HAS_PCH_SPLIT(dev))
 766                         lvds_reg = PCH_LVDS;
 767                 else
 768                         lvds_reg = LVDS;
 769                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 770                     LVDS_CLKB_POWER_UP)
 771                         clock.p2 = limit->p2.p2_fast;
 772                 else
 773                         clock.p2 = limit->p2.p2_slow;
 774         } else {
 775                 if (target < limit->p2.dot_limit)
 776                         clock.p2 = limit->p2.p2_slow;
 777                 else
 778                         clock.p2 = limit->p2.p2_fast;
 779         }
 780
 781         memset(best_clock, 0, sizeof(*best_clock));
 782         max_n = limit->n.max;
 783         /* based on hardware requirement, prefer smaller n to precision */
 784         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 785                 /* based on hardware requirement, prefere larger m1,m2 */
 786                 for (clock.m1 = limit->m1.max;
 787                      clock.m1 >= limit->m1.min; clock.m1--) {
 788                         for (clock.m2 = limit->m2.max;
 789                              clock.m2 >= limit->m2.min; clock.m2--) {
 790                                 for (clock.p1 = limit->p1.max;
 791                                      clock.p1 >= limit->p1.min; clock.p1--) {
 792                                         int this_err;
 793
 794                                         intel_clock(dev, refclk, &clock);
 795                                         if (!intel_PLL_is_valid(dev, limit,
 796                                                                 &clock))
 797                                                 continue;
 798                                         if (match_clock &&
 799                                             clock.p != match_clock->p)
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err_most) {
 804                                                 *best_clock = clock;
 805                                                 err_most = this_err;
 806                                                 max_n = clock.n;
 807                                                 found = true;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813         return found;
 814 }
 815
 816 static bool
 817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                            int target, int refclk, intel_clock_t *match_clock,
 819                            intel_clock_t *best_clock)
 820 {
 821         struct drm_device *dev = crtc->dev;
 822         intel_clock_t clock;
 823
 824         if (target < 200000) {
 825                 clock.n = 1;
 826                 clock.p1 = 2;
 827                 clock.p2 = 10;
 828                 clock.m1 = 12;
 829                 clock.m2 = 9;
 830         } else {
 831                 clock.n = 2;
 832                 clock.p1 = 1;
 833                 clock.p2 = 10;
 834                 clock.m1 = 14;
 835                 clock.m2 = 8;
 836         }
 837         intel_clock(dev, refclk, &clock);
 838         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 839         return true;
 840 }
 841
 842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 843 static bool
 844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 845                       int target, int refclk, intel_clock_t *match_clock,
 846                       intel_clock_t *best_clock)
 847 {
 848         intel_clock_t clock;
 849         if (target < 200000) {
 850                 clock.p1 = 2;
 851                 clock.p2 = 10;
 852                 clock.n = 2;
 853                 clock.m1 = 23;
 854                 clock.m2 = 8;
 855         } else {
 856                 clock.p1 = 1;
 857                 clock.p2 = 10;
 858                 clock.n = 1;
 859                 clock.m1 = 14;
 860                 clock.m2 = 2;
 861         }
 862         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 863         clock.p = (clock.p1 * clock.p2);
 864         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 865         clock.vco = 0;
 866         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 867         return true;
 868 }
 869 static bool
 870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *match_clock,
 872                         intel_clock_t *best_clock)
 873 {
 874         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 875         u32 m, n, fastclk;
 876         u32 updrate, minupdate, fracbits, p;
 877         unsigned long bestppm, ppm, absppm;
 878         int dotclk, flag;
 879
 880         flag = 0;
 881         dotclk = target * 1000;
 882         bestppm = 1000000;
 883         ppm = absppm = 0;
 884         fastclk = dotclk / (2*100);
 885         updrate = 0;
 886         minupdate = 19200;
 887         fracbits = 1;
 888         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 889         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 890
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 893                 updrate = refclk / n;
 894                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 895                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 896                                 if (p2 > 10)
 897                                         p2 = p2 - 1;
 898                                 p = p1 * p2;
 899                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 900                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 901                                         m2 = (((2*(fastclk * p * n / m1 )) +
 902                                                refclk) / (2*refclk));
 903                                         m = m1 * m2;
 904                                         vco = updrate * m;
 905                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 906                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 907                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 908                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 909                                                         bestppm = 0;
 910                                                         flag = 1;
 911                                                 }
 912                                                 if (absppm < bestppm - 10) {
 913                                                         bestppm = absppm;
 914                                                         flag = 1;
 915                                                 }
 916                                                 if (flag) {
 917                                                         bestn = n;
 918                                                         bestm1 = m1;
 919                                                         bestm2 = m2;
 920                                                         bestp1 = p1;
 921                                                         bestp2 = p2;
 922                                                         flag = 0;
 923                                                 }
 924                                         }
 925                                 }
 926                         }
 927                 }
 928         }
 929         best_clock->n = bestn;
 930         best_clock->m1 = bestm1;
 931         best_clock->m2 = bestm2;
 932         best_clock->p1 = bestp1;
 933         best_clock->p2 = bestp2;
 934
 935         return true;
 936 }
 937
 938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 939                                              enum pipe pipe)
 940 {
 941         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 943
 944         return intel_crtc->cpu_transcoder;
 945 }
 946
 947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 948 {
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         u32 frame, frame_reg = PIPEFRAME(pipe);
 951
 952         frame = I915_READ(frame_reg);
 953
 954         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 955                 DRM_DEBUG_KMS("vblank wait timed out\n");
 956 }
 957
 958 /**
 959  * intel_wait_for_vblank - wait for vblank on a given pipe
 960  * @dev: drm device
 961  * @pipe: pipe to wait for
 962  *
 963  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 964  * mode setting code.
 965  */
 966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 967 {
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         int pipestat_reg = PIPESTAT(pipe);
 970
 971         if (INTEL_INFO(dev)->gen >= 5) {
 972                 ironlake_wait_for_vblank(dev, pipe);
 973                 return;
 974         }
 975
 976         /* Clear existing vblank status. Note this will clear any other
 977          * sticky status fields as well.
 978          *
 979          * This races with i915_driver_irq_handler() with the result
 980          * that either function could miss a vblank event.  Here it is not
 981          * fatal, as we will either wait upon the next vblank interrupt or
 982          * timeout.  Generally speaking intel_wait_for_vblank() is only
 983          * called during modeset at which time the GPU should be idle and
 984          * should *not* be performing page flips and thus not waiting on
 985          * vblanks...
 986          * Currently, the result of us stealing a vblank from the irq
 987          * handler is that a single frame will be skipped during swapbuffers.
 988          */
 989         I915_WRITE(pipestat_reg,
 990                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 991
 992         /* Wait for vblank interrupt bit to set */
 993         if (wait_for(I915_READ(pipestat_reg) &
 994                      PIPE_VBLANK_INTERRUPT_STATUS,
 995                      50))
 996                 DRM_DEBUG_KMS("vblank wait timed out\n");
 997 }
 998
 999 /*
1000  * intel_wait_for_pipe_off - wait for pipe to turn off
1001  * @dev: drm device
1002  * @pipe: pipe to wait for
1003  *
1004  * After disabling a pipe, we can't wait for vblank in the usual way,
1005  * spinning on the vblank interrupt status bit, since we won't actually
1006  * see an interrupt when the pipe is disabled.
1007  *
1008  * On Gen4 and above:
1009  *   wait for the pipe register state bit to turn off
1010  *
1011  * Otherwise:
1012  *   wait for the display line value to settle (it usually
1013  *   ends up stopping at the start of the next frame).
1014  *
1015  */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020                                                                       pipe);
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(cpu_transcoder);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126                                                                       pipe);
1127
1128         if (IS_HASWELL(dev_priv->dev)) {
1129                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 reg = FDI_TX_CTL(pipe);
1135                 val = I915_READ(reg);
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151
1152         reg = FDI_RX_CTL(pipe);
1153         val = I915_READ(reg);
1154         cur_state = !!(val & FDI_RX_ENABLE);
1155         WARN(cur_state != state,
1156              "FDI RX state assertion failure (expected %s, current %s)\n",
1157              state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163                                       enum pipe pipe)
1164 {
1165         int reg;
1166         u32 val;
1167
1168         /* ILK FDI PLL is always enabled */
1169         if (dev_priv->info->gen == 5)
1170                 return;
1171
1172         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173         if (IS_HASWELL(dev_priv->dev))
1174                 return;
1175
1176         reg = FDI_TX_CTL(pipe);
1177         val = I915_READ(reg);
1178         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182                                       enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         reg = FDI_RX_CTL(pipe);
1188         val = I915_READ(reg);
1189         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222                  enum pipe pipe, bool state)
1223 {
1224         int reg;
1225         u32 val;
1226         bool cur_state;
1227         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228                                                                       pipe);
1229
1230         /* if we need the pipe A quirk it must be always on */
1231         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232                 state = true;
1233
1234         reg = PIPECONF(cpu_transcoder);
1235         val = I915_READ(reg);
1236         cur_state = !!(val & PIPECONF_ENABLE);
1237         WARN(cur_state != state,
1238              "pipe %c assertion failure (expected %s, current %s)\n",
1239              pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243                          enum plane plane, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = DSPCNTR(plane);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252         WARN(cur_state != state,
1253              "plane %c assertion failure (expected %s, current %s)\n",
1254              plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261                                    enum pipe pipe)
1262 {
1263         int reg, i;
1264         u32 val;
1265         int cur_pipe;
1266
1267         /* Planes are fixed to pipes on ILK+ */
1268         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269                 reg = DSPCNTR(pipe);
1270                 val = I915_READ(reg);
1271                 WARN((val & DISPLAY_PLANE_ENABLE),
1272                      "plane %c assertion failure, should be disabled but not\n",
1273                      plane_name(pipe));
1274                 return;
1275         }
1276
1277         /* Need to check both planes against the pipe */
1278         for (i = 0; i < 2; i++) {
1279                 reg = DSPCNTR(i);
1280                 val = I915_READ(reg);
1281                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282                         DISPPLANE_SEL_PIPE_SHIFT;
1283                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285                      plane_name(i), pipe_name(pipe));
1286         }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291         u32 val;
1292         bool enabled;
1293
1294         if (HAS_PCH_LPT(dev_priv->dev)) {
1295                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296                 return;
1297         }
1298
1299         val = I915_READ(PCH_DREF_CONTROL);
1300         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301                             DREF_SUPERSPREAD_SOURCE_MASK));
1302         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306                                        enum pipe pipe)
1307 {
1308         int reg;
1309         u32 val;
1310         bool enabled;
1311
1312         reg = TRANSCONF(pipe);
1313         val = I915_READ(reg);
1314         enabled = !!(val & TRANS_ENABLE);
1315         WARN(enabled,
1316              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317              pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321                             enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323         if ((val & DP_PORT_EN) == 0)
1324                 return false;
1325
1326         if (HAS_PCH_CPT(dev_priv->dev)) {
1327                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330                         return false;
1331         } else {
1332                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333                         return false;
1334         }
1335         return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339                               enum pipe pipe, u32 val)
1340 {
1341         if ((val & PORT_ENABLE) == 0)
1342                 return false;
1343
1344         if (HAS_PCH_CPT(dev_priv->dev)) {
1345                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346                         return false;
1347         } else {
1348                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349                         return false;
1350         }
1351         return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355                               enum pipe pipe, u32 val)
1356 {
1357         if ((val & LVDS_PORT_EN) == 0)
1358                 return false;
1359
1360         if (HAS_PCH_CPT(dev_priv->dev)) {
1361                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & ADPA_DAC_ENABLE) == 0)
1374                 return false;
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe, int reg, u32 port_sel)
1387 {
1388         u32 val = I915_READ(reg);
1389         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391              reg, pipe_name(pipe));
1392
1393         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394              && (val & DP_PIPEB_SELECT),
1395              "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399                                      enum pipe pipe, int reg)
1400 {
1401         u32 val = I915_READ(reg);
1402         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404              reg, pipe_name(pipe));
1405
1406         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407              && (val & SDVO_PIPE_B_SELECT),
1408              "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412                                       enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421         reg = PCH_ADPA;
1422         val = I915_READ(reg);
1423         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424              "PCH VGA enabled on transcoder %c, should be disabled\n",
1425              pipe_name(pipe));
1426
1427         reg = PCH_LVDS;
1428         val = I915_READ(reg);
1429         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431              pipe_name(pipe));
1432
1433         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439  * intel_enable_pll - enable a PLL
1440  * @dev_priv: i915 private structure
1441  * @pipe: pipe PLL to enable
1442  *
1443  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1444  * make sure the PLL reg is writable first though, since the panel write
1445  * protect mechanism may be enabled.
1446  *
1447  * Note!  This is for pre-ILK only.
1448  *
1449  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450  */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453         int reg;
1454         u32 val;
1455
1456         /* No really, not for ILK+ */
1457         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459         /* PLL is protected by panel, make sure we can write it */
1460         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461                 assert_panel_unlocked(dev_priv, pipe);
1462
1463         reg = DPLL(pipe);
1464         val = I915_READ(reg);
1465         val |= DPLL_VCO_ENABLE;
1466
1467         /* We do this three times for luck */
1468         I915_WRITE(reg, val);
1469         POSTING_READ(reg);
1470         udelay(150); /* wait for warmup */
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, val);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480  * intel_disable_pll - disable a PLL
1481  * @dev_priv: i915 private structure
1482  * @pipe: pipe PLL to disable
1483  *
1484  * Disable the PLL for @pipe, making sure the pipe is off first.
1485  *
1486  * Note!  This is for pre-ILK only.
1487  */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490         int reg;
1491         u32 val;
1492
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         reg = DPLL(pipe);
1501         val = I915_READ(reg);
1502         val &= ~DPLL_VCO_ENABLE;
1503         I915_WRITE(reg, val);
1504         POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510 {
1511         unsigned long flags;
1512
1513         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517                 goto out_unlock;
1518         }
1519
1520         I915_WRITE(SBI_ADDR,
1521                         (reg << 16));
1522         I915_WRITE(SBI_DATA,
1523                         value);
1524         I915_WRITE(SBI_CTL_STAT,
1525                         SBI_BUSY |
1526                         SBI_CTL_OP_CRWR);
1527
1528         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1529                                 100)) {
1530                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531                 goto out_unlock;
1532         }
1533
1534 out_unlock:
1535         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536 }
1537
1538 static u32
1539 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540 {
1541         unsigned long flags;
1542         u32 value = 0;
1543
1544         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1545         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1546                                 100)) {
1547                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548                 goto out_unlock;
1549         }
1550
1551         I915_WRITE(SBI_ADDR,
1552                         (reg << 16));
1553         I915_WRITE(SBI_CTL_STAT,
1554                         SBI_BUSY |
1555                         SBI_CTL_OP_CRRD);
1556
1557         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1558                                 100)) {
1559                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560                 goto out_unlock;
1561         }
1562
1563         value = I915_READ(SBI_DATA);
1564
1565 out_unlock:
1566         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567         return value;
1568 }
1569
1570 /**
1571  * ironlake_enable_pch_pll - enable PCH PLL
1572  * @dev_priv: i915 private structure
1573  * @pipe: pipe PLL to enable
1574  *
1575  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576  * drives the transcoder clock.
1577  */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581         struct intel_pch_pll *pll;
1582         int reg;
1583         u32 val;
1584
1585         /* PCH PLLs only available on ILK, SNB and IVB */
1586         BUG_ON(dev_priv->info->gen < 5);
1587         pll = intel_crtc->pch_pll;
1588         if (pll == NULL)
1589                 return;
1590
1591         if (WARN_ON(pll->refcount == 0))
1592                 return;
1593
1594         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595                       pll->pll_reg, pll->active, pll->on,
1596                       intel_crtc->base.base.id);
1597
1598         /* PCH refclock must be enabled first */
1599         assert_pch_refclk_enabled(dev_priv);
1600
1601         if (pll->active++ && pll->on) {
1602                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603                 return;
1604         }
1605
1606         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608         reg = pll->pll_reg;
1609         val = I915_READ(reg);
1610         val |= DPLL_VCO_ENABLE;
1611         I915_WRITE(reg, val);
1612         POSTING_READ(reg);
1613         udelay(200);
1614
1615         pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622         int reg;
1623         u32 val;
1624
1625         /* PCH only available on ILK+ */
1626         BUG_ON(dev_priv->info->gen < 5);
1627         if (pll == NULL)
1628                return;
1629
1630         if (WARN_ON(pll->refcount == 0))
1631                 return;
1632
1633         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634                       pll->pll_reg, pll->active, pll->on,
1635                       intel_crtc->base.base.id);
1636
1637         if (WARN_ON(pll->active == 0)) {
1638                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639                 return;
1640         }
1641
1642         if (--pll->active) {
1643                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644                 return;
1645         }
1646
1647         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649         /* Make sure transcoder isn't still depending on us */
1650         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652         reg = pll->pll_reg;
1653         val = I915_READ(reg);
1654         val &= ~DPLL_VCO_ENABLE;
1655         I915_WRITE(reg, val);
1656         POSTING_READ(reg);
1657         udelay(200);
1658
1659         pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                            enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667         uint32_t reg, val, pipeconf_val;
1668
1669         /* PCH only available on ILK+ */
1670         BUG_ON(dev_priv->info->gen < 5);
1671
1672         /* Make sure PCH DPLL is enabled */
1673         assert_pch_pll_enabled(dev_priv,
1674                                to_intel_crtc(crtc)->pch_pll,
1675                                to_intel_crtc(crtc));
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, pipe);
1679         assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681         if (HAS_PCH_CPT(dev)) {
1682                 /* Workaround: Set the timing override bit before enabling the
1683                  * pch transcoder. */
1684                 reg = TRANS_CHICKEN2(pipe);
1685                 val = I915_READ(reg);
1686                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv->dev)) {
1695                 /*
1696                  * make the BPC in transcoder be consistent with
1697                  * that in pipeconf reg.
1698                  */
1699                 val &= ~PIPE_BPC_MASK;
1700                 val |= pipeconf_val & PIPE_BPC_MASK;
1701         }
1702
1703         val &= ~TRANS_INTERLACE_MASK;
1704         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705                 if (HAS_PCH_IBX(dev_priv->dev) &&
1706                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707                         val |= TRANS_LEGACY_INTERLACED_ILK;
1708                 else
1709                         val |= TRANS_INTERLACED;
1710         else
1711                 val |= TRANS_PROGRESSIVE;
1712
1713         I915_WRITE(reg, val | TRANS_ENABLE);
1714         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719                                       enum transcoder cpu_transcoder)
1720 {
1721         u32 val, pipeconf_val;
1722
1723         /* PCH only available on ILK+ */
1724         BUG_ON(dev_priv->info->gen < 5);
1725
1726         /* FDI must be feeding us bits for PCH ports */
1727         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730         /* Workaround: set timing override bit. */
1731         val = I915_READ(_TRANSA_CHICKEN2);
1732         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733         I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735         val = TRANS_ENABLE;
1736         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739             PIPECONF_INTERLACED_ILK)
1740                 val |= TRANS_INTERLACED;
1741         else
1742                 val |= TRANS_PROGRESSIVE;
1743
1744         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746                 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                             enum pipe pipe)
1751 {
1752         struct drm_device *dev = dev_priv->dev;
1753         uint32_t reg, val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = TRANSCONF(pipe);
1763         val = I915_READ(reg);
1764         val &= ~TRANS_ENABLE;
1765         I915_WRITE(reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770         if (!HAS_PCH_IBX(dev)) {
1771                 /* Workaround: Clear the timing override chicken bit again. */
1772                 reg = TRANS_CHICKEN2(pipe);
1773                 val = I915_READ(reg);
1774                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775                 I915_WRITE(reg, val);
1776         }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781         u32 val;
1782
1783         val = I915_READ(_TRANSACONF);
1784         val &= ~TRANS_ENABLE;
1785         I915_WRITE(_TRANSACONF, val);
1786         /* wait for PCH transcoder off, transcoder state */
1787         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788                 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790         /* Workaround: clear timing override bit. */
1791         val = I915_READ(_TRANSA_CHICKEN2);
1792         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793         I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797  * intel_enable_pipe - enable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to enable
1800  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801  *
1802  * Enable @pipe, making sure that various hardware specific requirements
1803  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804  *
1805  * @pipe should be %PIPE_A or %PIPE_B.
1806  *
1807  * Will wait until the pipe is actually running (i.e. first vblank) before
1808  * returning.
1809  */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811                               bool pch_port)
1812 {
1813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814                                                                       pipe);
1815         enum transcoder pch_transcoder;
1816         int reg;
1817         u32 val;
1818
1819         if (IS_HASWELL(dev_priv->dev))
1820                 pch_transcoder = TRANSCODER_A;
1821         else
1822                 pch_transcoder = pipe;
1823
1824         /*
1825          * A pipe without a PLL won't actually be able to drive bits from
1826          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1827          * need the check.
1828          */
1829         if (!HAS_PCH_SPLIT(dev_priv->dev))
1830                 assert_pll_enabled(dev_priv, pipe);
1831         else {
1832                 if (pch_port) {
1833                         /* if driving the PCH, we need FDI enabled */
1834                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1836                 }
1837                 /* FIXME: assert CPU port conditions for SNB+ */
1838         }
1839
1840         reg = PIPECONF(cpu_transcoder);
1841         val = I915_READ(reg);
1842         if (val & PIPECONF_ENABLE)
1843                 return;
1844
1845         I915_WRITE(reg, val | PIPECONF_ENABLE);
1846         intel_wait_for_vblank(dev_priv->dev, pipe);
1847 }
1848
1849 /**
1850  * intel_disable_pipe - disable a pipe, asserting requirements
1851  * @dev_priv: i915 private structure
1852  * @pipe: pipe to disable
1853  *
1854  * Disable @pipe, making sure that various hardware specific requirements
1855  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856  *
1857  * @pipe should be %PIPE_A or %PIPE_B.
1858  *
1859  * Will wait until the pipe has shut down before returning.
1860  */
1861 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862                                enum pipe pipe)
1863 {
1864         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865                                                                       pipe);
1866         int reg;
1867         u32 val;
1868
1869         /*
1870          * Make sure planes won't keep trying to pump pixels to us,
1871          * or we might hang the display.
1872          */
1873         assert_planes_disabled(dev_priv, pipe);
1874
1875         /* Don't disable pipe A or pipe A PLLs if needed */
1876         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877                 return;
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = I915_READ(reg);
1881         if ((val & PIPECONF_ENABLE) == 0)
1882                 return;
1883
1884         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1885         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886 }
1887
1888 /*
1889  * Plane regs are double buffered, going from enabled->disabled needs a
1890  * trigger in order to latch.  The display address reg provides this.
1891  */
1892 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1893                                       enum plane plane)
1894 {
1895         if (dev_priv->info->gen >= 4)
1896                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897         else
1898                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1899 }
1900
1901 /**
1902  * intel_enable_plane - enable a display plane on a given pipe
1903  * @dev_priv: i915 private structure
1904  * @plane: plane to enable
1905  * @pipe: pipe being fed
1906  *
1907  * Enable @plane on @pipe, making sure that @pipe is running first.
1908  */
1909 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910                                enum plane plane, enum pipe pipe)
1911 {
1912         int reg;
1913         u32 val;
1914
1915         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916         assert_pipe_enabled(dev_priv, pipe);
1917
1918         reg = DSPCNTR(plane);
1919         val = I915_READ(reg);
1920         if (val & DISPLAY_PLANE_ENABLE)
1921                 return;
1922
1923         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1924         intel_flush_display_plane(dev_priv, plane);
1925         intel_wait_for_vblank(dev_priv->dev, pipe);
1926 }
1927
1928 /**
1929  * intel_disable_plane - disable a display plane
1930  * @dev_priv: i915 private structure
1931  * @plane: plane to disable
1932  * @pipe: pipe consuming the data
1933  *
1934  * Disable @plane; should be an independent operation.
1935  */
1936 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937                                 enum plane plane, enum pipe pipe)
1938 {
1939         int reg;
1940         u32 val;
1941
1942         reg = DSPCNTR(plane);
1943         val = I915_READ(reg);
1944         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945                 return;
1946
1947         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1948         intel_flush_display_plane(dev_priv, plane);
1949         intel_wait_for_vblank(dev_priv->dev, pipe);
1950 }
1951
1952 int
1953 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1954                            struct drm_i915_gem_object *obj,
1955                            struct intel_ring_buffer *pipelined)
1956 {
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         u32 alignment;
1959         int ret;
1960
1961         switch (obj->tiling_mode) {
1962         case I915_TILING_NONE:
1963                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964                         alignment = 128 * 1024;
1965                 else if (INTEL_INFO(dev)->gen >= 4)
1966                         alignment = 4 * 1024;
1967                 else
1968                         alignment = 64 * 1024;
1969                 break;
1970         case I915_TILING_X:
1971                 /* pin() will align the object as required by fence */
1972                 alignment = 0;
1973                 break;
1974         case I915_TILING_Y:
1975                 /* FIXME: Is this true? */
1976                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977                 return -EINVAL;
1978         default:
1979                 BUG();
1980         }
1981
1982         dev_priv->mm.interruptible = false;
1983         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1984         if (ret)
1985                 goto err_interruptible;
1986
1987         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988          * fence, whereas 965+ only requires a fence if using
1989          * framebuffer compression.  For simplicity, we always install
1990          * a fence as the cost is not that onerous.
1991          */
1992         ret = i915_gem_object_get_fence(obj);
1993         if (ret)
1994                 goto err_unpin;
1995
1996         i915_gem_object_pin_fence(obj);
1997
1998         dev_priv->mm.interruptible = true;
1999         return 0;
2000
2001 err_unpin:
2002         i915_gem_object_unpin(obj);
2003 err_interruptible:
2004         dev_priv->mm.interruptible = true;
2005         return ret;
2006 }
2007
2008 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009 {
2010         i915_gem_object_unpin_fence(obj);
2011         i915_gem_object_unpin(obj);
2012 }
2013
2014 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015  * is assumed to be a power-of-two. */
2016 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017                                                unsigned int bpp,
2018                                                unsigned int pitch)
2019 {
2020         int tile_rows, tiles;
2021
2022         tile_rows = *y / 8;
2023         *y %= 8;
2024         tiles = *x / (512/bpp);
2025         *x %= 512/bpp;
2026
2027         return tile_rows * pitch * 8 + tiles * 4096;
2028 }
2029
2030 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031                              int x, int y)
2032 {
2033         struct drm_device *dev = crtc->dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036         struct intel_framebuffer *intel_fb;
2037         struct drm_i915_gem_object *obj;
2038         int plane = intel_crtc->plane;
2039         unsigned long linear_offset;
2040         u32 dspcntr;
2041         u32 reg;
2042
2043         switch (plane) {
2044         case 0:
2045         case 1:
2046                 break;
2047         default:
2048                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049                 return -EINVAL;
2050         }
2051
2052         intel_fb = to_intel_framebuffer(fb);
2053         obj = intel_fb->obj;
2054
2055         reg = DSPCNTR(plane);
2056         dspcntr = I915_READ(reg);
2057         /* Mask out pixel format bits in case we change it */
2058         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2059         switch (fb->pixel_format) {
2060         case DRM_FORMAT_C8:
2061                 dspcntr |= DISPPLANE_8BPP;
2062                 break;
2063         case DRM_FORMAT_XRGB1555:
2064         case DRM_FORMAT_ARGB1555:
2065                 dspcntr |= DISPPLANE_BGRX555;
2066                 break;
2067         case DRM_FORMAT_RGB565:
2068                 dspcntr |= DISPPLANE_BGRX565;
2069                 break;
2070         case DRM_FORMAT_XRGB8888:
2071         case DRM_FORMAT_ARGB8888:
2072                 dspcntr |= DISPPLANE_BGRX888;
2073                 break;
2074         case DRM_FORMAT_XBGR8888:
2075         case DRM_FORMAT_ABGR8888:
2076                 dspcntr |= DISPPLANE_RGBX888;
2077                 break;
2078         case DRM_FORMAT_XRGB2101010:
2079         case DRM_FORMAT_ARGB2101010:
2080                 dspcntr |= DISPPLANE_BGRX101010;
2081                 break;
2082         case DRM_FORMAT_XBGR2101010:
2083         case DRM_FORMAT_ABGR2101010:
2084                 dspcntr |= DISPPLANE_RGBX101010;
2085                 break;
2086         default:
2087                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2088                 return -EINVAL;
2089         }
2090
2091         if (INTEL_INFO(dev)->gen >= 4) {
2092                 if (obj->tiling_mode != I915_TILING_NONE)
2093                         dspcntr |= DISPPLANE_TILED;
2094                 else
2095                         dspcntr &= ~DISPPLANE_TILED;
2096         }
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_offset_xtiled(&x, &y,
2105                                                          fb->bits_per_pixel / 8,
2106                                                          fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2114         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2115         if (INTEL_INFO(dev)->gen >= 4) {
2116                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2118                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2119                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2120         } else
2121                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2122         POSTING_READ(reg);
2123
2124         return 0;
2125 }
2126
2127 static int ironlake_update_plane(struct drm_crtc *crtc,
2128                                  struct drm_framebuffer *fb, int x, int y)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         struct intel_framebuffer *intel_fb;
2134         struct drm_i915_gem_object *obj;
2135         int plane = intel_crtc->plane;
2136         unsigned long linear_offset;
2137         u32 dspcntr;
2138         u32 reg;
2139
2140         switch (plane) {
2141         case 0:
2142         case 1:
2143         case 2:
2144                 break;
2145         default:
2146                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147                 return -EINVAL;
2148         }
2149
2150         intel_fb = to_intel_framebuffer(fb);
2151         obj = intel_fb->obj;
2152
2153         reg = DSPCNTR(plane);
2154         dspcntr = I915_READ(reg);
2155         /* Mask out pixel format bits in case we change it */
2156         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2157         switch (fb->pixel_format) {
2158         case DRM_FORMAT_C8:
2159                 dspcntr |= DISPPLANE_8BPP;
2160                 break;
2161         case DRM_FORMAT_RGB565:
2162                 dspcntr |= DISPPLANE_BGRX565;
2163                 break;
2164         case DRM_FORMAT_XRGB8888:
2165         case DRM_FORMAT_ARGB8888:
2166                 dspcntr |= DISPPLANE_BGRX888;
2167                 break;
2168         case DRM_FORMAT_XBGR8888:
2169         case DRM_FORMAT_ABGR8888:
2170                 dspcntr |= DISPPLANE_RGBX888;
2171                 break;
2172         case DRM_FORMAT_XRGB2101010:
2173         case DRM_FORMAT_ARGB2101010:
2174                 dspcntr |= DISPPLANE_BGRX101010;
2175                 break;
2176         case DRM_FORMAT_XBGR2101010:
2177         case DRM_FORMAT_ABGR2101010:
2178                 dspcntr |= DISPPLANE_RGBX101010;
2179                 break;
2180         default:
2181                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2182                 return -EINVAL;
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         /* must disable */
2191         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193         I915_WRITE(reg, dspcntr);
2194
2195         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2196         intel_crtc->dspaddr_offset =
2197                 intel_gen4_compute_offset_xtiled(&x, &y,
2198                                                  fb->bits_per_pixel / 8,
2199                                                  fb->pitches[0]);
2200         linear_offset -= intel_crtc->dspaddr_offset;
2201
2202         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2204         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2205         I915_MODIFY_DISPBASE(DSPSURF(plane),
2206                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2207         if (IS_HASWELL(dev)) {
2208                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209         } else {
2210                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212         }
2213         POSTING_READ(reg);
2214
2215         return 0;
2216 }
2217
2218 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2219 static int
2220 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221                            int x, int y, enum mode_set_atomic state)
2222 {
2223         struct drm_device *dev = crtc->dev;
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225
2226         if (dev_priv->display.disable_fbc)
2227                 dev_priv->display.disable_fbc(dev);
2228         intel_increase_pllclock(crtc);
2229
2230         return dev_priv->display.update_plane(crtc, fb, x, y);
2231 }
2232
2233 static int
2234 intel_finish_fb(struct drm_framebuffer *old_fb)
2235 {
2236         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238         bool was_interruptible = dev_priv->mm.interruptible;
2239         int ret;
2240
2241         wait_event(dev_priv->pending_flip_queue,
2242                    atomic_read(&dev_priv->mm.wedged) ||
2243                    atomic_read(&obj->pending_flip) == 0);
2244
2245         /* Big Hammer, we also need to ensure that any pending
2246          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247          * current scanout is retired before unpinning the old
2248          * framebuffer.
2249          *
2250          * This should only fail upon a hung GPU, in which case we
2251          * can safely continue.
2252          */
2253         dev_priv->mm.interruptible = false;
2254         ret = i915_gem_object_finish_gpu(obj);
2255         dev_priv->mm.interruptible = was_interruptible;
2256
2257         return ret;
2258 }
2259
2260 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct drm_i915_master_private *master_priv;
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266         if (!dev->primary->master)
2267                 return;
2268
2269         master_priv = dev->primary->master->driver_priv;
2270         if (!master_priv->sarea_priv)
2271                 return;
2272
2273         switch (intel_crtc->pipe) {
2274         case 0:
2275                 master_priv->sarea_priv->pipeA_x = x;
2276                 master_priv->sarea_priv->pipeA_y = y;
2277                 break;
2278         case 1:
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281                 break;
2282         default:
2283                 break;
2284         }
2285 }
2286
2287 static int
2288 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2289                     struct drm_framebuffer *fb)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         struct drm_framebuffer *old_fb;
2295         int ret;
2296
2297         /* no fb bound */
2298         if (!fb) {
2299                 DRM_ERROR("No FB bound\n");
2300                 return 0;
2301         }
2302
2303         if(intel_crtc->plane > dev_priv->num_pipe) {
2304                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305                                 intel_crtc->plane,
2306                                 dev_priv->num_pipe);
2307                 return -EINVAL;
2308         }
2309
2310         mutex_lock(&dev->struct_mutex);
2311         ret = intel_pin_and_fence_fb_obj(dev,
2312                                          to_intel_framebuffer(fb)->obj,
2313                                          NULL);
2314         if (ret != 0) {
2315                 mutex_unlock(&dev->struct_mutex);
2316                 DRM_ERROR("pin & fence failed\n");
2317                 return ret;
2318         }
2319
2320         if (crtc->fb)
2321                 intel_finish_fb(crtc->fb);
2322
2323         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2324         if (ret) {
2325                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2326                 mutex_unlock(&dev->struct_mutex);
2327                 DRM_ERROR("failed to update base address\n");
2328                 return ret;
2329         }
2330
2331         old_fb = crtc->fb;
2332         crtc->fb = fb;
2333         crtc->x = x;
2334         crtc->y = y;
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         intel_update_fbc(dev);
2342         mutex_unlock(&dev->struct_mutex);
2343
2344         intel_crtc_update_sarea_pos(crtc, x, y);
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 static void ivb_modeset_global_resources(struct drm_device *dev)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *pipe_B_crtc =
2443                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444         struct intel_crtc *pipe_C_crtc =
2445                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446         uint32_t temp;
2447
2448         /* When everything is off disable fdi C so that we could enable fdi B
2449          * with all lanes. XXX: This misses the case where a pipe is not using
2450          * any pch resources and so doesn't need any fdi lanes. */
2451         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455                 temp = I915_READ(SOUTH_CHICKEN1);
2456                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458                 I915_WRITE(SOUTH_CHICKEN1, temp);
2459         }
2460 }
2461
2462 /* The FDI link training functions for ILK/Ibexpeak. */
2463 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468         int pipe = intel_crtc->pipe;
2469         int plane = intel_crtc->plane;
2470         u32 reg, temp, tries;
2471
2472         /* FDI needs bits from pipe & plane first */
2473         assert_pipe_enabled(dev_priv, pipe);
2474         assert_plane_enabled(dev_priv, plane);
2475
2476         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477            for train result */
2478         reg = FDI_RX_IMR(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_RX_SYMBOL_LOCK;
2481         temp &= ~FDI_RX_BIT_LOCK;
2482         I915_WRITE(reg, temp);
2483         I915_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         reg = FDI_RX_CTL(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_LINK_TRAIN_NONE;
2498         temp |= FDI_LINK_TRAIN_PATTERN_1;
2499         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         /* Ironlake workaround, enable clock pointer after FDI enable*/
2505         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2506         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507                    FDI_RX_PHASE_SYNC_POINTER_EN);
2508
2509         reg = FDI_RX_IIR(pipe);
2510         for (tries = 0; tries < 5; tries++) {
2511                 temp = I915_READ(reg);
2512                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514                 if ((temp & FDI_RX_BIT_LOCK)) {
2515                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2516                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2517                         break;
2518                 }
2519         }
2520         if (tries == 5)
2521                 DRM_ERROR("FDI train 1 fail!\n");
2522
2523         /* Train 2 */
2524         reg = FDI_TX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~FDI_LINK_TRAIN_NONE;
2527         temp |= FDI_LINK_TRAIN_PATTERN_2;
2528         I915_WRITE(reg, temp);
2529
2530         reg = FDI_RX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_LINK_TRAIN_NONE;
2533         temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         I915_WRITE(reg, temp);
2535
2536         POSTING_READ(reg);
2537         udelay(150);
2538
2539         reg = FDI_RX_IIR(pipe);
2540         for (tries = 0; tries < 5; tries++) {
2541                 temp = I915_READ(reg);
2542                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543
2544                 if (temp & FDI_RX_SYMBOL_LOCK) {
2545                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2546                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2547                         break;
2548                 }
2549         }
2550         if (tries == 5)
2551                 DRM_ERROR("FDI train 2 fail!\n");
2552
2553         DRM_DEBUG_KMS("FDI train done\n");
2554
2555 }
2556
2557 static const int snb_b_fdi_train_param[] = {
2558         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2559         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2560         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2561         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2562 };
2563
2564 /* The FDI link training functions for SNB/Cougarpoint. */
2565 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2566 {
2567         struct drm_device *dev = crtc->dev;
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570         int pipe = intel_crtc->pipe;
2571         u32 reg, temp, i, retry;
2572
2573         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2574            for train result */
2575         reg = FDI_RX_IMR(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_RX_SYMBOL_LOCK;
2578         temp &= ~FDI_RX_BIT_LOCK;
2579         I915_WRITE(reg, temp);
2580
2581         POSTING_READ(reg);
2582         udelay(150);
2583
2584         /* enable CPU FDI TX and PCH FDI RX */
2585         reg = FDI_TX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~(7 << 19);
2588         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_1;
2591         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592         /* SNB-B */
2593         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2594         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2595
2596         I915_WRITE(FDI_RX_MISC(pipe),
2597                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2598
2599         reg = FDI_RX_CTL(pipe);
2600         temp = I915_READ(reg);
2601         if (HAS_PCH_CPT(dev)) {
2602                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2603                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2604         } else {
2605                 temp &= ~FDI_LINK_TRAIN_NONE;
2606                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2607         }
2608         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2609
2610         POSTING_READ(reg);
2611         udelay(150);
2612
2613         cpt_phase_pointer_enable(dev, pipe);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_BIT_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 1 fail!\n");
2641
2642         /* Train 2 */
2643         reg = FDI_TX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2;
2647         if (IS_GEN6(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 /* SNB-B */
2650                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         reg = FDI_RX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         if (HAS_PCH_CPT(dev)) {
2657                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659         } else {
2660                 temp &= ~FDI_LINK_TRAIN_NONE;
2661                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662         }
2663         I915_WRITE(reg, temp);
2664
2665         POSTING_READ(reg);
2666         udelay(150);
2667
2668         for (i = 0; i < 4; i++) {
2669                 reg = FDI_TX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672                 temp |= snb_b_fdi_train_param[i];
2673                 I915_WRITE(reg, temp);
2674
2675                 POSTING_READ(reg);
2676                 udelay(500);
2677
2678                 for (retry = 0; retry < 5; retry++) {
2679                         reg = FDI_RX_IIR(pipe);
2680                         temp = I915_READ(reg);
2681                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682                         if (temp & FDI_RX_SYMBOL_LOCK) {
2683                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2684                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685                                 break;
2686                         }
2687                         udelay(50);
2688                 }
2689                 if (retry < 5)
2690                         break;
2691         }
2692         if (i == 4)
2693                 DRM_ERROR("FDI train 2 fail!\n");
2694
2695         DRM_DEBUG_KMS("FDI train done.\n");
2696 }
2697
2698 /* Manual link training for Ivy Bridge A0 parts */
2699 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2700 {
2701         struct drm_device *dev = crtc->dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704         int pipe = intel_crtc->pipe;
2705         u32 reg, temp, i;
2706
2707         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708            for train result */
2709         reg = FDI_RX_IMR(pipe);
2710         temp = I915_READ(reg);
2711         temp &= ~FDI_RX_SYMBOL_LOCK;
2712         temp &= ~FDI_RX_BIT_LOCK;
2713         I915_WRITE(reg, temp);
2714
2715         POSTING_READ(reg);
2716         udelay(150);
2717
2718         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719                       I915_READ(FDI_RX_IIR(pipe)));
2720
2721         /* enable CPU FDI TX and PCH FDI RX */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~(7 << 19);
2725         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2726         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2727         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2728         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2729         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2730         temp |= FDI_COMPOSITE_SYNC;
2731         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2732
2733         I915_WRITE(FDI_RX_MISC(pipe),
2734                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2735
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_LINK_TRAIN_AUTO;
2739         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2740         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2741         temp |= FDI_COMPOSITE_SYNC;
2742         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743
2744         POSTING_READ(reg);
2745         udelay(150);
2746
2747         cpt_phase_pointer_enable(dev, pipe);
2748
2749         for (i = 0; i < 4; i++) {
2750                 reg = FDI_TX_CTL(pipe);
2751                 temp = I915_READ(reg);
2752                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753                 temp |= snb_b_fdi_train_param[i];
2754                 I915_WRITE(reg, temp);
2755
2756                 POSTING_READ(reg);
2757                 udelay(500);
2758
2759                 reg = FDI_RX_IIR(pipe);
2760                 temp = I915_READ(reg);
2761                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2762
2763                 if (temp & FDI_RX_BIT_LOCK ||
2764                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2765                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2766                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2767                         break;
2768                 }
2769         }
2770         if (i == 4)
2771                 DRM_ERROR("FDI train 1 fail!\n");
2772
2773         /* Train 2 */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780         I915_WRITE(reg, temp);
2781
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2785         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2786         I915_WRITE(reg, temp);
2787
2788         POSTING_READ(reg);
2789         udelay(150);
2790
2791         for (i = 0; i < 4; i++) {
2792                 reg = FDI_TX_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795                 temp |= snb_b_fdi_train_param[i];
2796                 I915_WRITE(reg, temp);
2797
2798                 POSTING_READ(reg);
2799                 udelay(500);
2800
2801                 reg = FDI_RX_IIR(pipe);
2802                 temp = I915_READ(reg);
2803                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805                 if (temp & FDI_RX_SYMBOL_LOCK) {
2806                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2807                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2808                         break;
2809                 }
2810         }
2811         if (i == 4)
2812                 DRM_ERROR("FDI train 2 fail!\n");
2813
2814         DRM_DEBUG_KMS("FDI train done.\n");
2815 }
2816
2817 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2818 {
2819         struct drm_device *dev = intel_crtc->base.dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         int pipe = intel_crtc->pipe;
2822         u32 reg, temp;
2823
2824
2825         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         temp &= ~((0x7 << 19) | (0x7 << 16));
2829         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2830         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2832
2833         POSTING_READ(reg);
2834         udelay(200);
2835
2836         /* Switch from Rawclk to PCDclk */
2837         temp = I915_READ(reg);
2838         I915_WRITE(reg, temp | FDI_PCDCLK);
2839
2840         POSTING_READ(reg);
2841         udelay(200);
2842
2843         /* On Haswell, the PLL configuration for ports and pipes is handled
2844          * separately, as part of DDI setup */
2845         if (!IS_HASWELL(dev)) {
2846                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847                 reg = FDI_TX_CTL(pipe);
2848                 temp = I915_READ(reg);
2849                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2850                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2851
2852                         POSTING_READ(reg);
2853                         udelay(100);
2854                 }
2855         }
2856 }
2857
2858 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2859 {
2860         struct drm_device *dev = intel_crtc->base.dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         int pipe = intel_crtc->pipe;
2863         u32 reg, temp;
2864
2865         /* Switch from PCDclk to Rawclk */
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2869
2870         /* Disable CPU FDI TX PLL */
2871         reg = FDI_TX_CTL(pipe);
2872         temp = I915_READ(reg);
2873         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2874
2875         POSTING_READ(reg);
2876         udelay(100);
2877
2878         reg = FDI_RX_CTL(pipe);
2879         temp = I915_READ(reg);
2880         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2881
2882         /* Wait for the clocks to turn off. */
2883         POSTING_READ(reg);
2884         udelay(100);
2885 }
2886
2887 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2888 {
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890         u32 flags = I915_READ(SOUTH_CHICKEN1);
2891
2892         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2893         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2894         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2895         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2896         POSTING_READ(SOUTH_CHICKEN1);
2897 }
2898 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         u32 reg, temp;
2905
2906         /* disable CPU FDI tx and PCH FDI rx */
2907         reg = FDI_TX_CTL(pipe);
2908         temp = I915_READ(reg);
2909         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910         POSTING_READ(reg);
2911
2912         reg = FDI_RX_CTL(pipe);
2913         temp = I915_READ(reg);
2914         temp &= ~(0x7 << 16);
2915         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2916         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918         POSTING_READ(reg);
2919         udelay(100);
2920
2921         /* Ironlake workaround, disable clock pointer after downing FDI */
2922         if (HAS_PCH_IBX(dev)) {
2923                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2924         } else if (HAS_PCH_CPT(dev)) {
2925                 cpt_phase_pointer_disable(dev, pipe);
2926         }
2927
2928         /* still set train pattern 1 */
2929         reg = FDI_TX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_LINK_TRAIN_NONE;
2932         temp |= FDI_LINK_TRAIN_PATTERN_1;
2933         I915_WRITE(reg, temp);
2934
2935         reg = FDI_RX_CTL(pipe);
2936         temp = I915_READ(reg);
2937         if (HAS_PCH_CPT(dev)) {
2938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940         } else {
2941                 temp &= ~FDI_LINK_TRAIN_NONE;
2942                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943         }
2944         /* BPC in FDI rx is consistent with that in PIPECONF */
2945         temp &= ~(0x07 << 16);
2946         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947         I915_WRITE(reg, temp);
2948
2949         POSTING_READ(reg);
2950         udelay(100);
2951 }
2952
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954 {
2955         struct drm_device *dev = crtc->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         unsigned long flags;
2958         bool pending;
2959
2960         if (atomic_read(&dev_priv->mm.wedged))
2961                 return false;
2962
2963         spin_lock_irqsave(&dev->event_lock, flags);
2964         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965         spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967         return pending;
2968 }
2969
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974
2975         if (crtc->fb == NULL)
2976                 return;
2977
2978         wait_event(dev_priv->pending_flip_queue,
2979                    !intel_crtc_has_pending_flip(crtc));
2980
2981         mutex_lock(&dev->struct_mutex);
2982         intel_finish_fb(crtc->fb);
2983         mutex_unlock(&dev->struct_mutex);
2984 }
2985
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct intel_encoder *intel_encoder;
2990
2991         /*
2992          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993          * must be driven by its own crtc; no sharing is possible.
2994          */
2995         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2996                 switch (intel_encoder->type) {
2997                 case INTEL_OUTPUT_EDP:
2998                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2999                                 return false;
3000                         continue;
3001                 }
3002         }
3003
3004         return true;
3005 }
3006
3007 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008 {
3009         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010 }
3011
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc *crtc)
3014 {
3015         struct drm_device *dev = crtc->dev;
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018         u32 temp;
3019
3020         /* It is necessary to ungate the pixclk gate prior to programming
3021          * the divisors, and gate it back when it is done.
3022          */
3023         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025         /* Disable SSCCTL */
3026         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028                                         SBI_SSCCTL_DISABLE);
3029
3030         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031         if (crtc->mode.clock == 20000) {
3032                 auxdiv = 1;
3033                 divsel = 0x41;
3034                 phaseinc = 0x20;
3035         } else {
3036                 /* The iCLK virtual clock root frequency is in MHz,
3037                  * but the crtc->mode.clock in in KHz. To get the divisors,
3038                  * it is necessary to divide one by another, so we
3039                  * convert the virtual clock precision to KHz here for higher
3040                  * precision.
3041                  */
3042                 u32 iclk_virtual_root_freq = 172800 * 1000;
3043                 u32 iclk_pi_range = 64;
3044                 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047                 msb_divisor_value = desired_divisor / iclk_pi_range;
3048                 pi_value = desired_divisor % iclk_pi_range;
3049
3050                 auxdiv = 0;
3051                 divsel = msb_divisor_value - 2;
3052                 phaseinc = pi_value;
3053         }
3054
3055         /* This should not happen with any sane values */
3056         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062                         crtc->mode.clock,
3063                         auxdiv,
3064                         divsel,
3065                         phasedir,
3066                         phaseinc);
3067
3068         /* Program SSCDIVINTPHASE6 */
3069         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077         intel_sbi_write(dev_priv,
3078                         SBI_SSCDIVINTPHASE6,
3079                         temp);
3080
3081         /* Program SSCAUXDIV */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085         intel_sbi_write(dev_priv,
3086                         SBI_SSCAUXDIV6,
3087                         temp);
3088
3089
3090         /* Enable modulator and associated divider */
3091         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092         temp &= ~SBI_SSCCTL_DISABLE;
3093         intel_sbi_write(dev_priv,
3094                         SBI_SSCCTL6,
3095                         temp);
3096
3097         /* Wait for initialization time */
3098         udelay(24);
3099
3100         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101 }
3102
3103 /*
3104  * Enable PCH resources required for PCH ports:
3105  *   - PCH PLLs
3106  *   - FDI training & RX/TX
3107  *   - update transcoder timings
3108  *   - DP transcoding bits
3109  *   - transcoder
3110  */
3111 static void ironlake_pch_enable(struct drm_crtc *crtc)
3112 {
3113         struct drm_device *dev = crtc->dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116         int pipe = intel_crtc->pipe;
3117         u32 reg, temp;
3118
3119         assert_transcoder_disabled(dev_priv, pipe);
3120
3121         /* Write the TU size bits before fdi link training, so that error
3122          * detection works. */
3123         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
3126         /* For PCH output, training FDI link */
3127         dev_priv->display.fdi_link_train(crtc);
3128
3129         /* XXX: pch pll's can be enabled any time before we enable the PCH
3130          * transcoder, and we actually should do this to not upset any PCH
3131          * transcoder that already use the clock when we share it.
3132          *
3133          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134          * unconditionally resets the pll - we need that to have the right LVDS
3135          * enable sequence. */
3136         ironlake_enable_pch_pll(intel_crtc);
3137
3138         if (HAS_PCH_CPT(dev)) {
3139                 u32 sel;
3140
3141                 temp = I915_READ(PCH_DPLL_SEL);
3142                 switch (pipe) {
3143                 default:
3144                 case 0:
3145                         temp |= TRANSA_DPLL_ENABLE;
3146                         sel = TRANSA_DPLLB_SEL;
3147                         break;
3148                 case 1:
3149                         temp |= TRANSB_DPLL_ENABLE;
3150                         sel = TRANSB_DPLLB_SEL;
3151                         break;
3152                 case 2:
3153                         temp |= TRANSC_DPLL_ENABLE;
3154                         sel = TRANSC_DPLLB_SEL;
3155                         break;
3156                 }
3157                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158                         temp |= sel;
3159                 else
3160                         temp &= ~sel;
3161                 I915_WRITE(PCH_DPLL_SEL, temp);
3162         }
3163
3164         /* set transcoder timing, panel must allow it */
3165         assert_panel_unlocked(dev_priv, pipe);
3166         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3169
3170         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3173         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3174
3175         intel_fdi_normal_train(crtc);
3176
3177         /* For PCH DP, enable TRANS_DP_CTL */
3178         if (HAS_PCH_CPT(dev) &&
3179             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3181                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3185                           TRANS_DP_SYNC_MASK |
3186                           TRANS_DP_BPC_MASK);
3187                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188                          TRANS_DP_ENH_FRAMING);
3189                 temp |= bpc << 9; /* same format but at 11:9 */
3190
3191                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3192                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3193                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3194                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3195
3196                 switch (intel_trans_dp_port_sel(crtc)) {
3197                 case PCH_DP_B:
3198                         temp |= TRANS_DP_PORT_SEL_B;
3199                         break;
3200                 case PCH_DP_C:
3201                         temp |= TRANS_DP_PORT_SEL_C;
3202                         break;
3203                 case PCH_DP_D:
3204                         temp |= TRANS_DP_PORT_SEL_D;
3205                         break;
3206                 default:
3207                         BUG();
3208                 }
3209
3210                 I915_WRITE(reg, temp);
3211         }
3212
3213         ironlake_enable_pch_transcoder(dev_priv, pipe);
3214 }
3215
3216 static void lpt_pch_enable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3222
3223         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3224
3225         lpt_program_iclkip(crtc);
3226
3227         /* Set transcoder timing. */
3228         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3231
3232         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3236
3237         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3238 }
3239
3240 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241 {
3242         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244         if (pll == NULL)
3245                 return;
3246
3247         if (pll->refcount == 0) {
3248                 WARN(1, "bad PCH PLL refcount\n");
3249                 return;
3250         }
3251
3252         --pll->refcount;
3253         intel_crtc->pch_pll = NULL;
3254 }
3255
3256 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257 {
3258         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259         struct intel_pch_pll *pll;
3260         int i;
3261
3262         pll = intel_crtc->pch_pll;
3263         if (pll) {
3264                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265                               intel_crtc->base.base.id, pll->pll_reg);
3266                 goto prepare;
3267         }
3268
3269         if (HAS_PCH_IBX(dev_priv->dev)) {
3270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271                 i = intel_crtc->pipe;
3272                 pll = &dev_priv->pch_plls[i];
3273
3274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275                               intel_crtc->base.base.id, pll->pll_reg);
3276
3277                 goto found;
3278         }
3279
3280         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 /* Only want to check enabled timings first */
3284                 if (pll->refcount == 0)
3285                         continue;
3286
3287                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288                     fp == I915_READ(pll->fp0_reg)) {
3289                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290                                       intel_crtc->base.base.id,
3291                                       pll->pll_reg, pll->refcount, pll->active);
3292
3293                         goto found;
3294                 }
3295         }
3296
3297         /* Ok no matching timings, maybe there's a free one? */
3298         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299                 pll = &dev_priv->pch_plls[i];
3300                 if (pll->refcount == 0) {
3301                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302                                       intel_crtc->base.base.id, pll->pll_reg);
3303                         goto found;
3304                 }
3305         }
3306
3307         return NULL;
3308
3309 found:
3310         intel_crtc->pch_pll = pll;
3311         pll->refcount++;
3312         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313 prepare: /* separate function? */
3314         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3315
3316         /* Wait for the clocks to stabilize before rewriting the regs */
3317         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3318         POSTING_READ(pll->pll_reg);
3319         udelay(150);
3320
3321         I915_WRITE(pll->fp0_reg, fp);
3322         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3323         pll->on = false;
3324         return pll;
3325 }
3326
3327 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 if (wait_for(I915_READ(dslreg) != temp, 5))
3337                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338         }
3339 }
3340
3341 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         struct intel_encoder *encoder;
3347         int pipe = intel_crtc->pipe;
3348         int plane = intel_crtc->plane;
3349         u32 temp;
3350         bool is_pch_port;
3351
3352         WARN_ON(!crtc->enabled);
3353
3354         if (intel_crtc->active)
3355                 return;
3356
3357         intel_crtc->active = true;
3358         intel_update_watermarks(dev);
3359
3360         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3361                 temp = I915_READ(PCH_LVDS);
3362                 if ((temp & LVDS_PORT_EN) == 0)
3363                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3364         }
3365
3366         is_pch_port = ironlake_crtc_driving_pch(crtc);
3367
3368         if (is_pch_port) {
3369                 /* Note: FDI PLL enabling _must_ be done before we enable the
3370                  * cpu pipes, hence this is separate from all the other fdi/pch
3371                  * enabling. */
3372                 ironlake_fdi_pll_enable(intel_crtc);
3373         } else {
3374                 assert_fdi_tx_disabled(dev_priv, pipe);
3375                 assert_fdi_rx_disabled(dev_priv, pipe);
3376         }
3377
3378         for_each_encoder_on_crtc(dev, crtc, encoder)
3379                 if (encoder->pre_enable)
3380                         encoder->pre_enable(encoder);
3381
3382         /* Enable panel fitting for LVDS */
3383         if (dev_priv->pch_pf_size &&
3384             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3385              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3386                 /* Force use of hard-coded filter coefficients
3387                  * as some pre-programmed values are broken,
3388                  * e.g. x201.
3389                  */
3390                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3391                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3392                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3393         }
3394
3395         /*
3396          * On ILK+ LUT must be loaded before the pipe is running but with
3397          * clocks enabled
3398          */
3399         intel_crtc_load_lut(crtc);
3400
3401         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3402         intel_enable_plane(dev_priv, plane, pipe);
3403
3404         if (is_pch_port)
3405                 ironlake_pch_enable(crtc);
3406
3407         mutex_lock(&dev->struct_mutex);
3408         intel_update_fbc(dev);
3409         mutex_unlock(&dev->struct_mutex);
3410
3411         intel_crtc_update_cursor(crtc, true);
3412
3413         for_each_encoder_on_crtc(dev, crtc, encoder)
3414                 encoder->enable(encoder);
3415
3416         if (HAS_PCH_CPT(dev))
3417                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3418
3419         /*
3420          * There seems to be a race in PCH platform hw (at least on some
3421          * outputs) where an enabled pipe still completes any pageflip right
3422          * away (as if the pipe is off) instead of waiting for vblank. As soon
3423          * as the first vblank happend, everything works as expected. Hence just
3424          * wait for one vblank before returning to avoid strange things
3425          * happening.
3426          */
3427         intel_wait_for_vblank(dev, intel_crtc->pipe);
3428 }
3429
3430 static void haswell_crtc_enable(struct drm_crtc *crtc)
3431 {
3432         struct drm_device *dev = crtc->dev;
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3435         struct intel_encoder *encoder;
3436         int pipe = intel_crtc->pipe;
3437         int plane = intel_crtc->plane;
3438         bool is_pch_port;
3439
3440         WARN_ON(!crtc->enabled);
3441
3442         if (intel_crtc->active)
3443                 return;
3444
3445         intel_crtc->active = true;
3446         intel_update_watermarks(dev);
3447
3448         is_pch_port = haswell_crtc_driving_pch(crtc);
3449
3450         if (is_pch_port)
3451                 dev_priv->display.fdi_link_train(crtc);
3452
3453         for_each_encoder_on_crtc(dev, crtc, encoder)
3454                 if (encoder->pre_enable)
3455                         encoder->pre_enable(encoder);
3456
3457         intel_ddi_enable_pipe_clock(intel_crtc);
3458
3459         /* Enable panel fitting for eDP */
3460         if (dev_priv->pch_pf_size &&
3461             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3462                 /* Force use of hard-coded filter coefficients
3463                  * as some pre-programmed values are broken,
3464                  * e.g. x201.
3465                  */
3466                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3467                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3468                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3469         }
3470
3471         /*
3472          * On ILK+ LUT must be loaded before the pipe is running but with
3473          * clocks enabled
3474          */
3475         intel_crtc_load_lut(crtc);
3476
3477         intel_ddi_set_pipe_settings(crtc);
3478         intel_ddi_enable_pipe_func(crtc);
3479
3480         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3481         intel_enable_plane(dev_priv, plane, pipe);
3482
3483         if (is_pch_port)
3484                 lpt_pch_enable(crtc);
3485
3486         mutex_lock(&dev->struct_mutex);
3487         intel_update_fbc(dev);
3488         mutex_unlock(&dev->struct_mutex);
3489
3490         intel_crtc_update_cursor(crtc, true);
3491
3492         for_each_encoder_on_crtc(dev, crtc, encoder)
3493                 encoder->enable(encoder);
3494
3495         /*
3496          * There seems to be a race in PCH platform hw (at least on some
3497          * outputs) where an enabled pipe still completes any pageflip right
3498          * away (as if the pipe is off) instead of waiting for vblank. As soon
3499          * as the first vblank happend, everything works as expected. Hence just
3500          * wait for one vblank before returning to avoid strange things
3501          * happening.
3502          */
3503         intel_wait_for_vblank(dev, intel_crtc->pipe);
3504 }
3505
3506 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         struct intel_encoder *encoder;
3512         int pipe = intel_crtc->pipe;
3513         int plane = intel_crtc->plane;
3514         u32 reg, temp;
3515
3516
3517         if (!intel_crtc->active)
3518                 return;
3519
3520         for_each_encoder_on_crtc(dev, crtc, encoder)
3521                 encoder->disable(encoder);
3522
3523         intel_crtc_wait_for_pending_flips(crtc);
3524         drm_vblank_off(dev, pipe);
3525         intel_crtc_update_cursor(crtc, false);
3526
3527         intel_disable_plane(dev_priv, plane, pipe);
3528
3529         if (dev_priv->cfb_plane == plane)
3530                 intel_disable_fbc(dev);
3531
3532         intel_disable_pipe(dev_priv, pipe);
3533
3534         /* Disable PF */
3535         I915_WRITE(PF_CTL(pipe), 0);
3536         I915_WRITE(PF_WIN_SZ(pipe), 0);
3537
3538         for_each_encoder_on_crtc(dev, crtc, encoder)
3539                 if (encoder->post_disable)
3540                         encoder->post_disable(encoder);
3541
3542         ironlake_fdi_disable(crtc);
3543
3544         ironlake_disable_pch_transcoder(dev_priv, pipe);
3545
3546         if (HAS_PCH_CPT(dev)) {
3547                 /* disable TRANS_DP_CTL */
3548                 reg = TRANS_DP_CTL(pipe);
3549                 temp = I915_READ(reg);
3550                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3551                 temp |= TRANS_DP_PORT_SEL_NONE;
3552                 I915_WRITE(reg, temp);
3553
3554                 /* disable DPLL_SEL */
3555                 temp = I915_READ(PCH_DPLL_SEL);
3556                 switch (pipe) {
3557                 case 0:
3558                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3559                         break;
3560                 case 1:
3561                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3562                         break;
3563                 case 2:
3564                         /* C shares PLL A or B */
3565                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3566                         break;
3567                 default:
3568                         BUG(); /* wtf */
3569                 }
3570                 I915_WRITE(PCH_DPLL_SEL, temp);
3571         }
3572
3573         /* disable PCH DPLL */
3574         intel_disable_pch_pll(intel_crtc);
3575
3576         ironlake_fdi_pll_disable(intel_crtc);
3577
3578         intel_crtc->active = false;
3579         intel_update_watermarks(dev);
3580
3581         mutex_lock(&dev->struct_mutex);
3582         intel_update_fbc(dev);
3583         mutex_unlock(&dev->struct_mutex);
3584 }
3585
3586 static void haswell_crtc_disable(struct drm_crtc *crtc)
3587 {
3588         struct drm_device *dev = crtc->dev;
3589         struct drm_i915_private *dev_priv = dev->dev_private;
3590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3591         struct intel_encoder *encoder;
3592         int pipe = intel_crtc->pipe;
3593         int plane = intel_crtc->plane;
3594         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3595         bool is_pch_port;
3596
3597         if (!intel_crtc->active)
3598                 return;
3599
3600         is_pch_port = haswell_crtc_driving_pch(crtc);
3601
3602         for_each_encoder_on_crtc(dev, crtc, encoder)
3603                 encoder->disable(encoder);
3604
3605         intel_crtc_wait_for_pending_flips(crtc);
3606         drm_vblank_off(dev, pipe);
3607         intel_crtc_update_cursor(crtc, false);
3608
3609         intel_disable_plane(dev_priv, plane, pipe);
3610
3611         if (dev_priv->cfb_plane == plane)
3612                 intel_disable_fbc(dev);
3613
3614         intel_disable_pipe(dev_priv, pipe);
3615
3616         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3617
3618         /* Disable PF */
3619         I915_WRITE(PF_CTL(pipe), 0);
3620         I915_WRITE(PF_WIN_SZ(pipe), 0);
3621
3622         intel_ddi_disable_pipe_clock(intel_crtc);
3623
3624         for_each_encoder_on_crtc(dev, crtc, encoder)
3625                 if (encoder->post_disable)
3626                         encoder->post_disable(encoder);
3627
3628         if (is_pch_port) {
3629                 lpt_disable_pch_transcoder(dev_priv);
3630                 intel_ddi_fdi_disable(crtc);
3631         }
3632
3633         intel_crtc->active = false;
3634         intel_update_watermarks(dev);
3635
3636         mutex_lock(&dev->struct_mutex);
3637         intel_update_fbc(dev);
3638         mutex_unlock(&dev->struct_mutex);
3639 }
3640
3641 static void ironlake_crtc_off(struct drm_crtc *crtc)
3642 {
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         intel_put_pch_pll(intel_crtc);
3645 }
3646
3647 static void haswell_crtc_off(struct drm_crtc *crtc)
3648 {
3649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650
3651         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3652          * start using it. */
3653         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3654
3655         intel_ddi_put_crtc_pll(crtc);
3656 }
3657
3658 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3659 {
3660         if (!enable && intel_crtc->overlay) {
3661                 struct drm_device *dev = intel_crtc->base.dev;
3662                 struct drm_i915_private *dev_priv = dev->dev_private;
3663
3664                 mutex_lock(&dev->struct_mutex);
3665                 dev_priv->mm.interruptible = false;
3666                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3667                 dev_priv->mm.interruptible = true;
3668                 mutex_unlock(&dev->struct_mutex);
3669         }
3670
3671         /* Let userspace switch the overlay on again. In most cases userspace
3672          * has to recompute where to put it anyway.
3673          */
3674 }
3675
3676 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3677 {
3678         struct drm_device *dev = crtc->dev;
3679         struct drm_i915_private *dev_priv = dev->dev_private;
3680         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3681         struct intel_encoder *encoder;
3682         int pipe = intel_crtc->pipe;
3683         int plane = intel_crtc->plane;
3684
3685         WARN_ON(!crtc->enabled);
3686
3687         if (intel_crtc->active)
3688                 return;
3689
3690         intel_crtc->active = true;
3691         intel_update_watermarks(dev);
3692
3693         intel_enable_pll(dev_priv, pipe);
3694         intel_enable_pipe(dev_priv, pipe, false);
3695         intel_enable_plane(dev_priv, plane, pipe);
3696
3697         intel_crtc_load_lut(crtc);
3698         intel_update_fbc(dev);
3699
3700         /* Give the overlay scaler a chance to enable if it's on this pipe */
3701         intel_crtc_dpms_overlay(intel_crtc, true);
3702         intel_crtc_update_cursor(crtc, true);
3703
3704         for_each_encoder_on_crtc(dev, crtc, encoder)
3705                 encoder->enable(encoder);
3706 }
3707
3708 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3709 {
3710         struct drm_device *dev = crtc->dev;
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3713         struct intel_encoder *encoder;
3714         int pipe = intel_crtc->pipe;
3715         int plane = intel_crtc->plane;
3716
3717
3718         if (!intel_crtc->active)
3719                 return;
3720
3721         for_each_encoder_on_crtc(dev, crtc, encoder)
3722                 encoder->disable(encoder);
3723
3724         /* Give the overlay scaler a chance to disable if it's on this pipe */
3725         intel_crtc_wait_for_pending_flips(crtc);
3726         drm_vblank_off(dev, pipe);
3727         intel_crtc_dpms_overlay(intel_crtc, false);
3728         intel_crtc_update_cursor(crtc, false);
3729
3730         if (dev_priv->cfb_plane == plane)
3731                 intel_disable_fbc(dev);
3732
3733         intel_disable_plane(dev_priv, plane, pipe);
3734         intel_disable_pipe(dev_priv, pipe);
3735         intel_disable_pll(dev_priv, pipe);
3736
3737         intel_crtc->active = false;
3738         intel_update_fbc(dev);
3739         intel_update_watermarks(dev);
3740 }
3741
3742 static void i9xx_crtc_off(struct drm_crtc *crtc)
3743 {
3744 }
3745
3746 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3747                                     bool enabled)
3748 {
3749         struct drm_device *dev = crtc->dev;
3750         struct drm_i915_master_private *master_priv;
3751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752         int pipe = intel_crtc->pipe;
3753
3754         if (!dev->primary->master)
3755                 return;
3756
3757         master_priv = dev->primary->master->driver_priv;
3758         if (!master_priv->sarea_priv)
3759                 return;
3760
3761         switch (pipe) {
3762         case 0:
3763                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3764                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3765                 break;
3766         case 1:
3767                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3768                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3769                 break;
3770         default:
3771                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3772                 break;
3773         }
3774 }
3775
3776 /**
3777  * Sets the power management mode of the pipe and plane.
3778  */
3779 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_encoder *intel_encoder;
3784         bool enable = false;
3785
3786         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3787                 enable |= intel_encoder->connectors_active;
3788
3789         if (enable)
3790                 dev_priv->display.crtc_enable(crtc);
3791         else
3792                 dev_priv->display.crtc_disable(crtc);
3793
3794         intel_crtc_update_sarea(crtc, enable);
3795 }
3796
3797 static void intel_crtc_noop(struct drm_crtc *crtc)
3798 {
3799 }
3800
3801 static void intel_crtc_disable(struct drm_crtc *crtc)
3802 {
3803         struct drm_device *dev = crtc->dev;
3804         struct drm_connector *connector;
3805         struct drm_i915_private *dev_priv = dev->dev_private;
3806
3807         /* crtc should still be enabled when we disable it. */
3808         WARN_ON(!crtc->enabled);
3809
3810         dev_priv->display.crtc_disable(crtc);
3811         intel_crtc_update_sarea(crtc, false);
3812         dev_priv->display.off(crtc);
3813
3814         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3815         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3816
3817         if (crtc->fb) {
3818                 mutex_lock(&dev->struct_mutex);
3819                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3820                 mutex_unlock(&dev->struct_mutex);
3821                 crtc->fb = NULL;
3822         }
3823
3824         /* Update computed state. */
3825         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3826                 if (!connector->encoder || !connector->encoder->crtc)
3827                         continue;
3828
3829                 if (connector->encoder->crtc != crtc)
3830                         continue;
3831
3832                 connector->dpms = DRM_MODE_DPMS_OFF;
3833                 to_intel_encoder(connector->encoder)->connectors_active = false;
3834         }
3835 }
3836
3837 void intel_modeset_disable(struct drm_device *dev)
3838 {
3839         struct drm_crtc *crtc;
3840
3841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3842                 if (crtc->enabled)
3843                         intel_crtc_disable(crtc);
3844         }
3845 }
3846
3847 void intel_encoder_noop(struct drm_encoder *encoder)
3848 {
3849 }
3850
3851 void intel_encoder_destroy(struct drm_encoder *encoder)
3852 {
3853         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3854
3855         drm_encoder_cleanup(encoder);
3856         kfree(intel_encoder);
3857 }
3858
3859 /* Simple dpms helper for encodres with just one connector, no cloning and only
3860  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3861  * state of the entire output pipe. */
3862 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3863 {
3864         if (mode == DRM_MODE_DPMS_ON) {
3865                 encoder->connectors_active = true;
3866
3867                 intel_crtc_update_dpms(encoder->base.crtc);
3868         } else {
3869                 encoder->connectors_active = false;
3870
3871                 intel_crtc_update_dpms(encoder->base.crtc);
3872         }
3873 }
3874
3875 /* Cross check the actual hw state with our own modeset state tracking (and it's
3876  * internal consistency). */
3877 static void intel_connector_check_state(struct intel_connector *connector)
3878 {
3879         if (connector->get_hw_state(connector)) {
3880                 struct intel_encoder *encoder = connector->encoder;
3881                 struct drm_crtc *crtc;
3882                 bool encoder_enabled;
3883                 enum pipe pipe;
3884
3885                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3886                               connector->base.base.id,
3887                               drm_get_connector_name(&connector->base));
3888
3889                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3890                      "wrong connector dpms state\n");
3891                 WARN(connector->base.encoder != &encoder->base,
3892                      "active connector not linked to encoder\n");
3893                 WARN(!encoder->connectors_active,
3894                      "encoder->connectors_active not set\n");
3895
3896                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3897                 WARN(!encoder_enabled, "encoder not enabled\n");
3898                 if (WARN_ON(!encoder->base.crtc))
3899                         return;
3900
3901                 crtc = encoder->base.crtc;
3902
3903                 WARN(!crtc->enabled, "crtc not enabled\n");
3904                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3905                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3906                      "encoder active on the wrong pipe\n");
3907         }
3908 }
3909
3910 /* Even simpler default implementation, if there's really no special case to
3911  * consider. */
3912 void intel_connector_dpms(struct drm_connector *connector, int mode)
3913 {
3914         struct intel_encoder *encoder = intel_attached_encoder(connector);
3915
3916         /* All the simple cases only support two dpms states. */
3917         if (mode != DRM_MODE_DPMS_ON)
3918                 mode = DRM_MODE_DPMS_OFF;
3919
3920         if (mode == connector->dpms)
3921                 return;
3922
3923         connector->dpms = mode;
3924
3925         /* Only need to change hw state when actually enabled */
3926         if (encoder->base.crtc)
3927                 intel_encoder_dpms(encoder, mode);
3928         else
3929                 WARN_ON(encoder->connectors_active != false);
3930
3931         intel_modeset_check_state(connector->dev);
3932 }
3933
3934 /* Simple connector->get_hw_state implementation for encoders that support only
3935  * one connector and no cloning and hence the encoder state determines the state
3936  * of the connector. */
3937 bool intel_connector_get_hw_state(struct intel_connector *connector)
3938 {
3939         enum pipe pipe = 0;
3940         struct intel_encoder *encoder = connector->encoder;
3941
3942         return encoder->get_hw_state(encoder, &pipe);
3943 }
3944
3945 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3946                                   const struct drm_display_mode *mode,
3947                                   struct drm_display_mode *adjusted_mode)
3948 {
3949         struct drm_device *dev = crtc->dev;
3950
3951         if (HAS_PCH_SPLIT(dev)) {
3952                 /* FDI link clock is fixed at 2.7G */
3953                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3954                         return false;
3955         }
3956
3957         /* All interlaced capable intel hw wants timings in frames. Note though
3958          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3959          * timings, so we need to be careful not to clobber these.*/
3960         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3961                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3962
3963         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3964          * with a hsync front porch of 0.
3965          */
3966         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3967                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3968                 return false;
3969
3970         return true;
3971 }
3972
3973 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3974 {
3975         return 400000; /* FIXME */
3976 }
3977
3978 static int i945_get_display_clock_speed(struct drm_device *dev)
3979 {
3980         return 400000;
3981 }
3982
3983 static int i915_get_display_clock_speed(struct drm_device *dev)
3984 {
3985         return 333000;
3986 }
3987
3988 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3989 {
3990         return 200000;
3991 }
3992
3993 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3994 {
3995         u16 gcfgc = 0;
3996
3997         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3998
3999         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4000                 return 133000;
4001         else {
4002                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4003                 case GC_DISPLAY_CLOCK_333_MHZ:
4004                         return 333000;
4005                 default:
4006                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4007                         return 190000;
4008                 }
4009         }
4010 }
4011
4012 static int i865_get_display_clock_speed(struct drm_device *dev)
4013 {
4014         return 266000;
4015 }
4016
4017 static int i855_get_display_clock_speed(struct drm_device *dev)
4018 {
4019         u16 hpllcc = 0;
4020         /* Assume that the hardware is in the high speed state.  This
4021          * should be the default.
4022          */
4023         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4024         case GC_CLOCK_133_200:
4025         case GC_CLOCK_100_200:
4026                 return 200000;
4027         case GC_CLOCK_166_250:
4028                 return 250000;
4029         case GC_CLOCK_100_133:
4030                 return 133000;
4031         }
4032
4033         /* Shouldn't happen */
4034         return 0;
4035 }
4036
4037 static int i830_get_display_clock_speed(struct drm_device *dev)
4038 {
4039         return 133000;
4040 }
4041
4042 struct fdi_m_n {
4043         u32        tu;
4044         u32        gmch_m;
4045         u32        gmch_n;
4046         u32        link_m;
4047         u32        link_n;
4048 };
4049
4050 static void
4051 fdi_reduce_ratio(u32 *num, u32 *den)
4052 {
4053         while (*num > 0xffffff || *den > 0xffffff) {
4054                 *num >>= 1;
4055                 *den >>= 1;
4056         }
4057 }
4058
4059 static void
4060 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4061                      int link_clock, struct fdi_m_n *m_n)
4062 {
4063         m_n->tu = 64; /* default size */
4064
4065         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4066         m_n->gmch_m = bits_per_pixel * pixel_clock;
4067         m_n->gmch_n = link_clock * nlanes * 8;
4068         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4069
4070         m_n->link_m = pixel_clock;
4071         m_n->link_n = link_clock;
4072         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4073 }
4074
4075 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4076 {
4077         if (i915_panel_use_ssc >= 0)
4078                 return i915_panel_use_ssc != 0;
4079         return dev_priv->lvds_use_ssc
4080                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4081 }
4082
4083 /**
4084  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4085  * @crtc: CRTC structure
4086  * @mode: requested mode
4087  *
4088  * A pipe may be connected to one or more outputs.  Based on the depth of the
4089  * attached framebuffer, choose a good color depth to use on the pipe.
4090  *
4091  * If possible, match the pipe depth to the fb depth.  In some cases, this
4092  * isn't ideal, because the connected output supports a lesser or restricted
4093  * set of depths.  Resolve that here:
4094  *    LVDS typically supports only 6bpc, so clamp down in that case
4095  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4096  *    Displays may support a restricted set as well, check EDID and clamp as
4097  *      appropriate.
4098  *    DP may want to dither down to 6bpc to fit larger modes
4099  *
4100  * RETURNS:
4101  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4102  * true if they don't match).
4103  */
4104 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4105                                          struct drm_framebuffer *fb,
4106                                          unsigned int *pipe_bpp,
4107                                          struct drm_display_mode *mode)
4108 {
4109         struct drm_device *dev = crtc->dev;
4110         struct drm_i915_private *dev_priv = dev->dev_private;
4111         struct drm_connector *connector;
4112         struct intel_encoder *intel_encoder;
4113         unsigned int display_bpc = UINT_MAX, bpc;
4114
4115         /* Walk the encoders & connectors on this crtc, get min bpc */
4116         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4117
4118                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4119                         unsigned int lvds_bpc;
4120
4121                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4122                             LVDS_A3_POWER_UP)
4123                                 lvds_bpc = 8;
4124                         else
4125                                 lvds_bpc = 6;
4126
4127                         if (lvds_bpc < display_bpc) {
4128                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4129                                 display_bpc = lvds_bpc;
4130                         }
4131                         continue;
4132                 }
4133
4134                 /* Not one of the known troublemakers, check the EDID */
4135                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4136                                     head) {
4137                         if (connector->encoder != &intel_encoder->base)
4138                                 continue;
4139
4140                         /* Don't use an invalid EDID bpc value */
4141                         if (connector->display_info.bpc &&
4142                             connector->display_info.bpc < display_bpc) {
4143                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4144                                 display_bpc = connector->display_info.bpc;
4145                         }
4146                 }
4147
4148                 /*
4149                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4150                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4151                  */
4152                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4153                         if (display_bpc > 8 && display_bpc < 12) {
4154                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4155                                 display_bpc = 12;
4156                         } else {
4157                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4158                                 display_bpc = 8;
4159                         }
4160                 }
4161         }
4162
4163         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4164                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4165                 display_bpc = 6;
4166         }
4167
4168         /*
4169          * We could just drive the pipe at the highest bpc all the time and
4170          * enable dithering as needed, but that costs bandwidth.  So choose
4171          * the minimum value that expresses the full color range of the fb but
4172          * also stays within the max display bpc discovered above.
4173          */
4174
4175         switch (fb->depth) {
4176         case 8:
4177                 bpc = 8; /* since we go through a colormap */
4178                 break;
4179         case 15:
4180         case 16:
4181                 bpc = 6; /* min is 18bpp */
4182                 break;
4183         case 24:
4184                 bpc = 8;
4185                 break;
4186         case 30:
4187                 bpc = 10;
4188                 break;
4189         case 48:
4190                 bpc = 12;
4191                 break;
4192         default:
4193                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4194                 bpc = min((unsigned int)8, display_bpc);
4195                 break;
4196         }
4197
4198         display_bpc = min(display_bpc, bpc);
4199
4200         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4201                       bpc, display_bpc);
4202
4203         *pipe_bpp = display_bpc * 3;
4204
4205         return display_bpc != bpc;
4206 }
4207
4208 static int vlv_get_refclk(struct drm_crtc *crtc)
4209 {
4210         struct drm_device *dev = crtc->dev;
4211         struct drm_i915_private *dev_priv = dev->dev_private;
4212         int refclk = 27000; /* for DP & HDMI */
4213
4214         return 100000; /* only one validated so far */
4215
4216         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4217                 refclk = 96000;
4218         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4219                 if (intel_panel_use_ssc(dev_priv))
4220                         refclk = 100000;
4221                 else
4222                         refclk = 96000;
4223         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4224                 refclk = 100000;
4225         }
4226
4227         return refclk;
4228 }
4229
4230 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4231 {
4232         struct drm_device *dev = crtc->dev;
4233         struct drm_i915_private *dev_priv = dev->dev_private;
4234         int refclk;
4235
4236         if (IS_VALLEYVIEW(dev)) {
4237                 refclk = vlv_get_refclk(crtc);
4238         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4239             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4240                 refclk = dev_priv->lvds_ssc_freq * 1000;
4241                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4242                               refclk / 1000);
4243         } else if (!IS_GEN2(dev)) {
4244                 refclk = 96000;
4245         } else {
4246                 refclk = 48000;
4247         }
4248
4249         return refclk;
4250 }
4251
4252 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4253                                       intel_clock_t *clock)
4254 {
4255         /* SDVO TV has fixed PLL values depend on its clock range,
4256            this mirrors vbios setting. */
4257         if (adjusted_mode->clock >= 100000
4258             && adjusted_mode->clock < 140500) {
4259                 clock->p1 = 2;
4260                 clock->p2 = 10;
4261                 clock->n = 3;
4262                 clock->m1 = 16;
4263                 clock->m2 = 8;
4264         } else if (adjusted_mode->clock >= 140500
4265                    && adjusted_mode->clock <= 200000) {
4266                 clock->p1 = 1;
4267                 clock->p2 = 10;
4268                 clock->n = 6;
4269                 clock->m1 = 12;
4270                 clock->m2 = 8;
4271         }
4272 }
4273
4274 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4275                                      intel_clock_t *clock,
4276                                      intel_clock_t *reduced_clock)
4277 {
4278         struct drm_device *dev = crtc->dev;
4279         struct drm_i915_private *dev_priv = dev->dev_private;
4280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281         int pipe = intel_crtc->pipe;
4282         u32 fp, fp2 = 0;
4283
4284         if (IS_PINEVIEW(dev)) {
4285                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4286                 if (reduced_clock)
4287                         fp2 = (1 << reduced_clock->n) << 16 |
4288                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4289         } else {
4290                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4291                 if (reduced_clock)
4292                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4293                                 reduced_clock->m2;
4294         }
4295
4296         I915_WRITE(FP0(pipe), fp);
4297
4298         intel_crtc->lowfreq_avail = false;
4299         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4300             reduced_clock && i915_powersave) {
4301                 I915_WRITE(FP1(pipe), fp2);
4302                 intel_crtc->lowfreq_avail = true;
4303         } else {
4304                 I915_WRITE(FP1(pipe), fp);
4305         }
4306 }
4307
4308 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4309                               struct drm_display_mode *adjusted_mode)
4310 {
4311         struct drm_device *dev = crtc->dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314         int pipe = intel_crtc->pipe;
4315         u32 temp;
4316
4317         temp = I915_READ(LVDS);
4318         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4319         if (pipe == 1) {
4320                 temp |= LVDS_PIPEB_SELECT;
4321         } else {
4322                 temp &= ~LVDS_PIPEB_SELECT;
4323         }
4324         /* set the corresponsding LVDS_BORDER bit */
4325         temp |= dev_priv->lvds_border_bits;
4326         /* Set the B0-B3 data pairs corresponding to whether we're going to
4327          * set the DPLLs for dual-channel mode or not.
4328          */
4329         if (clock->p2 == 7)
4330                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4331         else
4332                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4333
4334         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4335          * appropriately here, but we need to look more thoroughly into how
4336          * panels behave in the two modes.
4337          */
4338         /* set the dithering flag on LVDS as needed */
4339         if (INTEL_INFO(dev)->gen >= 4) {
4340                 if (dev_priv->lvds_dither)
4341                         temp |= LVDS_ENABLE_DITHER;
4342                 else
4343                         temp &= ~LVDS_ENABLE_DITHER;
4344         }
4345         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4346         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4347                 temp |= LVDS_HSYNC_POLARITY;
4348         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4349                 temp |= LVDS_VSYNC_POLARITY;
4350         I915_WRITE(LVDS, temp);
4351 }
4352
4353 static void vlv_update_pll(struct drm_crtc *crtc,
4354                            struct drm_display_mode *mode,
4355                            struct drm_display_mode *adjusted_mode,
4356                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4357                            int num_connectors)
4358 {
4359         struct drm_device *dev = crtc->dev;
4360         struct drm_i915_private *dev_priv = dev->dev_private;
4361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4362         int pipe = intel_crtc->pipe;
4363         u32 dpll, mdiv, pdiv;
4364         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4365         bool is_sdvo;
4366         u32 temp;
4367
4368         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4369                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4370
4371         dpll = DPLL_VGA_MODE_DIS;
4372         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4373         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4374         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4375
4376         I915_WRITE(DPLL(pipe), dpll);
4377         POSTING_READ(DPLL(pipe));
4378
4379         bestn = clock->n;
4380         bestm1 = clock->m1;
4381         bestm2 = clock->m2;
4382         bestp1 = clock->p1;
4383         bestp2 = clock->p2;
4384
4385         /*
4386          * In Valleyview PLL and program lane counter registers are exposed
4387          * through DPIO interface
4388          */
4389         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391         mdiv |= ((bestn << DPIO_N_SHIFT));
4392         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4393         mdiv |= (1 << DPIO_K_SHIFT);
4394         mdiv |= DPIO_ENABLE_CALIBRATION;
4395         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4396
4397         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4398
4399         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4400                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4401                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4402                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4403         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4404
4405         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4406
4407         dpll |= DPLL_VCO_ENABLE;
4408         I915_WRITE(DPLL(pipe), dpll);
4409         POSTING_READ(DPLL(pipe));
4410         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4411                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4412
4413         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4414
4415         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4416                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4417
4418         I915_WRITE(DPLL(pipe), dpll);
4419
4420         /* Wait for the clocks to stabilize. */
4421         POSTING_READ(DPLL(pipe));
4422         udelay(150);
4423
4424         temp = 0;
4425         if (is_sdvo) {
4426                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4427                 if (temp > 1)
4428                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4429                 else
4430                         temp = 0;
4431         }
4432         I915_WRITE(DPLL_MD(pipe), temp);
4433         POSTING_READ(DPLL_MD(pipe));
4434
4435         /* Now program lane control registers */
4436         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4437                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4438         {
4439                 temp = 0x1000C4;
4440                 if(pipe == 1)
4441                         temp |= (1 << 21);
4442                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4443         }
4444         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4445         {
4446                 temp = 0x1000C4;
4447                 if(pipe == 1)
4448                         temp |= (1 << 21);
4449                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4450         }
4451 }
4452
4453 static void i9xx_update_pll(struct drm_crtc *crtc,
4454                             struct drm_display_mode *mode,
4455                             struct drm_display_mode *adjusted_mode,
4456                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4457                             int num_connectors)
4458 {
4459         struct drm_device *dev = crtc->dev;
4460         struct drm_i915_private *dev_priv = dev->dev_private;
4461         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4462         int pipe = intel_crtc->pipe;
4463         u32 dpll;
4464         bool is_sdvo;
4465
4466         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4467
4468         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4469                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4470
4471         dpll = DPLL_VGA_MODE_DIS;
4472
4473         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4474                 dpll |= DPLLB_MODE_LVDS;
4475         else
4476                 dpll |= DPLLB_MODE_DAC_SERIAL;
4477         if (is_sdvo) {
4478                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4479                 if (pixel_multiplier > 1) {
4480                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4481                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4482                 }
4483                 dpll |= DPLL_DVO_HIGH_SPEED;
4484         }
4485         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4486                 dpll |= DPLL_DVO_HIGH_SPEED;
4487
4488         /* compute bitmask from p1 value */
4489         if (IS_PINEVIEW(dev))
4490                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4491         else {
4492                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4493                 if (IS_G4X(dev) && reduced_clock)
4494                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4495         }
4496         switch (clock->p2) {
4497         case 5:
4498                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4499                 break;
4500         case 7:
4501                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4502                 break;
4503         case 10:
4504                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4505                 break;
4506         case 14:
4507                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4508                 break;
4509         }
4510         if (INTEL_INFO(dev)->gen >= 4)
4511                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4512
4513         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4514                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4515         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4516                 /* XXX: just matching BIOS for now */
4517                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4518                 dpll |= 3;
4519         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4520                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4521                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4522         else
4523                 dpll |= PLL_REF_INPUT_DREFCLK;
4524
4525         dpll |= DPLL_VCO_ENABLE;
4526         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4527         POSTING_READ(DPLL(pipe));
4528         udelay(150);
4529
4530         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4531          * This is an exception to the general rule that mode_set doesn't turn
4532          * things on.
4533          */
4534         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4535                 intel_update_lvds(crtc, clock, adjusted_mode);
4536
4537         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4538                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4539
4540         I915_WRITE(DPLL(pipe), dpll);
4541
4542         /* Wait for the clocks to stabilize. */
4543         POSTING_READ(DPLL(pipe));
4544         udelay(150);
4545
4546         if (INTEL_INFO(dev)->gen >= 4) {
4547                 u32 temp = 0;
4548                 if (is_sdvo) {
4549                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4550                         if (temp > 1)
4551                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4552                         else
4553                                 temp = 0;
4554                 }
4555                 I915_WRITE(DPLL_MD(pipe), temp);
4556         } else {
4557                 /* The pixel multiplier can only be updated once the
4558                  * DPLL is enabled and the clocks are stable.
4559                  *
4560                  * So write it again.
4561                  */
4562                 I915_WRITE(DPLL(pipe), dpll);
4563         }
4564 }
4565
4566 static void i8xx_update_pll(struct drm_crtc *crtc,
4567                             struct drm_display_mode *adjusted_mode,
4568                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4569                             int num_connectors)
4570 {
4571         struct drm_device *dev = crtc->dev;
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4574         int pipe = intel_crtc->pipe;
4575         u32 dpll;
4576
4577         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4578
4579         dpll = DPLL_VGA_MODE_DIS;
4580
4581         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4582                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4583         } else {
4584                 if (clock->p1 == 2)
4585                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4586                 else
4587                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588                 if (clock->p2 == 4)
4589                         dpll |= PLL_P2_DIVIDE_BY_4;
4590         }
4591
4592         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4593                 /* XXX: just matching BIOS for now */
4594                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4595                 dpll |= 3;
4596         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4597                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4598                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4599         else
4600                 dpll |= PLL_REF_INPUT_DREFCLK;
4601
4602         dpll |= DPLL_VCO_ENABLE;
4603         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4604         POSTING_READ(DPLL(pipe));
4605         udelay(150);
4606
4607         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4608          * This is an exception to the general rule that mode_set doesn't turn
4609          * things on.
4610          */
4611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4612                 intel_update_lvds(crtc, clock, adjusted_mode);
4613
4614         I915_WRITE(DPLL(pipe), dpll);
4615
4616         /* Wait for the clocks to stabilize. */
4617         POSTING_READ(DPLL(pipe));
4618         udelay(150);
4619
4620         /* The pixel multiplier can only be updated once the
4621          * DPLL is enabled and the clocks are stable.
4622          *
4623          * So write it again.
4624          */
4625         I915_WRITE(DPLL(pipe), dpll);
4626 }
4627
4628 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4629                                    struct drm_display_mode *mode,
4630                                    struct drm_display_mode *adjusted_mode)
4631 {
4632         struct drm_device *dev = intel_crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         enum pipe pipe = intel_crtc->pipe;
4635         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4636         uint32_t vsyncshift;
4637
4638         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4639                 /* the chip adds 2 halflines automatically */
4640                 adjusted_mode->crtc_vtotal -= 1;
4641                 adjusted_mode->crtc_vblank_end -= 1;
4642                 vsyncshift = adjusted_mode->crtc_hsync_start
4643                              - adjusted_mode->crtc_htotal / 2;
4644         } else {
4645                 vsyncshift = 0;
4646         }
4647
4648         if (INTEL_INFO(dev)->gen > 3)
4649                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4650
4651         I915_WRITE(HTOTAL(cpu_transcoder),
4652                    (adjusted_mode->crtc_hdisplay - 1) |
4653                    ((adjusted_mode->crtc_htotal - 1) << 16));
4654         I915_WRITE(HBLANK(cpu_transcoder),
4655                    (adjusted_mode->crtc_hblank_start - 1) |
4656                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4657         I915_WRITE(HSYNC(cpu_transcoder),
4658                    (adjusted_mode->crtc_hsync_start - 1) |
4659                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4660
4661         I915_WRITE(VTOTAL(cpu_transcoder),
4662                    (adjusted_mode->crtc_vdisplay - 1) |
4663                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4664         I915_WRITE(VBLANK(cpu_transcoder),
4665                    (adjusted_mode->crtc_vblank_start - 1) |
4666                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4667         I915_WRITE(VSYNC(cpu_transcoder),
4668                    (adjusted_mode->crtc_vsync_start - 1) |
4669                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4670
4671         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4672          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4673          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4674          * bits. */
4675         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4676             (pipe == PIPE_B || pipe == PIPE_C))
4677                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4678
4679         /* pipesrc controls the size that is scaled from, which should
4680          * always be the user's requested size.
4681          */
4682         I915_WRITE(PIPESRC(pipe),
4683                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4684 }
4685
4686 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4687                               struct drm_display_mode *mode,
4688                               struct drm_display_mode *adjusted_mode,
4689                               int x, int y,
4690                               struct drm_framebuffer *fb)
4691 {
4692         struct drm_device *dev = crtc->dev;
4693         struct drm_i915_private *dev_priv = dev->dev_private;
4694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4695         int pipe = intel_crtc->pipe;
4696         int plane = intel_crtc->plane;
4697         int refclk, num_connectors = 0;
4698         intel_clock_t clock, reduced_clock;
4699         u32 dspcntr, pipeconf;
4700         bool ok, has_reduced_clock = false, is_sdvo = false;
4701         bool is_lvds = false, is_tv = false, is_dp = false;
4702         struct intel_encoder *encoder;
4703         const intel_limit_t *limit;
4704         int ret;
4705
4706         for_each_encoder_on_crtc(dev, crtc, encoder) {
4707                 switch (encoder->type) {
4708                 case INTEL_OUTPUT_LVDS:
4709                         is_lvds = true;
4710                         break;
4711                 case INTEL_OUTPUT_SDVO:
4712                 case INTEL_OUTPUT_HDMI:
4713                         is_sdvo = true;
4714                         if (encoder->needs_tv_clock)
4715                                 is_tv = true;
4716                         break;
4717                 case INTEL_OUTPUT_TVOUT:
4718                         is_tv = true;
4719                         break;
4720                 case INTEL_OUTPUT_DISPLAYPORT:
4721                         is_dp = true;
4722                         break;
4723                 }
4724
4725                 num_connectors++;
4726         }
4727
4728         refclk = i9xx_get_refclk(crtc, num_connectors);
4729
4730         /*
4731          * Returns a set of divisors for the desired target clock with the given
4732          * refclk, or FALSE.  The returned values represent the clock equation:
4733          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4734          */
4735         limit = intel_limit(crtc, refclk);
4736         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4737                              &clock);
4738         if (!ok) {
4739                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4740                 return -EINVAL;
4741         }
4742
4743         /* Ensure that the cursor is valid for the new mode before changing... */
4744         intel_crtc_update_cursor(crtc, true);
4745
4746         if (is_lvds && dev_priv->lvds_downclock_avail) {
4747                 /*
4748                  * Ensure we match the reduced clock's P to the target clock.
4749                  * If the clocks don't match, we can't switch the display clock
4750                  * by using the FP0/FP1. In such case we will disable the LVDS
4751                  * downclock feature.
4752                 */
4753                 has_reduced_clock = limit->find_pll(limit, crtc,
4754                                                     dev_priv->lvds_downclock,
4755                                                     refclk,
4756                                                     &clock,
4757                                                     &reduced_clock);
4758         }
4759
4760         if (is_sdvo && is_tv)
4761                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4762
4763         if (IS_GEN2(dev))
4764                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4765                                 has_reduced_clock ? &reduced_clock : NULL,
4766                                 num_connectors);
4767         else if (IS_VALLEYVIEW(dev))
4768                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4769                                 has_reduced_clock ? &reduced_clock : NULL,
4770                                 num_connectors);
4771         else
4772                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4773                                 has_reduced_clock ? &reduced_clock : NULL,
4774                                 num_connectors);
4775
4776         /* setup pipeconf */
4777         pipeconf = I915_READ(PIPECONF(pipe));
4778
4779         /* Set up the display plane register */
4780         dspcntr = DISPPLANE_GAMMA_ENABLE;
4781
4782         if (pipe == 0)
4783                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4784         else
4785                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4786
4787         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4788                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4789                  * core speed.
4790                  *
4791                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4792                  * pipe == 0 check?
4793                  */
4794                 if (mode->clock >
4795                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4796                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4797                 else
4798                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4799         }
4800
4801         /* default to 8bpc */
4802         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4803         if (is_dp) {
4804                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4805                         pipeconf |= PIPECONF_BPP_6 |
4806                                     PIPECONF_DITHER_EN |
4807                                     PIPECONF_DITHER_TYPE_SP;
4808                 }
4809         }
4810
4811         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4812                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4813                         pipeconf |= PIPECONF_BPP_6 |
4814                                         PIPECONF_ENABLE |
4815                                         I965_PIPECONF_ACTIVE;
4816                 }
4817         }
4818
4819         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4820         drm_mode_debug_printmodeline(mode);
4821
4822         if (HAS_PIPE_CXSR(dev)) {
4823                 if (intel_crtc->lowfreq_avail) {
4824                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4825                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4826                 } else {
4827                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4828                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4829                 }
4830         }
4831
4832         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4833         if (!IS_GEN2(dev) &&
4834             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4835                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4836         else
4837                 pipeconf |= PIPECONF_PROGRESSIVE;
4838
4839         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4840
4841         /* pipesrc and dspsize control the size that is scaled from,
4842          * which should always be the user's requested size.
4843          */
4844         I915_WRITE(DSPSIZE(plane),
4845                    ((mode->vdisplay - 1) << 16) |
4846                    (mode->hdisplay - 1));
4847         I915_WRITE(DSPPOS(plane), 0);
4848
4849         I915_WRITE(PIPECONF(pipe), pipeconf);
4850         POSTING_READ(PIPECONF(pipe));
4851         intel_enable_pipe(dev_priv, pipe, false);
4852
4853         intel_wait_for_vblank(dev, pipe);
4854
4855         I915_WRITE(DSPCNTR(plane), dspcntr);
4856         POSTING_READ(DSPCNTR(plane));
4857
4858         ret = intel_pipe_set_base(crtc, x, y, fb);
4859
4860         intel_update_watermarks(dev);
4861
4862         return ret;
4863 }
4864
4865 /*
4866  * Initialize reference clocks when the driver loads
4867  */
4868 void ironlake_init_pch_refclk(struct drm_device *dev)
4869 {
4870         struct drm_i915_private *dev_priv = dev->dev_private;
4871         struct drm_mode_config *mode_config = &dev->mode_config;
4872         struct intel_encoder *encoder;
4873         u32 temp;
4874         bool has_lvds = false;
4875         bool has_cpu_edp = false;
4876         bool has_pch_edp = false;
4877         bool has_panel = false;
4878         bool has_ck505 = false;
4879         bool can_ssc = false;
4880
4881         /* We need to take the global config into account */
4882         list_for_each_entry(encoder, &mode_config->encoder_list,
4883                             base.head) {
4884                 switch (encoder->type) {
4885                 case INTEL_OUTPUT_LVDS:
4886                         has_panel = true;
4887                         has_lvds = true;
4888                         break;
4889                 case INTEL_OUTPUT_EDP:
4890                         has_panel = true;
4891                         if (intel_encoder_is_pch_edp(&encoder->base))
4892                                 has_pch_edp = true;
4893                         else
4894                                 has_cpu_edp = true;
4895                         break;
4896                 }
4897         }
4898
4899         if (HAS_PCH_IBX(dev)) {
4900                 has_ck505 = dev_priv->display_clock_mode;
4901                 can_ssc = has_ck505;
4902         } else {
4903                 has_ck505 = false;
4904                 can_ssc = true;
4905         }
4906
4907         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4908                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4909                       has_ck505);
4910
4911         /* Ironlake: try to setup display ref clock before DPLL
4912          * enabling. This is only under driver's control after
4913          * PCH B stepping, previous chipset stepping should be
4914          * ignoring this setting.
4915          */
4916         temp = I915_READ(PCH_DREF_CONTROL);
4917         /* Always enable nonspread source */
4918         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4919
4920         if (has_ck505)
4921                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4922         else
4923                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4924
4925         if (has_panel) {
4926                 temp &= ~DREF_SSC_SOURCE_MASK;
4927                 temp |= DREF_SSC_SOURCE_ENABLE;
4928
4929                 /* SSC must be turned on before enabling the CPU output  */
4930                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4931                         DRM_DEBUG_KMS("Using SSC on panel\n");
4932                         temp |= DREF_SSC1_ENABLE;
4933                 } else
4934                         temp &= ~DREF_SSC1_ENABLE;
4935
4936                 /* Get SSC going before enabling the outputs */
4937                 I915_WRITE(PCH_DREF_CONTROL, temp);
4938                 POSTING_READ(PCH_DREF_CONTROL);
4939                 udelay(200);
4940
4941                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4942
4943                 /* Enable CPU source on CPU attached eDP */
4944                 if (has_cpu_edp) {
4945                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4946                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4947                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4948                         }
4949                         else
4950                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4951                 } else
4952                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4953
4954                 I915_WRITE(PCH_DREF_CONTROL, temp);
4955                 POSTING_READ(PCH_DREF_CONTROL);
4956                 udelay(200);
4957         } else {
4958                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4959
4960                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4961
4962                 /* Turn off CPU output */
4963                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4964
4965                 I915_WRITE(PCH_DREF_CONTROL, temp);
4966                 POSTING_READ(PCH_DREF_CONTROL);
4967                 udelay(200);
4968
4969                 /* Turn off the SSC source */
4970                 temp &= ~DREF_SSC_SOURCE_MASK;
4971                 temp |= DREF_SSC_SOURCE_DISABLE;
4972
4973                 /* Turn off SSC1 */
4974                 temp &= ~ DREF_SSC1_ENABLE;
4975
4976                 I915_WRITE(PCH_DREF_CONTROL, temp);
4977                 POSTING_READ(PCH_DREF_CONTROL);
4978                 udelay(200);
4979         }
4980 }
4981
4982 static int ironlake_get_refclk(struct drm_crtc *crtc)
4983 {
4984         struct drm_device *dev = crtc->dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         struct intel_encoder *encoder;
4987         struct intel_encoder *edp_encoder = NULL;
4988         int num_connectors = 0;
4989         bool is_lvds = false;
4990
4991         for_each_encoder_on_crtc(dev, crtc, encoder) {
4992                 switch (encoder->type) {
4993                 case INTEL_OUTPUT_LVDS:
4994                         is_lvds = true;
4995                         break;
4996                 case INTEL_OUTPUT_EDP:
4997                         edp_encoder = encoder;
4998                         break;
4999                 }
5000                 num_connectors++;
5001         }
5002
5003         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5004                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5005                               dev_priv->lvds_ssc_freq);
5006                 return dev_priv->lvds_ssc_freq * 1000;
5007         }
5008
5009         return 120000;
5010 }
5011
5012 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5013                                   struct drm_display_mode *adjusted_mode,
5014                                   bool dither)
5015 {
5016         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5018         int pipe = intel_crtc->pipe;
5019         uint32_t val;
5020
5021         val = I915_READ(PIPECONF(pipe));
5022
5023         val &= ~PIPE_BPC_MASK;
5024         switch (intel_crtc->bpp) {
5025         case 18:
5026                 val |= PIPE_6BPC;
5027                 break;
5028         case 24:
5029                 val |= PIPE_8BPC;
5030                 break;
5031         case 30:
5032                 val |= PIPE_10BPC;
5033                 break;
5034         case 36:
5035                 val |= PIPE_12BPC;
5036                 break;
5037         default:
5038                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5039                 BUG();
5040         }
5041
5042         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5043         if (dither)
5044                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5045
5046         val &= ~PIPECONF_INTERLACE_MASK;
5047         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5048                 val |= PIPECONF_INTERLACED_ILK;
5049         else
5050                 val |= PIPECONF_PROGRESSIVE;
5051
5052         I915_WRITE(PIPECONF(pipe), val);
5053         POSTING_READ(PIPECONF(pipe));
5054 }
5055
5056 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5057                                  struct drm_display_mode *adjusted_mode,
5058                                  bool dither)
5059 {
5060         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5063         uint32_t val;
5064
5065         val = I915_READ(PIPECONF(cpu_transcoder));
5066
5067         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5068         if (dither)
5069                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5070
5071         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5072         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5073                 val |= PIPECONF_INTERLACED_ILK;
5074         else
5075                 val |= PIPECONF_PROGRESSIVE;
5076
5077         I915_WRITE(PIPECONF(cpu_transcoder), val);
5078         POSTING_READ(PIPECONF(cpu_transcoder));
5079 }
5080
5081 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5082                                     struct drm_display_mode *adjusted_mode,
5083                                     intel_clock_t *clock,
5084                                     bool *has_reduced_clock,
5085                                     intel_clock_t *reduced_clock)
5086 {
5087         struct drm_device *dev = crtc->dev;
5088         struct drm_i915_private *dev_priv = dev->dev_private;
5089         struct intel_encoder *intel_encoder;
5090         int refclk;
5091         const intel_limit_t *limit;
5092         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5093
5094         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5095                 switch (intel_encoder->type) {
5096                 case INTEL_OUTPUT_LVDS:
5097                         is_lvds = true;
5098                         break;
5099                 case INTEL_OUTPUT_SDVO:
5100                 case INTEL_OUTPUT_HDMI:
5101                         is_sdvo = true;
5102                         if (intel_encoder->needs_tv_clock)
5103                                 is_tv = true;
5104                         break;
5105                 case INTEL_OUTPUT_TVOUT:
5106                         is_tv = true;
5107                         break;
5108                 }
5109         }
5110
5111         refclk = ironlake_get_refclk(crtc);
5112
5113         /*
5114          * Returns a set of divisors for the desired target clock with the given
5115          * refclk, or FALSE.  The returned values represent the clock equation:
5116          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5117          */
5118         limit = intel_limit(crtc, refclk);
5119         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5120                               clock);
5121         if (!ret)
5122                 return false;
5123
5124         if (is_lvds && dev_priv->lvds_downclock_avail) {
5125                 /*
5126                  * Ensure we match the reduced clock's P to the target clock.
5127                  * If the clocks don't match, we can't switch the display clock
5128                  * by using the FP0/FP1. In such case we will disable the LVDS
5129                  * downclock feature.
5130                 */
5131                 *has_reduced_clock = limit->find_pll(limit, crtc,
5132                                                      dev_priv->lvds_downclock,
5133                                                      refclk,
5134                                                      clock,
5135                                                      reduced_clock);
5136         }
5137
5138         if (is_sdvo && is_tv)
5139                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5140
5141         return true;
5142 }
5143
5144 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5145 {
5146         struct drm_i915_private *dev_priv = dev->dev_private;
5147         uint32_t temp;
5148
5149         temp = I915_READ(SOUTH_CHICKEN1);
5150         if (temp & FDI_BC_BIFURCATION_SELECT)
5151                 return;
5152
5153         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5154         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5155
5156         temp |= FDI_BC_BIFURCATION_SELECT;
5157         DRM_DEBUG_KMS("enabling fdi C rx\n");
5158         I915_WRITE(SOUTH_CHICKEN1, temp);
5159         POSTING_READ(SOUTH_CHICKEN1);
5160 }
5161
5162 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5163 {
5164         struct drm_device *dev = intel_crtc->base.dev;
5165         struct drm_i915_private *dev_priv = dev->dev_private;
5166         struct intel_crtc *pipe_B_crtc =
5167                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5168
5169         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5170                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5171         if (intel_crtc->fdi_lanes > 4) {
5172                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5173                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5174                 /* Clamp lanes to avoid programming the hw with bogus values. */
5175                 intel_crtc->fdi_lanes = 4;
5176
5177                 return false;
5178         }
5179
5180         if (dev_priv->num_pipe == 2)
5181                 return true;
5182
5183         switch (intel_crtc->pipe) {
5184         case PIPE_A:
5185                 return true;
5186         case PIPE_B:
5187                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5188                     intel_crtc->fdi_lanes > 2) {
5189                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5190                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5191                         /* Clamp lanes to avoid programming the hw with bogus values. */
5192                         intel_crtc->fdi_lanes = 2;
5193
5194                         return false;
5195                 }
5196
5197                 if (intel_crtc->fdi_lanes > 2)
5198                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5199                 else
5200                         cpt_enable_fdi_bc_bifurcation(dev);
5201
5202                 return true;
5203         case PIPE_C:
5204                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5205                         if (intel_crtc->fdi_lanes > 2) {
5206                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5207                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5208                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5209                                 intel_crtc->fdi_lanes = 2;
5210
5211                                 return false;
5212                         }
5213                 } else {
5214                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5215                         return false;
5216                 }
5217
5218                 cpt_enable_fdi_bc_bifurcation(dev);
5219
5220                 return true;
5221         default:
5222                 BUG();
5223         }
5224 }
5225
5226 static void ironlake_set_m_n(struct drm_crtc *crtc,
5227                              struct drm_display_mode *mode,
5228                              struct drm_display_mode *adjusted_mode)
5229 {
5230         struct drm_device *dev = crtc->dev;
5231         struct drm_i915_private *dev_priv = dev->dev_private;
5232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5234         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5235         struct fdi_m_n m_n = {0};
5236         int target_clock, pixel_multiplier, lane, link_bw;
5237         bool is_dp = false, is_cpu_edp = false;
5238
5239         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5240                 switch (intel_encoder->type) {
5241                 case INTEL_OUTPUT_DISPLAYPORT:
5242                         is_dp = true;
5243                         break;
5244                 case INTEL_OUTPUT_EDP:
5245                         is_dp = true;
5246                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5247                                 is_cpu_edp = true;
5248                         edp_encoder = intel_encoder;
5249                         break;
5250                 }
5251         }
5252
5253         /* FDI link */
5254         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5255         lane = 0;
5256         /* CPU eDP doesn't require FDI link, so just set DP M/N
5257            according to current link config */
5258         if (is_cpu_edp) {
5259                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5260         } else {
5261                 /* FDI is a binary signal running at ~2.7GHz, encoding
5262                  * each output octet as 10 bits. The actual frequency
5263                  * is stored as a divider into a 100MHz clock, and the
5264                  * mode pixel clock is stored in units of 1KHz.
5265                  * Hence the bw of each lane in terms of the mode signal
5266                  * is:
5267                  */
5268                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5269         }
5270
5271         /* [e]DP over FDI requires target mode clock instead of link clock. */
5272         if (edp_encoder)
5273                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5274         else if (is_dp)
5275                 target_clock = mode->clock;
5276         else
5277                 target_clock = adjusted_mode->clock;
5278
5279         if (!lane) {
5280                 /*
5281                  * Account for spread spectrum to avoid
5282                  * oversubscribing the link. Max center spread
5283                  * is 2.5%; use 5% for safety's sake.
5284                  */
5285                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5286                 lane = bps / (link_bw * 8) + 1;
5287         }
5288
5289         intel_crtc->fdi_lanes = lane;
5290
5291         if (pixel_multiplier > 1)
5292                 link_bw *= pixel_multiplier;
5293         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5294                              &m_n);
5295
5296         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5297         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5298         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5299         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5300 }
5301
5302 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5303                                       struct drm_display_mode *adjusted_mode,
5304                                       intel_clock_t *clock, u32 fp)
5305 {
5306         struct drm_crtc *crtc = &intel_crtc->base;
5307         struct drm_device *dev = crtc->dev;
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         struct intel_encoder *intel_encoder;
5310         uint32_t dpll;
5311         int factor, pixel_multiplier, num_connectors = 0;
5312         bool is_lvds = false, is_sdvo = false, is_tv = false;
5313         bool is_dp = false, is_cpu_edp = false;
5314
5315         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5316                 switch (intel_encoder->type) {
5317                 case INTEL_OUTPUT_LVDS:
5318                         is_lvds = true;
5319                         break;
5320                 case INTEL_OUTPUT_SDVO:
5321                 case INTEL_OUTPUT_HDMI:
5322                         is_sdvo = true;
5323                         if (intel_encoder->needs_tv_clock)
5324                                 is_tv = true;
5325                         break;
5326                 case INTEL_OUTPUT_TVOUT:
5327                         is_tv = true;
5328                         break;
5329                 case INTEL_OUTPUT_DISPLAYPORT:
5330                         is_dp = true;
5331                         break;
5332                 case INTEL_OUTPUT_EDP:
5333                         is_dp = true;
5334                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5335                                 is_cpu_edp = true;
5336                         break;
5337                 }
5338
5339                 num_connectors++;
5340         }
5341
5342         /* Enable autotuning of the PLL clock (if permissible) */
5343         factor = 21;
5344         if (is_lvds) {
5345                 if ((intel_panel_use_ssc(dev_priv) &&
5346                      dev_priv->lvds_ssc_freq == 100) ||
5347                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5348                         factor = 25;
5349         } else if (is_sdvo && is_tv)
5350                 factor = 20;
5351
5352         if (clock->m < factor * clock->n)
5353                 fp |= FP_CB_TUNE;
5354
5355         dpll = 0;
5356
5357         if (is_lvds)
5358                 dpll |= DPLLB_MODE_LVDS;
5359         else
5360                 dpll |= DPLLB_MODE_DAC_SERIAL;
5361         if (is_sdvo) {
5362                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5363                 if (pixel_multiplier > 1) {
5364                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5365                 }
5366                 dpll |= DPLL_DVO_HIGH_SPEED;
5367         }
5368         if (is_dp && !is_cpu_edp)
5369                 dpll |= DPLL_DVO_HIGH_SPEED;
5370
5371         /* compute bitmask from p1 value */
5372         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5373         /* also FPA1 */
5374         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5375
5376         switch (clock->p2) {
5377         case 5:
5378                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5379                 break;
5380         case 7:
5381                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5382                 break;
5383         case 10:
5384                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5385                 break;
5386         case 14:
5387                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5388                 break;
5389         }
5390
5391         if (is_sdvo && is_tv)
5392                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5393         else if (is_tv)
5394                 /* XXX: just matching BIOS for now */
5395                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5396                 dpll |= 3;
5397         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5398                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5399         else
5400                 dpll |= PLL_REF_INPUT_DREFCLK;
5401
5402         return dpll;
5403 }
5404
5405 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5406                                   struct drm_display_mode *mode,
5407                                   struct drm_display_mode *adjusted_mode,
5408                                   int x, int y,
5409                                   struct drm_framebuffer *fb)
5410 {
5411         struct drm_device *dev = crtc->dev;
5412         struct drm_i915_private *dev_priv = dev->dev_private;
5413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414         int pipe = intel_crtc->pipe;
5415         int plane = intel_crtc->plane;
5416         int num_connectors = 0;
5417         intel_clock_t clock, reduced_clock;
5418         u32 dpll, fp = 0, fp2 = 0;
5419         bool ok, has_reduced_clock = false;
5420         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5421         struct intel_encoder *encoder;
5422         u32 temp;
5423         int ret;
5424         bool dither, fdi_config_ok;
5425
5426         for_each_encoder_on_crtc(dev, crtc, encoder) {
5427                 switch (encoder->type) {
5428                 case INTEL_OUTPUT_LVDS:
5429                         is_lvds = true;
5430                         break;
5431                 case INTEL_OUTPUT_DISPLAYPORT:
5432                         is_dp = true;
5433                         break;
5434                 case INTEL_OUTPUT_EDP:
5435                         is_dp = true;
5436                         if (!intel_encoder_is_pch_edp(&encoder->base))
5437                                 is_cpu_edp = true;
5438                         break;
5439                 }
5440
5441                 num_connectors++;
5442         }
5443
5444         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5445              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5446
5447         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5448                                      &has_reduced_clock, &reduced_clock);
5449         if (!ok) {
5450                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5451                 return -EINVAL;
5452         }
5453
5454         /* Ensure that the cursor is valid for the new mode before changing... */
5455         intel_crtc_update_cursor(crtc, true);
5456
5457         /* determine panel color depth */
5458         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5459                                               adjusted_mode);
5460         if (is_lvds && dev_priv->lvds_dither)
5461                 dither = true;
5462
5463         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5464         if (has_reduced_clock)
5465                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5466                         reduced_clock.m2;
5467
5468         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5469
5470         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5471         drm_mode_debug_printmodeline(mode);
5472
5473         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5474         if (!is_cpu_edp) {
5475                 struct intel_pch_pll *pll;
5476
5477                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5478                 if (pll == NULL) {
5479                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5480                                          pipe);
5481                         return -EINVAL;
5482                 }
5483         } else
5484                 intel_put_pch_pll(intel_crtc);
5485
5486         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5487          * This is an exception to the general rule that mode_set doesn't turn
5488          * things on.
5489          */
5490         if (is_lvds) {
5491                 temp = I915_READ(PCH_LVDS);
5492                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5493                 if (HAS_PCH_CPT(dev)) {
5494                         temp &= ~PORT_TRANS_SEL_MASK;
5495                         temp |= PORT_TRANS_SEL_CPT(pipe);
5496                 } else {
5497                         if (pipe == 1)
5498                                 temp |= LVDS_PIPEB_SELECT;
5499                         else
5500                                 temp &= ~LVDS_PIPEB_SELECT;
5501                 }
5502
5503                 /* set the corresponsding LVDS_BORDER bit */
5504                 temp |= dev_priv->lvds_border_bits;
5505                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5506                  * set the DPLLs for dual-channel mode or not.
5507                  */
5508                 if (clock.p2 == 7)
5509                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5510                 else
5511                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5512
5513                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5514                  * appropriately here, but we need to look more thoroughly into how
5515                  * panels behave in the two modes.
5516                  */
5517                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5518                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5519                         temp |= LVDS_HSYNC_POLARITY;
5520                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5521                         temp |= LVDS_VSYNC_POLARITY;
5522                 I915_WRITE(PCH_LVDS, temp);
5523         }
5524
5525         if (is_dp && !is_cpu_edp) {
5526                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5527         } else {
5528                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5529                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5530                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5531                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5532                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5533         }
5534
5535         if (intel_crtc->pch_pll) {
5536                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5537
5538                 /* Wait for the clocks to stabilize. */
5539                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5540                 udelay(150);
5541
5542                 /* The pixel multiplier can only be updated once the
5543                  * DPLL is enabled and the clocks are stable.
5544                  *
5545                  * So write it again.
5546                  */
5547                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5548         }
5549
5550         intel_crtc->lowfreq_avail = false;
5551         if (intel_crtc->pch_pll) {
5552                 if (is_lvds && has_reduced_clock && i915_powersave) {
5553                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5554                         intel_crtc->lowfreq_avail = true;
5555                 } else {
5556                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5557                 }
5558         }
5559
5560         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5561
5562         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5563          * ironlake_check_fdi_lanes. */
5564         ironlake_set_m_n(crtc, mode, adjusted_mode);
5565
5566         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5567
5568         if (is_cpu_edp)
5569                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5570
5571         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5572
5573         intel_wait_for_vblank(dev, pipe);
5574
5575         /* Set up the display plane register */
5576         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5577         POSTING_READ(DSPCNTR(plane));
5578
5579         ret = intel_pipe_set_base(crtc, x, y, fb);
5580
5581         intel_update_watermarks(dev);
5582
5583         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5584
5585         return fdi_config_ok ? ret : -EINVAL;
5586 }
5587
5588 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5589                                  struct drm_display_mode *mode,
5590                                  struct drm_display_mode *adjusted_mode,
5591                                  int x, int y,
5592                                  struct drm_framebuffer *fb)
5593 {
5594         struct drm_device *dev = crtc->dev;
5595         struct drm_i915_private *dev_priv = dev->dev_private;
5596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5597         int pipe = intel_crtc->pipe;
5598         int plane = intel_crtc->plane;
5599         int num_connectors = 0;
5600         intel_clock_t clock, reduced_clock;
5601         u32 dpll = 0, fp = 0, fp2 = 0;
5602         bool ok, has_reduced_clock = false;
5603         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5604         struct intel_encoder *encoder;
5605         u32 temp;
5606         int ret;
5607         bool dither;
5608
5609         for_each_encoder_on_crtc(dev, crtc, encoder) {
5610                 switch (encoder->type) {
5611                 case INTEL_OUTPUT_LVDS:
5612                         is_lvds = true;
5613                         break;
5614                 case INTEL_OUTPUT_DISPLAYPORT:
5615                         is_dp = true;
5616                         break;
5617                 case INTEL_OUTPUT_EDP:
5618                         is_dp = true;
5619                         if (!intel_encoder_is_pch_edp(&encoder->base))
5620                                 is_cpu_edp = true;
5621                         break;
5622                 }
5623
5624                 num_connectors++;
5625         }
5626
5627         if (is_cpu_edp)
5628                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5629         else
5630                 intel_crtc->cpu_transcoder = pipe;
5631
5632         /* We are not sure yet this won't happen. */
5633         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5634              INTEL_PCH_TYPE(dev));
5635
5636         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5637              num_connectors, pipe_name(pipe));
5638
5639         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5640                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5641
5642         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5643
5644         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5645                 return -EINVAL;
5646
5647         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5648                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5649                                              &has_reduced_clock,
5650                                              &reduced_clock);
5651                 if (!ok) {
5652                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5653                         return -EINVAL;
5654                 }
5655         }
5656
5657         /* Ensure that the cursor is valid for the new mode before changing... */
5658         intel_crtc_update_cursor(crtc, true);
5659
5660         /* determine panel color depth */
5661         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5662                                               adjusted_mode);
5663         if (is_lvds && dev_priv->lvds_dither)
5664                 dither = true;
5665
5666         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5667         drm_mode_debug_printmodeline(mode);
5668
5669         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5670                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5671                 if (has_reduced_clock)
5672                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5673                               reduced_clock.m2;
5674
5675                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5676                                              fp);
5677
5678                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5679                  * own on pre-Haswell/LPT generation */
5680                 if (!is_cpu_edp) {
5681                         struct intel_pch_pll *pll;
5682
5683                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5684                         if (pll == NULL) {
5685                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5686                                                  pipe);
5687                                 return -EINVAL;
5688                         }
5689                 } else
5690                         intel_put_pch_pll(intel_crtc);
5691
5692                 /* The LVDS pin pair needs to be on before the DPLLs are
5693                  * enabled.  This is an exception to the general rule that
5694                  * mode_set doesn't turn things on.
5695                  */
5696                 if (is_lvds) {
5697                         temp = I915_READ(PCH_LVDS);
5698                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5699                         if (HAS_PCH_CPT(dev)) {
5700                                 temp &= ~PORT_TRANS_SEL_MASK;
5701                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5702                         } else {
5703                                 if (pipe == 1)
5704                                         temp |= LVDS_PIPEB_SELECT;
5705                                 else
5706                                         temp &= ~LVDS_PIPEB_SELECT;
5707                         }
5708
5709                         /* set the corresponsding LVDS_BORDER bit */
5710                         temp |= dev_priv->lvds_border_bits;
5711                         /* Set the B0-B3 data pairs corresponding to whether
5712                          * we're going to set the DPLLs for dual-channel mode or
5713                          * not.
5714                          */
5715                         if (clock.p2 == 7)
5716                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5717                         else
5718                                 temp &= ~(LVDS_B0B3_POWER_UP |
5719                                           LVDS_CLKB_POWER_UP);
5720
5721                         /* It would be nice to set 24 vs 18-bit mode
5722                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5723                          * look more thoroughly into how panels behave in the
5724                          * two modes.
5725                          */
5726                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5727                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5728                                 temp |= LVDS_HSYNC_POLARITY;
5729                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5730                                 temp |= LVDS_VSYNC_POLARITY;
5731                         I915_WRITE(PCH_LVDS, temp);
5732                 }
5733         }
5734
5735         if (is_dp && !is_cpu_edp) {
5736                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5737         } else {
5738                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5739                         /* For non-DP output, clear any trans DP clock recovery
5740                          * setting.*/
5741                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5742                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5743                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5744                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5745                 }
5746         }
5747
5748         intel_crtc->lowfreq_avail = false;
5749         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5750                 if (intel_crtc->pch_pll) {
5751                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5752
5753                         /* Wait for the clocks to stabilize. */
5754                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5755                         udelay(150);
5756
5757                         /* The pixel multiplier can only be updated once the
5758                          * DPLL is enabled and the clocks are stable.
5759                          *
5760                          * So write it again.
5761                          */
5762                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5763                 }
5764
5765                 if (intel_crtc->pch_pll) {
5766                         if (is_lvds && has_reduced_clock && i915_powersave) {
5767                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5768                                 intel_crtc->lowfreq_avail = true;
5769                         } else {
5770                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5771                         }
5772                 }
5773         }
5774
5775         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5776
5777         if (!is_dp || is_cpu_edp)
5778                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5779
5780         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5781                 if (is_cpu_edp)
5782                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5783
5784         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5785
5786         /* Set up the display plane register */
5787         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5788         POSTING_READ(DSPCNTR(plane));
5789
5790         ret = intel_pipe_set_base(crtc, x, y, fb);
5791
5792         intel_update_watermarks(dev);
5793
5794         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5795
5796         return ret;
5797 }
5798
5799 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5800                                struct drm_display_mode *mode,
5801                                struct drm_display_mode *adjusted_mode,
5802                                int x, int y,
5803                                struct drm_framebuffer *fb)
5804 {
5805         struct drm_device *dev = crtc->dev;
5806         struct drm_i915_private *dev_priv = dev->dev_private;
5807         struct drm_encoder_helper_funcs *encoder_funcs;
5808         struct intel_encoder *encoder;
5809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5810         int pipe = intel_crtc->pipe;
5811         int ret;
5812
5813         drm_vblank_pre_modeset(dev, pipe);
5814
5815         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5816                                               x, y, fb);
5817         drm_vblank_post_modeset(dev, pipe);
5818
5819         if (ret != 0)
5820                 return ret;
5821
5822         for_each_encoder_on_crtc(dev, crtc, encoder) {
5823                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5824                         encoder->base.base.id,
5825                         drm_get_encoder_name(&encoder->base),
5826                         mode->base.id, mode->name);
5827                 encoder_funcs = encoder->base.helper_private;
5828                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5829         }
5830
5831         return 0;
5832 }
5833
5834 static bool intel_eld_uptodate(struct drm_connector *connector,
5835                                int reg_eldv, uint32_t bits_eldv,
5836                                int reg_elda, uint32_t bits_elda,
5837                                int reg_edid)
5838 {
5839         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5840         uint8_t *eld = connector->eld;
5841         uint32_t i;
5842
5843         i = I915_READ(reg_eldv);
5844         i &= bits_eldv;
5845
5846         if (!eld[0])
5847                 return !i;
5848
5849         if (!i)
5850                 return false;
5851
5852         i = I915_READ(reg_elda);
5853         i &= ~bits_elda;
5854         I915_WRITE(reg_elda, i);
5855
5856         for (i = 0; i < eld[2]; i++)
5857                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5858                         return false;
5859
5860         return true;
5861 }
5862
5863 static void g4x_write_eld(struct drm_connector *connector,
5864                           struct drm_crtc *crtc)
5865 {
5866         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5867         uint8_t *eld = connector->eld;
5868         uint32_t eldv;
5869         uint32_t len;
5870         uint32_t i;
5871
5872         i = I915_READ(G4X_AUD_VID_DID);
5873
5874         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5875                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5876         else
5877                 eldv = G4X_ELDV_DEVCTG;
5878
5879         if (intel_eld_uptodate(connector,
5880                                G4X_AUD_CNTL_ST, eldv,
5881                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5882                                G4X_HDMIW_HDMIEDID))
5883                 return;
5884
5885         i = I915_READ(G4X_AUD_CNTL_ST);
5886         i &= ~(eldv | G4X_ELD_ADDR);
5887         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5888         I915_WRITE(G4X_AUD_CNTL_ST, i);
5889
5890         if (!eld[0])
5891                 return;
5892
5893         len = min_t(uint8_t, eld[2], len);
5894         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5895         for (i = 0; i < len; i++)
5896                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5897
5898         i = I915_READ(G4X_AUD_CNTL_ST);
5899         i |= eldv;
5900         I915_WRITE(G4X_AUD_CNTL_ST, i);
5901 }
5902
5903 static void haswell_write_eld(struct drm_connector *connector,
5904                                      struct drm_crtc *crtc)
5905 {
5906         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5907         uint8_t *eld = connector->eld;
5908         struct drm_device *dev = crtc->dev;
5909         uint32_t eldv;
5910         uint32_t i;
5911         int len;
5912         int pipe = to_intel_crtc(crtc)->pipe;
5913         int tmp;
5914
5915         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5916         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5917         int aud_config = HSW_AUD_CFG(pipe);
5918         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5919
5920
5921         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5922
5923         /* Audio output enable */
5924         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5925         tmp = I915_READ(aud_cntrl_st2);
5926         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5927         I915_WRITE(aud_cntrl_st2, tmp);
5928
5929         /* Wait for 1 vertical blank */
5930         intel_wait_for_vblank(dev, pipe);
5931
5932         /* Set ELD valid state */
5933         tmp = I915_READ(aud_cntrl_st2);
5934         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5935         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5936         I915_WRITE(aud_cntrl_st2, tmp);
5937         tmp = I915_READ(aud_cntrl_st2);
5938         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5939
5940         /* Enable HDMI mode */
5941         tmp = I915_READ(aud_config);
5942         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5943         /* clear N_programing_enable and N_value_index */
5944         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5945         I915_WRITE(aud_config, tmp);
5946
5947         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5948
5949         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5950
5951         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5952                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5953                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5954                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5955         } else
5956                 I915_WRITE(aud_config, 0);
5957
5958         if (intel_eld_uptodate(connector,
5959                                aud_cntrl_st2, eldv,
5960                                aud_cntl_st, IBX_ELD_ADDRESS,
5961                                hdmiw_hdmiedid))
5962                 return;
5963
5964         i = I915_READ(aud_cntrl_st2);
5965         i &= ~eldv;
5966         I915_WRITE(aud_cntrl_st2, i);
5967
5968         if (!eld[0])
5969                 return;
5970
5971         i = I915_READ(aud_cntl_st);
5972         i &= ~IBX_ELD_ADDRESS;
5973         I915_WRITE(aud_cntl_st, i);
5974         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5975         DRM_DEBUG_DRIVER("port num:%d\n", i);
5976
5977         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5978         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5979         for (i = 0; i < len; i++)
5980                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5981
5982         i = I915_READ(aud_cntrl_st2);
5983         i |= eldv;
5984         I915_WRITE(aud_cntrl_st2, i);
5985
5986 }
5987
5988 static void ironlake_write_eld(struct drm_connector *connector,
5989                                      struct drm_crtc *crtc)
5990 {
5991         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5992         uint8_t *eld = connector->eld;
5993         uint32_t eldv;
5994         uint32_t i;
5995         int len;
5996         int hdmiw_hdmiedid;
5997         int aud_config;
5998         int aud_cntl_st;
5999         int aud_cntrl_st2;
6000         int pipe = to_intel_crtc(crtc)->pipe;
6001
6002         if (HAS_PCH_IBX(connector->dev)) {
6003                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6004                 aud_config = IBX_AUD_CFG(pipe);
6005                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6006                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6007         } else {
6008                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6009                 aud_config = CPT_AUD_CFG(pipe);
6010                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6011                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6012         }
6013
6014         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6015
6016         i = I915_READ(aud_cntl_st);
6017         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6018         if (!i) {
6019                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6020                 /* operate blindly on all ports */
6021                 eldv = IBX_ELD_VALIDB;
6022                 eldv |= IBX_ELD_VALIDB << 4;
6023                 eldv |= IBX_ELD_VALIDB << 8;
6024         } else {
6025                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6026                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6027         }
6028
6029         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6030                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6031                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6032                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6033         } else
6034                 I915_WRITE(aud_config, 0);
6035
6036         if (intel_eld_uptodate(connector,
6037                                aud_cntrl_st2, eldv,
6038                                aud_cntl_st, IBX_ELD_ADDRESS,
6039                                hdmiw_hdmiedid))
6040                 return;
6041
6042         i = I915_READ(aud_cntrl_st2);
6043         i &= ~eldv;
6044         I915_WRITE(aud_cntrl_st2, i);
6045
6046         if (!eld[0])
6047                 return;
6048
6049         i = I915_READ(aud_cntl_st);
6050         i &= ~IBX_ELD_ADDRESS;
6051         I915_WRITE(aud_cntl_st, i);
6052
6053         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6054         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6055         for (i = 0; i < len; i++)
6056                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6057
6058         i = I915_READ(aud_cntrl_st2);
6059         i |= eldv;
6060         I915_WRITE(aud_cntrl_st2, i);
6061 }
6062
6063 void intel_write_eld(struct drm_encoder *encoder,
6064                      struct drm_display_mode *mode)
6065 {
6066         struct drm_crtc *crtc = encoder->crtc;
6067         struct drm_connector *connector;
6068         struct drm_device *dev = encoder->dev;
6069         struct drm_i915_private *dev_priv = dev->dev_private;
6070
6071         connector = drm_select_eld(encoder, mode);
6072         if (!connector)
6073                 return;
6074
6075         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6076                          connector->base.id,
6077                          drm_get_connector_name(connector),
6078                          connector->encoder->base.id,
6079                          drm_get_encoder_name(connector->encoder));
6080
6081         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6082
6083         if (dev_priv->display.write_eld)
6084                 dev_priv->display.write_eld(connector, crtc);
6085 }
6086
6087 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6088 void intel_crtc_load_lut(struct drm_crtc *crtc)
6089 {
6090         struct drm_device *dev = crtc->dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6093         int palreg = PALETTE(intel_crtc->pipe);
6094         int i;
6095
6096         /* The clocks have to be on to load the palette. */
6097         if (!crtc->enabled || !intel_crtc->active)
6098                 return;
6099
6100         /* use legacy palette for Ironlake */
6101         if (HAS_PCH_SPLIT(dev))
6102                 palreg = LGC_PALETTE(intel_crtc->pipe);
6103
6104         for (i = 0; i < 256; i++) {
6105                 I915_WRITE(palreg + 4 * i,
6106                            (intel_crtc->lut_r[i] << 16) |
6107                            (intel_crtc->lut_g[i] << 8) |
6108                            intel_crtc->lut_b[i]);
6109         }
6110 }
6111
6112 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6113 {
6114         struct drm_device *dev = crtc->dev;
6115         struct drm_i915_private *dev_priv = dev->dev_private;
6116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6117         bool visible = base != 0;
6118         u32 cntl;
6119
6120         if (intel_crtc->cursor_visible == visible)
6121                 return;
6122
6123         cntl = I915_READ(_CURACNTR);
6124         if (visible) {
6125                 /* On these chipsets we can only modify the base whilst
6126                  * the cursor is disabled.
6127                  */
6128                 I915_WRITE(_CURABASE, base);
6129
6130                 cntl &= ~(CURSOR_FORMAT_MASK);
6131                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6132                 cntl |= CURSOR_ENABLE |
6133                         CURSOR_GAMMA_ENABLE |
6134                         CURSOR_FORMAT_ARGB;
6135         } else
6136                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6137         I915_WRITE(_CURACNTR, cntl);
6138
6139         intel_crtc->cursor_visible = visible;
6140 }
6141
6142 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6143 {
6144         struct drm_device *dev = crtc->dev;
6145         struct drm_i915_private *dev_priv = dev->dev_private;
6146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6147         int pipe = intel_crtc->pipe;
6148         bool visible = base != 0;
6149
6150         if (intel_crtc->cursor_visible != visible) {
6151                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6152                 if (base) {
6153                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6154                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6155                         cntl |= pipe << 28; /* Connect to correct pipe */
6156                 } else {
6157                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6158                         cntl |= CURSOR_MODE_DISABLE;
6159                 }
6160                 I915_WRITE(CURCNTR(pipe), cntl);
6161
6162                 intel_crtc->cursor_visible = visible;
6163         }
6164         /* and commit changes on next vblank */
6165         I915_WRITE(CURBASE(pipe), base);
6166 }
6167
6168 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6169 {
6170         struct drm_device *dev = crtc->dev;
6171         struct drm_i915_private *dev_priv = dev->dev_private;
6172         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6173         int pipe = intel_crtc->pipe;
6174         bool visible = base != 0;
6175
6176         if (intel_crtc->cursor_visible != visible) {
6177                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6178                 if (base) {
6179                         cntl &= ~CURSOR_MODE;
6180                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6181                 } else {
6182                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6183                         cntl |= CURSOR_MODE_DISABLE;
6184                 }
6185                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6186
6187                 intel_crtc->cursor_visible = visible;
6188         }
6189         /* and commit changes on next vblank */
6190         I915_WRITE(CURBASE_IVB(pipe), base);
6191 }
6192
6193 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6194 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6195                                      bool on)
6196 {
6197         struct drm_device *dev = crtc->dev;
6198         struct drm_i915_private *dev_priv = dev->dev_private;
6199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6200         int pipe = intel_crtc->pipe;
6201         int x = intel_crtc->cursor_x;
6202         int y = intel_crtc->cursor_y;
6203         u32 base, pos;
6204         bool visible;
6205
6206         pos = 0;
6207
6208         if (on && crtc->enabled && crtc->fb) {
6209                 base = intel_crtc->cursor_addr;
6210                 if (x > (int) crtc->fb->width)
6211                         base = 0;
6212
6213                 if (y > (int) crtc->fb->height)
6214                         base = 0;
6215         } else
6216                 base = 0;
6217
6218         if (x < 0) {
6219                 if (x + intel_crtc->cursor_width < 0)
6220                         base = 0;
6221
6222                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6223                 x = -x;
6224         }
6225         pos |= x << CURSOR_X_SHIFT;
6226
6227         if (y < 0) {
6228                 if (y + intel_crtc->cursor_height < 0)
6229                         base = 0;
6230
6231                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6232                 y = -y;
6233         }
6234         pos |= y << CURSOR_Y_SHIFT;
6235
6236         visible = base != 0;
6237         if (!visible && !intel_crtc->cursor_visible)
6238                 return;
6239
6240         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6241                 I915_WRITE(CURPOS_IVB(pipe), pos);
6242                 ivb_update_cursor(crtc, base);
6243         } else {
6244                 I915_WRITE(CURPOS(pipe), pos);
6245                 if (IS_845G(dev) || IS_I865G(dev))
6246                         i845_update_cursor(crtc, base);
6247                 else
6248                         i9xx_update_cursor(crtc, base);
6249         }
6250 }
6251
6252 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6253                                  struct drm_file *file,
6254                                  uint32_t handle,
6255                                  uint32_t width, uint32_t height)
6256 {
6257         struct drm_device *dev = crtc->dev;
6258         struct drm_i915_private *dev_priv = dev->dev_private;
6259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260         struct drm_i915_gem_object *obj;
6261         uint32_t addr;
6262         int ret;
6263
6264         /* if we want to turn off the cursor ignore width and height */
6265         if (!handle) {
6266                 DRM_DEBUG_KMS("cursor off\n");
6267                 addr = 0;
6268                 obj = NULL;
6269                 mutex_lock(&dev->struct_mutex);
6270                 goto finish;
6271         }
6272
6273         /* Currently we only support 64x64 cursors */
6274         if (width != 64 || height != 64) {
6275                 DRM_ERROR("we currently only support 64x64 cursors\n");
6276                 return -EINVAL;
6277         }
6278
6279         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6280         if (&obj->base == NULL)
6281                 return -ENOENT;
6282
6283         if (obj->base.size < width * height * 4) {
6284                 DRM_ERROR("buffer is to small\n");
6285                 ret = -ENOMEM;
6286                 goto fail;
6287         }
6288
6289         /* we only need to pin inside GTT if cursor is non-phy */
6290         mutex_lock(&dev->struct_mutex);
6291         if (!dev_priv->info->cursor_needs_physical) {
6292                 if (obj->tiling_mode) {
6293                         DRM_ERROR("cursor cannot be tiled\n");
6294                         ret = -EINVAL;
6295                         goto fail_locked;
6296                 }
6297
6298                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6299                 if (ret) {
6300                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6301                         goto fail_locked;
6302                 }
6303
6304                 ret = i915_gem_object_put_fence(obj);
6305                 if (ret) {
6306                         DRM_ERROR("failed to release fence for cursor");
6307                         goto fail_unpin;
6308                 }
6309
6310                 addr = obj->gtt_offset;
6311         } else {
6312                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6313                 ret = i915_gem_attach_phys_object(dev, obj,
6314                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6315                                                   align);
6316                 if (ret) {
6317                         DRM_ERROR("failed to attach phys object\n");
6318                         goto fail_locked;
6319                 }
6320                 addr = obj->phys_obj->handle->busaddr;
6321         }
6322
6323         if (IS_GEN2(dev))
6324                 I915_WRITE(CURSIZE, (height << 12) | width);
6325
6326  finish:
6327         if (intel_crtc->cursor_bo) {
6328                 if (dev_priv->info->cursor_needs_physical) {
6329                         if (intel_crtc->cursor_bo != obj)
6330                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6331                 } else
6332                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6333                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6334         }
6335
6336         mutex_unlock(&dev->struct_mutex);
6337
6338         intel_crtc->cursor_addr = addr;
6339         intel_crtc->cursor_bo = obj;
6340         intel_crtc->cursor_width = width;
6341         intel_crtc->cursor_height = height;
6342
6343         intel_crtc_update_cursor(crtc, true);
6344
6345         return 0;
6346 fail_unpin:
6347         i915_gem_object_unpin(obj);
6348 fail_locked:
6349         mutex_unlock(&dev->struct_mutex);
6350 fail:
6351         drm_gem_object_unreference_unlocked(&obj->base);
6352         return ret;
6353 }
6354
6355 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6356 {
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358
6359         intel_crtc->cursor_x = x;
6360         intel_crtc->cursor_y = y;
6361
6362         intel_crtc_update_cursor(crtc, true);
6363
6364         return 0;
6365 }
6366
6367 /** Sets the color ramps on behalf of RandR */
6368 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6369                                  u16 blue, int regno)
6370 {
6371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6372
6373         intel_crtc->lut_r[regno] = red >> 8;
6374         intel_crtc->lut_g[regno] = green >> 8;
6375         intel_crtc->lut_b[regno] = blue >> 8;
6376 }
6377
6378 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6379                              u16 *blue, int regno)
6380 {
6381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382
6383         *red = intel_crtc->lut_r[regno] << 8;
6384         *green = intel_crtc->lut_g[regno] << 8;
6385         *blue = intel_crtc->lut_b[regno] << 8;
6386 }
6387
6388 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6389                                  u16 *blue, uint32_t start, uint32_t size)
6390 {
6391         int end = (start + size > 256) ? 256 : start + size, i;
6392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6393
6394         for (i = start; i < end; i++) {
6395                 intel_crtc->lut_r[i] = red[i] >> 8;
6396                 intel_crtc->lut_g[i] = green[i] >> 8;
6397                 intel_crtc->lut_b[i] = blue[i] >> 8;
6398         }
6399
6400         intel_crtc_load_lut(crtc);
6401 }
6402
6403 /**
6404  * Get a pipe with a simple mode set on it for doing load-based monitor
6405  * detection.
6406  *
6407  * It will be up to the load-detect code to adjust the pipe as appropriate for
6408  * its requirements.  The pipe will be connected to no other encoders.
6409  *
6410  * Currently this code will only succeed if there is a pipe with no encoders
6411  * configured for it.  In the future, it could choose to temporarily disable
6412  * some outputs to free up a pipe for its use.
6413  *
6414  * \return crtc, or NULL if no pipes are available.
6415  */
6416
6417 /* VESA 640x480x72Hz mode to set on the pipe */
6418 static struct drm_display_mode load_detect_mode = {
6419         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6420                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6421 };
6422
6423 static struct drm_framebuffer *
6424 intel_framebuffer_create(struct drm_device *dev,
6425                          struct drm_mode_fb_cmd2 *mode_cmd,
6426                          struct drm_i915_gem_object *obj)
6427 {
6428         struct intel_framebuffer *intel_fb;
6429         int ret;
6430
6431         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6432         if (!intel_fb) {
6433                 drm_gem_object_unreference_unlocked(&obj->base);
6434                 return ERR_PTR(-ENOMEM);
6435         }
6436
6437         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6438         if (ret) {
6439                 drm_gem_object_unreference_unlocked(&obj->base);
6440                 kfree(intel_fb);
6441                 return ERR_PTR(ret);
6442         }
6443
6444         return &intel_fb->base;
6445 }
6446
6447 static u32
6448 intel_framebuffer_pitch_for_width(int width, int bpp)
6449 {
6450         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6451         return ALIGN(pitch, 64);
6452 }
6453
6454 static u32
6455 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6456 {
6457         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6458         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6459 }
6460
6461 static struct drm_framebuffer *
6462 intel_framebuffer_create_for_mode(struct drm_device *dev,
6463                                   struct drm_display_mode *mode,
6464                                   int depth, int bpp)
6465 {
6466         struct drm_i915_gem_object *obj;
6467         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6468
6469         obj = i915_gem_alloc_object(dev,
6470                                     intel_framebuffer_size_for_mode(mode, bpp));
6471         if (obj == NULL)
6472                 return ERR_PTR(-ENOMEM);
6473
6474         mode_cmd.width = mode->hdisplay;
6475         mode_cmd.height = mode->vdisplay;
6476         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6477                                                                 bpp);
6478         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6479
6480         return intel_framebuffer_create(dev, &mode_cmd, obj);
6481 }
6482
6483 static struct drm_framebuffer *
6484 mode_fits_in_fbdev(struct drm_device *dev,
6485                    struct drm_display_mode *mode)
6486 {
6487         struct drm_i915_private *dev_priv = dev->dev_private;
6488         struct drm_i915_gem_object *obj;
6489         struct drm_framebuffer *fb;
6490
6491         if (dev_priv->fbdev == NULL)
6492                 return NULL;
6493
6494         obj = dev_priv->fbdev->ifb.obj;
6495         if (obj == NULL)
6496                 return NULL;
6497
6498         fb = &dev_priv->fbdev->ifb.base;
6499         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6500                                                                fb->bits_per_pixel))
6501                 return NULL;
6502
6503         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6504                 return NULL;
6505
6506         return fb;
6507 }
6508
6509 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6510                                 struct drm_display_mode *mode,
6511                                 struct intel_load_detect_pipe *old)
6512 {
6513         struct intel_crtc *intel_crtc;
6514         struct intel_encoder *intel_encoder =
6515                 intel_attached_encoder(connector);
6516         struct drm_crtc *possible_crtc;
6517         struct drm_encoder *encoder = &intel_encoder->base;
6518         struct drm_crtc *crtc = NULL;
6519         struct drm_device *dev = encoder->dev;
6520         struct drm_framebuffer *fb;
6521         int i = -1;
6522
6523         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6524                       connector->base.id, drm_get_connector_name(connector),
6525                       encoder->base.id, drm_get_encoder_name(encoder));
6526
6527         /*
6528          * Algorithm gets a little messy:
6529          *
6530          *   - if the connector already has an assigned crtc, use it (but make
6531          *     sure it's on first)
6532          *
6533          *   - try to find the first unused crtc that can drive this connector,
6534          *     and use that if we find one
6535          */
6536
6537         /* See if we already have a CRTC for this connector */
6538         if (encoder->crtc) {
6539                 crtc = encoder->crtc;
6540
6541                 old->dpms_mode = connector->dpms;
6542                 old->load_detect_temp = false;
6543
6544                 /* Make sure the crtc and connector are running */
6545                 if (connector->dpms != DRM_MODE_DPMS_ON)
6546                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6547
6548                 return true;
6549         }
6550
6551         /* Find an unused one (if possible) */
6552         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6553                 i++;
6554                 if (!(encoder->possible_crtcs & (1 << i)))
6555                         continue;
6556                 if (!possible_crtc->enabled) {
6557                         crtc = possible_crtc;
6558                         break;
6559                 }
6560         }
6561
6562         /*
6563          * If we didn't find an unused CRTC, don't use any.
6564          */
6565         if (!crtc) {
6566                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6567                 return false;
6568         }
6569
6570         intel_encoder->new_crtc = to_intel_crtc(crtc);
6571         to_intel_connector(connector)->new_encoder = intel_encoder;
6572
6573         intel_crtc = to_intel_crtc(crtc);
6574         old->dpms_mode = connector->dpms;
6575         old->load_detect_temp = true;
6576         old->release_fb = NULL;
6577
6578         if (!mode)
6579                 mode = &load_detect_mode;
6580
6581         /* We need a framebuffer large enough to accommodate all accesses
6582          * that the plane may generate whilst we perform load detection.
6583          * We can not rely on the fbcon either being present (we get called
6584          * during its initialisation to detect all boot displays, or it may
6585          * not even exist) or that it is large enough to satisfy the
6586          * requested mode.
6587          */
6588         fb = mode_fits_in_fbdev(dev, mode);
6589         if (fb == NULL) {
6590                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6591                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6592                 old->release_fb = fb;
6593         } else
6594                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6595         if (IS_ERR(fb)) {
6596                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6597                 return false;
6598         }
6599
6600         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6601                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6602                 if (old->release_fb)
6603                         old->release_fb->funcs->destroy(old->release_fb);
6604                 return false;
6605         }
6606
6607         /* let the connector get through one full cycle before testing */
6608         intel_wait_for_vblank(dev, intel_crtc->pipe);
6609         return true;
6610 }
6611
6612 void intel_release_load_detect_pipe(struct drm_connector *connector,
6613                                     struct intel_load_detect_pipe *old)
6614 {
6615         struct intel_encoder *intel_encoder =
6616                 intel_attached_encoder(connector);
6617         struct drm_encoder *encoder = &intel_encoder->base;
6618
6619         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6620                       connector->base.id, drm_get_connector_name(connector),
6621                       encoder->base.id, drm_get_encoder_name(encoder));
6622
6623         if (old->load_detect_temp) {
6624                 struct drm_crtc *crtc = encoder->crtc;
6625
6626                 to_intel_connector(connector)->new_encoder = NULL;
6627                 intel_encoder->new_crtc = NULL;
6628                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6629
6630                 if (old->release_fb)
6631                         old->release_fb->funcs->destroy(old->release_fb);
6632
6633                 return;
6634         }
6635
6636         /* Switch crtc and encoder back off if necessary */
6637         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6638                 connector->funcs->dpms(connector, old->dpms_mode);
6639 }
6640
6641 /* Returns the clock of the currently programmed mode of the given pipe. */
6642 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6643 {
6644         struct drm_i915_private *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         int pipe = intel_crtc->pipe;
6647         u32 dpll = I915_READ(DPLL(pipe));
6648         u32 fp;
6649         intel_clock_t clock;
6650
6651         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6652                 fp = I915_READ(FP0(pipe));
6653         else
6654                 fp = I915_READ(FP1(pipe));
6655
6656         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6657         if (IS_PINEVIEW(dev)) {
6658                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6659                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6660         } else {
6661                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6662                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6663         }
6664
6665         if (!IS_GEN2(dev)) {
6666                 if (IS_PINEVIEW(dev))
6667                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6668                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6669                 else
6670                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6671                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6672
6673                 switch (dpll & DPLL_MODE_MASK) {
6674                 case DPLLB_MODE_DAC_SERIAL:
6675                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6676                                 5 : 10;
6677                         break;
6678                 case DPLLB_MODE_LVDS:
6679                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6680                                 7 : 14;
6681                         break;
6682                 default:
6683                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6684                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6685                         return 0;
6686                 }
6687
6688                 /* XXX: Handle the 100Mhz refclk */
6689                 intel_clock(dev, 96000, &clock);
6690         } else {
6691                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6692
6693                 if (is_lvds) {
6694                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6695                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6696                         clock.p2 = 14;
6697
6698                         if ((dpll & PLL_REF_INPUT_MASK) ==
6699                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6700                                 /* XXX: might not be 66MHz */
6701                                 intel_clock(dev, 66000, &clock);
6702                         } else
6703                                 intel_clock(dev, 48000, &clock);
6704                 } else {
6705                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6706                                 clock.p1 = 2;
6707                         else {
6708                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6709                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6710                         }
6711                         if (dpll & PLL_P2_DIVIDE_BY_4)
6712                                 clock.p2 = 4;
6713                         else
6714                                 clock.p2 = 2;
6715
6716                         intel_clock(dev, 48000, &clock);
6717                 }
6718         }
6719
6720         /* XXX: It would be nice to validate the clocks, but we can't reuse
6721          * i830PllIsValid() because it relies on the xf86_config connector
6722          * configuration being accurate, which it isn't necessarily.
6723          */
6724
6725         return clock.dot;
6726 }
6727
6728 /** Returns the currently programmed mode of the given pipe. */
6729 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6730                                              struct drm_crtc *crtc)
6731 {
6732         struct drm_i915_private *dev_priv = dev->dev_private;
6733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6734         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6735         struct drm_display_mode *mode;
6736         int htot = I915_READ(HTOTAL(cpu_transcoder));
6737         int hsync = I915_READ(HSYNC(cpu_transcoder));
6738         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6739         int vsync = I915_READ(VSYNC(cpu_transcoder));
6740
6741         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6742         if (!mode)
6743                 return NULL;
6744
6745         mode->clock = intel_crtc_clock_get(dev, crtc);
6746         mode->hdisplay = (htot & 0xffff) + 1;
6747         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6748         mode->hsync_start = (hsync & 0xffff) + 1;
6749         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6750         mode->vdisplay = (vtot & 0xffff) + 1;
6751         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6752         mode->vsync_start = (vsync & 0xffff) + 1;
6753         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6754
6755         drm_mode_set_name(mode);
6756
6757         return mode;
6758 }
6759
6760 static void intel_increase_pllclock(struct drm_crtc *crtc)
6761 {
6762         struct drm_device *dev = crtc->dev;
6763         drm_i915_private_t *dev_priv = dev->dev_private;
6764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6765         int pipe = intel_crtc->pipe;
6766         int dpll_reg = DPLL(pipe);
6767         int dpll;
6768
6769         if (HAS_PCH_SPLIT(dev))
6770                 return;
6771
6772         if (!dev_priv->lvds_downclock_avail)
6773                 return;
6774
6775         dpll = I915_READ(dpll_reg);
6776         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6777                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6778
6779                 assert_panel_unlocked(dev_priv, pipe);
6780
6781                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6782                 I915_WRITE(dpll_reg, dpll);
6783                 intel_wait_for_vblank(dev, pipe);
6784
6785                 dpll = I915_READ(dpll_reg);
6786                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6787                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6788         }
6789 }
6790
6791 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6792 {
6793         struct drm_device *dev = crtc->dev;
6794         drm_i915_private_t *dev_priv = dev->dev_private;
6795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6796
6797         if (HAS_PCH_SPLIT(dev))
6798                 return;
6799
6800         if (!dev_priv->lvds_downclock_avail)
6801                 return;
6802
6803         /*
6804          * Since this is called by a timer, we should never get here in
6805          * the manual case.
6806          */
6807         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6808                 int pipe = intel_crtc->pipe;
6809                 int dpll_reg = DPLL(pipe);
6810                 int dpll;
6811
6812                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6813
6814                 assert_panel_unlocked(dev_priv, pipe);
6815
6816                 dpll = I915_READ(dpll_reg);
6817                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6818                 I915_WRITE(dpll_reg, dpll);
6819                 intel_wait_for_vblank(dev, pipe);
6820                 dpll = I915_READ(dpll_reg);
6821                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6822                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6823         }
6824
6825 }
6826
6827 void intel_mark_busy(struct drm_device *dev)
6828 {
6829         i915_update_gfx_val(dev->dev_private);
6830 }
6831
6832 void intel_mark_idle(struct drm_device *dev)
6833 {
6834 }
6835
6836 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6837 {
6838         struct drm_device *dev = obj->base.dev;
6839         struct drm_crtc *crtc;
6840
6841         if (!i915_powersave)
6842                 return;
6843
6844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6845                 if (!crtc->fb)
6846                         continue;
6847
6848                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6849                         intel_increase_pllclock(crtc);
6850         }
6851 }
6852
6853 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6854 {
6855         struct drm_device *dev = obj->base.dev;
6856         struct drm_crtc *crtc;
6857
6858         if (!i915_powersave)
6859                 return;
6860
6861         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6862                 if (!crtc->fb)
6863                         continue;
6864
6865                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6866                         intel_decrease_pllclock(crtc);
6867         }
6868 }
6869
6870 static void intel_crtc_destroy(struct drm_crtc *crtc)
6871 {
6872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6873         struct drm_device *dev = crtc->dev;
6874         struct intel_unpin_work *work;
6875         unsigned long flags;
6876
6877         spin_lock_irqsave(&dev->event_lock, flags);
6878         work = intel_crtc->unpin_work;
6879         intel_crtc->unpin_work = NULL;
6880         spin_unlock_irqrestore(&dev->event_lock, flags);
6881
6882         if (work) {
6883                 cancel_work_sync(&work->work);
6884                 kfree(work);
6885         }
6886
6887         drm_crtc_cleanup(crtc);
6888
6889         kfree(intel_crtc);
6890 }
6891
6892 static void intel_unpin_work_fn(struct work_struct *__work)
6893 {
6894         struct intel_unpin_work *work =
6895                 container_of(__work, struct intel_unpin_work, work);
6896         struct drm_device *dev = work->crtc->dev;
6897
6898         mutex_lock(&dev->struct_mutex);
6899         intel_unpin_fb_obj(work->old_fb_obj);
6900         drm_gem_object_unreference(&work->pending_flip_obj->base);
6901         drm_gem_object_unreference(&work->old_fb_obj->base);
6902
6903         intel_update_fbc(dev);
6904         mutex_unlock(&dev->struct_mutex);
6905
6906         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6907         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6908
6909         kfree(work);
6910 }
6911
6912 static void do_intel_finish_page_flip(struct drm_device *dev,
6913                                       struct drm_crtc *crtc)
6914 {
6915         drm_i915_private_t *dev_priv = dev->dev_private;
6916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6917         struct intel_unpin_work *work;
6918         struct drm_i915_gem_object *obj;
6919         struct drm_pending_vblank_event *e;
6920         struct timeval tvbl;
6921         unsigned long flags;
6922
6923         /* Ignore early vblank irqs */
6924         if (intel_crtc == NULL)
6925                 return;
6926
6927         spin_lock_irqsave(&dev->event_lock, flags);
6928         work = intel_crtc->unpin_work;
6929         if (work == NULL || !work->pending) {
6930                 spin_unlock_irqrestore(&dev->event_lock, flags);
6931                 return;
6932         }
6933
6934         intel_crtc->unpin_work = NULL;
6935
6936         if (work->event) {
6937                 e = work->event;
6938                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6939
6940                 e->event.tv_sec = tvbl.tv_sec;
6941                 e->event.tv_usec = tvbl.tv_usec;
6942
6943                 list_add_tail(&e->base.link,
6944                               &e->base.file_priv->event_list);
6945                 wake_up_interruptible(&e->base.file_priv->event_wait);
6946         }
6947
6948         drm_vblank_put(dev, intel_crtc->pipe);
6949
6950         spin_unlock_irqrestore(&dev->event_lock, flags);
6951
6952         obj = work->old_fb_obj;
6953
6954         atomic_clear_mask(1 << intel_crtc->plane,
6955                           &obj->pending_flip.counter);
6956         wake_up(&dev_priv->pending_flip_queue);
6957
6958         queue_work(dev_priv->wq, &work->work);
6959
6960         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6961 }
6962
6963 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6964 {
6965         drm_i915_private_t *dev_priv = dev->dev_private;
6966         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6967
6968         do_intel_finish_page_flip(dev, crtc);
6969 }
6970
6971 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6972 {
6973         drm_i915_private_t *dev_priv = dev->dev_private;
6974         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6975
6976         do_intel_finish_page_flip(dev, crtc);
6977 }
6978
6979 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6980 {
6981         drm_i915_private_t *dev_priv = dev->dev_private;
6982         struct intel_crtc *intel_crtc =
6983                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6984         unsigned long flags;
6985
6986         spin_lock_irqsave(&dev->event_lock, flags);
6987         if (intel_crtc->unpin_work) {
6988                 if ((++intel_crtc->unpin_work->pending) > 1)
6989                         DRM_ERROR("Prepared flip multiple times\n");
6990         } else {
6991                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6992         }
6993         spin_unlock_irqrestore(&dev->event_lock, flags);
6994 }
6995
6996 static int intel_gen2_queue_flip(struct drm_device *dev,
6997                                  struct drm_crtc *crtc,
6998                                  struct drm_framebuffer *fb,
6999                                  struct drm_i915_gem_object *obj)
7000 {
7001         struct drm_i915_private *dev_priv = dev->dev_private;
7002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7003         u32 flip_mask;
7004         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7005         int ret;
7006
7007         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7008         if (ret)
7009                 goto err;
7010
7011         ret = intel_ring_begin(ring, 6);
7012         if (ret)
7013                 goto err_unpin;
7014
7015         /* Can't queue multiple flips, so wait for the previous
7016          * one to finish before executing the next.
7017          */
7018         if (intel_crtc->plane)
7019                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7020         else
7021                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7022         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7023         intel_ring_emit(ring, MI_NOOP);
7024         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7025                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7026         intel_ring_emit(ring, fb->pitches[0]);
7027         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7028         intel_ring_emit(ring, 0); /* aux display base address, unused */
7029         intel_ring_advance(ring);
7030         return 0;
7031
7032 err_unpin:
7033         intel_unpin_fb_obj(obj);
7034 err:
7035         return ret;
7036 }
7037
7038 static int intel_gen3_queue_flip(struct drm_device *dev,
7039                                  struct drm_crtc *crtc,
7040                                  struct drm_framebuffer *fb,
7041                                  struct drm_i915_gem_object *obj)
7042 {
7043         struct drm_i915_private *dev_priv = dev->dev_private;
7044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7045         u32 flip_mask;
7046         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7047         int ret;
7048
7049         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7050         if (ret)
7051                 goto err;
7052
7053         ret = intel_ring_begin(ring, 6);
7054         if (ret)
7055                 goto err_unpin;
7056
7057         if (intel_crtc->plane)
7058                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7059         else
7060                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7061         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7062         intel_ring_emit(ring, MI_NOOP);
7063         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7064                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7065         intel_ring_emit(ring, fb->pitches[0]);
7066         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7067         intel_ring_emit(ring, MI_NOOP);
7068
7069         intel_ring_advance(ring);
7070         return 0;
7071
7072 err_unpin:
7073         intel_unpin_fb_obj(obj);
7074 err:
7075         return ret;
7076 }
7077
7078 static int intel_gen4_queue_flip(struct drm_device *dev,
7079                                  struct drm_crtc *crtc,
7080                                  struct drm_framebuffer *fb,
7081                                  struct drm_i915_gem_object *obj)
7082 {
7083         struct drm_i915_private *dev_priv = dev->dev_private;
7084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7085         uint32_t pf, pipesrc;
7086         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7087         int ret;
7088
7089         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7090         if (ret)
7091                 goto err;
7092
7093         ret = intel_ring_begin(ring, 4);
7094         if (ret)
7095                 goto err_unpin;
7096
7097         /* i965+ uses the linear or tiled offsets from the
7098          * Display Registers (which do not change across a page-flip)
7099          * so we need only reprogram the base address.
7100          */
7101         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7102                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7103         intel_ring_emit(ring, fb->pitches[0]);
7104         intel_ring_emit(ring,
7105                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7106                         obj->tiling_mode);
7107
7108         /* XXX Enabling the panel-fitter across page-flip is so far
7109          * untested on non-native modes, so ignore it for now.
7110          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7111          */
7112         pf = 0;
7113         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7114         intel_ring_emit(ring, pf | pipesrc);
7115         intel_ring_advance(ring);
7116         return 0;
7117
7118 err_unpin:
7119         intel_unpin_fb_obj(obj);
7120 err:
7121         return ret;
7122 }
7123
7124 static int intel_gen6_queue_flip(struct drm_device *dev,
7125                                  struct drm_crtc *crtc,
7126                                  struct drm_framebuffer *fb,
7127                                  struct drm_i915_gem_object *obj)
7128 {
7129         struct drm_i915_private *dev_priv = dev->dev_private;
7130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7131         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7132         uint32_t pf, pipesrc;
7133         int ret;
7134
7135         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7136         if (ret)
7137                 goto err;
7138
7139         ret = intel_ring_begin(ring, 4);
7140         if (ret)
7141                 goto err_unpin;
7142
7143         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7144                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7145         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7146         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7147
7148         /* Contrary to the suggestions in the documentation,
7149          * "Enable Panel Fitter" does not seem to be required when page
7150          * flipping with a non-native mode, and worse causes a normal
7151          * modeset to fail.
7152          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7153          */
7154         pf = 0;
7155         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7156         intel_ring_emit(ring, pf | pipesrc);
7157         intel_ring_advance(ring);
7158         return 0;
7159
7160 err_unpin:
7161         intel_unpin_fb_obj(obj);
7162 err:
7163         return ret;
7164 }
7165
7166 /*
7167  * On gen7 we currently use the blit ring because (in early silicon at least)
7168  * the render ring doesn't give us interrpts for page flip completion, which
7169  * means clients will hang after the first flip is queued.  Fortunately the
7170  * blit ring generates interrupts properly, so use it instead.
7171  */
7172 static int intel_gen7_queue_flip(struct drm_device *dev,
7173                                  struct drm_crtc *crtc,
7174                                  struct drm_framebuffer *fb,
7175                                  struct drm_i915_gem_object *obj)
7176 {
7177         struct drm_i915_private *dev_priv = dev->dev_private;
7178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7180         uint32_t plane_bit = 0;
7181         int ret;
7182
7183         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7184         if (ret)
7185                 goto err;
7186
7187         switch(intel_crtc->plane) {
7188         case PLANE_A:
7189                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7190                 break;
7191         case PLANE_B:
7192                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7193                 break;
7194         case PLANE_C:
7195                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7196                 break;
7197         default:
7198                 WARN_ONCE(1, "unknown plane in flip command\n");
7199                 ret = -ENODEV;
7200                 goto err_unpin;
7201         }
7202
7203         ret = intel_ring_begin(ring, 4);
7204         if (ret)
7205                 goto err_unpin;
7206
7207         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7208         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7209         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7210         intel_ring_emit(ring, (MI_NOOP));
7211         intel_ring_advance(ring);
7212         return 0;
7213
7214 err_unpin:
7215         intel_unpin_fb_obj(obj);
7216 err:
7217         return ret;
7218 }
7219
7220 static int intel_default_queue_flip(struct drm_device *dev,
7221                                     struct drm_crtc *crtc,
7222                                     struct drm_framebuffer *fb,
7223                                     struct drm_i915_gem_object *obj)
7224 {
7225         return -ENODEV;
7226 }
7227
7228 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7229                                 struct drm_framebuffer *fb,
7230                                 struct drm_pending_vblank_event *event)
7231 {
7232         struct drm_device *dev = crtc->dev;
7233         struct drm_i915_private *dev_priv = dev->dev_private;
7234         struct intel_framebuffer *intel_fb;
7235         struct drm_i915_gem_object *obj;
7236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7237         struct intel_unpin_work *work;
7238         unsigned long flags;
7239         int ret;
7240
7241         /* Can't change pixel format via MI display flips. */
7242         if (fb->pixel_format != crtc->fb->pixel_format)
7243                 return -EINVAL;
7244
7245         /*
7246          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7247          * Note that pitch changes could also affect these register.
7248          */
7249         if (INTEL_INFO(dev)->gen > 3 &&
7250             (fb->offsets[0] != crtc->fb->offsets[0] ||
7251              fb->pitches[0] != crtc->fb->pitches[0]))
7252                 return -EINVAL;
7253
7254         work = kzalloc(sizeof *work, GFP_KERNEL);
7255         if (work == NULL)
7256                 return -ENOMEM;
7257
7258         work->event = event;
7259         work->crtc = crtc;
7260         intel_fb = to_intel_framebuffer(crtc->fb);
7261         work->old_fb_obj = intel_fb->obj;
7262         INIT_WORK(&work->work, intel_unpin_work_fn);
7263
7264         ret = drm_vblank_get(dev, intel_crtc->pipe);
7265         if (ret)
7266                 goto free_work;
7267
7268         /* We borrow the event spin lock for protecting unpin_work */
7269         spin_lock_irqsave(&dev->event_lock, flags);
7270         if (intel_crtc->unpin_work) {
7271                 spin_unlock_irqrestore(&dev->event_lock, flags);
7272                 kfree(work);
7273                 drm_vblank_put(dev, intel_crtc->pipe);
7274
7275                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7276                 return -EBUSY;
7277         }
7278         intel_crtc->unpin_work = work;
7279         spin_unlock_irqrestore(&dev->event_lock, flags);
7280
7281         intel_fb = to_intel_framebuffer(fb);
7282         obj = intel_fb->obj;
7283
7284         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7285                 flush_workqueue(dev_priv->wq);
7286
7287         ret = i915_mutex_lock_interruptible(dev);
7288         if (ret)
7289                 goto cleanup;
7290
7291         /* Reference the objects for the scheduled work. */
7292         drm_gem_object_reference(&work->old_fb_obj->base);
7293         drm_gem_object_reference(&obj->base);
7294
7295         crtc->fb = fb;
7296
7297         work->pending_flip_obj = obj;
7298
7299         work->enable_stall_check = true;
7300
7301         /* Block clients from rendering to the new back buffer until
7302          * the flip occurs and the object is no longer visible.
7303          */
7304         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7305         atomic_inc(&intel_crtc->unpin_work_count);
7306
7307         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7308         if (ret)
7309                 goto cleanup_pending;
7310
7311         intel_disable_fbc(dev);
7312         intel_mark_fb_busy(obj);
7313         mutex_unlock(&dev->struct_mutex);
7314
7315         trace_i915_flip_request(intel_crtc->plane, obj);
7316
7317         return 0;
7318
7319 cleanup_pending:
7320         atomic_dec(&intel_crtc->unpin_work_count);
7321         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7322         drm_gem_object_unreference(&work->old_fb_obj->base);
7323         drm_gem_object_unreference(&obj->base);
7324         mutex_unlock(&dev->struct_mutex);
7325
7326 cleanup:
7327         spin_lock_irqsave(&dev->event_lock, flags);
7328         intel_crtc->unpin_work = NULL;
7329         spin_unlock_irqrestore(&dev->event_lock, flags);
7330
7331         drm_vblank_put(dev, intel_crtc->pipe);
7332 free_work:
7333         kfree(work);
7334
7335         return ret;
7336 }
7337
7338 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7339         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7340         .load_lut = intel_crtc_load_lut,
7341         .disable = intel_crtc_noop,
7342 };
7343
7344 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7345 {
7346         struct intel_encoder *other_encoder;
7347         struct drm_crtc *crtc = &encoder->new_crtc->base;
7348
7349         if (WARN_ON(!crtc))
7350                 return false;
7351
7352         list_for_each_entry(other_encoder,
7353                             &crtc->dev->mode_config.encoder_list,
7354                             base.head) {
7355
7356                 if (&other_encoder->new_crtc->base != crtc ||
7357                     encoder == other_encoder)
7358                         continue;
7359                 else
7360                         return true;
7361         }
7362
7363         return false;
7364 }
7365
7366 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7367                                   struct drm_crtc *crtc)
7368 {
7369         struct drm_device *dev;
7370         struct drm_crtc *tmp;
7371         int crtc_mask = 1;
7372
7373         WARN(!crtc, "checking null crtc?\n");
7374
7375         dev = crtc->dev;
7376
7377         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7378                 if (tmp == crtc)
7379                         break;
7380                 crtc_mask <<= 1;
7381         }
7382
7383         if (encoder->possible_crtcs & crtc_mask)
7384                 return true;
7385         return false;
7386 }
7387
7388 /**
7389  * intel_modeset_update_staged_output_state
7390  *
7391  * Updates the staged output configuration state, e.g. after we've read out the
7392  * current hw state.
7393  */
7394 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7395 {
7396         struct intel_encoder *encoder;
7397         struct intel_connector *connector;
7398
7399         list_for_each_entry(connector, &dev->mode_config.connector_list,
7400                             base.head) {
7401                 connector->new_encoder =
7402                         to_intel_encoder(connector->base.encoder);
7403         }
7404
7405         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7406                             base.head) {
7407                 encoder->new_crtc =
7408                         to_intel_crtc(encoder->base.crtc);
7409         }
7410 }
7411
7412 /**
7413  * intel_modeset_commit_output_state
7414  *
7415  * This function copies the stage display pipe configuration to the real one.
7416  */
7417 static void intel_modeset_commit_output_state(struct drm_device *dev)
7418 {
7419         struct intel_encoder *encoder;
7420         struct intel_connector *connector;
7421
7422         list_for_each_entry(connector, &dev->mode_config.connector_list,
7423                             base.head) {
7424                 connector->base.encoder = &connector->new_encoder->base;
7425         }
7426
7427         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7428                             base.head) {
7429                 encoder->base.crtc = &encoder->new_crtc->base;
7430         }
7431 }
7432
7433 static struct drm_display_mode *
7434 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7435                             struct drm_display_mode *mode)
7436 {
7437         struct drm_device *dev = crtc->dev;
7438         struct drm_display_mode *adjusted_mode;
7439         struct drm_encoder_helper_funcs *encoder_funcs;
7440         struct intel_encoder *encoder;
7441
7442         adjusted_mode = drm_mode_duplicate(dev, mode);
7443         if (!adjusted_mode)
7444                 return ERR_PTR(-ENOMEM);
7445
7446         /* Pass our mode to the connectors and the CRTC to give them a chance to
7447          * adjust it according to limitations or connector properties, and also
7448          * a chance to reject the mode entirely.
7449          */
7450         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7451                             base.head) {
7452
7453                 if (&encoder->new_crtc->base != crtc)
7454                         continue;
7455                 encoder_funcs = encoder->base.helper_private;
7456                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7457                                                 adjusted_mode))) {
7458                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7459                         goto fail;
7460                 }
7461         }
7462
7463         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7464                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7465                 goto fail;
7466         }
7467         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7468
7469         return adjusted_mode;
7470 fail:
7471         drm_mode_destroy(dev, adjusted_mode);
7472         return ERR_PTR(-EINVAL);
7473 }
7474
7475 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7476  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7477 static void
7478 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7479                              unsigned *prepare_pipes, unsigned *disable_pipes)
7480 {
7481         struct intel_crtc *intel_crtc;
7482         struct drm_device *dev = crtc->dev;
7483         struct intel_encoder *encoder;
7484         struct intel_connector *connector;
7485         struct drm_crtc *tmp_crtc;
7486
7487         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7488
7489         /* Check which crtcs have changed outputs connected to them, these need
7490          * to be part of the prepare_pipes mask. We don't (yet) support global
7491          * modeset across multiple crtcs, so modeset_pipes will only have one
7492          * bit set at most. */
7493         list_for_each_entry(connector, &dev->mode_config.connector_list,
7494                             base.head) {
7495                 if (connector->base.encoder == &connector->new_encoder->base)
7496                         continue;
7497
7498                 if (connector->base.encoder) {
7499                         tmp_crtc = connector->base.encoder->crtc;
7500
7501                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7502                 }
7503
7504                 if (connector->new_encoder)
7505                         *prepare_pipes |=
7506                                 1 << connector->new_encoder->new_crtc->pipe;
7507         }
7508
7509         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7510                             base.head) {
7511                 if (encoder->base.crtc == &encoder->new_crtc->base)
7512                         continue;
7513
7514                 if (encoder->base.crtc) {
7515                         tmp_crtc = encoder->base.crtc;
7516
7517                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7518                 }
7519
7520                 if (encoder->new_crtc)
7521                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7522         }
7523
7524         /* Check for any pipes that will be fully disabled ... */
7525         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7526                             base.head) {
7527                 bool used = false;
7528
7529                 /* Don't try to disable disabled crtcs. */
7530                 if (!intel_crtc->base.enabled)
7531                         continue;
7532
7533                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7534                                     base.head) {
7535                         if (encoder->new_crtc == intel_crtc)
7536                                 used = true;
7537                 }
7538
7539                 if (!used)
7540                         *disable_pipes |= 1 << intel_crtc->pipe;
7541         }
7542
7543
7544         /* set_mode is also used to update properties on life display pipes. */
7545         intel_crtc = to_intel_crtc(crtc);
7546         if (crtc->enabled)
7547                 *prepare_pipes |= 1 << intel_crtc->pipe;
7548
7549         /* We only support modeset on one single crtc, hence we need to do that
7550          * only for the passed in crtc iff we change anything else than just
7551          * disable crtcs.
7552          *
7553          * This is actually not true, to be fully compatible with the old crtc
7554          * helper we automatically disable _any_ output (i.e. doesn't need to be
7555          * connected to the crtc we're modesetting on) if it's disconnected.
7556          * Which is a rather nutty api (since changed the output configuration
7557          * without userspace's explicit request can lead to confusion), but
7558          * alas. Hence we currently need to modeset on all pipes we prepare. */
7559         if (*prepare_pipes)
7560                 *modeset_pipes = *prepare_pipes;
7561
7562         /* ... and mask these out. */
7563         *modeset_pipes &= ~(*disable_pipes);
7564         *prepare_pipes &= ~(*disable_pipes);
7565 }
7566
7567 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7568 {
7569         struct drm_encoder *encoder;
7570         struct drm_device *dev = crtc->dev;
7571
7572         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7573                 if (encoder->crtc == crtc)
7574                         return true;
7575
7576         return false;
7577 }
7578
7579 static void
7580 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7581 {
7582         struct intel_encoder *intel_encoder;
7583         struct intel_crtc *intel_crtc;
7584         struct drm_connector *connector;
7585
7586         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7587                             base.head) {
7588                 if (!intel_encoder->base.crtc)
7589                         continue;
7590
7591                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7592
7593                 if (prepare_pipes & (1 << intel_crtc->pipe))
7594                         intel_encoder->connectors_active = false;
7595         }
7596
7597         intel_modeset_commit_output_state(dev);
7598
7599         /* Update computed state. */
7600         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7601                             base.head) {
7602                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7603         }
7604
7605         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7606                 if (!connector->encoder || !connector->encoder->crtc)
7607                         continue;
7608
7609                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7610
7611                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7612                         struct drm_property *dpms_property =
7613                                 dev->mode_config.dpms_property;
7614
7615                         connector->dpms = DRM_MODE_DPMS_ON;
7616                         drm_connector_property_set_value(connector,
7617                                                          dpms_property,
7618                                                          DRM_MODE_DPMS_ON);
7619
7620                         intel_encoder = to_intel_encoder(connector->encoder);
7621                         intel_encoder->connectors_active = true;
7622                 }
7623         }
7624
7625 }
7626
7627 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7628         list_for_each_entry((intel_crtc), \
7629                             &(dev)->mode_config.crtc_list, \
7630                             base.head) \
7631                 if (mask & (1 <<(intel_crtc)->pipe)) \
7632
7633 void
7634 intel_modeset_check_state(struct drm_device *dev)
7635 {
7636         struct intel_crtc *crtc;
7637         struct intel_encoder *encoder;
7638         struct intel_connector *connector;
7639
7640         list_for_each_entry(connector, &dev->mode_config.connector_list,
7641                             base.head) {
7642                 /* This also checks the encoder/connector hw state with the
7643                  * ->get_hw_state callbacks. */
7644                 intel_connector_check_state(connector);
7645
7646                 WARN(&connector->new_encoder->base != connector->base.encoder,
7647                      "connector's staged encoder doesn't match current encoder\n");
7648         }
7649
7650         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7651                             base.head) {
7652                 bool enabled = false;
7653                 bool active = false;
7654                 enum pipe pipe, tracked_pipe;
7655
7656                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7657                               encoder->base.base.id,
7658                               drm_get_encoder_name(&encoder->base));
7659
7660                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7661                      "encoder's stage crtc doesn't match current crtc\n");
7662                 WARN(encoder->connectors_active && !encoder->base.crtc,
7663                      "encoder's active_connectors set, but no crtc\n");
7664
7665                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7666                                     base.head) {
7667                         if (connector->base.encoder != &encoder->base)
7668                                 continue;
7669                         enabled = true;
7670                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7671                                 active = true;
7672                 }
7673                 WARN(!!encoder->base.crtc != enabled,
7674                      "encoder's enabled state mismatch "
7675                      "(expected %i, found %i)\n",
7676                      !!encoder->base.crtc, enabled);
7677                 WARN(active && !encoder->base.crtc,
7678                      "active encoder with no crtc\n");
7679
7680                 WARN(encoder->connectors_active != active,
7681                      "encoder's computed active state doesn't match tracked active state "
7682                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7683
7684                 active = encoder->get_hw_state(encoder, &pipe);
7685                 WARN(active != encoder->connectors_active,
7686                      "encoder's hw state doesn't match sw tracking "
7687                      "(expected %i, found %i)\n",
7688                      encoder->connectors_active, active);
7689
7690                 if (!encoder->base.crtc)
7691                         continue;
7692
7693                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7694                 WARN(active && pipe != tracked_pipe,
7695                      "active encoder's pipe doesn't match"
7696                      "(expected %i, found %i)\n",
7697                      tracked_pipe, pipe);
7698
7699         }
7700
7701         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7702                             base.head) {
7703                 bool enabled = false;
7704                 bool active = false;
7705
7706                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7707                               crtc->base.base.id);
7708
7709                 WARN(crtc->active && !crtc->base.enabled,
7710                      "active crtc, but not enabled in sw tracking\n");
7711
7712                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7713                                     base.head) {
7714                         if (encoder->base.crtc != &crtc->base)
7715                                 continue;
7716                         enabled = true;
7717                         if (encoder->connectors_active)
7718                                 active = true;
7719                 }
7720                 WARN(active != crtc->active,
7721                      "crtc's computed active state doesn't match tracked active state "
7722                      "(expected %i, found %i)\n", active, crtc->active);
7723                 WARN(enabled != crtc->base.enabled,
7724                      "crtc's computed enabled state doesn't match tracked enabled state "
7725                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7726
7727                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7728         }
7729 }
7730
7731 bool intel_set_mode(struct drm_crtc *crtc,
7732                     struct drm_display_mode *mode,
7733                     int x, int y, struct drm_framebuffer *fb)
7734 {
7735         struct drm_device *dev = crtc->dev;
7736         drm_i915_private_t *dev_priv = dev->dev_private;
7737         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7738         struct intel_crtc *intel_crtc;
7739         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7740         bool ret = true;
7741
7742         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7743                                      &prepare_pipes, &disable_pipes);
7744
7745         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7746                       modeset_pipes, prepare_pipes, disable_pipes);
7747
7748         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7749                 intel_crtc_disable(&intel_crtc->base);
7750
7751         saved_hwmode = crtc->hwmode;
7752         saved_mode = crtc->mode;
7753
7754         /* Hack: Because we don't (yet) support global modeset on multiple
7755          * crtcs, we don't keep track of the new mode for more than one crtc.
7756          * Hence simply check whether any bit is set in modeset_pipes in all the
7757          * pieces of code that are not yet converted to deal with mutliple crtcs
7758          * changing their mode at the same time. */
7759         adjusted_mode = NULL;
7760         if (modeset_pipes) {
7761                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7762                 if (IS_ERR(adjusted_mode)) {
7763                         return false;
7764                 }
7765         }
7766
7767         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7768                 if (intel_crtc->base.enabled)
7769                         dev_priv->display.crtc_disable(&intel_crtc->base);
7770         }
7771
7772         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7773          * to set it here already despite that we pass it down the callchain.
7774          */
7775         if (modeset_pipes)
7776                 crtc->mode = *mode;
7777
7778         /* Only after disabling all output pipelines that will be changed can we
7779          * update the the output configuration. */
7780         intel_modeset_update_state(dev, prepare_pipes);
7781
7782         if (dev_priv->display.modeset_global_resources)
7783                 dev_priv->display.modeset_global_resources(dev);
7784
7785         /* Set up the DPLL and any encoders state that needs to adjust or depend
7786          * on the DPLL.
7787          */
7788         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7789                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7790                                            mode, adjusted_mode,
7791                                            x, y, fb);
7792                 if (!ret)
7793                     goto done;
7794         }
7795
7796         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7797         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7798                 dev_priv->display.crtc_enable(&intel_crtc->base);
7799
7800         if (modeset_pipes) {
7801                 /* Store real post-adjustment hardware mode. */
7802                 crtc->hwmode = *adjusted_mode;
7803
7804                 /* Calculate and store various constants which
7805                  * are later needed by vblank and swap-completion
7806                  * timestamping. They are derived from true hwmode.
7807                  */
7808                 drm_calc_timestamping_constants(crtc);
7809         }
7810
7811         /* FIXME: add subpixel order */
7812 done:
7813         drm_mode_destroy(dev, adjusted_mode);
7814         if (!ret && crtc->enabled) {
7815                 crtc->hwmode = saved_hwmode;
7816                 crtc->mode = saved_mode;
7817         } else {
7818                 intel_modeset_check_state(dev);
7819         }
7820
7821         return ret;
7822 }
7823
7824 #undef for_each_intel_crtc_masked
7825
7826 static void intel_set_config_free(struct intel_set_config *config)
7827 {
7828         if (!config)
7829                 return;
7830
7831         kfree(config->save_connector_encoders);
7832         kfree(config->save_encoder_crtcs);
7833         kfree(config);
7834 }
7835
7836 static int intel_set_config_save_state(struct drm_device *dev,
7837                                        struct intel_set_config *config)
7838 {
7839         struct drm_encoder *encoder;
7840         struct drm_connector *connector;
7841         int count;
7842
7843         config->save_encoder_crtcs =
7844                 kcalloc(dev->mode_config.num_encoder,
7845                         sizeof(struct drm_crtc *), GFP_KERNEL);
7846         if (!config->save_encoder_crtcs)
7847                 return -ENOMEM;
7848
7849         config->save_connector_encoders =
7850                 kcalloc(dev->mode_config.num_connector,
7851                         sizeof(struct drm_encoder *), GFP_KERNEL);
7852         if (!config->save_connector_encoders)
7853                 return -ENOMEM;
7854
7855         /* Copy data. Note that driver private data is not affected.
7856          * Should anything bad happen only the expected state is
7857          * restored, not the drivers personal bookkeeping.
7858          */
7859         count = 0;
7860         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7861                 config->save_encoder_crtcs[count++] = encoder->crtc;
7862         }
7863
7864         count = 0;
7865         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7866                 config->save_connector_encoders[count++] = connector->encoder;
7867         }
7868
7869         return 0;
7870 }
7871
7872 static void intel_set_config_restore_state(struct drm_device *dev,
7873                                            struct intel_set_config *config)
7874 {
7875         struct intel_encoder *encoder;
7876         struct intel_connector *connector;
7877         int count;
7878
7879         count = 0;
7880         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7881                 encoder->new_crtc =
7882                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7883         }
7884
7885         count = 0;
7886         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7887                 connector->new_encoder =
7888                         to_intel_encoder(config->save_connector_encoders[count++]);
7889         }
7890 }
7891
7892 static void
7893 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7894                                       struct intel_set_config *config)
7895 {
7896
7897         /* We should be able to check here if the fb has the same properties
7898          * and then just flip_or_move it */
7899         if (set->crtc->fb != set->fb) {
7900                 /* If we have no fb then treat it as a full mode set */
7901                 if (set->crtc->fb == NULL) {
7902                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7903                         config->mode_changed = true;
7904                 } else if (set->fb == NULL) {
7905                         config->mode_changed = true;
7906                 } else if (set->fb->depth != set->crtc->fb->depth) {
7907                         config->mode_changed = true;
7908                 } else if (set->fb->bits_per_pixel !=
7909                            set->crtc->fb->bits_per_pixel) {
7910                         config->mode_changed = true;
7911                 } else
7912                         config->fb_changed = true;
7913         }
7914
7915         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7916                 config->fb_changed = true;
7917
7918         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7919                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7920                 drm_mode_debug_printmodeline(&set->crtc->mode);
7921                 drm_mode_debug_printmodeline(set->mode);
7922                 config->mode_changed = true;
7923         }
7924 }
7925
7926 static int
7927 intel_modeset_stage_output_state(struct drm_device *dev,
7928                                  struct drm_mode_set *set,
7929                                  struct intel_set_config *config)
7930 {
7931         struct drm_crtc *new_crtc;
7932         struct intel_connector *connector;
7933         struct intel_encoder *encoder;
7934         int count, ro;
7935
7936         /* The upper layers ensure that we either disabl a crtc or have a list
7937          * of connectors. For paranoia, double-check this. */
7938         WARN_ON(!set->fb && (set->num_connectors != 0));
7939         WARN_ON(set->fb && (set->num_connectors == 0));
7940
7941         count = 0;
7942         list_for_each_entry(connector, &dev->mode_config.connector_list,
7943                             base.head) {
7944                 /* Otherwise traverse passed in connector list and get encoders
7945                  * for them. */
7946                 for (ro = 0; ro < set->num_connectors; ro++) {
7947                         if (set->connectors[ro] == &connector->base) {
7948                                 connector->new_encoder = connector->encoder;
7949                                 break;
7950                         }
7951                 }
7952
7953                 /* If we disable the crtc, disable all its connectors. Also, if
7954                  * the connector is on the changing crtc but not on the new
7955                  * connector list, disable it. */
7956                 if ((!set->fb || ro == set->num_connectors) &&
7957                     connector->base.encoder &&
7958                     connector->base.encoder->crtc == set->crtc) {
7959                         connector->new_encoder = NULL;
7960
7961                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7962                                 connector->base.base.id,
7963                                 drm_get_connector_name(&connector->base));
7964                 }
7965
7966
7967                 if (&connector->new_encoder->base != connector->base.encoder) {
7968                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7969                         config->mode_changed = true;
7970                 }
7971
7972                 /* Disable all disconnected encoders. */
7973                 if (connector->base.status == connector_status_disconnected)
7974                         connector->new_encoder = NULL;
7975         }
7976         /* connector->new_encoder is now updated for all connectors. */
7977
7978         /* Update crtc of enabled connectors. */
7979         count = 0;
7980         list_for_each_entry(connector, &dev->mode_config.connector_list,
7981                             base.head) {
7982                 if (!connector->new_encoder)
7983                         continue;
7984
7985                 new_crtc = connector->new_encoder->base.crtc;
7986
7987                 for (ro = 0; ro < set->num_connectors; ro++) {
7988                         if (set->connectors[ro] == &connector->base)
7989                                 new_crtc = set->crtc;
7990                 }
7991
7992                 /* Make sure the new CRTC will work with the encoder */
7993                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7994                                            new_crtc)) {
7995                         return -EINVAL;
7996                 }
7997                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7998
7999                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8000                         connector->base.base.id,
8001                         drm_get_connector_name(&connector->base),
8002                         new_crtc->base.id);
8003         }
8004
8005         /* Check for any encoders that needs to be disabled. */
8006         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8007                             base.head) {
8008                 list_for_each_entry(connector,
8009                                     &dev->mode_config.connector_list,
8010                                     base.head) {
8011                         if (connector->new_encoder == encoder) {
8012                                 WARN_ON(!connector->new_encoder->new_crtc);
8013
8014                                 goto next_encoder;
8015                         }
8016                 }
8017                 encoder->new_crtc = NULL;
8018 next_encoder:
8019                 /* Only now check for crtc changes so we don't miss encoders
8020                  * that will be disabled. */
8021                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8022                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8023                         config->mode_changed = true;
8024                 }
8025         }
8026         /* Now we've also updated encoder->new_crtc for all encoders. */
8027
8028         return 0;
8029 }
8030
8031 static int intel_crtc_set_config(struct drm_mode_set *set)
8032 {
8033         struct drm_device *dev;
8034         struct drm_mode_set save_set;
8035         struct intel_set_config *config;
8036         int ret;
8037
8038         BUG_ON(!set);
8039         BUG_ON(!set->crtc);
8040         BUG_ON(!set->crtc->helper_private);
8041
8042         if (!set->mode)
8043                 set->fb = NULL;
8044
8045         /* The fb helper likes to play gross jokes with ->mode_set_config.
8046          * Unfortunately the crtc helper doesn't do much at all for this case,
8047          * so we have to cope with this madness until the fb helper is fixed up. */
8048         if (set->fb && set->num_connectors == 0)
8049                 return 0;
8050
8051         if (set->fb) {
8052                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8053                                 set->crtc->base.id, set->fb->base.id,
8054                                 (int)set->num_connectors, set->x, set->y);
8055         } else {
8056                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8057         }
8058
8059         dev = set->crtc->dev;
8060
8061         ret = -ENOMEM;
8062         config = kzalloc(sizeof(*config), GFP_KERNEL);
8063         if (!config)
8064                 goto out_config;
8065
8066         ret = intel_set_config_save_state(dev, config);
8067         if (ret)
8068                 goto out_config;
8069
8070         save_set.crtc = set->crtc;
8071         save_set.mode = &set->crtc->mode;
8072         save_set.x = set->crtc->x;
8073         save_set.y = set->crtc->y;
8074         save_set.fb = set->crtc->fb;
8075
8076         /* Compute whether we need a full modeset, only an fb base update or no
8077          * change at all. In the future we might also check whether only the
8078          * mode changed, e.g. for LVDS where we only change the panel fitter in
8079          * such cases. */
8080         intel_set_config_compute_mode_changes(set, config);
8081
8082         ret = intel_modeset_stage_output_state(dev, set, config);
8083         if (ret)
8084                 goto fail;
8085
8086         if (config->mode_changed) {
8087                 if (set->mode) {
8088                         DRM_DEBUG_KMS("attempting to set mode from"
8089                                         " userspace\n");
8090                         drm_mode_debug_printmodeline(set->mode);
8091                 }
8092
8093                 if (!intel_set_mode(set->crtc, set->mode,
8094                                     set->x, set->y, set->fb)) {
8095                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8096                                   set->crtc->base.id);
8097                         ret = -EINVAL;
8098                         goto fail;
8099                 }
8100         } else if (config->fb_changed) {
8101                 ret = intel_pipe_set_base(set->crtc,
8102                                           set->x, set->y, set->fb);
8103         }
8104
8105         intel_set_config_free(config);
8106
8107         return 0;
8108
8109 fail:
8110         intel_set_config_restore_state(dev, config);
8111
8112         /* Try to restore the config */
8113         if (config->mode_changed &&
8114             !intel_set_mode(save_set.crtc, save_set.mode,
8115                             save_set.x, save_set.y, save_set.fb))
8116                 DRM_ERROR("failed to restore config after modeset failure\n");
8117
8118 out_config:
8119         intel_set_config_free(config);
8120         return ret;
8121 }
8122
8123 static const struct drm_crtc_funcs intel_crtc_funcs = {
8124         .cursor_set = intel_crtc_cursor_set,
8125         .cursor_move = intel_crtc_cursor_move,
8126         .gamma_set = intel_crtc_gamma_set,
8127         .set_config = intel_crtc_set_config,
8128         .destroy = intel_crtc_destroy,
8129         .page_flip = intel_crtc_page_flip,
8130 };
8131
8132 static void intel_cpu_pll_init(struct drm_device *dev)
8133 {
8134         if (IS_HASWELL(dev))
8135                 intel_ddi_pll_init(dev);
8136 }
8137
8138 static void intel_pch_pll_init(struct drm_device *dev)
8139 {
8140         drm_i915_private_t *dev_priv = dev->dev_private;
8141         int i;
8142
8143         if (dev_priv->num_pch_pll == 0) {
8144                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8145                 return;
8146         }
8147
8148         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8149                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8150                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8151                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8152         }
8153 }
8154
8155 static void intel_crtc_init(struct drm_device *dev, int pipe)
8156 {
8157         drm_i915_private_t *dev_priv = dev->dev_private;
8158         struct intel_crtc *intel_crtc;
8159         int i;
8160
8161         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8162         if (intel_crtc == NULL)
8163                 return;
8164
8165         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8166
8167         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8168         for (i = 0; i < 256; i++) {
8169                 intel_crtc->lut_r[i] = i;
8170                 intel_crtc->lut_g[i] = i;
8171                 intel_crtc->lut_b[i] = i;
8172         }
8173
8174         /* Swap pipes & planes for FBC on pre-965 */
8175         intel_crtc->pipe = pipe;
8176         intel_crtc->plane = pipe;
8177         intel_crtc->cpu_transcoder = pipe;
8178         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8179                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8180                 intel_crtc->plane = !pipe;
8181         }
8182
8183         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8184                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8185         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8186         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8187
8188         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8189
8190         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8191 }
8192
8193 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8194                                 struct drm_file *file)
8195 {
8196         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8197         struct drm_mode_object *drmmode_obj;
8198         struct intel_crtc *crtc;
8199
8200         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8201                 return -ENODEV;
8202
8203         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8204                         DRM_MODE_OBJECT_CRTC);
8205
8206         if (!drmmode_obj) {
8207                 DRM_ERROR("no such CRTC id\n");
8208                 return -EINVAL;
8209         }
8210
8211         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8212         pipe_from_crtc_id->pipe = crtc->pipe;
8213
8214         return 0;
8215 }
8216
8217 static int intel_encoder_clones(struct intel_encoder *encoder)
8218 {
8219         struct drm_device *dev = encoder->base.dev;
8220         struct intel_encoder *source_encoder;
8221         int index_mask = 0;
8222         int entry = 0;
8223
8224         list_for_each_entry(source_encoder,
8225                             &dev->mode_config.encoder_list, base.head) {
8226
8227                 if (encoder == source_encoder)
8228                         index_mask |= (1 << entry);
8229
8230                 /* Intel hw has only one MUX where enocoders could be cloned. */
8231                 if (encoder->cloneable && source_encoder->cloneable)
8232                         index_mask |= (1 << entry);
8233
8234                 entry++;
8235         }
8236
8237         return index_mask;
8238 }
8239
8240 static bool has_edp_a(struct drm_device *dev)
8241 {
8242         struct drm_i915_private *dev_priv = dev->dev_private;
8243
8244         if (!IS_MOBILE(dev))
8245                 return false;
8246
8247         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8248                 return false;
8249
8250         if (IS_GEN5(dev) &&
8251             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8252                 return false;
8253
8254         return true;
8255 }
8256
8257 static void intel_setup_outputs(struct drm_device *dev)
8258 {
8259         struct drm_i915_private *dev_priv = dev->dev_private;
8260         struct intel_encoder *encoder;
8261         bool dpd_is_edp = false;
8262         bool has_lvds;
8263
8264         has_lvds = intel_lvds_init(dev);
8265         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8266                 /* disable the panel fitter on everything but LVDS */
8267                 I915_WRITE(PFIT_CONTROL, 0);
8268         }
8269
8270         intel_crt_init(dev);
8271
8272         if (IS_HASWELL(dev)) {
8273                 int found;
8274
8275                 /* Haswell uses DDI functions to detect digital outputs */
8276                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8277                 /* DDI A only supports eDP */
8278                 if (found)
8279                         intel_ddi_init(dev, PORT_A);
8280
8281                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8282                  * register */
8283                 found = I915_READ(SFUSE_STRAP);
8284
8285                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8286                         intel_ddi_init(dev, PORT_B);
8287                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8288                         intel_ddi_init(dev, PORT_C);
8289                 if (found & SFUSE_STRAP_DDID_DETECTED)
8290                         intel_ddi_init(dev, PORT_D);
8291         } else if (HAS_PCH_SPLIT(dev)) {
8292                 int found;
8293                 dpd_is_edp = intel_dpd_is_edp(dev);
8294
8295                 if (has_edp_a(dev))
8296                         intel_dp_init(dev, DP_A, PORT_A);
8297
8298                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8299                         /* PCH SDVOB multiplex with HDMIB */
8300                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8301                         if (!found)
8302                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8303                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8304                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8305                 }
8306
8307                 if (I915_READ(HDMIC) & PORT_DETECTED)
8308                         intel_hdmi_init(dev, HDMIC, PORT_C);
8309
8310                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8311                         intel_hdmi_init(dev, HDMID, PORT_D);
8312
8313                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8314                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8315
8316                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8317                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8318         } else if (IS_VALLEYVIEW(dev)) {
8319                 int found;
8320
8321                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8322                 if (I915_READ(DP_C) & DP_DETECTED)
8323                         intel_dp_init(dev, DP_C, PORT_C);
8324
8325                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8326                         /* SDVOB multiplex with HDMIB */
8327                         found = intel_sdvo_init(dev, SDVOB, true);
8328                         if (!found)
8329                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8330                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8331                                 intel_dp_init(dev, DP_B, PORT_B);
8332                 }
8333
8334                 if (I915_READ(SDVOC) & PORT_DETECTED)
8335                         intel_hdmi_init(dev, SDVOC, PORT_C);
8336
8337         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8338                 bool found = false;
8339
8340                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8341                         DRM_DEBUG_KMS("probing SDVOB\n");
8342                         found = intel_sdvo_init(dev, SDVOB, true);
8343                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8344                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8345                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8346                         }
8347
8348                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8349                                 DRM_DEBUG_KMS("probing DP_B\n");
8350                                 intel_dp_init(dev, DP_B, PORT_B);
8351                         }
8352                 }
8353
8354                 /* Before G4X SDVOC doesn't have its own detect register */
8355
8356                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8357                         DRM_DEBUG_KMS("probing SDVOC\n");
8358                         found = intel_sdvo_init(dev, SDVOC, false);
8359                 }
8360
8361                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8362
8363                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8364                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8365                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8366                         }
8367                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8368                                 DRM_DEBUG_KMS("probing DP_C\n");
8369                                 intel_dp_init(dev, DP_C, PORT_C);
8370                         }
8371                 }
8372
8373                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8374                     (I915_READ(DP_D) & DP_DETECTED)) {
8375                         DRM_DEBUG_KMS("probing DP_D\n");
8376                         intel_dp_init(dev, DP_D, PORT_D);
8377                 }
8378         } else if (IS_GEN2(dev))
8379                 intel_dvo_init(dev);
8380
8381         if (SUPPORTS_TV(dev))
8382                 intel_tv_init(dev);
8383
8384         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8385                 encoder->base.possible_crtcs = encoder->crtc_mask;
8386                 encoder->base.possible_clones =
8387                         intel_encoder_clones(encoder);
8388         }
8389
8390         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8391                 ironlake_init_pch_refclk(dev);
8392
8393         drm_helper_move_panel_connectors_to_head(dev);
8394 }
8395
8396 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8397 {
8398         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8399
8400         drm_framebuffer_cleanup(fb);
8401         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8402
8403         kfree(intel_fb);
8404 }
8405
8406 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8407                                                 struct drm_file *file,
8408                                                 unsigned int *handle)
8409 {
8410         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8411         struct drm_i915_gem_object *obj = intel_fb->obj;
8412
8413         return drm_gem_handle_create(file, &obj->base, handle);
8414 }
8415
8416 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8417         .destroy = intel_user_framebuffer_destroy,
8418         .create_handle = intel_user_framebuffer_create_handle,
8419 };
8420
8421 int intel_framebuffer_init(struct drm_device *dev,
8422                            struct intel_framebuffer *intel_fb,
8423                            struct drm_mode_fb_cmd2 *mode_cmd,
8424                            struct drm_i915_gem_object *obj)
8425 {
8426         int ret;
8427
8428         if (obj->tiling_mode == I915_TILING_Y)
8429                 return -EINVAL;
8430
8431         if (mode_cmd->pitches[0] & 63)
8432                 return -EINVAL;
8433
8434         /* FIXME <= Gen4 stride limits are bit unclear */
8435         if (mode_cmd->pitches[0] > 32768)
8436                 return -EINVAL;
8437
8438         if (obj->tiling_mode != I915_TILING_NONE &&
8439             mode_cmd->pitches[0] != obj->stride)
8440                 return -EINVAL;
8441
8442         /* Reject formats not supported by any plane early. */
8443         switch (mode_cmd->pixel_format) {
8444         case DRM_FORMAT_C8:
8445         case DRM_FORMAT_RGB565:
8446         case DRM_FORMAT_XRGB8888:
8447         case DRM_FORMAT_ARGB8888:
8448                 break;
8449         case DRM_FORMAT_XRGB1555:
8450         case DRM_FORMAT_ARGB1555:
8451                 if (INTEL_INFO(dev)->gen > 3)
8452                         return -EINVAL;
8453                 break;
8454         case DRM_FORMAT_XBGR8888:
8455         case DRM_FORMAT_ABGR8888:
8456         case DRM_FORMAT_XRGB2101010:
8457         case DRM_FORMAT_ARGB2101010:
8458         case DRM_FORMAT_XBGR2101010:
8459         case DRM_FORMAT_ABGR2101010:
8460                 if (INTEL_INFO(dev)->gen < 4)
8461                         return -EINVAL;
8462                 break;
8463         case DRM_FORMAT_YUYV:
8464         case DRM_FORMAT_UYVY:
8465         case DRM_FORMAT_YVYU:
8466         case DRM_FORMAT_VYUY:
8467                 if (INTEL_INFO(dev)->gen < 6)
8468                         return -EINVAL;
8469                 break;
8470         default:
8471                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8472                 return -EINVAL;
8473         }
8474
8475         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8476         if (mode_cmd->offsets[0] != 0)
8477                 return -EINVAL;
8478
8479         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8480         if (ret) {
8481                 DRM_ERROR("framebuffer init failed %d\n", ret);
8482                 return ret;
8483         }
8484
8485         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8486         intel_fb->obj = obj;
8487         return 0;
8488 }
8489
8490 static struct drm_framebuffer *
8491 intel_user_framebuffer_create(struct drm_device *dev,
8492                               struct drm_file *filp,
8493                               struct drm_mode_fb_cmd2 *mode_cmd)
8494 {
8495         struct drm_i915_gem_object *obj;
8496
8497         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8498                                                 mode_cmd->handles[0]));
8499         if (&obj->base == NULL)
8500                 return ERR_PTR(-ENOENT);
8501
8502         return intel_framebuffer_create(dev, mode_cmd, obj);
8503 }
8504
8505 static const struct drm_mode_config_funcs intel_mode_funcs = {
8506         .fb_create = intel_user_framebuffer_create,
8507         .output_poll_changed = intel_fb_output_poll_changed,
8508 };
8509
8510 /* Set up chip specific display functions */
8511 static void intel_init_display(struct drm_device *dev)
8512 {
8513         struct drm_i915_private *dev_priv = dev->dev_private;
8514
8515         /* We always want a DPMS function */
8516         if (IS_HASWELL(dev)) {
8517                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8518                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8519                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8520                 dev_priv->display.off = haswell_crtc_off;
8521                 dev_priv->display.update_plane = ironlake_update_plane;
8522         } else if (HAS_PCH_SPLIT(dev)) {
8523                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8524                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8525                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8526                 dev_priv->display.off = ironlake_crtc_off;
8527                 dev_priv->display.update_plane = ironlake_update_plane;
8528         } else {
8529                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8530                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8531                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8532                 dev_priv->display.off = i9xx_crtc_off;
8533                 dev_priv->display.update_plane = i9xx_update_plane;
8534         }
8535
8536         /* Returns the core display clock speed */
8537         if (IS_VALLEYVIEW(dev))
8538                 dev_priv->display.get_display_clock_speed =
8539                         valleyview_get_display_clock_speed;
8540         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8541                 dev_priv->display.get_display_clock_speed =
8542                         i945_get_display_clock_speed;
8543         else if (IS_I915G(dev))
8544                 dev_priv->display.get_display_clock_speed =
8545                         i915_get_display_clock_speed;
8546         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8547                 dev_priv->display.get_display_clock_speed =
8548                         i9xx_misc_get_display_clock_speed;
8549         else if (IS_I915GM(dev))
8550                 dev_priv->display.get_display_clock_speed =
8551                         i915gm_get_display_clock_speed;
8552         else if (IS_I865G(dev))
8553                 dev_priv->display.get_display_clock_speed =
8554                         i865_get_display_clock_speed;
8555         else if (IS_I85X(dev))
8556                 dev_priv->display.get_display_clock_speed =
8557                         i855_get_display_clock_speed;
8558         else /* 852, 830 */
8559                 dev_priv->display.get_display_clock_speed =
8560                         i830_get_display_clock_speed;
8561
8562         if (HAS_PCH_SPLIT(dev)) {
8563                 if (IS_GEN5(dev)) {
8564                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8565                         dev_priv->display.write_eld = ironlake_write_eld;
8566                 } else if (IS_GEN6(dev)) {
8567                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8568                         dev_priv->display.write_eld = ironlake_write_eld;
8569                 } else if (IS_IVYBRIDGE(dev)) {
8570                         /* FIXME: detect B0+ stepping and use auto training */
8571                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8572                         dev_priv->display.write_eld = ironlake_write_eld;
8573                         dev_priv->display.modeset_global_resources =
8574                                 ivb_modeset_global_resources;
8575                 } else if (IS_HASWELL(dev)) {
8576                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8577                         dev_priv->display.write_eld = haswell_write_eld;
8578                 } else
8579                         dev_priv->display.update_wm = NULL;
8580         } else if (IS_G4X(dev)) {
8581                 dev_priv->display.write_eld = g4x_write_eld;
8582         }
8583
8584         /* Default just returns -ENODEV to indicate unsupported */
8585         dev_priv->display.queue_flip = intel_default_queue_flip;
8586
8587         switch (INTEL_INFO(dev)->gen) {
8588         case 2:
8589                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8590                 break;
8591
8592         case 3:
8593                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8594                 break;
8595
8596         case 4:
8597         case 5:
8598                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8599                 break;
8600
8601         case 6:
8602                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8603                 break;
8604         case 7:
8605                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8606                 break;
8607         }
8608 }
8609
8610 /*
8611  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8612  * resume, or other times.  This quirk makes sure that's the case for
8613  * affected systems.
8614  */
8615 static void quirk_pipea_force(struct drm_device *dev)
8616 {
8617         struct drm_i915_private *dev_priv = dev->dev_private;
8618
8619         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8620         DRM_INFO("applying pipe a force quirk\n");
8621 }
8622
8623 /*
8624  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8625  */
8626 static void quirk_ssc_force_disable(struct drm_device *dev)
8627 {
8628         struct drm_i915_private *dev_priv = dev->dev_private;
8629         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8630         DRM_INFO("applying lvds SSC disable quirk\n");
8631 }
8632
8633 /*
8634  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8635  * brightness value
8636  */
8637 static void quirk_invert_brightness(struct drm_device *dev)
8638 {
8639         struct drm_i915_private *dev_priv = dev->dev_private;
8640         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8641         DRM_INFO("applying inverted panel brightness quirk\n");
8642 }
8643
8644 struct intel_quirk {
8645         int device;
8646         int subsystem_vendor;
8647         int subsystem_device;
8648         void (*hook)(struct drm_device *dev);
8649 };
8650
8651 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8652 struct intel_dmi_quirk {
8653         void (*hook)(struct drm_device *dev);
8654         const struct dmi_system_id (*dmi_id_list)[];
8655 };
8656
8657 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8658 {
8659         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8660         return 1;
8661 }
8662
8663 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8664         {
8665                 .dmi_id_list = &(const struct dmi_system_id[]) {
8666                         {
8667                                 .callback = intel_dmi_reverse_brightness,
8668                                 .ident = "NCR Corporation",
8669                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8670                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8671                                 },
8672                         },
8673                         { }  /* terminating entry */
8674                 },
8675                 .hook = quirk_invert_brightness,
8676         },
8677 };
8678
8679 static struct intel_quirk intel_quirks[] = {
8680         /* HP Mini needs pipe A force quirk (LP: #322104) */
8681         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8682
8683         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8684         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8685
8686         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8687         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8688
8689         /* 830/845 need to leave pipe A & dpll A up */
8690         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8691         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8692
8693         /* Lenovo U160 cannot use SSC on LVDS */
8694         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8695
8696         /* Sony Vaio Y cannot use SSC on LVDS */
8697         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8698
8699         /* Acer Aspire 5734Z must invert backlight brightness */
8700         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8701 };
8702
8703 static void intel_init_quirks(struct drm_device *dev)
8704 {
8705         struct pci_dev *d = dev->pdev;
8706         int i;
8707
8708         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8709                 struct intel_quirk *q = &intel_quirks[i];
8710
8711                 if (d->device == q->device &&
8712                     (d->subsystem_vendor == q->subsystem_vendor ||
8713                      q->subsystem_vendor == PCI_ANY_ID) &&
8714                     (d->subsystem_device == q->subsystem_device ||
8715                      q->subsystem_device == PCI_ANY_ID))
8716                         q->hook(dev);
8717         }
8718         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8719                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8720                         intel_dmi_quirks[i].hook(dev);
8721         }
8722 }
8723
8724 /* Disable the VGA plane that we never use */
8725 static void i915_disable_vga(struct drm_device *dev)
8726 {
8727         struct drm_i915_private *dev_priv = dev->dev_private;
8728         u8 sr1;
8729         u32 vga_reg;
8730
8731         if (HAS_PCH_SPLIT(dev))
8732                 vga_reg = CPU_VGACNTRL;
8733         else
8734                 vga_reg = VGACNTRL;
8735
8736         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8737         outb(SR01, VGA_SR_INDEX);
8738         sr1 = inb(VGA_SR_DATA);
8739         outb(sr1 | 1<<5, VGA_SR_DATA);
8740         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8741         udelay(300);
8742
8743         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8744         POSTING_READ(vga_reg);
8745 }
8746
8747 void intel_modeset_init_hw(struct drm_device *dev)
8748 {
8749         /* We attempt to init the necessary power wells early in the initialization
8750          * time, so the subsystems that expect power to be enabled can work.
8751          */
8752         intel_init_power_wells(dev);
8753
8754         intel_prepare_ddi(dev);
8755
8756         intel_init_clock_gating(dev);
8757
8758         mutex_lock(&dev->struct_mutex);
8759         intel_enable_gt_powersave(dev);
8760         mutex_unlock(&dev->struct_mutex);
8761 }
8762
8763 void intel_modeset_init(struct drm_device *dev)
8764 {
8765         struct drm_i915_private *dev_priv = dev->dev_private;
8766         int i, ret;
8767
8768         drm_mode_config_init(dev);
8769
8770         dev->mode_config.min_width = 0;
8771         dev->mode_config.min_height = 0;
8772
8773         dev->mode_config.preferred_depth = 24;
8774         dev->mode_config.prefer_shadow = 1;
8775
8776         dev->mode_config.funcs = &intel_mode_funcs;
8777
8778         intel_init_quirks(dev);
8779
8780         intel_init_pm(dev);
8781
8782         intel_init_display(dev);
8783
8784         if (IS_GEN2(dev)) {
8785                 dev->mode_config.max_width = 2048;
8786                 dev->mode_config.max_height = 2048;
8787         } else if (IS_GEN3(dev)) {
8788                 dev->mode_config.max_width = 4096;
8789                 dev->mode_config.max_height = 4096;
8790         } else {
8791                 dev->mode_config.max_width = 8192;
8792                 dev->mode_config.max_height = 8192;
8793         }
8794         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8795
8796         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8797                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8798
8799         for (i = 0; i < dev_priv->num_pipe; i++) {
8800                 intel_crtc_init(dev, i);
8801                 ret = intel_plane_init(dev, i);
8802                 if (ret)
8803                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8804         }
8805
8806         intel_cpu_pll_init(dev);
8807         intel_pch_pll_init(dev);
8808
8809         /* Just disable it once at startup */
8810         i915_disable_vga(dev);
8811         intel_setup_outputs(dev);
8812 }
8813
8814 static void
8815 intel_connector_break_all_links(struct intel_connector *connector)
8816 {
8817         connector->base.dpms = DRM_MODE_DPMS_OFF;
8818         connector->base.encoder = NULL;
8819         connector->encoder->connectors_active = false;
8820         connector->encoder->base.crtc = NULL;
8821 }
8822
8823 static void intel_enable_pipe_a(struct drm_device *dev)
8824 {
8825         struct intel_connector *connector;
8826         struct drm_connector *crt = NULL;
8827         struct intel_load_detect_pipe load_detect_temp;
8828
8829         /* We can't just switch on the pipe A, we need to set things up with a
8830          * proper mode and output configuration. As a gross hack, enable pipe A
8831          * by enabling the load detect pipe once. */
8832         list_for_each_entry(connector,
8833                             &dev->mode_config.connector_list,
8834                             base.head) {
8835                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8836                         crt = &connector->base;
8837                         break;
8838                 }
8839         }
8840
8841         if (!crt)
8842                 return;
8843
8844         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8845                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8846
8847
8848 }
8849
8850 static bool
8851 intel_check_plane_mapping(struct intel_crtc *crtc)
8852 {
8853         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8854         u32 reg, val;
8855
8856         if (dev_priv->num_pipe == 1)
8857                 return true;
8858
8859         reg = DSPCNTR(!crtc->plane);
8860         val = I915_READ(reg);
8861
8862         if ((val & DISPLAY_PLANE_ENABLE) &&
8863             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8864                 return false;
8865
8866         return true;
8867 }
8868
8869 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8870 {
8871         struct drm_device *dev = crtc->base.dev;
8872         struct drm_i915_private *dev_priv = dev->dev_private;
8873         u32 reg;
8874
8875         /* Clear any frame start delays used for debugging left by the BIOS */
8876         reg = PIPECONF(crtc->cpu_transcoder);
8877         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8878
8879         /* We need to sanitize the plane -> pipe mapping first because this will
8880          * disable the crtc (and hence change the state) if it is wrong. Note
8881          * that gen4+ has a fixed plane -> pipe mapping.  */
8882         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8883                 struct intel_connector *connector;
8884                 bool plane;
8885
8886                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8887                               crtc->base.base.id);
8888
8889                 /* Pipe has the wrong plane attached and the plane is active.
8890                  * Temporarily change the plane mapping and disable everything
8891                  * ...  */
8892                 plane = crtc->plane;
8893                 crtc->plane = !plane;
8894                 dev_priv->display.crtc_disable(&crtc->base);
8895                 crtc->plane = plane;
8896
8897                 /* ... and break all links. */
8898                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8899                                     base.head) {
8900                         if (connector->encoder->base.crtc != &crtc->base)
8901                                 continue;
8902
8903                         intel_connector_break_all_links(connector);
8904                 }
8905
8906                 WARN_ON(crtc->active);
8907                 crtc->base.enabled = false;
8908         }
8909
8910         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8911             crtc->pipe == PIPE_A && !crtc->active) {
8912                 /* BIOS forgot to enable pipe A, this mostly happens after
8913                  * resume. Force-enable the pipe to fix this, the update_dpms
8914                  * call below we restore the pipe to the right state, but leave
8915                  * the required bits on. */
8916                 intel_enable_pipe_a(dev);
8917         }
8918
8919         /* Adjust the state of the output pipe according to whether we
8920          * have active connectors/encoders. */
8921         intel_crtc_update_dpms(&crtc->base);
8922
8923         if (crtc->active != crtc->base.enabled) {
8924                 struct intel_encoder *encoder;
8925
8926                 /* This can happen either due to bugs in the get_hw_state
8927                  * functions or because the pipe is force-enabled due to the
8928                  * pipe A quirk. */
8929                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8930                               crtc->base.base.id,
8931                               crtc->base.enabled ? "enabled" : "disabled",
8932                               crtc->active ? "enabled" : "disabled");
8933
8934                 crtc->base.enabled = crtc->active;
8935
8936                 /* Because we only establish the connector -> encoder ->
8937                  * crtc links if something is active, this means the
8938                  * crtc is now deactivated. Break the links. connector
8939                  * -> encoder links are only establish when things are
8940                  *  actually up, hence no need to break them. */
8941                 WARN_ON(crtc->active);
8942
8943                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8944                         WARN_ON(encoder->connectors_active);
8945                         encoder->base.crtc = NULL;
8946                 }
8947         }
8948 }
8949
8950 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8951 {
8952         struct intel_connector *connector;
8953         struct drm_device *dev = encoder->base.dev;
8954
8955         /* We need to check both for a crtc link (meaning that the
8956          * encoder is active and trying to read from a pipe) and the
8957          * pipe itself being active. */
8958         bool has_active_crtc = encoder->base.crtc &&
8959                 to_intel_crtc(encoder->base.crtc)->active;
8960
8961         if (encoder->connectors_active && !has_active_crtc) {
8962                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8963                               encoder->base.base.id,
8964                               drm_get_encoder_name(&encoder->base));
8965
8966                 /* Connector is active, but has no active pipe. This is
8967                  * fallout from our resume register restoring. Disable
8968                  * the encoder manually again. */
8969                 if (encoder->base.crtc) {
8970                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8971                                       encoder->base.base.id,
8972                                       drm_get_encoder_name(&encoder->base));
8973                         encoder->disable(encoder);
8974                 }
8975
8976                 /* Inconsistent output/port/pipe state happens presumably due to
8977                  * a bug in one of the get_hw_state functions. Or someplace else
8978                  * in our code, like the register restore mess on resume. Clamp
8979                  * things to off as a safer default. */
8980                 list_for_each_entry(connector,
8981                                     &dev->mode_config.connector_list,
8982                                     base.head) {
8983                         if (connector->encoder != encoder)
8984                                 continue;
8985
8986                         intel_connector_break_all_links(connector);
8987                 }
8988         }
8989         /* Enabled encoders without active connectors will be fixed in
8990          * the crtc fixup. */
8991 }
8992
8993 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8994  * and i915 state tracking structures. */
8995 void intel_modeset_setup_hw_state(struct drm_device *dev)
8996 {
8997         struct drm_i915_private *dev_priv = dev->dev_private;
8998         enum pipe pipe;
8999         u32 tmp;
9000         struct intel_crtc *crtc;
9001         struct intel_encoder *encoder;
9002         struct intel_connector *connector;
9003
9004         if (IS_HASWELL(dev)) {
9005                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9006
9007                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9008                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9009                         case TRANS_DDI_EDP_INPUT_A_ON:
9010                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9011                                 pipe = PIPE_A;
9012                                 break;
9013                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9014                                 pipe = PIPE_B;
9015                                 break;
9016                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9017                                 pipe = PIPE_C;
9018                                 break;
9019                         }
9020
9021                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9022                         crtc->cpu_transcoder = TRANSCODER_EDP;
9023
9024                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9025                                       pipe_name(pipe));
9026                 }
9027         }
9028
9029         for_each_pipe(pipe) {
9030                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9031
9032                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9033                 if (tmp & PIPECONF_ENABLE)
9034                         crtc->active = true;
9035                 else
9036                         crtc->active = false;
9037
9038                 crtc->base.enabled = crtc->active;
9039
9040                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9041                               crtc->base.base.id,
9042                               crtc->active ? "enabled" : "disabled");
9043         }
9044
9045         if (IS_HASWELL(dev))
9046                 intel_ddi_setup_hw_pll_state(dev);
9047
9048         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9049                             base.head) {
9050                 pipe = 0;
9051
9052                 if (encoder->get_hw_state(encoder, &pipe)) {
9053                         encoder->base.crtc =
9054                                 dev_priv->pipe_to_crtc_mapping[pipe];
9055                 } else {
9056                         encoder->base.crtc = NULL;
9057                 }
9058
9059                 encoder->connectors_active = false;
9060                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9061                               encoder->base.base.id,
9062                               drm_get_encoder_name(&encoder->base),
9063                               encoder->base.crtc ? "enabled" : "disabled",
9064                               pipe);
9065         }
9066
9067         list_for_each_entry(connector, &dev->mode_config.connector_list,
9068                             base.head) {
9069                 if (connector->get_hw_state(connector)) {
9070                         connector->base.dpms = DRM_MODE_DPMS_ON;
9071                         connector->encoder->connectors_active = true;
9072                         connector->base.encoder = &connector->encoder->base;
9073                 } else {
9074                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9075                         connector->base.encoder = NULL;
9076                 }
9077                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9078                               connector->base.base.id,
9079                               drm_get_connector_name(&connector->base),
9080                               connector->base.encoder ? "enabled" : "disabled");
9081         }
9082
9083         /* HW state is read out, now we need to sanitize this mess. */
9084         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9085                             base.head) {
9086                 intel_sanitize_encoder(encoder);
9087         }
9088
9089         for_each_pipe(pipe) {
9090                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9091                 intel_sanitize_crtc(crtc);
9092         }
9093
9094         intel_modeset_update_staged_output_state(dev);
9095
9096         intel_modeset_check_state(dev);
9097
9098         drm_mode_config_reset(dev);
9099 }
9100
9101 void intel_modeset_gem_init(struct drm_device *dev)
9102 {
9103         intel_modeset_init_hw(dev);
9104
9105         intel_setup_overlay(dev);
9106
9107         intel_modeset_setup_hw_state(dev);
9108 }
9109
9110 void intel_modeset_cleanup(struct drm_device *dev)
9111 {
9112         struct drm_i915_private *dev_priv = dev->dev_private;
9113         struct drm_crtc *crtc;
9114         struct intel_crtc *intel_crtc;
9115
9116         drm_kms_helper_poll_fini(dev);
9117         mutex_lock(&dev->struct_mutex);
9118
9119         intel_unregister_dsm_handler();
9120
9121
9122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9123                 /* Skip inactive CRTCs */
9124                 if (!crtc->fb)
9125                         continue;
9126
9127                 intel_crtc = to_intel_crtc(crtc);
9128                 intel_increase_pllclock(crtc);
9129         }
9130
9131         intel_disable_fbc(dev);
9132
9133         intel_disable_gt_powersave(dev);
9134
9135         ironlake_teardown_rc6(dev);
9136
9137         if (IS_VALLEYVIEW(dev))
9138                 vlv_init_dpio(dev);
9139
9140         mutex_unlock(&dev->struct_mutex);
9141
9142         /* Disable the irq before mode object teardown, for the irq might
9143          * enqueue unpin/hotplug work. */
9144         drm_irq_uninstall(dev);
9145         cancel_work_sync(&dev_priv->hotplug_work);
9146         cancel_work_sync(&dev_priv->rps.work);
9147
9148         /* flush any delayed tasks or pending work */
9149         flush_scheduled_work();
9150
9151         drm_mode_config_cleanup(dev);
9152 }
9153
9154 /*
9155  * Return which encoder is currently attached for connector.
9156  */
9157 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9158 {
9159         return &intel_attached_encoder(connector)->base;
9160 }
9161
9162 void intel_connector_attach_encoder(struct intel_connector *connector,
9163                                     struct intel_encoder *encoder)
9164 {
9165         connector->encoder = encoder;
9166         drm_mode_connector_attach_encoder(&connector->base,
9167                                           &encoder->base);
9168 }
9169
9170 /*
9171  * set vga decode state - true == enable VGA decode
9172  */
9173 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9174 {
9175         struct drm_i915_private *dev_priv = dev->dev_private;
9176         u16 gmch_ctrl;
9177
9178         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9179         if (state)
9180                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9181         else
9182                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9183         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9184         return 0;
9185 }
9186
9187 #ifdef CONFIG_DEBUG_FS
9188 #include <linux/seq_file.h>
9189
9190 struct intel_display_error_state {
9191         struct intel_cursor_error_state {
9192                 u32 control;
9193                 u32 position;
9194                 u32 base;
9195                 u32 size;
9196         } cursor[I915_MAX_PIPES];
9197
9198         struct intel_pipe_error_state {
9199                 u32 conf;
9200                 u32 source;
9201
9202                 u32 htotal;
9203                 u32 hblank;
9204                 u32 hsync;
9205                 u32 vtotal;
9206                 u32 vblank;
9207                 u32 vsync;
9208         } pipe[I915_MAX_PIPES];
9209
9210         struct intel_plane_error_state {
9211                 u32 control;
9212                 u32 stride;
9213                 u32 size;
9214                 u32 pos;
9215                 u32 addr;
9216                 u32 surface;
9217                 u32 tile_offset;
9218         } plane[I915_MAX_PIPES];
9219 };
9220
9221 struct intel_display_error_state *
9222 intel_display_capture_error_state(struct drm_device *dev)
9223 {
9224         drm_i915_private_t *dev_priv = dev->dev_private;
9225         struct intel_display_error_state *error;
9226         enum transcoder cpu_transcoder;
9227         int i;
9228
9229         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9230         if (error == NULL)
9231                 return NULL;
9232
9233         for_each_pipe(i) {
9234                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9235
9236                 error->cursor[i].control = I915_READ(CURCNTR(i));
9237                 error->cursor[i].position = I915_READ(CURPOS(i));
9238                 error->cursor[i].base = I915_READ(CURBASE(i));
9239
9240                 error->plane[i].control = I915_READ(DSPCNTR(i));
9241                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9242                 error->plane[i].size = I915_READ(DSPSIZE(i));
9243                 error->plane[i].pos = I915_READ(DSPPOS(i));
9244                 error->plane[i].addr = I915_READ(DSPADDR(i));
9245                 if (INTEL_INFO(dev)->gen >= 4) {
9246                         error->plane[i].surface = I915_READ(DSPSURF(i));
9247                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9248                 }
9249
9250                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9251                 error->pipe[i].source = I915_READ(PIPESRC(i));
9252                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9253                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9254                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9255                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9256                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9257                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9258         }
9259
9260         return error;
9261 }
9262
9263 void
9264 intel_display_print_error_state(struct seq_file *m,
9265                                 struct drm_device *dev,
9266                                 struct intel_display_error_state *error)
9267 {
9268         drm_i915_private_t *dev_priv = dev->dev_private;
9269         int i;
9270
9271         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9272         for_each_pipe(i) {
9273                 seq_printf(m, "Pipe [%d]:\n", i);
9274                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9275                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9276                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9277                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9278                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9279                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9280                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9281                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9282
9283                 seq_printf(m, "Plane [%d]:\n", i);
9284                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9285                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9286                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9287                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9288                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9289                 if (INTEL_INFO(dev)->gen >= 4) {
9290                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9291                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9292                 }
9293
9294                 seq_printf(m, "Cursor [%d]:\n", i);
9295                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9296                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9297                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9298         }
9299 }
9300 #endif