Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 4000000, .max = 5994000},
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 25000, .max = 270000 },
 397         .vco = { .min = 4000000, .max = 6000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 22, .max = 450 },
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         WARN(1, "pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380              && (val & DP_PIPEB_SELECT),
1381              "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385                                      enum pipe pipe, int reg)
1386 {
1387         u32 val = I915_READ(reg);
1388         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390              reg, pipe_name(pipe));
1391
1392         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393              && (val & SDVO_PIPE_B_SELECT),
1394              "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398                                       enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407         reg = PCH_ADPA;
1408         val = I915_READ(reg);
1409         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410              "PCH VGA enabled on transcoder %c, should be disabled\n",
1411              pipe_name(pipe));
1412
1413         reg = PCH_LVDS;
1414         val = I915_READ(reg);
1415         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425  * intel_enable_pll - enable a PLL
1426  * @dev_priv: i915 private structure
1427  * @pipe: pipe PLL to enable
1428  *
1429  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1430  * make sure the PLL reg is writable first though, since the panel write
1431  * protect mechanism may be enabled.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  *
1435  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436  */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439         int reg;
1440         u32 val;
1441
1442         /* No really, not for ILK+ */
1443         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445         /* PLL is protected by panel, make sure we can write it */
1446         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447                 assert_panel_unlocked(dev_priv, pipe);
1448
1449         reg = DPLL(pipe);
1450         val = I915_READ(reg);
1451         val |= DPLL_VCO_ENABLE;
1452
1453         /* We do this three times for luck */
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         udelay(150); /* wait for warmup */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466  * intel_disable_pll - disable a PLL
1467  * @dev_priv: i915 private structure
1468  * @pipe: pipe PLL to disable
1469  *
1470  * Disable the PLL for @pipe, making sure the pipe is off first.
1471  *
1472  * Note!  This is for pre-ILK only.
1473  */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476         int reg;
1477         u32 val;
1478
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         reg = DPLL(pipe);
1487         val = I915_READ(reg);
1488         val &= ~DPLL_VCO_ENABLE;
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497         unsigned long flags;
1498
1499         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501                                 100)) {
1502                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503                 goto out_unlock;
1504         }
1505
1506         I915_WRITE(SBI_ADDR,
1507                         (reg << 16));
1508         I915_WRITE(SBI_DATA,
1509                         value);
1510         I915_WRITE(SBI_CTL_STAT,
1511                         SBI_BUSY |
1512                         SBI_CTL_OP_CRWR);
1513
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517                 goto out_unlock;
1518         }
1519
1520 out_unlock:
1521         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527         unsigned long flags;
1528         u32 value = 0;
1529
1530         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532                                 100)) {
1533                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534                 goto out_unlock;
1535         }
1536
1537         I915_WRITE(SBI_ADDR,
1538                         (reg << 16));
1539         I915_WRITE(SBI_CTL_STAT,
1540                         SBI_BUSY |
1541                         SBI_CTL_OP_CRRD);
1542
1543         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544                                 100)) {
1545                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546                 goto out_unlock;
1547         }
1548
1549         value = I915_READ(SBI_DATA);
1550
1551 out_unlock:
1552         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553         return value;
1554 }
1555
1556 /**
1557  * intel_enable_pch_pll - enable PCH PLL
1558  * @dev_priv: i915 private structure
1559  * @pipe: pipe PLL to enable
1560  *
1561  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562  * drives the transcoder clock.
1563  */
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567         struct intel_pch_pll *pll;
1568         int reg;
1569         u32 val;
1570
1571         /* PCH PLLs only available on ILK, SNB and IVB */
1572         BUG_ON(dev_priv->info->gen < 5);
1573         pll = intel_crtc->pch_pll;
1574         if (pll == NULL)
1575                 return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         /* PCH refclock must be enabled first */
1585         assert_pch_refclk_enabled(dev_priv);
1586
1587         if (pll->active++ && pll->on) {
1588                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1589                 return;
1590         }
1591
1592         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594         reg = pll->pll_reg;
1595         val = I915_READ(reg);
1596         val |= DPLL_VCO_ENABLE;
1597         I915_WRITE(reg, val);
1598         POSTING_READ(reg);
1599         udelay(200);
1600
1601         pll->on = true;
1602 }
1603
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608         int reg;
1609         u32 val;
1610
1611         /* PCH only available on ILK+ */
1612         BUG_ON(dev_priv->info->gen < 5);
1613         if (pll == NULL)
1614                return;
1615
1616         if (WARN_ON(pll->refcount == 0))
1617                 return;
1618
1619         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620                       pll->pll_reg, pll->active, pll->on,
1621                       intel_crtc->base.base.id);
1622
1623         if (WARN_ON(pll->active == 0)) {
1624                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1625                 return;
1626         }
1627
1628         if (--pll->active) {
1629                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1630                 return;
1631         }
1632
1633         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635         /* Make sure transcoder isn't still depending on us */
1636         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637
1638         reg = pll->pll_reg;
1639         val = I915_READ(reg);
1640         val &= ~DPLL_VCO_ENABLE;
1641         I915_WRITE(reg, val);
1642         POSTING_READ(reg);
1643         udelay(200);
1644
1645         pll->on = false;
1646 }
1647
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649                                     enum pipe pipe)
1650 {
1651         int reg;
1652         u32 val, pipeconf_val;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654
1655         /* PCH only available on ILK+ */
1656         BUG_ON(dev_priv->info->gen < 5);
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_pch_pll_enabled(dev_priv,
1660                                to_intel_crtc(crtc)->pch_pll,
1661                                to_intel_crtc(crtc));
1662
1663         /* FDI must be feeding us bits for PCH ports */
1664         assert_fdi_tx_enabled(dev_priv, pipe);
1665         assert_fdi_rx_enabled(dev_priv, pipe);
1666
1667         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669                 return;
1670         }
1671         reg = TRANSCONF(pipe);
1672         val = I915_READ(reg);
1673         pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675         if (HAS_PCH_IBX(dev_priv->dev)) {
1676                 /*
1677                  * make the BPC in transcoder be consistent with
1678                  * that in pipeconf reg.
1679                  */
1680                 val &= ~PIPE_BPC_MASK;
1681                 val |= pipeconf_val & PIPE_BPC_MASK;
1682         }
1683
1684         val &= ~TRANS_INTERLACE_MASK;
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686                 if (HAS_PCH_IBX(dev_priv->dev) &&
1687                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688                         val |= TRANS_LEGACY_INTERLACED_ILK;
1689                 else
1690                         val |= TRANS_INTERLACED;
1691         else
1692                 val |= TRANS_PROGRESSIVE;
1693
1694         I915_WRITE(reg, val | TRANS_ENABLE);
1695         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700                                      enum pipe pipe)
1701 {
1702         int reg;
1703         u32 val;
1704
1705         /* FDI relies on the transcoder */
1706         assert_fdi_tx_disabled(dev_priv, pipe);
1707         assert_fdi_rx_disabled(dev_priv, pipe);
1708
1709         /* Ports must be off as well */
1710         assert_pch_ports_disabled(dev_priv, pipe);
1711
1712         reg = TRANSCONF(pipe);
1713         val = I915_READ(reg);
1714         val &= ~TRANS_ENABLE;
1715         I915_WRITE(reg, val);
1716         /* wait for PCH transcoder off, transcoder state */
1717         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720
1721 /**
1722  * intel_enable_pipe - enable a pipe, asserting requirements
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe to enable
1725  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726  *
1727  * Enable @pipe, making sure that various hardware specific requirements
1728  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729  *
1730  * @pipe should be %PIPE_A or %PIPE_B.
1731  *
1732  * Will wait until the pipe is actually running (i.e. first vblank) before
1733  * returning.
1734  */
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736                               bool pch_port)
1737 {
1738         int reg;
1739         u32 val;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 assert_pll_enabled(dev_priv, pipe);
1748         else {
1749                 if (pch_port) {
1750                         /* if driving the PCH, we need FDI enabled */
1751                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753                 }
1754                 /* FIXME: assert CPU port conditions for SNB+ */
1755         }
1756
1757         reg = PIPECONF(pipe);
1758         val = I915_READ(reg);
1759         if (val & PIPECONF_ENABLE)
1760                 return;
1761
1762         I915_WRITE(reg, val | PIPECONF_ENABLE);
1763         intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765
1766 /**
1767  * intel_disable_pipe - disable a pipe, asserting requirements
1768  * @dev_priv: i915 private structure
1769  * @pipe: pipe to disable
1770  *
1771  * Disable @pipe, making sure that various hardware specific requirements
1772  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773  *
1774  * @pipe should be %PIPE_A or %PIPE_B.
1775  *
1776  * Will wait until the pipe has shut down before returning.
1777  */
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779                                enum pipe pipe)
1780 {
1781         int reg;
1782         u32 val;
1783
1784         /*
1785          * Make sure planes won't keep trying to pump pixels to us,
1786          * or we might hang the display.
1787          */
1788         assert_planes_disabled(dev_priv, pipe);
1789
1790         /* Don't disable pipe A or pipe A PLLs if needed */
1791         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792                 return;
1793
1794         reg = PIPECONF(pipe);
1795         val = I915_READ(reg);
1796         if ((val & PIPECONF_ENABLE) == 0)
1797                 return;
1798
1799         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802
1803 /*
1804  * Plane regs are double buffered, going from enabled->disabled needs a
1805  * trigger in order to latch.  The display address reg provides this.
1806  */
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808                                       enum plane plane)
1809 {
1810         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813
1814 /**
1815  * intel_enable_plane - enable a display plane on a given pipe
1816  * @dev_priv: i915 private structure
1817  * @plane: plane to enable
1818  * @pipe: pipe being fed
1819  *
1820  * Enable @plane on @pipe, making sure that @pipe is running first.
1821  */
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823                                enum plane plane, enum pipe pipe)
1824 {
1825         int reg;
1826         u32 val;
1827
1828         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829         assert_pipe_enabled(dev_priv, pipe);
1830
1831         reg = DSPCNTR(plane);
1832         val = I915_READ(reg);
1833         if (val & DISPLAY_PLANE_ENABLE)
1834                 return;
1835
1836         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837         intel_flush_display_plane(dev_priv, plane);
1838         intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840
1841 /**
1842  * intel_disable_plane - disable a display plane
1843  * @dev_priv: i915 private structure
1844  * @plane: plane to disable
1845  * @pipe: pipe consuming the data
1846  *
1847  * Disable @plane; should be an independent operation.
1848  */
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850                                 enum plane plane, enum pipe pipe)
1851 {
1852         int reg;
1853         u32 val;
1854
1855         reg = DSPCNTR(plane);
1856         val = I915_READ(reg);
1857         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858                 return;
1859
1860         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861         intel_flush_display_plane(dev_priv, plane);
1862         intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864
1865 int
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867                            struct drm_i915_gem_object *obj,
1868                            struct intel_ring_buffer *pipelined)
1869 {
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         u32 alignment;
1872         int ret;
1873
1874         switch (obj->tiling_mode) {
1875         case I915_TILING_NONE:
1876                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877                         alignment = 128 * 1024;
1878                 else if (INTEL_INFO(dev)->gen >= 4)
1879                         alignment = 4 * 1024;
1880                 else
1881                         alignment = 64 * 1024;
1882                 break;
1883         case I915_TILING_X:
1884                 /* pin() will align the object as required by fence */
1885                 alignment = 0;
1886                 break;
1887         case I915_TILING_Y:
1888                 /* FIXME: Is this true? */
1889                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890                 return -EINVAL;
1891         default:
1892                 BUG();
1893         }
1894
1895         dev_priv->mm.interruptible = false;
1896         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897         if (ret)
1898                 goto err_interruptible;
1899
1900         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901          * fence, whereas 965+ only requires a fence if using
1902          * framebuffer compression.  For simplicity, we always install
1903          * a fence as the cost is not that onerous.
1904          */
1905         ret = i915_gem_object_get_fence(obj);
1906         if (ret)
1907                 goto err_unpin;
1908
1909         i915_gem_object_pin_fence(obj);
1910
1911         dev_priv->mm.interruptible = true;
1912         return 0;
1913
1914 err_unpin:
1915         i915_gem_object_unpin(obj);
1916 err_interruptible:
1917         dev_priv->mm.interruptible = true;
1918         return ret;
1919 }
1920
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922 {
1923         i915_gem_object_unpin_fence(obj);
1924         i915_gem_object_unpin(obj);
1925 }
1926
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928  * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930                                                         unsigned int bpp,
1931                                                         unsigned int pitch)
1932 {
1933         int tile_rows, tiles;
1934
1935         tile_rows = *y / 8;
1936         *y %= 8;
1937         tiles = *x / (512/bpp);
1938         *x %= 512/bpp;
1939
1940         return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long linear_offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000
2001         if (INTEL_INFO(dev)->gen >= 4) {
2002                 intel_crtc->dspaddr_offset =
2003                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004                                                            fb->bits_per_pixel / 8,
2005                                                            fb->pitches[0]);
2006                 linear_offset -= intel_crtc->dspaddr_offset;
2007         } else {
2008                 intel_crtc->dspaddr_offset = linear_offset;
2009         }
2010
2011         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014         if (INTEL_INFO(dev)->gen >= 4) {
2015                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2017                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2019         } else
2020                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021         POSTING_READ(reg);
2022
2023         return 0;
2024 }
2025
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027                                  struct drm_framebuffer *fb, int x, int y)
2028 {
2029         struct drm_device *dev = crtc->dev;
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032         struct intel_framebuffer *intel_fb;
2033         struct drm_i915_gem_object *obj;
2034         int plane = intel_crtc->plane;
2035         unsigned long linear_offset;
2036         u32 dspcntr;
2037         u32 reg;
2038
2039         switch (plane) {
2040         case 0:
2041         case 1:
2042         case 2:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth != 16)
2062                         return -EINVAL;
2063
2064                 dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 if (fb->depth == 24)
2069                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070                 else if (fb->depth == 30)
2071                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072                 else
2073                         return -EINVAL;
2074                 break;
2075         default:
2076                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077                 return -EINVAL;
2078         }
2079
2080         if (obj->tiling_mode != I915_TILING_NONE)
2081                 dspcntr |= DISPPLANE_TILED;
2082         else
2083                 dspcntr &= ~DISPPLANE_TILED;
2084
2085         /* must disable */
2086         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088         I915_WRITE(reg, dspcntr);
2089
2090         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091         intel_crtc->dspaddr_offset =
2092                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093                                                    fb->bits_per_pixel / 8,
2094                                                    fb->pitches[0]);
2095         linear_offset -= intel_crtc->dspaddr_offset;
2096
2097         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100         I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2102         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103         I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         POSTING_READ(reg);
2105
2106         return 0;
2107 }
2108
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112                            int x, int y, enum mode_set_atomic state)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117         if (dev_priv->display.disable_fbc)
2118                 dev_priv->display.disable_fbc(dev);
2119         intel_increase_pllclock(crtc);
2120
2121         return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129         bool was_interruptible = dev_priv->mm.interruptible;
2130         int ret;
2131
2132         wait_event(dev_priv->pending_flip_queue,
2133                    atomic_read(&dev_priv->mm.wedged) ||
2134                    atomic_read(&obj->pending_flip) == 0);
2135
2136         /* Big Hammer, we also need to ensure that any pending
2137          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138          * current scanout is retired before unpinning the old
2139          * framebuffer.
2140          *
2141          * This should only fail upon a hung GPU, in which case we
2142          * can safely continue.
2143          */
2144         dev_priv->mm.interruptible = false;
2145         ret = i915_gem_object_finish_gpu(obj);
2146         dev_priv->mm.interruptible = was_interruptible;
2147
2148         return ret;
2149 }
2150
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153                     struct drm_framebuffer *fb)
2154 {
2155         struct drm_device *dev = crtc->dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct drm_i915_master_private *master_priv;
2158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159         struct drm_framebuffer *old_fb;
2160         int ret;
2161
2162         /* no fb bound */
2163         if (!fb) {
2164                 DRM_ERROR("No FB bound\n");
2165                 return 0;
2166         }
2167
2168         if(intel_crtc->plane > dev_priv->num_pipe) {
2169                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170                                 intel_crtc->plane,
2171                                 dev_priv->num_pipe);
2172                 return -EINVAL;
2173         }
2174
2175         mutex_lock(&dev->struct_mutex);
2176         ret = intel_pin_and_fence_fb_obj(dev,
2177                                          to_intel_framebuffer(fb)->obj,
2178                                          NULL);
2179         if (ret != 0) {
2180                 mutex_unlock(&dev->struct_mutex);
2181                 DRM_ERROR("pin & fence failed\n");
2182                 return ret;
2183         }
2184
2185         if (crtc->fb)
2186                 intel_finish_fb(crtc->fb);
2187
2188         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189         if (ret) {
2190                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191                 mutex_unlock(&dev->struct_mutex);
2192                 DRM_ERROR("failed to update base address\n");
2193                 return ret;
2194         }
2195
2196         old_fb = crtc->fb;
2197         crtc->fb = fb;
2198         crtc->x = x;
2199         crtc->y = y;
2200
2201         if (old_fb) {
2202                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204         }
2205
2206         intel_update_fbc(dev);
2207         mutex_unlock(&dev->struct_mutex);
2208
2209         if (!dev->primary->master)
2210                 return 0;
2211
2212         master_priv = dev->primary->master->driver_priv;
2213         if (!master_priv->sarea_priv)
2214                 return 0;
2215
2216         if (intel_crtc->pipe) {
2217                 master_priv->sarea_priv->pipeB_x = x;
2218                 master_priv->sarea_priv->pipeB_y = y;
2219         } else {
2220                 master_priv->sarea_priv->pipeA_x = x;
2221                 master_priv->sarea_priv->pipeA_y = y;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         u32 dpa_ctl;
2232
2233         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234         dpa_ctl = I915_READ(DP_A);
2235         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237         if (clock < 200000) {
2238                 u32 temp;
2239                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240                 /* workaround for 160Mhz:
2241                    1) program 0x4600c bits 15:0 = 0x8124
2242                    2) program 0x46010 bit 0 = 1
2243                    3) program 0x46034 bit 24 = 1
2244                    4) program 0x64000 bit 14 = 1
2245                    */
2246                 temp = I915_READ(0x4600c);
2247                 temp &= 0xffff0000;
2248                 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250                 temp = I915_READ(0x46010);
2251                 I915_WRITE(0x46010, temp | 1);
2252
2253                 temp = I915_READ(0x46034);
2254                 I915_WRITE(0x46034, temp | (1 << 24));
2255         } else {
2256                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257         }
2258         I915_WRITE(DP_A, dpa_ctl);
2259
2260         POSTING_READ(DP_A);
2261         udelay(500);
2262 }
2263
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269         int pipe = intel_crtc->pipe;
2270         u32 reg, temp;
2271
2272         /* enable normal train */
2273         reg = FDI_TX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         if (IS_IVYBRIDGE(dev)) {
2276                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278         } else {
2279                 temp &= ~FDI_LINK_TRAIN_NONE;
2280                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281         }
2282         I915_WRITE(reg, temp);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         if (HAS_PCH_CPT(dev)) {
2287                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289         } else {
2290                 temp &= ~FDI_LINK_TRAIN_NONE;
2291                 temp |= FDI_LINK_TRAIN_NONE;
2292         }
2293         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295         /* wait one idle pattern time */
2296         POSTING_READ(reg);
2297         udelay(1000);
2298
2299         /* IVB wants error correction enabled */
2300         if (IS_IVYBRIDGE(dev))
2301                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302                            FDI_FE_ERRC_ENABLE);
2303 }
2304
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310         flags |= FDI_PHASE_SYNC_OVR(pipe);
2311         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312         flags |= FDI_PHASE_SYNC_EN(pipe);
2313         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314         POSTING_READ(SOUTH_CHICKEN1);
2315 }
2316
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325         u32 reg, temp, tries;
2326
2327         /* FDI needs bits from pipe & plane first */
2328         assert_pipe_enabled(dev_priv, pipe);
2329         assert_plane_enabled(dev_priv, plane);
2330
2331         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332            for train result */
2333         reg = FDI_RX_IMR(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~FDI_RX_SYMBOL_LOCK;
2336         temp &= ~FDI_RX_BIT_LOCK;
2337         I915_WRITE(reg, temp);
2338         I915_READ(reg);
2339         udelay(150);
2340
2341         /* enable CPU FDI TX and PCH FDI RX */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~(7 << 19);
2345         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346         temp &= ~FDI_LINK_TRAIN_NONE;
2347         temp |= FDI_LINK_TRAIN_PATTERN_1;
2348         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         temp &= ~FDI_LINK_TRAIN_NONE;
2353         temp |= FDI_LINK_TRAIN_PATTERN_1;
2354         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356         POSTING_READ(reg);
2357         udelay(150);
2358
2359         /* Ironlake workaround, enable clock pointer after FDI enable*/
2360         if (HAS_PCH_IBX(dev)) {
2361                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                            FDI_RX_PHASE_SYNC_POINTER_EN);
2364         }
2365
2366         reg = FDI_RX_IIR(pipe);
2367         for (tries = 0; tries < 5; tries++) {
2368                 temp = I915_READ(reg);
2369                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371                 if ((temp & FDI_RX_BIT_LOCK)) {
2372                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2373                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374                         break;
2375                 }
2376         }
2377         if (tries == 5)
2378                 DRM_ERROR("FDI train 1 fail!\n");
2379
2380         /* Train 2 */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_LINK_TRAIN_NONE;
2384         temp |= FDI_LINK_TRAIN_PATTERN_2;
2385         I915_WRITE(reg, temp);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_2;
2391         I915_WRITE(reg, temp);
2392
2393         POSTING_READ(reg);
2394         udelay(150);
2395
2396         reg = FDI_RX_IIR(pipe);
2397         for (tries = 0; tries < 5; tries++) {
2398                 temp = I915_READ(reg);
2399                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401                 if (temp & FDI_RX_SYMBOL_LOCK) {
2402                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2404                         break;
2405                 }
2406         }
2407         if (tries == 5)
2408                 DRM_ERROR("FDI train 2 fail!\n");
2409
2410         DRM_DEBUG_KMS("FDI train done\n");
2411
2412 }
2413
2414 static const int snb_b_fdi_train_param[] = {
2415         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419 };
2420
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424         struct drm_device *dev = crtc->dev;
2425         struct drm_i915_private *dev_priv = dev->dev_private;
2426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427         int pipe = intel_crtc->pipe;
2428         u32 reg, temp, i, retry;
2429
2430         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431            for train result */
2432         reg = FDI_RX_IMR(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_RX_SYMBOL_LOCK;
2435         temp &= ~FDI_RX_BIT_LOCK;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         /* enable CPU FDI TX and PCH FDI RX */
2442         reg = FDI_TX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~(7 << 19);
2445         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446         temp &= ~FDI_LINK_TRAIN_NONE;
2447         temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449         /* SNB-B */
2450         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452
2453         reg = FDI_RX_CTL(pipe);
2454         temp = I915_READ(reg);
2455         if (HAS_PCH_CPT(dev)) {
2456                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458         } else {
2459                 temp &= ~FDI_LINK_TRAIN_NONE;
2460                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461         }
2462         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464         POSTING_READ(reg);
2465         udelay(150);
2466
2467         if (HAS_PCH_CPT(dev))
2468                 cpt_phase_pointer_enable(dev, pipe);
2469
2470         for (i = 0; i < 4; i++) {
2471                 reg = FDI_TX_CTL(pipe);
2472                 temp = I915_READ(reg);
2473                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474                 temp |= snb_b_fdi_train_param[i];
2475                 I915_WRITE(reg, temp);
2476
2477                 POSTING_READ(reg);
2478                 udelay(500);
2479
2480                 for (retry = 0; retry < 5; retry++) {
2481                         reg = FDI_RX_IIR(pipe);
2482                         temp = I915_READ(reg);
2483                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484                         if (temp & FDI_RX_BIT_LOCK) {
2485                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487                                 break;
2488                         }
2489                         udelay(50);
2490                 }
2491                 if (retry < 5)
2492                         break;
2493         }
2494         if (i == 4)
2495                 DRM_ERROR("FDI train 1 fail!\n");
2496
2497         /* Train 2 */
2498         reg = FDI_TX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_2;
2502         if (IS_GEN6(dev)) {
2503                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504                 /* SNB-B */
2505                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506         }
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         if (HAS_PCH_CPT(dev)) {
2512                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514         } else {
2515                 temp &= ~FDI_LINK_TRAIN_NONE;
2516                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517         }
2518         I915_WRITE(reg, temp);
2519
2520         POSTING_READ(reg);
2521         udelay(150);
2522
2523         for (i = 0; i < 4; i++) {
2524                 reg = FDI_TX_CTL(pipe);
2525                 temp = I915_READ(reg);
2526                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527                 temp |= snb_b_fdi_train_param[i];
2528                 I915_WRITE(reg, temp);
2529
2530                 POSTING_READ(reg);
2531                 udelay(500);
2532
2533                 for (retry = 0; retry < 5; retry++) {
2534                         reg = FDI_RX_IIR(pipe);
2535                         temp = I915_READ(reg);
2536                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537                         if (temp & FDI_RX_SYMBOL_LOCK) {
2538                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                                 break;
2541                         }
2542                         udelay(50);
2543                 }
2544                 if (retry < 5)
2545                         break;
2546         }
2547         if (i == 4)
2548                 DRM_ERROR("FDI train 2 fail!\n");
2549
2550         DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         struct drm_i915_private *dev_priv = dev->dev_private;
2558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559         int pipe = intel_crtc->pipe;
2560         u32 reg, temp, i;
2561
2562         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563            for train result */
2564         reg = FDI_RX_IMR(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~FDI_RX_SYMBOL_LOCK;
2567         temp &= ~FDI_RX_BIT_LOCK;
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         /* enable CPU FDI TX and PCH FDI RX */
2574         reg = FDI_TX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~(7 << 19);
2577         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         temp |= FDI_COMPOSITE_SYNC;
2583         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~FDI_LINK_TRAIN_AUTO;
2588         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         temp |= FDI_COMPOSITE_SYNC;
2591         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593         POSTING_READ(reg);
2594         udelay(150);
2595
2596         if (HAS_PCH_CPT(dev))
2597                 cpt_phase_pointer_enable(dev, pipe);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 reg = FDI_RX_IIR(pipe);
2610                 temp = I915_READ(reg);
2611                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613                 if (temp & FDI_RX_BIT_LOCK ||
2614                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2617                         break;
2618                 }
2619         }
2620         if (i == 4)
2621                 DRM_ERROR("FDI train 1 fail!\n");
2622
2623         /* Train 2 */
2624         reg = FDI_TX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630         I915_WRITE(reg, temp);
2631
2632         reg = FDI_RX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669         struct drm_device *dev = intel_crtc->base.dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         int pipe = intel_crtc->pipe;
2672         u32 reg, temp;
2673
2674         /* Write the TU size bits so error detection works */
2675         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677
2678         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679         reg = FDI_RX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~((0x7 << 19) | (0x7 << 16));
2682         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686         POSTING_READ(reg);
2687         udelay(200);
2688
2689         /* Switch from Rawclk to PCDclk */
2690         temp = I915_READ(reg);
2691         I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693         POSTING_READ(reg);
2694         udelay(200);
2695
2696         /* On Haswell, the PLL configuration for ports and pipes is handled
2697          * separately, as part of DDI setup */
2698         if (!IS_HASWELL(dev)) {
2699                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700                 reg = FDI_TX_CTL(pipe);
2701                 temp = I915_READ(reg);
2702                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704
2705                         POSTING_READ(reg);
2706                         udelay(100);
2707                 }
2708         }
2709 }
2710
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* Switch from PCDclk to Rawclk */
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723         /* Disable CPU FDI TX PLL */
2724         reg = FDI_TX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728         POSTING_READ(reg);
2729         udelay(100);
2730
2731         reg = FDI_RX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735         /* Wait for the clocks to turn off. */
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749         POSTING_READ(SOUTH_CHICKEN1);
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759         /* disable CPU FDI tx and PCH FDI rx */
2760         reg = FDI_TX_CTL(pipe);
2761         temp = I915_READ(reg);
2762         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763         POSTING_READ(reg);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(0x7 << 16);
2768         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(100);
2773
2774         /* Ironlake workaround, disable clock pointer after downing FDI */
2775         if (HAS_PCH_IBX(dev)) {
2776                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778                            I915_READ(FDI_RX_CHICKEN(pipe) &
2779                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780         } else if (HAS_PCH_CPT(dev)) {
2781                 cpt_phase_pointer_disable(dev, pipe);
2782         }
2783
2784         /* still set train pattern 1 */
2785         reg = FDI_TX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         temp &= ~FDI_LINK_TRAIN_NONE;
2788         temp |= FDI_LINK_TRAIN_PATTERN_1;
2789         I915_WRITE(reg, temp);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         if (HAS_PCH_CPT(dev)) {
2794                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796         } else {
2797                 temp &= ~FDI_LINK_TRAIN_NONE;
2798                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         }
2800         /* BPC in FDI rx is consistent with that in PIPECONF */
2801         temp &= ~(0x07 << 16);
2802         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803         I915_WRITE(reg, temp);
2804
2805         POSTING_READ(reg);
2806         udelay(100);
2807 }
2808
2809 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         unsigned long flags;
2814         bool pending;
2815
2816         if (atomic_read(&dev_priv->mm.wedged))
2817                 return false;
2818
2819         spin_lock_irqsave(&dev->event_lock, flags);
2820         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821         spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823         return pending;
2824 }
2825
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830
2831         if (crtc->fb == NULL)
2832                 return;
2833
2834         wait_event(dev_priv->pending_flip_queue,
2835                    !intel_crtc_has_pending_flip(crtc));
2836
2837         mutex_lock(&dev->struct_mutex);
2838         intel_finish_fb(crtc->fb);
2839         mutex_unlock(&dev->struct_mutex);
2840 }
2841
2842 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2843 {
2844         struct drm_device *dev = crtc->dev;
2845         struct intel_encoder *intel_encoder;
2846
2847         /*
2848          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2849          * must be driven by its own crtc; no sharing is possible.
2850          */
2851         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2852
2853                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2854                  * CPU handles all others */
2855                 if (IS_HASWELL(dev)) {
2856                         /* It is still unclear how this will work on PPT, so throw up a warning */
2857                         WARN_ON(!HAS_PCH_LPT(dev));
2858
2859                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2860                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2861                                 return true;
2862                         } else {
2863                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2864                                               intel_encoder->type);
2865                                 return false;
2866                         }
2867                 }
2868
2869                 switch (intel_encoder->type) {
2870                 case INTEL_OUTPUT_EDP:
2871                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2872                                 return false;
2873                         continue;
2874                 }
2875         }
2876
2877         return true;
2878 }
2879
2880 /* Program iCLKIP clock to the desired frequency */
2881 static void lpt_program_iclkip(struct drm_crtc *crtc)
2882 {
2883         struct drm_device *dev = crtc->dev;
2884         struct drm_i915_private *dev_priv = dev->dev_private;
2885         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2886         u32 temp;
2887
2888         /* It is necessary to ungate the pixclk gate prior to programming
2889          * the divisors, and gate it back when it is done.
2890          */
2891         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2892
2893         /* Disable SSCCTL */
2894         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2895                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2896                                         SBI_SSCCTL_DISABLE);
2897
2898         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2899         if (crtc->mode.clock == 20000) {
2900                 auxdiv = 1;
2901                 divsel = 0x41;
2902                 phaseinc = 0x20;
2903         } else {
2904                 /* The iCLK virtual clock root frequency is in MHz,
2905                  * but the crtc->mode.clock in in KHz. To get the divisors,
2906                  * it is necessary to divide one by another, so we
2907                  * convert the virtual clock precision to KHz here for higher
2908                  * precision.
2909                  */
2910                 u32 iclk_virtual_root_freq = 172800 * 1000;
2911                 u32 iclk_pi_range = 64;
2912                 u32 desired_divisor, msb_divisor_value, pi_value;
2913
2914                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2915                 msb_divisor_value = desired_divisor / iclk_pi_range;
2916                 pi_value = desired_divisor % iclk_pi_range;
2917
2918                 auxdiv = 0;
2919                 divsel = msb_divisor_value - 2;
2920                 phaseinc = pi_value;
2921         }
2922
2923         /* This should not happen with any sane values */
2924         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2925                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2926         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2927                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2928
2929         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2930                         crtc->mode.clock,
2931                         auxdiv,
2932                         divsel,
2933                         phasedir,
2934                         phaseinc);
2935
2936         /* Program SSCDIVINTPHASE6 */
2937         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2938         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2939         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2940         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2941         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2942         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2943         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2944
2945         intel_sbi_write(dev_priv,
2946                         SBI_SSCDIVINTPHASE6,
2947                         temp);
2948
2949         /* Program SSCAUXDIV */
2950         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2951         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2952         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2953         intel_sbi_write(dev_priv,
2954                         SBI_SSCAUXDIV6,
2955                         temp);
2956
2957
2958         /* Enable modulator and associated divider */
2959         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2960         temp &= ~SBI_SSCCTL_DISABLE;
2961         intel_sbi_write(dev_priv,
2962                         SBI_SSCCTL6,
2963                         temp);
2964
2965         /* Wait for initialization time */
2966         udelay(24);
2967
2968         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2969 }
2970
2971 /*
2972  * Enable PCH resources required for PCH ports:
2973  *   - PCH PLLs
2974  *   - FDI training & RX/TX
2975  *   - update transcoder timings
2976  *   - DP transcoding bits
2977  *   - transcoder
2978  */
2979 static void ironlake_pch_enable(struct drm_crtc *crtc)
2980 {
2981         struct drm_device *dev = crtc->dev;
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984         int pipe = intel_crtc->pipe;
2985         u32 reg, temp;
2986
2987         assert_transcoder_disabled(dev_priv, pipe);
2988
2989         /* For PCH output, training FDI link */
2990         dev_priv->display.fdi_link_train(crtc);
2991
2992         intel_enable_pch_pll(intel_crtc);
2993
2994         if (HAS_PCH_LPT(dev)) {
2995                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2996                 lpt_program_iclkip(crtc);
2997         } else if (HAS_PCH_CPT(dev)) {
2998                 u32 sel;
2999
3000                 temp = I915_READ(PCH_DPLL_SEL);
3001                 switch (pipe) {
3002                 default:
3003                 case 0:
3004                         temp |= TRANSA_DPLL_ENABLE;
3005                         sel = TRANSA_DPLLB_SEL;
3006                         break;
3007                 case 1:
3008                         temp |= TRANSB_DPLL_ENABLE;
3009                         sel = TRANSB_DPLLB_SEL;
3010                         break;
3011                 case 2:
3012                         temp |= TRANSC_DPLL_ENABLE;
3013                         sel = TRANSC_DPLLB_SEL;
3014                         break;
3015                 }
3016                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3017                         temp |= sel;
3018                 else
3019                         temp &= ~sel;
3020                 I915_WRITE(PCH_DPLL_SEL, temp);
3021         }
3022
3023         /* set transcoder timing, panel must allow it */
3024         assert_panel_unlocked(dev_priv, pipe);
3025         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3026         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3027         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3028
3029         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3030         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3031         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3032         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3033
3034         if (!IS_HASWELL(dev))
3035                 intel_fdi_normal_train(crtc);
3036
3037         /* For PCH DP, enable TRANS_DP_CTL */
3038         if (HAS_PCH_CPT(dev) &&
3039             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3040              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3041                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3042                 reg = TRANS_DP_CTL(pipe);
3043                 temp = I915_READ(reg);
3044                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3045                           TRANS_DP_SYNC_MASK |
3046                           TRANS_DP_BPC_MASK);
3047                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3048                          TRANS_DP_ENH_FRAMING);
3049                 temp |= bpc << 9; /* same format but at 11:9 */
3050
3051                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3052                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3053                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3054                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3055
3056                 switch (intel_trans_dp_port_sel(crtc)) {
3057                 case PCH_DP_B:
3058                         temp |= TRANS_DP_PORT_SEL_B;
3059                         break;
3060                 case PCH_DP_C:
3061                         temp |= TRANS_DP_PORT_SEL_C;
3062                         break;
3063                 case PCH_DP_D:
3064                         temp |= TRANS_DP_PORT_SEL_D;
3065                         break;
3066                 default:
3067                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3068                         temp |= TRANS_DP_PORT_SEL_B;
3069                         break;
3070                 }
3071
3072                 I915_WRITE(reg, temp);
3073         }
3074
3075         intel_enable_transcoder(dev_priv, pipe);
3076 }
3077
3078 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3079 {
3080         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3081
3082         if (pll == NULL)
3083                 return;
3084
3085         if (pll->refcount == 0) {
3086                 WARN(1, "bad PCH PLL refcount\n");
3087                 return;
3088         }
3089
3090         --pll->refcount;
3091         intel_crtc->pch_pll = NULL;
3092 }
3093
3094 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3095 {
3096         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3097         struct intel_pch_pll *pll;
3098         int i;
3099
3100         pll = intel_crtc->pch_pll;
3101         if (pll) {
3102                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3103                               intel_crtc->base.base.id, pll->pll_reg);
3104                 goto prepare;
3105         }
3106
3107         if (HAS_PCH_IBX(dev_priv->dev)) {
3108                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3109                 i = intel_crtc->pipe;
3110                 pll = &dev_priv->pch_plls[i];
3111
3112                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3113                               intel_crtc->base.base.id, pll->pll_reg);
3114
3115                 goto found;
3116         }
3117
3118         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119                 pll = &dev_priv->pch_plls[i];
3120
3121                 /* Only want to check enabled timings first */
3122                 if (pll->refcount == 0)
3123                         continue;
3124
3125                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3126                     fp == I915_READ(pll->fp0_reg)) {
3127                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3128                                       intel_crtc->base.base.id,
3129                                       pll->pll_reg, pll->refcount, pll->active);
3130
3131                         goto found;
3132                 }
3133         }
3134
3135         /* Ok no matching timings, maybe there's a free one? */
3136         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3137                 pll = &dev_priv->pch_plls[i];
3138                 if (pll->refcount == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3140                                       intel_crtc->base.base.id, pll->pll_reg);
3141                         goto found;
3142                 }
3143         }
3144
3145         return NULL;
3146
3147 found:
3148         intel_crtc->pch_pll = pll;
3149         pll->refcount++;
3150         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3151 prepare: /* separate function? */
3152         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3153
3154         /* Wait for the clocks to stabilize before rewriting the regs */
3155         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3156         POSTING_READ(pll->pll_reg);
3157         udelay(150);
3158
3159         I915_WRITE(pll->fp0_reg, fp);
3160         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3161         pll->on = false;
3162         return pll;
3163 }
3164
3165 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3169         u32 temp;
3170
3171         temp = I915_READ(dslreg);
3172         udelay(500);
3173         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3174                 /* Without this, mode sets may fail silently on FDI */
3175                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3176                 udelay(250);
3177                 I915_WRITE(tc2reg, 0);
3178                 if (wait_for(I915_READ(dslreg) != temp, 5))
3179                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3180         }
3181 }
3182
3183 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3184 {
3185         struct drm_device *dev = crtc->dev;
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188         struct intel_encoder *encoder;
3189         int pipe = intel_crtc->pipe;
3190         int plane = intel_crtc->plane;
3191         u32 temp;
3192         bool is_pch_port;
3193
3194         WARN_ON(!crtc->enabled);
3195
3196         if (intel_crtc->active)
3197                 return;
3198
3199         intel_crtc->active = true;
3200         intel_update_watermarks(dev);
3201
3202         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3203                 temp = I915_READ(PCH_LVDS);
3204                 if ((temp & LVDS_PORT_EN) == 0)
3205                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3206         }
3207
3208         is_pch_port = intel_crtc_driving_pch(crtc);
3209
3210         if (is_pch_port) {
3211                 ironlake_fdi_pll_enable(intel_crtc);
3212         } else {
3213                 assert_fdi_tx_disabled(dev_priv, pipe);
3214                 assert_fdi_rx_disabled(dev_priv, pipe);
3215         }
3216
3217         for_each_encoder_on_crtc(dev, crtc, encoder)
3218                 if (encoder->pre_enable)
3219                         encoder->pre_enable(encoder);
3220
3221         if (IS_HASWELL(dev))
3222                 intel_ddi_enable_pipe_clock(intel_crtc);
3223
3224         /* Enable panel fitting for LVDS */
3225         if (dev_priv->pch_pf_size &&
3226             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3227                 /* Force use of hard-coded filter coefficients
3228                  * as some pre-programmed values are broken,
3229                  * e.g. x201.
3230                  */
3231                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3232                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3233                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3234         }
3235
3236         /*
3237          * On ILK+ LUT must be loaded before the pipe is running but with
3238          * clocks enabled
3239          */
3240         intel_crtc_load_lut(crtc);
3241
3242         if (IS_HASWELL(dev)) {
3243                 intel_ddi_set_pipe_settings(crtc);
3244                 intel_ddi_enable_pipe_func(crtc);
3245         }
3246
3247         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3248         intel_enable_plane(dev_priv, plane, pipe);
3249
3250         if (is_pch_port)
3251                 ironlake_pch_enable(crtc);
3252
3253         mutex_lock(&dev->struct_mutex);
3254         intel_update_fbc(dev);
3255         mutex_unlock(&dev->struct_mutex);
3256
3257         intel_crtc_update_cursor(crtc, true);
3258
3259         for_each_encoder_on_crtc(dev, crtc, encoder)
3260                 encoder->enable(encoder);
3261
3262         if (HAS_PCH_CPT(dev))
3263                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3264
3265         /*
3266          * There seems to be a race in PCH platform hw (at least on some
3267          * outputs) where an enabled pipe still completes any pageflip right
3268          * away (as if the pipe is off) instead of waiting for vblank. As soon
3269          * as the first vblank happend, everything works as expected. Hence just
3270          * wait for one vblank before returning to avoid strange things
3271          * happening.
3272          */
3273         intel_wait_for_vblank(dev, intel_crtc->pipe);
3274 }
3275
3276 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3277 {
3278         struct drm_device *dev = crtc->dev;
3279         struct drm_i915_private *dev_priv = dev->dev_private;
3280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281         struct intel_encoder *encoder;
3282         int pipe = intel_crtc->pipe;
3283         int plane = intel_crtc->plane;
3284         u32 reg, temp;
3285
3286
3287         if (!intel_crtc->active)
3288                 return;
3289
3290         for_each_encoder_on_crtc(dev, crtc, encoder)
3291                 encoder->disable(encoder);
3292
3293         intel_crtc_wait_for_pending_flips(crtc);
3294         drm_vblank_off(dev, pipe);
3295         intel_crtc_update_cursor(crtc, false);
3296
3297         intel_disable_plane(dev_priv, plane, pipe);
3298
3299         if (dev_priv->cfb_plane == plane)
3300                 intel_disable_fbc(dev);
3301
3302         intel_disable_pipe(dev_priv, pipe);
3303
3304         if (IS_HASWELL(dev))
3305                 intel_ddi_disable_pipe_func(dev_priv, pipe);
3306
3307         /* Disable PF */
3308         I915_WRITE(PF_CTL(pipe), 0);
3309         I915_WRITE(PF_WIN_SZ(pipe), 0);
3310
3311         if (IS_HASWELL(dev))
3312                 intel_ddi_disable_pipe_clock(intel_crtc);
3313
3314         for_each_encoder_on_crtc(dev, crtc, encoder)
3315                 if (encoder->post_disable)
3316                         encoder->post_disable(encoder);
3317
3318         ironlake_fdi_disable(crtc);
3319
3320         intel_disable_transcoder(dev_priv, pipe);
3321
3322         if (HAS_PCH_CPT(dev)) {
3323                 /* disable TRANS_DP_CTL */
3324                 reg = TRANS_DP_CTL(pipe);
3325                 temp = I915_READ(reg);
3326                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3327                 temp |= TRANS_DP_PORT_SEL_NONE;
3328                 I915_WRITE(reg, temp);
3329
3330                 /* disable DPLL_SEL */
3331                 temp = I915_READ(PCH_DPLL_SEL);
3332                 switch (pipe) {
3333                 case 0:
3334                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3335                         break;
3336                 case 1:
3337                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3338                         break;
3339                 case 2:
3340                         /* C shares PLL A or B */
3341                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3342                         break;
3343                 default:
3344                         BUG(); /* wtf */
3345                 }
3346                 I915_WRITE(PCH_DPLL_SEL, temp);
3347         }
3348
3349         /* disable PCH DPLL */
3350         intel_disable_pch_pll(intel_crtc);
3351
3352         ironlake_fdi_pll_disable(intel_crtc);
3353
3354         intel_crtc->active = false;
3355         intel_update_watermarks(dev);
3356
3357         mutex_lock(&dev->struct_mutex);
3358         intel_update_fbc(dev);
3359         mutex_unlock(&dev->struct_mutex);
3360 }
3361
3362 static void ironlake_crtc_off(struct drm_crtc *crtc)
3363 {
3364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365         intel_put_pch_pll(intel_crtc);
3366 }
3367
3368 static void haswell_crtc_off(struct drm_crtc *crtc)
3369 {
3370         intel_ddi_put_crtc_pll(crtc);
3371 }
3372
3373 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3374 {
3375         if (!enable && intel_crtc->overlay) {
3376                 struct drm_device *dev = intel_crtc->base.dev;
3377                 struct drm_i915_private *dev_priv = dev->dev_private;
3378
3379                 mutex_lock(&dev->struct_mutex);
3380                 dev_priv->mm.interruptible = false;
3381                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382                 dev_priv->mm.interruptible = true;
3383                 mutex_unlock(&dev->struct_mutex);
3384         }
3385
3386         /* Let userspace switch the overlay on again. In most cases userspace
3387          * has to recompute where to put it anyway.
3388          */
3389 }
3390
3391 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         struct intel_encoder *encoder;
3397         int pipe = intel_crtc->pipe;
3398         int plane = intel_crtc->plane;
3399
3400         WARN_ON(!crtc->enabled);
3401
3402         if (intel_crtc->active)
3403                 return;
3404
3405         intel_crtc->active = true;
3406         intel_update_watermarks(dev);
3407
3408         intel_enable_pll(dev_priv, pipe);
3409         intel_enable_pipe(dev_priv, pipe, false);
3410         intel_enable_plane(dev_priv, plane, pipe);
3411
3412         intel_crtc_load_lut(crtc);
3413         intel_update_fbc(dev);
3414
3415         /* Give the overlay scaler a chance to enable if it's on this pipe */
3416         intel_crtc_dpms_overlay(intel_crtc, true);
3417         intel_crtc_update_cursor(crtc, true);
3418
3419         for_each_encoder_on_crtc(dev, crtc, encoder)
3420                 encoder->enable(encoder);
3421 }
3422
3423 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3424 {
3425         struct drm_device *dev = crtc->dev;
3426         struct drm_i915_private *dev_priv = dev->dev_private;
3427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428         struct intel_encoder *encoder;
3429         int pipe = intel_crtc->pipe;
3430         int plane = intel_crtc->plane;
3431
3432
3433         if (!intel_crtc->active)
3434                 return;
3435
3436         for_each_encoder_on_crtc(dev, crtc, encoder)
3437                 encoder->disable(encoder);
3438
3439         /* Give the overlay scaler a chance to disable if it's on this pipe */
3440         intel_crtc_wait_for_pending_flips(crtc);
3441         drm_vblank_off(dev, pipe);
3442         intel_crtc_dpms_overlay(intel_crtc, false);
3443         intel_crtc_update_cursor(crtc, false);
3444
3445         if (dev_priv->cfb_plane == plane)
3446                 intel_disable_fbc(dev);
3447
3448         intel_disable_plane(dev_priv, plane, pipe);
3449         intel_disable_pipe(dev_priv, pipe);
3450         intel_disable_pll(dev_priv, pipe);
3451
3452         intel_crtc->active = false;
3453         intel_update_fbc(dev);
3454         intel_update_watermarks(dev);
3455 }
3456
3457 static void i9xx_crtc_off(struct drm_crtc *crtc)
3458 {
3459 }
3460
3461 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3462                                     bool enabled)
3463 {
3464         struct drm_device *dev = crtc->dev;
3465         struct drm_i915_master_private *master_priv;
3466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467         int pipe = intel_crtc->pipe;
3468
3469         if (!dev->primary->master)
3470                 return;
3471
3472         master_priv = dev->primary->master->driver_priv;
3473         if (!master_priv->sarea_priv)
3474                 return;
3475
3476         switch (pipe) {
3477         case 0:
3478                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3479                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3480                 break;
3481         case 1:
3482                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3483                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3484                 break;
3485         default:
3486                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3487                 break;
3488         }
3489 }
3490
3491 /**
3492  * Sets the power management mode of the pipe and plane.
3493  */
3494 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3495 {
3496         struct drm_device *dev = crtc->dev;
3497         struct drm_i915_private *dev_priv = dev->dev_private;
3498         struct intel_encoder *intel_encoder;
3499         bool enable = false;
3500
3501         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3502                 enable |= intel_encoder->connectors_active;
3503
3504         if (enable)
3505                 dev_priv->display.crtc_enable(crtc);
3506         else
3507                 dev_priv->display.crtc_disable(crtc);
3508
3509         intel_crtc_update_sarea(crtc, enable);
3510 }
3511
3512 static void intel_crtc_noop(struct drm_crtc *crtc)
3513 {
3514 }
3515
3516 static void intel_crtc_disable(struct drm_crtc *crtc)
3517 {
3518         struct drm_device *dev = crtc->dev;
3519         struct drm_connector *connector;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521
3522         /* crtc should still be enabled when we disable it. */
3523         WARN_ON(!crtc->enabled);
3524
3525         dev_priv->display.crtc_disable(crtc);
3526         intel_crtc_update_sarea(crtc, false);
3527         dev_priv->display.off(crtc);
3528
3529         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3530         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3531
3532         if (crtc->fb) {
3533                 mutex_lock(&dev->struct_mutex);
3534                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3535                 mutex_unlock(&dev->struct_mutex);
3536                 crtc->fb = NULL;
3537         }
3538
3539         /* Update computed state. */
3540         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3541                 if (!connector->encoder || !connector->encoder->crtc)
3542                         continue;
3543
3544                 if (connector->encoder->crtc != crtc)
3545                         continue;
3546
3547                 connector->dpms = DRM_MODE_DPMS_OFF;
3548                 to_intel_encoder(connector->encoder)->connectors_active = false;
3549         }
3550 }
3551
3552 void intel_modeset_disable(struct drm_device *dev)
3553 {
3554         struct drm_crtc *crtc;
3555
3556         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3557                 if (crtc->enabled)
3558                         intel_crtc_disable(crtc);
3559         }
3560 }
3561
3562 void intel_encoder_noop(struct drm_encoder *encoder)
3563 {
3564 }
3565
3566 void intel_encoder_destroy(struct drm_encoder *encoder)
3567 {
3568         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3569
3570         drm_encoder_cleanup(encoder);
3571         kfree(intel_encoder);
3572 }
3573
3574 /* Simple dpms helper for encodres with just one connector, no cloning and only
3575  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3576  * state of the entire output pipe. */
3577 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3578 {
3579         if (mode == DRM_MODE_DPMS_ON) {
3580                 encoder->connectors_active = true;
3581
3582                 intel_crtc_update_dpms(encoder->base.crtc);
3583         } else {
3584                 encoder->connectors_active = false;
3585
3586                 intel_crtc_update_dpms(encoder->base.crtc);
3587         }
3588 }
3589
3590 /* Cross check the actual hw state with our own modeset state tracking (and it's
3591  * internal consistency). */
3592 static void intel_connector_check_state(struct intel_connector *connector)
3593 {
3594         if (connector->get_hw_state(connector)) {
3595                 struct intel_encoder *encoder = connector->encoder;
3596                 struct drm_crtc *crtc;
3597                 bool encoder_enabled;
3598                 enum pipe pipe;
3599
3600                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3601                               connector->base.base.id,
3602                               drm_get_connector_name(&connector->base));
3603
3604                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3605                      "wrong connector dpms state\n");
3606                 WARN(connector->base.encoder != &encoder->base,
3607                      "active connector not linked to encoder\n");
3608                 WARN(!encoder->connectors_active,
3609                      "encoder->connectors_active not set\n");
3610
3611                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3612                 WARN(!encoder_enabled, "encoder not enabled\n");
3613                 if (WARN_ON(!encoder->base.crtc))
3614                         return;
3615
3616                 crtc = encoder->base.crtc;
3617
3618                 WARN(!crtc->enabled, "crtc not enabled\n");
3619                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3620                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3621                      "encoder active on the wrong pipe\n");
3622         }
3623 }
3624
3625 /* Even simpler default implementation, if there's really no special case to
3626  * consider. */
3627 void intel_connector_dpms(struct drm_connector *connector, int mode)
3628 {
3629         struct intel_encoder *encoder = intel_attached_encoder(connector);
3630
3631         /* All the simple cases only support two dpms states. */
3632         if (mode != DRM_MODE_DPMS_ON)
3633                 mode = DRM_MODE_DPMS_OFF;
3634
3635         if (mode == connector->dpms)
3636                 return;
3637
3638         connector->dpms = mode;
3639
3640         /* Only need to change hw state when actually enabled */
3641         if (encoder->base.crtc)
3642                 intel_encoder_dpms(encoder, mode);
3643         else
3644                 WARN_ON(encoder->connectors_active != false);
3645
3646         intel_modeset_check_state(connector->dev);
3647 }
3648
3649 /* Simple connector->get_hw_state implementation for encoders that support only
3650  * one connector and no cloning and hence the encoder state determines the state
3651  * of the connector. */
3652 bool intel_connector_get_hw_state(struct intel_connector *connector)
3653 {
3654         enum pipe pipe = 0;
3655         struct intel_encoder *encoder = connector->encoder;
3656
3657         return encoder->get_hw_state(encoder, &pipe);
3658 }
3659
3660 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3661                                   const struct drm_display_mode *mode,
3662                                   struct drm_display_mode *adjusted_mode)
3663 {
3664         struct drm_device *dev = crtc->dev;
3665
3666         if (HAS_PCH_SPLIT(dev)) {
3667                 /* FDI link clock is fixed at 2.7G */
3668                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3669                         return false;
3670         }
3671
3672         /* All interlaced capable intel hw wants timings in frames. Note though
3673          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3674          * timings, so we need to be careful not to clobber these.*/
3675         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3676                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3677
3678         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3679          * with a hsync front porch of 0.
3680          */
3681         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3682                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3683                 return false;
3684
3685         return true;
3686 }
3687
3688 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3689 {
3690         return 400000; /* FIXME */
3691 }
3692
3693 static int i945_get_display_clock_speed(struct drm_device *dev)
3694 {
3695         return 400000;
3696 }
3697
3698 static int i915_get_display_clock_speed(struct drm_device *dev)
3699 {
3700         return 333000;
3701 }
3702
3703 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3704 {
3705         return 200000;
3706 }
3707
3708 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3709 {
3710         u16 gcfgc = 0;
3711
3712         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3713
3714         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3715                 return 133000;
3716         else {
3717                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3718                 case GC_DISPLAY_CLOCK_333_MHZ:
3719                         return 333000;
3720                 default:
3721                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3722                         return 190000;
3723                 }
3724         }
3725 }
3726
3727 static int i865_get_display_clock_speed(struct drm_device *dev)
3728 {
3729         return 266000;
3730 }
3731
3732 static int i855_get_display_clock_speed(struct drm_device *dev)
3733 {
3734         u16 hpllcc = 0;
3735         /* Assume that the hardware is in the high speed state.  This
3736          * should be the default.
3737          */
3738         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3739         case GC_CLOCK_133_200:
3740         case GC_CLOCK_100_200:
3741                 return 200000;
3742         case GC_CLOCK_166_250:
3743                 return 250000;
3744         case GC_CLOCK_100_133:
3745                 return 133000;
3746         }
3747
3748         /* Shouldn't happen */
3749         return 0;
3750 }
3751
3752 static int i830_get_display_clock_speed(struct drm_device *dev)
3753 {
3754         return 133000;
3755 }
3756
3757 struct fdi_m_n {
3758         u32        tu;
3759         u32        gmch_m;
3760         u32        gmch_n;
3761         u32        link_m;
3762         u32        link_n;
3763 };
3764
3765 static void
3766 fdi_reduce_ratio(u32 *num, u32 *den)
3767 {
3768         while (*num > 0xffffff || *den > 0xffffff) {
3769                 *num >>= 1;
3770                 *den >>= 1;
3771         }
3772 }
3773
3774 static void
3775 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3776                      int link_clock, struct fdi_m_n *m_n)
3777 {
3778         m_n->tu = 64; /* default size */
3779
3780         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3781         m_n->gmch_m = bits_per_pixel * pixel_clock;
3782         m_n->gmch_n = link_clock * nlanes * 8;
3783         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3784
3785         m_n->link_m = pixel_clock;
3786         m_n->link_n = link_clock;
3787         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3788 }
3789
3790 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3791 {
3792         if (i915_panel_use_ssc >= 0)
3793                 return i915_panel_use_ssc != 0;
3794         return dev_priv->lvds_use_ssc
3795                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3796 }
3797
3798 /**
3799  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3800  * @crtc: CRTC structure
3801  * @mode: requested mode
3802  *
3803  * A pipe may be connected to one or more outputs.  Based on the depth of the
3804  * attached framebuffer, choose a good color depth to use on the pipe.
3805  *
3806  * If possible, match the pipe depth to the fb depth.  In some cases, this
3807  * isn't ideal, because the connected output supports a lesser or restricted
3808  * set of depths.  Resolve that here:
3809  *    LVDS typically supports only 6bpc, so clamp down in that case
3810  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3811  *    Displays may support a restricted set as well, check EDID and clamp as
3812  *      appropriate.
3813  *    DP may want to dither down to 6bpc to fit larger modes
3814  *
3815  * RETURNS:
3816  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3817  * true if they don't match).
3818  */
3819 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3820                                          struct drm_framebuffer *fb,
3821                                          unsigned int *pipe_bpp,
3822                                          struct drm_display_mode *mode)
3823 {
3824         struct drm_device *dev = crtc->dev;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826         struct drm_connector *connector;
3827         struct intel_encoder *intel_encoder;
3828         unsigned int display_bpc = UINT_MAX, bpc;
3829
3830         /* Walk the encoders & connectors on this crtc, get min bpc */
3831         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3832
3833                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3834                         unsigned int lvds_bpc;
3835
3836                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3837                             LVDS_A3_POWER_UP)
3838                                 lvds_bpc = 8;
3839                         else
3840                                 lvds_bpc = 6;
3841
3842                         if (lvds_bpc < display_bpc) {
3843                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3844                                 display_bpc = lvds_bpc;
3845                         }
3846                         continue;
3847                 }
3848
3849                 /* Not one of the known troublemakers, check the EDID */
3850                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3851                                     head) {
3852                         if (connector->encoder != &intel_encoder->base)
3853                                 continue;
3854
3855                         /* Don't use an invalid EDID bpc value */
3856                         if (connector->display_info.bpc &&
3857                             connector->display_info.bpc < display_bpc) {
3858                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3859                                 display_bpc = connector->display_info.bpc;
3860                         }
3861                 }
3862
3863                 /*
3864                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3865                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3866                  */
3867                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3868                         if (display_bpc > 8 && display_bpc < 12) {
3869                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3870                                 display_bpc = 12;
3871                         } else {
3872                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3873                                 display_bpc = 8;
3874                         }
3875                 }
3876         }
3877
3878         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3879                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3880                 display_bpc = 6;
3881         }
3882
3883         /*
3884          * We could just drive the pipe at the highest bpc all the time and
3885          * enable dithering as needed, but that costs bandwidth.  So choose
3886          * the minimum value that expresses the full color range of the fb but
3887          * also stays within the max display bpc discovered above.
3888          */
3889
3890         switch (fb->depth) {
3891         case 8:
3892                 bpc = 8; /* since we go through a colormap */
3893                 break;
3894         case 15:
3895         case 16:
3896                 bpc = 6; /* min is 18bpp */
3897                 break;
3898         case 24:
3899                 bpc = 8;
3900                 break;
3901         case 30:
3902                 bpc = 10;
3903                 break;
3904         case 48:
3905                 bpc = 12;
3906                 break;
3907         default:
3908                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3909                 bpc = min((unsigned int)8, display_bpc);
3910                 break;
3911         }
3912
3913         display_bpc = min(display_bpc, bpc);
3914
3915         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3916                       bpc, display_bpc);
3917
3918         *pipe_bpp = display_bpc * 3;
3919
3920         return display_bpc != bpc;
3921 }
3922
3923 static int vlv_get_refclk(struct drm_crtc *crtc)
3924 {
3925         struct drm_device *dev = crtc->dev;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927         int refclk = 27000; /* for DP & HDMI */
3928
3929         return 100000; /* only one validated so far */
3930
3931         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3932                 refclk = 96000;
3933         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3934                 if (intel_panel_use_ssc(dev_priv))
3935                         refclk = 100000;
3936                 else
3937                         refclk = 96000;
3938         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3939                 refclk = 100000;
3940         }
3941
3942         return refclk;
3943 }
3944
3945 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3946 {
3947         struct drm_device *dev = crtc->dev;
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         int refclk;
3950
3951         if (IS_VALLEYVIEW(dev)) {
3952                 refclk = vlv_get_refclk(crtc);
3953         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3954             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3955                 refclk = dev_priv->lvds_ssc_freq * 1000;
3956                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3957                               refclk / 1000);
3958         } else if (!IS_GEN2(dev)) {
3959                 refclk = 96000;
3960         } else {
3961                 refclk = 48000;
3962         }
3963
3964         return refclk;
3965 }
3966
3967 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3968                                       intel_clock_t *clock)
3969 {
3970         /* SDVO TV has fixed PLL values depend on its clock range,
3971            this mirrors vbios setting. */
3972         if (adjusted_mode->clock >= 100000
3973             && adjusted_mode->clock < 140500) {
3974                 clock->p1 = 2;
3975                 clock->p2 = 10;
3976                 clock->n = 3;
3977                 clock->m1 = 16;
3978                 clock->m2 = 8;
3979         } else if (adjusted_mode->clock >= 140500
3980                    && adjusted_mode->clock <= 200000) {
3981                 clock->p1 = 1;
3982                 clock->p2 = 10;
3983                 clock->n = 6;
3984                 clock->m1 = 12;
3985                 clock->m2 = 8;
3986         }
3987 }
3988
3989 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3990                                      intel_clock_t *clock,
3991                                      intel_clock_t *reduced_clock)
3992 {
3993         struct drm_device *dev = crtc->dev;
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996         int pipe = intel_crtc->pipe;
3997         u32 fp, fp2 = 0;
3998
3999         if (IS_PINEVIEW(dev)) {
4000                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4001                 if (reduced_clock)
4002                         fp2 = (1 << reduced_clock->n) << 16 |
4003                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4004         } else {
4005                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4006                 if (reduced_clock)
4007                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4008                                 reduced_clock->m2;
4009         }
4010
4011         I915_WRITE(FP0(pipe), fp);
4012
4013         intel_crtc->lowfreq_avail = false;
4014         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4015             reduced_clock && i915_powersave) {
4016                 I915_WRITE(FP1(pipe), fp2);
4017                 intel_crtc->lowfreq_avail = true;
4018         } else {
4019                 I915_WRITE(FP1(pipe), fp);
4020         }
4021 }
4022
4023 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4024                               struct drm_display_mode *adjusted_mode)
4025 {
4026         struct drm_device *dev = crtc->dev;
4027         struct drm_i915_private *dev_priv = dev->dev_private;
4028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4029         int pipe = intel_crtc->pipe;
4030         u32 temp;
4031
4032         temp = I915_READ(LVDS);
4033         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4034         if (pipe == 1) {
4035                 temp |= LVDS_PIPEB_SELECT;
4036         } else {
4037                 temp &= ~LVDS_PIPEB_SELECT;
4038         }
4039         /* set the corresponsding LVDS_BORDER bit */
4040         temp |= dev_priv->lvds_border_bits;
4041         /* Set the B0-B3 data pairs corresponding to whether we're going to
4042          * set the DPLLs for dual-channel mode or not.
4043          */
4044         if (clock->p2 == 7)
4045                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4046         else
4047                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4048
4049         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4050          * appropriately here, but we need to look more thoroughly into how
4051          * panels behave in the two modes.
4052          */
4053         /* set the dithering flag on LVDS as needed */
4054         if (INTEL_INFO(dev)->gen >= 4) {
4055                 if (dev_priv->lvds_dither)
4056                         temp |= LVDS_ENABLE_DITHER;
4057                 else
4058                         temp &= ~LVDS_ENABLE_DITHER;
4059         }
4060         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4061         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4062                 temp |= LVDS_HSYNC_POLARITY;
4063         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4064                 temp |= LVDS_VSYNC_POLARITY;
4065         I915_WRITE(LVDS, temp);
4066 }
4067
4068 static void vlv_update_pll(struct drm_crtc *crtc,
4069                            struct drm_display_mode *mode,
4070                            struct drm_display_mode *adjusted_mode,
4071                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4072                            int num_connectors)
4073 {
4074         struct drm_device *dev = crtc->dev;
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4077         int pipe = intel_crtc->pipe;
4078         u32 dpll, mdiv, pdiv;
4079         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4080         bool is_sdvo;
4081         u32 temp;
4082
4083         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4084                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4085
4086         dpll = DPLL_VGA_MODE_DIS;
4087         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4088         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4089         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4090
4091         I915_WRITE(DPLL(pipe), dpll);
4092         POSTING_READ(DPLL(pipe));
4093
4094         bestn = clock->n;
4095         bestm1 = clock->m1;
4096         bestm2 = clock->m2;
4097         bestp1 = clock->p1;
4098         bestp2 = clock->p2;
4099
4100         /*
4101          * In Valleyview PLL and program lane counter registers are exposed
4102          * through DPIO interface
4103          */
4104         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4105         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4106         mdiv |= ((bestn << DPIO_N_SHIFT));
4107         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4108         mdiv |= (1 << DPIO_K_SHIFT);
4109         mdiv |= DPIO_ENABLE_CALIBRATION;
4110         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4111
4112         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4113
4114         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4115                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4116                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4117                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4118         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4119
4120         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4121
4122         dpll |= DPLL_VCO_ENABLE;
4123         I915_WRITE(DPLL(pipe), dpll);
4124         POSTING_READ(DPLL(pipe));
4125         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4126                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4127
4128         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4129
4130         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4131                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4132
4133         I915_WRITE(DPLL(pipe), dpll);
4134
4135         /* Wait for the clocks to stabilize. */
4136         POSTING_READ(DPLL(pipe));
4137         udelay(150);
4138
4139         temp = 0;
4140         if (is_sdvo) {
4141                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4142                 if (temp > 1)
4143                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4144                 else
4145                         temp = 0;
4146         }
4147         I915_WRITE(DPLL_MD(pipe), temp);
4148         POSTING_READ(DPLL_MD(pipe));
4149
4150         /* Now program lane control registers */
4151         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4152                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4153         {
4154                 temp = 0x1000C4;
4155                 if(pipe == 1)
4156                         temp |= (1 << 21);
4157                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4158         }
4159         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4160         {
4161                 temp = 0x1000C4;
4162                 if(pipe == 1)
4163                         temp |= (1 << 21);
4164                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4165         }
4166 }
4167
4168 static void i9xx_update_pll(struct drm_crtc *crtc,
4169                             struct drm_display_mode *mode,
4170                             struct drm_display_mode *adjusted_mode,
4171                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4172                             int num_connectors)
4173 {
4174         struct drm_device *dev = crtc->dev;
4175         struct drm_i915_private *dev_priv = dev->dev_private;
4176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4177         int pipe = intel_crtc->pipe;
4178         u32 dpll;
4179         bool is_sdvo;
4180
4181         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4182
4183         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4184                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4185
4186         dpll = DPLL_VGA_MODE_DIS;
4187
4188         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4189                 dpll |= DPLLB_MODE_LVDS;
4190         else
4191                 dpll |= DPLLB_MODE_DAC_SERIAL;
4192         if (is_sdvo) {
4193                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4194                 if (pixel_multiplier > 1) {
4195                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4196                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4197                 }
4198                 dpll |= DPLL_DVO_HIGH_SPEED;
4199         }
4200         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4201                 dpll |= DPLL_DVO_HIGH_SPEED;
4202
4203         /* compute bitmask from p1 value */
4204         if (IS_PINEVIEW(dev))
4205                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4206         else {
4207                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4208                 if (IS_G4X(dev) && reduced_clock)
4209                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4210         }
4211         switch (clock->p2) {
4212         case 5:
4213                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4214                 break;
4215         case 7:
4216                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4217                 break;
4218         case 10:
4219                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4220                 break;
4221         case 14:
4222                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4223                 break;
4224         }
4225         if (INTEL_INFO(dev)->gen >= 4)
4226                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4227
4228         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4229                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4230         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4231                 /* XXX: just matching BIOS for now */
4232                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4233                 dpll |= 3;
4234         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4235                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4236                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4237         else
4238                 dpll |= PLL_REF_INPUT_DREFCLK;
4239
4240         dpll |= DPLL_VCO_ENABLE;
4241         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4242         POSTING_READ(DPLL(pipe));
4243         udelay(150);
4244
4245         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4246          * This is an exception to the general rule that mode_set doesn't turn
4247          * things on.
4248          */
4249         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4250                 intel_update_lvds(crtc, clock, adjusted_mode);
4251
4252         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4253                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4254
4255         I915_WRITE(DPLL(pipe), dpll);
4256
4257         /* Wait for the clocks to stabilize. */
4258         POSTING_READ(DPLL(pipe));
4259         udelay(150);
4260
4261         if (INTEL_INFO(dev)->gen >= 4) {
4262                 u32 temp = 0;
4263                 if (is_sdvo) {
4264                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4265                         if (temp > 1)
4266                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4267                         else
4268                                 temp = 0;
4269                 }
4270                 I915_WRITE(DPLL_MD(pipe), temp);
4271         } else {
4272                 /* The pixel multiplier can only be updated once the
4273                  * DPLL is enabled and the clocks are stable.
4274                  *
4275                  * So write it again.
4276                  */
4277                 I915_WRITE(DPLL(pipe), dpll);
4278         }
4279 }
4280
4281 static void i8xx_update_pll(struct drm_crtc *crtc,
4282                             struct drm_display_mode *adjusted_mode,
4283                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4284                             int num_connectors)
4285 {
4286         struct drm_device *dev = crtc->dev;
4287         struct drm_i915_private *dev_priv = dev->dev_private;
4288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289         int pipe = intel_crtc->pipe;
4290         u32 dpll;
4291
4292         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4293
4294         dpll = DPLL_VGA_MODE_DIS;
4295
4296         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4297                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4298         } else {
4299                 if (clock->p1 == 2)
4300                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4301                 else
4302                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4303                 if (clock->p2 == 4)
4304                         dpll |= PLL_P2_DIVIDE_BY_4;
4305         }
4306
4307         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4308                 /* XXX: just matching BIOS for now */
4309                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4310                 dpll |= 3;
4311         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4312                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4313                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4314         else
4315                 dpll |= PLL_REF_INPUT_DREFCLK;
4316
4317         dpll |= DPLL_VCO_ENABLE;
4318         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4319         POSTING_READ(DPLL(pipe));
4320         udelay(150);
4321
4322         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4323          * This is an exception to the general rule that mode_set doesn't turn
4324          * things on.
4325          */
4326         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4327                 intel_update_lvds(crtc, clock, adjusted_mode);
4328
4329         I915_WRITE(DPLL(pipe), dpll);
4330
4331         /* Wait for the clocks to stabilize. */
4332         POSTING_READ(DPLL(pipe));
4333         udelay(150);
4334
4335         /* The pixel multiplier can only be updated once the
4336          * DPLL is enabled and the clocks are stable.
4337          *
4338          * So write it again.
4339          */
4340         I915_WRITE(DPLL(pipe), dpll);
4341 }
4342
4343 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4344                                    struct drm_display_mode *mode,
4345                                    struct drm_display_mode *adjusted_mode)
4346 {
4347         struct drm_device *dev = intel_crtc->base.dev;
4348         struct drm_i915_private *dev_priv = dev->dev_private;
4349         enum pipe pipe = intel_crtc->pipe;
4350         uint32_t vsyncshift;
4351
4352         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4353                 /* the chip adds 2 halflines automatically */
4354                 adjusted_mode->crtc_vtotal -= 1;
4355                 adjusted_mode->crtc_vblank_end -= 1;
4356                 vsyncshift = adjusted_mode->crtc_hsync_start
4357                              - adjusted_mode->crtc_htotal / 2;
4358         } else {
4359                 vsyncshift = 0;
4360         }
4361
4362         if (INTEL_INFO(dev)->gen > 3)
4363                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4364
4365         I915_WRITE(HTOTAL(pipe),
4366                    (adjusted_mode->crtc_hdisplay - 1) |
4367                    ((adjusted_mode->crtc_htotal - 1) << 16));
4368         I915_WRITE(HBLANK(pipe),
4369                    (adjusted_mode->crtc_hblank_start - 1) |
4370                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4371         I915_WRITE(HSYNC(pipe),
4372                    (adjusted_mode->crtc_hsync_start - 1) |
4373                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4374
4375         I915_WRITE(VTOTAL(pipe),
4376                    (adjusted_mode->crtc_vdisplay - 1) |
4377                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4378         I915_WRITE(VBLANK(pipe),
4379                    (adjusted_mode->crtc_vblank_start - 1) |
4380                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4381         I915_WRITE(VSYNC(pipe),
4382                    (adjusted_mode->crtc_vsync_start - 1) |
4383                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4384
4385         /* pipesrc controls the size that is scaled from, which should
4386          * always be the user's requested size.
4387          */
4388         I915_WRITE(PIPESRC(pipe),
4389                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4390 }
4391
4392 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4393                               struct drm_display_mode *mode,
4394                               struct drm_display_mode *adjusted_mode,
4395                               int x, int y,
4396                               struct drm_framebuffer *fb)
4397 {
4398         struct drm_device *dev = crtc->dev;
4399         struct drm_i915_private *dev_priv = dev->dev_private;
4400         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4401         int pipe = intel_crtc->pipe;
4402         int plane = intel_crtc->plane;
4403         int refclk, num_connectors = 0;
4404         intel_clock_t clock, reduced_clock;
4405         u32 dspcntr, pipeconf;
4406         bool ok, has_reduced_clock = false, is_sdvo = false;
4407         bool is_lvds = false, is_tv = false, is_dp = false;
4408         struct intel_encoder *encoder;
4409         const intel_limit_t *limit;
4410         int ret;
4411
4412         for_each_encoder_on_crtc(dev, crtc, encoder) {
4413                 switch (encoder->type) {
4414                 case INTEL_OUTPUT_LVDS:
4415                         is_lvds = true;
4416                         break;
4417                 case INTEL_OUTPUT_SDVO:
4418                 case INTEL_OUTPUT_HDMI:
4419                         is_sdvo = true;
4420                         if (encoder->needs_tv_clock)
4421                                 is_tv = true;
4422                         break;
4423                 case INTEL_OUTPUT_TVOUT:
4424                         is_tv = true;
4425                         break;
4426                 case INTEL_OUTPUT_DISPLAYPORT:
4427                         is_dp = true;
4428                         break;
4429                 }
4430
4431                 num_connectors++;
4432         }
4433
4434         refclk = i9xx_get_refclk(crtc, num_connectors);
4435
4436         /*
4437          * Returns a set of divisors for the desired target clock with the given
4438          * refclk, or FALSE.  The returned values represent the clock equation:
4439          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4440          */
4441         limit = intel_limit(crtc, refclk);
4442         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4443                              &clock);
4444         if (!ok) {
4445                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4446                 return -EINVAL;
4447         }
4448
4449         /* Ensure that the cursor is valid for the new mode before changing... */
4450         intel_crtc_update_cursor(crtc, true);
4451
4452         if (is_lvds && dev_priv->lvds_downclock_avail) {
4453                 /*
4454                  * Ensure we match the reduced clock's P to the target clock.
4455                  * If the clocks don't match, we can't switch the display clock
4456                  * by using the FP0/FP1. In such case we will disable the LVDS
4457                  * downclock feature.
4458                 */
4459                 has_reduced_clock = limit->find_pll(limit, crtc,
4460                                                     dev_priv->lvds_downclock,
4461                                                     refclk,
4462                                                     &clock,
4463                                                     &reduced_clock);
4464         }
4465
4466         if (is_sdvo && is_tv)
4467                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4468
4469         if (IS_GEN2(dev))
4470                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4471                                 has_reduced_clock ? &reduced_clock : NULL,
4472                                 num_connectors);
4473         else if (IS_VALLEYVIEW(dev))
4474                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4475                                 has_reduced_clock ? &reduced_clock : NULL,
4476                                 num_connectors);
4477         else
4478                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4479                                 has_reduced_clock ? &reduced_clock : NULL,
4480                                 num_connectors);
4481
4482         /* setup pipeconf */
4483         pipeconf = I915_READ(PIPECONF(pipe));
4484
4485         /* Set up the display plane register */
4486         dspcntr = DISPPLANE_GAMMA_ENABLE;
4487
4488         if (pipe == 0)
4489                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4490         else
4491                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4492
4493         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4494                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4495                  * core speed.
4496                  *
4497                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4498                  * pipe == 0 check?
4499                  */
4500                 if (mode->clock >
4501                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4502                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4503                 else
4504                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4505         }
4506
4507         /* default to 8bpc */
4508         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4509         if (is_dp) {
4510                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4511                         pipeconf |= PIPECONF_BPP_6 |
4512                                     PIPECONF_DITHER_EN |
4513                                     PIPECONF_DITHER_TYPE_SP;
4514                 }
4515         }
4516
4517         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4518                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4519                         pipeconf |= PIPECONF_BPP_6 |
4520                                         PIPECONF_ENABLE |
4521                                         I965_PIPECONF_ACTIVE;
4522                 }
4523         }
4524
4525         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4526         drm_mode_debug_printmodeline(mode);
4527
4528         if (HAS_PIPE_CXSR(dev)) {
4529                 if (intel_crtc->lowfreq_avail) {
4530                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4531                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4532                 } else {
4533                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4534                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4535                 }
4536         }
4537
4538         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4539         if (!IS_GEN2(dev) &&
4540             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4541                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4542         else
4543                 pipeconf |= PIPECONF_PROGRESSIVE;
4544
4545         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4546
4547         /* pipesrc and dspsize control the size that is scaled from,
4548          * which should always be the user's requested size.
4549          */
4550         I915_WRITE(DSPSIZE(plane),
4551                    ((mode->vdisplay - 1) << 16) |
4552                    (mode->hdisplay - 1));
4553         I915_WRITE(DSPPOS(plane), 0);
4554
4555         I915_WRITE(PIPECONF(pipe), pipeconf);
4556         POSTING_READ(PIPECONF(pipe));
4557         intel_enable_pipe(dev_priv, pipe, false);
4558
4559         intel_wait_for_vblank(dev, pipe);
4560
4561         I915_WRITE(DSPCNTR(plane), dspcntr);
4562         POSTING_READ(DSPCNTR(plane));
4563
4564         ret = intel_pipe_set_base(crtc, x, y, fb);
4565
4566         intel_update_watermarks(dev);
4567
4568         return ret;
4569 }
4570
4571 /*
4572  * Initialize reference clocks when the driver loads
4573  */
4574 void ironlake_init_pch_refclk(struct drm_device *dev)
4575 {
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct drm_mode_config *mode_config = &dev->mode_config;
4578         struct intel_encoder *encoder;
4579         u32 temp;
4580         bool has_lvds = false;
4581         bool has_cpu_edp = false;
4582         bool has_pch_edp = false;
4583         bool has_panel = false;
4584         bool has_ck505 = false;
4585         bool can_ssc = false;
4586
4587         /* We need to take the global config into account */
4588         list_for_each_entry(encoder, &mode_config->encoder_list,
4589                             base.head) {
4590                 switch (encoder->type) {
4591                 case INTEL_OUTPUT_LVDS:
4592                         has_panel = true;
4593                         has_lvds = true;
4594                         break;
4595                 case INTEL_OUTPUT_EDP:
4596                         has_panel = true;
4597                         if (intel_encoder_is_pch_edp(&encoder->base))
4598                                 has_pch_edp = true;
4599                         else
4600                                 has_cpu_edp = true;
4601                         break;
4602                 }
4603         }
4604
4605         if (HAS_PCH_IBX(dev)) {
4606                 has_ck505 = dev_priv->display_clock_mode;
4607                 can_ssc = has_ck505;
4608         } else {
4609                 has_ck505 = false;
4610                 can_ssc = true;
4611         }
4612
4613         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4614                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4615                       has_ck505);
4616
4617         /* Ironlake: try to setup display ref clock before DPLL
4618          * enabling. This is only under driver's control after
4619          * PCH B stepping, previous chipset stepping should be
4620          * ignoring this setting.
4621          */
4622         temp = I915_READ(PCH_DREF_CONTROL);
4623         /* Always enable nonspread source */
4624         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4625
4626         if (has_ck505)
4627                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4628         else
4629                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4630
4631         if (has_panel) {
4632                 temp &= ~DREF_SSC_SOURCE_MASK;
4633                 temp |= DREF_SSC_SOURCE_ENABLE;
4634
4635                 /* SSC must be turned on before enabling the CPU output  */
4636                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4637                         DRM_DEBUG_KMS("Using SSC on panel\n");
4638                         temp |= DREF_SSC1_ENABLE;
4639                 } else
4640                         temp &= ~DREF_SSC1_ENABLE;
4641
4642                 /* Get SSC going before enabling the outputs */
4643                 I915_WRITE(PCH_DREF_CONTROL, temp);
4644                 POSTING_READ(PCH_DREF_CONTROL);
4645                 udelay(200);
4646
4647                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4648
4649                 /* Enable CPU source on CPU attached eDP */
4650                 if (has_cpu_edp) {
4651                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4652                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4653                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4654                         }
4655                         else
4656                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4657                 } else
4658                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4659
4660                 I915_WRITE(PCH_DREF_CONTROL, temp);
4661                 POSTING_READ(PCH_DREF_CONTROL);
4662                 udelay(200);
4663         } else {
4664                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4665
4666                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4667
4668                 /* Turn off CPU output */
4669                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4670
4671                 I915_WRITE(PCH_DREF_CONTROL, temp);
4672                 POSTING_READ(PCH_DREF_CONTROL);
4673                 udelay(200);
4674
4675                 /* Turn off the SSC source */
4676                 temp &= ~DREF_SSC_SOURCE_MASK;
4677                 temp |= DREF_SSC_SOURCE_DISABLE;
4678
4679                 /* Turn off SSC1 */
4680                 temp &= ~ DREF_SSC1_ENABLE;
4681
4682                 I915_WRITE(PCH_DREF_CONTROL, temp);
4683                 POSTING_READ(PCH_DREF_CONTROL);
4684                 udelay(200);
4685         }
4686 }
4687
4688 static int ironlake_get_refclk(struct drm_crtc *crtc)
4689 {
4690         struct drm_device *dev = crtc->dev;
4691         struct drm_i915_private *dev_priv = dev->dev_private;
4692         struct intel_encoder *encoder;
4693         struct intel_encoder *edp_encoder = NULL;
4694         int num_connectors = 0;
4695         bool is_lvds = false;
4696
4697         for_each_encoder_on_crtc(dev, crtc, encoder) {
4698                 switch (encoder->type) {
4699                 case INTEL_OUTPUT_LVDS:
4700                         is_lvds = true;
4701                         break;
4702                 case INTEL_OUTPUT_EDP:
4703                         edp_encoder = encoder;
4704                         break;
4705                 }
4706                 num_connectors++;
4707         }
4708
4709         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4710                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4711                               dev_priv->lvds_ssc_freq);
4712                 return dev_priv->lvds_ssc_freq * 1000;
4713         }
4714
4715         return 120000;
4716 }
4717
4718 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4719                                   struct drm_display_mode *adjusted_mode,
4720                                   bool dither)
4721 {
4722         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4724         int pipe = intel_crtc->pipe;
4725         uint32_t val;
4726
4727         val = I915_READ(PIPECONF(pipe));
4728
4729         val &= ~PIPE_BPC_MASK;
4730         switch (intel_crtc->bpp) {
4731         case 18:
4732                 val |= PIPE_6BPC;
4733                 break;
4734         case 24:
4735                 val |= PIPE_8BPC;
4736                 break;
4737         case 30:
4738                 val |= PIPE_10BPC;
4739                 break;
4740         case 36:
4741                 val |= PIPE_12BPC;
4742                 break;
4743         default:
4744                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4745                 BUG();
4746         }
4747
4748         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4749         if (dither)
4750                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4751
4752         val &= ~PIPECONF_INTERLACE_MASK;
4753         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4754                 val |= PIPECONF_INTERLACED_ILK;
4755         else
4756                 val |= PIPECONF_PROGRESSIVE;
4757
4758         I915_WRITE(PIPECONF(pipe), val);
4759         POSTING_READ(PIPECONF(pipe));
4760 }
4761
4762 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4763                                  struct drm_display_mode *adjusted_mode,
4764                                  bool dither)
4765 {
4766         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768         int pipe = intel_crtc->pipe;
4769         uint32_t val;
4770
4771         val = I915_READ(PIPECONF(pipe));
4772
4773         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4774         if (dither)
4775                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4776
4777         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4778         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4779                 val |= PIPECONF_INTERLACED_ILK;
4780         else
4781                 val |= PIPECONF_PROGRESSIVE;
4782
4783         I915_WRITE(PIPECONF(pipe), val);
4784         POSTING_READ(PIPECONF(pipe));
4785 }
4786
4787 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4788                                     struct drm_display_mode *adjusted_mode,
4789                                     intel_clock_t *clock,
4790                                     bool *has_reduced_clock,
4791                                     intel_clock_t *reduced_clock)
4792 {
4793         struct drm_device *dev = crtc->dev;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         struct intel_encoder *intel_encoder;
4796         int refclk;
4797         const intel_limit_t *limit;
4798         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4799
4800         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4801                 switch (intel_encoder->type) {
4802                 case INTEL_OUTPUT_LVDS:
4803                         is_lvds = true;
4804                         break;
4805                 case INTEL_OUTPUT_SDVO:
4806                 case INTEL_OUTPUT_HDMI:
4807                         is_sdvo = true;
4808                         if (intel_encoder->needs_tv_clock)
4809                                 is_tv = true;
4810                         break;
4811                 case INTEL_OUTPUT_TVOUT:
4812                         is_tv = true;
4813                         break;
4814                 }
4815         }
4816
4817         refclk = ironlake_get_refclk(crtc);
4818
4819         /*
4820          * Returns a set of divisors for the desired target clock with the given
4821          * refclk, or FALSE.  The returned values represent the clock equation:
4822          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4823          */
4824         limit = intel_limit(crtc, refclk);
4825         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4826                               clock);
4827         if (!ret)
4828                 return false;
4829
4830         if (is_lvds && dev_priv->lvds_downclock_avail) {
4831                 /*
4832                  * Ensure we match the reduced clock's P to the target clock.
4833                  * If the clocks don't match, we can't switch the display clock
4834                  * by using the FP0/FP1. In such case we will disable the LVDS
4835                  * downclock feature.
4836                 */
4837                 *has_reduced_clock = limit->find_pll(limit, crtc,
4838                                                      dev_priv->lvds_downclock,
4839                                                      refclk,
4840                                                      clock,
4841                                                      reduced_clock);
4842         }
4843
4844         if (is_sdvo && is_tv)
4845                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4846
4847         return true;
4848 }
4849
4850 static void ironlake_set_m_n(struct drm_crtc *crtc,
4851                              struct drm_display_mode *mode,
4852                              struct drm_display_mode *adjusted_mode)
4853 {
4854         struct drm_device *dev = crtc->dev;
4855         struct drm_i915_private *dev_priv = dev->dev_private;
4856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857         enum pipe pipe = intel_crtc->pipe;
4858         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4859         struct fdi_m_n m_n = {0};
4860         int target_clock, pixel_multiplier, lane, link_bw;
4861         bool is_dp = false, is_cpu_edp = false;
4862
4863         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4864                 switch (intel_encoder->type) {
4865                 case INTEL_OUTPUT_DISPLAYPORT:
4866                         is_dp = true;
4867                         break;
4868                 case INTEL_OUTPUT_EDP:
4869                         is_dp = true;
4870                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4871                                 is_cpu_edp = true;
4872                         edp_encoder = intel_encoder;
4873                         break;
4874                 }
4875         }
4876
4877         /* FDI link */
4878         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4879         lane = 0;
4880         /* CPU eDP doesn't require FDI link, so just set DP M/N
4881            according to current link config */
4882         if (is_cpu_edp) {
4883                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4884         } else {
4885                 /* FDI is a binary signal running at ~2.7GHz, encoding
4886                  * each output octet as 10 bits. The actual frequency
4887                  * is stored as a divider into a 100MHz clock, and the
4888                  * mode pixel clock is stored in units of 1KHz.
4889                  * Hence the bw of each lane in terms of the mode signal
4890                  * is:
4891                  */
4892                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4893         }
4894
4895         /* [e]DP over FDI requires target mode clock instead of link clock. */
4896         if (edp_encoder)
4897                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4898         else if (is_dp)
4899                 target_clock = mode->clock;
4900         else
4901                 target_clock = adjusted_mode->clock;
4902
4903         if (!lane) {
4904                 /*
4905                  * Account for spread spectrum to avoid
4906                  * oversubscribing the link. Max center spread
4907                  * is 2.5%; use 5% for safety's sake.
4908                  */
4909                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4910                 lane = bps / (link_bw * 8) + 1;
4911         }
4912
4913         intel_crtc->fdi_lanes = lane;
4914
4915         if (pixel_multiplier > 1)
4916                 link_bw *= pixel_multiplier;
4917         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4918                              &m_n);
4919
4920         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4921         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4922         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4923         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4924 }
4925
4926 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4927                                       struct drm_display_mode *adjusted_mode,
4928                                       intel_clock_t *clock, u32 fp)
4929 {
4930         struct drm_crtc *crtc = &intel_crtc->base;
4931         struct drm_device *dev = crtc->dev;
4932         struct drm_i915_private *dev_priv = dev->dev_private;
4933         struct intel_encoder *intel_encoder;
4934         uint32_t dpll;
4935         int factor, pixel_multiplier, num_connectors = 0;
4936         bool is_lvds = false, is_sdvo = false, is_tv = false;
4937         bool is_dp = false, is_cpu_edp = false;
4938
4939         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4940                 switch (intel_encoder->type) {
4941                 case INTEL_OUTPUT_LVDS:
4942                         is_lvds = true;
4943                         break;
4944                 case INTEL_OUTPUT_SDVO:
4945                 case INTEL_OUTPUT_HDMI:
4946                         is_sdvo = true;
4947                         if (intel_encoder->needs_tv_clock)
4948                                 is_tv = true;
4949                         break;
4950                 case INTEL_OUTPUT_TVOUT:
4951                         is_tv = true;
4952                         break;
4953                 case INTEL_OUTPUT_DISPLAYPORT:
4954                         is_dp = true;
4955                         break;
4956                 case INTEL_OUTPUT_EDP:
4957                         is_dp = true;
4958                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4959                                 is_cpu_edp = true;
4960                         break;
4961                 }
4962
4963                 num_connectors++;
4964         }
4965
4966         /* Enable autotuning of the PLL clock (if permissible) */
4967         factor = 21;
4968         if (is_lvds) {
4969                 if ((intel_panel_use_ssc(dev_priv) &&
4970                      dev_priv->lvds_ssc_freq == 100) ||
4971                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4972                         factor = 25;
4973         } else if (is_sdvo && is_tv)
4974                 factor = 20;
4975
4976         if (clock->m < factor * clock->n)
4977                 fp |= FP_CB_TUNE;
4978
4979         dpll = 0;
4980
4981         if (is_lvds)
4982                 dpll |= DPLLB_MODE_LVDS;
4983         else
4984                 dpll |= DPLLB_MODE_DAC_SERIAL;
4985         if (is_sdvo) {
4986                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4987                 if (pixel_multiplier > 1) {
4988                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4989                 }
4990                 dpll |= DPLL_DVO_HIGH_SPEED;
4991         }
4992         if (is_dp && !is_cpu_edp)
4993                 dpll |= DPLL_DVO_HIGH_SPEED;
4994
4995         /* compute bitmask from p1 value */
4996         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4997         /* also FPA1 */
4998         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4999
5000         switch (clock->p2) {
5001         case 5:
5002                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5003                 break;
5004         case 7:
5005                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5006                 break;
5007         case 10:
5008                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5009                 break;
5010         case 14:
5011                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5012                 break;
5013         }
5014
5015         if (is_sdvo && is_tv)
5016                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5017         else if (is_tv)
5018                 /* XXX: just matching BIOS for now */
5019                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5020                 dpll |= 3;
5021         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5022                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5023         else
5024                 dpll |= PLL_REF_INPUT_DREFCLK;
5025
5026         return dpll;
5027 }
5028
5029 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5030                                   struct drm_display_mode *mode,
5031                                   struct drm_display_mode *adjusted_mode,
5032                                   int x, int y,
5033                                   struct drm_framebuffer *fb)
5034 {
5035         struct drm_device *dev = crtc->dev;
5036         struct drm_i915_private *dev_priv = dev->dev_private;
5037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038         int pipe = intel_crtc->pipe;
5039         int plane = intel_crtc->plane;
5040         int num_connectors = 0;
5041         intel_clock_t clock, reduced_clock;
5042         u32 dpll, fp = 0, fp2 = 0;
5043         bool ok, has_reduced_clock = false;
5044         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5045         struct intel_encoder *encoder;
5046         u32 temp;
5047         int ret;
5048         bool dither;
5049
5050         for_each_encoder_on_crtc(dev, crtc, encoder) {
5051                 switch (encoder->type) {
5052                 case INTEL_OUTPUT_LVDS:
5053                         is_lvds = true;
5054                         break;
5055                 case INTEL_OUTPUT_DISPLAYPORT:
5056                         is_dp = true;
5057                         break;
5058                 case INTEL_OUTPUT_EDP:
5059                         is_dp = true;
5060                         if (!intel_encoder_is_pch_edp(&encoder->base))
5061                                 is_cpu_edp = true;
5062                         break;
5063                 }
5064
5065                 num_connectors++;
5066         }
5067
5068         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5069              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5070
5071         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5072                                      &has_reduced_clock, &reduced_clock);
5073         if (!ok) {
5074                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5075                 return -EINVAL;
5076         }
5077
5078         /* Ensure that the cursor is valid for the new mode before changing... */
5079         intel_crtc_update_cursor(crtc, true);
5080
5081         /* determine panel color depth */
5082         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5083         if (is_lvds && dev_priv->lvds_dither)
5084                 dither = true;
5085
5086         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5087         if (has_reduced_clock)
5088                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5089                         reduced_clock.m2;
5090
5091         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5092
5093         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5094         drm_mode_debug_printmodeline(mode);
5095
5096         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5097         if (!is_cpu_edp) {
5098                 struct intel_pch_pll *pll;
5099
5100                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5101                 if (pll == NULL) {
5102                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5103                                          pipe);
5104                         return -EINVAL;
5105                 }
5106         } else
5107                 intel_put_pch_pll(intel_crtc);
5108
5109         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5110          * This is an exception to the general rule that mode_set doesn't turn
5111          * things on.
5112          */
5113         if (is_lvds) {
5114                 temp = I915_READ(PCH_LVDS);
5115                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5116                 if (HAS_PCH_CPT(dev)) {
5117                         temp &= ~PORT_TRANS_SEL_MASK;
5118                         temp |= PORT_TRANS_SEL_CPT(pipe);
5119                 } else {
5120                         if (pipe == 1)
5121                                 temp |= LVDS_PIPEB_SELECT;
5122                         else
5123                                 temp &= ~LVDS_PIPEB_SELECT;
5124                 }
5125
5126                 /* set the corresponsding LVDS_BORDER bit */
5127                 temp |= dev_priv->lvds_border_bits;
5128                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5129                  * set the DPLLs for dual-channel mode or not.
5130                  */
5131                 if (clock.p2 == 7)
5132                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5133                 else
5134                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5135
5136                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5137                  * appropriately here, but we need to look more thoroughly into how
5138                  * panels behave in the two modes.
5139                  */
5140                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5141                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5142                         temp |= LVDS_HSYNC_POLARITY;
5143                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5144                         temp |= LVDS_VSYNC_POLARITY;
5145                 I915_WRITE(PCH_LVDS, temp);
5146         }
5147
5148         if (is_dp && !is_cpu_edp) {
5149                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5150         } else {
5151                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5152                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5153                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5154                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5155                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5156         }
5157
5158         if (intel_crtc->pch_pll) {
5159                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5160
5161                 /* Wait for the clocks to stabilize. */
5162                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5163                 udelay(150);
5164
5165                 /* The pixel multiplier can only be updated once the
5166                  * DPLL is enabled and the clocks are stable.
5167                  *
5168                  * So write it again.
5169                  */
5170                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5171         }
5172
5173         intel_crtc->lowfreq_avail = false;
5174         if (intel_crtc->pch_pll) {
5175                 if (is_lvds && has_reduced_clock && i915_powersave) {
5176                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5177                         intel_crtc->lowfreq_avail = true;
5178                 } else {
5179                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5180                 }
5181         }
5182
5183         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5184
5185         ironlake_set_m_n(crtc, mode, adjusted_mode);
5186
5187         if (is_cpu_edp)
5188                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5189
5190         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5191
5192         intel_wait_for_vblank(dev, pipe);
5193
5194         /* Set up the display plane register */
5195         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5196         POSTING_READ(DSPCNTR(plane));
5197
5198         ret = intel_pipe_set_base(crtc, x, y, fb);
5199
5200         intel_update_watermarks(dev);
5201
5202         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5203
5204         return ret;
5205 }
5206
5207 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5208                                  struct drm_display_mode *mode,
5209                                  struct drm_display_mode *adjusted_mode,
5210                                  int x, int y,
5211                                  struct drm_framebuffer *fb)
5212 {
5213         struct drm_device *dev = crtc->dev;
5214         struct drm_i915_private *dev_priv = dev->dev_private;
5215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216         int pipe = intel_crtc->pipe;
5217         int plane = intel_crtc->plane;
5218         int num_connectors = 0;
5219         intel_clock_t clock, reduced_clock;
5220         u32 dpll = 0, fp = 0, fp2 = 0;
5221         bool ok, has_reduced_clock = false;
5222         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5223         struct intel_encoder *encoder;
5224         u32 temp;
5225         int ret;
5226         bool dither;
5227
5228         for_each_encoder_on_crtc(dev, crtc, encoder) {
5229                 switch (encoder->type) {
5230                 case INTEL_OUTPUT_LVDS:
5231                         is_lvds = true;
5232                         break;
5233                 case INTEL_OUTPUT_DISPLAYPORT:
5234                         is_dp = true;
5235                         break;
5236                 case INTEL_OUTPUT_EDP:
5237                         is_dp = true;
5238                         if (!intel_encoder_is_pch_edp(&encoder->base))
5239                                 is_cpu_edp = true;
5240                         break;
5241                 }
5242
5243                 num_connectors++;
5244         }
5245
5246         /* We are not sure yet this won't happen. */
5247         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5248              INTEL_PCH_TYPE(dev));
5249
5250         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5251              num_connectors, pipe_name(pipe));
5252
5253         WARN_ON(I915_READ(PIPECONF(pipe)) &
5254                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5255
5256         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5257
5258         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5259                 return -EINVAL;
5260
5261         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5262                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5263                                              &has_reduced_clock,
5264                                              &reduced_clock);
5265                 if (!ok) {
5266                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5267                         return -EINVAL;
5268                 }
5269         }
5270
5271         /* Ensure that the cursor is valid for the new mode before changing... */
5272         intel_crtc_update_cursor(crtc, true);
5273
5274         /* determine panel color depth */
5275         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5276         if (is_lvds && dev_priv->lvds_dither)
5277                 dither = true;
5278
5279         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5280         drm_mode_debug_printmodeline(mode);
5281
5282         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5283                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5284                 if (has_reduced_clock)
5285                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5286                               reduced_clock.m2;
5287
5288                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5289                                              fp);
5290
5291                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5292                  * own on pre-Haswell/LPT generation */
5293                 if (!is_cpu_edp) {
5294                         struct intel_pch_pll *pll;
5295
5296                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5297                         if (pll == NULL) {
5298                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5299                                                  pipe);
5300                                 return -EINVAL;
5301                         }
5302                 } else
5303                         intel_put_pch_pll(intel_crtc);
5304
5305                 /* The LVDS pin pair needs to be on before the DPLLs are
5306                  * enabled.  This is an exception to the general rule that
5307                  * mode_set doesn't turn things on.
5308                  */
5309                 if (is_lvds) {
5310                         temp = I915_READ(PCH_LVDS);
5311                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5312                         if (HAS_PCH_CPT(dev)) {
5313                                 temp &= ~PORT_TRANS_SEL_MASK;
5314                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5315                         } else {
5316                                 if (pipe == 1)
5317                                         temp |= LVDS_PIPEB_SELECT;
5318                                 else
5319                                         temp &= ~LVDS_PIPEB_SELECT;
5320                         }
5321
5322                         /* set the corresponsding LVDS_BORDER bit */
5323                         temp |= dev_priv->lvds_border_bits;
5324                         /* Set the B0-B3 data pairs corresponding to whether
5325                          * we're going to set the DPLLs for dual-channel mode or
5326                          * not.
5327                          */
5328                         if (clock.p2 == 7)
5329                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5330                         else
5331                                 temp &= ~(LVDS_B0B3_POWER_UP |
5332                                           LVDS_CLKB_POWER_UP);
5333
5334                         /* It would be nice to set 24 vs 18-bit mode
5335                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5336                          * look more thoroughly into how panels behave in the
5337                          * two modes.
5338                          */
5339                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5340                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5341                                 temp |= LVDS_HSYNC_POLARITY;
5342                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5343                                 temp |= LVDS_VSYNC_POLARITY;
5344                         I915_WRITE(PCH_LVDS, temp);
5345                 }
5346         }
5347
5348         if (is_dp && !is_cpu_edp) {
5349                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5350         } else {
5351                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5352                         /* For non-DP output, clear any trans DP clock recovery
5353                          * setting.*/
5354                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5355                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5356                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5357                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5358                 }
5359         }
5360
5361         intel_crtc->lowfreq_avail = false;
5362         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5363                 if (intel_crtc->pch_pll) {
5364                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5365
5366                         /* Wait for the clocks to stabilize. */
5367                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5368                         udelay(150);
5369
5370                         /* The pixel multiplier can only be updated once the
5371                          * DPLL is enabled and the clocks are stable.
5372                          *
5373                          * So write it again.
5374                          */
5375                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5376                 }
5377
5378                 if (intel_crtc->pch_pll) {
5379                         if (is_lvds && has_reduced_clock && i915_powersave) {
5380                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5381                                 intel_crtc->lowfreq_avail = true;
5382                         } else {
5383                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5384                         }
5385                 }
5386         }
5387
5388         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5389
5390         if (!is_dp || is_cpu_edp)
5391                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5392
5393         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5394                 if (is_cpu_edp)
5395                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5396
5397         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5398
5399         /* Set up the display plane register */
5400         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5401         POSTING_READ(DSPCNTR(plane));
5402
5403         ret = intel_pipe_set_base(crtc, x, y, fb);
5404
5405         intel_update_watermarks(dev);
5406
5407         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5408
5409         return ret;
5410 }
5411
5412 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5413                                struct drm_display_mode *mode,
5414                                struct drm_display_mode *adjusted_mode,
5415                                int x, int y,
5416                                struct drm_framebuffer *fb)
5417 {
5418         struct drm_device *dev = crtc->dev;
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421         int pipe = intel_crtc->pipe;
5422         int ret;
5423
5424         drm_vblank_pre_modeset(dev, pipe);
5425
5426         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5427                                               x, y, fb);
5428         drm_vblank_post_modeset(dev, pipe);
5429
5430         return ret;
5431 }
5432
5433 static bool intel_eld_uptodate(struct drm_connector *connector,
5434                                int reg_eldv, uint32_t bits_eldv,
5435                                int reg_elda, uint32_t bits_elda,
5436                                int reg_edid)
5437 {
5438         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5439         uint8_t *eld = connector->eld;
5440         uint32_t i;
5441
5442         i = I915_READ(reg_eldv);
5443         i &= bits_eldv;
5444
5445         if (!eld[0])
5446                 return !i;
5447
5448         if (!i)
5449                 return false;
5450
5451         i = I915_READ(reg_elda);
5452         i &= ~bits_elda;
5453         I915_WRITE(reg_elda, i);
5454
5455         for (i = 0; i < eld[2]; i++)
5456                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5457                         return false;
5458
5459         return true;
5460 }
5461
5462 static void g4x_write_eld(struct drm_connector *connector,
5463                           struct drm_crtc *crtc)
5464 {
5465         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5466         uint8_t *eld = connector->eld;
5467         uint32_t eldv;
5468         uint32_t len;
5469         uint32_t i;
5470
5471         i = I915_READ(G4X_AUD_VID_DID);
5472
5473         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5474                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5475         else
5476                 eldv = G4X_ELDV_DEVCTG;
5477
5478         if (intel_eld_uptodate(connector,
5479                                G4X_AUD_CNTL_ST, eldv,
5480                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5481                                G4X_HDMIW_HDMIEDID))
5482                 return;
5483
5484         i = I915_READ(G4X_AUD_CNTL_ST);
5485         i &= ~(eldv | G4X_ELD_ADDR);
5486         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5487         I915_WRITE(G4X_AUD_CNTL_ST, i);
5488
5489         if (!eld[0])
5490                 return;
5491
5492         len = min_t(uint8_t, eld[2], len);
5493         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5494         for (i = 0; i < len; i++)
5495                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5496
5497         i = I915_READ(G4X_AUD_CNTL_ST);
5498         i |= eldv;
5499         I915_WRITE(G4X_AUD_CNTL_ST, i);
5500 }
5501
5502 static void haswell_write_eld(struct drm_connector *connector,
5503                                      struct drm_crtc *crtc)
5504 {
5505         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5506         uint8_t *eld = connector->eld;
5507         struct drm_device *dev = crtc->dev;
5508         uint32_t eldv;
5509         uint32_t i;
5510         int len;
5511         int pipe = to_intel_crtc(crtc)->pipe;
5512         int tmp;
5513
5514         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5515         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5516         int aud_config = HSW_AUD_CFG(pipe);
5517         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5518
5519
5520         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5521
5522         /* Audio output enable */
5523         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5524         tmp = I915_READ(aud_cntrl_st2);
5525         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5526         I915_WRITE(aud_cntrl_st2, tmp);
5527
5528         /* Wait for 1 vertical blank */
5529         intel_wait_for_vblank(dev, pipe);
5530
5531         /* Set ELD valid state */
5532         tmp = I915_READ(aud_cntrl_st2);
5533         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5534         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5535         I915_WRITE(aud_cntrl_st2, tmp);
5536         tmp = I915_READ(aud_cntrl_st2);
5537         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5538
5539         /* Enable HDMI mode */
5540         tmp = I915_READ(aud_config);
5541         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5542         /* clear N_programing_enable and N_value_index */
5543         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5544         I915_WRITE(aud_config, tmp);
5545
5546         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5547
5548         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5549
5550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5551                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5552                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5553                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5554         } else
5555                 I915_WRITE(aud_config, 0);
5556
5557         if (intel_eld_uptodate(connector,
5558                                aud_cntrl_st2, eldv,
5559                                aud_cntl_st, IBX_ELD_ADDRESS,
5560                                hdmiw_hdmiedid))
5561                 return;
5562
5563         i = I915_READ(aud_cntrl_st2);
5564         i &= ~eldv;
5565         I915_WRITE(aud_cntrl_st2, i);
5566
5567         if (!eld[0])
5568                 return;
5569
5570         i = I915_READ(aud_cntl_st);
5571         i &= ~IBX_ELD_ADDRESS;
5572         I915_WRITE(aud_cntl_st, i);
5573         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5574         DRM_DEBUG_DRIVER("port num:%d\n", i);
5575
5576         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5577         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5578         for (i = 0; i < len; i++)
5579                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5580
5581         i = I915_READ(aud_cntrl_st2);
5582         i |= eldv;
5583         I915_WRITE(aud_cntrl_st2, i);
5584
5585 }
5586
5587 static void ironlake_write_eld(struct drm_connector *connector,
5588                                      struct drm_crtc *crtc)
5589 {
5590         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5591         uint8_t *eld = connector->eld;
5592         uint32_t eldv;
5593         uint32_t i;
5594         int len;
5595         int hdmiw_hdmiedid;
5596         int aud_config;
5597         int aud_cntl_st;
5598         int aud_cntrl_st2;
5599         int pipe = to_intel_crtc(crtc)->pipe;
5600
5601         if (HAS_PCH_IBX(connector->dev)) {
5602                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5603                 aud_config = IBX_AUD_CFG(pipe);
5604                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5605                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5606         } else {
5607                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5608                 aud_config = CPT_AUD_CFG(pipe);
5609                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5610                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5611         }
5612
5613         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5614
5615         i = I915_READ(aud_cntl_st);
5616         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5617         if (!i) {
5618                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5619                 /* operate blindly on all ports */
5620                 eldv = IBX_ELD_VALIDB;
5621                 eldv |= IBX_ELD_VALIDB << 4;
5622                 eldv |= IBX_ELD_VALIDB << 8;
5623         } else {
5624                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5625                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5626         }
5627
5628         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5629                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5630                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5631                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5632         } else
5633                 I915_WRITE(aud_config, 0);
5634
5635         if (intel_eld_uptodate(connector,
5636                                aud_cntrl_st2, eldv,
5637                                aud_cntl_st, IBX_ELD_ADDRESS,
5638                                hdmiw_hdmiedid))
5639                 return;
5640
5641         i = I915_READ(aud_cntrl_st2);
5642         i &= ~eldv;
5643         I915_WRITE(aud_cntrl_st2, i);
5644
5645         if (!eld[0])
5646                 return;
5647
5648         i = I915_READ(aud_cntl_st);
5649         i &= ~IBX_ELD_ADDRESS;
5650         I915_WRITE(aud_cntl_st, i);
5651
5652         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5653         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5654         for (i = 0; i < len; i++)
5655                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5656
5657         i = I915_READ(aud_cntrl_st2);
5658         i |= eldv;
5659         I915_WRITE(aud_cntrl_st2, i);
5660 }
5661
5662 void intel_write_eld(struct drm_encoder *encoder,
5663                      struct drm_display_mode *mode)
5664 {
5665         struct drm_crtc *crtc = encoder->crtc;
5666         struct drm_connector *connector;
5667         struct drm_device *dev = encoder->dev;
5668         struct drm_i915_private *dev_priv = dev->dev_private;
5669
5670         connector = drm_select_eld(encoder, mode);
5671         if (!connector)
5672                 return;
5673
5674         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5675                          connector->base.id,
5676                          drm_get_connector_name(connector),
5677                          connector->encoder->base.id,
5678                          drm_get_encoder_name(connector->encoder));
5679
5680         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5681
5682         if (dev_priv->display.write_eld)
5683                 dev_priv->display.write_eld(connector, crtc);
5684 }
5685
5686 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5687 void intel_crtc_load_lut(struct drm_crtc *crtc)
5688 {
5689         struct drm_device *dev = crtc->dev;
5690         struct drm_i915_private *dev_priv = dev->dev_private;
5691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692         int palreg = PALETTE(intel_crtc->pipe);
5693         int i;
5694
5695         /* The clocks have to be on to load the palette. */
5696         if (!crtc->enabled || !intel_crtc->active)
5697                 return;
5698
5699         /* use legacy palette for Ironlake */
5700         if (HAS_PCH_SPLIT(dev))
5701                 palreg = LGC_PALETTE(intel_crtc->pipe);
5702
5703         for (i = 0; i < 256; i++) {
5704                 I915_WRITE(palreg + 4 * i,
5705                            (intel_crtc->lut_r[i] << 16) |
5706                            (intel_crtc->lut_g[i] << 8) |
5707                            intel_crtc->lut_b[i]);
5708         }
5709 }
5710
5711 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5712 {
5713         struct drm_device *dev = crtc->dev;
5714         struct drm_i915_private *dev_priv = dev->dev_private;
5715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716         bool visible = base != 0;
5717         u32 cntl;
5718
5719         if (intel_crtc->cursor_visible == visible)
5720                 return;
5721
5722         cntl = I915_READ(_CURACNTR);
5723         if (visible) {
5724                 /* On these chipsets we can only modify the base whilst
5725                  * the cursor is disabled.
5726                  */
5727                 I915_WRITE(_CURABASE, base);
5728
5729                 cntl &= ~(CURSOR_FORMAT_MASK);
5730                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5731                 cntl |= CURSOR_ENABLE |
5732                         CURSOR_GAMMA_ENABLE |
5733                         CURSOR_FORMAT_ARGB;
5734         } else
5735                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5736         I915_WRITE(_CURACNTR, cntl);
5737
5738         intel_crtc->cursor_visible = visible;
5739 }
5740
5741 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5742 {
5743         struct drm_device *dev = crtc->dev;
5744         struct drm_i915_private *dev_priv = dev->dev_private;
5745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5746         int pipe = intel_crtc->pipe;
5747         bool visible = base != 0;
5748
5749         if (intel_crtc->cursor_visible != visible) {
5750                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5751                 if (base) {
5752                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5753                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5754                         cntl |= pipe << 28; /* Connect to correct pipe */
5755                 } else {
5756                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5757                         cntl |= CURSOR_MODE_DISABLE;
5758                 }
5759                 I915_WRITE(CURCNTR(pipe), cntl);
5760
5761                 intel_crtc->cursor_visible = visible;
5762         }
5763         /* and commit changes on next vblank */
5764         I915_WRITE(CURBASE(pipe), base);
5765 }
5766
5767 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5768 {
5769         struct drm_device *dev = crtc->dev;
5770         struct drm_i915_private *dev_priv = dev->dev_private;
5771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5772         int pipe = intel_crtc->pipe;
5773         bool visible = base != 0;
5774
5775         if (intel_crtc->cursor_visible != visible) {
5776                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5777                 if (base) {
5778                         cntl &= ~CURSOR_MODE;
5779                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5780                 } else {
5781                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5782                         cntl |= CURSOR_MODE_DISABLE;
5783                 }
5784                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5785
5786                 intel_crtc->cursor_visible = visible;
5787         }
5788         /* and commit changes on next vblank */
5789         I915_WRITE(CURBASE_IVB(pipe), base);
5790 }
5791
5792 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5793 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5794                                      bool on)
5795 {
5796         struct drm_device *dev = crtc->dev;
5797         struct drm_i915_private *dev_priv = dev->dev_private;
5798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799         int pipe = intel_crtc->pipe;
5800         int x = intel_crtc->cursor_x;
5801         int y = intel_crtc->cursor_y;
5802         u32 base, pos;
5803         bool visible;
5804
5805         pos = 0;
5806
5807         if (on && crtc->enabled && crtc->fb) {
5808                 base = intel_crtc->cursor_addr;
5809                 if (x > (int) crtc->fb->width)
5810                         base = 0;
5811
5812                 if (y > (int) crtc->fb->height)
5813                         base = 0;
5814         } else
5815                 base = 0;
5816
5817         if (x < 0) {
5818                 if (x + intel_crtc->cursor_width < 0)
5819                         base = 0;
5820
5821                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5822                 x = -x;
5823         }
5824         pos |= x << CURSOR_X_SHIFT;
5825
5826         if (y < 0) {
5827                 if (y + intel_crtc->cursor_height < 0)
5828                         base = 0;
5829
5830                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5831                 y = -y;
5832         }
5833         pos |= y << CURSOR_Y_SHIFT;
5834
5835         visible = base != 0;
5836         if (!visible && !intel_crtc->cursor_visible)
5837                 return;
5838
5839         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5840                 I915_WRITE(CURPOS_IVB(pipe), pos);
5841                 ivb_update_cursor(crtc, base);
5842         } else {
5843                 I915_WRITE(CURPOS(pipe), pos);
5844                 if (IS_845G(dev) || IS_I865G(dev))
5845                         i845_update_cursor(crtc, base);
5846                 else
5847                         i9xx_update_cursor(crtc, base);
5848         }
5849 }
5850
5851 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5852                                  struct drm_file *file,
5853                                  uint32_t handle,
5854                                  uint32_t width, uint32_t height)
5855 {
5856         struct drm_device *dev = crtc->dev;
5857         struct drm_i915_private *dev_priv = dev->dev_private;
5858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5859         struct drm_i915_gem_object *obj;
5860         uint32_t addr;
5861         int ret;
5862
5863         /* if we want to turn off the cursor ignore width and height */
5864         if (!handle) {
5865                 DRM_DEBUG_KMS("cursor off\n");
5866                 addr = 0;
5867                 obj = NULL;
5868                 mutex_lock(&dev->struct_mutex);
5869                 goto finish;
5870         }
5871
5872         /* Currently we only support 64x64 cursors */
5873         if (width != 64 || height != 64) {
5874                 DRM_ERROR("we currently only support 64x64 cursors\n");
5875                 return -EINVAL;
5876         }
5877
5878         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5879         if (&obj->base == NULL)
5880                 return -ENOENT;
5881
5882         if (obj->base.size < width * height * 4) {
5883                 DRM_ERROR("buffer is to small\n");
5884                 ret = -ENOMEM;
5885                 goto fail;
5886         }
5887
5888         /* we only need to pin inside GTT if cursor is non-phy */
5889         mutex_lock(&dev->struct_mutex);
5890         if (!dev_priv->info->cursor_needs_physical) {
5891                 if (obj->tiling_mode) {
5892                         DRM_ERROR("cursor cannot be tiled\n");
5893                         ret = -EINVAL;
5894                         goto fail_locked;
5895                 }
5896
5897                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5898                 if (ret) {
5899                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5900                         goto fail_locked;
5901                 }
5902
5903                 ret = i915_gem_object_put_fence(obj);
5904                 if (ret) {
5905                         DRM_ERROR("failed to release fence for cursor");
5906                         goto fail_unpin;
5907                 }
5908
5909                 addr = obj->gtt_offset;
5910         } else {
5911                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5912                 ret = i915_gem_attach_phys_object(dev, obj,
5913                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5914                                                   align);
5915                 if (ret) {
5916                         DRM_ERROR("failed to attach phys object\n");
5917                         goto fail_locked;
5918                 }
5919                 addr = obj->phys_obj->handle->busaddr;
5920         }
5921
5922         if (IS_GEN2(dev))
5923                 I915_WRITE(CURSIZE, (height << 12) | width);
5924
5925  finish:
5926         if (intel_crtc->cursor_bo) {
5927                 if (dev_priv->info->cursor_needs_physical) {
5928                         if (intel_crtc->cursor_bo != obj)
5929                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5930                 } else
5931                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5932                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5933         }
5934
5935         mutex_unlock(&dev->struct_mutex);
5936
5937         intel_crtc->cursor_addr = addr;
5938         intel_crtc->cursor_bo = obj;
5939         intel_crtc->cursor_width = width;
5940         intel_crtc->cursor_height = height;
5941
5942         intel_crtc_update_cursor(crtc, true);
5943
5944         return 0;
5945 fail_unpin:
5946         i915_gem_object_unpin(obj);
5947 fail_locked:
5948         mutex_unlock(&dev->struct_mutex);
5949 fail:
5950         drm_gem_object_unreference_unlocked(&obj->base);
5951         return ret;
5952 }
5953
5954 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5955 {
5956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957
5958         intel_crtc->cursor_x = x;
5959         intel_crtc->cursor_y = y;
5960
5961         intel_crtc_update_cursor(crtc, true);
5962
5963         return 0;
5964 }
5965
5966 /** Sets the color ramps on behalf of RandR */
5967 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5968                                  u16 blue, int regno)
5969 {
5970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5971
5972         intel_crtc->lut_r[regno] = red >> 8;
5973         intel_crtc->lut_g[regno] = green >> 8;
5974         intel_crtc->lut_b[regno] = blue >> 8;
5975 }
5976
5977 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5978                              u16 *blue, int regno)
5979 {
5980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5981
5982         *red = intel_crtc->lut_r[regno] << 8;
5983         *green = intel_crtc->lut_g[regno] << 8;
5984         *blue = intel_crtc->lut_b[regno] << 8;
5985 }
5986
5987 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5988                                  u16 *blue, uint32_t start, uint32_t size)
5989 {
5990         int end = (start + size > 256) ? 256 : start + size, i;
5991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5992
5993         for (i = start; i < end; i++) {
5994                 intel_crtc->lut_r[i] = red[i] >> 8;
5995                 intel_crtc->lut_g[i] = green[i] >> 8;
5996                 intel_crtc->lut_b[i] = blue[i] >> 8;
5997         }
5998
5999         intel_crtc_load_lut(crtc);
6000 }
6001
6002 /**
6003  * Get a pipe with a simple mode set on it for doing load-based monitor
6004  * detection.
6005  *
6006  * It will be up to the load-detect code to adjust the pipe as appropriate for
6007  * its requirements.  The pipe will be connected to no other encoders.
6008  *
6009  * Currently this code will only succeed if there is a pipe with no encoders
6010  * configured for it.  In the future, it could choose to temporarily disable
6011  * some outputs to free up a pipe for its use.
6012  *
6013  * \return crtc, or NULL if no pipes are available.
6014  */
6015
6016 /* VESA 640x480x72Hz mode to set on the pipe */
6017 static struct drm_display_mode load_detect_mode = {
6018         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6019                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6020 };
6021
6022 static struct drm_framebuffer *
6023 intel_framebuffer_create(struct drm_device *dev,
6024                          struct drm_mode_fb_cmd2 *mode_cmd,
6025                          struct drm_i915_gem_object *obj)
6026 {
6027         struct intel_framebuffer *intel_fb;
6028         int ret;
6029
6030         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6031         if (!intel_fb) {
6032                 drm_gem_object_unreference_unlocked(&obj->base);
6033                 return ERR_PTR(-ENOMEM);
6034         }
6035
6036         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6037         if (ret) {
6038                 drm_gem_object_unreference_unlocked(&obj->base);
6039                 kfree(intel_fb);
6040                 return ERR_PTR(ret);
6041         }
6042
6043         return &intel_fb->base;
6044 }
6045
6046 static u32
6047 intel_framebuffer_pitch_for_width(int width, int bpp)
6048 {
6049         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6050         return ALIGN(pitch, 64);
6051 }
6052
6053 static u32
6054 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6055 {
6056         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6057         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6058 }
6059
6060 static struct drm_framebuffer *
6061 intel_framebuffer_create_for_mode(struct drm_device *dev,
6062                                   struct drm_display_mode *mode,
6063                                   int depth, int bpp)
6064 {
6065         struct drm_i915_gem_object *obj;
6066         struct drm_mode_fb_cmd2 mode_cmd;
6067
6068         obj = i915_gem_alloc_object(dev,
6069                                     intel_framebuffer_size_for_mode(mode, bpp));
6070         if (obj == NULL)
6071                 return ERR_PTR(-ENOMEM);
6072
6073         mode_cmd.width = mode->hdisplay;
6074         mode_cmd.height = mode->vdisplay;
6075         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6076                                                                 bpp);
6077         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6078
6079         return intel_framebuffer_create(dev, &mode_cmd, obj);
6080 }
6081
6082 static struct drm_framebuffer *
6083 mode_fits_in_fbdev(struct drm_device *dev,
6084                    struct drm_display_mode *mode)
6085 {
6086         struct drm_i915_private *dev_priv = dev->dev_private;
6087         struct drm_i915_gem_object *obj;
6088         struct drm_framebuffer *fb;
6089
6090         if (dev_priv->fbdev == NULL)
6091                 return NULL;
6092
6093         obj = dev_priv->fbdev->ifb.obj;
6094         if (obj == NULL)
6095                 return NULL;
6096
6097         fb = &dev_priv->fbdev->ifb.base;
6098         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6099                                                                fb->bits_per_pixel))
6100                 return NULL;
6101
6102         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6103                 return NULL;
6104
6105         return fb;
6106 }
6107
6108 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6109                                 struct drm_display_mode *mode,
6110                                 struct intel_load_detect_pipe *old)
6111 {
6112         struct intel_crtc *intel_crtc;
6113         struct intel_encoder *intel_encoder =
6114                 intel_attached_encoder(connector);
6115         struct drm_crtc *possible_crtc;
6116         struct drm_encoder *encoder = &intel_encoder->base;
6117         struct drm_crtc *crtc = NULL;
6118         struct drm_device *dev = encoder->dev;
6119         struct drm_framebuffer *fb;
6120         int i = -1;
6121
6122         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6123                       connector->base.id, drm_get_connector_name(connector),
6124                       encoder->base.id, drm_get_encoder_name(encoder));
6125
6126         /*
6127          * Algorithm gets a little messy:
6128          *
6129          *   - if the connector already has an assigned crtc, use it (but make
6130          *     sure it's on first)
6131          *
6132          *   - try to find the first unused crtc that can drive this connector,
6133          *     and use that if we find one
6134          */
6135
6136         /* See if we already have a CRTC for this connector */
6137         if (encoder->crtc) {
6138                 crtc = encoder->crtc;
6139
6140                 old->dpms_mode = connector->dpms;
6141                 old->load_detect_temp = false;
6142
6143                 /* Make sure the crtc and connector are running */
6144                 if (connector->dpms != DRM_MODE_DPMS_ON)
6145                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6146
6147                 return true;
6148         }
6149
6150         /* Find an unused one (if possible) */
6151         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6152                 i++;
6153                 if (!(encoder->possible_crtcs & (1 << i)))
6154                         continue;
6155                 if (!possible_crtc->enabled) {
6156                         crtc = possible_crtc;
6157                         break;
6158                 }
6159         }
6160
6161         /*
6162          * If we didn't find an unused CRTC, don't use any.
6163          */
6164         if (!crtc) {
6165                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6166                 return false;
6167         }
6168
6169         intel_encoder->new_crtc = to_intel_crtc(crtc);
6170         to_intel_connector(connector)->new_encoder = intel_encoder;
6171
6172         intel_crtc = to_intel_crtc(crtc);
6173         old->dpms_mode = connector->dpms;
6174         old->load_detect_temp = true;
6175         old->release_fb = NULL;
6176
6177         if (!mode)
6178                 mode = &load_detect_mode;
6179
6180         /* We need a framebuffer large enough to accommodate all accesses
6181          * that the plane may generate whilst we perform load detection.
6182          * We can not rely on the fbcon either being present (we get called
6183          * during its initialisation to detect all boot displays, or it may
6184          * not even exist) or that it is large enough to satisfy the
6185          * requested mode.
6186          */
6187         fb = mode_fits_in_fbdev(dev, mode);
6188         if (fb == NULL) {
6189                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6190                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6191                 old->release_fb = fb;
6192         } else
6193                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6194         if (IS_ERR(fb)) {
6195                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6196                 goto fail;
6197         }
6198
6199         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6200                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6201                 if (old->release_fb)
6202                         old->release_fb->funcs->destroy(old->release_fb);
6203                 goto fail;
6204         }
6205
6206         /* let the connector get through one full cycle before testing */
6207         intel_wait_for_vblank(dev, intel_crtc->pipe);
6208
6209         return true;
6210 fail:
6211         connector->encoder = NULL;
6212         encoder->crtc = NULL;
6213         return false;
6214 }
6215
6216 void intel_release_load_detect_pipe(struct drm_connector *connector,
6217                                     struct intel_load_detect_pipe *old)
6218 {
6219         struct intel_encoder *intel_encoder =
6220                 intel_attached_encoder(connector);
6221         struct drm_encoder *encoder = &intel_encoder->base;
6222
6223         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6224                       connector->base.id, drm_get_connector_name(connector),
6225                       encoder->base.id, drm_get_encoder_name(encoder));
6226
6227         if (old->load_detect_temp) {
6228                 struct drm_crtc *crtc = encoder->crtc;
6229
6230                 to_intel_connector(connector)->new_encoder = NULL;
6231                 intel_encoder->new_crtc = NULL;
6232                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6233
6234                 if (old->release_fb)
6235                         old->release_fb->funcs->destroy(old->release_fb);
6236
6237                 return;
6238         }
6239
6240         /* Switch crtc and encoder back off if necessary */
6241         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6242                 connector->funcs->dpms(connector, old->dpms_mode);
6243 }
6244
6245 /* Returns the clock of the currently programmed mode of the given pipe. */
6246 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6247 {
6248         struct drm_i915_private *dev_priv = dev->dev_private;
6249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6250         int pipe = intel_crtc->pipe;
6251         u32 dpll = I915_READ(DPLL(pipe));
6252         u32 fp;
6253         intel_clock_t clock;
6254
6255         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6256                 fp = I915_READ(FP0(pipe));
6257         else
6258                 fp = I915_READ(FP1(pipe));
6259
6260         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6261         if (IS_PINEVIEW(dev)) {
6262                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6263                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6264         } else {
6265                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6266                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6267         }
6268
6269         if (!IS_GEN2(dev)) {
6270                 if (IS_PINEVIEW(dev))
6271                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6272                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6273                 else
6274                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6275                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6276
6277                 switch (dpll & DPLL_MODE_MASK) {
6278                 case DPLLB_MODE_DAC_SERIAL:
6279                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6280                                 5 : 10;
6281                         break;
6282                 case DPLLB_MODE_LVDS:
6283                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6284                                 7 : 14;
6285                         break;
6286                 default:
6287                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6288                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6289                         return 0;
6290                 }
6291
6292                 /* XXX: Handle the 100Mhz refclk */
6293                 intel_clock(dev, 96000, &clock);
6294         } else {
6295                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6296
6297                 if (is_lvds) {
6298                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6299                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6300                         clock.p2 = 14;
6301
6302                         if ((dpll & PLL_REF_INPUT_MASK) ==
6303                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6304                                 /* XXX: might not be 66MHz */
6305                                 intel_clock(dev, 66000, &clock);
6306                         } else
6307                                 intel_clock(dev, 48000, &clock);
6308                 } else {
6309                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6310                                 clock.p1 = 2;
6311                         else {
6312                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6313                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6314                         }
6315                         if (dpll & PLL_P2_DIVIDE_BY_4)
6316                                 clock.p2 = 4;
6317                         else
6318                                 clock.p2 = 2;
6319
6320                         intel_clock(dev, 48000, &clock);
6321                 }
6322         }
6323
6324         /* XXX: It would be nice to validate the clocks, but we can't reuse
6325          * i830PllIsValid() because it relies on the xf86_config connector
6326          * configuration being accurate, which it isn't necessarily.
6327          */
6328
6329         return clock.dot;
6330 }
6331
6332 /** Returns the currently programmed mode of the given pipe. */
6333 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6334                                              struct drm_crtc *crtc)
6335 {
6336         struct drm_i915_private *dev_priv = dev->dev_private;
6337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338         int pipe = intel_crtc->pipe;
6339         struct drm_display_mode *mode;
6340         int htot = I915_READ(HTOTAL(pipe));
6341         int hsync = I915_READ(HSYNC(pipe));
6342         int vtot = I915_READ(VTOTAL(pipe));
6343         int vsync = I915_READ(VSYNC(pipe));
6344
6345         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6346         if (!mode)
6347                 return NULL;
6348
6349         mode->clock = intel_crtc_clock_get(dev, crtc);
6350         mode->hdisplay = (htot & 0xffff) + 1;
6351         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6352         mode->hsync_start = (hsync & 0xffff) + 1;
6353         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6354         mode->vdisplay = (vtot & 0xffff) + 1;
6355         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6356         mode->vsync_start = (vsync & 0xffff) + 1;
6357         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6358
6359         drm_mode_set_name(mode);
6360
6361         return mode;
6362 }
6363
6364 static void intel_increase_pllclock(struct drm_crtc *crtc)
6365 {
6366         struct drm_device *dev = crtc->dev;
6367         drm_i915_private_t *dev_priv = dev->dev_private;
6368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369         int pipe = intel_crtc->pipe;
6370         int dpll_reg = DPLL(pipe);
6371         int dpll;
6372
6373         if (HAS_PCH_SPLIT(dev))
6374                 return;
6375
6376         if (!dev_priv->lvds_downclock_avail)
6377                 return;
6378
6379         dpll = I915_READ(dpll_reg);
6380         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6381                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6382
6383                 assert_panel_unlocked(dev_priv, pipe);
6384
6385                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6386                 I915_WRITE(dpll_reg, dpll);
6387                 intel_wait_for_vblank(dev, pipe);
6388
6389                 dpll = I915_READ(dpll_reg);
6390                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6391                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6392         }
6393 }
6394
6395 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6396 {
6397         struct drm_device *dev = crtc->dev;
6398         drm_i915_private_t *dev_priv = dev->dev_private;
6399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400
6401         if (HAS_PCH_SPLIT(dev))
6402                 return;
6403
6404         if (!dev_priv->lvds_downclock_avail)
6405                 return;
6406
6407         /*
6408          * Since this is called by a timer, we should never get here in
6409          * the manual case.
6410          */
6411         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6412                 int pipe = intel_crtc->pipe;
6413                 int dpll_reg = DPLL(pipe);
6414                 int dpll;
6415
6416                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6417
6418                 assert_panel_unlocked(dev_priv, pipe);
6419
6420                 dpll = I915_READ(dpll_reg);
6421                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6422                 I915_WRITE(dpll_reg, dpll);
6423                 intel_wait_for_vblank(dev, pipe);
6424                 dpll = I915_READ(dpll_reg);
6425                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6426                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6427         }
6428
6429 }
6430
6431 void intel_mark_busy(struct drm_device *dev)
6432 {
6433         i915_update_gfx_val(dev->dev_private);
6434 }
6435
6436 void intel_mark_idle(struct drm_device *dev)
6437 {
6438 }
6439
6440 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6441 {
6442         struct drm_device *dev = obj->base.dev;
6443         struct drm_crtc *crtc;
6444
6445         if (!i915_powersave)
6446                 return;
6447
6448         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6449                 if (!crtc->fb)
6450                         continue;
6451
6452                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6453                         intel_increase_pllclock(crtc);
6454         }
6455 }
6456
6457 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6458 {
6459         struct drm_device *dev = obj->base.dev;
6460         struct drm_crtc *crtc;
6461
6462         if (!i915_powersave)
6463                 return;
6464
6465         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6466                 if (!crtc->fb)
6467                         continue;
6468
6469                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6470                         intel_decrease_pllclock(crtc);
6471         }
6472 }
6473
6474 static void intel_crtc_destroy(struct drm_crtc *crtc)
6475 {
6476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477         struct drm_device *dev = crtc->dev;
6478         struct intel_unpin_work *work;
6479         unsigned long flags;
6480
6481         spin_lock_irqsave(&dev->event_lock, flags);
6482         work = intel_crtc->unpin_work;
6483         intel_crtc->unpin_work = NULL;
6484         spin_unlock_irqrestore(&dev->event_lock, flags);
6485
6486         if (work) {
6487                 cancel_work_sync(&work->work);
6488                 kfree(work);
6489         }
6490
6491         drm_crtc_cleanup(crtc);
6492
6493         kfree(intel_crtc);
6494 }
6495
6496 static void intel_unpin_work_fn(struct work_struct *__work)
6497 {
6498         struct intel_unpin_work *work =
6499                 container_of(__work, struct intel_unpin_work, work);
6500
6501         mutex_lock(&work->dev->struct_mutex);
6502         intel_unpin_fb_obj(work->old_fb_obj);
6503         drm_gem_object_unreference(&work->pending_flip_obj->base);
6504         drm_gem_object_unreference(&work->old_fb_obj->base);
6505
6506         intel_update_fbc(work->dev);
6507         mutex_unlock(&work->dev->struct_mutex);
6508         kfree(work);
6509 }
6510
6511 static void do_intel_finish_page_flip(struct drm_device *dev,
6512                                       struct drm_crtc *crtc)
6513 {
6514         drm_i915_private_t *dev_priv = dev->dev_private;
6515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6516         struct intel_unpin_work *work;
6517         struct drm_i915_gem_object *obj;
6518         struct drm_pending_vblank_event *e;
6519         struct timeval tvbl;
6520         unsigned long flags;
6521
6522         /* Ignore early vblank irqs */
6523         if (intel_crtc == NULL)
6524                 return;
6525
6526         spin_lock_irqsave(&dev->event_lock, flags);
6527         work = intel_crtc->unpin_work;
6528         if (work == NULL || !work->pending) {
6529                 spin_unlock_irqrestore(&dev->event_lock, flags);
6530                 return;
6531         }
6532
6533         intel_crtc->unpin_work = NULL;
6534
6535         if (work->event) {
6536                 e = work->event;
6537                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6538
6539                 e->event.tv_sec = tvbl.tv_sec;
6540                 e->event.tv_usec = tvbl.tv_usec;
6541
6542                 list_add_tail(&e->base.link,
6543                               &e->base.file_priv->event_list);
6544                 wake_up_interruptible(&e->base.file_priv->event_wait);
6545         }
6546
6547         drm_vblank_put(dev, intel_crtc->pipe);
6548
6549         spin_unlock_irqrestore(&dev->event_lock, flags);
6550
6551         obj = work->old_fb_obj;
6552
6553         atomic_clear_mask(1 << intel_crtc->plane,
6554                           &obj->pending_flip.counter);
6555
6556         wake_up(&dev_priv->pending_flip_queue);
6557         schedule_work(&work->work);
6558
6559         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6560 }
6561
6562 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6563 {
6564         drm_i915_private_t *dev_priv = dev->dev_private;
6565         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6566
6567         do_intel_finish_page_flip(dev, crtc);
6568 }
6569
6570 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6571 {
6572         drm_i915_private_t *dev_priv = dev->dev_private;
6573         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6574
6575         do_intel_finish_page_flip(dev, crtc);
6576 }
6577
6578 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6579 {
6580         drm_i915_private_t *dev_priv = dev->dev_private;
6581         struct intel_crtc *intel_crtc =
6582                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6583         unsigned long flags;
6584
6585         spin_lock_irqsave(&dev->event_lock, flags);
6586         if (intel_crtc->unpin_work) {
6587                 if ((++intel_crtc->unpin_work->pending) > 1)
6588                         DRM_ERROR("Prepared flip multiple times\n");
6589         } else {
6590                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6591         }
6592         spin_unlock_irqrestore(&dev->event_lock, flags);
6593 }
6594
6595 static int intel_gen2_queue_flip(struct drm_device *dev,
6596                                  struct drm_crtc *crtc,
6597                                  struct drm_framebuffer *fb,
6598                                  struct drm_i915_gem_object *obj)
6599 {
6600         struct drm_i915_private *dev_priv = dev->dev_private;
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602         u32 flip_mask;
6603         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6604         int ret;
6605
6606         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6607         if (ret)
6608                 goto err;
6609
6610         ret = intel_ring_begin(ring, 6);
6611         if (ret)
6612                 goto err_unpin;
6613
6614         /* Can't queue multiple flips, so wait for the previous
6615          * one to finish before executing the next.
6616          */
6617         if (intel_crtc->plane)
6618                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6619         else
6620                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6621         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6622         intel_ring_emit(ring, MI_NOOP);
6623         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6624                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6625         intel_ring_emit(ring, fb->pitches[0]);
6626         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6627         intel_ring_emit(ring, 0); /* aux display base address, unused */
6628         intel_ring_advance(ring);
6629         return 0;
6630
6631 err_unpin:
6632         intel_unpin_fb_obj(obj);
6633 err:
6634         return ret;
6635 }
6636
6637 static int intel_gen3_queue_flip(struct drm_device *dev,
6638                                  struct drm_crtc *crtc,
6639                                  struct drm_framebuffer *fb,
6640                                  struct drm_i915_gem_object *obj)
6641 {
6642         struct drm_i915_private *dev_priv = dev->dev_private;
6643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644         u32 flip_mask;
6645         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6646         int ret;
6647
6648         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6649         if (ret)
6650                 goto err;
6651
6652         ret = intel_ring_begin(ring, 6);
6653         if (ret)
6654                 goto err_unpin;
6655
6656         if (intel_crtc->plane)
6657                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6658         else
6659                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6660         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6661         intel_ring_emit(ring, MI_NOOP);
6662         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6663                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6664         intel_ring_emit(ring, fb->pitches[0]);
6665         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6666         intel_ring_emit(ring, MI_NOOP);
6667
6668         intel_ring_advance(ring);
6669         return 0;
6670
6671 err_unpin:
6672         intel_unpin_fb_obj(obj);
6673 err:
6674         return ret;
6675 }
6676
6677 static int intel_gen4_queue_flip(struct drm_device *dev,
6678                                  struct drm_crtc *crtc,
6679                                  struct drm_framebuffer *fb,
6680                                  struct drm_i915_gem_object *obj)
6681 {
6682         struct drm_i915_private *dev_priv = dev->dev_private;
6683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684         uint32_t pf, pipesrc;
6685         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6686         int ret;
6687
6688         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6689         if (ret)
6690                 goto err;
6691
6692         ret = intel_ring_begin(ring, 4);
6693         if (ret)
6694                 goto err_unpin;
6695
6696         /* i965+ uses the linear or tiled offsets from the
6697          * Display Registers (which do not change across a page-flip)
6698          * so we need only reprogram the base address.
6699          */
6700         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6701                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6702         intel_ring_emit(ring, fb->pitches[0]);
6703         intel_ring_emit(ring,
6704                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6705                         obj->tiling_mode);
6706
6707         /* XXX Enabling the panel-fitter across page-flip is so far
6708          * untested on non-native modes, so ignore it for now.
6709          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6710          */
6711         pf = 0;
6712         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6713         intel_ring_emit(ring, pf | pipesrc);
6714         intel_ring_advance(ring);
6715         return 0;
6716
6717 err_unpin:
6718         intel_unpin_fb_obj(obj);
6719 err:
6720         return ret;
6721 }
6722
6723 static int intel_gen6_queue_flip(struct drm_device *dev,
6724                                  struct drm_crtc *crtc,
6725                                  struct drm_framebuffer *fb,
6726                                  struct drm_i915_gem_object *obj)
6727 {
6728         struct drm_i915_private *dev_priv = dev->dev_private;
6729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6730         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6731         uint32_t pf, pipesrc;
6732         int ret;
6733
6734         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6735         if (ret)
6736                 goto err;
6737
6738         ret = intel_ring_begin(ring, 4);
6739         if (ret)
6740                 goto err_unpin;
6741
6742         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6743                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6744         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6745         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6746
6747         /* Contrary to the suggestions in the documentation,
6748          * "Enable Panel Fitter" does not seem to be required when page
6749          * flipping with a non-native mode, and worse causes a normal
6750          * modeset to fail.
6751          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6752          */
6753         pf = 0;
6754         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6755         intel_ring_emit(ring, pf | pipesrc);
6756         intel_ring_advance(ring);
6757         return 0;
6758
6759 err_unpin:
6760         intel_unpin_fb_obj(obj);
6761 err:
6762         return ret;
6763 }
6764
6765 /*
6766  * On gen7 we currently use the blit ring because (in early silicon at least)
6767  * the render ring doesn't give us interrpts for page flip completion, which
6768  * means clients will hang after the first flip is queued.  Fortunately the
6769  * blit ring generates interrupts properly, so use it instead.
6770  */
6771 static int intel_gen7_queue_flip(struct drm_device *dev,
6772                                  struct drm_crtc *crtc,
6773                                  struct drm_framebuffer *fb,
6774                                  struct drm_i915_gem_object *obj)
6775 {
6776         struct drm_i915_private *dev_priv = dev->dev_private;
6777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6779         uint32_t plane_bit = 0;
6780         int ret;
6781
6782         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6783         if (ret)
6784                 goto err;
6785
6786         switch(intel_crtc->plane) {
6787         case PLANE_A:
6788                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6789                 break;
6790         case PLANE_B:
6791                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6792                 break;
6793         case PLANE_C:
6794                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6795                 break;
6796         default:
6797                 WARN_ONCE(1, "unknown plane in flip command\n");
6798                 ret = -ENODEV;
6799                 goto err_unpin;
6800         }
6801
6802         ret = intel_ring_begin(ring, 4);
6803         if (ret)
6804                 goto err_unpin;
6805
6806         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6807         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6808         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6809         intel_ring_emit(ring, (MI_NOOP));
6810         intel_ring_advance(ring);
6811         return 0;
6812
6813 err_unpin:
6814         intel_unpin_fb_obj(obj);
6815 err:
6816         return ret;
6817 }
6818
6819 static int intel_default_queue_flip(struct drm_device *dev,
6820                                     struct drm_crtc *crtc,
6821                                     struct drm_framebuffer *fb,
6822                                     struct drm_i915_gem_object *obj)
6823 {
6824         return -ENODEV;
6825 }
6826
6827 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6828                                 struct drm_framebuffer *fb,
6829                                 struct drm_pending_vblank_event *event)
6830 {
6831         struct drm_device *dev = crtc->dev;
6832         struct drm_i915_private *dev_priv = dev->dev_private;
6833         struct intel_framebuffer *intel_fb;
6834         struct drm_i915_gem_object *obj;
6835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6836         struct intel_unpin_work *work;
6837         unsigned long flags;
6838         int ret;
6839
6840         /* Can't change pixel format via MI display flips. */
6841         if (fb->pixel_format != crtc->fb->pixel_format)
6842                 return -EINVAL;
6843
6844         /*
6845          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6846          * Note that pitch changes could also affect these register.
6847          */
6848         if (INTEL_INFO(dev)->gen > 3 &&
6849             (fb->offsets[0] != crtc->fb->offsets[0] ||
6850              fb->pitches[0] != crtc->fb->pitches[0]))
6851                 return -EINVAL;
6852
6853         work = kzalloc(sizeof *work, GFP_KERNEL);
6854         if (work == NULL)
6855                 return -ENOMEM;
6856
6857         work->event = event;
6858         work->dev = crtc->dev;
6859         intel_fb = to_intel_framebuffer(crtc->fb);
6860         work->old_fb_obj = intel_fb->obj;
6861         INIT_WORK(&work->work, intel_unpin_work_fn);
6862
6863         ret = drm_vblank_get(dev, intel_crtc->pipe);
6864         if (ret)
6865                 goto free_work;
6866
6867         /* We borrow the event spin lock for protecting unpin_work */
6868         spin_lock_irqsave(&dev->event_lock, flags);
6869         if (intel_crtc->unpin_work) {
6870                 spin_unlock_irqrestore(&dev->event_lock, flags);
6871                 kfree(work);
6872                 drm_vblank_put(dev, intel_crtc->pipe);
6873
6874                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6875                 return -EBUSY;
6876         }
6877         intel_crtc->unpin_work = work;
6878         spin_unlock_irqrestore(&dev->event_lock, flags);
6879
6880         intel_fb = to_intel_framebuffer(fb);
6881         obj = intel_fb->obj;
6882
6883         ret = i915_mutex_lock_interruptible(dev);
6884         if (ret)
6885                 goto cleanup;
6886
6887         /* Reference the objects for the scheduled work. */
6888         drm_gem_object_reference(&work->old_fb_obj->base);
6889         drm_gem_object_reference(&obj->base);
6890
6891         crtc->fb = fb;
6892
6893         work->pending_flip_obj = obj;
6894
6895         work->enable_stall_check = true;
6896
6897         /* Block clients from rendering to the new back buffer until
6898          * the flip occurs and the object is no longer visible.
6899          */
6900         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6901
6902         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6903         if (ret)
6904                 goto cleanup_pending;
6905
6906         intel_disable_fbc(dev);
6907         intel_mark_fb_busy(obj);
6908         mutex_unlock(&dev->struct_mutex);
6909
6910         trace_i915_flip_request(intel_crtc->plane, obj);
6911
6912         return 0;
6913
6914 cleanup_pending:
6915         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6916         drm_gem_object_unreference(&work->old_fb_obj->base);
6917         drm_gem_object_unreference(&obj->base);
6918         mutex_unlock(&dev->struct_mutex);
6919
6920 cleanup:
6921         spin_lock_irqsave(&dev->event_lock, flags);
6922         intel_crtc->unpin_work = NULL;
6923         spin_unlock_irqrestore(&dev->event_lock, flags);
6924
6925         drm_vblank_put(dev, intel_crtc->pipe);
6926 free_work:
6927         kfree(work);
6928
6929         return ret;
6930 }
6931
6932 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6933         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6934         .load_lut = intel_crtc_load_lut,
6935         .disable = intel_crtc_noop,
6936 };
6937
6938 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6939 {
6940         struct intel_encoder *other_encoder;
6941         struct drm_crtc *crtc = &encoder->new_crtc->base;
6942
6943         if (WARN_ON(!crtc))
6944                 return false;
6945
6946         list_for_each_entry(other_encoder,
6947                             &crtc->dev->mode_config.encoder_list,
6948                             base.head) {
6949
6950                 if (&other_encoder->new_crtc->base != crtc ||
6951                     encoder == other_encoder)
6952                         continue;
6953                 else
6954                         return true;
6955         }
6956
6957         return false;
6958 }
6959
6960 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6961                                   struct drm_crtc *crtc)
6962 {
6963         struct drm_device *dev;
6964         struct drm_crtc *tmp;
6965         int crtc_mask = 1;
6966
6967         WARN(!crtc, "checking null crtc?\n");
6968
6969         dev = crtc->dev;
6970
6971         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6972                 if (tmp == crtc)
6973                         break;
6974                 crtc_mask <<= 1;
6975         }
6976
6977         if (encoder->possible_crtcs & crtc_mask)
6978                 return true;
6979         return false;
6980 }
6981
6982 /**
6983  * intel_modeset_update_staged_output_state
6984  *
6985  * Updates the staged output configuration state, e.g. after we've read out the
6986  * current hw state.
6987  */
6988 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6989 {
6990         struct intel_encoder *encoder;
6991         struct intel_connector *connector;
6992
6993         list_for_each_entry(connector, &dev->mode_config.connector_list,
6994                             base.head) {
6995                 connector->new_encoder =
6996                         to_intel_encoder(connector->base.encoder);
6997         }
6998
6999         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7000                             base.head) {
7001                 encoder->new_crtc =
7002                         to_intel_crtc(encoder->base.crtc);
7003         }
7004 }
7005
7006 /**
7007  * intel_modeset_commit_output_state
7008  *
7009  * This function copies the stage display pipe configuration to the real one.
7010  */
7011 static void intel_modeset_commit_output_state(struct drm_device *dev)
7012 {
7013         struct intel_encoder *encoder;
7014         struct intel_connector *connector;
7015
7016         list_for_each_entry(connector, &dev->mode_config.connector_list,
7017                             base.head) {
7018                 connector->base.encoder = &connector->new_encoder->base;
7019         }
7020
7021         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7022                             base.head) {
7023                 encoder->base.crtc = &encoder->new_crtc->base;
7024         }
7025 }
7026
7027 static struct drm_display_mode *
7028 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7029                             struct drm_display_mode *mode)
7030 {
7031         struct drm_device *dev = crtc->dev;
7032         struct drm_display_mode *adjusted_mode;
7033         struct drm_encoder_helper_funcs *encoder_funcs;
7034         struct intel_encoder *encoder;
7035
7036         adjusted_mode = drm_mode_duplicate(dev, mode);
7037         if (!adjusted_mode)
7038                 return ERR_PTR(-ENOMEM);
7039
7040         /* Pass our mode to the connectors and the CRTC to give them a chance to
7041          * adjust it according to limitations or connector properties, and also
7042          * a chance to reject the mode entirely.
7043          */
7044         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7045                             base.head) {
7046
7047                 if (&encoder->new_crtc->base != crtc)
7048                         continue;
7049                 encoder_funcs = encoder->base.helper_private;
7050                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7051                                                 adjusted_mode))) {
7052                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7053                         goto fail;
7054                 }
7055         }
7056
7057         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7058                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7059                 goto fail;
7060         }
7061         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7062
7063         return adjusted_mode;
7064 fail:
7065         drm_mode_destroy(dev, adjusted_mode);
7066         return ERR_PTR(-EINVAL);
7067 }
7068
7069 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7070  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7071 static void
7072 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7073                              unsigned *prepare_pipes, unsigned *disable_pipes)
7074 {
7075         struct intel_crtc *intel_crtc;
7076         struct drm_device *dev = crtc->dev;
7077         struct intel_encoder *encoder;
7078         struct intel_connector *connector;
7079         struct drm_crtc *tmp_crtc;
7080
7081         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7082
7083         /* Check which crtcs have changed outputs connected to them, these need
7084          * to be part of the prepare_pipes mask. We don't (yet) support global
7085          * modeset across multiple crtcs, so modeset_pipes will only have one
7086          * bit set at most. */
7087         list_for_each_entry(connector, &dev->mode_config.connector_list,
7088                             base.head) {
7089                 if (connector->base.encoder == &connector->new_encoder->base)
7090                         continue;
7091
7092                 if (connector->base.encoder) {
7093                         tmp_crtc = connector->base.encoder->crtc;
7094
7095                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7096                 }
7097
7098                 if (connector->new_encoder)
7099                         *prepare_pipes |=
7100                                 1 << connector->new_encoder->new_crtc->pipe;
7101         }
7102
7103         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7104                             base.head) {
7105                 if (encoder->base.crtc == &encoder->new_crtc->base)
7106                         continue;
7107
7108                 if (encoder->base.crtc) {
7109                         tmp_crtc = encoder->base.crtc;
7110
7111                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7112                 }
7113
7114                 if (encoder->new_crtc)
7115                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7116         }
7117
7118         /* Check for any pipes that will be fully disabled ... */
7119         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7120                             base.head) {
7121                 bool used = false;
7122
7123                 /* Don't try to disable disabled crtcs. */
7124                 if (!intel_crtc->base.enabled)
7125                         continue;
7126
7127                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7128                                     base.head) {
7129                         if (encoder->new_crtc == intel_crtc)
7130                                 used = true;
7131                 }
7132
7133                 if (!used)
7134                         *disable_pipes |= 1 << intel_crtc->pipe;
7135         }
7136
7137
7138         /* set_mode is also used to update properties on life display pipes. */
7139         intel_crtc = to_intel_crtc(crtc);
7140         if (crtc->enabled)
7141                 *prepare_pipes |= 1 << intel_crtc->pipe;
7142
7143         /* We only support modeset on one single crtc, hence we need to do that
7144          * only for the passed in crtc iff we change anything else than just
7145          * disable crtcs.
7146          *
7147          * This is actually not true, to be fully compatible with the old crtc
7148          * helper we automatically disable _any_ output (i.e. doesn't need to be
7149          * connected to the crtc we're modesetting on) if it's disconnected.
7150          * Which is a rather nutty api (since changed the output configuration
7151          * without userspace's explicit request can lead to confusion), but
7152          * alas. Hence we currently need to modeset on all pipes we prepare. */
7153         if (*prepare_pipes)
7154                 *modeset_pipes = *prepare_pipes;
7155
7156         /* ... and mask these out. */
7157         *modeset_pipes &= ~(*disable_pipes);
7158         *prepare_pipes &= ~(*disable_pipes);
7159 }
7160
7161 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7162 {
7163         struct drm_encoder *encoder;
7164         struct drm_device *dev = crtc->dev;
7165
7166         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7167                 if (encoder->crtc == crtc)
7168                         return true;
7169
7170         return false;
7171 }
7172
7173 static void
7174 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7175 {
7176         struct intel_encoder *intel_encoder;
7177         struct intel_crtc *intel_crtc;
7178         struct drm_connector *connector;
7179
7180         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7181                             base.head) {
7182                 if (!intel_encoder->base.crtc)
7183                         continue;
7184
7185                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7186
7187                 if (prepare_pipes & (1 << intel_crtc->pipe))
7188                         intel_encoder->connectors_active = false;
7189         }
7190
7191         intel_modeset_commit_output_state(dev);
7192
7193         /* Update computed state. */
7194         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7195                             base.head) {
7196                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7197         }
7198
7199         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7200                 if (!connector->encoder || !connector->encoder->crtc)
7201                         continue;
7202
7203                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7204
7205                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7206                         struct drm_property *dpms_property =
7207                                 dev->mode_config.dpms_property;
7208
7209                         connector->dpms = DRM_MODE_DPMS_ON;
7210                         drm_connector_property_set_value(connector,
7211                                                          dpms_property,
7212                                                          DRM_MODE_DPMS_ON);
7213
7214                         intel_encoder = to_intel_encoder(connector->encoder);
7215                         intel_encoder->connectors_active = true;
7216                 }
7217         }
7218
7219 }
7220
7221 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7222         list_for_each_entry((intel_crtc), \
7223                             &(dev)->mode_config.crtc_list, \
7224                             base.head) \
7225                 if (mask & (1 <<(intel_crtc)->pipe)) \
7226
7227 void
7228 intel_modeset_check_state(struct drm_device *dev)
7229 {
7230         struct intel_crtc *crtc;
7231         struct intel_encoder *encoder;
7232         struct intel_connector *connector;
7233
7234         list_for_each_entry(connector, &dev->mode_config.connector_list,
7235                             base.head) {
7236                 /* This also checks the encoder/connector hw state with the
7237                  * ->get_hw_state callbacks. */
7238                 intel_connector_check_state(connector);
7239
7240                 WARN(&connector->new_encoder->base != connector->base.encoder,
7241                      "connector's staged encoder doesn't match current encoder\n");
7242         }
7243
7244         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7245                             base.head) {
7246                 bool enabled = false;
7247                 bool active = false;
7248                 enum pipe pipe, tracked_pipe;
7249
7250                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7251                               encoder->base.base.id,
7252                               drm_get_encoder_name(&encoder->base));
7253
7254                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7255                      "encoder's stage crtc doesn't match current crtc\n");
7256                 WARN(encoder->connectors_active && !encoder->base.crtc,
7257                      "encoder's active_connectors set, but no crtc\n");
7258
7259                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7260                                     base.head) {
7261                         if (connector->base.encoder != &encoder->base)
7262                                 continue;
7263                         enabled = true;
7264                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7265                                 active = true;
7266                 }
7267                 WARN(!!encoder->base.crtc != enabled,
7268                      "encoder's enabled state mismatch "
7269                      "(expected %i, found %i)\n",
7270                      !!encoder->base.crtc, enabled);
7271                 WARN(active && !encoder->base.crtc,
7272                      "active encoder with no crtc\n");
7273
7274                 WARN(encoder->connectors_active != active,
7275                      "encoder's computed active state doesn't match tracked active state "
7276                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7277
7278                 active = encoder->get_hw_state(encoder, &pipe);
7279                 WARN(active != encoder->connectors_active,
7280                      "encoder's hw state doesn't match sw tracking "
7281                      "(expected %i, found %i)\n",
7282                      encoder->connectors_active, active);
7283
7284                 if (!encoder->base.crtc)
7285                         continue;
7286
7287                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7288                 WARN(active && pipe != tracked_pipe,
7289                      "active encoder's pipe doesn't match"
7290                      "(expected %i, found %i)\n",
7291                      tracked_pipe, pipe);
7292
7293         }
7294
7295         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7296                             base.head) {
7297                 bool enabled = false;
7298                 bool active = false;
7299
7300                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7301                               crtc->base.base.id);
7302
7303                 WARN(crtc->active && !crtc->base.enabled,
7304                      "active crtc, but not enabled in sw tracking\n");
7305
7306                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7307                                     base.head) {
7308                         if (encoder->base.crtc != &crtc->base)
7309                                 continue;
7310                         enabled = true;
7311                         if (encoder->connectors_active)
7312                                 active = true;
7313                 }
7314                 WARN(active != crtc->active,
7315                      "crtc's computed active state doesn't match tracked active state "
7316                      "(expected %i, found %i)\n", active, crtc->active);
7317                 WARN(enabled != crtc->base.enabled,
7318                      "crtc's computed enabled state doesn't match tracked enabled state "
7319                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7320
7321                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7322         }
7323 }
7324
7325 bool intel_set_mode(struct drm_crtc *crtc,
7326                     struct drm_display_mode *mode,
7327                     int x, int y, struct drm_framebuffer *fb)
7328 {
7329         struct drm_device *dev = crtc->dev;
7330         drm_i915_private_t *dev_priv = dev->dev_private;
7331         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7332         struct drm_encoder_helper_funcs *encoder_funcs;
7333         struct drm_encoder *encoder;
7334         struct intel_crtc *intel_crtc;
7335         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7336         bool ret = true;
7337
7338         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7339                                      &prepare_pipes, &disable_pipes);
7340
7341         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7342                       modeset_pipes, prepare_pipes, disable_pipes);
7343
7344         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7345                 intel_crtc_disable(&intel_crtc->base);
7346
7347         saved_hwmode = crtc->hwmode;
7348         saved_mode = crtc->mode;
7349
7350         /* Hack: Because we don't (yet) support global modeset on multiple
7351          * crtcs, we don't keep track of the new mode for more than one crtc.
7352          * Hence simply check whether any bit is set in modeset_pipes in all the
7353          * pieces of code that are not yet converted to deal with mutliple crtcs
7354          * changing their mode at the same time. */
7355         adjusted_mode = NULL;
7356         if (modeset_pipes) {
7357                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7358                 if (IS_ERR(adjusted_mode)) {
7359                         return false;
7360                 }
7361         }
7362
7363         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7364                 if (intel_crtc->base.enabled)
7365                         dev_priv->display.crtc_disable(&intel_crtc->base);
7366         }
7367
7368         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7369          * to set it here already despite that we pass it down the callchain.
7370          */
7371         if (modeset_pipes)
7372                 crtc->mode = *mode;
7373
7374         /* Only after disabling all output pipelines that will be changed can we
7375          * update the the output configuration. */
7376         intel_modeset_update_state(dev, prepare_pipes);
7377
7378         /* Set up the DPLL and any encoders state that needs to adjust or depend
7379          * on the DPLL.
7380          */
7381         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7382                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7383                                            mode, adjusted_mode,
7384                                            x, y, fb);
7385                 if (!ret)
7386                     goto done;
7387
7388                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7389
7390                         if (encoder->crtc != &intel_crtc->base)
7391                                 continue;
7392
7393                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7394                                 encoder->base.id, drm_get_encoder_name(encoder),
7395                                 mode->base.id, mode->name);
7396                         encoder_funcs = encoder->helper_private;
7397                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7398                 }
7399         }
7400
7401         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7402         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7403                 dev_priv->display.crtc_enable(&intel_crtc->base);
7404
7405         if (modeset_pipes) {
7406                 /* Store real post-adjustment hardware mode. */
7407                 crtc->hwmode = *adjusted_mode;
7408
7409                 /* Calculate and store various constants which
7410                  * are later needed by vblank and swap-completion
7411                  * timestamping. They are derived from true hwmode.
7412                  */
7413                 drm_calc_timestamping_constants(crtc);
7414         }
7415
7416         /* FIXME: add subpixel order */
7417 done:
7418         drm_mode_destroy(dev, adjusted_mode);
7419         if (!ret && crtc->enabled) {
7420                 crtc->hwmode = saved_hwmode;
7421                 crtc->mode = saved_mode;
7422         } else {
7423                 intel_modeset_check_state(dev);
7424         }
7425
7426         return ret;
7427 }
7428
7429 #undef for_each_intel_crtc_masked
7430
7431 static void intel_set_config_free(struct intel_set_config *config)
7432 {
7433         if (!config)
7434                 return;
7435
7436         kfree(config->save_connector_encoders);
7437         kfree(config->save_encoder_crtcs);
7438         kfree(config);
7439 }
7440
7441 static int intel_set_config_save_state(struct drm_device *dev,
7442                                        struct intel_set_config *config)
7443 {
7444         struct drm_encoder *encoder;
7445         struct drm_connector *connector;
7446         int count;
7447
7448         config->save_encoder_crtcs =
7449                 kcalloc(dev->mode_config.num_encoder,
7450                         sizeof(struct drm_crtc *), GFP_KERNEL);
7451         if (!config->save_encoder_crtcs)
7452                 return -ENOMEM;
7453
7454         config->save_connector_encoders =
7455                 kcalloc(dev->mode_config.num_connector,
7456                         sizeof(struct drm_encoder *), GFP_KERNEL);
7457         if (!config->save_connector_encoders)
7458                 return -ENOMEM;
7459
7460         /* Copy data. Note that driver private data is not affected.
7461          * Should anything bad happen only the expected state is
7462          * restored, not the drivers personal bookkeeping.
7463          */
7464         count = 0;
7465         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7466                 config->save_encoder_crtcs[count++] = encoder->crtc;
7467         }
7468
7469         count = 0;
7470         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7471                 config->save_connector_encoders[count++] = connector->encoder;
7472         }
7473
7474         return 0;
7475 }
7476
7477 static void intel_set_config_restore_state(struct drm_device *dev,
7478                                            struct intel_set_config *config)
7479 {
7480         struct intel_encoder *encoder;
7481         struct intel_connector *connector;
7482         int count;
7483
7484         count = 0;
7485         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7486                 encoder->new_crtc =
7487                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7488         }
7489
7490         count = 0;
7491         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7492                 connector->new_encoder =
7493                         to_intel_encoder(config->save_connector_encoders[count++]);
7494         }
7495 }
7496
7497 static void
7498 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7499                                       struct intel_set_config *config)
7500 {
7501
7502         /* We should be able to check here if the fb has the same properties
7503          * and then just flip_or_move it */
7504         if (set->crtc->fb != set->fb) {
7505                 /* If we have no fb then treat it as a full mode set */
7506                 if (set->crtc->fb == NULL) {
7507                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7508                         config->mode_changed = true;
7509                 } else if (set->fb == NULL) {
7510                         config->mode_changed = true;
7511                 } else if (set->fb->depth != set->crtc->fb->depth) {
7512                         config->mode_changed = true;
7513                 } else if (set->fb->bits_per_pixel !=
7514                            set->crtc->fb->bits_per_pixel) {
7515                         config->mode_changed = true;
7516                 } else
7517                         config->fb_changed = true;
7518         }
7519
7520         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7521                 config->fb_changed = true;
7522
7523         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7524                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7525                 drm_mode_debug_printmodeline(&set->crtc->mode);
7526                 drm_mode_debug_printmodeline(set->mode);
7527                 config->mode_changed = true;
7528         }
7529 }
7530
7531 static int
7532 intel_modeset_stage_output_state(struct drm_device *dev,
7533                                  struct drm_mode_set *set,
7534                                  struct intel_set_config *config)
7535 {
7536         struct drm_crtc *new_crtc;
7537         struct intel_connector *connector;
7538         struct intel_encoder *encoder;
7539         int count, ro;
7540
7541         /* The upper layers ensure that we either disabl a crtc or have a list
7542          * of connectors. For paranoia, double-check this. */
7543         WARN_ON(!set->fb && (set->num_connectors != 0));
7544         WARN_ON(set->fb && (set->num_connectors == 0));
7545
7546         count = 0;
7547         list_for_each_entry(connector, &dev->mode_config.connector_list,
7548                             base.head) {
7549                 /* Otherwise traverse passed in connector list and get encoders
7550                  * for them. */
7551                 for (ro = 0; ro < set->num_connectors; ro++) {
7552                         if (set->connectors[ro] == &connector->base) {
7553                                 connector->new_encoder = connector->encoder;
7554                                 break;
7555                         }
7556                 }
7557
7558                 /* If we disable the crtc, disable all its connectors. Also, if
7559                  * the connector is on the changing crtc but not on the new
7560                  * connector list, disable it. */
7561                 if ((!set->fb || ro == set->num_connectors) &&
7562                     connector->base.encoder &&
7563                     connector->base.encoder->crtc == set->crtc) {
7564                         connector->new_encoder = NULL;
7565
7566                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7567                                 connector->base.base.id,
7568                                 drm_get_connector_name(&connector->base));
7569                 }
7570
7571
7572                 if (&connector->new_encoder->base != connector->base.encoder) {
7573                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7574                         config->mode_changed = true;
7575                 }
7576
7577                 /* Disable all disconnected encoders. */
7578                 if (connector->base.status == connector_status_disconnected)
7579                         connector->new_encoder = NULL;
7580         }
7581         /* connector->new_encoder is now updated for all connectors. */
7582
7583         /* Update crtc of enabled connectors. */
7584         count = 0;
7585         list_for_each_entry(connector, &dev->mode_config.connector_list,
7586                             base.head) {
7587                 if (!connector->new_encoder)
7588                         continue;
7589
7590                 new_crtc = connector->new_encoder->base.crtc;
7591
7592                 for (ro = 0; ro < set->num_connectors; ro++) {
7593                         if (set->connectors[ro] == &connector->base)
7594                                 new_crtc = set->crtc;
7595                 }
7596
7597                 /* Make sure the new CRTC will work with the encoder */
7598                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7599                                            new_crtc)) {
7600                         return -EINVAL;
7601                 }
7602                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7603
7604                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7605                         connector->base.base.id,
7606                         drm_get_connector_name(&connector->base),
7607                         new_crtc->base.id);
7608         }
7609
7610         /* Check for any encoders that needs to be disabled. */
7611         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7612                             base.head) {
7613                 list_for_each_entry(connector,
7614                                     &dev->mode_config.connector_list,
7615                                     base.head) {
7616                         if (connector->new_encoder == encoder) {
7617                                 WARN_ON(!connector->new_encoder->new_crtc);
7618
7619                                 goto next_encoder;
7620                         }
7621                 }
7622                 encoder->new_crtc = NULL;
7623 next_encoder:
7624                 /* Only now check for crtc changes so we don't miss encoders
7625                  * that will be disabled. */
7626                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7627                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7628                         config->mode_changed = true;
7629                 }
7630         }
7631         /* Now we've also updated encoder->new_crtc for all encoders. */
7632
7633         return 0;
7634 }
7635
7636 static int intel_crtc_set_config(struct drm_mode_set *set)
7637 {
7638         struct drm_device *dev;
7639         struct drm_mode_set save_set;
7640         struct intel_set_config *config;
7641         int ret;
7642
7643         BUG_ON(!set);
7644         BUG_ON(!set->crtc);
7645         BUG_ON(!set->crtc->helper_private);
7646
7647         if (!set->mode)
7648                 set->fb = NULL;
7649
7650         /* The fb helper likes to play gross jokes with ->mode_set_config.
7651          * Unfortunately the crtc helper doesn't do much at all for this case,
7652          * so we have to cope with this madness until the fb helper is fixed up. */
7653         if (set->fb && set->num_connectors == 0)
7654                 return 0;
7655
7656         if (set->fb) {
7657                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7658                                 set->crtc->base.id, set->fb->base.id,
7659                                 (int)set->num_connectors, set->x, set->y);
7660         } else {
7661                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7662         }
7663
7664         dev = set->crtc->dev;
7665
7666         ret = -ENOMEM;
7667         config = kzalloc(sizeof(*config), GFP_KERNEL);
7668         if (!config)
7669                 goto out_config;
7670
7671         ret = intel_set_config_save_state(dev, config);
7672         if (ret)
7673                 goto out_config;
7674
7675         save_set.crtc = set->crtc;
7676         save_set.mode = &set->crtc->mode;
7677         save_set.x = set->crtc->x;
7678         save_set.y = set->crtc->y;
7679         save_set.fb = set->crtc->fb;
7680
7681         /* Compute whether we need a full modeset, only an fb base update or no
7682          * change at all. In the future we might also check whether only the
7683          * mode changed, e.g. for LVDS where we only change the panel fitter in
7684          * such cases. */
7685         intel_set_config_compute_mode_changes(set, config);
7686
7687         ret = intel_modeset_stage_output_state(dev, set, config);
7688         if (ret)
7689                 goto fail;
7690
7691         if (config->mode_changed) {
7692                 if (set->mode) {
7693                         DRM_DEBUG_KMS("attempting to set mode from"
7694                                         " userspace\n");
7695                         drm_mode_debug_printmodeline(set->mode);
7696                 }
7697
7698                 if (!intel_set_mode(set->crtc, set->mode,
7699                                     set->x, set->y, set->fb)) {
7700                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7701                                   set->crtc->base.id);
7702                         ret = -EINVAL;
7703                         goto fail;
7704                 }
7705         } else if (config->fb_changed) {
7706                 ret = intel_pipe_set_base(set->crtc,
7707                                           set->x, set->y, set->fb);
7708         }
7709
7710         intel_set_config_free(config);
7711
7712         return 0;
7713
7714 fail:
7715         intel_set_config_restore_state(dev, config);
7716
7717         /* Try to restore the config */
7718         if (config->mode_changed &&
7719             !intel_set_mode(save_set.crtc, save_set.mode,
7720                             save_set.x, save_set.y, save_set.fb))
7721                 DRM_ERROR("failed to restore config after modeset failure\n");
7722
7723 out_config:
7724         intel_set_config_free(config);
7725         return ret;
7726 }
7727
7728 static const struct drm_crtc_funcs intel_crtc_funcs = {
7729         .cursor_set = intel_crtc_cursor_set,
7730         .cursor_move = intel_crtc_cursor_move,
7731         .gamma_set = intel_crtc_gamma_set,
7732         .set_config = intel_crtc_set_config,
7733         .destroy = intel_crtc_destroy,
7734         .page_flip = intel_crtc_page_flip,
7735 };
7736
7737 static void intel_cpu_pll_init(struct drm_device *dev)
7738 {
7739         if (IS_HASWELL(dev))
7740                 intel_ddi_pll_init(dev);
7741 }
7742
7743 static void intel_pch_pll_init(struct drm_device *dev)
7744 {
7745         drm_i915_private_t *dev_priv = dev->dev_private;
7746         int i;
7747
7748         if (dev_priv->num_pch_pll == 0) {
7749                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7750                 return;
7751         }
7752
7753         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7754                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7755                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7756                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7757         }
7758 }
7759
7760 static void intel_crtc_init(struct drm_device *dev, int pipe)
7761 {
7762         drm_i915_private_t *dev_priv = dev->dev_private;
7763         struct intel_crtc *intel_crtc;
7764         int i;
7765
7766         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7767         if (intel_crtc == NULL)
7768                 return;
7769
7770         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7771
7772         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7773         for (i = 0; i < 256; i++) {
7774                 intel_crtc->lut_r[i] = i;
7775                 intel_crtc->lut_g[i] = i;
7776                 intel_crtc->lut_b[i] = i;
7777         }
7778
7779         /* Swap pipes & planes for FBC on pre-965 */
7780         intel_crtc->pipe = pipe;
7781         intel_crtc->plane = pipe;
7782         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7783                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7784                 intel_crtc->plane = !pipe;
7785         }
7786
7787         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7788                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7789         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7790         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7791
7792         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7793
7794         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7795 }
7796
7797 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7798                                 struct drm_file *file)
7799 {
7800         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7801         struct drm_mode_object *drmmode_obj;
7802         struct intel_crtc *crtc;
7803
7804         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7805                 return -ENODEV;
7806
7807         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7808                         DRM_MODE_OBJECT_CRTC);
7809
7810         if (!drmmode_obj) {
7811                 DRM_ERROR("no such CRTC id\n");
7812                 return -EINVAL;
7813         }
7814
7815         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7816         pipe_from_crtc_id->pipe = crtc->pipe;
7817
7818         return 0;
7819 }
7820
7821 static int intel_encoder_clones(struct intel_encoder *encoder)
7822 {
7823         struct drm_device *dev = encoder->base.dev;
7824         struct intel_encoder *source_encoder;
7825         int index_mask = 0;
7826         int entry = 0;
7827
7828         list_for_each_entry(source_encoder,
7829                             &dev->mode_config.encoder_list, base.head) {
7830
7831                 if (encoder == source_encoder)
7832                         index_mask |= (1 << entry);
7833
7834                 /* Intel hw has only one MUX where enocoders could be cloned. */
7835                 if (encoder->cloneable && source_encoder->cloneable)
7836                         index_mask |= (1 << entry);
7837
7838                 entry++;
7839         }
7840
7841         return index_mask;
7842 }
7843
7844 static bool has_edp_a(struct drm_device *dev)
7845 {
7846         struct drm_i915_private *dev_priv = dev->dev_private;
7847
7848         if (!IS_MOBILE(dev))
7849                 return false;
7850
7851         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7852                 return false;
7853
7854         if (IS_GEN5(dev) &&
7855             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7856                 return false;
7857
7858         return true;
7859 }
7860
7861 static void intel_setup_outputs(struct drm_device *dev)
7862 {
7863         struct drm_i915_private *dev_priv = dev->dev_private;
7864         struct intel_encoder *encoder;
7865         bool dpd_is_edp = false;
7866         bool has_lvds;
7867
7868         has_lvds = intel_lvds_init(dev);
7869         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7870                 /* disable the panel fitter on everything but LVDS */
7871                 I915_WRITE(PFIT_CONTROL, 0);
7872         }
7873
7874         if (HAS_PCH_SPLIT(dev)) {
7875                 dpd_is_edp = intel_dpd_is_edp(dev);
7876
7877                 if (has_edp_a(dev))
7878                         intel_dp_init(dev, DP_A, PORT_A);
7879
7880                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7881                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7882         }
7883
7884         intel_crt_init(dev);
7885
7886         if (IS_HASWELL(dev)) {
7887                 int found;
7888
7889                 /* Haswell uses DDI functions to detect digital outputs */
7890                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7891                 /* DDI A only supports eDP */
7892                 if (found)
7893                         intel_ddi_init(dev, PORT_A);
7894
7895                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7896                  * register */
7897                 found = I915_READ(SFUSE_STRAP);
7898
7899                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7900                         intel_ddi_init(dev, PORT_B);
7901                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7902                         intel_ddi_init(dev, PORT_C);
7903                 if (found & SFUSE_STRAP_DDID_DETECTED)
7904                         intel_ddi_init(dev, PORT_D);
7905         } else if (HAS_PCH_SPLIT(dev)) {
7906                 int found;
7907
7908                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7909                         /* PCH SDVOB multiplex with HDMIB */
7910                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7911                         if (!found)
7912                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7913                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7914                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7915                 }
7916
7917                 if (I915_READ(HDMIC) & PORT_DETECTED)
7918                         intel_hdmi_init(dev, HDMIC, PORT_C);
7919
7920                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7921                         intel_hdmi_init(dev, HDMID, PORT_D);
7922
7923                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7924                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7925
7926                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7927                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7928         } else if (IS_VALLEYVIEW(dev)) {
7929                 int found;
7930
7931                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7932                 if (I915_READ(DP_C) & DP_DETECTED)
7933                         intel_dp_init(dev, DP_C, PORT_C);
7934
7935                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7936                         /* SDVOB multiplex with HDMIB */
7937                         found = intel_sdvo_init(dev, SDVOB, true);
7938                         if (!found)
7939                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7940                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7941                                 intel_dp_init(dev, DP_B, PORT_B);
7942                 }
7943
7944                 if (I915_READ(SDVOC) & PORT_DETECTED)
7945                         intel_hdmi_init(dev, SDVOC, PORT_C);
7946
7947         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7948                 bool found = false;
7949
7950                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7951                         DRM_DEBUG_KMS("probing SDVOB\n");
7952                         found = intel_sdvo_init(dev, SDVOB, true);
7953                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7954                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7955                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7956                         }
7957
7958                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7959                                 DRM_DEBUG_KMS("probing DP_B\n");
7960                                 intel_dp_init(dev, DP_B, PORT_B);
7961                         }
7962                 }
7963
7964                 /* Before G4X SDVOC doesn't have its own detect register */
7965
7966                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7967                         DRM_DEBUG_KMS("probing SDVOC\n");
7968                         found = intel_sdvo_init(dev, SDVOC, false);
7969                 }
7970
7971                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7972
7973                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7974                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7975                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7976                         }
7977                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7978                                 DRM_DEBUG_KMS("probing DP_C\n");
7979                                 intel_dp_init(dev, DP_C, PORT_C);
7980                         }
7981                 }
7982
7983                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7984                     (I915_READ(DP_D) & DP_DETECTED)) {
7985                         DRM_DEBUG_KMS("probing DP_D\n");
7986                         intel_dp_init(dev, DP_D, PORT_D);
7987                 }
7988         } else if (IS_GEN2(dev))
7989                 intel_dvo_init(dev);
7990
7991         if (SUPPORTS_TV(dev))
7992                 intel_tv_init(dev);
7993
7994         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7995                 encoder->base.possible_crtcs = encoder->crtc_mask;
7996                 encoder->base.possible_clones =
7997                         intel_encoder_clones(encoder);
7998         }
7999
8000         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8001                 ironlake_init_pch_refclk(dev);
8002 }
8003
8004 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8005 {
8006         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8007
8008         drm_framebuffer_cleanup(fb);
8009         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8010
8011         kfree(intel_fb);
8012 }
8013
8014 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8015                                                 struct drm_file *file,
8016                                                 unsigned int *handle)
8017 {
8018         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8019         struct drm_i915_gem_object *obj = intel_fb->obj;
8020
8021         return drm_gem_handle_create(file, &obj->base, handle);
8022 }
8023
8024 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8025         .destroy = intel_user_framebuffer_destroy,
8026         .create_handle = intel_user_framebuffer_create_handle,
8027 };
8028
8029 int intel_framebuffer_init(struct drm_device *dev,
8030                            struct intel_framebuffer *intel_fb,
8031                            struct drm_mode_fb_cmd2 *mode_cmd,
8032                            struct drm_i915_gem_object *obj)
8033 {
8034         int ret;
8035
8036         if (obj->tiling_mode == I915_TILING_Y)
8037                 return -EINVAL;
8038
8039         if (mode_cmd->pitches[0] & 63)
8040                 return -EINVAL;
8041
8042         switch (mode_cmd->pixel_format) {
8043         case DRM_FORMAT_RGB332:
8044         case DRM_FORMAT_RGB565:
8045         case DRM_FORMAT_XRGB8888:
8046         case DRM_FORMAT_XBGR8888:
8047         case DRM_FORMAT_ARGB8888:
8048         case DRM_FORMAT_XRGB2101010:
8049         case DRM_FORMAT_ARGB2101010:
8050                 /* RGB formats are common across chipsets */
8051                 break;
8052         case DRM_FORMAT_YUYV:
8053         case DRM_FORMAT_UYVY:
8054         case DRM_FORMAT_YVYU:
8055         case DRM_FORMAT_VYUY:
8056                 break;
8057         default:
8058                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8059                                 mode_cmd->pixel_format);
8060                 return -EINVAL;
8061         }
8062
8063         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8064         if (ret) {
8065                 DRM_ERROR("framebuffer init failed %d\n", ret);
8066                 return ret;
8067         }
8068
8069         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8070         intel_fb->obj = obj;
8071         return 0;
8072 }
8073
8074 static struct drm_framebuffer *
8075 intel_user_framebuffer_create(struct drm_device *dev,
8076                               struct drm_file *filp,
8077                               struct drm_mode_fb_cmd2 *mode_cmd)
8078 {
8079         struct drm_i915_gem_object *obj;
8080
8081         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8082                                                 mode_cmd->handles[0]));
8083         if (&obj->base == NULL)
8084                 return ERR_PTR(-ENOENT);
8085
8086         return intel_framebuffer_create(dev, mode_cmd, obj);
8087 }
8088
8089 static const struct drm_mode_config_funcs intel_mode_funcs = {
8090         .fb_create = intel_user_framebuffer_create,
8091         .output_poll_changed = intel_fb_output_poll_changed,
8092 };
8093
8094 /* Set up chip specific display functions */
8095 static void intel_init_display(struct drm_device *dev)
8096 {
8097         struct drm_i915_private *dev_priv = dev->dev_private;
8098
8099         /* We always want a DPMS function */
8100         if (IS_HASWELL(dev)) {
8101                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8102                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8103                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8104                 dev_priv->display.off = haswell_crtc_off;
8105                 dev_priv->display.update_plane = ironlake_update_plane;
8106         } else if (HAS_PCH_SPLIT(dev)) {
8107                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8108                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8109                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8110                 dev_priv->display.off = ironlake_crtc_off;
8111                 dev_priv->display.update_plane = ironlake_update_plane;
8112         } else {
8113                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8114                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8115                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8116                 dev_priv->display.off = i9xx_crtc_off;
8117                 dev_priv->display.update_plane = i9xx_update_plane;
8118         }
8119
8120         /* Returns the core display clock speed */
8121         if (IS_VALLEYVIEW(dev))
8122                 dev_priv->display.get_display_clock_speed =
8123                         valleyview_get_display_clock_speed;
8124         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8125                 dev_priv->display.get_display_clock_speed =
8126                         i945_get_display_clock_speed;
8127         else if (IS_I915G(dev))
8128                 dev_priv->display.get_display_clock_speed =
8129                         i915_get_display_clock_speed;
8130         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8131                 dev_priv->display.get_display_clock_speed =
8132                         i9xx_misc_get_display_clock_speed;
8133         else if (IS_I915GM(dev))
8134                 dev_priv->display.get_display_clock_speed =
8135                         i915gm_get_display_clock_speed;
8136         else if (IS_I865G(dev))
8137                 dev_priv->display.get_display_clock_speed =
8138                         i865_get_display_clock_speed;
8139         else if (IS_I85X(dev))
8140                 dev_priv->display.get_display_clock_speed =
8141                         i855_get_display_clock_speed;
8142         else /* 852, 830 */
8143                 dev_priv->display.get_display_clock_speed =
8144                         i830_get_display_clock_speed;
8145
8146         if (HAS_PCH_SPLIT(dev)) {
8147                 if (IS_GEN5(dev)) {
8148                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8149                         dev_priv->display.write_eld = ironlake_write_eld;
8150                 } else if (IS_GEN6(dev)) {
8151                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8152                         dev_priv->display.write_eld = ironlake_write_eld;
8153                 } else if (IS_IVYBRIDGE(dev)) {
8154                         /* FIXME: detect B0+ stepping and use auto training */
8155                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8156                         dev_priv->display.write_eld = ironlake_write_eld;
8157                 } else if (IS_HASWELL(dev)) {
8158                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8159                         dev_priv->display.write_eld = haswell_write_eld;
8160                 } else
8161                         dev_priv->display.update_wm = NULL;
8162         } else if (IS_G4X(dev)) {
8163                 dev_priv->display.write_eld = g4x_write_eld;
8164         }
8165
8166         /* Default just returns -ENODEV to indicate unsupported */
8167         dev_priv->display.queue_flip = intel_default_queue_flip;
8168
8169         switch (INTEL_INFO(dev)->gen) {
8170         case 2:
8171                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8172                 break;
8173
8174         case 3:
8175                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8176                 break;
8177
8178         case 4:
8179         case 5:
8180                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8181                 break;
8182
8183         case 6:
8184                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8185                 break;
8186         case 7:
8187                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8188                 break;
8189         }
8190 }
8191
8192 /*
8193  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8194  * resume, or other times.  This quirk makes sure that's the case for
8195  * affected systems.
8196  */
8197 static void quirk_pipea_force(struct drm_device *dev)
8198 {
8199         struct drm_i915_private *dev_priv = dev->dev_private;
8200
8201         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8202         DRM_INFO("applying pipe a force quirk\n");
8203 }
8204
8205 /*
8206  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8207  */
8208 static void quirk_ssc_force_disable(struct drm_device *dev)
8209 {
8210         struct drm_i915_private *dev_priv = dev->dev_private;
8211         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8212         DRM_INFO("applying lvds SSC disable quirk\n");
8213 }
8214
8215 /*
8216  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8217  * brightness value
8218  */
8219 static void quirk_invert_brightness(struct drm_device *dev)
8220 {
8221         struct drm_i915_private *dev_priv = dev->dev_private;
8222         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8223         DRM_INFO("applying inverted panel brightness quirk\n");
8224 }
8225
8226 struct intel_quirk {
8227         int device;
8228         int subsystem_vendor;
8229         int subsystem_device;
8230         void (*hook)(struct drm_device *dev);
8231 };
8232
8233 static struct intel_quirk intel_quirks[] = {
8234         /* HP Mini needs pipe A force quirk (LP: #322104) */
8235         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8236
8237         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8238         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8239
8240         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8241         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8242
8243         /* 830/845 need to leave pipe A & dpll A up */
8244         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8245         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8246
8247         /* Lenovo U160 cannot use SSC on LVDS */
8248         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8249
8250         /* Sony Vaio Y cannot use SSC on LVDS */
8251         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8252
8253         /* Acer Aspire 5734Z must invert backlight brightness */
8254         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8255 };
8256
8257 static void intel_init_quirks(struct drm_device *dev)
8258 {
8259         struct pci_dev *d = dev->pdev;
8260         int i;
8261
8262         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8263                 struct intel_quirk *q = &intel_quirks[i];
8264
8265                 if (d->device == q->device &&
8266                     (d->subsystem_vendor == q->subsystem_vendor ||
8267                      q->subsystem_vendor == PCI_ANY_ID) &&
8268                     (d->subsystem_device == q->subsystem_device ||
8269                      q->subsystem_device == PCI_ANY_ID))
8270                         q->hook(dev);
8271         }
8272 }
8273
8274 /* Disable the VGA plane that we never use */
8275 static void i915_disable_vga(struct drm_device *dev)
8276 {
8277         struct drm_i915_private *dev_priv = dev->dev_private;
8278         u8 sr1;
8279         u32 vga_reg;
8280
8281         if (HAS_PCH_SPLIT(dev))
8282                 vga_reg = CPU_VGACNTRL;
8283         else
8284                 vga_reg = VGACNTRL;
8285
8286         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8287         outb(SR01, VGA_SR_INDEX);
8288         sr1 = inb(VGA_SR_DATA);
8289         outb(sr1 | 1<<5, VGA_SR_DATA);
8290         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8291         udelay(300);
8292
8293         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8294         POSTING_READ(vga_reg);
8295 }
8296
8297 void intel_modeset_init_hw(struct drm_device *dev)
8298 {
8299         /* We attempt to init the necessary power wells early in the initialization
8300          * time, so the subsystems that expect power to be enabled can work.
8301          */
8302         intel_init_power_wells(dev);
8303
8304         intel_prepare_ddi(dev);
8305
8306         intel_init_clock_gating(dev);
8307
8308         mutex_lock(&dev->struct_mutex);
8309         intel_enable_gt_powersave(dev);
8310         mutex_unlock(&dev->struct_mutex);
8311 }
8312
8313 void intel_modeset_init(struct drm_device *dev)
8314 {
8315         struct drm_i915_private *dev_priv = dev->dev_private;
8316         int i, ret;
8317
8318         drm_mode_config_init(dev);
8319
8320         dev->mode_config.min_width = 0;
8321         dev->mode_config.min_height = 0;
8322
8323         dev->mode_config.preferred_depth = 24;
8324         dev->mode_config.prefer_shadow = 1;
8325
8326         dev->mode_config.funcs = &intel_mode_funcs;
8327
8328         intel_init_quirks(dev);
8329
8330         intel_init_pm(dev);
8331
8332         intel_init_display(dev);
8333
8334         if (IS_GEN2(dev)) {
8335                 dev->mode_config.max_width = 2048;
8336                 dev->mode_config.max_height = 2048;
8337         } else if (IS_GEN3(dev)) {
8338                 dev->mode_config.max_width = 4096;
8339                 dev->mode_config.max_height = 4096;
8340         } else {
8341                 dev->mode_config.max_width = 8192;
8342                 dev->mode_config.max_height = 8192;
8343         }
8344         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8345
8346         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8347                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8348
8349         for (i = 0; i < dev_priv->num_pipe; i++) {
8350                 intel_crtc_init(dev, i);
8351                 ret = intel_plane_init(dev, i);
8352                 if (ret)
8353                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8354         }
8355
8356         intel_cpu_pll_init(dev);
8357         intel_pch_pll_init(dev);
8358
8359         /* Just disable it once at startup */
8360         i915_disable_vga(dev);
8361         intel_setup_outputs(dev);
8362 }
8363
8364 static void
8365 intel_connector_break_all_links(struct intel_connector *connector)
8366 {
8367         connector->base.dpms = DRM_MODE_DPMS_OFF;
8368         connector->base.encoder = NULL;
8369         connector->encoder->connectors_active = false;
8370         connector->encoder->base.crtc = NULL;
8371 }
8372
8373 static void intel_enable_pipe_a(struct drm_device *dev)
8374 {
8375         struct intel_connector *connector;
8376         struct drm_connector *crt = NULL;
8377         struct intel_load_detect_pipe load_detect_temp;
8378
8379         /* We can't just switch on the pipe A, we need to set things up with a
8380          * proper mode and output configuration. As a gross hack, enable pipe A
8381          * by enabling the load detect pipe once. */
8382         list_for_each_entry(connector,
8383                             &dev->mode_config.connector_list,
8384                             base.head) {
8385                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8386                         crt = &connector->base;
8387                         break;
8388                 }
8389         }
8390
8391         if (!crt)
8392                 return;
8393
8394         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8395                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8396
8397
8398 }
8399
8400 static bool
8401 intel_check_plane_mapping(struct intel_crtc *crtc)
8402 {
8403         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8404         u32 reg, val;
8405
8406         if (dev_priv->num_pipe == 1)
8407                 return true;
8408
8409         reg = DSPCNTR(!crtc->plane);
8410         val = I915_READ(reg);
8411
8412         if ((val & DISPLAY_PLANE_ENABLE) &&
8413             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8414                 return false;
8415
8416         return true;
8417 }
8418
8419 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8420 {
8421         struct drm_device *dev = crtc->base.dev;
8422         struct drm_i915_private *dev_priv = dev->dev_private;
8423         u32 reg;
8424
8425         /* Clear any frame start delays used for debugging left by the BIOS */
8426         reg = PIPECONF(crtc->pipe);
8427         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8428
8429         /* We need to sanitize the plane -> pipe mapping first because this will
8430          * disable the crtc (and hence change the state) if it is wrong. Note
8431          * that gen4+ has a fixed plane -> pipe mapping.  */
8432         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8433                 struct intel_connector *connector;
8434                 bool plane;
8435
8436                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8437                               crtc->base.base.id);
8438
8439                 /* Pipe has the wrong plane attached and the plane is active.
8440                  * Temporarily change the plane mapping and disable everything
8441                  * ...  */
8442                 plane = crtc->plane;
8443                 crtc->plane = !plane;
8444                 dev_priv->display.crtc_disable(&crtc->base);
8445                 crtc->plane = plane;
8446
8447                 /* ... and break all links. */
8448                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8449                                     base.head) {
8450                         if (connector->encoder->base.crtc != &crtc->base)
8451                                 continue;
8452
8453                         intel_connector_break_all_links(connector);
8454                 }
8455
8456                 WARN_ON(crtc->active);
8457                 crtc->base.enabled = false;
8458         }
8459
8460         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8461             crtc->pipe == PIPE_A && !crtc->active) {
8462                 /* BIOS forgot to enable pipe A, this mostly happens after
8463                  * resume. Force-enable the pipe to fix this, the update_dpms
8464                  * call below we restore the pipe to the right state, but leave
8465                  * the required bits on. */
8466                 intel_enable_pipe_a(dev);
8467         }
8468
8469         /* Adjust the state of the output pipe according to whether we
8470          * have active connectors/encoders. */
8471         intel_crtc_update_dpms(&crtc->base);
8472
8473         if (crtc->active != crtc->base.enabled) {
8474                 struct intel_encoder *encoder;
8475
8476                 /* This can happen either due to bugs in the get_hw_state
8477                  * functions or because the pipe is force-enabled due to the
8478                  * pipe A quirk. */
8479                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8480                               crtc->base.base.id,
8481                               crtc->base.enabled ? "enabled" : "disabled",
8482                               crtc->active ? "enabled" : "disabled");
8483
8484                 crtc->base.enabled = crtc->active;
8485
8486                 /* Because we only establish the connector -> encoder ->
8487                  * crtc links if something is active, this means the
8488                  * crtc is now deactivated. Break the links. connector
8489                  * -> encoder links are only establish when things are
8490                  *  actually up, hence no need to break them. */
8491                 WARN_ON(crtc->active);
8492
8493                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8494                         WARN_ON(encoder->connectors_active);
8495                         encoder->base.crtc = NULL;
8496                 }
8497         }
8498 }
8499
8500 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8501 {
8502         struct intel_connector *connector;
8503         struct drm_device *dev = encoder->base.dev;
8504
8505         /* We need to check both for a crtc link (meaning that the
8506          * encoder is active and trying to read from a pipe) and the
8507          * pipe itself being active. */
8508         bool has_active_crtc = encoder->base.crtc &&
8509                 to_intel_crtc(encoder->base.crtc)->active;
8510
8511         if (encoder->connectors_active && !has_active_crtc) {
8512                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8513                               encoder->base.base.id,
8514                               drm_get_encoder_name(&encoder->base));
8515
8516                 /* Connector is active, but has no active pipe. This is
8517                  * fallout from our resume register restoring. Disable
8518                  * the encoder manually again. */
8519                 if (encoder->base.crtc) {
8520                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8521                                       encoder->base.base.id,
8522                                       drm_get_encoder_name(&encoder->base));
8523                         encoder->disable(encoder);
8524                 }
8525
8526                 /* Inconsistent output/port/pipe state happens presumably due to
8527                  * a bug in one of the get_hw_state functions. Or someplace else
8528                  * in our code, like the register restore mess on resume. Clamp
8529                  * things to off as a safer default. */
8530                 list_for_each_entry(connector,
8531                                     &dev->mode_config.connector_list,
8532                                     base.head) {
8533                         if (connector->encoder != encoder)
8534                                 continue;
8535
8536                         intel_connector_break_all_links(connector);
8537                 }
8538         }
8539         /* Enabled encoders without active connectors will be fixed in
8540          * the crtc fixup. */
8541 }
8542
8543 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8544  * and i915 state tracking structures. */
8545 void intel_modeset_setup_hw_state(struct drm_device *dev)
8546 {
8547         struct drm_i915_private *dev_priv = dev->dev_private;
8548         enum pipe pipe;
8549         u32 tmp;
8550         struct intel_crtc *crtc;
8551         struct intel_encoder *encoder;
8552         struct intel_connector *connector;
8553
8554         for_each_pipe(pipe) {
8555                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8556
8557                 tmp = I915_READ(PIPECONF(pipe));
8558                 if (tmp & PIPECONF_ENABLE)
8559                         crtc->active = true;
8560                 else
8561                         crtc->active = false;
8562
8563                 crtc->base.enabled = crtc->active;
8564
8565                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8566                               crtc->base.base.id,
8567                               crtc->active ? "enabled" : "disabled");
8568         }
8569
8570         if (IS_HASWELL(dev))
8571                 intel_ddi_setup_hw_pll_state(dev);
8572
8573         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8574                             base.head) {
8575                 pipe = 0;
8576
8577                 if (encoder->get_hw_state(encoder, &pipe)) {
8578                         encoder->base.crtc =
8579                                 dev_priv->pipe_to_crtc_mapping[pipe];
8580                 } else {
8581                         encoder->base.crtc = NULL;
8582                 }
8583
8584                 encoder->connectors_active = false;
8585                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8586                               encoder->base.base.id,
8587                               drm_get_encoder_name(&encoder->base),
8588                               encoder->base.crtc ? "enabled" : "disabled",
8589                               pipe);
8590         }
8591
8592         list_for_each_entry(connector, &dev->mode_config.connector_list,
8593                             base.head) {
8594                 if (connector->get_hw_state(connector)) {
8595                         connector->base.dpms = DRM_MODE_DPMS_ON;
8596                         connector->encoder->connectors_active = true;
8597                         connector->base.encoder = &connector->encoder->base;
8598                 } else {
8599                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8600                         connector->base.encoder = NULL;
8601                 }
8602                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8603                               connector->base.base.id,
8604                               drm_get_connector_name(&connector->base),
8605                               connector->base.encoder ? "enabled" : "disabled");
8606         }
8607
8608         /* HW state is read out, now we need to sanitize this mess. */
8609         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8610                             base.head) {
8611                 intel_sanitize_encoder(encoder);
8612         }
8613
8614         for_each_pipe(pipe) {
8615                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8616                 intel_sanitize_crtc(crtc);
8617         }
8618
8619         intel_modeset_update_staged_output_state(dev);
8620
8621         intel_modeset_check_state(dev);
8622
8623         drm_mode_config_reset(dev);
8624 }
8625
8626 void intel_modeset_gem_init(struct drm_device *dev)
8627 {
8628         intel_modeset_init_hw(dev);
8629
8630         intel_setup_overlay(dev);
8631
8632         intel_modeset_setup_hw_state(dev);
8633 }
8634
8635 void intel_modeset_cleanup(struct drm_device *dev)
8636 {
8637         struct drm_i915_private *dev_priv = dev->dev_private;
8638         struct drm_crtc *crtc;
8639         struct intel_crtc *intel_crtc;
8640
8641         drm_kms_helper_poll_fini(dev);
8642         mutex_lock(&dev->struct_mutex);
8643
8644         intel_unregister_dsm_handler();
8645
8646
8647         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8648                 /* Skip inactive CRTCs */
8649                 if (!crtc->fb)
8650                         continue;
8651
8652                 intel_crtc = to_intel_crtc(crtc);
8653                 intel_increase_pllclock(crtc);
8654         }
8655
8656         intel_disable_fbc(dev);
8657
8658         intel_disable_gt_powersave(dev);
8659
8660         ironlake_teardown_rc6(dev);
8661
8662         if (IS_VALLEYVIEW(dev))
8663                 vlv_init_dpio(dev);
8664
8665         mutex_unlock(&dev->struct_mutex);
8666
8667         /* Disable the irq before mode object teardown, for the irq might
8668          * enqueue unpin/hotplug work. */
8669         drm_irq_uninstall(dev);
8670         cancel_work_sync(&dev_priv->hotplug_work);
8671         cancel_work_sync(&dev_priv->rps.work);
8672
8673         /* flush any delayed tasks or pending work */
8674         flush_scheduled_work();
8675
8676         drm_mode_config_cleanup(dev);
8677 }
8678
8679 /*
8680  * Return which encoder is currently attached for connector.
8681  */
8682 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8683 {
8684         return &intel_attached_encoder(connector)->base;
8685 }
8686
8687 void intel_connector_attach_encoder(struct intel_connector *connector,
8688                                     struct intel_encoder *encoder)
8689 {
8690         connector->encoder = encoder;
8691         drm_mode_connector_attach_encoder(&connector->base,
8692                                           &encoder->base);
8693 }
8694
8695 /*
8696  * set vga decode state - true == enable VGA decode
8697  */
8698 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701         u16 gmch_ctrl;
8702
8703         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8704         if (state)
8705                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8706         else
8707                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8708         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8709         return 0;
8710 }
8711
8712 #ifdef CONFIG_DEBUG_FS
8713 #include <linux/seq_file.h>
8714
8715 struct intel_display_error_state {
8716         struct intel_cursor_error_state {
8717                 u32 control;
8718                 u32 position;
8719                 u32 base;
8720                 u32 size;
8721         } cursor[I915_MAX_PIPES];
8722
8723         struct intel_pipe_error_state {
8724                 u32 conf;
8725                 u32 source;
8726
8727                 u32 htotal;
8728                 u32 hblank;
8729                 u32 hsync;
8730                 u32 vtotal;
8731                 u32 vblank;
8732                 u32 vsync;
8733         } pipe[I915_MAX_PIPES];
8734
8735         struct intel_plane_error_state {
8736                 u32 control;
8737                 u32 stride;
8738                 u32 size;
8739                 u32 pos;
8740                 u32 addr;
8741                 u32 surface;
8742                 u32 tile_offset;
8743         } plane[I915_MAX_PIPES];
8744 };
8745
8746 struct intel_display_error_state *
8747 intel_display_capture_error_state(struct drm_device *dev)
8748 {
8749         drm_i915_private_t *dev_priv = dev->dev_private;
8750         struct intel_display_error_state *error;
8751         int i;
8752
8753         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8754         if (error == NULL)
8755                 return NULL;
8756
8757         for_each_pipe(i) {
8758                 error->cursor[i].control = I915_READ(CURCNTR(i));
8759                 error->cursor[i].position = I915_READ(CURPOS(i));
8760                 error->cursor[i].base = I915_READ(CURBASE(i));
8761
8762                 error->plane[i].control = I915_READ(DSPCNTR(i));
8763                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8764                 error->plane[i].size = I915_READ(DSPSIZE(i));
8765                 error->plane[i].pos = I915_READ(DSPPOS(i));
8766                 error->plane[i].addr = I915_READ(DSPADDR(i));
8767                 if (INTEL_INFO(dev)->gen >= 4) {
8768                         error->plane[i].surface = I915_READ(DSPSURF(i));
8769                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8770                 }
8771
8772                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8773                 error->pipe[i].source = I915_READ(PIPESRC(i));
8774                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8775                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8776                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8777                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8778                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8779                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8780         }
8781
8782         return error;
8783 }
8784
8785 void
8786 intel_display_print_error_state(struct seq_file *m,
8787                                 struct drm_device *dev,
8788                                 struct intel_display_error_state *error)
8789 {
8790         drm_i915_private_t *dev_priv = dev->dev_private;
8791         int i;
8792
8793         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8794         for_each_pipe(i) {
8795                 seq_printf(m, "Pipe [%d]:\n", i);
8796                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8797                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8798                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8799                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8800                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8801                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8802                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8803                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8804
8805                 seq_printf(m, "Plane [%d]:\n", i);
8806                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8807                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8808                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8809                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8810                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8811                 if (INTEL_INFO(dev)->gen >= 4) {
8812                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8813                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8814                 }
8815
8816                 seq_printf(m, "Cursor [%d]:\n", i);
8817                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8818                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8819                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8820         }
8821 }
8822 #endif