Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum transcoder cpu_transcoder)
1722 {
1723         u32 val, pipeconf_val;
1724
1725         /* PCH only available on ILK+ */
1726         BUG_ON(dev_priv->info->gen < 5);
1727
1728         /* FDI must be feeding us bits for PCH ports */
1729         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1731
1732         /* Workaround: set timing override bit. */
1733         val = I915_READ(_TRANSA_CHICKEN2);
1734         val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
1735         I915_WRITE(_TRANSA_CHICKEN2, val);
1736
1737         val = TRANS_ENABLE;
1738         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1739
1740         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1741             PIPECONF_INTERLACED_ILK)
1742                 val |= TRANS_INTERLACED;
1743         else
1744                 val |= TRANS_PROGRESSIVE;
1745
1746         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1747         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1748                 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 }
1750
1751 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752                                             enum pipe pipe)
1753 {
1754         int reg;
1755         u32 val;
1756
1757         /* FDI relies on the transcoder */
1758         assert_fdi_tx_disabled(dev_priv, pipe);
1759         assert_fdi_rx_disabled(dev_priv, pipe);
1760
1761         /* Ports must be off as well */
1762         assert_pch_ports_disabled(dev_priv, pipe);
1763
1764         reg = TRANSCONF(pipe);
1765         val = I915_READ(reg);
1766         val &= ~TRANS_ENABLE;
1767         I915_WRITE(reg, val);
1768         /* wait for PCH transcoder off, transcoder state */
1769         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1770                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1771 }
1772
1773 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1774 {
1775         u32 val;
1776
1777         val = I915_READ(_TRANSACONF);
1778         val &= ~TRANS_ENABLE;
1779         I915_WRITE(_TRANSACONF, val);
1780         /* wait for PCH transcoder off, transcoder state */
1781         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1782                 DRM_ERROR("Failed to disable PCH transcoder\n");
1783
1784         /* Workaround: clear timing override bit. */
1785         val = I915_READ(_TRANSA_CHICKEN2);
1786         val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
1787         I915_WRITE(_TRANSA_CHICKEN2, val);
1788 }
1789
1790 /**
1791  * intel_enable_pipe - enable a pipe, asserting requirements
1792  * @dev_priv: i915 private structure
1793  * @pipe: pipe to enable
1794  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1795  *
1796  * Enable @pipe, making sure that various hardware specific requirements
1797  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1798  *
1799  * @pipe should be %PIPE_A or %PIPE_B.
1800  *
1801  * Will wait until the pipe is actually running (i.e. first vblank) before
1802  * returning.
1803  */
1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1805                               bool pch_port)
1806 {
1807         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1808                                                                       pipe);
1809         int reg;
1810         u32 val;
1811
1812         /*
1813          * A pipe without a PLL won't actually be able to drive bits from
1814          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1815          * need the check.
1816          */
1817         if (!HAS_PCH_SPLIT(dev_priv->dev))
1818                 assert_pll_enabled(dev_priv, pipe);
1819         else {
1820                 if (pch_port) {
1821                         /* if driving the PCH, we need FDI enabled */
1822                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1823                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005                                                unsigned int bpp,
2006                                                unsigned int pitch)
2007 {
2008         int tile_rows, tiles;
2009
2010         tile_rows = *y / 8;
2011         *y %= 8;
2012         tiles = *x / (512/bpp);
2013         *x %= 512/bpp;
2014
2015         return tile_rows * pitch * 8 + tiles * 4096;
2016 }
2017
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019                              int x, int y)
2020 {
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024         struct intel_framebuffer *intel_fb;
2025         struct drm_i915_gem_object *obj;
2026         int plane = intel_crtc->plane;
2027         unsigned long linear_offset;
2028         u32 dspcntr;
2029         u32 reg;
2030
2031         switch (plane) {
2032         case 0:
2033         case 1:
2034                 break;
2035         default:
2036                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037                 return -EINVAL;
2038         }
2039
2040         intel_fb = to_intel_framebuffer(fb);
2041         obj = intel_fb->obj;
2042
2043         reg = DSPCNTR(plane);
2044         dspcntr = I915_READ(reg);
2045         /* Mask out pixel format bits in case we change it */
2046         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047         switch (fb->pixel_format) {
2048         case DRM_FORMAT_C8:
2049                 dspcntr |= DISPPLANE_8BPP;
2050                 break;
2051         case DRM_FORMAT_XRGB1555:
2052         case DRM_FORMAT_ARGB1555:
2053                 dspcntr |= DISPPLANE_BGRX555;
2054                 break;
2055         case DRM_FORMAT_RGB565:
2056                 dspcntr |= DISPPLANE_BGRX565;
2057                 break;
2058         case DRM_FORMAT_XRGB8888:
2059         case DRM_FORMAT_ARGB8888:
2060                 dspcntr |= DISPPLANE_BGRX888;
2061                 break;
2062         case DRM_FORMAT_XBGR8888:
2063         case DRM_FORMAT_ABGR8888:
2064                 dspcntr |= DISPPLANE_RGBX888;
2065                 break;
2066         case DRM_FORMAT_XRGB2101010:
2067         case DRM_FORMAT_ARGB2101010:
2068                 dspcntr |= DISPPLANE_BGRX101010;
2069                 break;
2070         case DRM_FORMAT_XBGR2101010:
2071         case DRM_FORMAT_ABGR2101010:
2072                 dspcntr |= DISPPLANE_RGBX101010;
2073                 break;
2074         default:
2075                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2076                 return -EINVAL;
2077         }
2078
2079         if (INTEL_INFO(dev)->gen >= 4) {
2080                 if (obj->tiling_mode != I915_TILING_NONE)
2081                         dspcntr |= DISPPLANE_TILED;
2082                 else
2083                         dspcntr &= ~DISPPLANE_TILED;
2084         }
2085
2086         I915_WRITE(reg, dspcntr);
2087
2088         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 intel_crtc->dspaddr_offset =
2092                         intel_gen4_compute_offset_xtiled(&x, &y,
2093                                                          fb->bits_per_pixel / 8,
2094                                                          fb->pitches[0]);
2095                 linear_offset -= intel_crtc->dspaddr_offset;
2096         } else {
2097                 intel_crtc->dspaddr_offset = linear_offset;
2098         }
2099
2100         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103         if (INTEL_INFO(dev)->gen >= 4) {
2104                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2106                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108         } else
2109                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2110         POSTING_READ(reg);
2111
2112         return 0;
2113 }
2114
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116                                  struct drm_framebuffer *fb, int x, int y)
2117 {
2118         struct drm_device *dev = crtc->dev;
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121         struct intel_framebuffer *intel_fb;
2122         struct drm_i915_gem_object *obj;
2123         int plane = intel_crtc->plane;
2124         unsigned long linear_offset;
2125         u32 dspcntr;
2126         u32 reg;
2127
2128         switch (plane) {
2129         case 0:
2130         case 1:
2131         case 2:
2132                 break;
2133         default:
2134                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135                 return -EINVAL;
2136         }
2137
2138         intel_fb = to_intel_framebuffer(fb);
2139         obj = intel_fb->obj;
2140
2141         reg = DSPCNTR(plane);
2142         dspcntr = I915_READ(reg);
2143         /* Mask out pixel format bits in case we change it */
2144         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145         switch (fb->pixel_format) {
2146         case DRM_FORMAT_C8:
2147                 dspcntr |= DISPPLANE_8BPP;
2148                 break;
2149         case DRM_FORMAT_RGB565:
2150                 dspcntr |= DISPPLANE_BGRX565;
2151                 break;
2152         case DRM_FORMAT_XRGB8888:
2153         case DRM_FORMAT_ARGB8888:
2154                 dspcntr |= DISPPLANE_BGRX888;
2155                 break;
2156         case DRM_FORMAT_XBGR8888:
2157         case DRM_FORMAT_ABGR8888:
2158                 dspcntr |= DISPPLANE_RGBX888;
2159                 break;
2160         case DRM_FORMAT_XRGB2101010:
2161         case DRM_FORMAT_ARGB2101010:
2162                 dspcntr |= DISPPLANE_BGRX101010;
2163                 break;
2164         case DRM_FORMAT_XBGR2101010:
2165         case DRM_FORMAT_ABGR2101010:
2166                 dspcntr |= DISPPLANE_RGBX101010;
2167                 break;
2168         default:
2169                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2170                 return -EINVAL;
2171         }
2172
2173         if (obj->tiling_mode != I915_TILING_NONE)
2174                 dspcntr |= DISPPLANE_TILED;
2175         else
2176                 dspcntr &= ~DISPPLANE_TILED;
2177
2178         /* must disable */
2179         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181         I915_WRITE(reg, dspcntr);
2182
2183         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184         intel_crtc->dspaddr_offset =
2185                 intel_gen4_compute_offset_xtiled(&x, &y,
2186                                                  fb->bits_per_pixel / 8,
2187                                                  fb->pitches[0]);
2188         linear_offset -= intel_crtc->dspaddr_offset;
2189
2190         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193         I915_MODIFY_DISPBASE(DSPSURF(plane),
2194                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2195         if (IS_HASWELL(dev)) {
2196                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197         } else {
2198                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200         }
2201         POSTING_READ(reg);
2202
2203         return 0;
2204 }
2205
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2207 static int
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209                            int x, int y, enum mode_set_atomic state)
2210 {
2211         struct drm_device *dev = crtc->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213
2214         if (dev_priv->display.disable_fbc)
2215                 dev_priv->display.disable_fbc(dev);
2216         intel_increase_pllclock(crtc);
2217
2218         return dev_priv->display.update_plane(crtc, fb, x, y);
2219 }
2220
2221 static int
2222 intel_finish_fb(struct drm_framebuffer *old_fb)
2223 {
2224         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226         bool was_interruptible = dev_priv->mm.interruptible;
2227         int ret;
2228
2229         wait_event(dev_priv->pending_flip_queue,
2230                    atomic_read(&dev_priv->mm.wedged) ||
2231                    atomic_read(&obj->pending_flip) == 0);
2232
2233         /* Big Hammer, we also need to ensure that any pending
2234          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235          * current scanout is retired before unpinning the old
2236          * framebuffer.
2237          *
2238          * This should only fail upon a hung GPU, in which case we
2239          * can safely continue.
2240          */
2241         dev_priv->mm.interruptible = false;
2242         ret = i915_gem_object_finish_gpu(obj);
2243         dev_priv->mm.interruptible = was_interruptible;
2244
2245         return ret;
2246 }
2247
2248 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_master_private *master_priv;
2252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254         if (!dev->primary->master)
2255                 return;
2256
2257         master_priv = dev->primary->master->driver_priv;
2258         if (!master_priv->sarea_priv)
2259                 return;
2260
2261         switch (intel_crtc->pipe) {
2262         case 0:
2263                 master_priv->sarea_priv->pipeA_x = x;
2264                 master_priv->sarea_priv->pipeA_y = y;
2265                 break;
2266         case 1:
2267                 master_priv->sarea_priv->pipeB_x = x;
2268                 master_priv->sarea_priv->pipeB_y = y;
2269                 break;
2270         default:
2271                 break;
2272         }
2273 }
2274
2275 static int
2276 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2277                     struct drm_framebuffer *fb)
2278 {
2279         struct drm_device *dev = crtc->dev;
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2282         struct drm_framebuffer *old_fb;
2283         int ret;
2284
2285         /* no fb bound */
2286         if (!fb) {
2287                 DRM_ERROR("No FB bound\n");
2288                 return 0;
2289         }
2290
2291         if(intel_crtc->plane > dev_priv->num_pipe) {
2292                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2293                                 intel_crtc->plane,
2294                                 dev_priv->num_pipe);
2295                 return -EINVAL;
2296         }
2297
2298         mutex_lock(&dev->struct_mutex);
2299         ret = intel_pin_and_fence_fb_obj(dev,
2300                                          to_intel_framebuffer(fb)->obj,
2301                                          NULL);
2302         if (ret != 0) {
2303                 mutex_unlock(&dev->struct_mutex);
2304                 DRM_ERROR("pin & fence failed\n");
2305                 return ret;
2306         }
2307
2308         if (crtc->fb)
2309                 intel_finish_fb(crtc->fb);
2310
2311         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2312         if (ret) {
2313                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2314                 mutex_unlock(&dev->struct_mutex);
2315                 DRM_ERROR("failed to update base address\n");
2316                 return ret;
2317         }
2318
2319         old_fb = crtc->fb;
2320         crtc->fb = fb;
2321         crtc->x = x;
2322         crtc->y = y;
2323
2324         if (old_fb) {
2325                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327         }
2328
2329         intel_update_fbc(dev);
2330         mutex_unlock(&dev->struct_mutex);
2331
2332         intel_crtc_update_sarea_pos(crtc, x, y);
2333
2334         return 0;
2335 }
2336
2337 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2338 {
2339         struct drm_device *dev = crtc->dev;
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         u32 dpa_ctl;
2342
2343         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2344         dpa_ctl = I915_READ(DP_A);
2345         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2346
2347         if (clock < 200000) {
2348                 u32 temp;
2349                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2350                 /* workaround for 160Mhz:
2351                    1) program 0x4600c bits 15:0 = 0x8124
2352                    2) program 0x46010 bit 0 = 1
2353                    3) program 0x46034 bit 24 = 1
2354                    4) program 0x64000 bit 14 = 1
2355                    */
2356                 temp = I915_READ(0x4600c);
2357                 temp &= 0xffff0000;
2358                 I915_WRITE(0x4600c, temp | 0x8124);
2359
2360                 temp = I915_READ(0x46010);
2361                 I915_WRITE(0x46010, temp | 1);
2362
2363                 temp = I915_READ(0x46034);
2364                 I915_WRITE(0x46034, temp | (1 << 24));
2365         } else {
2366                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2367         }
2368         I915_WRITE(DP_A, dpa_ctl);
2369
2370         POSTING_READ(DP_A);
2371         udelay(500);
2372 }
2373
2374 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2375 {
2376         struct drm_device *dev = crtc->dev;
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379         int pipe = intel_crtc->pipe;
2380         u32 reg, temp;
2381
2382         /* enable normal train */
2383         reg = FDI_TX_CTL(pipe);
2384         temp = I915_READ(reg);
2385         if (IS_IVYBRIDGE(dev)) {
2386                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2387                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2388         } else {
2389                 temp &= ~FDI_LINK_TRAIN_NONE;
2390                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2391         }
2392         I915_WRITE(reg, temp);
2393
2394         reg = FDI_RX_CTL(pipe);
2395         temp = I915_READ(reg);
2396         if (HAS_PCH_CPT(dev)) {
2397                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2398                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2399         } else {
2400                 temp &= ~FDI_LINK_TRAIN_NONE;
2401                 temp |= FDI_LINK_TRAIN_NONE;
2402         }
2403         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2404
2405         /* wait one idle pattern time */
2406         POSTING_READ(reg);
2407         udelay(1000);
2408
2409         /* IVB wants error correction enabled */
2410         if (IS_IVYBRIDGE(dev))
2411                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2412                            FDI_FE_ERRC_ENABLE);
2413 }
2414
2415 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2416 {
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         u32 flags = I915_READ(SOUTH_CHICKEN1);
2419
2420         flags |= FDI_PHASE_SYNC_OVR(pipe);
2421         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2422         flags |= FDI_PHASE_SYNC_EN(pipe);
2423         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2424         POSTING_READ(SOUTH_CHICKEN1);
2425 }
2426
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         struct intel_crtc *pipe_B_crtc =
2431                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432         struct intel_crtc *pipe_C_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434         uint32_t temp;
2435
2436         /* When everything is off disable fdi C so that we could enable fdi B
2437          * with all lanes. XXX: This misses the case where a pipe is not using
2438          * any pch resources and so doesn't need any fdi lanes. */
2439         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2440                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2441                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2442
2443                 temp = I915_READ(SOUTH_CHICKEN1);
2444                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2445                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2446                 I915_WRITE(SOUTH_CHICKEN1, temp);
2447         }
2448 }
2449
2450 /* The FDI link training functions for ILK/Ibexpeak. */
2451 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453         struct drm_device *dev = crtc->dev;
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456         int pipe = intel_crtc->pipe;
2457         int plane = intel_crtc->plane;
2458         u32 reg, temp, tries;
2459
2460         /* FDI needs bits from pipe & plane first */
2461         assert_pipe_enabled(dev_priv, pipe);
2462         assert_plane_enabled(dev_priv, plane);
2463
2464         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2465            for train result */
2466         reg = FDI_RX_IMR(pipe);
2467         temp = I915_READ(reg);
2468         temp &= ~FDI_RX_SYMBOL_LOCK;
2469         temp &= ~FDI_RX_BIT_LOCK;
2470         I915_WRITE(reg, temp);
2471         I915_READ(reg);
2472         udelay(150);
2473
2474         /* enable CPU FDI TX and PCH FDI RX */
2475         reg = FDI_TX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         temp &= ~(7 << 19);
2478         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2479         temp &= ~FDI_LINK_TRAIN_NONE;
2480         temp |= FDI_LINK_TRAIN_PATTERN_1;
2481         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2482
2483         reg = FDI_RX_CTL(pipe);
2484         temp = I915_READ(reg);
2485         temp &= ~FDI_LINK_TRAIN_NONE;
2486         temp |= FDI_LINK_TRAIN_PATTERN_1;
2487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488
2489         POSTING_READ(reg);
2490         udelay(150);
2491
2492         /* Ironlake workaround, enable clock pointer after FDI enable*/
2493         if (HAS_PCH_IBX(dev)) {
2494                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2495                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2496                            FDI_RX_PHASE_SYNC_POINTER_EN);
2497         }
2498
2499         reg = FDI_RX_IIR(pipe);
2500         for (tries = 0; tries < 5; tries++) {
2501                 temp = I915_READ(reg);
2502                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503
2504                 if ((temp & FDI_RX_BIT_LOCK)) {
2505                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2506                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507                         break;
2508                 }
2509         }
2510         if (tries == 5)
2511                 DRM_ERROR("FDI train 1 fail!\n");
2512
2513         /* Train 2 */
2514         reg = FDI_TX_CTL(pipe);
2515         temp = I915_READ(reg);
2516         temp &= ~FDI_LINK_TRAIN_NONE;
2517         temp |= FDI_LINK_TRAIN_PATTERN_2;
2518         I915_WRITE(reg, temp);
2519
2520         reg = FDI_RX_CTL(pipe);
2521         temp = I915_READ(reg);
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_2;
2524         I915_WRITE(reg, temp);
2525
2526         POSTING_READ(reg);
2527         udelay(150);
2528
2529         reg = FDI_RX_IIR(pipe);
2530         for (tries = 0; tries < 5; tries++) {
2531                 temp = I915_READ(reg);
2532                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534                 if (temp & FDI_RX_SYMBOL_LOCK) {
2535                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2537                         break;
2538                 }
2539         }
2540         if (tries == 5)
2541                 DRM_ERROR("FDI train 2 fail!\n");
2542
2543         DRM_DEBUG_KMS("FDI train done\n");
2544
2545 }
2546
2547 static const int snb_b_fdi_train_param[] = {
2548         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2552 };
2553
2554 /* The FDI link training functions for SNB/Cougarpoint. */
2555 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2556 {
2557         struct drm_device *dev = crtc->dev;
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560         int pipe = intel_crtc->pipe;
2561         u32 reg, temp, i, retry;
2562
2563         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564            for train result */
2565         reg = FDI_RX_IMR(pipe);
2566         temp = I915_READ(reg);
2567         temp &= ~FDI_RX_SYMBOL_LOCK;
2568         temp &= ~FDI_RX_BIT_LOCK;
2569         I915_WRITE(reg, temp);
2570
2571         POSTING_READ(reg);
2572         udelay(150);
2573
2574         /* enable CPU FDI TX and PCH FDI RX */
2575         reg = FDI_TX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~(7 << 19);
2578         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2579         temp &= ~FDI_LINK_TRAIN_NONE;
2580         temp |= FDI_LINK_TRAIN_PATTERN_1;
2581         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582         /* SNB-B */
2583         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2585
2586         I915_WRITE(FDI_RX_MISC(pipe),
2587                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2588
2589         reg = FDI_RX_CTL(pipe);
2590         temp = I915_READ(reg);
2591         if (HAS_PCH_CPT(dev)) {
2592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594         } else {
2595                 temp &= ~FDI_LINK_TRAIN_NONE;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597         }
2598         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600         POSTING_READ(reg);
2601         udelay(150);
2602
2603         if (HAS_PCH_CPT(dev))
2604                 cpt_phase_pointer_enable(dev, pipe);
2605
2606         for (i = 0; i < 4; i++) {
2607                 reg = FDI_TX_CTL(pipe);
2608                 temp = I915_READ(reg);
2609                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610                 temp |= snb_b_fdi_train_param[i];
2611                 I915_WRITE(reg, temp);
2612
2613                 POSTING_READ(reg);
2614                 udelay(500);
2615
2616                 for (retry = 0; retry < 5; retry++) {
2617                         reg = FDI_RX_IIR(pipe);
2618                         temp = I915_READ(reg);
2619                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620                         if (temp & FDI_RX_BIT_LOCK) {
2621                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623                                 break;
2624                         }
2625                         udelay(50);
2626                 }
2627                 if (retry < 5)
2628                         break;
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2;
2638         if (IS_GEN6(dev)) {
2639                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640                 /* SNB-B */
2641                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642         }
2643         I915_WRITE(reg, temp);
2644
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         if (HAS_PCH_CPT(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650         } else {
2651                 temp &= ~FDI_LINK_TRAIN_NONE;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653         }
2654         I915_WRITE(reg, temp);
2655
2656         POSTING_READ(reg);
2657         udelay(150);
2658
2659         for (i = 0; i < 4; i++) {
2660                 reg = FDI_TX_CTL(pipe);
2661                 temp = I915_READ(reg);
2662                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663                 temp |= snb_b_fdi_train_param[i];
2664                 I915_WRITE(reg, temp);
2665
2666                 POSTING_READ(reg);
2667                 udelay(500);
2668
2669                 for (retry = 0; retry < 5; retry++) {
2670                         reg = FDI_RX_IIR(pipe);
2671                         temp = I915_READ(reg);
2672                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673                         if (temp & FDI_RX_SYMBOL_LOCK) {
2674                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676                                 break;
2677                         }
2678                         udelay(50);
2679                 }
2680                 if (retry < 5)
2681                         break;
2682         }
2683         if (i == 4)
2684                 DRM_ERROR("FDI train 2 fail!\n");
2685
2686         DRM_DEBUG_KMS("FDI train done.\n");
2687 }
2688
2689 /* Manual link training for Ivy Bridge A0 parts */
2690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691 {
2692         struct drm_device *dev = crtc->dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp, i;
2697
2698         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699            for train result */
2700         reg = FDI_RX_IMR(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~FDI_RX_SYMBOL_LOCK;
2703         temp &= ~FDI_RX_BIT_LOCK;
2704         I915_WRITE(reg, temp);
2705
2706         POSTING_READ(reg);
2707         udelay(150);
2708
2709         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710                       I915_READ(FDI_RX_IIR(pipe)));
2711
2712         /* enable CPU FDI TX and PCH FDI RX */
2713         reg = FDI_TX_CTL(pipe);
2714         temp = I915_READ(reg);
2715         temp &= ~(7 << 19);
2716         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2717         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2719         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721         temp |= FDI_COMPOSITE_SYNC;
2722         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2723
2724         I915_WRITE(FDI_RX_MISC(pipe),
2725                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2726
2727         reg = FDI_RX_CTL(pipe);
2728         temp = I915_READ(reg);
2729         temp &= ~FDI_LINK_TRAIN_AUTO;
2730         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2731         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2732         temp |= FDI_COMPOSITE_SYNC;
2733         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2734
2735         POSTING_READ(reg);
2736         udelay(150);
2737
2738         if (HAS_PCH_CPT(dev))
2739                 cpt_phase_pointer_enable(dev, pipe);
2740
2741         for (i = 0; i < 4; i++) {
2742                 reg = FDI_TX_CTL(pipe);
2743                 temp = I915_READ(reg);
2744                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745                 temp |= snb_b_fdi_train_param[i];
2746                 I915_WRITE(reg, temp);
2747
2748                 POSTING_READ(reg);
2749                 udelay(500);
2750
2751                 reg = FDI_RX_IIR(pipe);
2752                 temp = I915_READ(reg);
2753                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2754
2755                 if (temp & FDI_RX_BIT_LOCK ||
2756                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2757                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2758                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2759                         break;
2760                 }
2761         }
2762         if (i == 4)
2763                 DRM_ERROR("FDI train 1 fail!\n");
2764
2765         /* Train 2 */
2766         reg = FDI_TX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2769         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2770         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2771         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2772         I915_WRITE(reg, temp);
2773
2774         reg = FDI_RX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2778         I915_WRITE(reg, temp);
2779
2780         POSTING_READ(reg);
2781         udelay(150);
2782
2783         for (i = 0; i < 4; i++) {
2784                 reg = FDI_TX_CTL(pipe);
2785                 temp = I915_READ(reg);
2786                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787                 temp |= snb_b_fdi_train_param[i];
2788                 I915_WRITE(reg, temp);
2789
2790                 POSTING_READ(reg);
2791                 udelay(500);
2792
2793                 reg = FDI_RX_IIR(pipe);
2794                 temp = I915_READ(reg);
2795                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2796
2797                 if (temp & FDI_RX_SYMBOL_LOCK) {
2798                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2799                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2800                         break;
2801                 }
2802         }
2803         if (i == 4)
2804                 DRM_ERROR("FDI train 2 fail!\n");
2805
2806         DRM_DEBUG_KMS("FDI train done.\n");
2807 }
2808
2809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2810 {
2811         struct drm_device *dev = intel_crtc->base.dev;
2812         struct drm_i915_private *dev_priv = dev->dev_private;
2813         int pipe = intel_crtc->pipe;
2814         u32 reg, temp;
2815
2816
2817         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2818         reg = FDI_RX_CTL(pipe);
2819         temp = I915_READ(reg);
2820         temp &= ~((0x7 << 19) | (0x7 << 16));
2821         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2822         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2823         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2824
2825         POSTING_READ(reg);
2826         udelay(200);
2827
2828         /* Switch from Rawclk to PCDclk */
2829         temp = I915_READ(reg);
2830         I915_WRITE(reg, temp | FDI_PCDCLK);
2831
2832         POSTING_READ(reg);
2833         udelay(200);
2834
2835         /* On Haswell, the PLL configuration for ports and pipes is handled
2836          * separately, as part of DDI setup */
2837         if (!IS_HASWELL(dev)) {
2838                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2839                 reg = FDI_TX_CTL(pipe);
2840                 temp = I915_READ(reg);
2841                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2842                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2843
2844                         POSTING_READ(reg);
2845                         udelay(100);
2846                 }
2847         }
2848 }
2849
2850 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2851 {
2852         struct drm_device *dev = intel_crtc->base.dev;
2853         struct drm_i915_private *dev_priv = dev->dev_private;
2854         int pipe = intel_crtc->pipe;
2855         u32 reg, temp;
2856
2857         /* Switch from PCDclk to Rawclk */
2858         reg = FDI_RX_CTL(pipe);
2859         temp = I915_READ(reg);
2860         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2861
2862         /* Disable CPU FDI TX PLL */
2863         reg = FDI_TX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2866
2867         POSTING_READ(reg);
2868         udelay(100);
2869
2870         reg = FDI_RX_CTL(pipe);
2871         temp = I915_READ(reg);
2872         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2873
2874         /* Wait for the clocks to turn off. */
2875         POSTING_READ(reg);
2876         udelay(100);
2877 }
2878
2879 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2880 {
2881         struct drm_i915_private *dev_priv = dev->dev_private;
2882         u32 flags = I915_READ(SOUTH_CHICKEN1);
2883
2884         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2885         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2886         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2887         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2888         POSTING_READ(SOUTH_CHICKEN1);
2889 }
2890 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2891 {
2892         struct drm_device *dev = crtc->dev;
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895         int pipe = intel_crtc->pipe;
2896         u32 reg, temp;
2897
2898         /* disable CPU FDI tx and PCH FDI rx */
2899         reg = FDI_TX_CTL(pipe);
2900         temp = I915_READ(reg);
2901         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2902         POSTING_READ(reg);
2903
2904         reg = FDI_RX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~(0x7 << 16);
2907         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2908         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2909
2910         POSTING_READ(reg);
2911         udelay(100);
2912
2913         /* Ironlake workaround, disable clock pointer after downing FDI */
2914         if (HAS_PCH_IBX(dev)) {
2915                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2916                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2917                            I915_READ(FDI_RX_CHICKEN(pipe) &
2918                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2919         } else if (HAS_PCH_CPT(dev)) {
2920                 cpt_phase_pointer_disable(dev, pipe);
2921         }
2922
2923         /* still set train pattern 1 */
2924         reg = FDI_TX_CTL(pipe);
2925         temp = I915_READ(reg);
2926         temp &= ~FDI_LINK_TRAIN_NONE;
2927         temp |= FDI_LINK_TRAIN_PATTERN_1;
2928         I915_WRITE(reg, temp);
2929
2930         reg = FDI_RX_CTL(pipe);
2931         temp = I915_READ(reg);
2932         if (HAS_PCH_CPT(dev)) {
2933                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2934                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2935         } else {
2936                 temp &= ~FDI_LINK_TRAIN_NONE;
2937                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2938         }
2939         /* BPC in FDI rx is consistent with that in PIPECONF */
2940         temp &= ~(0x07 << 16);
2941         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2942         I915_WRITE(reg, temp);
2943
2944         POSTING_READ(reg);
2945         udelay(100);
2946 }
2947
2948 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2949 {
2950         struct drm_device *dev = crtc->dev;
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952         unsigned long flags;
2953         bool pending;
2954
2955         if (atomic_read(&dev_priv->mm.wedged))
2956                 return false;
2957
2958         spin_lock_irqsave(&dev->event_lock, flags);
2959         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2960         spin_unlock_irqrestore(&dev->event_lock, flags);
2961
2962         return pending;
2963 }
2964
2965 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969
2970         if (crtc->fb == NULL)
2971                 return;
2972
2973         wait_event(dev_priv->pending_flip_queue,
2974                    !intel_crtc_has_pending_flip(crtc));
2975
2976         mutex_lock(&dev->struct_mutex);
2977         intel_finish_fb(crtc->fb);
2978         mutex_unlock(&dev->struct_mutex);
2979 }
2980
2981 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2982 {
2983         struct drm_device *dev = crtc->dev;
2984         struct intel_encoder *intel_encoder;
2985
2986         /*
2987          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2988          * must be driven by its own crtc; no sharing is possible.
2989          */
2990         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2991                 switch (intel_encoder->type) {
2992                 case INTEL_OUTPUT_EDP:
2993                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2994                                 return false;
2995                         continue;
2996                 }
2997         }
2998
2999         return true;
3000 }
3001
3002 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3003 {
3004         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3005 }
3006
3007 /* Program iCLKIP clock to the desired frequency */
3008 static void lpt_program_iclkip(struct drm_crtc *crtc)
3009 {
3010         struct drm_device *dev = crtc->dev;
3011         struct drm_i915_private *dev_priv = dev->dev_private;
3012         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3013         u32 temp;
3014
3015         /* It is necessary to ungate the pixclk gate prior to programming
3016          * the divisors, and gate it back when it is done.
3017          */
3018         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3019
3020         /* Disable SSCCTL */
3021         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3022                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3023                                         SBI_SSCCTL_DISABLE);
3024
3025         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3026         if (crtc->mode.clock == 20000) {
3027                 auxdiv = 1;
3028                 divsel = 0x41;
3029                 phaseinc = 0x20;
3030         } else {
3031                 /* The iCLK virtual clock root frequency is in MHz,
3032                  * but the crtc->mode.clock in in KHz. To get the divisors,
3033                  * it is necessary to divide one by another, so we
3034                  * convert the virtual clock precision to KHz here for higher
3035                  * precision.
3036                  */
3037                 u32 iclk_virtual_root_freq = 172800 * 1000;
3038                 u32 iclk_pi_range = 64;
3039                 u32 desired_divisor, msb_divisor_value, pi_value;
3040
3041                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3042                 msb_divisor_value = desired_divisor / iclk_pi_range;
3043                 pi_value = desired_divisor % iclk_pi_range;
3044
3045                 auxdiv = 0;
3046                 divsel = msb_divisor_value - 2;
3047                 phaseinc = pi_value;
3048         }
3049
3050         /* This should not happen with any sane values */
3051         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3052                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3053         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3054                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3055
3056         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3057                         crtc->mode.clock,
3058                         auxdiv,
3059                         divsel,
3060                         phasedir,
3061                         phaseinc);
3062
3063         /* Program SSCDIVINTPHASE6 */
3064         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3065         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3066         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3067         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3068         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3069         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3070         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3071
3072         intel_sbi_write(dev_priv,
3073                         SBI_SSCDIVINTPHASE6,
3074                         temp);
3075
3076         /* Program SSCAUXDIV */
3077         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3078         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3080         intel_sbi_write(dev_priv,
3081                         SBI_SSCAUXDIV6,
3082                         temp);
3083
3084
3085         /* Enable modulator and associated divider */
3086         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3087         temp &= ~SBI_SSCCTL_DISABLE;
3088         intel_sbi_write(dev_priv,
3089                         SBI_SSCCTL6,
3090                         temp);
3091
3092         /* Wait for initialization time */
3093         udelay(24);
3094
3095         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3096 }
3097
3098 /*
3099  * Enable PCH resources required for PCH ports:
3100  *   - PCH PLLs
3101  *   - FDI training & RX/TX
3102  *   - update transcoder timings
3103  *   - DP transcoding bits
3104  *   - transcoder
3105  */
3106 static void ironlake_pch_enable(struct drm_crtc *crtc)
3107 {
3108         struct drm_device *dev = crtc->dev;
3109         struct drm_i915_private *dev_priv = dev->dev_private;
3110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3111         int pipe = intel_crtc->pipe;
3112         u32 reg, temp;
3113
3114         assert_transcoder_disabled(dev_priv, pipe);
3115
3116         /* Write the TU size bits before fdi link training, so that error
3117          * detection works. */
3118         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3119                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3120
3121         /* For PCH output, training FDI link */
3122         dev_priv->display.fdi_link_train(crtc);
3123
3124         /* XXX: pch pll's can be enabled any time before we enable the PCH
3125          * transcoder, and we actually should do this to not upset any PCH
3126          * transcoder that already use the clock when we share it.
3127          *
3128          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3129          * unconditionally resets the pll - we need that to have the right LVDS
3130          * enable sequence. */
3131         ironlake_enable_pch_pll(intel_crtc);
3132
3133         if (HAS_PCH_CPT(dev)) {
3134                 u32 sel;
3135
3136                 temp = I915_READ(PCH_DPLL_SEL);
3137                 switch (pipe) {
3138                 default:
3139                 case 0:
3140                         temp |= TRANSA_DPLL_ENABLE;
3141                         sel = TRANSA_DPLLB_SEL;
3142                         break;
3143                 case 1:
3144                         temp |= TRANSB_DPLL_ENABLE;
3145                         sel = TRANSB_DPLLB_SEL;
3146                         break;
3147                 case 2:
3148                         temp |= TRANSC_DPLL_ENABLE;
3149                         sel = TRANSC_DPLLB_SEL;
3150                         break;
3151                 }
3152                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3153                         temp |= sel;
3154                 else
3155                         temp &= ~sel;
3156                 I915_WRITE(PCH_DPLL_SEL, temp);
3157         }
3158
3159         /* set transcoder timing, panel must allow it */
3160         assert_panel_unlocked(dev_priv, pipe);
3161         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3162         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3163         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3164
3165         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3166         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3167         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3168         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3169
3170         intel_fdi_normal_train(crtc);
3171
3172         /* For PCH DP, enable TRANS_DP_CTL */
3173         if (HAS_PCH_CPT(dev) &&
3174             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3175              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3176                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3177                 reg = TRANS_DP_CTL(pipe);
3178                 temp = I915_READ(reg);
3179                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3180                           TRANS_DP_SYNC_MASK |
3181                           TRANS_DP_BPC_MASK);
3182                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3183                          TRANS_DP_ENH_FRAMING);
3184                 temp |= bpc << 9; /* same format but at 11:9 */
3185
3186                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3187                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3188                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3189                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3190
3191                 switch (intel_trans_dp_port_sel(crtc)) {
3192                 case PCH_DP_B:
3193                         temp |= TRANS_DP_PORT_SEL_B;
3194                         break;
3195                 case PCH_DP_C:
3196                         temp |= TRANS_DP_PORT_SEL_C;
3197                         break;
3198                 case PCH_DP_D:
3199                         temp |= TRANS_DP_PORT_SEL_D;
3200                         break;
3201                 default:
3202                         BUG();
3203                 }
3204
3205                 I915_WRITE(reg, temp);
3206         }
3207
3208         ironlake_enable_pch_transcoder(dev_priv, pipe);
3209 }
3210
3211 static void lpt_pch_enable(struct drm_crtc *crtc)
3212 {
3213         struct drm_device *dev = crtc->dev;
3214         struct drm_i915_private *dev_priv = dev->dev_private;
3215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216         int pipe = intel_crtc->pipe;
3217         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3218
3219         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3220
3221         /* Write the TU size bits before fdi link training, so that error
3222          * detection works. */
3223         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3224                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3225
3226         /* For PCH output, training FDI link */
3227         dev_priv->display.fdi_link_train(crtc);
3228
3229         lpt_program_iclkip(crtc);
3230
3231         /* Set transcoder timing. */
3232         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3235
3236         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3237         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3238         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3239         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3240
3241         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3242 }
3243
3244 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3245 {
3246         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3247
3248         if (pll == NULL)
3249                 return;
3250
3251         if (pll->refcount == 0) {
3252                 WARN(1, "bad PCH PLL refcount\n");
3253                 return;
3254         }
3255
3256         --pll->refcount;
3257         intel_crtc->pch_pll = NULL;
3258 }
3259
3260 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3261 {
3262         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3263         struct intel_pch_pll *pll;
3264         int i;
3265
3266         pll = intel_crtc->pch_pll;
3267         if (pll) {
3268                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3269                               intel_crtc->base.base.id, pll->pll_reg);
3270                 goto prepare;
3271         }
3272
3273         if (HAS_PCH_IBX(dev_priv->dev)) {
3274                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3275                 i = intel_crtc->pipe;
3276                 pll = &dev_priv->pch_plls[i];
3277
3278                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3279                               intel_crtc->base.base.id, pll->pll_reg);
3280
3281                 goto found;
3282         }
3283
3284         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3285                 pll = &dev_priv->pch_plls[i];
3286
3287                 /* Only want to check enabled timings first */
3288                 if (pll->refcount == 0)
3289                         continue;
3290
3291                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3292                     fp == I915_READ(pll->fp0_reg)) {
3293                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3294                                       intel_crtc->base.base.id,
3295                                       pll->pll_reg, pll->refcount, pll->active);
3296
3297                         goto found;
3298                 }
3299         }
3300
3301         /* Ok no matching timings, maybe there's a free one? */
3302         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3303                 pll = &dev_priv->pch_plls[i];
3304                 if (pll->refcount == 0) {
3305                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3306                                       intel_crtc->base.base.id, pll->pll_reg);
3307                         goto found;
3308                 }
3309         }
3310
3311         return NULL;
3312
3313 found:
3314         intel_crtc->pch_pll = pll;
3315         pll->refcount++;
3316         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3317 prepare: /* separate function? */
3318         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3319
3320         /* Wait for the clocks to stabilize before rewriting the regs */
3321         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3322         POSTING_READ(pll->pll_reg);
3323         udelay(150);
3324
3325         I915_WRITE(pll->fp0_reg, fp);
3326         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3327         pll->on = false;
3328         return pll;
3329 }
3330
3331 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3332 {
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3335         u32 temp;
3336
3337         temp = I915_READ(dslreg);
3338         udelay(500);
3339         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3340                 /* Without this, mode sets may fail silently on FDI */
3341                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3342                 udelay(250);
3343                 I915_WRITE(tc2reg, 0);
3344                 if (wait_for(I915_READ(dslreg) != temp, 5))
3345                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3346         }
3347 }
3348
3349 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         struct intel_encoder *encoder;
3355         int pipe = intel_crtc->pipe;
3356         int plane = intel_crtc->plane;
3357         u32 temp;
3358         bool is_pch_port;
3359
3360         WARN_ON(!crtc->enabled);
3361
3362         if (intel_crtc->active)
3363                 return;
3364
3365         intel_crtc->active = true;
3366         intel_update_watermarks(dev);
3367
3368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3369                 temp = I915_READ(PCH_LVDS);
3370                 if ((temp & LVDS_PORT_EN) == 0)
3371                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3372         }
3373
3374         is_pch_port = ironlake_crtc_driving_pch(crtc);
3375
3376         if (is_pch_port) {
3377                 /* Note: FDI PLL enabling _must_ be done before we enable the
3378                  * cpu pipes, hence this is separate from all the other fdi/pch
3379                  * enabling. */
3380                 ironlake_fdi_pll_enable(intel_crtc);
3381         } else {
3382                 assert_fdi_tx_disabled(dev_priv, pipe);
3383                 assert_fdi_rx_disabled(dev_priv, pipe);
3384         }
3385
3386         for_each_encoder_on_crtc(dev, crtc, encoder)
3387                 if (encoder->pre_enable)
3388                         encoder->pre_enable(encoder);
3389
3390         /* Enable panel fitting for LVDS */
3391         if (dev_priv->pch_pf_size &&
3392             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3393                 /* Force use of hard-coded filter coefficients
3394                  * as some pre-programmed values are broken,
3395                  * e.g. x201.
3396                  */
3397                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3398                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3400         }
3401
3402         /*
3403          * On ILK+ LUT must be loaded before the pipe is running but with
3404          * clocks enabled
3405          */
3406         intel_crtc_load_lut(crtc);
3407
3408         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3409         intel_enable_plane(dev_priv, plane, pipe);
3410
3411         if (is_pch_port)
3412                 ironlake_pch_enable(crtc);
3413
3414         mutex_lock(&dev->struct_mutex);
3415         intel_update_fbc(dev);
3416         mutex_unlock(&dev->struct_mutex);
3417
3418         intel_crtc_update_cursor(crtc, true);
3419
3420         for_each_encoder_on_crtc(dev, crtc, encoder)
3421                 encoder->enable(encoder);
3422
3423         if (HAS_PCH_CPT(dev))
3424                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3425
3426         /*
3427          * There seems to be a race in PCH platform hw (at least on some
3428          * outputs) where an enabled pipe still completes any pageflip right
3429          * away (as if the pipe is off) instead of waiting for vblank. As soon
3430          * as the first vblank happend, everything works as expected. Hence just
3431          * wait for one vblank before returning to avoid strange things
3432          * happening.
3433          */
3434         intel_wait_for_vblank(dev, intel_crtc->pipe);
3435 }
3436
3437 static void haswell_crtc_enable(struct drm_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         struct intel_encoder *encoder;
3443         int pipe = intel_crtc->pipe;
3444         int plane = intel_crtc->plane;
3445         bool is_pch_port;
3446
3447         WARN_ON(!crtc->enabled);
3448
3449         if (intel_crtc->active)
3450                 return;
3451
3452         intel_crtc->active = true;
3453         intel_update_watermarks(dev);
3454
3455         is_pch_port = haswell_crtc_driving_pch(crtc);
3456
3457         if (is_pch_port)
3458                 ironlake_fdi_pll_enable(intel_crtc);
3459
3460         for_each_encoder_on_crtc(dev, crtc, encoder)
3461                 if (encoder->pre_enable)
3462                         encoder->pre_enable(encoder);
3463
3464         intel_ddi_enable_pipe_clock(intel_crtc);
3465
3466         /* Enable panel fitting for eDP */
3467         if (dev_priv->pch_pf_size && HAS_eDP) {
3468                 /* Force use of hard-coded filter coefficients
3469                  * as some pre-programmed values are broken,
3470                  * e.g. x201.
3471                  */
3472                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3473                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3474                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3475         }
3476
3477         /*
3478          * On ILK+ LUT must be loaded before the pipe is running but with
3479          * clocks enabled
3480          */
3481         intel_crtc_load_lut(crtc);
3482
3483         intel_ddi_set_pipe_settings(crtc);
3484         intel_ddi_enable_pipe_func(crtc);
3485
3486         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3487         intel_enable_plane(dev_priv, plane, pipe);
3488
3489         if (is_pch_port)
3490                 lpt_pch_enable(crtc);
3491
3492         mutex_lock(&dev->struct_mutex);
3493         intel_update_fbc(dev);
3494         mutex_unlock(&dev->struct_mutex);
3495
3496         intel_crtc_update_cursor(crtc, true);
3497
3498         for_each_encoder_on_crtc(dev, crtc, encoder)
3499                 encoder->enable(encoder);
3500
3501         /*
3502          * There seems to be a race in PCH platform hw (at least on some
3503          * outputs) where an enabled pipe still completes any pageflip right
3504          * away (as if the pipe is off) instead of waiting for vblank. As soon
3505          * as the first vblank happend, everything works as expected. Hence just
3506          * wait for one vblank before returning to avoid strange things
3507          * happening.
3508          */
3509         intel_wait_for_vblank(dev, intel_crtc->pipe);
3510 }
3511
3512 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3513 {
3514         struct drm_device *dev = crtc->dev;
3515         struct drm_i915_private *dev_priv = dev->dev_private;
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517         struct intel_encoder *encoder;
3518         int pipe = intel_crtc->pipe;
3519         int plane = intel_crtc->plane;
3520         u32 reg, temp;
3521
3522
3523         if (!intel_crtc->active)
3524                 return;
3525
3526         for_each_encoder_on_crtc(dev, crtc, encoder)
3527                 encoder->disable(encoder);
3528
3529         intel_crtc_wait_for_pending_flips(crtc);
3530         drm_vblank_off(dev, pipe);
3531         intel_crtc_update_cursor(crtc, false);
3532
3533         intel_disable_plane(dev_priv, plane, pipe);
3534
3535         if (dev_priv->cfb_plane == plane)
3536                 intel_disable_fbc(dev);
3537
3538         intel_disable_pipe(dev_priv, pipe);
3539
3540         /* Disable PF */
3541         I915_WRITE(PF_CTL(pipe), 0);
3542         I915_WRITE(PF_WIN_SZ(pipe), 0);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         ironlake_fdi_disable(crtc);
3549
3550         ironlake_disable_pch_transcoder(dev_priv, pipe);
3551
3552         if (HAS_PCH_CPT(dev)) {
3553                 /* disable TRANS_DP_CTL */
3554                 reg = TRANS_DP_CTL(pipe);
3555                 temp = I915_READ(reg);
3556                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3557                 temp |= TRANS_DP_PORT_SEL_NONE;
3558                 I915_WRITE(reg, temp);
3559
3560                 /* disable DPLL_SEL */
3561                 temp = I915_READ(PCH_DPLL_SEL);
3562                 switch (pipe) {
3563                 case 0:
3564                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3565                         break;
3566                 case 1:
3567                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3568                         break;
3569                 case 2:
3570                         /* C shares PLL A or B */
3571                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3572                         break;
3573                 default:
3574                         BUG(); /* wtf */
3575                 }
3576                 I915_WRITE(PCH_DPLL_SEL, temp);
3577         }
3578
3579         /* disable PCH DPLL */
3580         intel_disable_pch_pll(intel_crtc);
3581
3582         ironlake_fdi_pll_disable(intel_crtc);
3583
3584         intel_crtc->active = false;
3585         intel_update_watermarks(dev);
3586
3587         mutex_lock(&dev->struct_mutex);
3588         intel_update_fbc(dev);
3589         mutex_unlock(&dev->struct_mutex);
3590 }
3591
3592 static void haswell_crtc_disable(struct drm_crtc *crtc)
3593 {
3594         struct drm_device *dev = crtc->dev;
3595         struct drm_i915_private *dev_priv = dev->dev_private;
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         struct intel_encoder *encoder;
3598         int pipe = intel_crtc->pipe;
3599         int plane = intel_crtc->plane;
3600         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3601         bool is_pch_port;
3602
3603         if (!intel_crtc->active)
3604                 return;
3605
3606         is_pch_port = haswell_crtc_driving_pch(crtc);
3607
3608         for_each_encoder_on_crtc(dev, crtc, encoder)
3609                 encoder->disable(encoder);
3610
3611         intel_crtc_wait_for_pending_flips(crtc);
3612         drm_vblank_off(dev, pipe);
3613         intel_crtc_update_cursor(crtc, false);
3614
3615         intel_disable_plane(dev_priv, plane, pipe);
3616
3617         if (dev_priv->cfb_plane == plane)
3618                 intel_disable_fbc(dev);
3619
3620         intel_disable_pipe(dev_priv, pipe);
3621
3622         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3623
3624         /* Disable PF */
3625         I915_WRITE(PF_CTL(pipe), 0);
3626         I915_WRITE(PF_WIN_SZ(pipe), 0);
3627
3628         intel_ddi_disable_pipe_clock(intel_crtc);
3629
3630         for_each_encoder_on_crtc(dev, crtc, encoder)
3631                 if (encoder->post_disable)
3632                         encoder->post_disable(encoder);
3633
3634         if (is_pch_port) {
3635                 ironlake_fdi_disable(crtc);
3636                 lpt_disable_pch_transcoder(dev_priv);
3637                 ironlake_fdi_pll_disable(intel_crtc);
3638         }
3639
3640         intel_crtc->active = false;
3641         intel_update_watermarks(dev);
3642
3643         mutex_lock(&dev->struct_mutex);
3644         intel_update_fbc(dev);
3645         mutex_unlock(&dev->struct_mutex);
3646 }
3647
3648 static void ironlake_crtc_off(struct drm_crtc *crtc)
3649 {
3650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3651         intel_put_pch_pll(intel_crtc);
3652 }
3653
3654 static void haswell_crtc_off(struct drm_crtc *crtc)
3655 {
3656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657
3658         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3659          * start using it. */
3660         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3661
3662         intel_ddi_put_crtc_pll(crtc);
3663 }
3664
3665 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3666 {
3667         if (!enable && intel_crtc->overlay) {
3668                 struct drm_device *dev = intel_crtc->base.dev;
3669                 struct drm_i915_private *dev_priv = dev->dev_private;
3670
3671                 mutex_lock(&dev->struct_mutex);
3672                 dev_priv->mm.interruptible = false;
3673                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3674                 dev_priv->mm.interruptible = true;
3675                 mutex_unlock(&dev->struct_mutex);
3676         }
3677
3678         /* Let userspace switch the overlay on again. In most cases userspace
3679          * has to recompute where to put it anyway.
3680          */
3681 }
3682
3683 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3684 {
3685         struct drm_device *dev = crtc->dev;
3686         struct drm_i915_private *dev_priv = dev->dev_private;
3687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688         struct intel_encoder *encoder;
3689         int pipe = intel_crtc->pipe;
3690         int plane = intel_crtc->plane;
3691
3692         WARN_ON(!crtc->enabled);
3693
3694         if (intel_crtc->active)
3695                 return;
3696
3697         intel_crtc->active = true;
3698         intel_update_watermarks(dev);
3699
3700         intel_enable_pll(dev_priv, pipe);
3701         intel_enable_pipe(dev_priv, pipe, false);
3702         intel_enable_plane(dev_priv, plane, pipe);
3703
3704         intel_crtc_load_lut(crtc);
3705         intel_update_fbc(dev);
3706
3707         /* Give the overlay scaler a chance to enable if it's on this pipe */
3708         intel_crtc_dpms_overlay(intel_crtc, true);
3709         intel_crtc_update_cursor(crtc, true);
3710
3711         for_each_encoder_on_crtc(dev, crtc, encoder)
3712                 encoder->enable(encoder);
3713 }
3714
3715 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3716 {
3717         struct drm_device *dev = crtc->dev;
3718         struct drm_i915_private *dev_priv = dev->dev_private;
3719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3720         struct intel_encoder *encoder;
3721         int pipe = intel_crtc->pipe;
3722         int plane = intel_crtc->plane;
3723
3724
3725         if (!intel_crtc->active)
3726                 return;
3727
3728         for_each_encoder_on_crtc(dev, crtc, encoder)
3729                 encoder->disable(encoder);
3730
3731         /* Give the overlay scaler a chance to disable if it's on this pipe */
3732         intel_crtc_wait_for_pending_flips(crtc);
3733         drm_vblank_off(dev, pipe);
3734         intel_crtc_dpms_overlay(intel_crtc, false);
3735         intel_crtc_update_cursor(crtc, false);
3736
3737         if (dev_priv->cfb_plane == plane)
3738                 intel_disable_fbc(dev);
3739
3740         intel_disable_plane(dev_priv, plane, pipe);
3741         intel_disable_pipe(dev_priv, pipe);
3742         intel_disable_pll(dev_priv, pipe);
3743
3744         intel_crtc->active = false;
3745         intel_update_fbc(dev);
3746         intel_update_watermarks(dev);
3747 }
3748
3749 static void i9xx_crtc_off(struct drm_crtc *crtc)
3750 {
3751 }
3752
3753 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3754                                     bool enabled)
3755 {
3756         struct drm_device *dev = crtc->dev;
3757         struct drm_i915_master_private *master_priv;
3758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759         int pipe = intel_crtc->pipe;
3760
3761         if (!dev->primary->master)
3762                 return;
3763
3764         master_priv = dev->primary->master->driver_priv;
3765         if (!master_priv->sarea_priv)
3766                 return;
3767
3768         switch (pipe) {
3769         case 0:
3770                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3771                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3772                 break;
3773         case 1:
3774                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3775                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3776                 break;
3777         default:
3778                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3779                 break;
3780         }
3781 }
3782
3783 /**
3784  * Sets the power management mode of the pipe and plane.
3785  */
3786 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_i915_private *dev_priv = dev->dev_private;
3790         struct intel_encoder *intel_encoder;
3791         bool enable = false;
3792
3793         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3794                 enable |= intel_encoder->connectors_active;
3795
3796         if (enable)
3797                 dev_priv->display.crtc_enable(crtc);
3798         else
3799                 dev_priv->display.crtc_disable(crtc);
3800
3801         intel_crtc_update_sarea(crtc, enable);
3802 }
3803
3804 static void intel_crtc_noop(struct drm_crtc *crtc)
3805 {
3806 }
3807
3808 static void intel_crtc_disable(struct drm_crtc *crtc)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811         struct drm_connector *connector;
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814         /* crtc should still be enabled when we disable it. */
3815         WARN_ON(!crtc->enabled);
3816
3817         dev_priv->display.crtc_disable(crtc);
3818         intel_crtc_update_sarea(crtc, false);
3819         dev_priv->display.off(crtc);
3820
3821         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3823
3824         if (crtc->fb) {
3825                 mutex_lock(&dev->struct_mutex);
3826                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3827                 mutex_unlock(&dev->struct_mutex);
3828                 crtc->fb = NULL;
3829         }
3830
3831         /* Update computed state. */
3832         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833                 if (!connector->encoder || !connector->encoder->crtc)
3834                         continue;
3835
3836                 if (connector->encoder->crtc != crtc)
3837                         continue;
3838
3839                 connector->dpms = DRM_MODE_DPMS_OFF;
3840                 to_intel_encoder(connector->encoder)->connectors_active = false;
3841         }
3842 }
3843
3844 void intel_modeset_disable(struct drm_device *dev)
3845 {
3846         struct drm_crtc *crtc;
3847
3848         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849                 if (crtc->enabled)
3850                         intel_crtc_disable(crtc);
3851         }
3852 }
3853
3854 void intel_encoder_noop(struct drm_encoder *encoder)
3855 {
3856 }
3857
3858 void intel_encoder_destroy(struct drm_encoder *encoder)
3859 {
3860         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3861
3862         drm_encoder_cleanup(encoder);
3863         kfree(intel_encoder);
3864 }
3865
3866 /* Simple dpms helper for encodres with just one connector, no cloning and only
3867  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3868  * state of the entire output pipe. */
3869 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3870 {
3871         if (mode == DRM_MODE_DPMS_ON) {
3872                 encoder->connectors_active = true;
3873
3874                 intel_crtc_update_dpms(encoder->base.crtc);
3875         } else {
3876                 encoder->connectors_active = false;
3877
3878                 intel_crtc_update_dpms(encoder->base.crtc);
3879         }
3880 }
3881
3882 /* Cross check the actual hw state with our own modeset state tracking (and it's
3883  * internal consistency). */
3884 static void intel_connector_check_state(struct intel_connector *connector)
3885 {
3886         if (connector->get_hw_state(connector)) {
3887                 struct intel_encoder *encoder = connector->encoder;
3888                 struct drm_crtc *crtc;
3889                 bool encoder_enabled;
3890                 enum pipe pipe;
3891
3892                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3893                               connector->base.base.id,
3894                               drm_get_connector_name(&connector->base));
3895
3896                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3897                      "wrong connector dpms state\n");
3898                 WARN(connector->base.encoder != &encoder->base,
3899                      "active connector not linked to encoder\n");
3900                 WARN(!encoder->connectors_active,
3901                      "encoder->connectors_active not set\n");
3902
3903                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3904                 WARN(!encoder_enabled, "encoder not enabled\n");
3905                 if (WARN_ON(!encoder->base.crtc))
3906                         return;
3907
3908                 crtc = encoder->base.crtc;
3909
3910                 WARN(!crtc->enabled, "crtc not enabled\n");
3911                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3912                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3913                      "encoder active on the wrong pipe\n");
3914         }
3915 }
3916
3917 /* Even simpler default implementation, if there's really no special case to
3918  * consider. */
3919 void intel_connector_dpms(struct drm_connector *connector, int mode)
3920 {
3921         struct intel_encoder *encoder = intel_attached_encoder(connector);
3922
3923         /* All the simple cases only support two dpms states. */
3924         if (mode != DRM_MODE_DPMS_ON)
3925                 mode = DRM_MODE_DPMS_OFF;
3926
3927         if (mode == connector->dpms)
3928                 return;
3929
3930         connector->dpms = mode;
3931
3932         /* Only need to change hw state when actually enabled */
3933         if (encoder->base.crtc)
3934                 intel_encoder_dpms(encoder, mode);
3935         else
3936                 WARN_ON(encoder->connectors_active != false);
3937
3938         intel_modeset_check_state(connector->dev);
3939 }
3940
3941 /* Simple connector->get_hw_state implementation for encoders that support only
3942  * one connector and no cloning and hence the encoder state determines the state
3943  * of the connector. */
3944 bool intel_connector_get_hw_state(struct intel_connector *connector)
3945 {
3946         enum pipe pipe = 0;
3947         struct intel_encoder *encoder = connector->encoder;
3948
3949         return encoder->get_hw_state(encoder, &pipe);
3950 }
3951
3952 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3953                                   const struct drm_display_mode *mode,
3954                                   struct drm_display_mode *adjusted_mode)
3955 {
3956         struct drm_device *dev = crtc->dev;
3957
3958         if (HAS_PCH_SPLIT(dev)) {
3959                 /* FDI link clock is fixed at 2.7G */
3960                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3961                         return false;
3962         }
3963
3964         /* All interlaced capable intel hw wants timings in frames. Note though
3965          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3966          * timings, so we need to be careful not to clobber these.*/
3967         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3968                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3969
3970         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3971          * with a hsync front porch of 0.
3972          */
3973         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3974                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3975                 return false;
3976
3977         return true;
3978 }
3979
3980 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3981 {
3982         return 400000; /* FIXME */
3983 }
3984
3985 static int i945_get_display_clock_speed(struct drm_device *dev)
3986 {
3987         return 400000;
3988 }
3989
3990 static int i915_get_display_clock_speed(struct drm_device *dev)
3991 {
3992         return 333000;
3993 }
3994
3995 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3996 {
3997         return 200000;
3998 }
3999
4000 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4001 {
4002         u16 gcfgc = 0;
4003
4004         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4005
4006         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4007                 return 133000;
4008         else {
4009                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4010                 case GC_DISPLAY_CLOCK_333_MHZ:
4011                         return 333000;
4012                 default:
4013                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4014                         return 190000;
4015                 }
4016         }
4017 }
4018
4019 static int i865_get_display_clock_speed(struct drm_device *dev)
4020 {
4021         return 266000;
4022 }
4023
4024 static int i855_get_display_clock_speed(struct drm_device *dev)
4025 {
4026         u16 hpllcc = 0;
4027         /* Assume that the hardware is in the high speed state.  This
4028          * should be the default.
4029          */
4030         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4031         case GC_CLOCK_133_200:
4032         case GC_CLOCK_100_200:
4033                 return 200000;
4034         case GC_CLOCK_166_250:
4035                 return 250000;
4036         case GC_CLOCK_100_133:
4037                 return 133000;
4038         }
4039
4040         /* Shouldn't happen */
4041         return 0;
4042 }
4043
4044 static int i830_get_display_clock_speed(struct drm_device *dev)
4045 {
4046         return 133000;
4047 }
4048
4049 struct fdi_m_n {
4050         u32        tu;
4051         u32        gmch_m;
4052         u32        gmch_n;
4053         u32        link_m;
4054         u32        link_n;
4055 };
4056
4057 static void
4058 fdi_reduce_ratio(u32 *num, u32 *den)
4059 {
4060         while (*num > 0xffffff || *den > 0xffffff) {
4061                 *num >>= 1;
4062                 *den >>= 1;
4063         }
4064 }
4065
4066 static void
4067 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4068                      int link_clock, struct fdi_m_n *m_n)
4069 {
4070         m_n->tu = 64; /* default size */
4071
4072         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4073         m_n->gmch_m = bits_per_pixel * pixel_clock;
4074         m_n->gmch_n = link_clock * nlanes * 8;
4075         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4076
4077         m_n->link_m = pixel_clock;
4078         m_n->link_n = link_clock;
4079         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4080 }
4081
4082 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4083 {
4084         if (i915_panel_use_ssc >= 0)
4085                 return i915_panel_use_ssc != 0;
4086         return dev_priv->lvds_use_ssc
4087                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4088 }
4089
4090 /**
4091  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4092  * @crtc: CRTC structure
4093  * @mode: requested mode
4094  *
4095  * A pipe may be connected to one or more outputs.  Based on the depth of the
4096  * attached framebuffer, choose a good color depth to use on the pipe.
4097  *
4098  * If possible, match the pipe depth to the fb depth.  In some cases, this
4099  * isn't ideal, because the connected output supports a lesser or restricted
4100  * set of depths.  Resolve that here:
4101  *    LVDS typically supports only 6bpc, so clamp down in that case
4102  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4103  *    Displays may support a restricted set as well, check EDID and clamp as
4104  *      appropriate.
4105  *    DP may want to dither down to 6bpc to fit larger modes
4106  *
4107  * RETURNS:
4108  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4109  * true if they don't match).
4110  */
4111 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4112                                          struct drm_framebuffer *fb,
4113                                          unsigned int *pipe_bpp,
4114                                          struct drm_display_mode *mode)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct drm_connector *connector;
4119         struct intel_encoder *intel_encoder;
4120         unsigned int display_bpc = UINT_MAX, bpc;
4121
4122         /* Walk the encoders & connectors on this crtc, get min bpc */
4123         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4124
4125                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4126                         unsigned int lvds_bpc;
4127
4128                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4129                             LVDS_A3_POWER_UP)
4130                                 lvds_bpc = 8;
4131                         else
4132                                 lvds_bpc = 6;
4133
4134                         if (lvds_bpc < display_bpc) {
4135                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4136                                 display_bpc = lvds_bpc;
4137                         }
4138                         continue;
4139                 }
4140
4141                 /* Not one of the known troublemakers, check the EDID */
4142                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4143                                     head) {
4144                         if (connector->encoder != &intel_encoder->base)
4145                                 continue;
4146
4147                         /* Don't use an invalid EDID bpc value */
4148                         if (connector->display_info.bpc &&
4149                             connector->display_info.bpc < display_bpc) {
4150                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4151                                 display_bpc = connector->display_info.bpc;
4152                         }
4153                 }
4154
4155                 /*
4156                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4157                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4158                  */
4159                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4160                         if (display_bpc > 8 && display_bpc < 12) {
4161                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4162                                 display_bpc = 12;
4163                         } else {
4164                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4165                                 display_bpc = 8;
4166                         }
4167                 }
4168         }
4169
4170         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4171                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4172                 display_bpc = 6;
4173         }
4174
4175         /*
4176          * We could just drive the pipe at the highest bpc all the time and
4177          * enable dithering as needed, but that costs bandwidth.  So choose
4178          * the minimum value that expresses the full color range of the fb but
4179          * also stays within the max display bpc discovered above.
4180          */
4181
4182         switch (fb->depth) {
4183         case 8:
4184                 bpc = 8; /* since we go through a colormap */
4185                 break;
4186         case 15:
4187         case 16:
4188                 bpc = 6; /* min is 18bpp */
4189                 break;
4190         case 24:
4191                 bpc = 8;
4192                 break;
4193         case 30:
4194                 bpc = 10;
4195                 break;
4196         case 48:
4197                 bpc = 12;
4198                 break;
4199         default:
4200                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4201                 bpc = min((unsigned int)8, display_bpc);
4202                 break;
4203         }
4204
4205         display_bpc = min(display_bpc, bpc);
4206
4207         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4208                       bpc, display_bpc);
4209
4210         *pipe_bpp = display_bpc * 3;
4211
4212         return display_bpc != bpc;
4213 }
4214
4215 static int vlv_get_refclk(struct drm_crtc *crtc)
4216 {
4217         struct drm_device *dev = crtc->dev;
4218         struct drm_i915_private *dev_priv = dev->dev_private;
4219         int refclk = 27000; /* for DP & HDMI */
4220
4221         return 100000; /* only one validated so far */
4222
4223         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4224                 refclk = 96000;
4225         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226                 if (intel_panel_use_ssc(dev_priv))
4227                         refclk = 100000;
4228                 else
4229                         refclk = 96000;
4230         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4231                 refclk = 100000;
4232         }
4233
4234         return refclk;
4235 }
4236
4237 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4238 {
4239         struct drm_device *dev = crtc->dev;
4240         struct drm_i915_private *dev_priv = dev->dev_private;
4241         int refclk;
4242
4243         if (IS_VALLEYVIEW(dev)) {
4244                 refclk = vlv_get_refclk(crtc);
4245         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4246             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4247                 refclk = dev_priv->lvds_ssc_freq * 1000;
4248                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4249                               refclk / 1000);
4250         } else if (!IS_GEN2(dev)) {
4251                 refclk = 96000;
4252         } else {
4253                 refclk = 48000;
4254         }
4255
4256         return refclk;
4257 }
4258
4259 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4260                                       intel_clock_t *clock)
4261 {
4262         /* SDVO TV has fixed PLL values depend on its clock range,
4263            this mirrors vbios setting. */
4264         if (adjusted_mode->clock >= 100000
4265             && adjusted_mode->clock < 140500) {
4266                 clock->p1 = 2;
4267                 clock->p2 = 10;
4268                 clock->n = 3;
4269                 clock->m1 = 16;
4270                 clock->m2 = 8;
4271         } else if (adjusted_mode->clock >= 140500
4272                    && adjusted_mode->clock <= 200000) {
4273                 clock->p1 = 1;
4274                 clock->p2 = 10;
4275                 clock->n = 6;
4276                 clock->m1 = 12;
4277                 clock->m2 = 8;
4278         }
4279 }
4280
4281 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4282                                      intel_clock_t *clock,
4283                                      intel_clock_t *reduced_clock)
4284 {
4285         struct drm_device *dev = crtc->dev;
4286         struct drm_i915_private *dev_priv = dev->dev_private;
4287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288         int pipe = intel_crtc->pipe;
4289         u32 fp, fp2 = 0;
4290
4291         if (IS_PINEVIEW(dev)) {
4292                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4293                 if (reduced_clock)
4294                         fp2 = (1 << reduced_clock->n) << 16 |
4295                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4296         } else {
4297                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4298                 if (reduced_clock)
4299                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4300                                 reduced_clock->m2;
4301         }
4302
4303         I915_WRITE(FP0(pipe), fp);
4304
4305         intel_crtc->lowfreq_avail = false;
4306         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4307             reduced_clock && i915_powersave) {
4308                 I915_WRITE(FP1(pipe), fp2);
4309                 intel_crtc->lowfreq_avail = true;
4310         } else {
4311                 I915_WRITE(FP1(pipe), fp);
4312         }
4313 }
4314
4315 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4316                               struct drm_display_mode *adjusted_mode)
4317 {
4318         struct drm_device *dev = crtc->dev;
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321         int pipe = intel_crtc->pipe;
4322         u32 temp;
4323
4324         temp = I915_READ(LVDS);
4325         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4326         if (pipe == 1) {
4327                 temp |= LVDS_PIPEB_SELECT;
4328         } else {
4329                 temp &= ~LVDS_PIPEB_SELECT;
4330         }
4331         /* set the corresponsding LVDS_BORDER bit */
4332         temp |= dev_priv->lvds_border_bits;
4333         /* Set the B0-B3 data pairs corresponding to whether we're going to
4334          * set the DPLLs for dual-channel mode or not.
4335          */
4336         if (clock->p2 == 7)
4337                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4338         else
4339                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4340
4341         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4342          * appropriately here, but we need to look more thoroughly into how
4343          * panels behave in the two modes.
4344          */
4345         /* set the dithering flag on LVDS as needed */
4346         if (INTEL_INFO(dev)->gen >= 4) {
4347                 if (dev_priv->lvds_dither)
4348                         temp |= LVDS_ENABLE_DITHER;
4349                 else
4350                         temp &= ~LVDS_ENABLE_DITHER;
4351         }
4352         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4353         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4354                 temp |= LVDS_HSYNC_POLARITY;
4355         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4356                 temp |= LVDS_VSYNC_POLARITY;
4357         I915_WRITE(LVDS, temp);
4358 }
4359
4360 static void vlv_update_pll(struct drm_crtc *crtc,
4361                            struct drm_display_mode *mode,
4362                            struct drm_display_mode *adjusted_mode,
4363                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4364                            int num_connectors)
4365 {
4366         struct drm_device *dev = crtc->dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369         int pipe = intel_crtc->pipe;
4370         u32 dpll, mdiv, pdiv;
4371         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4372         bool is_sdvo;
4373         u32 temp;
4374
4375         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4376                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4377
4378         dpll = DPLL_VGA_MODE_DIS;
4379         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4380         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4381         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4382
4383         I915_WRITE(DPLL(pipe), dpll);
4384         POSTING_READ(DPLL(pipe));
4385
4386         bestn = clock->n;
4387         bestm1 = clock->m1;
4388         bestm2 = clock->m2;
4389         bestp1 = clock->p1;
4390         bestp2 = clock->p2;
4391
4392         /*
4393          * In Valleyview PLL and program lane counter registers are exposed
4394          * through DPIO interface
4395          */
4396         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4397         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4398         mdiv |= ((bestn << DPIO_N_SHIFT));
4399         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4400         mdiv |= (1 << DPIO_K_SHIFT);
4401         mdiv |= DPIO_ENABLE_CALIBRATION;
4402         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4403
4404         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4405
4406         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4407                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4408                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4409                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4410         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4411
4412         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4413
4414         dpll |= DPLL_VCO_ENABLE;
4415         I915_WRITE(DPLL(pipe), dpll);
4416         POSTING_READ(DPLL(pipe));
4417         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4418                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4419
4420         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4421
4422         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4423                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4424
4425         I915_WRITE(DPLL(pipe), dpll);
4426
4427         /* Wait for the clocks to stabilize. */
4428         POSTING_READ(DPLL(pipe));
4429         udelay(150);
4430
4431         temp = 0;
4432         if (is_sdvo) {
4433                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4434                 if (temp > 1)
4435                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4436                 else
4437                         temp = 0;
4438         }
4439         I915_WRITE(DPLL_MD(pipe), temp);
4440         POSTING_READ(DPLL_MD(pipe));
4441
4442         /* Now program lane control registers */
4443         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4444                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4445         {
4446                 temp = 0x1000C4;
4447                 if(pipe == 1)
4448                         temp |= (1 << 21);
4449                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4450         }
4451         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4452         {
4453                 temp = 0x1000C4;
4454                 if(pipe == 1)
4455                         temp |= (1 << 21);
4456                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4457         }
4458 }
4459
4460 static void i9xx_update_pll(struct drm_crtc *crtc,
4461                             struct drm_display_mode *mode,
4462                             struct drm_display_mode *adjusted_mode,
4463                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4464                             int num_connectors)
4465 {
4466         struct drm_device *dev = crtc->dev;
4467         struct drm_i915_private *dev_priv = dev->dev_private;
4468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4469         int pipe = intel_crtc->pipe;
4470         u32 dpll;
4471         bool is_sdvo;
4472
4473         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4474
4475         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4476                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4477
4478         dpll = DPLL_VGA_MODE_DIS;
4479
4480         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4481                 dpll |= DPLLB_MODE_LVDS;
4482         else
4483                 dpll |= DPLLB_MODE_DAC_SERIAL;
4484         if (is_sdvo) {
4485                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4486                 if (pixel_multiplier > 1) {
4487                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4488                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4489                 }
4490                 dpll |= DPLL_DVO_HIGH_SPEED;
4491         }
4492         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4493                 dpll |= DPLL_DVO_HIGH_SPEED;
4494
4495         /* compute bitmask from p1 value */
4496         if (IS_PINEVIEW(dev))
4497                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4498         else {
4499                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4500                 if (IS_G4X(dev) && reduced_clock)
4501                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4502         }
4503         switch (clock->p2) {
4504         case 5:
4505                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4506                 break;
4507         case 7:
4508                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4509                 break;
4510         case 10:
4511                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4512                 break;
4513         case 14:
4514                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4515                 break;
4516         }
4517         if (INTEL_INFO(dev)->gen >= 4)
4518                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4519
4520         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4521                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4522         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4523                 /* XXX: just matching BIOS for now */
4524                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4525                 dpll |= 3;
4526         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4527                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4528                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4529         else
4530                 dpll |= PLL_REF_INPUT_DREFCLK;
4531
4532         dpll |= DPLL_VCO_ENABLE;
4533         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4534         POSTING_READ(DPLL(pipe));
4535         udelay(150);
4536
4537         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4538          * This is an exception to the general rule that mode_set doesn't turn
4539          * things on.
4540          */
4541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4542                 intel_update_lvds(crtc, clock, adjusted_mode);
4543
4544         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4545                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4546
4547         I915_WRITE(DPLL(pipe), dpll);
4548
4549         /* Wait for the clocks to stabilize. */
4550         POSTING_READ(DPLL(pipe));
4551         udelay(150);
4552
4553         if (INTEL_INFO(dev)->gen >= 4) {
4554                 u32 temp = 0;
4555                 if (is_sdvo) {
4556                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4557                         if (temp > 1)
4558                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4559                         else
4560                                 temp = 0;
4561                 }
4562                 I915_WRITE(DPLL_MD(pipe), temp);
4563         } else {
4564                 /* The pixel multiplier can only be updated once the
4565                  * DPLL is enabled and the clocks are stable.
4566                  *
4567                  * So write it again.
4568                  */
4569                 I915_WRITE(DPLL(pipe), dpll);
4570         }
4571 }
4572
4573 static void i8xx_update_pll(struct drm_crtc *crtc,
4574                             struct drm_display_mode *adjusted_mode,
4575                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4576                             int num_connectors)
4577 {
4578         struct drm_device *dev = crtc->dev;
4579         struct drm_i915_private *dev_priv = dev->dev_private;
4580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581         int pipe = intel_crtc->pipe;
4582         u32 dpll;
4583
4584         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4585
4586         dpll = DPLL_VGA_MODE_DIS;
4587
4588         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4589                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4590         } else {
4591                 if (clock->p1 == 2)
4592                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4593                 else
4594                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595                 if (clock->p2 == 4)
4596                         dpll |= PLL_P2_DIVIDE_BY_4;
4597         }
4598
4599         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4600                 /* XXX: just matching BIOS for now */
4601                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4602                 dpll |= 3;
4603         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4604                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4605                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4606         else
4607                 dpll |= PLL_REF_INPUT_DREFCLK;
4608
4609         dpll |= DPLL_VCO_ENABLE;
4610         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4611         POSTING_READ(DPLL(pipe));
4612         udelay(150);
4613
4614         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4615          * This is an exception to the general rule that mode_set doesn't turn
4616          * things on.
4617          */
4618         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4619                 intel_update_lvds(crtc, clock, adjusted_mode);
4620
4621         I915_WRITE(DPLL(pipe), dpll);
4622
4623         /* Wait for the clocks to stabilize. */
4624         POSTING_READ(DPLL(pipe));
4625         udelay(150);
4626
4627         /* The pixel multiplier can only be updated once the
4628          * DPLL is enabled and the clocks are stable.
4629          *
4630          * So write it again.
4631          */
4632         I915_WRITE(DPLL(pipe), dpll);
4633 }
4634
4635 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4636                                    struct drm_display_mode *mode,
4637                                    struct drm_display_mode *adjusted_mode)
4638 {
4639         struct drm_device *dev = intel_crtc->base.dev;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         enum pipe pipe = intel_crtc->pipe;
4642         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4643         uint32_t vsyncshift;
4644
4645         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4646                 /* the chip adds 2 halflines automatically */
4647                 adjusted_mode->crtc_vtotal -= 1;
4648                 adjusted_mode->crtc_vblank_end -= 1;
4649                 vsyncshift = adjusted_mode->crtc_hsync_start
4650                              - adjusted_mode->crtc_htotal / 2;
4651         } else {
4652                 vsyncshift = 0;
4653         }
4654
4655         if (INTEL_INFO(dev)->gen > 3)
4656                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4657
4658         I915_WRITE(HTOTAL(cpu_transcoder),
4659                    (adjusted_mode->crtc_hdisplay - 1) |
4660                    ((adjusted_mode->crtc_htotal - 1) << 16));
4661         I915_WRITE(HBLANK(cpu_transcoder),
4662                    (adjusted_mode->crtc_hblank_start - 1) |
4663                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4664         I915_WRITE(HSYNC(cpu_transcoder),
4665                    (adjusted_mode->crtc_hsync_start - 1) |
4666                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4667
4668         I915_WRITE(VTOTAL(cpu_transcoder),
4669                    (adjusted_mode->crtc_vdisplay - 1) |
4670                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4671         I915_WRITE(VBLANK(cpu_transcoder),
4672                    (adjusted_mode->crtc_vblank_start - 1) |
4673                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4674         I915_WRITE(VSYNC(cpu_transcoder),
4675                    (adjusted_mode->crtc_vsync_start - 1) |
4676                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4677
4678         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4679          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4680          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4681          * bits. */
4682         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4683             (pipe == PIPE_B || pipe == PIPE_C))
4684                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4685
4686         /* pipesrc controls the size that is scaled from, which should
4687          * always be the user's requested size.
4688          */
4689         I915_WRITE(PIPESRC(pipe),
4690                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4691 }
4692
4693 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4694                               struct drm_display_mode *mode,
4695                               struct drm_display_mode *adjusted_mode,
4696                               int x, int y,
4697                               struct drm_framebuffer *fb)
4698 {
4699         struct drm_device *dev = crtc->dev;
4700         struct drm_i915_private *dev_priv = dev->dev_private;
4701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702         int pipe = intel_crtc->pipe;
4703         int plane = intel_crtc->plane;
4704         int refclk, num_connectors = 0;
4705         intel_clock_t clock, reduced_clock;
4706         u32 dspcntr, pipeconf;
4707         bool ok, has_reduced_clock = false, is_sdvo = false;
4708         bool is_lvds = false, is_tv = false, is_dp = false;
4709         struct intel_encoder *encoder;
4710         const intel_limit_t *limit;
4711         int ret;
4712
4713         for_each_encoder_on_crtc(dev, crtc, encoder) {
4714                 switch (encoder->type) {
4715                 case INTEL_OUTPUT_LVDS:
4716                         is_lvds = true;
4717                         break;
4718                 case INTEL_OUTPUT_SDVO:
4719                 case INTEL_OUTPUT_HDMI:
4720                         is_sdvo = true;
4721                         if (encoder->needs_tv_clock)
4722                                 is_tv = true;
4723                         break;
4724                 case INTEL_OUTPUT_TVOUT:
4725                         is_tv = true;
4726                         break;
4727                 case INTEL_OUTPUT_DISPLAYPORT:
4728                         is_dp = true;
4729                         break;
4730                 }
4731
4732                 num_connectors++;
4733         }
4734
4735         refclk = i9xx_get_refclk(crtc, num_connectors);
4736
4737         /*
4738          * Returns a set of divisors for the desired target clock with the given
4739          * refclk, or FALSE.  The returned values represent the clock equation:
4740          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4741          */
4742         limit = intel_limit(crtc, refclk);
4743         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4744                              &clock);
4745         if (!ok) {
4746                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4747                 return -EINVAL;
4748         }
4749
4750         /* Ensure that the cursor is valid for the new mode before changing... */
4751         intel_crtc_update_cursor(crtc, true);
4752
4753         if (is_lvds && dev_priv->lvds_downclock_avail) {
4754                 /*
4755                  * Ensure we match the reduced clock's P to the target clock.
4756                  * If the clocks don't match, we can't switch the display clock
4757                  * by using the FP0/FP1. In such case we will disable the LVDS
4758                  * downclock feature.
4759                 */
4760                 has_reduced_clock = limit->find_pll(limit, crtc,
4761                                                     dev_priv->lvds_downclock,
4762                                                     refclk,
4763                                                     &clock,
4764                                                     &reduced_clock);
4765         }
4766
4767         if (is_sdvo && is_tv)
4768                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4769
4770         if (IS_GEN2(dev))
4771                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4772                                 has_reduced_clock ? &reduced_clock : NULL,
4773                                 num_connectors);
4774         else if (IS_VALLEYVIEW(dev))
4775                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4776                                 has_reduced_clock ? &reduced_clock : NULL,
4777                                 num_connectors);
4778         else
4779                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4780                                 has_reduced_clock ? &reduced_clock : NULL,
4781                                 num_connectors);
4782
4783         /* setup pipeconf */
4784         pipeconf = I915_READ(PIPECONF(pipe));
4785
4786         /* Set up the display plane register */
4787         dspcntr = DISPPLANE_GAMMA_ENABLE;
4788
4789         if (pipe == 0)
4790                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4791         else
4792                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4793
4794         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4795                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4796                  * core speed.
4797                  *
4798                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4799                  * pipe == 0 check?
4800                  */
4801                 if (mode->clock >
4802                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4803                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4804                 else
4805                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4806         }
4807
4808         /* default to 8bpc */
4809         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4810         if (is_dp) {
4811                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4812                         pipeconf |= PIPECONF_BPP_6 |
4813                                     PIPECONF_DITHER_EN |
4814                                     PIPECONF_DITHER_TYPE_SP;
4815                 }
4816         }
4817
4818         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4819                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4820                         pipeconf |= PIPECONF_BPP_6 |
4821                                         PIPECONF_ENABLE |
4822                                         I965_PIPECONF_ACTIVE;
4823                 }
4824         }
4825
4826         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4827         drm_mode_debug_printmodeline(mode);
4828
4829         if (HAS_PIPE_CXSR(dev)) {
4830                 if (intel_crtc->lowfreq_avail) {
4831                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4832                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4833                 } else {
4834                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4835                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4836                 }
4837         }
4838
4839         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4840         if (!IS_GEN2(dev) &&
4841             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4842                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4843         else
4844                 pipeconf |= PIPECONF_PROGRESSIVE;
4845
4846         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4847
4848         /* pipesrc and dspsize control the size that is scaled from,
4849          * which should always be the user's requested size.
4850          */
4851         I915_WRITE(DSPSIZE(plane),
4852                    ((mode->vdisplay - 1) << 16) |
4853                    (mode->hdisplay - 1));
4854         I915_WRITE(DSPPOS(plane), 0);
4855
4856         I915_WRITE(PIPECONF(pipe), pipeconf);
4857         POSTING_READ(PIPECONF(pipe));
4858         intel_enable_pipe(dev_priv, pipe, false);
4859
4860         intel_wait_for_vblank(dev, pipe);
4861
4862         I915_WRITE(DSPCNTR(plane), dspcntr);
4863         POSTING_READ(DSPCNTR(plane));
4864
4865         ret = intel_pipe_set_base(crtc, x, y, fb);
4866
4867         intel_update_watermarks(dev);
4868
4869         return ret;
4870 }
4871
4872 /*
4873  * Initialize reference clocks when the driver loads
4874  */
4875 void ironlake_init_pch_refclk(struct drm_device *dev)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct drm_mode_config *mode_config = &dev->mode_config;
4879         struct intel_encoder *encoder;
4880         u32 temp;
4881         bool has_lvds = false;
4882         bool has_cpu_edp = false;
4883         bool has_pch_edp = false;
4884         bool has_panel = false;
4885         bool has_ck505 = false;
4886         bool can_ssc = false;
4887
4888         /* We need to take the global config into account */
4889         list_for_each_entry(encoder, &mode_config->encoder_list,
4890                             base.head) {
4891                 switch (encoder->type) {
4892                 case INTEL_OUTPUT_LVDS:
4893                         has_panel = true;
4894                         has_lvds = true;
4895                         break;
4896                 case INTEL_OUTPUT_EDP:
4897                         has_panel = true;
4898                         if (intel_encoder_is_pch_edp(&encoder->base))
4899                                 has_pch_edp = true;
4900                         else
4901                                 has_cpu_edp = true;
4902                         break;
4903                 }
4904         }
4905
4906         if (HAS_PCH_IBX(dev)) {
4907                 has_ck505 = dev_priv->display_clock_mode;
4908                 can_ssc = has_ck505;
4909         } else {
4910                 has_ck505 = false;
4911                 can_ssc = true;
4912         }
4913
4914         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4915                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4916                       has_ck505);
4917
4918         /* Ironlake: try to setup display ref clock before DPLL
4919          * enabling. This is only under driver's control after
4920          * PCH B stepping, previous chipset stepping should be
4921          * ignoring this setting.
4922          */
4923         temp = I915_READ(PCH_DREF_CONTROL);
4924         /* Always enable nonspread source */
4925         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4926
4927         if (has_ck505)
4928                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4929         else
4930                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4931
4932         if (has_panel) {
4933                 temp &= ~DREF_SSC_SOURCE_MASK;
4934                 temp |= DREF_SSC_SOURCE_ENABLE;
4935
4936                 /* SSC must be turned on before enabling the CPU output  */
4937                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4938                         DRM_DEBUG_KMS("Using SSC on panel\n");
4939                         temp |= DREF_SSC1_ENABLE;
4940                 } else
4941                         temp &= ~DREF_SSC1_ENABLE;
4942
4943                 /* Get SSC going before enabling the outputs */
4944                 I915_WRITE(PCH_DREF_CONTROL, temp);
4945                 POSTING_READ(PCH_DREF_CONTROL);
4946                 udelay(200);
4947
4948                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4949
4950                 /* Enable CPU source on CPU attached eDP */
4951                 if (has_cpu_edp) {
4952                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4953                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4954                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4955                         }
4956                         else
4957                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4958                 } else
4959                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4960
4961                 I915_WRITE(PCH_DREF_CONTROL, temp);
4962                 POSTING_READ(PCH_DREF_CONTROL);
4963                 udelay(200);
4964         } else {
4965                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4966
4967                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4968
4969                 /* Turn off CPU output */
4970                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4971
4972                 I915_WRITE(PCH_DREF_CONTROL, temp);
4973                 POSTING_READ(PCH_DREF_CONTROL);
4974                 udelay(200);
4975
4976                 /* Turn off the SSC source */
4977                 temp &= ~DREF_SSC_SOURCE_MASK;
4978                 temp |= DREF_SSC_SOURCE_DISABLE;
4979
4980                 /* Turn off SSC1 */
4981                 temp &= ~ DREF_SSC1_ENABLE;
4982
4983                 I915_WRITE(PCH_DREF_CONTROL, temp);
4984                 POSTING_READ(PCH_DREF_CONTROL);
4985                 udelay(200);
4986         }
4987 }
4988
4989 static int ironlake_get_refclk(struct drm_crtc *crtc)
4990 {
4991         struct drm_device *dev = crtc->dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         struct intel_encoder *encoder;
4994         struct intel_encoder *edp_encoder = NULL;
4995         int num_connectors = 0;
4996         bool is_lvds = false;
4997
4998         for_each_encoder_on_crtc(dev, crtc, encoder) {
4999                 switch (encoder->type) {
5000                 case INTEL_OUTPUT_LVDS:
5001                         is_lvds = true;
5002                         break;
5003                 case INTEL_OUTPUT_EDP:
5004                         edp_encoder = encoder;
5005                         break;
5006                 }
5007                 num_connectors++;
5008         }
5009
5010         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5011                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5012                               dev_priv->lvds_ssc_freq);
5013                 return dev_priv->lvds_ssc_freq * 1000;
5014         }
5015
5016         return 120000;
5017 }
5018
5019 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5020                                   struct drm_display_mode *adjusted_mode,
5021                                   bool dither)
5022 {
5023         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025         int pipe = intel_crtc->pipe;
5026         uint32_t val;
5027
5028         val = I915_READ(PIPECONF(pipe));
5029
5030         val &= ~PIPE_BPC_MASK;
5031         switch (intel_crtc->bpp) {
5032         case 18:
5033                 val |= PIPE_6BPC;
5034                 break;
5035         case 24:
5036                 val |= PIPE_8BPC;
5037                 break;
5038         case 30:
5039                 val |= PIPE_10BPC;
5040                 break;
5041         case 36:
5042                 val |= PIPE_12BPC;
5043                 break;
5044         default:
5045                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5046                 BUG();
5047         }
5048
5049         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5050         if (dither)
5051                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5052
5053         val &= ~PIPECONF_INTERLACE_MASK;
5054         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5055                 val |= PIPECONF_INTERLACED_ILK;
5056         else
5057                 val |= PIPECONF_PROGRESSIVE;
5058
5059         I915_WRITE(PIPECONF(pipe), val);
5060         POSTING_READ(PIPECONF(pipe));
5061 }
5062
5063 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5064                                  struct drm_display_mode *adjusted_mode,
5065                                  bool dither)
5066 {
5067         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5070         uint32_t val;
5071
5072         val = I915_READ(PIPECONF(cpu_transcoder));
5073
5074         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5075         if (dither)
5076                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5077
5078         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5079         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5080                 val |= PIPECONF_INTERLACED_ILK;
5081         else
5082                 val |= PIPECONF_PROGRESSIVE;
5083
5084         I915_WRITE(PIPECONF(cpu_transcoder), val);
5085         POSTING_READ(PIPECONF(cpu_transcoder));
5086 }
5087
5088 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5089                                     struct drm_display_mode *adjusted_mode,
5090                                     intel_clock_t *clock,
5091                                     bool *has_reduced_clock,
5092                                     intel_clock_t *reduced_clock)
5093 {
5094         struct drm_device *dev = crtc->dev;
5095         struct drm_i915_private *dev_priv = dev->dev_private;
5096         struct intel_encoder *intel_encoder;
5097         int refclk;
5098         const intel_limit_t *limit;
5099         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5100
5101         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5102                 switch (intel_encoder->type) {
5103                 case INTEL_OUTPUT_LVDS:
5104                         is_lvds = true;
5105                         break;
5106                 case INTEL_OUTPUT_SDVO:
5107                 case INTEL_OUTPUT_HDMI:
5108                         is_sdvo = true;
5109                         if (intel_encoder->needs_tv_clock)
5110                                 is_tv = true;
5111                         break;
5112                 case INTEL_OUTPUT_TVOUT:
5113                         is_tv = true;
5114                         break;
5115                 }
5116         }
5117
5118         refclk = ironlake_get_refclk(crtc);
5119
5120         /*
5121          * Returns a set of divisors for the desired target clock with the given
5122          * refclk, or FALSE.  The returned values represent the clock equation:
5123          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5124          */
5125         limit = intel_limit(crtc, refclk);
5126         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5127                               clock);
5128         if (!ret)
5129                 return false;
5130
5131         if (is_lvds && dev_priv->lvds_downclock_avail) {
5132                 /*
5133                  * Ensure we match the reduced clock's P to the target clock.
5134                  * If the clocks don't match, we can't switch the display clock
5135                  * by using the FP0/FP1. In such case we will disable the LVDS
5136                  * downclock feature.
5137                 */
5138                 *has_reduced_clock = limit->find_pll(limit, crtc,
5139                                                      dev_priv->lvds_downclock,
5140                                                      refclk,
5141                                                      clock,
5142                                                      reduced_clock);
5143         }
5144
5145         if (is_sdvo && is_tv)
5146                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5147
5148         return true;
5149 }
5150
5151 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5152 {
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         uint32_t temp;
5155
5156         temp = I915_READ(SOUTH_CHICKEN1);
5157         if (temp & FDI_BC_BIFURCATION_SELECT)
5158                 return;
5159
5160         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5161         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5162
5163         temp |= FDI_BC_BIFURCATION_SELECT;
5164         DRM_DEBUG_KMS("enabling fdi C rx\n");
5165         I915_WRITE(SOUTH_CHICKEN1, temp);
5166         POSTING_READ(SOUTH_CHICKEN1);
5167 }
5168
5169 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5170 {
5171         struct drm_device *dev = intel_crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         struct intel_crtc *pipe_B_crtc =
5174                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5175
5176         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5177                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5178         if (intel_crtc->fdi_lanes > 4) {
5179                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5180                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5181                 /* Clamp lanes to avoid programming the hw with bogus values. */
5182                 intel_crtc->fdi_lanes = 4;
5183
5184                 return false;
5185         }
5186
5187         if (dev_priv->num_pipe == 2)
5188                 return true;
5189
5190         switch (intel_crtc->pipe) {
5191         case PIPE_A:
5192                 return true;
5193         case PIPE_B:
5194                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5195                     intel_crtc->fdi_lanes > 2) {
5196                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5197                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5198                         /* Clamp lanes to avoid programming the hw with bogus values. */
5199                         intel_crtc->fdi_lanes = 2;
5200
5201                         return false;
5202                 }
5203
5204                 if (intel_crtc->fdi_lanes > 2)
5205                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5206                 else
5207                         cpt_enable_fdi_bc_bifurcation(dev);
5208
5209                 return true;
5210         case PIPE_C:
5211                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5212                         if (intel_crtc->fdi_lanes > 2) {
5213                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5214                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5215                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5216                                 intel_crtc->fdi_lanes = 2;
5217
5218                                 return false;
5219                         }
5220                 } else {
5221                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5222                         return false;
5223                 }
5224
5225                 cpt_enable_fdi_bc_bifurcation(dev);
5226
5227                 return true;
5228         default:
5229                 BUG();
5230         }
5231 }
5232
5233 static void ironlake_set_m_n(struct drm_crtc *crtc,
5234                              struct drm_display_mode *mode,
5235                              struct drm_display_mode *adjusted_mode)
5236 {
5237         struct drm_device *dev = crtc->dev;
5238         struct drm_i915_private *dev_priv = dev->dev_private;
5239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5241         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5242         struct fdi_m_n m_n = {0};
5243         int target_clock, pixel_multiplier, lane, link_bw;
5244         bool is_dp = false, is_cpu_edp = false;
5245
5246         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5247                 switch (intel_encoder->type) {
5248                 case INTEL_OUTPUT_DISPLAYPORT:
5249                         is_dp = true;
5250                         break;
5251                 case INTEL_OUTPUT_EDP:
5252                         is_dp = true;
5253                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5254                                 is_cpu_edp = true;
5255                         edp_encoder = intel_encoder;
5256                         break;
5257                 }
5258         }
5259
5260         /* FDI link */
5261         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5262         lane = 0;
5263         /* CPU eDP doesn't require FDI link, so just set DP M/N
5264            according to current link config */
5265         if (is_cpu_edp) {
5266                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5267         } else {
5268                 /* FDI is a binary signal running at ~2.7GHz, encoding
5269                  * each output octet as 10 bits. The actual frequency
5270                  * is stored as a divider into a 100MHz clock, and the
5271                  * mode pixel clock is stored in units of 1KHz.
5272                  * Hence the bw of each lane in terms of the mode signal
5273                  * is:
5274                  */
5275                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5276         }
5277
5278         /* [e]DP over FDI requires target mode clock instead of link clock. */
5279         if (edp_encoder)
5280                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5281         else if (is_dp)
5282                 target_clock = mode->clock;
5283         else
5284                 target_clock = adjusted_mode->clock;
5285
5286         if (!lane) {
5287                 /*
5288                  * Account for spread spectrum to avoid
5289                  * oversubscribing the link. Max center spread
5290                  * is 2.5%; use 5% for safety's sake.
5291                  */
5292                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5293                 lane = bps / (link_bw * 8) + 1;
5294         }
5295
5296         intel_crtc->fdi_lanes = lane;
5297
5298         if (pixel_multiplier > 1)
5299                 link_bw *= pixel_multiplier;
5300         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5301                              &m_n);
5302
5303         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5304         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5305         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5306         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5307 }
5308
5309 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5310                                       struct drm_display_mode *adjusted_mode,
5311                                       intel_clock_t *clock, u32 fp)
5312 {
5313         struct drm_crtc *crtc = &intel_crtc->base;
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         struct intel_encoder *intel_encoder;
5317         uint32_t dpll;
5318         int factor, pixel_multiplier, num_connectors = 0;
5319         bool is_lvds = false, is_sdvo = false, is_tv = false;
5320         bool is_dp = false, is_cpu_edp = false;
5321
5322         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5323                 switch (intel_encoder->type) {
5324                 case INTEL_OUTPUT_LVDS:
5325                         is_lvds = true;
5326                         break;
5327                 case INTEL_OUTPUT_SDVO:
5328                 case INTEL_OUTPUT_HDMI:
5329                         is_sdvo = true;
5330                         if (intel_encoder->needs_tv_clock)
5331                                 is_tv = true;
5332                         break;
5333                 case INTEL_OUTPUT_TVOUT:
5334                         is_tv = true;
5335                         break;
5336                 case INTEL_OUTPUT_DISPLAYPORT:
5337                         is_dp = true;
5338                         break;
5339                 case INTEL_OUTPUT_EDP:
5340                         is_dp = true;
5341                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5342                                 is_cpu_edp = true;
5343                         break;
5344                 }
5345
5346                 num_connectors++;
5347         }
5348
5349         /* Enable autotuning of the PLL clock (if permissible) */
5350         factor = 21;
5351         if (is_lvds) {
5352                 if ((intel_panel_use_ssc(dev_priv) &&
5353                      dev_priv->lvds_ssc_freq == 100) ||
5354                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5355                         factor = 25;
5356         } else if (is_sdvo && is_tv)
5357                 factor = 20;
5358
5359         if (clock->m < factor * clock->n)
5360                 fp |= FP_CB_TUNE;
5361
5362         dpll = 0;
5363
5364         if (is_lvds)
5365                 dpll |= DPLLB_MODE_LVDS;
5366         else
5367                 dpll |= DPLLB_MODE_DAC_SERIAL;
5368         if (is_sdvo) {
5369                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5370                 if (pixel_multiplier > 1) {
5371                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5372                 }
5373                 dpll |= DPLL_DVO_HIGH_SPEED;
5374         }
5375         if (is_dp && !is_cpu_edp)
5376                 dpll |= DPLL_DVO_HIGH_SPEED;
5377
5378         /* compute bitmask from p1 value */
5379         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5380         /* also FPA1 */
5381         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5382
5383         switch (clock->p2) {
5384         case 5:
5385                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5386                 break;
5387         case 7:
5388                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5389                 break;
5390         case 10:
5391                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5392                 break;
5393         case 14:
5394                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5395                 break;
5396         }
5397
5398         if (is_sdvo && is_tv)
5399                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5400         else if (is_tv)
5401                 /* XXX: just matching BIOS for now */
5402                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5403                 dpll |= 3;
5404         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5405                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5406         else
5407                 dpll |= PLL_REF_INPUT_DREFCLK;
5408
5409         return dpll;
5410 }
5411
5412 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5413                                   struct drm_display_mode *mode,
5414                                   struct drm_display_mode *adjusted_mode,
5415                                   int x, int y,
5416                                   struct drm_framebuffer *fb)
5417 {
5418         struct drm_device *dev = crtc->dev;
5419         struct drm_i915_private *dev_priv = dev->dev_private;
5420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421         int pipe = intel_crtc->pipe;
5422         int plane = intel_crtc->plane;
5423         int num_connectors = 0;
5424         intel_clock_t clock, reduced_clock;
5425         u32 dpll, fp = 0, fp2 = 0;
5426         bool ok, has_reduced_clock = false;
5427         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5428         struct intel_encoder *encoder;
5429         u32 temp;
5430         int ret;
5431         bool dither, fdi_config_ok;
5432
5433         for_each_encoder_on_crtc(dev, crtc, encoder) {
5434                 switch (encoder->type) {
5435                 case INTEL_OUTPUT_LVDS:
5436                         is_lvds = true;
5437                         break;
5438                 case INTEL_OUTPUT_DISPLAYPORT:
5439                         is_dp = true;
5440                         break;
5441                 case INTEL_OUTPUT_EDP:
5442                         is_dp = true;
5443                         if (!intel_encoder_is_pch_edp(&encoder->base))
5444                                 is_cpu_edp = true;
5445                         break;
5446                 }
5447
5448                 num_connectors++;
5449         }
5450
5451         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5452              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5453
5454         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5455                                      &has_reduced_clock, &reduced_clock);
5456         if (!ok) {
5457                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5458                 return -EINVAL;
5459         }
5460
5461         /* Ensure that the cursor is valid for the new mode before changing... */
5462         intel_crtc_update_cursor(crtc, true);
5463
5464         /* determine panel color depth */
5465         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5466                                               adjusted_mode);
5467         if (is_lvds && dev_priv->lvds_dither)
5468                 dither = true;
5469
5470         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5471         if (has_reduced_clock)
5472                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5473                         reduced_clock.m2;
5474
5475         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5476
5477         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5478         drm_mode_debug_printmodeline(mode);
5479
5480         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5481         if (!is_cpu_edp) {
5482                 struct intel_pch_pll *pll;
5483
5484                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5485                 if (pll == NULL) {
5486                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5487                                          pipe);
5488                         return -EINVAL;
5489                 }
5490         } else
5491                 intel_put_pch_pll(intel_crtc);
5492
5493         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5494          * This is an exception to the general rule that mode_set doesn't turn
5495          * things on.
5496          */
5497         if (is_lvds) {
5498                 temp = I915_READ(PCH_LVDS);
5499                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5500                 if (HAS_PCH_CPT(dev)) {
5501                         temp &= ~PORT_TRANS_SEL_MASK;
5502                         temp |= PORT_TRANS_SEL_CPT(pipe);
5503                 } else {
5504                         if (pipe == 1)
5505                                 temp |= LVDS_PIPEB_SELECT;
5506                         else
5507                                 temp &= ~LVDS_PIPEB_SELECT;
5508                 }
5509
5510                 /* set the corresponsding LVDS_BORDER bit */
5511                 temp |= dev_priv->lvds_border_bits;
5512                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5513                  * set the DPLLs for dual-channel mode or not.
5514                  */
5515                 if (clock.p2 == 7)
5516                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5517                 else
5518                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5519
5520                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5521                  * appropriately here, but we need to look more thoroughly into how
5522                  * panels behave in the two modes.
5523                  */
5524                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5525                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5526                         temp |= LVDS_HSYNC_POLARITY;
5527                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5528                         temp |= LVDS_VSYNC_POLARITY;
5529                 I915_WRITE(PCH_LVDS, temp);
5530         }
5531
5532         if (is_dp && !is_cpu_edp) {
5533                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5534         } else {
5535                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5536                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5537                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5538                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5539                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5540         }
5541
5542         if (intel_crtc->pch_pll) {
5543                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5544
5545                 /* Wait for the clocks to stabilize. */
5546                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5547                 udelay(150);
5548
5549                 /* The pixel multiplier can only be updated once the
5550                  * DPLL is enabled and the clocks are stable.
5551                  *
5552                  * So write it again.
5553                  */
5554                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5555         }
5556
5557         intel_crtc->lowfreq_avail = false;
5558         if (intel_crtc->pch_pll) {
5559                 if (is_lvds && has_reduced_clock && i915_powersave) {
5560                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5561                         intel_crtc->lowfreq_avail = true;
5562                 } else {
5563                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5564                 }
5565         }
5566
5567         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5568
5569         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5570          * ironlake_check_fdi_lanes. */
5571         ironlake_set_m_n(crtc, mode, adjusted_mode);
5572
5573         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5574
5575         if (is_cpu_edp)
5576                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5577
5578         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5579
5580         intel_wait_for_vblank(dev, pipe);
5581
5582         /* Set up the display plane register */
5583         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5584         POSTING_READ(DSPCNTR(plane));
5585
5586         ret = intel_pipe_set_base(crtc, x, y, fb);
5587
5588         intel_update_watermarks(dev);
5589
5590         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5591
5592         return fdi_config_ok ? ret : -EINVAL;
5593 }
5594
5595 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5596                                  struct drm_display_mode *mode,
5597                                  struct drm_display_mode *adjusted_mode,
5598                                  int x, int y,
5599                                  struct drm_framebuffer *fb)
5600 {
5601         struct drm_device *dev = crtc->dev;
5602         struct drm_i915_private *dev_priv = dev->dev_private;
5603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5604         int pipe = intel_crtc->pipe;
5605         int plane = intel_crtc->plane;
5606         int num_connectors = 0;
5607         intel_clock_t clock, reduced_clock;
5608         u32 dpll = 0, fp = 0, fp2 = 0;
5609         bool ok, has_reduced_clock = false;
5610         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5611         struct intel_encoder *encoder;
5612         u32 temp;
5613         int ret;
5614         bool dither;
5615
5616         for_each_encoder_on_crtc(dev, crtc, encoder) {
5617                 switch (encoder->type) {
5618                 case INTEL_OUTPUT_LVDS:
5619                         is_lvds = true;
5620                         break;
5621                 case INTEL_OUTPUT_DISPLAYPORT:
5622                         is_dp = true;
5623                         break;
5624                 case INTEL_OUTPUT_EDP:
5625                         is_dp = true;
5626                         if (!intel_encoder_is_pch_edp(&encoder->base))
5627                                 is_cpu_edp = true;
5628                         break;
5629                 }
5630
5631                 num_connectors++;
5632         }
5633
5634         if (is_cpu_edp)
5635                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5636         else
5637                 intel_crtc->cpu_transcoder = pipe;
5638
5639         /* We are not sure yet this won't happen. */
5640         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5641              INTEL_PCH_TYPE(dev));
5642
5643         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5644              num_connectors, pipe_name(pipe));
5645
5646         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5647                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5648
5649         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5650
5651         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5652                 return -EINVAL;
5653
5654         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5655                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5656                                              &has_reduced_clock,
5657                                              &reduced_clock);
5658                 if (!ok) {
5659                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5660                         return -EINVAL;
5661                 }
5662         }
5663
5664         /* Ensure that the cursor is valid for the new mode before changing... */
5665         intel_crtc_update_cursor(crtc, true);
5666
5667         /* determine panel color depth */
5668         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5669                                               adjusted_mode);
5670         if (is_lvds && dev_priv->lvds_dither)
5671                 dither = true;
5672
5673         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5674         drm_mode_debug_printmodeline(mode);
5675
5676         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5677                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5678                 if (has_reduced_clock)
5679                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5680                               reduced_clock.m2;
5681
5682                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5683                                              fp);
5684
5685                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5686                  * own on pre-Haswell/LPT generation */
5687                 if (!is_cpu_edp) {
5688                         struct intel_pch_pll *pll;
5689
5690                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5691                         if (pll == NULL) {
5692                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5693                                                  pipe);
5694                                 return -EINVAL;
5695                         }
5696                 } else
5697                         intel_put_pch_pll(intel_crtc);
5698
5699                 /* The LVDS pin pair needs to be on before the DPLLs are
5700                  * enabled.  This is an exception to the general rule that
5701                  * mode_set doesn't turn things on.
5702                  */
5703                 if (is_lvds) {
5704                         temp = I915_READ(PCH_LVDS);
5705                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5706                         if (HAS_PCH_CPT(dev)) {
5707                                 temp &= ~PORT_TRANS_SEL_MASK;
5708                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5709                         } else {
5710                                 if (pipe == 1)
5711                                         temp |= LVDS_PIPEB_SELECT;
5712                                 else
5713                                         temp &= ~LVDS_PIPEB_SELECT;
5714                         }
5715
5716                         /* set the corresponsding LVDS_BORDER bit */
5717                         temp |= dev_priv->lvds_border_bits;
5718                         /* Set the B0-B3 data pairs corresponding to whether
5719                          * we're going to set the DPLLs for dual-channel mode or
5720                          * not.
5721                          */
5722                         if (clock.p2 == 7)
5723                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5724                         else
5725                                 temp &= ~(LVDS_B0B3_POWER_UP |
5726                                           LVDS_CLKB_POWER_UP);
5727
5728                         /* It would be nice to set 24 vs 18-bit mode
5729                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5730                          * look more thoroughly into how panels behave in the
5731                          * two modes.
5732                          */
5733                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5734                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5735                                 temp |= LVDS_HSYNC_POLARITY;
5736                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5737                                 temp |= LVDS_VSYNC_POLARITY;
5738                         I915_WRITE(PCH_LVDS, temp);
5739                 }
5740         }
5741
5742         if (is_dp && !is_cpu_edp) {
5743                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5744         } else {
5745                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5746                         /* For non-DP output, clear any trans DP clock recovery
5747                          * setting.*/
5748                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5749                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5750                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5751                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5752                 }
5753         }
5754
5755         intel_crtc->lowfreq_avail = false;
5756         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5757                 if (intel_crtc->pch_pll) {
5758                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5759
5760                         /* Wait for the clocks to stabilize. */
5761                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5762                         udelay(150);
5763
5764                         /* The pixel multiplier can only be updated once the
5765                          * DPLL is enabled and the clocks are stable.
5766                          *
5767                          * So write it again.
5768                          */
5769                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5770                 }
5771
5772                 if (intel_crtc->pch_pll) {
5773                         if (is_lvds && has_reduced_clock && i915_powersave) {
5774                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5775                                 intel_crtc->lowfreq_avail = true;
5776                         } else {
5777                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5778                         }
5779                 }
5780         }
5781
5782         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5783
5784         if (!is_dp || is_cpu_edp)
5785                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5786
5787         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5788                 if (is_cpu_edp)
5789                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5790
5791         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5792
5793         /* Set up the display plane register */
5794         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5795         POSTING_READ(DSPCNTR(plane));
5796
5797         ret = intel_pipe_set_base(crtc, x, y, fb);
5798
5799         intel_update_watermarks(dev);
5800
5801         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5802
5803         return ret;
5804 }
5805
5806 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5807                                struct drm_display_mode *mode,
5808                                struct drm_display_mode *adjusted_mode,
5809                                int x, int y,
5810                                struct drm_framebuffer *fb)
5811 {
5812         struct drm_device *dev = crtc->dev;
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         struct drm_encoder_helper_funcs *encoder_funcs;
5815         struct intel_encoder *encoder;
5816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817         int pipe = intel_crtc->pipe;
5818         int ret;
5819
5820         drm_vblank_pre_modeset(dev, pipe);
5821
5822         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5823                                               x, y, fb);
5824         drm_vblank_post_modeset(dev, pipe);
5825
5826         if (ret != 0)
5827                 return ret;
5828
5829         for_each_encoder_on_crtc(dev, crtc, encoder) {
5830                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5831                         encoder->base.base.id,
5832                         drm_get_encoder_name(&encoder->base),
5833                         mode->base.id, mode->name);
5834                 encoder_funcs = encoder->base.helper_private;
5835                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5836         }
5837
5838         return 0;
5839 }
5840
5841 static bool intel_eld_uptodate(struct drm_connector *connector,
5842                                int reg_eldv, uint32_t bits_eldv,
5843                                int reg_elda, uint32_t bits_elda,
5844                                int reg_edid)
5845 {
5846         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5847         uint8_t *eld = connector->eld;
5848         uint32_t i;
5849
5850         i = I915_READ(reg_eldv);
5851         i &= bits_eldv;
5852
5853         if (!eld[0])
5854                 return !i;
5855
5856         if (!i)
5857                 return false;
5858
5859         i = I915_READ(reg_elda);
5860         i &= ~bits_elda;
5861         I915_WRITE(reg_elda, i);
5862
5863         for (i = 0; i < eld[2]; i++)
5864                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5865                         return false;
5866
5867         return true;
5868 }
5869
5870 static void g4x_write_eld(struct drm_connector *connector,
5871                           struct drm_crtc *crtc)
5872 {
5873         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5874         uint8_t *eld = connector->eld;
5875         uint32_t eldv;
5876         uint32_t len;
5877         uint32_t i;
5878
5879         i = I915_READ(G4X_AUD_VID_DID);
5880
5881         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5882                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5883         else
5884                 eldv = G4X_ELDV_DEVCTG;
5885
5886         if (intel_eld_uptodate(connector,
5887                                G4X_AUD_CNTL_ST, eldv,
5888                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5889                                G4X_HDMIW_HDMIEDID))
5890                 return;
5891
5892         i = I915_READ(G4X_AUD_CNTL_ST);
5893         i &= ~(eldv | G4X_ELD_ADDR);
5894         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5895         I915_WRITE(G4X_AUD_CNTL_ST, i);
5896
5897         if (!eld[0])
5898                 return;
5899
5900         len = min_t(uint8_t, eld[2], len);
5901         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5902         for (i = 0; i < len; i++)
5903                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5904
5905         i = I915_READ(G4X_AUD_CNTL_ST);
5906         i |= eldv;
5907         I915_WRITE(G4X_AUD_CNTL_ST, i);
5908 }
5909
5910 static void haswell_write_eld(struct drm_connector *connector,
5911                                      struct drm_crtc *crtc)
5912 {
5913         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5914         uint8_t *eld = connector->eld;
5915         struct drm_device *dev = crtc->dev;
5916         uint32_t eldv;
5917         uint32_t i;
5918         int len;
5919         int pipe = to_intel_crtc(crtc)->pipe;
5920         int tmp;
5921
5922         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5923         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5924         int aud_config = HSW_AUD_CFG(pipe);
5925         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5926
5927
5928         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5929
5930         /* Audio output enable */
5931         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5932         tmp = I915_READ(aud_cntrl_st2);
5933         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5934         I915_WRITE(aud_cntrl_st2, tmp);
5935
5936         /* Wait for 1 vertical blank */
5937         intel_wait_for_vblank(dev, pipe);
5938
5939         /* Set ELD valid state */
5940         tmp = I915_READ(aud_cntrl_st2);
5941         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5942         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5943         I915_WRITE(aud_cntrl_st2, tmp);
5944         tmp = I915_READ(aud_cntrl_st2);
5945         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5946
5947         /* Enable HDMI mode */
5948         tmp = I915_READ(aud_config);
5949         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5950         /* clear N_programing_enable and N_value_index */
5951         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5952         I915_WRITE(aud_config, tmp);
5953
5954         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5955
5956         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5957
5958         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5959                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5960                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5961                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5962         } else
5963                 I915_WRITE(aud_config, 0);
5964
5965         if (intel_eld_uptodate(connector,
5966                                aud_cntrl_st2, eldv,
5967                                aud_cntl_st, IBX_ELD_ADDRESS,
5968                                hdmiw_hdmiedid))
5969                 return;
5970
5971         i = I915_READ(aud_cntrl_st2);
5972         i &= ~eldv;
5973         I915_WRITE(aud_cntrl_st2, i);
5974
5975         if (!eld[0])
5976                 return;
5977
5978         i = I915_READ(aud_cntl_st);
5979         i &= ~IBX_ELD_ADDRESS;
5980         I915_WRITE(aud_cntl_st, i);
5981         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5982         DRM_DEBUG_DRIVER("port num:%d\n", i);
5983
5984         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5985         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5986         for (i = 0; i < len; i++)
5987                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5988
5989         i = I915_READ(aud_cntrl_st2);
5990         i |= eldv;
5991         I915_WRITE(aud_cntrl_st2, i);
5992
5993 }
5994
5995 static void ironlake_write_eld(struct drm_connector *connector,
5996                                      struct drm_crtc *crtc)
5997 {
5998         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5999         uint8_t *eld = connector->eld;
6000         uint32_t eldv;
6001         uint32_t i;
6002         int len;
6003         int hdmiw_hdmiedid;
6004         int aud_config;
6005         int aud_cntl_st;
6006         int aud_cntrl_st2;
6007         int pipe = to_intel_crtc(crtc)->pipe;
6008
6009         if (HAS_PCH_IBX(connector->dev)) {
6010                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6011                 aud_config = IBX_AUD_CFG(pipe);
6012                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6013                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6014         } else {
6015                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6016                 aud_config = CPT_AUD_CFG(pipe);
6017                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6018                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6019         }
6020
6021         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6022
6023         i = I915_READ(aud_cntl_st);
6024         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6025         if (!i) {
6026                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6027                 /* operate blindly on all ports */
6028                 eldv = IBX_ELD_VALIDB;
6029                 eldv |= IBX_ELD_VALIDB << 4;
6030                 eldv |= IBX_ELD_VALIDB << 8;
6031         } else {
6032                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6033                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6034         }
6035
6036         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6037                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6038                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6039                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6040         } else
6041                 I915_WRITE(aud_config, 0);
6042
6043         if (intel_eld_uptodate(connector,
6044                                aud_cntrl_st2, eldv,
6045                                aud_cntl_st, IBX_ELD_ADDRESS,
6046                                hdmiw_hdmiedid))
6047                 return;
6048
6049         i = I915_READ(aud_cntrl_st2);
6050         i &= ~eldv;
6051         I915_WRITE(aud_cntrl_st2, i);
6052
6053         if (!eld[0])
6054                 return;
6055
6056         i = I915_READ(aud_cntl_st);
6057         i &= ~IBX_ELD_ADDRESS;
6058         I915_WRITE(aud_cntl_st, i);
6059
6060         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6061         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6062         for (i = 0; i < len; i++)
6063                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6064
6065         i = I915_READ(aud_cntrl_st2);
6066         i |= eldv;
6067         I915_WRITE(aud_cntrl_st2, i);
6068 }
6069
6070 void intel_write_eld(struct drm_encoder *encoder,
6071                      struct drm_display_mode *mode)
6072 {
6073         struct drm_crtc *crtc = encoder->crtc;
6074         struct drm_connector *connector;
6075         struct drm_device *dev = encoder->dev;
6076         struct drm_i915_private *dev_priv = dev->dev_private;
6077
6078         connector = drm_select_eld(encoder, mode);
6079         if (!connector)
6080                 return;
6081
6082         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6083                          connector->base.id,
6084                          drm_get_connector_name(connector),
6085                          connector->encoder->base.id,
6086                          drm_get_encoder_name(connector->encoder));
6087
6088         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6089
6090         if (dev_priv->display.write_eld)
6091                 dev_priv->display.write_eld(connector, crtc);
6092 }
6093
6094 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6095 void intel_crtc_load_lut(struct drm_crtc *crtc)
6096 {
6097         struct drm_device *dev = crtc->dev;
6098         struct drm_i915_private *dev_priv = dev->dev_private;
6099         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6100         int palreg = PALETTE(intel_crtc->pipe);
6101         int i;
6102
6103         /* The clocks have to be on to load the palette. */
6104         if (!crtc->enabled || !intel_crtc->active)
6105                 return;
6106
6107         /* use legacy palette for Ironlake */
6108         if (HAS_PCH_SPLIT(dev))
6109                 palreg = LGC_PALETTE(intel_crtc->pipe);
6110
6111         for (i = 0; i < 256; i++) {
6112                 I915_WRITE(palreg + 4 * i,
6113                            (intel_crtc->lut_r[i] << 16) |
6114                            (intel_crtc->lut_g[i] << 8) |
6115                            intel_crtc->lut_b[i]);
6116         }
6117 }
6118
6119 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6120 {
6121         struct drm_device *dev = crtc->dev;
6122         struct drm_i915_private *dev_priv = dev->dev_private;
6123         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124         bool visible = base != 0;
6125         u32 cntl;
6126
6127         if (intel_crtc->cursor_visible == visible)
6128                 return;
6129
6130         cntl = I915_READ(_CURACNTR);
6131         if (visible) {
6132                 /* On these chipsets we can only modify the base whilst
6133                  * the cursor is disabled.
6134                  */
6135                 I915_WRITE(_CURABASE, base);
6136
6137                 cntl &= ~(CURSOR_FORMAT_MASK);
6138                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6139                 cntl |= CURSOR_ENABLE |
6140                         CURSOR_GAMMA_ENABLE |
6141                         CURSOR_FORMAT_ARGB;
6142         } else
6143                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6144         I915_WRITE(_CURACNTR, cntl);
6145
6146         intel_crtc->cursor_visible = visible;
6147 }
6148
6149 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6150 {
6151         struct drm_device *dev = crtc->dev;
6152         struct drm_i915_private *dev_priv = dev->dev_private;
6153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154         int pipe = intel_crtc->pipe;
6155         bool visible = base != 0;
6156
6157         if (intel_crtc->cursor_visible != visible) {
6158                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6159                 if (base) {
6160                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6161                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6162                         cntl |= pipe << 28; /* Connect to correct pipe */
6163                 } else {
6164                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6165                         cntl |= CURSOR_MODE_DISABLE;
6166                 }
6167                 I915_WRITE(CURCNTR(pipe), cntl);
6168
6169                 intel_crtc->cursor_visible = visible;
6170         }
6171         /* and commit changes on next vblank */
6172         I915_WRITE(CURBASE(pipe), base);
6173 }
6174
6175 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6176 {
6177         struct drm_device *dev = crtc->dev;
6178         struct drm_i915_private *dev_priv = dev->dev_private;
6179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180         int pipe = intel_crtc->pipe;
6181         bool visible = base != 0;
6182
6183         if (intel_crtc->cursor_visible != visible) {
6184                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6185                 if (base) {
6186                         cntl &= ~CURSOR_MODE;
6187                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6188                 } else {
6189                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6190                         cntl |= CURSOR_MODE_DISABLE;
6191                 }
6192                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6193
6194                 intel_crtc->cursor_visible = visible;
6195         }
6196         /* and commit changes on next vblank */
6197         I915_WRITE(CURBASE_IVB(pipe), base);
6198 }
6199
6200 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6201 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6202                                      bool on)
6203 {
6204         struct drm_device *dev = crtc->dev;
6205         struct drm_i915_private *dev_priv = dev->dev_private;
6206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207         int pipe = intel_crtc->pipe;
6208         int x = intel_crtc->cursor_x;
6209         int y = intel_crtc->cursor_y;
6210         u32 base, pos;
6211         bool visible;
6212
6213         pos = 0;
6214
6215         if (on && crtc->enabled && crtc->fb) {
6216                 base = intel_crtc->cursor_addr;
6217                 if (x > (int) crtc->fb->width)
6218                         base = 0;
6219
6220                 if (y > (int) crtc->fb->height)
6221                         base = 0;
6222         } else
6223                 base = 0;
6224
6225         if (x < 0) {
6226                 if (x + intel_crtc->cursor_width < 0)
6227                         base = 0;
6228
6229                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6230                 x = -x;
6231         }
6232         pos |= x << CURSOR_X_SHIFT;
6233
6234         if (y < 0) {
6235                 if (y + intel_crtc->cursor_height < 0)
6236                         base = 0;
6237
6238                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6239                 y = -y;
6240         }
6241         pos |= y << CURSOR_Y_SHIFT;
6242
6243         visible = base != 0;
6244         if (!visible && !intel_crtc->cursor_visible)
6245                 return;
6246
6247         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6248                 I915_WRITE(CURPOS_IVB(pipe), pos);
6249                 ivb_update_cursor(crtc, base);
6250         } else {
6251                 I915_WRITE(CURPOS(pipe), pos);
6252                 if (IS_845G(dev) || IS_I865G(dev))
6253                         i845_update_cursor(crtc, base);
6254                 else
6255                         i9xx_update_cursor(crtc, base);
6256         }
6257 }
6258
6259 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6260                                  struct drm_file *file,
6261                                  uint32_t handle,
6262                                  uint32_t width, uint32_t height)
6263 {
6264         struct drm_device *dev = crtc->dev;
6265         struct drm_i915_private *dev_priv = dev->dev_private;
6266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267         struct drm_i915_gem_object *obj;
6268         uint32_t addr;
6269         int ret;
6270
6271         /* if we want to turn off the cursor ignore width and height */
6272         if (!handle) {
6273                 DRM_DEBUG_KMS("cursor off\n");
6274                 addr = 0;
6275                 obj = NULL;
6276                 mutex_lock(&dev->struct_mutex);
6277                 goto finish;
6278         }
6279
6280         /* Currently we only support 64x64 cursors */
6281         if (width != 64 || height != 64) {
6282                 DRM_ERROR("we currently only support 64x64 cursors\n");
6283                 return -EINVAL;
6284         }
6285
6286         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6287         if (&obj->base == NULL)
6288                 return -ENOENT;
6289
6290         if (obj->base.size < width * height * 4) {
6291                 DRM_ERROR("buffer is to small\n");
6292                 ret = -ENOMEM;
6293                 goto fail;
6294         }
6295
6296         /* we only need to pin inside GTT if cursor is non-phy */
6297         mutex_lock(&dev->struct_mutex);
6298         if (!dev_priv->info->cursor_needs_physical) {
6299                 if (obj->tiling_mode) {
6300                         DRM_ERROR("cursor cannot be tiled\n");
6301                         ret = -EINVAL;
6302                         goto fail_locked;
6303                 }
6304
6305                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6306                 if (ret) {
6307                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6308                         goto fail_locked;
6309                 }
6310
6311                 ret = i915_gem_object_put_fence(obj);
6312                 if (ret) {
6313                         DRM_ERROR("failed to release fence for cursor");
6314                         goto fail_unpin;
6315                 }
6316
6317                 addr = obj->gtt_offset;
6318         } else {
6319                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6320                 ret = i915_gem_attach_phys_object(dev, obj,
6321                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6322                                                   align);
6323                 if (ret) {
6324                         DRM_ERROR("failed to attach phys object\n");
6325                         goto fail_locked;
6326                 }
6327                 addr = obj->phys_obj->handle->busaddr;
6328         }
6329
6330         if (IS_GEN2(dev))
6331                 I915_WRITE(CURSIZE, (height << 12) | width);
6332
6333  finish:
6334         if (intel_crtc->cursor_bo) {
6335                 if (dev_priv->info->cursor_needs_physical) {
6336                         if (intel_crtc->cursor_bo != obj)
6337                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6338                 } else
6339                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6340                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6341         }
6342
6343         mutex_unlock(&dev->struct_mutex);
6344
6345         intel_crtc->cursor_addr = addr;
6346         intel_crtc->cursor_bo = obj;
6347         intel_crtc->cursor_width = width;
6348         intel_crtc->cursor_height = height;
6349
6350         intel_crtc_update_cursor(crtc, true);
6351
6352         return 0;
6353 fail_unpin:
6354         i915_gem_object_unpin(obj);
6355 fail_locked:
6356         mutex_unlock(&dev->struct_mutex);
6357 fail:
6358         drm_gem_object_unreference_unlocked(&obj->base);
6359         return ret;
6360 }
6361
6362 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6363 {
6364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365
6366         intel_crtc->cursor_x = x;
6367         intel_crtc->cursor_y = y;
6368
6369         intel_crtc_update_cursor(crtc, true);
6370
6371         return 0;
6372 }
6373
6374 /** Sets the color ramps on behalf of RandR */
6375 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6376                                  u16 blue, int regno)
6377 {
6378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379
6380         intel_crtc->lut_r[regno] = red >> 8;
6381         intel_crtc->lut_g[regno] = green >> 8;
6382         intel_crtc->lut_b[regno] = blue >> 8;
6383 }
6384
6385 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6386                              u16 *blue, int regno)
6387 {
6388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389
6390         *red = intel_crtc->lut_r[regno] << 8;
6391         *green = intel_crtc->lut_g[regno] << 8;
6392         *blue = intel_crtc->lut_b[regno] << 8;
6393 }
6394
6395 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6396                                  u16 *blue, uint32_t start, uint32_t size)
6397 {
6398         int end = (start + size > 256) ? 256 : start + size, i;
6399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6400
6401         for (i = start; i < end; i++) {
6402                 intel_crtc->lut_r[i] = red[i] >> 8;
6403                 intel_crtc->lut_g[i] = green[i] >> 8;
6404                 intel_crtc->lut_b[i] = blue[i] >> 8;
6405         }
6406
6407         intel_crtc_load_lut(crtc);
6408 }
6409
6410 /**
6411  * Get a pipe with a simple mode set on it for doing load-based monitor
6412  * detection.
6413  *
6414  * It will be up to the load-detect code to adjust the pipe as appropriate for
6415  * its requirements.  The pipe will be connected to no other encoders.
6416  *
6417  * Currently this code will only succeed if there is a pipe with no encoders
6418  * configured for it.  In the future, it could choose to temporarily disable
6419  * some outputs to free up a pipe for its use.
6420  *
6421  * \return crtc, or NULL if no pipes are available.
6422  */
6423
6424 /* VESA 640x480x72Hz mode to set on the pipe */
6425 static struct drm_display_mode load_detect_mode = {
6426         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6427                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6428 };
6429
6430 static struct drm_framebuffer *
6431 intel_framebuffer_create(struct drm_device *dev,
6432                          struct drm_mode_fb_cmd2 *mode_cmd,
6433                          struct drm_i915_gem_object *obj)
6434 {
6435         struct intel_framebuffer *intel_fb;
6436         int ret;
6437
6438         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6439         if (!intel_fb) {
6440                 drm_gem_object_unreference_unlocked(&obj->base);
6441                 return ERR_PTR(-ENOMEM);
6442         }
6443
6444         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6445         if (ret) {
6446                 drm_gem_object_unreference_unlocked(&obj->base);
6447                 kfree(intel_fb);
6448                 return ERR_PTR(ret);
6449         }
6450
6451         return &intel_fb->base;
6452 }
6453
6454 static u32
6455 intel_framebuffer_pitch_for_width(int width, int bpp)
6456 {
6457         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6458         return ALIGN(pitch, 64);
6459 }
6460
6461 static u32
6462 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6463 {
6464         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6465         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6466 }
6467
6468 static struct drm_framebuffer *
6469 intel_framebuffer_create_for_mode(struct drm_device *dev,
6470                                   struct drm_display_mode *mode,
6471                                   int depth, int bpp)
6472 {
6473         struct drm_i915_gem_object *obj;
6474         struct drm_mode_fb_cmd2 mode_cmd;
6475
6476         obj = i915_gem_alloc_object(dev,
6477                                     intel_framebuffer_size_for_mode(mode, bpp));
6478         if (obj == NULL)
6479                 return ERR_PTR(-ENOMEM);
6480
6481         mode_cmd.width = mode->hdisplay;
6482         mode_cmd.height = mode->vdisplay;
6483         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6484                                                                 bpp);
6485         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6486
6487         return intel_framebuffer_create(dev, &mode_cmd, obj);
6488 }
6489
6490 static struct drm_framebuffer *
6491 mode_fits_in_fbdev(struct drm_device *dev,
6492                    struct drm_display_mode *mode)
6493 {
6494         struct drm_i915_private *dev_priv = dev->dev_private;
6495         struct drm_i915_gem_object *obj;
6496         struct drm_framebuffer *fb;
6497
6498         if (dev_priv->fbdev == NULL)
6499                 return NULL;
6500
6501         obj = dev_priv->fbdev->ifb.obj;
6502         if (obj == NULL)
6503                 return NULL;
6504
6505         fb = &dev_priv->fbdev->ifb.base;
6506         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6507                                                                fb->bits_per_pixel))
6508                 return NULL;
6509
6510         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6511                 return NULL;
6512
6513         return fb;
6514 }
6515
6516 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6517                                 struct drm_display_mode *mode,
6518                                 struct intel_load_detect_pipe *old)
6519 {
6520         struct intel_crtc *intel_crtc;
6521         struct intel_encoder *intel_encoder =
6522                 intel_attached_encoder(connector);
6523         struct drm_crtc *possible_crtc;
6524         struct drm_encoder *encoder = &intel_encoder->base;
6525         struct drm_crtc *crtc = NULL;
6526         struct drm_device *dev = encoder->dev;
6527         struct drm_framebuffer *fb;
6528         int i = -1;
6529
6530         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6531                       connector->base.id, drm_get_connector_name(connector),
6532                       encoder->base.id, drm_get_encoder_name(encoder));
6533
6534         /*
6535          * Algorithm gets a little messy:
6536          *
6537          *   - if the connector already has an assigned crtc, use it (but make
6538          *     sure it's on first)
6539          *
6540          *   - try to find the first unused crtc that can drive this connector,
6541          *     and use that if we find one
6542          */
6543
6544         /* See if we already have a CRTC for this connector */
6545         if (encoder->crtc) {
6546                 crtc = encoder->crtc;
6547
6548                 old->dpms_mode = connector->dpms;
6549                 old->load_detect_temp = false;
6550
6551                 /* Make sure the crtc and connector are running */
6552                 if (connector->dpms != DRM_MODE_DPMS_ON)
6553                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6554
6555                 return true;
6556         }
6557
6558         /* Find an unused one (if possible) */
6559         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6560                 i++;
6561                 if (!(encoder->possible_crtcs & (1 << i)))
6562                         continue;
6563                 if (!possible_crtc->enabled) {
6564                         crtc = possible_crtc;
6565                         break;
6566                 }
6567         }
6568
6569         /*
6570          * If we didn't find an unused CRTC, don't use any.
6571          */
6572         if (!crtc) {
6573                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6574                 return false;
6575         }
6576
6577         intel_encoder->new_crtc = to_intel_crtc(crtc);
6578         to_intel_connector(connector)->new_encoder = intel_encoder;
6579
6580         intel_crtc = to_intel_crtc(crtc);
6581         old->dpms_mode = connector->dpms;
6582         old->load_detect_temp = true;
6583         old->release_fb = NULL;
6584
6585         if (!mode)
6586                 mode = &load_detect_mode;
6587
6588         /* We need a framebuffer large enough to accommodate all accesses
6589          * that the plane may generate whilst we perform load detection.
6590          * We can not rely on the fbcon either being present (we get called
6591          * during its initialisation to detect all boot displays, or it may
6592          * not even exist) or that it is large enough to satisfy the
6593          * requested mode.
6594          */
6595         fb = mode_fits_in_fbdev(dev, mode);
6596         if (fb == NULL) {
6597                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6598                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6599                 old->release_fb = fb;
6600         } else
6601                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6602         if (IS_ERR(fb)) {
6603                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6604                 goto fail;
6605         }
6606
6607         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6608                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6609                 if (old->release_fb)
6610                         old->release_fb->funcs->destroy(old->release_fb);
6611                 goto fail;
6612         }
6613
6614         /* let the connector get through one full cycle before testing */
6615         intel_wait_for_vblank(dev, intel_crtc->pipe);
6616
6617         return true;
6618 fail:
6619         connector->encoder = NULL;
6620         encoder->crtc = NULL;
6621         return false;
6622 }
6623
6624 void intel_release_load_detect_pipe(struct drm_connector *connector,
6625                                     struct intel_load_detect_pipe *old)
6626 {
6627         struct intel_encoder *intel_encoder =
6628                 intel_attached_encoder(connector);
6629         struct drm_encoder *encoder = &intel_encoder->base;
6630
6631         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6632                       connector->base.id, drm_get_connector_name(connector),
6633                       encoder->base.id, drm_get_encoder_name(encoder));
6634
6635         if (old->load_detect_temp) {
6636                 struct drm_crtc *crtc = encoder->crtc;
6637
6638                 to_intel_connector(connector)->new_encoder = NULL;
6639                 intel_encoder->new_crtc = NULL;
6640                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6641
6642                 if (old->release_fb)
6643                         old->release_fb->funcs->destroy(old->release_fb);
6644
6645                 return;
6646         }
6647
6648         /* Switch crtc and encoder back off if necessary */
6649         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6650                 connector->funcs->dpms(connector, old->dpms_mode);
6651 }
6652
6653 /* Returns the clock of the currently programmed mode of the given pipe. */
6654 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6655 {
6656         struct drm_i915_private *dev_priv = dev->dev_private;
6657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6658         int pipe = intel_crtc->pipe;
6659         u32 dpll = I915_READ(DPLL(pipe));
6660         u32 fp;
6661         intel_clock_t clock;
6662
6663         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6664                 fp = I915_READ(FP0(pipe));
6665         else
6666                 fp = I915_READ(FP1(pipe));
6667
6668         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6669         if (IS_PINEVIEW(dev)) {
6670                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6671                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6672         } else {
6673                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6674                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6675         }
6676
6677         if (!IS_GEN2(dev)) {
6678                 if (IS_PINEVIEW(dev))
6679                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6680                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6681                 else
6682                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6683                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6684
6685                 switch (dpll & DPLL_MODE_MASK) {
6686                 case DPLLB_MODE_DAC_SERIAL:
6687                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6688                                 5 : 10;
6689                         break;
6690                 case DPLLB_MODE_LVDS:
6691                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6692                                 7 : 14;
6693                         break;
6694                 default:
6695                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6696                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6697                         return 0;
6698                 }
6699
6700                 /* XXX: Handle the 100Mhz refclk */
6701                 intel_clock(dev, 96000, &clock);
6702         } else {
6703                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6704
6705                 if (is_lvds) {
6706                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6707                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6708                         clock.p2 = 14;
6709
6710                         if ((dpll & PLL_REF_INPUT_MASK) ==
6711                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6712                                 /* XXX: might not be 66MHz */
6713                                 intel_clock(dev, 66000, &clock);
6714                         } else
6715                                 intel_clock(dev, 48000, &clock);
6716                 } else {
6717                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6718                                 clock.p1 = 2;
6719                         else {
6720                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6721                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6722                         }
6723                         if (dpll & PLL_P2_DIVIDE_BY_4)
6724                                 clock.p2 = 4;
6725                         else
6726                                 clock.p2 = 2;
6727
6728                         intel_clock(dev, 48000, &clock);
6729                 }
6730         }
6731
6732         /* XXX: It would be nice to validate the clocks, but we can't reuse
6733          * i830PllIsValid() because it relies on the xf86_config connector
6734          * configuration being accurate, which it isn't necessarily.
6735          */
6736
6737         return clock.dot;
6738 }
6739
6740 /** Returns the currently programmed mode of the given pipe. */
6741 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6742                                              struct drm_crtc *crtc)
6743 {
6744         struct drm_i915_private *dev_priv = dev->dev_private;
6745         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6746         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6747         struct drm_display_mode *mode;
6748         int htot = I915_READ(HTOTAL(cpu_transcoder));
6749         int hsync = I915_READ(HSYNC(cpu_transcoder));
6750         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6751         int vsync = I915_READ(VSYNC(cpu_transcoder));
6752
6753         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6754         if (!mode)
6755                 return NULL;
6756
6757         mode->clock = intel_crtc_clock_get(dev, crtc);
6758         mode->hdisplay = (htot & 0xffff) + 1;
6759         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6760         mode->hsync_start = (hsync & 0xffff) + 1;
6761         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6762         mode->vdisplay = (vtot & 0xffff) + 1;
6763         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6764         mode->vsync_start = (vsync & 0xffff) + 1;
6765         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6766
6767         drm_mode_set_name(mode);
6768
6769         return mode;
6770 }
6771
6772 static void intel_increase_pllclock(struct drm_crtc *crtc)
6773 {
6774         struct drm_device *dev = crtc->dev;
6775         drm_i915_private_t *dev_priv = dev->dev_private;
6776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777         int pipe = intel_crtc->pipe;
6778         int dpll_reg = DPLL(pipe);
6779         int dpll;
6780
6781         if (HAS_PCH_SPLIT(dev))
6782                 return;
6783
6784         if (!dev_priv->lvds_downclock_avail)
6785                 return;
6786
6787         dpll = I915_READ(dpll_reg);
6788         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6789                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6790
6791                 assert_panel_unlocked(dev_priv, pipe);
6792
6793                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6794                 I915_WRITE(dpll_reg, dpll);
6795                 intel_wait_for_vblank(dev, pipe);
6796
6797                 dpll = I915_READ(dpll_reg);
6798                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6799                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6800         }
6801 }
6802
6803 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6804 {
6805         struct drm_device *dev = crtc->dev;
6806         drm_i915_private_t *dev_priv = dev->dev_private;
6807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808
6809         if (HAS_PCH_SPLIT(dev))
6810                 return;
6811
6812         if (!dev_priv->lvds_downclock_avail)
6813                 return;
6814
6815         /*
6816          * Since this is called by a timer, we should never get here in
6817          * the manual case.
6818          */
6819         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6820                 int pipe = intel_crtc->pipe;
6821                 int dpll_reg = DPLL(pipe);
6822                 int dpll;
6823
6824                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6825
6826                 assert_panel_unlocked(dev_priv, pipe);
6827
6828                 dpll = I915_READ(dpll_reg);
6829                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6830                 I915_WRITE(dpll_reg, dpll);
6831                 intel_wait_for_vblank(dev, pipe);
6832                 dpll = I915_READ(dpll_reg);
6833                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6834                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6835         }
6836
6837 }
6838
6839 void intel_mark_busy(struct drm_device *dev)
6840 {
6841         i915_update_gfx_val(dev->dev_private);
6842 }
6843
6844 void intel_mark_idle(struct drm_device *dev)
6845 {
6846 }
6847
6848 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6849 {
6850         struct drm_device *dev = obj->base.dev;
6851         struct drm_crtc *crtc;
6852
6853         if (!i915_powersave)
6854                 return;
6855
6856         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6857                 if (!crtc->fb)
6858                         continue;
6859
6860                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6861                         intel_increase_pllclock(crtc);
6862         }
6863 }
6864
6865 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6866 {
6867         struct drm_device *dev = obj->base.dev;
6868         struct drm_crtc *crtc;
6869
6870         if (!i915_powersave)
6871                 return;
6872
6873         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6874                 if (!crtc->fb)
6875                         continue;
6876
6877                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6878                         intel_decrease_pllclock(crtc);
6879         }
6880 }
6881
6882 static void intel_crtc_destroy(struct drm_crtc *crtc)
6883 {
6884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885         struct drm_device *dev = crtc->dev;
6886         struct intel_unpin_work *work;
6887         unsigned long flags;
6888
6889         spin_lock_irqsave(&dev->event_lock, flags);
6890         work = intel_crtc->unpin_work;
6891         intel_crtc->unpin_work = NULL;
6892         spin_unlock_irqrestore(&dev->event_lock, flags);
6893
6894         if (work) {
6895                 cancel_work_sync(&work->work);
6896                 kfree(work);
6897         }
6898
6899         drm_crtc_cleanup(crtc);
6900
6901         kfree(intel_crtc);
6902 }
6903
6904 static void intel_unpin_work_fn(struct work_struct *__work)
6905 {
6906         struct intel_unpin_work *work =
6907                 container_of(__work, struct intel_unpin_work, work);
6908
6909         mutex_lock(&work->dev->struct_mutex);
6910         intel_unpin_fb_obj(work->old_fb_obj);
6911         drm_gem_object_unreference(&work->pending_flip_obj->base);
6912         drm_gem_object_unreference(&work->old_fb_obj->base);
6913
6914         intel_update_fbc(work->dev);
6915         mutex_unlock(&work->dev->struct_mutex);
6916         kfree(work);
6917 }
6918
6919 static void do_intel_finish_page_flip(struct drm_device *dev,
6920                                       struct drm_crtc *crtc)
6921 {
6922         drm_i915_private_t *dev_priv = dev->dev_private;
6923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924         struct intel_unpin_work *work;
6925         struct drm_i915_gem_object *obj;
6926         struct drm_pending_vblank_event *e;
6927         struct timeval tvbl;
6928         unsigned long flags;
6929
6930         /* Ignore early vblank irqs */
6931         if (intel_crtc == NULL)
6932                 return;
6933
6934         spin_lock_irqsave(&dev->event_lock, flags);
6935         work = intel_crtc->unpin_work;
6936         if (work == NULL || !work->pending) {
6937                 spin_unlock_irqrestore(&dev->event_lock, flags);
6938                 return;
6939         }
6940
6941         intel_crtc->unpin_work = NULL;
6942
6943         if (work->event) {
6944                 e = work->event;
6945                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6946
6947                 e->event.tv_sec = tvbl.tv_sec;
6948                 e->event.tv_usec = tvbl.tv_usec;
6949
6950                 list_add_tail(&e->base.link,
6951                               &e->base.file_priv->event_list);
6952                 wake_up_interruptible(&e->base.file_priv->event_wait);
6953         }
6954
6955         drm_vblank_put(dev, intel_crtc->pipe);
6956
6957         spin_unlock_irqrestore(&dev->event_lock, flags);
6958
6959         obj = work->old_fb_obj;
6960
6961         atomic_clear_mask(1 << intel_crtc->plane,
6962                           &obj->pending_flip.counter);
6963
6964         wake_up(&dev_priv->pending_flip_queue);
6965         schedule_work(&work->work);
6966
6967         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6968 }
6969
6970 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6971 {
6972         drm_i915_private_t *dev_priv = dev->dev_private;
6973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6974
6975         do_intel_finish_page_flip(dev, crtc);
6976 }
6977
6978 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6979 {
6980         drm_i915_private_t *dev_priv = dev->dev_private;
6981         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6982
6983         do_intel_finish_page_flip(dev, crtc);
6984 }
6985
6986 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6987 {
6988         drm_i915_private_t *dev_priv = dev->dev_private;
6989         struct intel_crtc *intel_crtc =
6990                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6991         unsigned long flags;
6992
6993         spin_lock_irqsave(&dev->event_lock, flags);
6994         if (intel_crtc->unpin_work) {
6995                 if ((++intel_crtc->unpin_work->pending) > 1)
6996                         DRM_ERROR("Prepared flip multiple times\n");
6997         } else {
6998                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6999         }
7000         spin_unlock_irqrestore(&dev->event_lock, flags);
7001 }
7002
7003 static int intel_gen2_queue_flip(struct drm_device *dev,
7004                                  struct drm_crtc *crtc,
7005                                  struct drm_framebuffer *fb,
7006                                  struct drm_i915_gem_object *obj)
7007 {
7008         struct drm_i915_private *dev_priv = dev->dev_private;
7009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7010         u32 flip_mask;
7011         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7012         int ret;
7013
7014         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7015         if (ret)
7016                 goto err;
7017
7018         ret = intel_ring_begin(ring, 6);
7019         if (ret)
7020                 goto err_unpin;
7021
7022         /* Can't queue multiple flips, so wait for the previous
7023          * one to finish before executing the next.
7024          */
7025         if (intel_crtc->plane)
7026                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7027         else
7028                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7029         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7030         intel_ring_emit(ring, MI_NOOP);
7031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7033         intel_ring_emit(ring, fb->pitches[0]);
7034         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7035         intel_ring_emit(ring, 0); /* aux display base address, unused */
7036         intel_ring_advance(ring);
7037         return 0;
7038
7039 err_unpin:
7040         intel_unpin_fb_obj(obj);
7041 err:
7042         return ret;
7043 }
7044
7045 static int intel_gen3_queue_flip(struct drm_device *dev,
7046                                  struct drm_crtc *crtc,
7047                                  struct drm_framebuffer *fb,
7048                                  struct drm_i915_gem_object *obj)
7049 {
7050         struct drm_i915_private *dev_priv = dev->dev_private;
7051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7052         u32 flip_mask;
7053         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7054         int ret;
7055
7056         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7057         if (ret)
7058                 goto err;
7059
7060         ret = intel_ring_begin(ring, 6);
7061         if (ret)
7062                 goto err_unpin;
7063
7064         if (intel_crtc->plane)
7065                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7066         else
7067                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7068         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7069         intel_ring_emit(ring, MI_NOOP);
7070         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7071                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7072         intel_ring_emit(ring, fb->pitches[0]);
7073         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7074         intel_ring_emit(ring, MI_NOOP);
7075
7076         intel_ring_advance(ring);
7077         return 0;
7078
7079 err_unpin:
7080         intel_unpin_fb_obj(obj);
7081 err:
7082         return ret;
7083 }
7084
7085 static int intel_gen4_queue_flip(struct drm_device *dev,
7086                                  struct drm_crtc *crtc,
7087                                  struct drm_framebuffer *fb,
7088                                  struct drm_i915_gem_object *obj)
7089 {
7090         struct drm_i915_private *dev_priv = dev->dev_private;
7091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092         uint32_t pf, pipesrc;
7093         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7094         int ret;
7095
7096         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7097         if (ret)
7098                 goto err;
7099
7100         ret = intel_ring_begin(ring, 4);
7101         if (ret)
7102                 goto err_unpin;
7103
7104         /* i965+ uses the linear or tiled offsets from the
7105          * Display Registers (which do not change across a page-flip)
7106          * so we need only reprogram the base address.
7107          */
7108         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7109                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7110         intel_ring_emit(ring, fb->pitches[0]);
7111         intel_ring_emit(ring,
7112                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7113                         obj->tiling_mode);
7114
7115         /* XXX Enabling the panel-fitter across page-flip is so far
7116          * untested on non-native modes, so ignore it for now.
7117          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7118          */
7119         pf = 0;
7120         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7121         intel_ring_emit(ring, pf | pipesrc);
7122         intel_ring_advance(ring);
7123         return 0;
7124
7125 err_unpin:
7126         intel_unpin_fb_obj(obj);
7127 err:
7128         return ret;
7129 }
7130
7131 static int intel_gen6_queue_flip(struct drm_device *dev,
7132                                  struct drm_crtc *crtc,
7133                                  struct drm_framebuffer *fb,
7134                                  struct drm_i915_gem_object *obj)
7135 {
7136         struct drm_i915_private *dev_priv = dev->dev_private;
7137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7139         uint32_t pf, pipesrc;
7140         int ret;
7141
7142         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7143         if (ret)
7144                 goto err;
7145
7146         ret = intel_ring_begin(ring, 4);
7147         if (ret)
7148                 goto err_unpin;
7149
7150         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7151                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7152         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7153         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7154
7155         /* Contrary to the suggestions in the documentation,
7156          * "Enable Panel Fitter" does not seem to be required when page
7157          * flipping with a non-native mode, and worse causes a normal
7158          * modeset to fail.
7159          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7160          */
7161         pf = 0;
7162         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7163         intel_ring_emit(ring, pf | pipesrc);
7164         intel_ring_advance(ring);
7165         return 0;
7166
7167 err_unpin:
7168         intel_unpin_fb_obj(obj);
7169 err:
7170         return ret;
7171 }
7172
7173 /*
7174  * On gen7 we currently use the blit ring because (in early silicon at least)
7175  * the render ring doesn't give us interrpts for page flip completion, which
7176  * means clients will hang after the first flip is queued.  Fortunately the
7177  * blit ring generates interrupts properly, so use it instead.
7178  */
7179 static int intel_gen7_queue_flip(struct drm_device *dev,
7180                                  struct drm_crtc *crtc,
7181                                  struct drm_framebuffer *fb,
7182                                  struct drm_i915_gem_object *obj)
7183 {
7184         struct drm_i915_private *dev_priv = dev->dev_private;
7185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7187         uint32_t plane_bit = 0;
7188         int ret;
7189
7190         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7191         if (ret)
7192                 goto err;
7193
7194         switch(intel_crtc->plane) {
7195         case PLANE_A:
7196                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7197                 break;
7198         case PLANE_B:
7199                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7200                 break;
7201         case PLANE_C:
7202                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7203                 break;
7204         default:
7205                 WARN_ONCE(1, "unknown plane in flip command\n");
7206                 ret = -ENODEV;
7207                 goto err_unpin;
7208         }
7209
7210         ret = intel_ring_begin(ring, 4);
7211         if (ret)
7212                 goto err_unpin;
7213
7214         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7215         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7216         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7217         intel_ring_emit(ring, (MI_NOOP));
7218         intel_ring_advance(ring);
7219         return 0;
7220
7221 err_unpin:
7222         intel_unpin_fb_obj(obj);
7223 err:
7224         return ret;
7225 }
7226
7227 static int intel_default_queue_flip(struct drm_device *dev,
7228                                     struct drm_crtc *crtc,
7229                                     struct drm_framebuffer *fb,
7230                                     struct drm_i915_gem_object *obj)
7231 {
7232         return -ENODEV;
7233 }
7234
7235 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7236                                 struct drm_framebuffer *fb,
7237                                 struct drm_pending_vblank_event *event)
7238 {
7239         struct drm_device *dev = crtc->dev;
7240         struct drm_i915_private *dev_priv = dev->dev_private;
7241         struct intel_framebuffer *intel_fb;
7242         struct drm_i915_gem_object *obj;
7243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244         struct intel_unpin_work *work;
7245         unsigned long flags;
7246         int ret;
7247
7248         /* Can't change pixel format via MI display flips. */
7249         if (fb->pixel_format != crtc->fb->pixel_format)
7250                 return -EINVAL;
7251
7252         /*
7253          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7254          * Note that pitch changes could also affect these register.
7255          */
7256         if (INTEL_INFO(dev)->gen > 3 &&
7257             (fb->offsets[0] != crtc->fb->offsets[0] ||
7258              fb->pitches[0] != crtc->fb->pitches[0]))
7259                 return -EINVAL;
7260
7261         work = kzalloc(sizeof *work, GFP_KERNEL);
7262         if (work == NULL)
7263                 return -ENOMEM;
7264
7265         work->event = event;
7266         work->dev = crtc->dev;
7267         intel_fb = to_intel_framebuffer(crtc->fb);
7268         work->old_fb_obj = intel_fb->obj;
7269         INIT_WORK(&work->work, intel_unpin_work_fn);
7270
7271         ret = drm_vblank_get(dev, intel_crtc->pipe);
7272         if (ret)
7273                 goto free_work;
7274
7275         /* We borrow the event spin lock for protecting unpin_work */
7276         spin_lock_irqsave(&dev->event_lock, flags);
7277         if (intel_crtc->unpin_work) {
7278                 spin_unlock_irqrestore(&dev->event_lock, flags);
7279                 kfree(work);
7280                 drm_vblank_put(dev, intel_crtc->pipe);
7281
7282                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7283                 return -EBUSY;
7284         }
7285         intel_crtc->unpin_work = work;
7286         spin_unlock_irqrestore(&dev->event_lock, flags);
7287
7288         intel_fb = to_intel_framebuffer(fb);
7289         obj = intel_fb->obj;
7290
7291         ret = i915_mutex_lock_interruptible(dev);
7292         if (ret)
7293                 goto cleanup;
7294
7295         /* Reference the objects for the scheduled work. */
7296         drm_gem_object_reference(&work->old_fb_obj->base);
7297         drm_gem_object_reference(&obj->base);
7298
7299         crtc->fb = fb;
7300
7301         work->pending_flip_obj = obj;
7302
7303         work->enable_stall_check = true;
7304
7305         /* Block clients from rendering to the new back buffer until
7306          * the flip occurs and the object is no longer visible.
7307          */
7308         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7309
7310         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7311         if (ret)
7312                 goto cleanup_pending;
7313
7314         intel_disable_fbc(dev);
7315         intel_mark_fb_busy(obj);
7316         mutex_unlock(&dev->struct_mutex);
7317
7318         trace_i915_flip_request(intel_crtc->plane, obj);
7319
7320         return 0;
7321
7322 cleanup_pending:
7323         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7324         drm_gem_object_unreference(&work->old_fb_obj->base);
7325         drm_gem_object_unreference(&obj->base);
7326         mutex_unlock(&dev->struct_mutex);
7327
7328 cleanup:
7329         spin_lock_irqsave(&dev->event_lock, flags);
7330         intel_crtc->unpin_work = NULL;
7331         spin_unlock_irqrestore(&dev->event_lock, flags);
7332
7333         drm_vblank_put(dev, intel_crtc->pipe);
7334 free_work:
7335         kfree(work);
7336
7337         return ret;
7338 }
7339
7340 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7341         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7342         .load_lut = intel_crtc_load_lut,
7343         .disable = intel_crtc_noop,
7344 };
7345
7346 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7347 {
7348         struct intel_encoder *other_encoder;
7349         struct drm_crtc *crtc = &encoder->new_crtc->base;
7350
7351         if (WARN_ON(!crtc))
7352                 return false;
7353
7354         list_for_each_entry(other_encoder,
7355                             &crtc->dev->mode_config.encoder_list,
7356                             base.head) {
7357
7358                 if (&other_encoder->new_crtc->base != crtc ||
7359                     encoder == other_encoder)
7360                         continue;
7361                 else
7362                         return true;
7363         }
7364
7365         return false;
7366 }
7367
7368 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7369                                   struct drm_crtc *crtc)
7370 {
7371         struct drm_device *dev;
7372         struct drm_crtc *tmp;
7373         int crtc_mask = 1;
7374
7375         WARN(!crtc, "checking null crtc?\n");
7376
7377         dev = crtc->dev;
7378
7379         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7380                 if (tmp == crtc)
7381                         break;
7382                 crtc_mask <<= 1;
7383         }
7384
7385         if (encoder->possible_crtcs & crtc_mask)
7386                 return true;
7387         return false;
7388 }
7389
7390 /**
7391  * intel_modeset_update_staged_output_state
7392  *
7393  * Updates the staged output configuration state, e.g. after we've read out the
7394  * current hw state.
7395  */
7396 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7397 {
7398         struct intel_encoder *encoder;
7399         struct intel_connector *connector;
7400
7401         list_for_each_entry(connector, &dev->mode_config.connector_list,
7402                             base.head) {
7403                 connector->new_encoder =
7404                         to_intel_encoder(connector->base.encoder);
7405         }
7406
7407         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7408                             base.head) {
7409                 encoder->new_crtc =
7410                         to_intel_crtc(encoder->base.crtc);
7411         }
7412 }
7413
7414 /**
7415  * intel_modeset_commit_output_state
7416  *
7417  * This function copies the stage display pipe configuration to the real one.
7418  */
7419 static void intel_modeset_commit_output_state(struct drm_device *dev)
7420 {
7421         struct intel_encoder *encoder;
7422         struct intel_connector *connector;
7423
7424         list_for_each_entry(connector, &dev->mode_config.connector_list,
7425                             base.head) {
7426                 connector->base.encoder = &connector->new_encoder->base;
7427         }
7428
7429         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7430                             base.head) {
7431                 encoder->base.crtc = &encoder->new_crtc->base;
7432         }
7433 }
7434
7435 static struct drm_display_mode *
7436 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7437                             struct drm_display_mode *mode)
7438 {
7439         struct drm_device *dev = crtc->dev;
7440         struct drm_display_mode *adjusted_mode;
7441         struct drm_encoder_helper_funcs *encoder_funcs;
7442         struct intel_encoder *encoder;
7443
7444         adjusted_mode = drm_mode_duplicate(dev, mode);
7445         if (!adjusted_mode)
7446                 return ERR_PTR(-ENOMEM);
7447
7448         /* Pass our mode to the connectors and the CRTC to give them a chance to
7449          * adjust it according to limitations or connector properties, and also
7450          * a chance to reject the mode entirely.
7451          */
7452         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7453                             base.head) {
7454
7455                 if (&encoder->new_crtc->base != crtc)
7456                         continue;
7457                 encoder_funcs = encoder->base.helper_private;
7458                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7459                                                 adjusted_mode))) {
7460                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7461                         goto fail;
7462                 }
7463         }
7464
7465         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7466                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7467                 goto fail;
7468         }
7469         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7470
7471         return adjusted_mode;
7472 fail:
7473         drm_mode_destroy(dev, adjusted_mode);
7474         return ERR_PTR(-EINVAL);
7475 }
7476
7477 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7478  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7479 static void
7480 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7481                              unsigned *prepare_pipes, unsigned *disable_pipes)
7482 {
7483         struct intel_crtc *intel_crtc;
7484         struct drm_device *dev = crtc->dev;
7485         struct intel_encoder *encoder;
7486         struct intel_connector *connector;
7487         struct drm_crtc *tmp_crtc;
7488
7489         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7490
7491         /* Check which crtcs have changed outputs connected to them, these need
7492          * to be part of the prepare_pipes mask. We don't (yet) support global
7493          * modeset across multiple crtcs, so modeset_pipes will only have one
7494          * bit set at most. */
7495         list_for_each_entry(connector, &dev->mode_config.connector_list,
7496                             base.head) {
7497                 if (connector->base.encoder == &connector->new_encoder->base)
7498                         continue;
7499
7500                 if (connector->base.encoder) {
7501                         tmp_crtc = connector->base.encoder->crtc;
7502
7503                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7504                 }
7505
7506                 if (connector->new_encoder)
7507                         *prepare_pipes |=
7508                                 1 << connector->new_encoder->new_crtc->pipe;
7509         }
7510
7511         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7512                             base.head) {
7513                 if (encoder->base.crtc == &encoder->new_crtc->base)
7514                         continue;
7515
7516                 if (encoder->base.crtc) {
7517                         tmp_crtc = encoder->base.crtc;
7518
7519                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7520                 }
7521
7522                 if (encoder->new_crtc)
7523                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7524         }
7525
7526         /* Check for any pipes that will be fully disabled ... */
7527         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7528                             base.head) {
7529                 bool used = false;
7530
7531                 /* Don't try to disable disabled crtcs. */
7532                 if (!intel_crtc->base.enabled)
7533                         continue;
7534
7535                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7536                                     base.head) {
7537                         if (encoder->new_crtc == intel_crtc)
7538                                 used = true;
7539                 }
7540
7541                 if (!used)
7542                         *disable_pipes |= 1 << intel_crtc->pipe;
7543         }
7544
7545
7546         /* set_mode is also used to update properties on life display pipes. */
7547         intel_crtc = to_intel_crtc(crtc);
7548         if (crtc->enabled)
7549                 *prepare_pipes |= 1 << intel_crtc->pipe;
7550
7551         /* We only support modeset on one single crtc, hence we need to do that
7552          * only for the passed in crtc iff we change anything else than just
7553          * disable crtcs.
7554          *
7555          * This is actually not true, to be fully compatible with the old crtc
7556          * helper we automatically disable _any_ output (i.e. doesn't need to be
7557          * connected to the crtc we're modesetting on) if it's disconnected.
7558          * Which is a rather nutty api (since changed the output configuration
7559          * without userspace's explicit request can lead to confusion), but
7560          * alas. Hence we currently need to modeset on all pipes we prepare. */
7561         if (*prepare_pipes)
7562                 *modeset_pipes = *prepare_pipes;
7563
7564         /* ... and mask these out. */
7565         *modeset_pipes &= ~(*disable_pipes);
7566         *prepare_pipes &= ~(*disable_pipes);
7567 }
7568
7569 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7570 {
7571         struct drm_encoder *encoder;
7572         struct drm_device *dev = crtc->dev;
7573
7574         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7575                 if (encoder->crtc == crtc)
7576                         return true;
7577
7578         return false;
7579 }
7580
7581 static void
7582 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7583 {
7584         struct intel_encoder *intel_encoder;
7585         struct intel_crtc *intel_crtc;
7586         struct drm_connector *connector;
7587
7588         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7589                             base.head) {
7590                 if (!intel_encoder->base.crtc)
7591                         continue;
7592
7593                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7594
7595                 if (prepare_pipes & (1 << intel_crtc->pipe))
7596                         intel_encoder->connectors_active = false;
7597         }
7598
7599         intel_modeset_commit_output_state(dev);
7600
7601         /* Update computed state. */
7602         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7603                             base.head) {
7604                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7605         }
7606
7607         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7608                 if (!connector->encoder || !connector->encoder->crtc)
7609                         continue;
7610
7611                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7612
7613                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7614                         struct drm_property *dpms_property =
7615                                 dev->mode_config.dpms_property;
7616
7617                         connector->dpms = DRM_MODE_DPMS_ON;
7618                         drm_connector_property_set_value(connector,
7619                                                          dpms_property,
7620                                                          DRM_MODE_DPMS_ON);
7621
7622                         intel_encoder = to_intel_encoder(connector->encoder);
7623                         intel_encoder->connectors_active = true;
7624                 }
7625         }
7626
7627 }
7628
7629 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7630         list_for_each_entry((intel_crtc), \
7631                             &(dev)->mode_config.crtc_list, \
7632                             base.head) \
7633                 if (mask & (1 <<(intel_crtc)->pipe)) \
7634
7635 void
7636 intel_modeset_check_state(struct drm_device *dev)
7637 {
7638         struct intel_crtc *crtc;
7639         struct intel_encoder *encoder;
7640         struct intel_connector *connector;
7641
7642         list_for_each_entry(connector, &dev->mode_config.connector_list,
7643                             base.head) {
7644                 /* This also checks the encoder/connector hw state with the
7645                  * ->get_hw_state callbacks. */
7646                 intel_connector_check_state(connector);
7647
7648                 WARN(&connector->new_encoder->base != connector->base.encoder,
7649                      "connector's staged encoder doesn't match current encoder\n");
7650         }
7651
7652         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7653                             base.head) {
7654                 bool enabled = false;
7655                 bool active = false;
7656                 enum pipe pipe, tracked_pipe;
7657
7658                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7659                               encoder->base.base.id,
7660                               drm_get_encoder_name(&encoder->base));
7661
7662                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7663                      "encoder's stage crtc doesn't match current crtc\n");
7664                 WARN(encoder->connectors_active && !encoder->base.crtc,
7665                      "encoder's active_connectors set, but no crtc\n");
7666
7667                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7668                                     base.head) {
7669                         if (connector->base.encoder != &encoder->base)
7670                                 continue;
7671                         enabled = true;
7672                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7673                                 active = true;
7674                 }
7675                 WARN(!!encoder->base.crtc != enabled,
7676                      "encoder's enabled state mismatch "
7677                      "(expected %i, found %i)\n",
7678                      !!encoder->base.crtc, enabled);
7679                 WARN(active && !encoder->base.crtc,
7680                      "active encoder with no crtc\n");
7681
7682                 WARN(encoder->connectors_active != active,
7683                      "encoder's computed active state doesn't match tracked active state "
7684                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7685
7686                 active = encoder->get_hw_state(encoder, &pipe);
7687                 WARN(active != encoder->connectors_active,
7688                      "encoder's hw state doesn't match sw tracking "
7689                      "(expected %i, found %i)\n",
7690                      encoder->connectors_active, active);
7691
7692                 if (!encoder->base.crtc)
7693                         continue;
7694
7695                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7696                 WARN(active && pipe != tracked_pipe,
7697                      "active encoder's pipe doesn't match"
7698                      "(expected %i, found %i)\n",
7699                      tracked_pipe, pipe);
7700
7701         }
7702
7703         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7704                             base.head) {
7705                 bool enabled = false;
7706                 bool active = false;
7707
7708                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7709                               crtc->base.base.id);
7710
7711                 WARN(crtc->active && !crtc->base.enabled,
7712                      "active crtc, but not enabled in sw tracking\n");
7713
7714                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7715                                     base.head) {
7716                         if (encoder->base.crtc != &crtc->base)
7717                                 continue;
7718                         enabled = true;
7719                         if (encoder->connectors_active)
7720                                 active = true;
7721                 }
7722                 WARN(active != crtc->active,
7723                      "crtc's computed active state doesn't match tracked active state "
7724                      "(expected %i, found %i)\n", active, crtc->active);
7725                 WARN(enabled != crtc->base.enabled,
7726                      "crtc's computed enabled state doesn't match tracked enabled state "
7727                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7728
7729                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7730         }
7731 }
7732
7733 bool intel_set_mode(struct drm_crtc *crtc,
7734                     struct drm_display_mode *mode,
7735                     int x, int y, struct drm_framebuffer *fb)
7736 {
7737         struct drm_device *dev = crtc->dev;
7738         drm_i915_private_t *dev_priv = dev->dev_private;
7739         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7740         struct intel_crtc *intel_crtc;
7741         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7742         bool ret = true;
7743
7744         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7745                                      &prepare_pipes, &disable_pipes);
7746
7747         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7748                       modeset_pipes, prepare_pipes, disable_pipes);
7749
7750         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7751                 intel_crtc_disable(&intel_crtc->base);
7752
7753         saved_hwmode = crtc->hwmode;
7754         saved_mode = crtc->mode;
7755
7756         /* Hack: Because we don't (yet) support global modeset on multiple
7757          * crtcs, we don't keep track of the new mode for more than one crtc.
7758          * Hence simply check whether any bit is set in modeset_pipes in all the
7759          * pieces of code that are not yet converted to deal with mutliple crtcs
7760          * changing their mode at the same time. */
7761         adjusted_mode = NULL;
7762         if (modeset_pipes) {
7763                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7764                 if (IS_ERR(adjusted_mode)) {
7765                         return false;
7766                 }
7767         }
7768
7769         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7770                 if (intel_crtc->base.enabled)
7771                         dev_priv->display.crtc_disable(&intel_crtc->base);
7772         }
7773
7774         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7775          * to set it here already despite that we pass it down the callchain.
7776          */
7777         if (modeset_pipes)
7778                 crtc->mode = *mode;
7779
7780         /* Only after disabling all output pipelines that will be changed can we
7781          * update the the output configuration. */
7782         intel_modeset_update_state(dev, prepare_pipes);
7783
7784         if (dev_priv->display.modeset_global_resources)
7785                 dev_priv->display.modeset_global_resources(dev);
7786
7787         /* Set up the DPLL and any encoders state that needs to adjust or depend
7788          * on the DPLL.
7789          */
7790         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7791                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7792                                            mode, adjusted_mode,
7793                                            x, y, fb);
7794                 if (!ret)
7795                     goto done;
7796         }
7797
7798         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7799         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7800                 dev_priv->display.crtc_enable(&intel_crtc->base);
7801
7802         if (modeset_pipes) {
7803                 /* Store real post-adjustment hardware mode. */
7804                 crtc->hwmode = *adjusted_mode;
7805
7806                 /* Calculate and store various constants which
7807                  * are later needed by vblank and swap-completion
7808                  * timestamping. They are derived from true hwmode.
7809                  */
7810                 drm_calc_timestamping_constants(crtc);
7811         }
7812
7813         /* FIXME: add subpixel order */
7814 done:
7815         drm_mode_destroy(dev, adjusted_mode);
7816         if (!ret && crtc->enabled) {
7817                 crtc->hwmode = saved_hwmode;
7818                 crtc->mode = saved_mode;
7819         } else {
7820                 intel_modeset_check_state(dev);
7821         }
7822
7823         return ret;
7824 }
7825
7826 #undef for_each_intel_crtc_masked
7827
7828 static void intel_set_config_free(struct intel_set_config *config)
7829 {
7830         if (!config)
7831                 return;
7832
7833         kfree(config->save_connector_encoders);
7834         kfree(config->save_encoder_crtcs);
7835         kfree(config);
7836 }
7837
7838 static int intel_set_config_save_state(struct drm_device *dev,
7839                                        struct intel_set_config *config)
7840 {
7841         struct drm_encoder *encoder;
7842         struct drm_connector *connector;
7843         int count;
7844
7845         config->save_encoder_crtcs =
7846                 kcalloc(dev->mode_config.num_encoder,
7847                         sizeof(struct drm_crtc *), GFP_KERNEL);
7848         if (!config->save_encoder_crtcs)
7849                 return -ENOMEM;
7850
7851         config->save_connector_encoders =
7852                 kcalloc(dev->mode_config.num_connector,
7853                         sizeof(struct drm_encoder *), GFP_KERNEL);
7854         if (!config->save_connector_encoders)
7855                 return -ENOMEM;
7856
7857         /* Copy data. Note that driver private data is not affected.
7858          * Should anything bad happen only the expected state is
7859          * restored, not the drivers personal bookkeeping.
7860          */
7861         count = 0;
7862         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7863                 config->save_encoder_crtcs[count++] = encoder->crtc;
7864         }
7865
7866         count = 0;
7867         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7868                 config->save_connector_encoders[count++] = connector->encoder;
7869         }
7870
7871         return 0;
7872 }
7873
7874 static void intel_set_config_restore_state(struct drm_device *dev,
7875                                            struct intel_set_config *config)
7876 {
7877         struct intel_encoder *encoder;
7878         struct intel_connector *connector;
7879         int count;
7880
7881         count = 0;
7882         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7883                 encoder->new_crtc =
7884                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7885         }
7886
7887         count = 0;
7888         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7889                 connector->new_encoder =
7890                         to_intel_encoder(config->save_connector_encoders[count++]);
7891         }
7892 }
7893
7894 static void
7895 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7896                                       struct intel_set_config *config)
7897 {
7898
7899         /* We should be able to check here if the fb has the same properties
7900          * and then just flip_or_move it */
7901         if (set->crtc->fb != set->fb) {
7902                 /* If we have no fb then treat it as a full mode set */
7903                 if (set->crtc->fb == NULL) {
7904                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7905                         config->mode_changed = true;
7906                 } else if (set->fb == NULL) {
7907                         config->mode_changed = true;
7908                 } else if (set->fb->depth != set->crtc->fb->depth) {
7909                         config->mode_changed = true;
7910                 } else if (set->fb->bits_per_pixel !=
7911                            set->crtc->fb->bits_per_pixel) {
7912                         config->mode_changed = true;
7913                 } else
7914                         config->fb_changed = true;
7915         }
7916
7917         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7918                 config->fb_changed = true;
7919
7920         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7921                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7922                 drm_mode_debug_printmodeline(&set->crtc->mode);
7923                 drm_mode_debug_printmodeline(set->mode);
7924                 config->mode_changed = true;
7925         }
7926 }
7927
7928 static int
7929 intel_modeset_stage_output_state(struct drm_device *dev,
7930                                  struct drm_mode_set *set,
7931                                  struct intel_set_config *config)
7932 {
7933         struct drm_crtc *new_crtc;
7934         struct intel_connector *connector;
7935         struct intel_encoder *encoder;
7936         int count, ro;
7937
7938         /* The upper layers ensure that we either disabl a crtc or have a list
7939          * of connectors. For paranoia, double-check this. */
7940         WARN_ON(!set->fb && (set->num_connectors != 0));
7941         WARN_ON(set->fb && (set->num_connectors == 0));
7942
7943         count = 0;
7944         list_for_each_entry(connector, &dev->mode_config.connector_list,
7945                             base.head) {
7946                 /* Otherwise traverse passed in connector list and get encoders
7947                  * for them. */
7948                 for (ro = 0; ro < set->num_connectors; ro++) {
7949                         if (set->connectors[ro] == &connector->base) {
7950                                 connector->new_encoder = connector->encoder;
7951                                 break;
7952                         }
7953                 }
7954
7955                 /* If we disable the crtc, disable all its connectors. Also, if
7956                  * the connector is on the changing crtc but not on the new
7957                  * connector list, disable it. */
7958                 if ((!set->fb || ro == set->num_connectors) &&
7959                     connector->base.encoder &&
7960                     connector->base.encoder->crtc == set->crtc) {
7961                         connector->new_encoder = NULL;
7962
7963                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7964                                 connector->base.base.id,
7965                                 drm_get_connector_name(&connector->base));
7966                 }
7967
7968
7969                 if (&connector->new_encoder->base != connector->base.encoder) {
7970                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7971                         config->mode_changed = true;
7972                 }
7973
7974                 /* Disable all disconnected encoders. */
7975                 if (connector->base.status == connector_status_disconnected)
7976                         connector->new_encoder = NULL;
7977         }
7978         /* connector->new_encoder is now updated for all connectors. */
7979
7980         /* Update crtc of enabled connectors. */
7981         count = 0;
7982         list_for_each_entry(connector, &dev->mode_config.connector_list,
7983                             base.head) {
7984                 if (!connector->new_encoder)
7985                         continue;
7986
7987                 new_crtc = connector->new_encoder->base.crtc;
7988
7989                 for (ro = 0; ro < set->num_connectors; ro++) {
7990                         if (set->connectors[ro] == &connector->base)
7991                                 new_crtc = set->crtc;
7992                 }
7993
7994                 /* Make sure the new CRTC will work with the encoder */
7995                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7996                                            new_crtc)) {
7997                         return -EINVAL;
7998                 }
7999                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8000
8001                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8002                         connector->base.base.id,
8003                         drm_get_connector_name(&connector->base),
8004                         new_crtc->base.id);
8005         }
8006
8007         /* Check for any encoders that needs to be disabled. */
8008         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8009                             base.head) {
8010                 list_for_each_entry(connector,
8011                                     &dev->mode_config.connector_list,
8012                                     base.head) {
8013                         if (connector->new_encoder == encoder) {
8014                                 WARN_ON(!connector->new_encoder->new_crtc);
8015
8016                                 goto next_encoder;
8017                         }
8018                 }
8019                 encoder->new_crtc = NULL;
8020 next_encoder:
8021                 /* Only now check for crtc changes so we don't miss encoders
8022                  * that will be disabled. */
8023                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8024                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8025                         config->mode_changed = true;
8026                 }
8027         }
8028         /* Now we've also updated encoder->new_crtc for all encoders. */
8029
8030         return 0;
8031 }
8032
8033 static int intel_crtc_set_config(struct drm_mode_set *set)
8034 {
8035         struct drm_device *dev;
8036         struct drm_mode_set save_set;
8037         struct intel_set_config *config;
8038         int ret;
8039
8040         BUG_ON(!set);
8041         BUG_ON(!set->crtc);
8042         BUG_ON(!set->crtc->helper_private);
8043
8044         if (!set->mode)
8045                 set->fb = NULL;
8046
8047         /* The fb helper likes to play gross jokes with ->mode_set_config.
8048          * Unfortunately the crtc helper doesn't do much at all for this case,
8049          * so we have to cope with this madness until the fb helper is fixed up. */
8050         if (set->fb && set->num_connectors == 0)
8051                 return 0;
8052
8053         if (set->fb) {
8054                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8055                                 set->crtc->base.id, set->fb->base.id,
8056                                 (int)set->num_connectors, set->x, set->y);
8057         } else {
8058                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8059         }
8060
8061         dev = set->crtc->dev;
8062
8063         ret = -ENOMEM;
8064         config = kzalloc(sizeof(*config), GFP_KERNEL);
8065         if (!config)
8066                 goto out_config;
8067
8068         ret = intel_set_config_save_state(dev, config);
8069         if (ret)
8070                 goto out_config;
8071
8072         save_set.crtc = set->crtc;
8073         save_set.mode = &set->crtc->mode;
8074         save_set.x = set->crtc->x;
8075         save_set.y = set->crtc->y;
8076         save_set.fb = set->crtc->fb;
8077
8078         /* Compute whether we need a full modeset, only an fb base update or no
8079          * change at all. In the future we might also check whether only the
8080          * mode changed, e.g. for LVDS where we only change the panel fitter in
8081          * such cases. */
8082         intel_set_config_compute_mode_changes(set, config);
8083
8084         ret = intel_modeset_stage_output_state(dev, set, config);
8085         if (ret)
8086                 goto fail;
8087
8088         if (config->mode_changed) {
8089                 if (set->mode) {
8090                         DRM_DEBUG_KMS("attempting to set mode from"
8091                                         " userspace\n");
8092                         drm_mode_debug_printmodeline(set->mode);
8093                 }
8094
8095                 if (!intel_set_mode(set->crtc, set->mode,
8096                                     set->x, set->y, set->fb)) {
8097                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8098                                   set->crtc->base.id);
8099                         ret = -EINVAL;
8100                         goto fail;
8101                 }
8102         } else if (config->fb_changed) {
8103                 ret = intel_pipe_set_base(set->crtc,
8104                                           set->x, set->y, set->fb);
8105         }
8106
8107         intel_set_config_free(config);
8108
8109         return 0;
8110
8111 fail:
8112         intel_set_config_restore_state(dev, config);
8113
8114         /* Try to restore the config */
8115         if (config->mode_changed &&
8116             !intel_set_mode(save_set.crtc, save_set.mode,
8117                             save_set.x, save_set.y, save_set.fb))
8118                 DRM_ERROR("failed to restore config after modeset failure\n");
8119
8120 out_config:
8121         intel_set_config_free(config);
8122         return ret;
8123 }
8124
8125 static const struct drm_crtc_funcs intel_crtc_funcs = {
8126         .cursor_set = intel_crtc_cursor_set,
8127         .cursor_move = intel_crtc_cursor_move,
8128         .gamma_set = intel_crtc_gamma_set,
8129         .set_config = intel_crtc_set_config,
8130         .destroy = intel_crtc_destroy,
8131         .page_flip = intel_crtc_page_flip,
8132 };
8133
8134 static void intel_cpu_pll_init(struct drm_device *dev)
8135 {
8136         if (IS_HASWELL(dev))
8137                 intel_ddi_pll_init(dev);
8138 }
8139
8140 static void intel_pch_pll_init(struct drm_device *dev)
8141 {
8142         drm_i915_private_t *dev_priv = dev->dev_private;
8143         int i;
8144
8145         if (dev_priv->num_pch_pll == 0) {
8146                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8147                 return;
8148         }
8149
8150         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8151                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8152                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8153                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8154         }
8155 }
8156
8157 static void intel_crtc_init(struct drm_device *dev, int pipe)
8158 {
8159         drm_i915_private_t *dev_priv = dev->dev_private;
8160         struct intel_crtc *intel_crtc;
8161         int i;
8162
8163         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8164         if (intel_crtc == NULL)
8165                 return;
8166
8167         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8168
8169         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8170         for (i = 0; i < 256; i++) {
8171                 intel_crtc->lut_r[i] = i;
8172                 intel_crtc->lut_g[i] = i;
8173                 intel_crtc->lut_b[i] = i;
8174         }
8175
8176         /* Swap pipes & planes for FBC on pre-965 */
8177         intel_crtc->pipe = pipe;
8178         intel_crtc->plane = pipe;
8179         intel_crtc->cpu_transcoder = pipe;
8180         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8181                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8182                 intel_crtc->plane = !pipe;
8183         }
8184
8185         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8186                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8187         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8188         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8189
8190         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8191
8192         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8193 }
8194
8195 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8196                                 struct drm_file *file)
8197 {
8198         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8199         struct drm_mode_object *drmmode_obj;
8200         struct intel_crtc *crtc;
8201
8202         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8203                 return -ENODEV;
8204
8205         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8206                         DRM_MODE_OBJECT_CRTC);
8207
8208         if (!drmmode_obj) {
8209                 DRM_ERROR("no such CRTC id\n");
8210                 return -EINVAL;
8211         }
8212
8213         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8214         pipe_from_crtc_id->pipe = crtc->pipe;
8215
8216         return 0;
8217 }
8218
8219 static int intel_encoder_clones(struct intel_encoder *encoder)
8220 {
8221         struct drm_device *dev = encoder->base.dev;
8222         struct intel_encoder *source_encoder;
8223         int index_mask = 0;
8224         int entry = 0;
8225
8226         list_for_each_entry(source_encoder,
8227                             &dev->mode_config.encoder_list, base.head) {
8228
8229                 if (encoder == source_encoder)
8230                         index_mask |= (1 << entry);
8231
8232                 /* Intel hw has only one MUX where enocoders could be cloned. */
8233                 if (encoder->cloneable && source_encoder->cloneable)
8234                         index_mask |= (1 << entry);
8235
8236                 entry++;
8237         }
8238
8239         return index_mask;
8240 }
8241
8242 static bool has_edp_a(struct drm_device *dev)
8243 {
8244         struct drm_i915_private *dev_priv = dev->dev_private;
8245
8246         if (!IS_MOBILE(dev))
8247                 return false;
8248
8249         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8250                 return false;
8251
8252         if (IS_GEN5(dev) &&
8253             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8254                 return false;
8255
8256         return true;
8257 }
8258
8259 static void intel_setup_outputs(struct drm_device *dev)
8260 {
8261         struct drm_i915_private *dev_priv = dev->dev_private;
8262         struct intel_encoder *encoder;
8263         bool dpd_is_edp = false;
8264         bool has_lvds;
8265
8266         has_lvds = intel_lvds_init(dev);
8267         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8268                 /* disable the panel fitter on everything but LVDS */
8269                 I915_WRITE(PFIT_CONTROL, 0);
8270         }
8271
8272         if (HAS_PCH_SPLIT(dev)) {
8273                 dpd_is_edp = intel_dpd_is_edp(dev);
8274
8275                 if (has_edp_a(dev))
8276                         intel_dp_init(dev, DP_A, PORT_A);
8277
8278                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8279                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8280         }
8281
8282         intel_crt_init(dev);
8283
8284         if (IS_HASWELL(dev)) {
8285                 int found;
8286
8287                 /* Haswell uses DDI functions to detect digital outputs */
8288                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8289                 /* DDI A only supports eDP */
8290                 if (found)
8291                         intel_ddi_init(dev, PORT_A);
8292
8293                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8294                  * register */
8295                 found = I915_READ(SFUSE_STRAP);
8296
8297                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8298                         intel_ddi_init(dev, PORT_B);
8299                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8300                         intel_ddi_init(dev, PORT_C);
8301                 if (found & SFUSE_STRAP_DDID_DETECTED)
8302                         intel_ddi_init(dev, PORT_D);
8303         } else if (HAS_PCH_SPLIT(dev)) {
8304                 int found;
8305
8306                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8307                         /* PCH SDVOB multiplex with HDMIB */
8308                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8309                         if (!found)
8310                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8311                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8312                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8313                 }
8314
8315                 if (I915_READ(HDMIC) & PORT_DETECTED)
8316                         intel_hdmi_init(dev, HDMIC, PORT_C);
8317
8318                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8319                         intel_hdmi_init(dev, HDMID, PORT_D);
8320
8321                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8322                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8323
8324                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8325                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8326         } else if (IS_VALLEYVIEW(dev)) {
8327                 int found;
8328
8329                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8330                 if (I915_READ(DP_C) & DP_DETECTED)
8331                         intel_dp_init(dev, DP_C, PORT_C);
8332
8333                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8334                         /* SDVOB multiplex with HDMIB */
8335                         found = intel_sdvo_init(dev, SDVOB, true);
8336                         if (!found)
8337                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8338                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8339                                 intel_dp_init(dev, DP_B, PORT_B);
8340                 }
8341
8342                 if (I915_READ(SDVOC) & PORT_DETECTED)
8343                         intel_hdmi_init(dev, SDVOC, PORT_C);
8344
8345         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8346                 bool found = false;
8347
8348                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8349                         DRM_DEBUG_KMS("probing SDVOB\n");
8350                         found = intel_sdvo_init(dev, SDVOB, true);
8351                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8352                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8353                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8354                         }
8355
8356                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8357                                 DRM_DEBUG_KMS("probing DP_B\n");
8358                                 intel_dp_init(dev, DP_B, PORT_B);
8359                         }
8360                 }
8361
8362                 /* Before G4X SDVOC doesn't have its own detect register */
8363
8364                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8365                         DRM_DEBUG_KMS("probing SDVOC\n");
8366                         found = intel_sdvo_init(dev, SDVOC, false);
8367                 }
8368
8369                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8370
8371                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8372                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8373                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8374                         }
8375                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8376                                 DRM_DEBUG_KMS("probing DP_C\n");
8377                                 intel_dp_init(dev, DP_C, PORT_C);
8378                         }
8379                 }
8380
8381                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8382                     (I915_READ(DP_D) & DP_DETECTED)) {
8383                         DRM_DEBUG_KMS("probing DP_D\n");
8384                         intel_dp_init(dev, DP_D, PORT_D);
8385                 }
8386         } else if (IS_GEN2(dev))
8387                 intel_dvo_init(dev);
8388
8389         if (SUPPORTS_TV(dev))
8390                 intel_tv_init(dev);
8391
8392         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8393                 encoder->base.possible_crtcs = encoder->crtc_mask;
8394                 encoder->base.possible_clones =
8395                         intel_encoder_clones(encoder);
8396         }
8397
8398         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8399                 ironlake_init_pch_refclk(dev);
8400 }
8401
8402 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8403 {
8404         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8405
8406         drm_framebuffer_cleanup(fb);
8407         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8408
8409         kfree(intel_fb);
8410 }
8411
8412 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8413                                                 struct drm_file *file,
8414                                                 unsigned int *handle)
8415 {
8416         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8417         struct drm_i915_gem_object *obj = intel_fb->obj;
8418
8419         return drm_gem_handle_create(file, &obj->base, handle);
8420 }
8421
8422 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8423         .destroy = intel_user_framebuffer_destroy,
8424         .create_handle = intel_user_framebuffer_create_handle,
8425 };
8426
8427 int intel_framebuffer_init(struct drm_device *dev,
8428                            struct intel_framebuffer *intel_fb,
8429                            struct drm_mode_fb_cmd2 *mode_cmd,
8430                            struct drm_i915_gem_object *obj)
8431 {
8432         int ret;
8433
8434         if (obj->tiling_mode == I915_TILING_Y)
8435                 return -EINVAL;
8436
8437         if (mode_cmd->pitches[0] & 63)
8438                 return -EINVAL;
8439
8440         /* FIXME <= Gen4 stride limits are bit unclear */
8441         if (mode_cmd->pitches[0] > 32768)
8442                 return -EINVAL;
8443
8444         if (obj->tiling_mode != I915_TILING_NONE &&
8445             mode_cmd->pitches[0] != obj->stride)
8446                 return -EINVAL;
8447
8448         /* Reject formats not supported by any plane early. */
8449         switch (mode_cmd->pixel_format) {
8450         case DRM_FORMAT_C8:
8451         case DRM_FORMAT_RGB565:
8452         case DRM_FORMAT_XRGB8888:
8453         case DRM_FORMAT_ARGB8888:
8454                 break;
8455         case DRM_FORMAT_XRGB1555:
8456         case DRM_FORMAT_ARGB1555:
8457                 if (INTEL_INFO(dev)->gen > 3)
8458                         return -EINVAL;
8459                 break;
8460         case DRM_FORMAT_XBGR8888:
8461         case DRM_FORMAT_ABGR8888:
8462         case DRM_FORMAT_XRGB2101010:
8463         case DRM_FORMAT_ARGB2101010:
8464         case DRM_FORMAT_XBGR2101010:
8465         case DRM_FORMAT_ABGR2101010:
8466                 if (INTEL_INFO(dev)->gen < 4)
8467                         return -EINVAL;
8468                 break;
8469         case DRM_FORMAT_YUYV:
8470         case DRM_FORMAT_UYVY:
8471         case DRM_FORMAT_YVYU:
8472         case DRM_FORMAT_VYUY:
8473                 if (INTEL_INFO(dev)->gen < 6)
8474                         return -EINVAL;
8475                 break;
8476         default:
8477                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8478                 return -EINVAL;
8479         }
8480
8481         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8482         if (mode_cmd->offsets[0] != 0)
8483                 return -EINVAL;
8484
8485         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8486         if (ret) {
8487                 DRM_ERROR("framebuffer init failed %d\n", ret);
8488                 return ret;
8489         }
8490
8491         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8492         intel_fb->obj = obj;
8493         return 0;
8494 }
8495
8496 static struct drm_framebuffer *
8497 intel_user_framebuffer_create(struct drm_device *dev,
8498                               struct drm_file *filp,
8499                               struct drm_mode_fb_cmd2 *mode_cmd)
8500 {
8501         struct drm_i915_gem_object *obj;
8502
8503         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8504                                                 mode_cmd->handles[0]));
8505         if (&obj->base == NULL)
8506                 return ERR_PTR(-ENOENT);
8507
8508         return intel_framebuffer_create(dev, mode_cmd, obj);
8509 }
8510
8511 static const struct drm_mode_config_funcs intel_mode_funcs = {
8512         .fb_create = intel_user_framebuffer_create,
8513         .output_poll_changed = intel_fb_output_poll_changed,
8514 };
8515
8516 /* Set up chip specific display functions */
8517 static void intel_init_display(struct drm_device *dev)
8518 {
8519         struct drm_i915_private *dev_priv = dev->dev_private;
8520
8521         /* We always want a DPMS function */
8522         if (IS_HASWELL(dev)) {
8523                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8524                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8525                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8526                 dev_priv->display.off = haswell_crtc_off;
8527                 dev_priv->display.update_plane = ironlake_update_plane;
8528         } else if (HAS_PCH_SPLIT(dev)) {
8529                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8530                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8531                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8532                 dev_priv->display.off = ironlake_crtc_off;
8533                 dev_priv->display.update_plane = ironlake_update_plane;
8534         } else {
8535                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8536                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8537                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8538                 dev_priv->display.off = i9xx_crtc_off;
8539                 dev_priv->display.update_plane = i9xx_update_plane;
8540         }
8541
8542         /* Returns the core display clock speed */
8543         if (IS_VALLEYVIEW(dev))
8544                 dev_priv->display.get_display_clock_speed =
8545                         valleyview_get_display_clock_speed;
8546         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8547                 dev_priv->display.get_display_clock_speed =
8548                         i945_get_display_clock_speed;
8549         else if (IS_I915G(dev))
8550                 dev_priv->display.get_display_clock_speed =
8551                         i915_get_display_clock_speed;
8552         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8553                 dev_priv->display.get_display_clock_speed =
8554                         i9xx_misc_get_display_clock_speed;
8555         else if (IS_I915GM(dev))
8556                 dev_priv->display.get_display_clock_speed =
8557                         i915gm_get_display_clock_speed;
8558         else if (IS_I865G(dev))
8559                 dev_priv->display.get_display_clock_speed =
8560                         i865_get_display_clock_speed;
8561         else if (IS_I85X(dev))
8562                 dev_priv->display.get_display_clock_speed =
8563                         i855_get_display_clock_speed;
8564         else /* 852, 830 */
8565                 dev_priv->display.get_display_clock_speed =
8566                         i830_get_display_clock_speed;
8567
8568         if (HAS_PCH_SPLIT(dev)) {
8569                 if (IS_GEN5(dev)) {
8570                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8571                         dev_priv->display.write_eld = ironlake_write_eld;
8572                 } else if (IS_GEN6(dev)) {
8573                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8574                         dev_priv->display.write_eld = ironlake_write_eld;
8575                 } else if (IS_IVYBRIDGE(dev)) {
8576                         /* FIXME: detect B0+ stepping and use auto training */
8577                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8578                         dev_priv->display.write_eld = ironlake_write_eld;
8579                         dev_priv->display.modeset_global_resources =
8580                                 ivb_modeset_global_resources;
8581                 } else if (IS_HASWELL(dev)) {
8582                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8583                         dev_priv->display.write_eld = haswell_write_eld;
8584                 } else
8585                         dev_priv->display.update_wm = NULL;
8586         } else if (IS_G4X(dev)) {
8587                 dev_priv->display.write_eld = g4x_write_eld;
8588         }
8589
8590         /* Default just returns -ENODEV to indicate unsupported */
8591         dev_priv->display.queue_flip = intel_default_queue_flip;
8592
8593         switch (INTEL_INFO(dev)->gen) {
8594         case 2:
8595                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8596                 break;
8597
8598         case 3:
8599                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8600                 break;
8601
8602         case 4:
8603         case 5:
8604                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8605                 break;
8606
8607         case 6:
8608                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8609                 break;
8610         case 7:
8611                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8612                 break;
8613         }
8614 }
8615
8616 /*
8617  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8618  * resume, or other times.  This quirk makes sure that's the case for
8619  * affected systems.
8620  */
8621 static void quirk_pipea_force(struct drm_device *dev)
8622 {
8623         struct drm_i915_private *dev_priv = dev->dev_private;
8624
8625         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8626         DRM_INFO("applying pipe a force quirk\n");
8627 }
8628
8629 /*
8630  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8631  */
8632 static void quirk_ssc_force_disable(struct drm_device *dev)
8633 {
8634         struct drm_i915_private *dev_priv = dev->dev_private;
8635         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8636         DRM_INFO("applying lvds SSC disable quirk\n");
8637 }
8638
8639 /*
8640  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8641  * brightness value
8642  */
8643 static void quirk_invert_brightness(struct drm_device *dev)
8644 {
8645         struct drm_i915_private *dev_priv = dev->dev_private;
8646         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8647         DRM_INFO("applying inverted panel brightness quirk\n");
8648 }
8649
8650 struct intel_quirk {
8651         int device;
8652         int subsystem_vendor;
8653         int subsystem_device;
8654         void (*hook)(struct drm_device *dev);
8655 };
8656
8657 static struct intel_quirk intel_quirks[] = {
8658         /* HP Mini needs pipe A force quirk (LP: #322104) */
8659         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8660
8661         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8662         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8663
8664         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8665         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8666
8667         /* 830/845 need to leave pipe A & dpll A up */
8668         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8669         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8670
8671         /* Lenovo U160 cannot use SSC on LVDS */
8672         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8673
8674         /* Sony Vaio Y cannot use SSC on LVDS */
8675         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8676
8677         /* Acer Aspire 5734Z must invert backlight brightness */
8678         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8679 };
8680
8681 static void intel_init_quirks(struct drm_device *dev)
8682 {
8683         struct pci_dev *d = dev->pdev;
8684         int i;
8685
8686         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8687                 struct intel_quirk *q = &intel_quirks[i];
8688
8689                 if (d->device == q->device &&
8690                     (d->subsystem_vendor == q->subsystem_vendor ||
8691                      q->subsystem_vendor == PCI_ANY_ID) &&
8692                     (d->subsystem_device == q->subsystem_device ||
8693                      q->subsystem_device == PCI_ANY_ID))
8694                         q->hook(dev);
8695         }
8696 }
8697
8698 /* Disable the VGA plane that we never use */
8699 static void i915_disable_vga(struct drm_device *dev)
8700 {
8701         struct drm_i915_private *dev_priv = dev->dev_private;
8702         u8 sr1;
8703         u32 vga_reg;
8704
8705         if (HAS_PCH_SPLIT(dev))
8706                 vga_reg = CPU_VGACNTRL;
8707         else
8708                 vga_reg = VGACNTRL;
8709
8710         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8711         outb(SR01, VGA_SR_INDEX);
8712         sr1 = inb(VGA_SR_DATA);
8713         outb(sr1 | 1<<5, VGA_SR_DATA);
8714         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8715         udelay(300);
8716
8717         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8718         POSTING_READ(vga_reg);
8719 }
8720
8721 void intel_modeset_init_hw(struct drm_device *dev)
8722 {
8723         /* We attempt to init the necessary power wells early in the initialization
8724          * time, so the subsystems that expect power to be enabled can work.
8725          */
8726         intel_init_power_wells(dev);
8727
8728         intel_prepare_ddi(dev);
8729
8730         intel_init_clock_gating(dev);
8731
8732         mutex_lock(&dev->struct_mutex);
8733         intel_enable_gt_powersave(dev);
8734         mutex_unlock(&dev->struct_mutex);
8735 }
8736
8737 void intel_modeset_init(struct drm_device *dev)
8738 {
8739         struct drm_i915_private *dev_priv = dev->dev_private;
8740         int i, ret;
8741
8742         drm_mode_config_init(dev);
8743
8744         dev->mode_config.min_width = 0;
8745         dev->mode_config.min_height = 0;
8746
8747         dev->mode_config.preferred_depth = 24;
8748         dev->mode_config.prefer_shadow = 1;
8749
8750         dev->mode_config.funcs = &intel_mode_funcs;
8751
8752         intel_init_quirks(dev);
8753
8754         intel_init_pm(dev);
8755
8756         intel_init_display(dev);
8757
8758         if (IS_GEN2(dev)) {
8759                 dev->mode_config.max_width = 2048;
8760                 dev->mode_config.max_height = 2048;
8761         } else if (IS_GEN3(dev)) {
8762                 dev->mode_config.max_width = 4096;
8763                 dev->mode_config.max_height = 4096;
8764         } else {
8765                 dev->mode_config.max_width = 8192;
8766                 dev->mode_config.max_height = 8192;
8767         }
8768         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8769
8770         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8771                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8772
8773         for (i = 0; i < dev_priv->num_pipe; i++) {
8774                 intel_crtc_init(dev, i);
8775                 ret = intel_plane_init(dev, i);
8776                 if (ret)
8777                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8778         }
8779
8780         intel_cpu_pll_init(dev);
8781         intel_pch_pll_init(dev);
8782
8783         /* Just disable it once at startup */
8784         i915_disable_vga(dev);
8785         intel_setup_outputs(dev);
8786 }
8787
8788 static void
8789 intel_connector_break_all_links(struct intel_connector *connector)
8790 {
8791         connector->base.dpms = DRM_MODE_DPMS_OFF;
8792         connector->base.encoder = NULL;
8793         connector->encoder->connectors_active = false;
8794         connector->encoder->base.crtc = NULL;
8795 }
8796
8797 static void intel_enable_pipe_a(struct drm_device *dev)
8798 {
8799         struct intel_connector *connector;
8800         struct drm_connector *crt = NULL;
8801         struct intel_load_detect_pipe load_detect_temp;
8802
8803         /* We can't just switch on the pipe A, we need to set things up with a
8804          * proper mode and output configuration. As a gross hack, enable pipe A
8805          * by enabling the load detect pipe once. */
8806         list_for_each_entry(connector,
8807                             &dev->mode_config.connector_list,
8808                             base.head) {
8809                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8810                         crt = &connector->base;
8811                         break;
8812                 }
8813         }
8814
8815         if (!crt)
8816                 return;
8817
8818         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8819                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8820
8821
8822 }
8823
8824 static bool
8825 intel_check_plane_mapping(struct intel_crtc *crtc)
8826 {
8827         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8828         u32 reg, val;
8829
8830         if (dev_priv->num_pipe == 1)
8831                 return true;
8832
8833         reg = DSPCNTR(!crtc->plane);
8834         val = I915_READ(reg);
8835
8836         if ((val & DISPLAY_PLANE_ENABLE) &&
8837             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8838                 return false;
8839
8840         return true;
8841 }
8842
8843 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8844 {
8845         struct drm_device *dev = crtc->base.dev;
8846         struct drm_i915_private *dev_priv = dev->dev_private;
8847         u32 reg;
8848
8849         /* Clear any frame start delays used for debugging left by the BIOS */
8850         reg = PIPECONF(crtc->cpu_transcoder);
8851         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8852
8853         /* We need to sanitize the plane -> pipe mapping first because this will
8854          * disable the crtc (and hence change the state) if it is wrong. Note
8855          * that gen4+ has a fixed plane -> pipe mapping.  */
8856         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8857                 struct intel_connector *connector;
8858                 bool plane;
8859
8860                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8861                               crtc->base.base.id);
8862
8863                 /* Pipe has the wrong plane attached and the plane is active.
8864                  * Temporarily change the plane mapping and disable everything
8865                  * ...  */
8866                 plane = crtc->plane;
8867                 crtc->plane = !plane;
8868                 dev_priv->display.crtc_disable(&crtc->base);
8869                 crtc->plane = plane;
8870
8871                 /* ... and break all links. */
8872                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8873                                     base.head) {
8874                         if (connector->encoder->base.crtc != &crtc->base)
8875                                 continue;
8876
8877                         intel_connector_break_all_links(connector);
8878                 }
8879
8880                 WARN_ON(crtc->active);
8881                 crtc->base.enabled = false;
8882         }
8883
8884         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8885             crtc->pipe == PIPE_A && !crtc->active) {
8886                 /* BIOS forgot to enable pipe A, this mostly happens after
8887                  * resume. Force-enable the pipe to fix this, the update_dpms
8888                  * call below we restore the pipe to the right state, but leave
8889                  * the required bits on. */
8890                 intel_enable_pipe_a(dev);
8891         }
8892
8893         /* Adjust the state of the output pipe according to whether we
8894          * have active connectors/encoders. */
8895         intel_crtc_update_dpms(&crtc->base);
8896
8897         if (crtc->active != crtc->base.enabled) {
8898                 struct intel_encoder *encoder;
8899
8900                 /* This can happen either due to bugs in the get_hw_state
8901                  * functions or because the pipe is force-enabled due to the
8902                  * pipe A quirk. */
8903                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8904                               crtc->base.base.id,
8905                               crtc->base.enabled ? "enabled" : "disabled",
8906                               crtc->active ? "enabled" : "disabled");
8907
8908                 crtc->base.enabled = crtc->active;
8909
8910                 /* Because we only establish the connector -> encoder ->
8911                  * crtc links if something is active, this means the
8912                  * crtc is now deactivated. Break the links. connector
8913                  * -> encoder links are only establish when things are
8914                  *  actually up, hence no need to break them. */
8915                 WARN_ON(crtc->active);
8916
8917                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8918                         WARN_ON(encoder->connectors_active);
8919                         encoder->base.crtc = NULL;
8920                 }
8921         }
8922 }
8923
8924 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8925 {
8926         struct intel_connector *connector;
8927         struct drm_device *dev = encoder->base.dev;
8928
8929         /* We need to check both for a crtc link (meaning that the
8930          * encoder is active and trying to read from a pipe) and the
8931          * pipe itself being active. */
8932         bool has_active_crtc = encoder->base.crtc &&
8933                 to_intel_crtc(encoder->base.crtc)->active;
8934
8935         if (encoder->connectors_active && !has_active_crtc) {
8936                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8937                               encoder->base.base.id,
8938                               drm_get_encoder_name(&encoder->base));
8939
8940                 /* Connector is active, but has no active pipe. This is
8941                  * fallout from our resume register restoring. Disable
8942                  * the encoder manually again. */
8943                 if (encoder->base.crtc) {
8944                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8945                                       encoder->base.base.id,
8946                                       drm_get_encoder_name(&encoder->base));
8947                         encoder->disable(encoder);
8948                 }
8949
8950                 /* Inconsistent output/port/pipe state happens presumably due to
8951                  * a bug in one of the get_hw_state functions. Or someplace else
8952                  * in our code, like the register restore mess on resume. Clamp
8953                  * things to off as a safer default. */
8954                 list_for_each_entry(connector,
8955                                     &dev->mode_config.connector_list,
8956                                     base.head) {
8957                         if (connector->encoder != encoder)
8958                                 continue;
8959
8960                         intel_connector_break_all_links(connector);
8961                 }
8962         }
8963         /* Enabled encoders without active connectors will be fixed in
8964          * the crtc fixup. */
8965 }
8966
8967 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8968  * and i915 state tracking structures. */
8969 void intel_modeset_setup_hw_state(struct drm_device *dev)
8970 {
8971         struct drm_i915_private *dev_priv = dev->dev_private;
8972         enum pipe pipe;
8973         u32 tmp;
8974         struct intel_crtc *crtc;
8975         struct intel_encoder *encoder;
8976         struct intel_connector *connector;
8977
8978         if (IS_HASWELL(dev)) {
8979                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8980
8981                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8982                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8983                         case TRANS_DDI_EDP_INPUT_A_ON:
8984                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8985                                 pipe = PIPE_A;
8986                                 break;
8987                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8988                                 pipe = PIPE_B;
8989                                 break;
8990                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8991                                 pipe = PIPE_C;
8992                                 break;
8993                         }
8994
8995                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8996                         crtc->cpu_transcoder = TRANSCODER_EDP;
8997
8998                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8999                                       pipe_name(pipe));
9000                 }
9001         }
9002
9003         for_each_pipe(pipe) {
9004                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9005
9006                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9007                 if (tmp & PIPECONF_ENABLE)
9008                         crtc->active = true;
9009                 else
9010                         crtc->active = false;
9011
9012                 crtc->base.enabled = crtc->active;
9013
9014                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9015                               crtc->base.base.id,
9016                               crtc->active ? "enabled" : "disabled");
9017         }
9018
9019         if (IS_HASWELL(dev))
9020                 intel_ddi_setup_hw_pll_state(dev);
9021
9022         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9023                             base.head) {
9024                 pipe = 0;
9025
9026                 if (encoder->get_hw_state(encoder, &pipe)) {
9027                         encoder->base.crtc =
9028                                 dev_priv->pipe_to_crtc_mapping[pipe];
9029                 } else {
9030                         encoder->base.crtc = NULL;
9031                 }
9032
9033                 encoder->connectors_active = false;
9034                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9035                               encoder->base.base.id,
9036                               drm_get_encoder_name(&encoder->base),
9037                               encoder->base.crtc ? "enabled" : "disabled",
9038                               pipe);
9039         }
9040
9041         list_for_each_entry(connector, &dev->mode_config.connector_list,
9042                             base.head) {
9043                 if (connector->get_hw_state(connector)) {
9044                         connector->base.dpms = DRM_MODE_DPMS_ON;
9045                         connector->encoder->connectors_active = true;
9046                         connector->base.encoder = &connector->encoder->base;
9047                 } else {
9048                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9049                         connector->base.encoder = NULL;
9050                 }
9051                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9052                               connector->base.base.id,
9053                               drm_get_connector_name(&connector->base),
9054                               connector->base.encoder ? "enabled" : "disabled");
9055         }
9056
9057         /* HW state is read out, now we need to sanitize this mess. */
9058         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9059                             base.head) {
9060                 intel_sanitize_encoder(encoder);
9061         }
9062
9063         for_each_pipe(pipe) {
9064                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9065                 intel_sanitize_crtc(crtc);
9066         }
9067
9068         intel_modeset_update_staged_output_state(dev);
9069
9070         intel_modeset_check_state(dev);
9071
9072         drm_mode_config_reset(dev);
9073 }
9074
9075 void intel_modeset_gem_init(struct drm_device *dev)
9076 {
9077         intel_modeset_init_hw(dev);
9078
9079         intel_setup_overlay(dev);
9080
9081         intel_modeset_setup_hw_state(dev);
9082 }
9083
9084 void intel_modeset_cleanup(struct drm_device *dev)
9085 {
9086         struct drm_i915_private *dev_priv = dev->dev_private;
9087         struct drm_crtc *crtc;
9088         struct intel_crtc *intel_crtc;
9089
9090         drm_kms_helper_poll_fini(dev);
9091         mutex_lock(&dev->struct_mutex);
9092
9093         intel_unregister_dsm_handler();
9094
9095
9096         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9097                 /* Skip inactive CRTCs */
9098                 if (!crtc->fb)
9099                         continue;
9100
9101                 intel_crtc = to_intel_crtc(crtc);
9102                 intel_increase_pllclock(crtc);
9103         }
9104
9105         intel_disable_fbc(dev);
9106
9107         intel_disable_gt_powersave(dev);
9108
9109         ironlake_teardown_rc6(dev);
9110
9111         if (IS_VALLEYVIEW(dev))
9112                 vlv_init_dpio(dev);
9113
9114         mutex_unlock(&dev->struct_mutex);
9115
9116         /* Disable the irq before mode object teardown, for the irq might
9117          * enqueue unpin/hotplug work. */
9118         drm_irq_uninstall(dev);
9119         cancel_work_sync(&dev_priv->hotplug_work);
9120         cancel_work_sync(&dev_priv->rps.work);
9121
9122         /* flush any delayed tasks or pending work */
9123         flush_scheduled_work();
9124
9125         drm_mode_config_cleanup(dev);
9126 }
9127
9128 /*
9129  * Return which encoder is currently attached for connector.
9130  */
9131 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9132 {
9133         return &intel_attached_encoder(connector)->base;
9134 }
9135
9136 void intel_connector_attach_encoder(struct intel_connector *connector,
9137                                     struct intel_encoder *encoder)
9138 {
9139         connector->encoder = encoder;
9140         drm_mode_connector_attach_encoder(&connector->base,
9141                                           &encoder->base);
9142 }
9143
9144 /*
9145  * set vga decode state - true == enable VGA decode
9146  */
9147 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9148 {
9149         struct drm_i915_private *dev_priv = dev->dev_private;
9150         u16 gmch_ctrl;
9151
9152         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9153         if (state)
9154                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9155         else
9156                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9157         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9158         return 0;
9159 }
9160
9161 #ifdef CONFIG_DEBUG_FS
9162 #include <linux/seq_file.h>
9163
9164 struct intel_display_error_state {
9165         struct intel_cursor_error_state {
9166                 u32 control;
9167                 u32 position;
9168                 u32 base;
9169                 u32 size;
9170         } cursor[I915_MAX_PIPES];
9171
9172         struct intel_pipe_error_state {
9173                 u32 conf;
9174                 u32 source;
9175
9176                 u32 htotal;
9177                 u32 hblank;
9178                 u32 hsync;
9179                 u32 vtotal;
9180                 u32 vblank;
9181                 u32 vsync;
9182         } pipe[I915_MAX_PIPES];
9183
9184         struct intel_plane_error_state {
9185                 u32 control;
9186                 u32 stride;
9187                 u32 size;
9188                 u32 pos;
9189                 u32 addr;
9190                 u32 surface;
9191                 u32 tile_offset;
9192         } plane[I915_MAX_PIPES];
9193 };
9194
9195 struct intel_display_error_state *
9196 intel_display_capture_error_state(struct drm_device *dev)
9197 {
9198         drm_i915_private_t *dev_priv = dev->dev_private;
9199         struct intel_display_error_state *error;
9200         enum transcoder cpu_transcoder;
9201         int i;
9202
9203         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9204         if (error == NULL)
9205                 return NULL;
9206
9207         for_each_pipe(i) {
9208                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9209
9210                 error->cursor[i].control = I915_READ(CURCNTR(i));
9211                 error->cursor[i].position = I915_READ(CURPOS(i));
9212                 error->cursor[i].base = I915_READ(CURBASE(i));
9213
9214                 error->plane[i].control = I915_READ(DSPCNTR(i));
9215                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9216                 error->plane[i].size = I915_READ(DSPSIZE(i));
9217                 error->plane[i].pos = I915_READ(DSPPOS(i));
9218                 error->plane[i].addr = I915_READ(DSPADDR(i));
9219                 if (INTEL_INFO(dev)->gen >= 4) {
9220                         error->plane[i].surface = I915_READ(DSPSURF(i));
9221                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9222                 }
9223
9224                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9225                 error->pipe[i].source = I915_READ(PIPESRC(i));
9226                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9227                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9228                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9229                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9230                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9231                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9232         }
9233
9234         return error;
9235 }
9236
9237 void
9238 intel_display_print_error_state(struct seq_file *m,
9239                                 struct drm_device *dev,
9240                                 struct intel_display_error_state *error)
9241 {
9242         drm_i915_private_t *dev_priv = dev->dev_private;
9243         int i;
9244
9245         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9246         for_each_pipe(i) {
9247                 seq_printf(m, "Pipe [%d]:\n", i);
9248                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9249                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9250                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9251                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9252                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9253                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9254                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9255                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9256
9257                 seq_printf(m, "Plane [%d]:\n", i);
9258                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9259                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9260                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9261                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9262                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9263                 if (INTEL_INFO(dev)->gen >= 4) {
9264                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9265                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9266                 }
9267
9268                 seq_printf(m, "Cursor [%d]:\n", i);
9269                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9270                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9271                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9272         }
9273 }
9274 #endif