Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(pipe);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125
1126         if (IS_HASWELL(dev_priv->dev)) {
1127                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1128                 reg = DDI_FUNC_CTL(pipe);
1129                 val = I915_READ(reg);
1130                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1131         } else {
1132                 reg = FDI_TX_CTL(pipe);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & FDI_TX_ENABLE);
1135         }
1136         WARN(cur_state != state,
1137              "FDI TX state assertion failure (expected %s, current %s)\n",
1138              state_string(state), state_string(cur_state));
1139 }
1140 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1141 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1142
1143 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1144                           enum pipe pipe, bool state)
1145 {
1146         int reg;
1147         u32 val;
1148         bool cur_state;
1149
1150         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1151                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1152                         return;
1153         } else {
1154                 reg = FDI_RX_CTL(pipe);
1155                 val = I915_READ(reg);
1156                 cur_state = !!(val & FDI_RX_ENABLE);
1157         }
1158         WARN(cur_state != state,
1159              "FDI RX state assertion failure (expected %s, current %s)\n",
1160              state_string(state), state_string(cur_state));
1161 }
1162 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1163 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1164
1165 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         /* ILK FDI PLL is always enabled */
1172         if (dev_priv->info->gen == 5)
1173                 return;
1174
1175         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1176         if (IS_HASWELL(dev_priv->dev))
1177                 return;
1178
1179         reg = FDI_TX_CTL(pipe);
1180         val = I915_READ(reg);
1181         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1182 }
1183
1184 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1185                                       enum pipe pipe)
1186 {
1187         int reg;
1188         u32 val;
1189
1190         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1191                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1192                 return;
1193         }
1194         reg = FDI_RX_CTL(pipe);
1195         val = I915_READ(reg);
1196         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1197 }
1198
1199 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1200                                   enum pipe pipe)
1201 {
1202         int pp_reg, lvds_reg;
1203         u32 val;
1204         enum pipe panel_pipe = PIPE_A;
1205         bool locked = true;
1206
1207         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1208                 pp_reg = PCH_PP_CONTROL;
1209                 lvds_reg = PCH_LVDS;
1210         } else {
1211                 pp_reg = PP_CONTROL;
1212                 lvds_reg = LVDS;
1213         }
1214
1215         val = I915_READ(pp_reg);
1216         if (!(val & PANEL_POWER_ON) ||
1217             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1218                 locked = false;
1219
1220         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1221                 panel_pipe = PIPE_B;
1222
1223         WARN(panel_pipe == pipe && locked,
1224              "panel assertion failure, pipe %c regs locked\n",
1225              pipe_name(pipe));
1226 }
1227
1228 void assert_pipe(struct drm_i915_private *dev_priv,
1229                  enum pipe pipe, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         /* if we need the pipe A quirk it must be always on */
1236         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1237                 state = true;
1238
1239         reg = PIPECONF(pipe);
1240         val = I915_READ(reg);
1241         cur_state = !!(val & PIPECONF_ENABLE);
1242         WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         int reg, i;
1269         u32 val;
1270         int cur_pipe;
1271
1272         /* Planes are fixed to pipes on ILK+ */
1273         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1274                 reg = DSPCNTR(pipe);
1275                 val = I915_READ(reg);
1276                 WARN((val & DISPLAY_PLANE_ENABLE),
1277                      "plane %c assertion failure, should be disabled but not\n",
1278                      plane_name(pipe));
1279                 return;
1280         }
1281
1282         /* Need to check both planes against the pipe */
1283         for (i = 0; i < 2; i++) {
1284                 reg = DSPCNTR(i);
1285                 val = I915_READ(reg);
1286                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287                         DISPPLANE_SEL_PIPE_SHIFT;
1288                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290                      plane_name(i), pipe_name(pipe));
1291         }
1292 }
1293
1294 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1295 {
1296         u32 val;
1297         bool enabled;
1298
1299         if (HAS_PCH_LPT(dev_priv->dev)) {
1300                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301                 return;
1302         }
1303
1304         val = I915_READ(PCH_DREF_CONTROL);
1305         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1306                             DREF_SUPERSPREAD_SOURCE_MASK));
1307         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1308 }
1309
1310 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1311                                        enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315         bool enabled;
1316
1317         reg = TRANSCONF(pipe);
1318         val = I915_READ(reg);
1319         enabled = !!(val & TRANS_ENABLE);
1320         WARN(enabled,
1321              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322              pipe_name(pipe));
1323 }
1324
1325 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1326                             enum pipe pipe, u32 port_sel, u32 val)
1327 {
1328         if ((val & DP_PORT_EN) == 0)
1329                 return false;
1330
1331         if (HAS_PCH_CPT(dev_priv->dev)) {
1332                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1333                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1334                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1335                         return false;
1336         } else {
1337                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & PORT_ENABLE) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & LVDS_PORT_EN) == 0)
1363                 return false;
1364
1365         if (HAS_PCH_CPT(dev_priv->dev)) {
1366                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1367                         return false;
1368         } else {
1369                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1370                         return false;
1371         }
1372         return true;
1373 }
1374
1375 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1376                               enum pipe pipe, u32 val)
1377 {
1378         if ((val & ADPA_DAC_ENABLE) == 0)
1379                 return false;
1380         if (HAS_PCH_CPT(dev_priv->dev)) {
1381                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1382                         return false;
1383         } else {
1384                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1385                         return false;
1386         }
1387         return true;
1388 }
1389
1390 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1391                                    enum pipe pipe, int reg, u32 port_sel)
1392 {
1393         u32 val = I915_READ(reg);
1394         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1395              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1396              reg, pipe_name(pipe));
1397
1398         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1399              && (val & DP_PIPEB_SELECT),
1400              "IBX PCH dp port still using transcoder B\n");
1401 }
1402
1403 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1404                                      enum pipe pipe, int reg)
1405 {
1406         u32 val = I915_READ(reg);
1407         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1408              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1409              reg, pipe_name(pipe));
1410
1411         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1412              && (val & SDVO_PIPE_B_SELECT),
1413              "IBX PCH hdmi port still using transcoder B\n");
1414 }
1415
1416 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1417                                       enum pipe pipe)
1418 {
1419         int reg;
1420         u32 val;
1421
1422         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1423         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1424         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1425
1426         reg = PCH_ADPA;
1427         val = I915_READ(reg);
1428         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1429              "PCH VGA enabled on transcoder %c, should be disabled\n",
1430              pipe_name(pipe));
1431
1432         reg = PCH_LVDS;
1433         val = I915_READ(reg);
1434         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1435              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1439         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1440         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1441 }
1442
1443 /**
1444  * intel_enable_pll - enable a PLL
1445  * @dev_priv: i915 private structure
1446  * @pipe: pipe PLL to enable
1447  *
1448  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1449  * make sure the PLL reg is writable first though, since the panel write
1450  * protect mechanism may be enabled.
1451  *
1452  * Note!  This is for pre-ILK only.
1453  *
1454  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1455  */
1456 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460
1461         /* No really, not for ILK+ */
1462         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1463
1464         /* PLL is protected by panel, make sure we can write it */
1465         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1466                 assert_panel_unlocked(dev_priv, pipe);
1467
1468         reg = DPLL(pipe);
1469         val = I915_READ(reg);
1470         val |= DPLL_VCO_ENABLE;
1471
1472         /* We do this three times for luck */
1473         I915_WRITE(reg, val);
1474         POSTING_READ(reg);
1475         udelay(150); /* wait for warmup */
1476         I915_WRITE(reg, val);
1477         POSTING_READ(reg);
1478         udelay(150); /* wait for warmup */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482 }
1483
1484 /**
1485  * intel_disable_pll - disable a PLL
1486  * @dev_priv: i915 private structure
1487  * @pipe: pipe PLL to disable
1488  *
1489  * Disable the PLL for @pipe, making sure the pipe is off first.
1490  *
1491  * Note!  This is for pre-ILK only.
1492  */
1493 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1494 {
1495         int reg;
1496         u32 val;
1497
1498         /* Don't disable pipe A or pipe A PLLs if needed */
1499         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1500                 return;
1501
1502         /* Make sure the pipe isn't still relying on us */
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         reg = DPLL(pipe);
1506         val = I915_READ(reg);
1507         val &= ~DPLL_VCO_ENABLE;
1508         I915_WRITE(reg, val);
1509         POSTING_READ(reg);
1510 }
1511
1512 /* SBI access */
1513 static void
1514 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1515 {
1516         unsigned long flags;
1517
1518         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1519         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1520                                 100)) {
1521                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1522                 goto out_unlock;
1523         }
1524
1525         I915_WRITE(SBI_ADDR,
1526                         (reg << 16));
1527         I915_WRITE(SBI_DATA,
1528                         value);
1529         I915_WRITE(SBI_CTL_STAT,
1530                         SBI_BUSY |
1531                         SBI_CTL_OP_CRWR);
1532
1533         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1534                                 100)) {
1535                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1536                 goto out_unlock;
1537         }
1538
1539 out_unlock:
1540         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1541 }
1542
1543 static u32
1544 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1545 {
1546         unsigned long flags;
1547         u32 value = 0;
1548
1549         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1550         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1551                                 100)) {
1552                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553                 goto out_unlock;
1554         }
1555
1556         I915_WRITE(SBI_ADDR,
1557                         (reg << 16));
1558         I915_WRITE(SBI_CTL_STAT,
1559                         SBI_BUSY |
1560                         SBI_CTL_OP_CRRD);
1561
1562         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1563                                 100)) {
1564                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1565                 goto out_unlock;
1566         }
1567
1568         value = I915_READ(SBI_DATA);
1569
1570 out_unlock:
1571         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1572         return value;
1573 }
1574
1575 /**
1576  * intel_enable_pch_pll - enable PCH PLL
1577  * @dev_priv: i915 private structure
1578  * @pipe: pipe PLL to enable
1579  *
1580  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1581  * drives the transcoder clock.
1582  */
1583 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1584 {
1585         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1586         struct intel_pch_pll *pll;
1587         int reg;
1588         u32 val;
1589
1590         /* PCH PLLs only available on ILK, SNB and IVB */
1591         BUG_ON(dev_priv->info->gen < 5);
1592         pll = intel_crtc->pch_pll;
1593         if (pll == NULL)
1594                 return;
1595
1596         if (WARN_ON(pll->refcount == 0))
1597                 return;
1598
1599         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1600                       pll->pll_reg, pll->active, pll->on,
1601                       intel_crtc->base.base.id);
1602
1603         /* PCH refclock must be enabled first */
1604         assert_pch_refclk_enabled(dev_priv);
1605
1606         if (pll->active++ && pll->on) {
1607                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1608                 return;
1609         }
1610
1611         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1612
1613         reg = pll->pll_reg;
1614         val = I915_READ(reg);
1615         val |= DPLL_VCO_ENABLE;
1616         I915_WRITE(reg, val);
1617         POSTING_READ(reg);
1618         udelay(200);
1619
1620         pll->on = true;
1621 }
1622
1623 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1624 {
1625         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1626         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1627         int reg;
1628         u32 val;
1629
1630         /* PCH only available on ILK+ */
1631         BUG_ON(dev_priv->info->gen < 5);
1632         if (pll == NULL)
1633                return;
1634
1635         if (WARN_ON(pll->refcount == 0))
1636                 return;
1637
1638         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1639                       pll->pll_reg, pll->active, pll->on,
1640                       intel_crtc->base.base.id);
1641
1642         if (WARN_ON(pll->active == 0)) {
1643                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1644                 return;
1645         }
1646
1647         if (--pll->active) {
1648                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1649                 return;
1650         }
1651
1652         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1653
1654         /* Make sure transcoder isn't still depending on us */
1655         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1656
1657         reg = pll->pll_reg;
1658         val = I915_READ(reg);
1659         val &= ~DPLL_VCO_ENABLE;
1660         I915_WRITE(reg, val);
1661         POSTING_READ(reg);
1662         udelay(200);
1663
1664         pll->on = false;
1665 }
1666
1667 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1668                                     enum pipe pipe)
1669 {
1670         int reg;
1671         u32 val, pipeconf_val;
1672         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1673
1674         /* PCH only available on ILK+ */
1675         BUG_ON(dev_priv->info->gen < 5);
1676
1677         /* Make sure PCH DPLL is enabled */
1678         assert_pch_pll_enabled(dev_priv,
1679                                to_intel_crtc(crtc)->pch_pll,
1680                                to_intel_crtc(crtc));
1681
1682         /* FDI must be feeding us bits for PCH ports */
1683         assert_fdi_tx_enabled(dev_priv, pipe);
1684         assert_fdi_rx_enabled(dev_priv, pipe);
1685
1686         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1687                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1688                 return;
1689         }
1690         reg = TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv->dev)) {
1695                 /*
1696                  * make the BPC in transcoder be consistent with
1697                  * that in pipeconf reg.
1698                  */
1699                 val &= ~PIPE_BPC_MASK;
1700                 val |= pipeconf_val & PIPE_BPC_MASK;
1701         }
1702
1703         val &= ~TRANS_INTERLACE_MASK;
1704         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705                 if (HAS_PCH_IBX(dev_priv->dev) &&
1706                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707                         val |= TRANS_LEGACY_INTERLACED_ILK;
1708                 else
1709                         val |= TRANS_INTERLACED;
1710         else
1711                 val |= TRANS_PROGRESSIVE;
1712
1713         I915_WRITE(reg, val | TRANS_ENABLE);
1714         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1719                                      enum pipe pipe)
1720 {
1721         int reg;
1722         u32 val;
1723
1724         /* FDI relies on the transcoder */
1725         assert_fdi_tx_disabled(dev_priv, pipe);
1726         assert_fdi_rx_disabled(dev_priv, pipe);
1727
1728         /* Ports must be off as well */
1729         assert_pch_ports_disabled(dev_priv, pipe);
1730
1731         reg = TRANSCONF(pipe);
1732         val = I915_READ(reg);
1733         val &= ~TRANS_ENABLE;
1734         I915_WRITE(reg, val);
1735         /* wait for PCH transcoder off, transcoder state */
1736         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1737                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1738 }
1739
1740 /**
1741  * intel_enable_pipe - enable a pipe, asserting requirements
1742  * @dev_priv: i915 private structure
1743  * @pipe: pipe to enable
1744  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1745  *
1746  * Enable @pipe, making sure that various hardware specific requirements
1747  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1748  *
1749  * @pipe should be %PIPE_A or %PIPE_B.
1750  *
1751  * Will wait until the pipe is actually running (i.e. first vblank) before
1752  * returning.
1753  */
1754 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1755                               bool pch_port)
1756 {
1757         int reg;
1758         u32 val;
1759
1760         /*
1761          * A pipe without a PLL won't actually be able to drive bits from
1762          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1763          * need the check.
1764          */
1765         if (!HAS_PCH_SPLIT(dev_priv->dev))
1766                 assert_pll_enabled(dev_priv, pipe);
1767         else {
1768                 if (pch_port) {
1769                         /* if driving the PCH, we need FDI enabled */
1770                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1771                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1772                 }
1773                 /* FIXME: assert CPU port conditions for SNB+ */
1774         }
1775
1776         reg = PIPECONF(pipe);
1777         val = I915_READ(reg);
1778         if (val & PIPECONF_ENABLE)
1779                 return;
1780
1781         I915_WRITE(reg, val | PIPECONF_ENABLE);
1782         intel_wait_for_vblank(dev_priv->dev, pipe);
1783 }
1784
1785 /**
1786  * intel_disable_pipe - disable a pipe, asserting requirements
1787  * @dev_priv: i915 private structure
1788  * @pipe: pipe to disable
1789  *
1790  * Disable @pipe, making sure that various hardware specific requirements
1791  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1792  *
1793  * @pipe should be %PIPE_A or %PIPE_B.
1794  *
1795  * Will wait until the pipe has shut down before returning.
1796  */
1797 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1798                                enum pipe pipe)
1799 {
1800         int reg;
1801         u32 val;
1802
1803         /*
1804          * Make sure planes won't keep trying to pump pixels to us,
1805          * or we might hang the display.
1806          */
1807         assert_planes_disabled(dev_priv, pipe);
1808
1809         /* Don't disable pipe A or pipe A PLLs if needed */
1810         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1811                 return;
1812
1813         reg = PIPECONF(pipe);
1814         val = I915_READ(reg);
1815         if ((val & PIPECONF_ENABLE) == 0)
1816                 return;
1817
1818         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1819         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1820 }
1821
1822 /*
1823  * Plane regs are double buffered, going from enabled->disabled needs a
1824  * trigger in order to latch.  The display address reg provides this.
1825  */
1826 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1827                                       enum plane plane)
1828 {
1829         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1830         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1831 }
1832
1833 /**
1834  * intel_enable_plane - enable a display plane on a given pipe
1835  * @dev_priv: i915 private structure
1836  * @plane: plane to enable
1837  * @pipe: pipe being fed
1838  *
1839  * Enable @plane on @pipe, making sure that @pipe is running first.
1840  */
1841 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1842                                enum plane plane, enum pipe pipe)
1843 {
1844         int reg;
1845         u32 val;
1846
1847         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1848         assert_pipe_enabled(dev_priv, pipe);
1849
1850         reg = DSPCNTR(plane);
1851         val = I915_READ(reg);
1852         if (val & DISPLAY_PLANE_ENABLE)
1853                 return;
1854
1855         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1856         intel_flush_display_plane(dev_priv, plane);
1857         intel_wait_for_vblank(dev_priv->dev, pipe);
1858 }
1859
1860 /**
1861  * intel_disable_plane - disable a display plane
1862  * @dev_priv: i915 private structure
1863  * @plane: plane to disable
1864  * @pipe: pipe consuming the data
1865  *
1866  * Disable @plane; should be an independent operation.
1867  */
1868 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1869                                 enum plane plane, enum pipe pipe)
1870 {
1871         int reg;
1872         u32 val;
1873
1874         reg = DSPCNTR(plane);
1875         val = I915_READ(reg);
1876         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1877                 return;
1878
1879         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1880         intel_flush_display_plane(dev_priv, plane);
1881         intel_wait_for_vblank(dev_priv->dev, pipe);
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886                            struct drm_i915_gem_object *obj,
1887                            struct intel_ring_buffer *pipelined)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         u32 alignment;
1891         int ret;
1892
1893         switch (obj->tiling_mode) {
1894         case I915_TILING_NONE:
1895                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896                         alignment = 128 * 1024;
1897                 else if (INTEL_INFO(dev)->gen >= 4)
1898                         alignment = 4 * 1024;
1899                 else
1900                         alignment = 64 * 1024;
1901                 break;
1902         case I915_TILING_X:
1903                 /* pin() will align the object as required by fence */
1904                 alignment = 0;
1905                 break;
1906         case I915_TILING_Y:
1907                 /* FIXME: Is this true? */
1908                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1909                 return -EINVAL;
1910         default:
1911                 BUG();
1912         }
1913
1914         dev_priv->mm.interruptible = false;
1915         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1916         if (ret)
1917                 goto err_interruptible;
1918
1919         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1920          * fence, whereas 965+ only requires a fence if using
1921          * framebuffer compression.  For simplicity, we always install
1922          * a fence as the cost is not that onerous.
1923          */
1924         ret = i915_gem_object_get_fence(obj);
1925         if (ret)
1926                 goto err_unpin;
1927
1928         i915_gem_object_pin_fence(obj);
1929
1930         dev_priv->mm.interruptible = true;
1931         return 0;
1932
1933 err_unpin:
1934         i915_gem_object_unpin(obj);
1935 err_interruptible:
1936         dev_priv->mm.interruptible = true;
1937         return ret;
1938 }
1939
1940 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1941 {
1942         i915_gem_object_unpin_fence(obj);
1943         i915_gem_object_unpin(obj);
1944 }
1945
1946 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1947  * is assumed to be a power-of-two. */
1948 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1949                                                         unsigned int bpp,
1950                                                         unsigned int pitch)
1951 {
1952         int tile_rows, tiles;
1953
1954         tile_rows = *y / 8;
1955         *y %= 8;
1956         tiles = *x / (512/bpp);
1957         *x %= 512/bpp;
1958
1959         return tile_rows * pitch * 8 + tiles * 4096;
1960 }
1961
1962 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1963                              int x, int y)
1964 {
1965         struct drm_device *dev = crtc->dev;
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1968         struct intel_framebuffer *intel_fb;
1969         struct drm_i915_gem_object *obj;
1970         int plane = intel_crtc->plane;
1971         unsigned long linear_offset;
1972         u32 dspcntr;
1973         u32 reg;
1974
1975         switch (plane) {
1976         case 0:
1977         case 1:
1978                 break;
1979         default:
1980                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1981                 return -EINVAL;
1982         }
1983
1984         intel_fb = to_intel_framebuffer(fb);
1985         obj = intel_fb->obj;
1986
1987         reg = DSPCNTR(plane);
1988         dspcntr = I915_READ(reg);
1989         /* Mask out pixel format bits in case we change it */
1990         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1991         switch (fb->bits_per_pixel) {
1992         case 8:
1993                 dspcntr |= DISPPLANE_8BPP;
1994                 break;
1995         case 16:
1996                 if (fb->depth == 15)
1997                         dspcntr |= DISPPLANE_15_16BPP;
1998                 else
1999                         dspcntr |= DISPPLANE_16BPP;
2000                 break;
2001         case 24:
2002         case 32:
2003                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2004                 break;
2005         default:
2006                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2007                 return -EINVAL;
2008         }
2009         if (INTEL_INFO(dev)->gen >= 4) {
2010                 if (obj->tiling_mode != I915_TILING_NONE)
2011                         dspcntr |= DISPPLANE_TILED;
2012                 else
2013                         dspcntr &= ~DISPPLANE_TILED;
2014         }
2015
2016         I915_WRITE(reg, dspcntr);
2017
2018         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2019
2020         if (INTEL_INFO(dev)->gen >= 4) {
2021                 intel_crtc->dspaddr_offset =
2022                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2023                                                            fb->bits_per_pixel / 8,
2024                                                            fb->pitches[0]);
2025                 linear_offset -= intel_crtc->dspaddr_offset;
2026         } else {
2027                 intel_crtc->dspaddr_offset = linear_offset;
2028         }
2029
2030         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2031                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2032         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2033         if (INTEL_INFO(dev)->gen >= 4) {
2034                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2035                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2036                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2037                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2038         } else
2039                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2040         POSTING_READ(reg);
2041
2042         return 0;
2043 }
2044
2045 static int ironlake_update_plane(struct drm_crtc *crtc,
2046                                  struct drm_framebuffer *fb, int x, int y)
2047 {
2048         struct drm_device *dev = crtc->dev;
2049         struct drm_i915_private *dev_priv = dev->dev_private;
2050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2051         struct intel_framebuffer *intel_fb;
2052         struct drm_i915_gem_object *obj;
2053         int plane = intel_crtc->plane;
2054         unsigned long linear_offset;
2055         u32 dspcntr;
2056         u32 reg;
2057
2058         switch (plane) {
2059         case 0:
2060         case 1:
2061         case 2:
2062                 break;
2063         default:
2064                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2065                 return -EINVAL;
2066         }
2067
2068         intel_fb = to_intel_framebuffer(fb);
2069         obj = intel_fb->obj;
2070
2071         reg = DSPCNTR(plane);
2072         dspcntr = I915_READ(reg);
2073         /* Mask out pixel format bits in case we change it */
2074         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2075         switch (fb->bits_per_pixel) {
2076         case 8:
2077                 dspcntr |= DISPPLANE_8BPP;
2078                 break;
2079         case 16:
2080                 if (fb->depth != 16)
2081                         return -EINVAL;
2082
2083                 dspcntr |= DISPPLANE_16BPP;
2084                 break;
2085         case 24:
2086         case 32:
2087                 if (fb->depth == 24)
2088                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2089                 else if (fb->depth == 30)
2090                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2091                 else
2092                         return -EINVAL;
2093                 break;
2094         default:
2095                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2096                 return -EINVAL;
2097         }
2098
2099         if (obj->tiling_mode != I915_TILING_NONE)
2100                 dspcntr |= DISPPLANE_TILED;
2101         else
2102                 dspcntr &= ~DISPPLANE_TILED;
2103
2104         /* must disable */
2105         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2106
2107         I915_WRITE(reg, dspcntr);
2108
2109         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2110         intel_crtc->dspaddr_offset =
2111                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2112                                                    fb->bits_per_pixel / 8,
2113                                                    fb->pitches[0]);
2114         linear_offset -= intel_crtc->dspaddr_offset;
2115
2116         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119         I915_MODIFY_DISPBASE(DSPSURF(plane),
2120                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2121         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2122         I915_WRITE(DSPLINOFF(plane), linear_offset);
2123         POSTING_READ(reg);
2124
2125         return 0;
2126 }
2127
2128 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2129 static int
2130 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2131                            int x, int y, enum mode_set_atomic state)
2132 {
2133         struct drm_device *dev = crtc->dev;
2134         struct drm_i915_private *dev_priv = dev->dev_private;
2135
2136         if (dev_priv->display.disable_fbc)
2137                 dev_priv->display.disable_fbc(dev);
2138         intel_increase_pllclock(crtc);
2139
2140         return dev_priv->display.update_plane(crtc, fb, x, y);
2141 }
2142
2143 static int
2144 intel_finish_fb(struct drm_framebuffer *old_fb)
2145 {
2146         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2147         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2148         bool was_interruptible = dev_priv->mm.interruptible;
2149         int ret;
2150
2151         wait_event(dev_priv->pending_flip_queue,
2152                    atomic_read(&dev_priv->mm.wedged) ||
2153                    atomic_read(&obj->pending_flip) == 0);
2154
2155         /* Big Hammer, we also need to ensure that any pending
2156          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2157          * current scanout is retired before unpinning the old
2158          * framebuffer.
2159          *
2160          * This should only fail upon a hung GPU, in which case we
2161          * can safely continue.
2162          */
2163         dev_priv->mm.interruptible = false;
2164         ret = i915_gem_object_finish_gpu(obj);
2165         dev_priv->mm.interruptible = was_interruptible;
2166
2167         return ret;
2168 }
2169
2170 static int
2171 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2172                     struct drm_framebuffer *fb)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176         struct drm_i915_master_private *master_priv;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct drm_framebuffer *old_fb;
2179         int ret;
2180
2181         /* no fb bound */
2182         if (!fb) {
2183                 DRM_ERROR("No FB bound\n");
2184                 return 0;
2185         }
2186
2187         if(intel_crtc->plane > dev_priv->num_pipe) {
2188                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2189                                 intel_crtc->plane,
2190                                 dev_priv->num_pipe);
2191                 return -EINVAL;
2192         }
2193
2194         mutex_lock(&dev->struct_mutex);
2195         ret = intel_pin_and_fence_fb_obj(dev,
2196                                          to_intel_framebuffer(fb)->obj,
2197                                          NULL);
2198         if (ret != 0) {
2199                 mutex_unlock(&dev->struct_mutex);
2200                 DRM_ERROR("pin & fence failed\n");
2201                 return ret;
2202         }
2203
2204         if (crtc->fb)
2205                 intel_finish_fb(crtc->fb);
2206
2207         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2208         if (ret) {
2209                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2210                 mutex_unlock(&dev->struct_mutex);
2211                 DRM_ERROR("failed to update base address\n");
2212                 return ret;
2213         }
2214
2215         old_fb = crtc->fb;
2216         crtc->fb = fb;
2217         crtc->x = x;
2218         crtc->y = y;
2219
2220         if (old_fb) {
2221                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2222                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2223         }
2224
2225         intel_update_fbc(dev);
2226         mutex_unlock(&dev->struct_mutex);
2227
2228         if (!dev->primary->master)
2229                 return 0;
2230
2231         master_priv = dev->primary->master->driver_priv;
2232         if (!master_priv->sarea_priv)
2233                 return 0;
2234
2235         if (intel_crtc->pipe) {
2236                 master_priv->sarea_priv->pipeB_x = x;
2237                 master_priv->sarea_priv->pipeB_y = y;
2238         } else {
2239                 master_priv->sarea_priv->pipeA_x = x;
2240                 master_priv->sarea_priv->pipeA_y = y;
2241         }
2242
2243         return 0;
2244 }
2245
2246 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2247 {
2248         struct drm_device *dev = crtc->dev;
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         u32 dpa_ctl;
2251
2252         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2253         dpa_ctl = I915_READ(DP_A);
2254         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2255
2256         if (clock < 200000) {
2257                 u32 temp;
2258                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2259                 /* workaround for 160Mhz:
2260                    1) program 0x4600c bits 15:0 = 0x8124
2261                    2) program 0x46010 bit 0 = 1
2262                    3) program 0x46034 bit 24 = 1
2263                    4) program 0x64000 bit 14 = 1
2264                    */
2265                 temp = I915_READ(0x4600c);
2266                 temp &= 0xffff0000;
2267                 I915_WRITE(0x4600c, temp | 0x8124);
2268
2269                 temp = I915_READ(0x46010);
2270                 I915_WRITE(0x46010, temp | 1);
2271
2272                 temp = I915_READ(0x46034);
2273                 I915_WRITE(0x46034, temp | (1 << 24));
2274         } else {
2275                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2276         }
2277         I915_WRITE(DP_A, dpa_ctl);
2278
2279         POSTING_READ(DP_A);
2280         udelay(500);
2281 }
2282
2283 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2284 {
2285         struct drm_device *dev = crtc->dev;
2286         struct drm_i915_private *dev_priv = dev->dev_private;
2287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2288         int pipe = intel_crtc->pipe;
2289         u32 reg, temp;
2290
2291         /* enable normal train */
2292         reg = FDI_TX_CTL(pipe);
2293         temp = I915_READ(reg);
2294         if (IS_IVYBRIDGE(dev)) {
2295                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2296                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2297         } else {
2298                 temp &= ~FDI_LINK_TRAIN_NONE;
2299                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2300         }
2301         I915_WRITE(reg, temp);
2302
2303         reg = FDI_RX_CTL(pipe);
2304         temp = I915_READ(reg);
2305         if (HAS_PCH_CPT(dev)) {
2306                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2307                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2308         } else {
2309                 temp &= ~FDI_LINK_TRAIN_NONE;
2310                 temp |= FDI_LINK_TRAIN_NONE;
2311         }
2312         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2313
2314         /* wait one idle pattern time */
2315         POSTING_READ(reg);
2316         udelay(1000);
2317
2318         /* IVB wants error correction enabled */
2319         if (IS_IVYBRIDGE(dev))
2320                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2321                            FDI_FE_ERRC_ENABLE);
2322 }
2323
2324 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2325 {
2326         struct drm_i915_private *dev_priv = dev->dev_private;
2327         u32 flags = I915_READ(SOUTH_CHICKEN1);
2328
2329         flags |= FDI_PHASE_SYNC_OVR(pipe);
2330         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2331         flags |= FDI_PHASE_SYNC_EN(pipe);
2332         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2333         POSTING_READ(SOUTH_CHICKEN1);
2334 }
2335
2336 /* The FDI link training functions for ILK/Ibexpeak. */
2337 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2338 {
2339         struct drm_device *dev = crtc->dev;
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2342         int pipe = intel_crtc->pipe;
2343         int plane = intel_crtc->plane;
2344         u32 reg, temp, tries;
2345
2346         /* FDI needs bits from pipe & plane first */
2347         assert_pipe_enabled(dev_priv, pipe);
2348         assert_plane_enabled(dev_priv, plane);
2349
2350         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2351            for train result */
2352         reg = FDI_RX_IMR(pipe);
2353         temp = I915_READ(reg);
2354         temp &= ~FDI_RX_SYMBOL_LOCK;
2355         temp &= ~FDI_RX_BIT_LOCK;
2356         I915_WRITE(reg, temp);
2357         I915_READ(reg);
2358         udelay(150);
2359
2360         /* enable CPU FDI TX and PCH FDI RX */
2361         reg = FDI_TX_CTL(pipe);
2362         temp = I915_READ(reg);
2363         temp &= ~(7 << 19);
2364         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2365         temp &= ~FDI_LINK_TRAIN_NONE;
2366         temp |= FDI_LINK_TRAIN_PATTERN_1;
2367         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2368
2369         reg = FDI_RX_CTL(pipe);
2370         temp = I915_READ(reg);
2371         temp &= ~FDI_LINK_TRAIN_NONE;
2372         temp |= FDI_LINK_TRAIN_PATTERN_1;
2373         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2374
2375         POSTING_READ(reg);
2376         udelay(150);
2377
2378         /* Ironlake workaround, enable clock pointer after FDI enable*/
2379         if (HAS_PCH_IBX(dev)) {
2380                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2381                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2382                            FDI_RX_PHASE_SYNC_POINTER_EN);
2383         }
2384
2385         reg = FDI_RX_IIR(pipe);
2386         for (tries = 0; tries < 5; tries++) {
2387                 temp = I915_READ(reg);
2388                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2389
2390                 if ((temp & FDI_RX_BIT_LOCK)) {
2391                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2392                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2393                         break;
2394                 }
2395         }
2396         if (tries == 5)
2397                 DRM_ERROR("FDI train 1 fail!\n");
2398
2399         /* Train 2 */
2400         reg = FDI_TX_CTL(pipe);
2401         temp = I915_READ(reg);
2402         temp &= ~FDI_LINK_TRAIN_NONE;
2403         temp |= FDI_LINK_TRAIN_PATTERN_2;
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         temp &= ~FDI_LINK_TRAIN_NONE;
2409         temp |= FDI_LINK_TRAIN_PATTERN_2;
2410         I915_WRITE(reg, temp);
2411
2412         POSTING_READ(reg);
2413         udelay(150);
2414
2415         reg = FDI_RX_IIR(pipe);
2416         for (tries = 0; tries < 5; tries++) {
2417                 temp = I915_READ(reg);
2418                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419
2420                 if (temp & FDI_RX_SYMBOL_LOCK) {
2421                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2422                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2423                         break;
2424                 }
2425         }
2426         if (tries == 5)
2427                 DRM_ERROR("FDI train 2 fail!\n");
2428
2429         DRM_DEBUG_KMS("FDI train done\n");
2430
2431 }
2432
2433 static const int snb_b_fdi_train_param[] = {
2434         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2435         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2436         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2437         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2438 };
2439
2440 /* The FDI link training functions for SNB/Cougarpoint. */
2441 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2442 {
2443         struct drm_device *dev = crtc->dev;
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2446         int pipe = intel_crtc->pipe;
2447         u32 reg, temp, i, retry;
2448
2449         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2450            for train result */
2451         reg = FDI_RX_IMR(pipe);
2452         temp = I915_READ(reg);
2453         temp &= ~FDI_RX_SYMBOL_LOCK;
2454         temp &= ~FDI_RX_BIT_LOCK;
2455         I915_WRITE(reg, temp);
2456
2457         POSTING_READ(reg);
2458         udelay(150);
2459
2460         /* enable CPU FDI TX and PCH FDI RX */
2461         reg = FDI_TX_CTL(pipe);
2462         temp = I915_READ(reg);
2463         temp &= ~(7 << 19);
2464         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2465         temp &= ~FDI_LINK_TRAIN_NONE;
2466         temp |= FDI_LINK_TRAIN_PATTERN_1;
2467         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2468         /* SNB-B */
2469         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2470         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2471
2472         reg = FDI_RX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         if (HAS_PCH_CPT(dev)) {
2475                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2476                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2477         } else {
2478                 temp &= ~FDI_LINK_TRAIN_NONE;
2479                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2480         }
2481         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         if (HAS_PCH_CPT(dev))
2487                 cpt_phase_pointer_enable(dev, pipe);
2488
2489         for (i = 0; i < 4; i++) {
2490                 reg = FDI_TX_CTL(pipe);
2491                 temp = I915_READ(reg);
2492                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493                 temp |= snb_b_fdi_train_param[i];
2494                 I915_WRITE(reg, temp);
2495
2496                 POSTING_READ(reg);
2497                 udelay(500);
2498
2499                 for (retry = 0; retry < 5; retry++) {
2500                         reg = FDI_RX_IIR(pipe);
2501                         temp = I915_READ(reg);
2502                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503                         if (temp & FDI_RX_BIT_LOCK) {
2504                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2505                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2506                                 break;
2507                         }
2508                         udelay(50);
2509                 }
2510                 if (retry < 5)
2511                         break;
2512         }
2513         if (i == 4)
2514                 DRM_ERROR("FDI train 1 fail!\n");
2515
2516         /* Train 2 */
2517         reg = FDI_TX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_2;
2521         if (IS_GEN6(dev)) {
2522                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523                 /* SNB-B */
2524                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2525         }
2526         I915_WRITE(reg, temp);
2527
2528         reg = FDI_RX_CTL(pipe);
2529         temp = I915_READ(reg);
2530         if (HAS_PCH_CPT(dev)) {
2531                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2532                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2533         } else {
2534                 temp &= ~FDI_LINK_TRAIN_NONE;
2535                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2536         }
2537         I915_WRITE(reg, temp);
2538
2539         POSTING_READ(reg);
2540         udelay(150);
2541
2542         for (i = 0; i < 4; i++) {
2543                 reg = FDI_TX_CTL(pipe);
2544                 temp = I915_READ(reg);
2545                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546                 temp |= snb_b_fdi_train_param[i];
2547                 I915_WRITE(reg, temp);
2548
2549                 POSTING_READ(reg);
2550                 udelay(500);
2551
2552                 for (retry = 0; retry < 5; retry++) {
2553                         reg = FDI_RX_IIR(pipe);
2554                         temp = I915_READ(reg);
2555                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2556                         if (temp & FDI_RX_SYMBOL_LOCK) {
2557                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2558                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2559                                 break;
2560                         }
2561                         udelay(50);
2562                 }
2563                 if (retry < 5)
2564                         break;
2565         }
2566         if (i == 4)
2567                 DRM_ERROR("FDI train 2 fail!\n");
2568
2569         DRM_DEBUG_KMS("FDI train done.\n");
2570 }
2571
2572 /* Manual link training for Ivy Bridge A0 parts */
2573 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2574 {
2575         struct drm_device *dev = crtc->dev;
2576         struct drm_i915_private *dev_priv = dev->dev_private;
2577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578         int pipe = intel_crtc->pipe;
2579         u32 reg, temp, i;
2580
2581         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2582            for train result */
2583         reg = FDI_RX_IMR(pipe);
2584         temp = I915_READ(reg);
2585         temp &= ~FDI_RX_SYMBOL_LOCK;
2586         temp &= ~FDI_RX_BIT_LOCK;
2587         I915_WRITE(reg, temp);
2588
2589         POSTING_READ(reg);
2590         udelay(150);
2591
2592         /* enable CPU FDI TX and PCH FDI RX */
2593         reg = FDI_TX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~(7 << 19);
2596         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2597         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2598         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2599         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2600         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2601         temp |= FDI_COMPOSITE_SYNC;
2602         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2603
2604         reg = FDI_RX_CTL(pipe);
2605         temp = I915_READ(reg);
2606         temp &= ~FDI_LINK_TRAIN_AUTO;
2607         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2609         temp |= FDI_COMPOSITE_SYNC;
2610         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         if (HAS_PCH_CPT(dev))
2616                 cpt_phase_pointer_enable(dev, pipe);
2617
2618         for (i = 0; i < 4; i++) {
2619                 reg = FDI_TX_CTL(pipe);
2620                 temp = I915_READ(reg);
2621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622                 temp |= snb_b_fdi_train_param[i];
2623                 I915_WRITE(reg, temp);
2624
2625                 POSTING_READ(reg);
2626                 udelay(500);
2627
2628                 reg = FDI_RX_IIR(pipe);
2629                 temp = I915_READ(reg);
2630                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632                 if (temp & FDI_RX_BIT_LOCK ||
2633                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2634                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2635                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2636                         break;
2637                 }
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 1 fail!\n");
2641
2642         /* Train 2 */
2643         reg = FDI_TX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2647         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2649         I915_WRITE(reg, temp);
2650
2651         reg = FDI_RX_CTL(pipe);
2652         temp = I915_READ(reg);
2653         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2655         I915_WRITE(reg, temp);
2656
2657         POSTING_READ(reg);
2658         udelay(150);
2659
2660         for (i = 0; i < 4; i++) {
2661                 reg = FDI_TX_CTL(pipe);
2662                 temp = I915_READ(reg);
2663                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664                 temp |= snb_b_fdi_train_param[i];
2665                 I915_WRITE(reg, temp);
2666
2667                 POSTING_READ(reg);
2668                 udelay(500);
2669
2670                 reg = FDI_RX_IIR(pipe);
2671                 temp = I915_READ(reg);
2672                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673
2674                 if (temp & FDI_RX_SYMBOL_LOCK) {
2675                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2676                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2677                         break;
2678                 }
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 2 fail!\n");
2682
2683         DRM_DEBUG_KMS("FDI train done.\n");
2684 }
2685
2686 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2687 {
2688         struct drm_device *dev = intel_crtc->base.dev;
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         int pipe = intel_crtc->pipe;
2691         u32 reg, temp;
2692
2693         /* Write the TU size bits so error detection works */
2694         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2695                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2696
2697         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2698         reg = FDI_RX_CTL(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~((0x7 << 19) | (0x7 << 16));
2701         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2702         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2703         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2704
2705         POSTING_READ(reg);
2706         udelay(200);
2707
2708         /* Switch from Rawclk to PCDclk */
2709         temp = I915_READ(reg);
2710         I915_WRITE(reg, temp | FDI_PCDCLK);
2711
2712         POSTING_READ(reg);
2713         udelay(200);
2714
2715         /* On Haswell, the PLL configuration for ports and pipes is handled
2716          * separately, as part of DDI setup */
2717         if (!IS_HASWELL(dev)) {
2718                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2719                 reg = FDI_TX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2722                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2723
2724                         POSTING_READ(reg);
2725                         udelay(100);
2726                 }
2727         }
2728 }
2729
2730 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2731 {
2732         struct drm_device *dev = intel_crtc->base.dev;
2733         struct drm_i915_private *dev_priv = dev->dev_private;
2734         int pipe = intel_crtc->pipe;
2735         u32 reg, temp;
2736
2737         /* Switch from PCDclk to Rawclk */
2738         reg = FDI_RX_CTL(pipe);
2739         temp = I915_READ(reg);
2740         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2741
2742         /* Disable CPU FDI TX PLL */
2743         reg = FDI_TX_CTL(pipe);
2744         temp = I915_READ(reg);
2745         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2746
2747         POSTING_READ(reg);
2748         udelay(100);
2749
2750         reg = FDI_RX_CTL(pipe);
2751         temp = I915_READ(reg);
2752         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2753
2754         /* Wait for the clocks to turn off. */
2755         POSTING_READ(reg);
2756         udelay(100);
2757 }
2758
2759 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2760 {
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         u32 flags = I915_READ(SOUTH_CHICKEN1);
2763
2764         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2765         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2766         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2767         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2768         POSTING_READ(SOUTH_CHICKEN1);
2769 }
2770 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2771 {
2772         struct drm_device *dev = crtc->dev;
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2775         int pipe = intel_crtc->pipe;
2776         u32 reg, temp;
2777
2778         /* disable CPU FDI tx and PCH FDI rx */
2779         reg = FDI_TX_CTL(pipe);
2780         temp = I915_READ(reg);
2781         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2782         POSTING_READ(reg);
2783
2784         reg = FDI_RX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         temp &= ~(0x7 << 16);
2787         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2788         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2789
2790         POSTING_READ(reg);
2791         udelay(100);
2792
2793         /* Ironlake workaround, disable clock pointer after downing FDI */
2794         if (HAS_PCH_IBX(dev)) {
2795                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2796                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2797                            I915_READ(FDI_RX_CHICKEN(pipe) &
2798                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2799         } else if (HAS_PCH_CPT(dev)) {
2800                 cpt_phase_pointer_disable(dev, pipe);
2801         }
2802
2803         /* still set train pattern 1 */
2804         reg = FDI_TX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         temp &= ~FDI_LINK_TRAIN_NONE;
2807         temp |= FDI_LINK_TRAIN_PATTERN_1;
2808         I915_WRITE(reg, temp);
2809
2810         reg = FDI_RX_CTL(pipe);
2811         temp = I915_READ(reg);
2812         if (HAS_PCH_CPT(dev)) {
2813                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2814                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2815         } else {
2816                 temp &= ~FDI_LINK_TRAIN_NONE;
2817                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2818         }
2819         /* BPC in FDI rx is consistent with that in PIPECONF */
2820         temp &= ~(0x07 << 16);
2821         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2822         I915_WRITE(reg, temp);
2823
2824         POSTING_READ(reg);
2825         udelay(100);
2826 }
2827
2828 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2829 {
2830         struct drm_device *dev = crtc->dev;
2831         struct drm_i915_private *dev_priv = dev->dev_private;
2832         unsigned long flags;
2833         bool pending;
2834
2835         if (atomic_read(&dev_priv->mm.wedged))
2836                 return false;
2837
2838         spin_lock_irqsave(&dev->event_lock, flags);
2839         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2840         spin_unlock_irqrestore(&dev->event_lock, flags);
2841
2842         return pending;
2843 }
2844
2845 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850         if (crtc->fb == NULL)
2851                 return;
2852
2853         wait_event(dev_priv->pending_flip_queue,
2854                    !intel_crtc_has_pending_flip(crtc));
2855
2856         mutex_lock(&dev->struct_mutex);
2857         intel_finish_fb(crtc->fb);
2858         mutex_unlock(&dev->struct_mutex);
2859 }
2860
2861 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2862 {
2863         struct drm_device *dev = crtc->dev;
2864         struct intel_encoder *intel_encoder;
2865
2866         /*
2867          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2868          * must be driven by its own crtc; no sharing is possible.
2869          */
2870         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2871                 switch (intel_encoder->type) {
2872                 case INTEL_OUTPUT_EDP:
2873                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2874                                 return false;
2875                         continue;
2876                 }
2877         }
2878
2879         return true;
2880 }
2881
2882 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2883 {
2884         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2885 }
2886
2887 /* Program iCLKIP clock to the desired frequency */
2888 static void lpt_program_iclkip(struct drm_crtc *crtc)
2889 {
2890         struct drm_device *dev = crtc->dev;
2891         struct drm_i915_private *dev_priv = dev->dev_private;
2892         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2893         u32 temp;
2894
2895         /* It is necessary to ungate the pixclk gate prior to programming
2896          * the divisors, and gate it back when it is done.
2897          */
2898         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2899
2900         /* Disable SSCCTL */
2901         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2902                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2903                                         SBI_SSCCTL_DISABLE);
2904
2905         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2906         if (crtc->mode.clock == 20000) {
2907                 auxdiv = 1;
2908                 divsel = 0x41;
2909                 phaseinc = 0x20;
2910         } else {
2911                 /* The iCLK virtual clock root frequency is in MHz,
2912                  * but the crtc->mode.clock in in KHz. To get the divisors,
2913                  * it is necessary to divide one by another, so we
2914                  * convert the virtual clock precision to KHz here for higher
2915                  * precision.
2916                  */
2917                 u32 iclk_virtual_root_freq = 172800 * 1000;
2918                 u32 iclk_pi_range = 64;
2919                 u32 desired_divisor, msb_divisor_value, pi_value;
2920
2921                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2922                 msb_divisor_value = desired_divisor / iclk_pi_range;
2923                 pi_value = desired_divisor % iclk_pi_range;
2924
2925                 auxdiv = 0;
2926                 divsel = msb_divisor_value - 2;
2927                 phaseinc = pi_value;
2928         }
2929
2930         /* This should not happen with any sane values */
2931         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2932                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2933         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2934                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2935
2936         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2937                         crtc->mode.clock,
2938                         auxdiv,
2939                         divsel,
2940                         phasedir,
2941                         phaseinc);
2942
2943         /* Program SSCDIVINTPHASE6 */
2944         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2945         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2946         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2947         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2948         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2949         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2950         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2951
2952         intel_sbi_write(dev_priv,
2953                         SBI_SSCDIVINTPHASE6,
2954                         temp);
2955
2956         /* Program SSCAUXDIV */
2957         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2958         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2959         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2960         intel_sbi_write(dev_priv,
2961                         SBI_SSCAUXDIV6,
2962                         temp);
2963
2964
2965         /* Enable modulator and associated divider */
2966         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2967         temp &= ~SBI_SSCCTL_DISABLE;
2968         intel_sbi_write(dev_priv,
2969                         SBI_SSCCTL6,
2970                         temp);
2971
2972         /* Wait for initialization time */
2973         udelay(24);
2974
2975         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2976 }
2977
2978 /*
2979  * Enable PCH resources required for PCH ports:
2980  *   - PCH PLLs
2981  *   - FDI training & RX/TX
2982  *   - update transcoder timings
2983  *   - DP transcoding bits
2984  *   - transcoder
2985  */
2986 static void ironlake_pch_enable(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct drm_i915_private *dev_priv = dev->dev_private;
2990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2991         int pipe = intel_crtc->pipe;
2992         u32 reg, temp;
2993
2994         assert_transcoder_disabled(dev_priv, pipe);
2995
2996         /* For PCH output, training FDI link */
2997         dev_priv->display.fdi_link_train(crtc);
2998
2999         intel_enable_pch_pll(intel_crtc);
3000
3001         if (HAS_PCH_LPT(dev)) {
3002                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3003                 lpt_program_iclkip(crtc);
3004         } else if (HAS_PCH_CPT(dev)) {
3005                 u32 sel;
3006
3007                 temp = I915_READ(PCH_DPLL_SEL);
3008                 switch (pipe) {
3009                 default:
3010                 case 0:
3011                         temp |= TRANSA_DPLL_ENABLE;
3012                         sel = TRANSA_DPLLB_SEL;
3013                         break;
3014                 case 1:
3015                         temp |= TRANSB_DPLL_ENABLE;
3016                         sel = TRANSB_DPLLB_SEL;
3017                         break;
3018                 case 2:
3019                         temp |= TRANSC_DPLL_ENABLE;
3020                         sel = TRANSC_DPLLB_SEL;
3021                         break;
3022                 }
3023                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3024                         temp |= sel;
3025                 else
3026                         temp &= ~sel;
3027                 I915_WRITE(PCH_DPLL_SEL, temp);
3028         }
3029
3030         /* set transcoder timing, panel must allow it */
3031         assert_panel_unlocked(dev_priv, pipe);
3032         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3033         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3034         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3035
3036         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3037         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3038         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3039         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3040
3041         if (!IS_HASWELL(dev))
3042                 intel_fdi_normal_train(crtc);
3043
3044         /* For PCH DP, enable TRANS_DP_CTL */
3045         if (HAS_PCH_CPT(dev) &&
3046             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3047              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3048                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3049                 reg = TRANS_DP_CTL(pipe);
3050                 temp = I915_READ(reg);
3051                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3052                           TRANS_DP_SYNC_MASK |
3053                           TRANS_DP_BPC_MASK);
3054                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3055                          TRANS_DP_ENH_FRAMING);
3056                 temp |= bpc << 9; /* same format but at 11:9 */
3057
3058                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3059                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3060                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3061                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3062
3063                 switch (intel_trans_dp_port_sel(crtc)) {
3064                 case PCH_DP_B:
3065                         temp |= TRANS_DP_PORT_SEL_B;
3066                         break;
3067                 case PCH_DP_C:
3068                         temp |= TRANS_DP_PORT_SEL_C;
3069                         break;
3070                 case PCH_DP_D:
3071                         temp |= TRANS_DP_PORT_SEL_D;
3072                         break;
3073                 default:
3074                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3075                         temp |= TRANS_DP_PORT_SEL_B;
3076                         break;
3077                 }
3078
3079                 I915_WRITE(reg, temp);
3080         }
3081
3082         intel_enable_transcoder(dev_priv, pipe);
3083 }
3084
3085 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3086 {
3087         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3088
3089         if (pll == NULL)
3090                 return;
3091
3092         if (pll->refcount == 0) {
3093                 WARN(1, "bad PCH PLL refcount\n");
3094                 return;
3095         }
3096
3097         --pll->refcount;
3098         intel_crtc->pch_pll = NULL;
3099 }
3100
3101 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3102 {
3103         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3104         struct intel_pch_pll *pll;
3105         int i;
3106
3107         pll = intel_crtc->pch_pll;
3108         if (pll) {
3109                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3110                               intel_crtc->base.base.id, pll->pll_reg);
3111                 goto prepare;
3112         }
3113
3114         if (HAS_PCH_IBX(dev_priv->dev)) {
3115                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3116                 i = intel_crtc->pipe;
3117                 pll = &dev_priv->pch_plls[i];
3118
3119                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3120                               intel_crtc->base.base.id, pll->pll_reg);
3121
3122                 goto found;
3123         }
3124
3125         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3126                 pll = &dev_priv->pch_plls[i];
3127
3128                 /* Only want to check enabled timings first */
3129                 if (pll->refcount == 0)
3130                         continue;
3131
3132                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3133                     fp == I915_READ(pll->fp0_reg)) {
3134                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3135                                       intel_crtc->base.base.id,
3136                                       pll->pll_reg, pll->refcount, pll->active);
3137
3138                         goto found;
3139                 }
3140         }
3141
3142         /* Ok no matching timings, maybe there's a free one? */
3143         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3144                 pll = &dev_priv->pch_plls[i];
3145                 if (pll->refcount == 0) {
3146                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3147                                       intel_crtc->base.base.id, pll->pll_reg);
3148                         goto found;
3149                 }
3150         }
3151
3152         return NULL;
3153
3154 found:
3155         intel_crtc->pch_pll = pll;
3156         pll->refcount++;
3157         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3158 prepare: /* separate function? */
3159         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3160
3161         /* Wait for the clocks to stabilize before rewriting the regs */
3162         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3163         POSTING_READ(pll->pll_reg);
3164         udelay(150);
3165
3166         I915_WRITE(pll->fp0_reg, fp);
3167         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3168         pll->on = false;
3169         return pll;
3170 }
3171
3172 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3173 {
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3176         u32 temp;
3177
3178         temp = I915_READ(dslreg);
3179         udelay(500);
3180         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3181                 /* Without this, mode sets may fail silently on FDI */
3182                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3183                 udelay(250);
3184                 I915_WRITE(tc2reg, 0);
3185                 if (wait_for(I915_READ(dslreg) != temp, 5))
3186                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3187         }
3188 }
3189
3190 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3191 {
3192         struct drm_device *dev = crtc->dev;
3193         struct drm_i915_private *dev_priv = dev->dev_private;
3194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3195         struct intel_encoder *encoder;
3196         int pipe = intel_crtc->pipe;
3197         int plane = intel_crtc->plane;
3198         u32 temp;
3199         bool is_pch_port;
3200
3201         WARN_ON(!crtc->enabled);
3202
3203         if (intel_crtc->active)
3204                 return;
3205
3206         intel_crtc->active = true;
3207         intel_update_watermarks(dev);
3208
3209         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3210                 temp = I915_READ(PCH_LVDS);
3211                 if ((temp & LVDS_PORT_EN) == 0)
3212                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3213         }
3214
3215         is_pch_port = ironlake_crtc_driving_pch(crtc);
3216
3217         if (is_pch_port) {
3218                 ironlake_fdi_pll_enable(intel_crtc);
3219         } else {
3220                 assert_fdi_tx_disabled(dev_priv, pipe);
3221                 assert_fdi_rx_disabled(dev_priv, pipe);
3222         }
3223
3224         for_each_encoder_on_crtc(dev, crtc, encoder)
3225                 if (encoder->pre_enable)
3226                         encoder->pre_enable(encoder);
3227
3228         /* Enable panel fitting for LVDS */
3229         if (dev_priv->pch_pf_size &&
3230             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3231                 /* Force use of hard-coded filter coefficients
3232                  * as some pre-programmed values are broken,
3233                  * e.g. x201.
3234                  */
3235                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3236                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3237                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3238         }
3239
3240         /*
3241          * On ILK+ LUT must be loaded before the pipe is running but with
3242          * clocks enabled
3243          */
3244         intel_crtc_load_lut(crtc);
3245
3246         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3247         intel_enable_plane(dev_priv, plane, pipe);
3248
3249         if (is_pch_port)
3250                 ironlake_pch_enable(crtc);
3251
3252         mutex_lock(&dev->struct_mutex);
3253         intel_update_fbc(dev);
3254         mutex_unlock(&dev->struct_mutex);
3255
3256         intel_crtc_update_cursor(crtc, true);
3257
3258         for_each_encoder_on_crtc(dev, crtc, encoder)
3259                 encoder->enable(encoder);
3260
3261         if (HAS_PCH_CPT(dev))
3262                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3263
3264         /*
3265          * There seems to be a race in PCH platform hw (at least on some
3266          * outputs) where an enabled pipe still completes any pageflip right
3267          * away (as if the pipe is off) instead of waiting for vblank. As soon
3268          * as the first vblank happend, everything works as expected. Hence just
3269          * wait for one vblank before returning to avoid strange things
3270          * happening.
3271          */
3272         intel_wait_for_vblank(dev, intel_crtc->pipe);
3273 }
3274
3275 static void haswell_crtc_enable(struct drm_crtc *crtc)
3276 {
3277         struct drm_device *dev = crtc->dev;
3278         struct drm_i915_private *dev_priv = dev->dev_private;
3279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3280         struct intel_encoder *encoder;
3281         int pipe = intel_crtc->pipe;
3282         int plane = intel_crtc->plane;
3283         bool is_pch_port;
3284
3285         WARN_ON(!crtc->enabled);
3286
3287         if (intel_crtc->active)
3288                 return;
3289
3290         intel_crtc->active = true;
3291         intel_update_watermarks(dev);
3292
3293         is_pch_port = haswell_crtc_driving_pch(crtc);
3294
3295         if (is_pch_port)
3296                 ironlake_fdi_pll_enable(intel_crtc);
3297
3298         for_each_encoder_on_crtc(dev, crtc, encoder)
3299                 if (encoder->pre_enable)
3300                         encoder->pre_enable(encoder);
3301
3302         intel_ddi_enable_pipe_clock(intel_crtc);
3303
3304         /* Enable panel fitting for eDP */
3305         if (dev_priv->pch_pf_size && HAS_eDP) {
3306                 /* Force use of hard-coded filter coefficients
3307                  * as some pre-programmed values are broken,
3308                  * e.g. x201.
3309                  */
3310                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3311                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3312                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3313         }
3314
3315         /*
3316          * On ILK+ LUT must be loaded before the pipe is running but with
3317          * clocks enabled
3318          */
3319         intel_crtc_load_lut(crtc);
3320
3321         intel_ddi_set_pipe_settings(crtc);
3322         intel_ddi_enable_pipe_func(crtc);
3323
3324         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3325         intel_enable_plane(dev_priv, plane, pipe);
3326
3327         if (is_pch_port)
3328                 ironlake_pch_enable(crtc);
3329
3330         mutex_lock(&dev->struct_mutex);
3331         intel_update_fbc(dev);
3332         mutex_unlock(&dev->struct_mutex);
3333
3334         intel_crtc_update_cursor(crtc, true);
3335
3336         for_each_encoder_on_crtc(dev, crtc, encoder)
3337                 encoder->enable(encoder);
3338
3339         /*
3340          * There seems to be a race in PCH platform hw (at least on some
3341          * outputs) where an enabled pipe still completes any pageflip right
3342          * away (as if the pipe is off) instead of waiting for vblank. As soon
3343          * as the first vblank happend, everything works as expected. Hence just
3344          * wait for one vblank before returning to avoid strange things
3345          * happening.
3346          */
3347         intel_wait_for_vblank(dev, intel_crtc->pipe);
3348 }
3349
3350 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         struct intel_encoder *encoder;
3356         int pipe = intel_crtc->pipe;
3357         int plane = intel_crtc->plane;
3358         u32 reg, temp;
3359
3360
3361         if (!intel_crtc->active)
3362                 return;
3363
3364         for_each_encoder_on_crtc(dev, crtc, encoder)
3365                 encoder->disable(encoder);
3366
3367         intel_crtc_wait_for_pending_flips(crtc);
3368         drm_vblank_off(dev, pipe);
3369         intel_crtc_update_cursor(crtc, false);
3370
3371         intel_disable_plane(dev_priv, plane, pipe);
3372
3373         if (dev_priv->cfb_plane == plane)
3374                 intel_disable_fbc(dev);
3375
3376         intel_disable_pipe(dev_priv, pipe);
3377
3378         /* Disable PF */
3379         I915_WRITE(PF_CTL(pipe), 0);
3380         I915_WRITE(PF_WIN_SZ(pipe), 0);
3381
3382         for_each_encoder_on_crtc(dev, crtc, encoder)
3383                 if (encoder->post_disable)
3384                         encoder->post_disable(encoder);
3385
3386         ironlake_fdi_disable(crtc);
3387
3388         intel_disable_transcoder(dev_priv, pipe);
3389
3390         if (HAS_PCH_CPT(dev)) {
3391                 /* disable TRANS_DP_CTL */
3392                 reg = TRANS_DP_CTL(pipe);
3393                 temp = I915_READ(reg);
3394                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3395                 temp |= TRANS_DP_PORT_SEL_NONE;
3396                 I915_WRITE(reg, temp);
3397
3398                 /* disable DPLL_SEL */
3399                 temp = I915_READ(PCH_DPLL_SEL);
3400                 switch (pipe) {
3401                 case 0:
3402                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3403                         break;
3404                 case 1:
3405                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3406                         break;
3407                 case 2:
3408                         /* C shares PLL A or B */
3409                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3410                         break;
3411                 default:
3412                         BUG(); /* wtf */
3413                 }
3414                 I915_WRITE(PCH_DPLL_SEL, temp);
3415         }
3416
3417         /* disable PCH DPLL */
3418         intel_disable_pch_pll(intel_crtc);
3419
3420         ironlake_fdi_pll_disable(intel_crtc);
3421
3422         intel_crtc->active = false;
3423         intel_update_watermarks(dev);
3424
3425         mutex_lock(&dev->struct_mutex);
3426         intel_update_fbc(dev);
3427         mutex_unlock(&dev->struct_mutex);
3428 }
3429
3430 static void haswell_crtc_disable(struct drm_crtc *crtc)
3431 {
3432         struct drm_device *dev = crtc->dev;
3433         struct drm_i915_private *dev_priv = dev->dev_private;
3434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3435         struct intel_encoder *encoder;
3436         int pipe = intel_crtc->pipe;
3437         int plane = intel_crtc->plane;
3438         bool is_pch_port;
3439
3440         if (!intel_crtc->active)
3441                 return;
3442
3443         is_pch_port = haswell_crtc_driving_pch(crtc);
3444
3445         for_each_encoder_on_crtc(dev, crtc, encoder)
3446                 encoder->disable(encoder);
3447
3448         intel_crtc_wait_for_pending_flips(crtc);
3449         drm_vblank_off(dev, pipe);
3450         intel_crtc_update_cursor(crtc, false);
3451
3452         intel_disable_plane(dev_priv, plane, pipe);
3453
3454         if (dev_priv->cfb_plane == plane)
3455                 intel_disable_fbc(dev);
3456
3457         intel_disable_pipe(dev_priv, pipe);
3458
3459         intel_ddi_disable_pipe_func(dev_priv, pipe);
3460
3461         /* Disable PF */
3462         I915_WRITE(PF_CTL(pipe), 0);
3463         I915_WRITE(PF_WIN_SZ(pipe), 0);
3464
3465         intel_ddi_disable_pipe_clock(intel_crtc);
3466
3467         for_each_encoder_on_crtc(dev, crtc, encoder)
3468                 if (encoder->post_disable)
3469                         encoder->post_disable(encoder);
3470
3471         if (is_pch_port) {
3472                 ironlake_fdi_disable(crtc);
3473                 intel_disable_transcoder(dev_priv, pipe);
3474                 intel_disable_pch_pll(intel_crtc);
3475                 ironlake_fdi_pll_disable(intel_crtc);
3476         }
3477
3478         intel_crtc->active = false;
3479         intel_update_watermarks(dev);
3480
3481         mutex_lock(&dev->struct_mutex);
3482         intel_update_fbc(dev);
3483         mutex_unlock(&dev->struct_mutex);
3484 }
3485
3486 static void ironlake_crtc_off(struct drm_crtc *crtc)
3487 {
3488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3489         intel_put_pch_pll(intel_crtc);
3490 }
3491
3492 static void haswell_crtc_off(struct drm_crtc *crtc)
3493 {
3494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495
3496         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3497          * start using it. */
3498         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3499
3500         intel_ddi_put_crtc_pll(crtc);
3501 }
3502
3503 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3504 {
3505         if (!enable && intel_crtc->overlay) {
3506                 struct drm_device *dev = intel_crtc->base.dev;
3507                 struct drm_i915_private *dev_priv = dev->dev_private;
3508
3509                 mutex_lock(&dev->struct_mutex);
3510                 dev_priv->mm.interruptible = false;
3511                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3512                 dev_priv->mm.interruptible = true;
3513                 mutex_unlock(&dev->struct_mutex);
3514         }
3515
3516         /* Let userspace switch the overlay on again. In most cases userspace
3517          * has to recompute where to put it anyway.
3518          */
3519 }
3520
3521 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526         struct intel_encoder *encoder;
3527         int pipe = intel_crtc->pipe;
3528         int plane = intel_crtc->plane;
3529
3530         WARN_ON(!crtc->enabled);
3531
3532         if (intel_crtc->active)
3533                 return;
3534
3535         intel_crtc->active = true;
3536         intel_update_watermarks(dev);
3537
3538         intel_enable_pll(dev_priv, pipe);
3539         intel_enable_pipe(dev_priv, pipe, false);
3540         intel_enable_plane(dev_priv, plane, pipe);
3541
3542         intel_crtc_load_lut(crtc);
3543         intel_update_fbc(dev);
3544
3545         /* Give the overlay scaler a chance to enable if it's on this pipe */
3546         intel_crtc_dpms_overlay(intel_crtc, true);
3547         intel_crtc_update_cursor(crtc, true);
3548
3549         for_each_encoder_on_crtc(dev, crtc, encoder)
3550                 encoder->enable(encoder);
3551 }
3552
3553 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3554 {
3555         struct drm_device *dev = crtc->dev;
3556         struct drm_i915_private *dev_priv = dev->dev_private;
3557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558         struct intel_encoder *encoder;
3559         int pipe = intel_crtc->pipe;
3560         int plane = intel_crtc->plane;
3561
3562
3563         if (!intel_crtc->active)
3564                 return;
3565
3566         for_each_encoder_on_crtc(dev, crtc, encoder)
3567                 encoder->disable(encoder);
3568
3569         /* Give the overlay scaler a chance to disable if it's on this pipe */
3570         intel_crtc_wait_for_pending_flips(crtc);
3571         drm_vblank_off(dev, pipe);
3572         intel_crtc_dpms_overlay(intel_crtc, false);
3573         intel_crtc_update_cursor(crtc, false);
3574
3575         if (dev_priv->cfb_plane == plane)
3576                 intel_disable_fbc(dev);
3577
3578         intel_disable_plane(dev_priv, plane, pipe);
3579         intel_disable_pipe(dev_priv, pipe);
3580         intel_disable_pll(dev_priv, pipe);
3581
3582         intel_crtc->active = false;
3583         intel_update_fbc(dev);
3584         intel_update_watermarks(dev);
3585 }
3586
3587 static void i9xx_crtc_off(struct drm_crtc *crtc)
3588 {
3589 }
3590
3591 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3592                                     bool enabled)
3593 {
3594         struct drm_device *dev = crtc->dev;
3595         struct drm_i915_master_private *master_priv;
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         int pipe = intel_crtc->pipe;
3598
3599         if (!dev->primary->master)
3600                 return;
3601
3602         master_priv = dev->primary->master->driver_priv;
3603         if (!master_priv->sarea_priv)
3604                 return;
3605
3606         switch (pipe) {
3607         case 0:
3608                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3609                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3610                 break;
3611         case 1:
3612                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3613                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3614                 break;
3615         default:
3616                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3617                 break;
3618         }
3619 }
3620
3621 /**
3622  * Sets the power management mode of the pipe and plane.
3623  */
3624 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_encoder *intel_encoder;
3629         bool enable = false;
3630
3631         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3632                 enable |= intel_encoder->connectors_active;
3633
3634         if (enable)
3635                 dev_priv->display.crtc_enable(crtc);
3636         else
3637                 dev_priv->display.crtc_disable(crtc);
3638
3639         intel_crtc_update_sarea(crtc, enable);
3640 }
3641
3642 static void intel_crtc_noop(struct drm_crtc *crtc)
3643 {
3644 }
3645
3646 static void intel_crtc_disable(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_connector *connector;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651
3652         /* crtc should still be enabled when we disable it. */
3653         WARN_ON(!crtc->enabled);
3654
3655         dev_priv->display.crtc_disable(crtc);
3656         intel_crtc_update_sarea(crtc, false);
3657         dev_priv->display.off(crtc);
3658
3659         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3660         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3661
3662         if (crtc->fb) {
3663                 mutex_lock(&dev->struct_mutex);
3664                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3665                 mutex_unlock(&dev->struct_mutex);
3666                 crtc->fb = NULL;
3667         }
3668
3669         /* Update computed state. */
3670         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3671                 if (!connector->encoder || !connector->encoder->crtc)
3672                         continue;
3673
3674                 if (connector->encoder->crtc != crtc)
3675                         continue;
3676
3677                 connector->dpms = DRM_MODE_DPMS_OFF;
3678                 to_intel_encoder(connector->encoder)->connectors_active = false;
3679         }
3680 }
3681
3682 void intel_modeset_disable(struct drm_device *dev)
3683 {
3684         struct drm_crtc *crtc;
3685
3686         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3687                 if (crtc->enabled)
3688                         intel_crtc_disable(crtc);
3689         }
3690 }
3691
3692 void intel_encoder_noop(struct drm_encoder *encoder)
3693 {
3694 }
3695
3696 void intel_encoder_destroy(struct drm_encoder *encoder)
3697 {
3698         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3699
3700         drm_encoder_cleanup(encoder);
3701         kfree(intel_encoder);
3702 }
3703
3704 /* Simple dpms helper for encodres with just one connector, no cloning and only
3705  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3706  * state of the entire output pipe. */
3707 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3708 {
3709         if (mode == DRM_MODE_DPMS_ON) {
3710                 encoder->connectors_active = true;
3711
3712                 intel_crtc_update_dpms(encoder->base.crtc);
3713         } else {
3714                 encoder->connectors_active = false;
3715
3716                 intel_crtc_update_dpms(encoder->base.crtc);
3717         }
3718 }
3719
3720 /* Cross check the actual hw state with our own modeset state tracking (and it's
3721  * internal consistency). */
3722 static void intel_connector_check_state(struct intel_connector *connector)
3723 {
3724         if (connector->get_hw_state(connector)) {
3725                 struct intel_encoder *encoder = connector->encoder;
3726                 struct drm_crtc *crtc;
3727                 bool encoder_enabled;
3728                 enum pipe pipe;
3729
3730                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3731                               connector->base.base.id,
3732                               drm_get_connector_name(&connector->base));
3733
3734                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3735                      "wrong connector dpms state\n");
3736                 WARN(connector->base.encoder != &encoder->base,
3737                      "active connector not linked to encoder\n");
3738                 WARN(!encoder->connectors_active,
3739                      "encoder->connectors_active not set\n");
3740
3741                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3742                 WARN(!encoder_enabled, "encoder not enabled\n");
3743                 if (WARN_ON(!encoder->base.crtc))
3744                         return;
3745
3746                 crtc = encoder->base.crtc;
3747
3748                 WARN(!crtc->enabled, "crtc not enabled\n");
3749                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3750                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3751                      "encoder active on the wrong pipe\n");
3752         }
3753 }
3754
3755 /* Even simpler default implementation, if there's really no special case to
3756  * consider. */
3757 void intel_connector_dpms(struct drm_connector *connector, int mode)
3758 {
3759         struct intel_encoder *encoder = intel_attached_encoder(connector);
3760
3761         /* All the simple cases only support two dpms states. */
3762         if (mode != DRM_MODE_DPMS_ON)
3763                 mode = DRM_MODE_DPMS_OFF;
3764
3765         if (mode == connector->dpms)
3766                 return;
3767
3768         connector->dpms = mode;
3769
3770         /* Only need to change hw state when actually enabled */
3771         if (encoder->base.crtc)
3772                 intel_encoder_dpms(encoder, mode);
3773         else
3774                 WARN_ON(encoder->connectors_active != false);
3775
3776         intel_modeset_check_state(connector->dev);
3777 }
3778
3779 /* Simple connector->get_hw_state implementation for encoders that support only
3780  * one connector and no cloning and hence the encoder state determines the state
3781  * of the connector. */
3782 bool intel_connector_get_hw_state(struct intel_connector *connector)
3783 {
3784         enum pipe pipe = 0;
3785         struct intel_encoder *encoder = connector->encoder;
3786
3787         return encoder->get_hw_state(encoder, &pipe);
3788 }
3789
3790 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3791                                   const struct drm_display_mode *mode,
3792                                   struct drm_display_mode *adjusted_mode)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795
3796         if (HAS_PCH_SPLIT(dev)) {
3797                 /* FDI link clock is fixed at 2.7G */
3798                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3799                         return false;
3800         }
3801
3802         /* All interlaced capable intel hw wants timings in frames. Note though
3803          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3804          * timings, so we need to be careful not to clobber these.*/
3805         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3806                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3807
3808         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3809          * with a hsync front porch of 0.
3810          */
3811         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3812                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3813                 return false;
3814
3815         return true;
3816 }
3817
3818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3819 {
3820         return 400000; /* FIXME */
3821 }
3822
3823 static int i945_get_display_clock_speed(struct drm_device *dev)
3824 {
3825         return 400000;
3826 }
3827
3828 static int i915_get_display_clock_speed(struct drm_device *dev)
3829 {
3830         return 333000;
3831 }
3832
3833 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3834 {
3835         return 200000;
3836 }
3837
3838 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3839 {
3840         u16 gcfgc = 0;
3841
3842         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3843
3844         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3845                 return 133000;
3846         else {
3847                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3848                 case GC_DISPLAY_CLOCK_333_MHZ:
3849                         return 333000;
3850                 default:
3851                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3852                         return 190000;
3853                 }
3854         }
3855 }
3856
3857 static int i865_get_display_clock_speed(struct drm_device *dev)
3858 {
3859         return 266000;
3860 }
3861
3862 static int i855_get_display_clock_speed(struct drm_device *dev)
3863 {
3864         u16 hpllcc = 0;
3865         /* Assume that the hardware is in the high speed state.  This
3866          * should be the default.
3867          */
3868         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3869         case GC_CLOCK_133_200:
3870         case GC_CLOCK_100_200:
3871                 return 200000;
3872         case GC_CLOCK_166_250:
3873                 return 250000;
3874         case GC_CLOCK_100_133:
3875                 return 133000;
3876         }
3877
3878         /* Shouldn't happen */
3879         return 0;
3880 }
3881
3882 static int i830_get_display_clock_speed(struct drm_device *dev)
3883 {
3884         return 133000;
3885 }
3886
3887 struct fdi_m_n {
3888         u32        tu;
3889         u32        gmch_m;
3890         u32        gmch_n;
3891         u32        link_m;
3892         u32        link_n;
3893 };
3894
3895 static void
3896 fdi_reduce_ratio(u32 *num, u32 *den)
3897 {
3898         while (*num > 0xffffff || *den > 0xffffff) {
3899                 *num >>= 1;
3900                 *den >>= 1;
3901         }
3902 }
3903
3904 static void
3905 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3906                      int link_clock, struct fdi_m_n *m_n)
3907 {
3908         m_n->tu = 64; /* default size */
3909
3910         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3911         m_n->gmch_m = bits_per_pixel * pixel_clock;
3912         m_n->gmch_n = link_clock * nlanes * 8;
3913         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3914
3915         m_n->link_m = pixel_clock;
3916         m_n->link_n = link_clock;
3917         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3918 }
3919
3920 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3921 {
3922         if (i915_panel_use_ssc >= 0)
3923                 return i915_panel_use_ssc != 0;
3924         return dev_priv->lvds_use_ssc
3925                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3926 }
3927
3928 /**
3929  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3930  * @crtc: CRTC structure
3931  * @mode: requested mode
3932  *
3933  * A pipe may be connected to one or more outputs.  Based on the depth of the
3934  * attached framebuffer, choose a good color depth to use on the pipe.
3935  *
3936  * If possible, match the pipe depth to the fb depth.  In some cases, this
3937  * isn't ideal, because the connected output supports a lesser or restricted
3938  * set of depths.  Resolve that here:
3939  *    LVDS typically supports only 6bpc, so clamp down in that case
3940  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3941  *    Displays may support a restricted set as well, check EDID and clamp as
3942  *      appropriate.
3943  *    DP may want to dither down to 6bpc to fit larger modes
3944  *
3945  * RETURNS:
3946  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3947  * true if they don't match).
3948  */
3949 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3950                                          struct drm_framebuffer *fb,
3951                                          unsigned int *pipe_bpp,
3952                                          struct drm_display_mode *mode)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955         struct drm_i915_private *dev_priv = dev->dev_private;
3956         struct drm_connector *connector;
3957         struct intel_encoder *intel_encoder;
3958         unsigned int display_bpc = UINT_MAX, bpc;
3959
3960         /* Walk the encoders & connectors on this crtc, get min bpc */
3961         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3962
3963                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3964                         unsigned int lvds_bpc;
3965
3966                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3967                             LVDS_A3_POWER_UP)
3968                                 lvds_bpc = 8;
3969                         else
3970                                 lvds_bpc = 6;
3971
3972                         if (lvds_bpc < display_bpc) {
3973                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3974                                 display_bpc = lvds_bpc;
3975                         }
3976                         continue;
3977                 }
3978
3979                 /* Not one of the known troublemakers, check the EDID */
3980                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3981                                     head) {
3982                         if (connector->encoder != &intel_encoder->base)
3983                                 continue;
3984
3985                         /* Don't use an invalid EDID bpc value */
3986                         if (connector->display_info.bpc &&
3987                             connector->display_info.bpc < display_bpc) {
3988                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3989                                 display_bpc = connector->display_info.bpc;
3990                         }
3991                 }
3992
3993                 /*
3994                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3995                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3996                  */
3997                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3998                         if (display_bpc > 8 && display_bpc < 12) {
3999                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4000                                 display_bpc = 12;
4001                         } else {
4002                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4003                                 display_bpc = 8;
4004                         }
4005                 }
4006         }
4007
4008         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4009                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4010                 display_bpc = 6;
4011         }
4012
4013         /*
4014          * We could just drive the pipe at the highest bpc all the time and
4015          * enable dithering as needed, but that costs bandwidth.  So choose
4016          * the minimum value that expresses the full color range of the fb but
4017          * also stays within the max display bpc discovered above.
4018          */
4019
4020         switch (fb->depth) {
4021         case 8:
4022                 bpc = 8; /* since we go through a colormap */
4023                 break;
4024         case 15:
4025         case 16:
4026                 bpc = 6; /* min is 18bpp */
4027                 break;
4028         case 24:
4029                 bpc = 8;
4030                 break;
4031         case 30:
4032                 bpc = 10;
4033                 break;
4034         case 48:
4035                 bpc = 12;
4036                 break;
4037         default:
4038                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4039                 bpc = min((unsigned int)8, display_bpc);
4040                 break;
4041         }
4042
4043         display_bpc = min(display_bpc, bpc);
4044
4045         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4046                       bpc, display_bpc);
4047
4048         *pipe_bpp = display_bpc * 3;
4049
4050         return display_bpc != bpc;
4051 }
4052
4053 static int vlv_get_refclk(struct drm_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         int refclk = 27000; /* for DP & HDMI */
4058
4059         return 100000; /* only one validated so far */
4060
4061         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4062                 refclk = 96000;
4063         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4064                 if (intel_panel_use_ssc(dev_priv))
4065                         refclk = 100000;
4066                 else
4067                         refclk = 96000;
4068         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4069                 refclk = 100000;
4070         }
4071
4072         return refclk;
4073 }
4074
4075 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4076 {
4077         struct drm_device *dev = crtc->dev;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         int refclk;
4080
4081         if (IS_VALLEYVIEW(dev)) {
4082                 refclk = vlv_get_refclk(crtc);
4083         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4084             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4085                 refclk = dev_priv->lvds_ssc_freq * 1000;
4086                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4087                               refclk / 1000);
4088         } else if (!IS_GEN2(dev)) {
4089                 refclk = 96000;
4090         } else {
4091                 refclk = 48000;
4092         }
4093
4094         return refclk;
4095 }
4096
4097 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4098                                       intel_clock_t *clock)
4099 {
4100         /* SDVO TV has fixed PLL values depend on its clock range,
4101            this mirrors vbios setting. */
4102         if (adjusted_mode->clock >= 100000
4103             && adjusted_mode->clock < 140500) {
4104                 clock->p1 = 2;
4105                 clock->p2 = 10;
4106                 clock->n = 3;
4107                 clock->m1 = 16;
4108                 clock->m2 = 8;
4109         } else if (adjusted_mode->clock >= 140500
4110                    && adjusted_mode->clock <= 200000) {
4111                 clock->p1 = 1;
4112                 clock->p2 = 10;
4113                 clock->n = 6;
4114                 clock->m1 = 12;
4115                 clock->m2 = 8;
4116         }
4117 }
4118
4119 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4120                                      intel_clock_t *clock,
4121                                      intel_clock_t *reduced_clock)
4122 {
4123         struct drm_device *dev = crtc->dev;
4124         struct drm_i915_private *dev_priv = dev->dev_private;
4125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4126         int pipe = intel_crtc->pipe;
4127         u32 fp, fp2 = 0;
4128
4129         if (IS_PINEVIEW(dev)) {
4130                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4131                 if (reduced_clock)
4132                         fp2 = (1 << reduced_clock->n) << 16 |
4133                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4134         } else {
4135                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4136                 if (reduced_clock)
4137                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4138                                 reduced_clock->m2;
4139         }
4140
4141         I915_WRITE(FP0(pipe), fp);
4142
4143         intel_crtc->lowfreq_avail = false;
4144         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4145             reduced_clock && i915_powersave) {
4146                 I915_WRITE(FP1(pipe), fp2);
4147                 intel_crtc->lowfreq_avail = true;
4148         } else {
4149                 I915_WRITE(FP1(pipe), fp);
4150         }
4151 }
4152
4153 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4154                               struct drm_display_mode *adjusted_mode)
4155 {
4156         struct drm_device *dev = crtc->dev;
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159         int pipe = intel_crtc->pipe;
4160         u32 temp;
4161
4162         temp = I915_READ(LVDS);
4163         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4164         if (pipe == 1) {
4165                 temp |= LVDS_PIPEB_SELECT;
4166         } else {
4167                 temp &= ~LVDS_PIPEB_SELECT;
4168         }
4169         /* set the corresponsding LVDS_BORDER bit */
4170         temp |= dev_priv->lvds_border_bits;
4171         /* Set the B0-B3 data pairs corresponding to whether we're going to
4172          * set the DPLLs for dual-channel mode or not.
4173          */
4174         if (clock->p2 == 7)
4175                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4176         else
4177                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4178
4179         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4180          * appropriately here, but we need to look more thoroughly into how
4181          * panels behave in the two modes.
4182          */
4183         /* set the dithering flag on LVDS as needed */
4184         if (INTEL_INFO(dev)->gen >= 4) {
4185                 if (dev_priv->lvds_dither)
4186                         temp |= LVDS_ENABLE_DITHER;
4187                 else
4188                         temp &= ~LVDS_ENABLE_DITHER;
4189         }
4190         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4191         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4192                 temp |= LVDS_HSYNC_POLARITY;
4193         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4194                 temp |= LVDS_VSYNC_POLARITY;
4195         I915_WRITE(LVDS, temp);
4196 }
4197
4198 static void vlv_update_pll(struct drm_crtc *crtc,
4199                            struct drm_display_mode *mode,
4200                            struct drm_display_mode *adjusted_mode,
4201                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4202                            int num_connectors)
4203 {
4204         struct drm_device *dev = crtc->dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207         int pipe = intel_crtc->pipe;
4208         u32 dpll, mdiv, pdiv;
4209         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4210         bool is_sdvo;
4211         u32 temp;
4212
4213         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4214                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4215
4216         dpll = DPLL_VGA_MODE_DIS;
4217         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4218         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4219         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4220
4221         I915_WRITE(DPLL(pipe), dpll);
4222         POSTING_READ(DPLL(pipe));
4223
4224         bestn = clock->n;
4225         bestm1 = clock->m1;
4226         bestm2 = clock->m2;
4227         bestp1 = clock->p1;
4228         bestp2 = clock->p2;
4229
4230         /*
4231          * In Valleyview PLL and program lane counter registers are exposed
4232          * through DPIO interface
4233          */
4234         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4235         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4236         mdiv |= ((bestn << DPIO_N_SHIFT));
4237         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4238         mdiv |= (1 << DPIO_K_SHIFT);
4239         mdiv |= DPIO_ENABLE_CALIBRATION;
4240         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4241
4242         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4243
4244         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4245                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4246                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4247                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4248         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4249
4250         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4251
4252         dpll |= DPLL_VCO_ENABLE;
4253         I915_WRITE(DPLL(pipe), dpll);
4254         POSTING_READ(DPLL(pipe));
4255         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4256                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4257
4258         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4259
4260         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4261                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4262
4263         I915_WRITE(DPLL(pipe), dpll);
4264
4265         /* Wait for the clocks to stabilize. */
4266         POSTING_READ(DPLL(pipe));
4267         udelay(150);
4268
4269         temp = 0;
4270         if (is_sdvo) {
4271                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4272                 if (temp > 1)
4273                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4274                 else
4275                         temp = 0;
4276         }
4277         I915_WRITE(DPLL_MD(pipe), temp);
4278         POSTING_READ(DPLL_MD(pipe));
4279
4280         /* Now program lane control registers */
4281         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4282                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4283         {
4284                 temp = 0x1000C4;
4285                 if(pipe == 1)
4286                         temp |= (1 << 21);
4287                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4288         }
4289         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4290         {
4291                 temp = 0x1000C4;
4292                 if(pipe == 1)
4293                         temp |= (1 << 21);
4294                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4295         }
4296 }
4297
4298 static void i9xx_update_pll(struct drm_crtc *crtc,
4299                             struct drm_display_mode *mode,
4300                             struct drm_display_mode *adjusted_mode,
4301                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4302                             int num_connectors)
4303 {
4304         struct drm_device *dev = crtc->dev;
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307         int pipe = intel_crtc->pipe;
4308         u32 dpll;
4309         bool is_sdvo;
4310
4311         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4312
4313         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4314                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4315
4316         dpll = DPLL_VGA_MODE_DIS;
4317
4318         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4319                 dpll |= DPLLB_MODE_LVDS;
4320         else
4321                 dpll |= DPLLB_MODE_DAC_SERIAL;
4322         if (is_sdvo) {
4323                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4324                 if (pixel_multiplier > 1) {
4325                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4326                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4327                 }
4328                 dpll |= DPLL_DVO_HIGH_SPEED;
4329         }
4330         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4331                 dpll |= DPLL_DVO_HIGH_SPEED;
4332
4333         /* compute bitmask from p1 value */
4334         if (IS_PINEVIEW(dev))
4335                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4336         else {
4337                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4338                 if (IS_G4X(dev) && reduced_clock)
4339                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4340         }
4341         switch (clock->p2) {
4342         case 5:
4343                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4344                 break;
4345         case 7:
4346                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4347                 break;
4348         case 10:
4349                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4350                 break;
4351         case 14:
4352                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4353                 break;
4354         }
4355         if (INTEL_INFO(dev)->gen >= 4)
4356                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4357
4358         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4359                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4360         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4361                 /* XXX: just matching BIOS for now */
4362                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4363                 dpll |= 3;
4364         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4365                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4366                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4367         else
4368                 dpll |= PLL_REF_INPUT_DREFCLK;
4369
4370         dpll |= DPLL_VCO_ENABLE;
4371         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4372         POSTING_READ(DPLL(pipe));
4373         udelay(150);
4374
4375         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4376          * This is an exception to the general rule that mode_set doesn't turn
4377          * things on.
4378          */
4379         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4380                 intel_update_lvds(crtc, clock, adjusted_mode);
4381
4382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4383                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4384
4385         I915_WRITE(DPLL(pipe), dpll);
4386
4387         /* Wait for the clocks to stabilize. */
4388         POSTING_READ(DPLL(pipe));
4389         udelay(150);
4390
4391         if (INTEL_INFO(dev)->gen >= 4) {
4392                 u32 temp = 0;
4393                 if (is_sdvo) {
4394                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4395                         if (temp > 1)
4396                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4397                         else
4398                                 temp = 0;
4399                 }
4400                 I915_WRITE(DPLL_MD(pipe), temp);
4401         } else {
4402                 /* The pixel multiplier can only be updated once the
4403                  * DPLL is enabled and the clocks are stable.
4404                  *
4405                  * So write it again.
4406                  */
4407                 I915_WRITE(DPLL(pipe), dpll);
4408         }
4409 }
4410
4411 static void i8xx_update_pll(struct drm_crtc *crtc,
4412                             struct drm_display_mode *adjusted_mode,
4413                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4414                             int num_connectors)
4415 {
4416         struct drm_device *dev = crtc->dev;
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419         int pipe = intel_crtc->pipe;
4420         u32 dpll;
4421
4422         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4423
4424         dpll = DPLL_VGA_MODE_DIS;
4425
4426         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4427                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4428         } else {
4429                 if (clock->p1 == 2)
4430                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4431                 else
4432                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4433                 if (clock->p2 == 4)
4434                         dpll |= PLL_P2_DIVIDE_BY_4;
4435         }
4436
4437         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4438                 /* XXX: just matching BIOS for now */
4439                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4440                 dpll |= 3;
4441         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4442                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4443                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4444         else
4445                 dpll |= PLL_REF_INPUT_DREFCLK;
4446
4447         dpll |= DPLL_VCO_ENABLE;
4448         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4449         POSTING_READ(DPLL(pipe));
4450         udelay(150);
4451
4452         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4453          * This is an exception to the general rule that mode_set doesn't turn
4454          * things on.
4455          */
4456         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4457                 intel_update_lvds(crtc, clock, adjusted_mode);
4458
4459         I915_WRITE(DPLL(pipe), dpll);
4460
4461         /* Wait for the clocks to stabilize. */
4462         POSTING_READ(DPLL(pipe));
4463         udelay(150);
4464
4465         /* The pixel multiplier can only be updated once the
4466          * DPLL is enabled and the clocks are stable.
4467          *
4468          * So write it again.
4469          */
4470         I915_WRITE(DPLL(pipe), dpll);
4471 }
4472
4473 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4474                                    struct drm_display_mode *mode,
4475                                    struct drm_display_mode *adjusted_mode)
4476 {
4477         struct drm_device *dev = intel_crtc->base.dev;
4478         struct drm_i915_private *dev_priv = dev->dev_private;
4479         enum pipe pipe = intel_crtc->pipe;
4480         uint32_t vsyncshift;
4481
4482         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4483                 /* the chip adds 2 halflines automatically */
4484                 adjusted_mode->crtc_vtotal -= 1;
4485                 adjusted_mode->crtc_vblank_end -= 1;
4486                 vsyncshift = adjusted_mode->crtc_hsync_start
4487                              - adjusted_mode->crtc_htotal / 2;
4488         } else {
4489                 vsyncshift = 0;
4490         }
4491
4492         if (INTEL_INFO(dev)->gen > 3)
4493                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4494
4495         I915_WRITE(HTOTAL(pipe),
4496                    (adjusted_mode->crtc_hdisplay - 1) |
4497                    ((adjusted_mode->crtc_htotal - 1) << 16));
4498         I915_WRITE(HBLANK(pipe),
4499                    (adjusted_mode->crtc_hblank_start - 1) |
4500                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4501         I915_WRITE(HSYNC(pipe),
4502                    (adjusted_mode->crtc_hsync_start - 1) |
4503                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4504
4505         I915_WRITE(VTOTAL(pipe),
4506                    (adjusted_mode->crtc_vdisplay - 1) |
4507                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4508         I915_WRITE(VBLANK(pipe),
4509                    (adjusted_mode->crtc_vblank_start - 1) |
4510                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4511         I915_WRITE(VSYNC(pipe),
4512                    (adjusted_mode->crtc_vsync_start - 1) |
4513                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4514
4515         /* pipesrc controls the size that is scaled from, which should
4516          * always be the user's requested size.
4517          */
4518         I915_WRITE(PIPESRC(pipe),
4519                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4520 }
4521
4522 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4523                               struct drm_display_mode *mode,
4524                               struct drm_display_mode *adjusted_mode,
4525                               int x, int y,
4526                               struct drm_framebuffer *fb)
4527 {
4528         struct drm_device *dev = crtc->dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         int pipe = intel_crtc->pipe;
4532         int plane = intel_crtc->plane;
4533         int refclk, num_connectors = 0;
4534         intel_clock_t clock, reduced_clock;
4535         u32 dspcntr, pipeconf;
4536         bool ok, has_reduced_clock = false, is_sdvo = false;
4537         bool is_lvds = false, is_tv = false, is_dp = false;
4538         struct intel_encoder *encoder;
4539         const intel_limit_t *limit;
4540         int ret;
4541
4542         for_each_encoder_on_crtc(dev, crtc, encoder) {
4543                 switch (encoder->type) {
4544                 case INTEL_OUTPUT_LVDS:
4545                         is_lvds = true;
4546                         break;
4547                 case INTEL_OUTPUT_SDVO:
4548                 case INTEL_OUTPUT_HDMI:
4549                         is_sdvo = true;
4550                         if (encoder->needs_tv_clock)
4551                                 is_tv = true;
4552                         break;
4553                 case INTEL_OUTPUT_TVOUT:
4554                         is_tv = true;
4555                         break;
4556                 case INTEL_OUTPUT_DISPLAYPORT:
4557                         is_dp = true;
4558                         break;
4559                 }
4560
4561                 num_connectors++;
4562         }
4563
4564         refclk = i9xx_get_refclk(crtc, num_connectors);
4565
4566         /*
4567          * Returns a set of divisors for the desired target clock with the given
4568          * refclk, or FALSE.  The returned values represent the clock equation:
4569          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4570          */
4571         limit = intel_limit(crtc, refclk);
4572         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4573                              &clock);
4574         if (!ok) {
4575                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4576                 return -EINVAL;
4577         }
4578
4579         /* Ensure that the cursor is valid for the new mode before changing... */
4580         intel_crtc_update_cursor(crtc, true);
4581
4582         if (is_lvds && dev_priv->lvds_downclock_avail) {
4583                 /*
4584                  * Ensure we match the reduced clock's P to the target clock.
4585                  * If the clocks don't match, we can't switch the display clock
4586                  * by using the FP0/FP1. In such case we will disable the LVDS
4587                  * downclock feature.
4588                 */
4589                 has_reduced_clock = limit->find_pll(limit, crtc,
4590                                                     dev_priv->lvds_downclock,
4591                                                     refclk,
4592                                                     &clock,
4593                                                     &reduced_clock);
4594         }
4595
4596         if (is_sdvo && is_tv)
4597                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4598
4599         if (IS_GEN2(dev))
4600                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4601                                 has_reduced_clock ? &reduced_clock : NULL,
4602                                 num_connectors);
4603         else if (IS_VALLEYVIEW(dev))
4604                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4605                                 has_reduced_clock ? &reduced_clock : NULL,
4606                                 num_connectors);
4607         else
4608                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4609                                 has_reduced_clock ? &reduced_clock : NULL,
4610                                 num_connectors);
4611
4612         /* setup pipeconf */
4613         pipeconf = I915_READ(PIPECONF(pipe));
4614
4615         /* Set up the display plane register */
4616         dspcntr = DISPPLANE_GAMMA_ENABLE;
4617
4618         if (pipe == 0)
4619                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4620         else
4621                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4622
4623         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4624                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4625                  * core speed.
4626                  *
4627                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4628                  * pipe == 0 check?
4629                  */
4630                 if (mode->clock >
4631                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4632                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4633                 else
4634                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4635         }
4636
4637         /* default to 8bpc */
4638         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4639         if (is_dp) {
4640                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4641                         pipeconf |= PIPECONF_BPP_6 |
4642                                     PIPECONF_DITHER_EN |
4643                                     PIPECONF_DITHER_TYPE_SP;
4644                 }
4645         }
4646
4647         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4648                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4649                         pipeconf |= PIPECONF_BPP_6 |
4650                                         PIPECONF_ENABLE |
4651                                         I965_PIPECONF_ACTIVE;
4652                 }
4653         }
4654
4655         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4656         drm_mode_debug_printmodeline(mode);
4657
4658         if (HAS_PIPE_CXSR(dev)) {
4659                 if (intel_crtc->lowfreq_avail) {
4660                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4661                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4662                 } else {
4663                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4664                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4665                 }
4666         }
4667
4668         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4669         if (!IS_GEN2(dev) &&
4670             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4671                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4672         else
4673                 pipeconf |= PIPECONF_PROGRESSIVE;
4674
4675         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4676
4677         /* pipesrc and dspsize control the size that is scaled from,
4678          * which should always be the user's requested size.
4679          */
4680         I915_WRITE(DSPSIZE(plane),
4681                    ((mode->vdisplay - 1) << 16) |
4682                    (mode->hdisplay - 1));
4683         I915_WRITE(DSPPOS(plane), 0);
4684
4685         I915_WRITE(PIPECONF(pipe), pipeconf);
4686         POSTING_READ(PIPECONF(pipe));
4687         intel_enable_pipe(dev_priv, pipe, false);
4688
4689         intel_wait_for_vblank(dev, pipe);
4690
4691         I915_WRITE(DSPCNTR(plane), dspcntr);
4692         POSTING_READ(DSPCNTR(plane));
4693
4694         ret = intel_pipe_set_base(crtc, x, y, fb);
4695
4696         intel_update_watermarks(dev);
4697
4698         return ret;
4699 }
4700
4701 /*
4702  * Initialize reference clocks when the driver loads
4703  */
4704 void ironlake_init_pch_refclk(struct drm_device *dev)
4705 {
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         struct drm_mode_config *mode_config = &dev->mode_config;
4708         struct intel_encoder *encoder;
4709         u32 temp;
4710         bool has_lvds = false;
4711         bool has_cpu_edp = false;
4712         bool has_pch_edp = false;
4713         bool has_panel = false;
4714         bool has_ck505 = false;
4715         bool can_ssc = false;
4716
4717         /* We need to take the global config into account */
4718         list_for_each_entry(encoder, &mode_config->encoder_list,
4719                             base.head) {
4720                 switch (encoder->type) {
4721                 case INTEL_OUTPUT_LVDS:
4722                         has_panel = true;
4723                         has_lvds = true;
4724                         break;
4725                 case INTEL_OUTPUT_EDP:
4726                         has_panel = true;
4727                         if (intel_encoder_is_pch_edp(&encoder->base))
4728                                 has_pch_edp = true;
4729                         else
4730                                 has_cpu_edp = true;
4731                         break;
4732                 }
4733         }
4734
4735         if (HAS_PCH_IBX(dev)) {
4736                 has_ck505 = dev_priv->display_clock_mode;
4737                 can_ssc = has_ck505;
4738         } else {
4739                 has_ck505 = false;
4740                 can_ssc = true;
4741         }
4742
4743         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4744                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4745                       has_ck505);
4746
4747         /* Ironlake: try to setup display ref clock before DPLL
4748          * enabling. This is only under driver's control after
4749          * PCH B stepping, previous chipset stepping should be
4750          * ignoring this setting.
4751          */
4752         temp = I915_READ(PCH_DREF_CONTROL);
4753         /* Always enable nonspread source */
4754         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4755
4756         if (has_ck505)
4757                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4758         else
4759                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4760
4761         if (has_panel) {
4762                 temp &= ~DREF_SSC_SOURCE_MASK;
4763                 temp |= DREF_SSC_SOURCE_ENABLE;
4764
4765                 /* SSC must be turned on before enabling the CPU output  */
4766                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4767                         DRM_DEBUG_KMS("Using SSC on panel\n");
4768                         temp |= DREF_SSC1_ENABLE;
4769                 } else
4770                         temp &= ~DREF_SSC1_ENABLE;
4771
4772                 /* Get SSC going before enabling the outputs */
4773                 I915_WRITE(PCH_DREF_CONTROL, temp);
4774                 POSTING_READ(PCH_DREF_CONTROL);
4775                 udelay(200);
4776
4777                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4778
4779                 /* Enable CPU source on CPU attached eDP */
4780                 if (has_cpu_edp) {
4781                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4782                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4783                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4784                         }
4785                         else
4786                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4787                 } else
4788                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4789
4790                 I915_WRITE(PCH_DREF_CONTROL, temp);
4791                 POSTING_READ(PCH_DREF_CONTROL);
4792                 udelay(200);
4793         } else {
4794                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4795
4796                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4797
4798                 /* Turn off CPU output */
4799                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4800
4801                 I915_WRITE(PCH_DREF_CONTROL, temp);
4802                 POSTING_READ(PCH_DREF_CONTROL);
4803                 udelay(200);
4804
4805                 /* Turn off the SSC source */
4806                 temp &= ~DREF_SSC_SOURCE_MASK;
4807                 temp |= DREF_SSC_SOURCE_DISABLE;
4808
4809                 /* Turn off SSC1 */
4810                 temp &= ~ DREF_SSC1_ENABLE;
4811
4812                 I915_WRITE(PCH_DREF_CONTROL, temp);
4813                 POSTING_READ(PCH_DREF_CONTROL);
4814                 udelay(200);
4815         }
4816 }
4817
4818 static int ironlake_get_refclk(struct drm_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_encoder *encoder;
4823         struct intel_encoder *edp_encoder = NULL;
4824         int num_connectors = 0;
4825         bool is_lvds = false;
4826
4827         for_each_encoder_on_crtc(dev, crtc, encoder) {
4828                 switch (encoder->type) {
4829                 case INTEL_OUTPUT_LVDS:
4830                         is_lvds = true;
4831                         break;
4832                 case INTEL_OUTPUT_EDP:
4833                         edp_encoder = encoder;
4834                         break;
4835                 }
4836                 num_connectors++;
4837         }
4838
4839         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4840                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4841                               dev_priv->lvds_ssc_freq);
4842                 return dev_priv->lvds_ssc_freq * 1000;
4843         }
4844
4845         return 120000;
4846 }
4847
4848 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4849                                   struct drm_display_mode *adjusted_mode,
4850                                   bool dither)
4851 {
4852         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854         int pipe = intel_crtc->pipe;
4855         uint32_t val;
4856
4857         val = I915_READ(PIPECONF(pipe));
4858
4859         val &= ~PIPE_BPC_MASK;
4860         switch (intel_crtc->bpp) {
4861         case 18:
4862                 val |= PIPE_6BPC;
4863                 break;
4864         case 24:
4865                 val |= PIPE_8BPC;
4866                 break;
4867         case 30:
4868                 val |= PIPE_10BPC;
4869                 break;
4870         case 36:
4871                 val |= PIPE_12BPC;
4872                 break;
4873         default:
4874                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4875                 BUG();
4876         }
4877
4878         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4879         if (dither)
4880                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4881
4882         val &= ~PIPECONF_INTERLACE_MASK;
4883         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4884                 val |= PIPECONF_INTERLACED_ILK;
4885         else
4886                 val |= PIPECONF_PROGRESSIVE;
4887
4888         I915_WRITE(PIPECONF(pipe), val);
4889         POSTING_READ(PIPECONF(pipe));
4890 }
4891
4892 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4893                                  struct drm_display_mode *adjusted_mode,
4894                                  bool dither)
4895 {
4896         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898         int pipe = intel_crtc->pipe;
4899         uint32_t val;
4900
4901         val = I915_READ(PIPECONF(pipe));
4902
4903         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4904         if (dither)
4905                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4906
4907         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4908         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4909                 val |= PIPECONF_INTERLACED_ILK;
4910         else
4911                 val |= PIPECONF_PROGRESSIVE;
4912
4913         I915_WRITE(PIPECONF(pipe), val);
4914         POSTING_READ(PIPECONF(pipe));
4915 }
4916
4917 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4918                                     struct drm_display_mode *adjusted_mode,
4919                                     intel_clock_t *clock,
4920                                     bool *has_reduced_clock,
4921                                     intel_clock_t *reduced_clock)
4922 {
4923         struct drm_device *dev = crtc->dev;
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925         struct intel_encoder *intel_encoder;
4926         int refclk;
4927         const intel_limit_t *limit;
4928         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4929
4930         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4931                 switch (intel_encoder->type) {
4932                 case INTEL_OUTPUT_LVDS:
4933                         is_lvds = true;
4934                         break;
4935                 case INTEL_OUTPUT_SDVO:
4936                 case INTEL_OUTPUT_HDMI:
4937                         is_sdvo = true;
4938                         if (intel_encoder->needs_tv_clock)
4939                                 is_tv = true;
4940                         break;
4941                 case INTEL_OUTPUT_TVOUT:
4942                         is_tv = true;
4943                         break;
4944                 }
4945         }
4946
4947         refclk = ironlake_get_refclk(crtc);
4948
4949         /*
4950          * Returns a set of divisors for the desired target clock with the given
4951          * refclk, or FALSE.  The returned values represent the clock equation:
4952          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4953          */
4954         limit = intel_limit(crtc, refclk);
4955         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4956                               clock);
4957         if (!ret)
4958                 return false;
4959
4960         if (is_lvds && dev_priv->lvds_downclock_avail) {
4961                 /*
4962                  * Ensure we match the reduced clock's P to the target clock.
4963                  * If the clocks don't match, we can't switch the display clock
4964                  * by using the FP0/FP1. In such case we will disable the LVDS
4965                  * downclock feature.
4966                 */
4967                 *has_reduced_clock = limit->find_pll(limit, crtc,
4968                                                      dev_priv->lvds_downclock,
4969                                                      refclk,
4970                                                      clock,
4971                                                      reduced_clock);
4972         }
4973
4974         if (is_sdvo && is_tv)
4975                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4976
4977         return true;
4978 }
4979
4980 static void ironlake_set_m_n(struct drm_crtc *crtc,
4981                              struct drm_display_mode *mode,
4982                              struct drm_display_mode *adjusted_mode)
4983 {
4984         struct drm_device *dev = crtc->dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4987         enum pipe pipe = intel_crtc->pipe;
4988         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4989         struct fdi_m_n m_n = {0};
4990         int target_clock, pixel_multiplier, lane, link_bw;
4991         bool is_dp = false, is_cpu_edp = false;
4992
4993         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4994                 switch (intel_encoder->type) {
4995                 case INTEL_OUTPUT_DISPLAYPORT:
4996                         is_dp = true;
4997                         break;
4998                 case INTEL_OUTPUT_EDP:
4999                         is_dp = true;
5000                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5001                                 is_cpu_edp = true;
5002                         edp_encoder = intel_encoder;
5003                         break;
5004                 }
5005         }
5006
5007         /* FDI link */
5008         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5009         lane = 0;
5010         /* CPU eDP doesn't require FDI link, so just set DP M/N
5011            according to current link config */
5012         if (is_cpu_edp) {
5013                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5014         } else {
5015                 /* FDI is a binary signal running at ~2.7GHz, encoding
5016                  * each output octet as 10 bits. The actual frequency
5017                  * is stored as a divider into a 100MHz clock, and the
5018                  * mode pixel clock is stored in units of 1KHz.
5019                  * Hence the bw of each lane in terms of the mode signal
5020                  * is:
5021                  */
5022                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5023         }
5024
5025         /* [e]DP over FDI requires target mode clock instead of link clock. */
5026         if (edp_encoder)
5027                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5028         else if (is_dp)
5029                 target_clock = mode->clock;
5030         else
5031                 target_clock = adjusted_mode->clock;
5032
5033         if (!lane) {
5034                 /*
5035                  * Account for spread spectrum to avoid
5036                  * oversubscribing the link. Max center spread
5037                  * is 2.5%; use 5% for safety's sake.
5038                  */
5039                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5040                 lane = bps / (link_bw * 8) + 1;
5041         }
5042
5043         intel_crtc->fdi_lanes = lane;
5044
5045         if (pixel_multiplier > 1)
5046                 link_bw *= pixel_multiplier;
5047         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5048                              &m_n);
5049
5050         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5051         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5052         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5053         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5054 }
5055
5056 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5057                                       struct drm_display_mode *adjusted_mode,
5058                                       intel_clock_t *clock, u32 fp)
5059 {
5060         struct drm_crtc *crtc = &intel_crtc->base;
5061         struct drm_device *dev = crtc->dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_encoder *intel_encoder;
5064         uint32_t dpll;
5065         int factor, pixel_multiplier, num_connectors = 0;
5066         bool is_lvds = false, is_sdvo = false, is_tv = false;
5067         bool is_dp = false, is_cpu_edp = false;
5068
5069         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5070                 switch (intel_encoder->type) {
5071                 case INTEL_OUTPUT_LVDS:
5072                         is_lvds = true;
5073                         break;
5074                 case INTEL_OUTPUT_SDVO:
5075                 case INTEL_OUTPUT_HDMI:
5076                         is_sdvo = true;
5077                         if (intel_encoder->needs_tv_clock)
5078                                 is_tv = true;
5079                         break;
5080                 case INTEL_OUTPUT_TVOUT:
5081                         is_tv = true;
5082                         break;
5083                 case INTEL_OUTPUT_DISPLAYPORT:
5084                         is_dp = true;
5085                         break;
5086                 case INTEL_OUTPUT_EDP:
5087                         is_dp = true;
5088                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5089                                 is_cpu_edp = true;
5090                         break;
5091                 }
5092
5093                 num_connectors++;
5094         }
5095
5096         /* Enable autotuning of the PLL clock (if permissible) */
5097         factor = 21;
5098         if (is_lvds) {
5099                 if ((intel_panel_use_ssc(dev_priv) &&
5100                      dev_priv->lvds_ssc_freq == 100) ||
5101                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5102                         factor = 25;
5103         } else if (is_sdvo && is_tv)
5104                 factor = 20;
5105
5106         if (clock->m < factor * clock->n)
5107                 fp |= FP_CB_TUNE;
5108
5109         dpll = 0;
5110
5111         if (is_lvds)
5112                 dpll |= DPLLB_MODE_LVDS;
5113         else
5114                 dpll |= DPLLB_MODE_DAC_SERIAL;
5115         if (is_sdvo) {
5116                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5117                 if (pixel_multiplier > 1) {
5118                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5119                 }
5120                 dpll |= DPLL_DVO_HIGH_SPEED;
5121         }
5122         if (is_dp && !is_cpu_edp)
5123                 dpll |= DPLL_DVO_HIGH_SPEED;
5124
5125         /* compute bitmask from p1 value */
5126         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5127         /* also FPA1 */
5128         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5129
5130         switch (clock->p2) {
5131         case 5:
5132                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5133                 break;
5134         case 7:
5135                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5136                 break;
5137         case 10:
5138                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5139                 break;
5140         case 14:
5141                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5142                 break;
5143         }
5144
5145         if (is_sdvo && is_tv)
5146                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5147         else if (is_tv)
5148                 /* XXX: just matching BIOS for now */
5149                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5150                 dpll |= 3;
5151         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5152                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5153         else
5154                 dpll |= PLL_REF_INPUT_DREFCLK;
5155
5156         return dpll;
5157 }
5158
5159 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5160                                   struct drm_display_mode *mode,
5161                                   struct drm_display_mode *adjusted_mode,
5162                                   int x, int y,
5163                                   struct drm_framebuffer *fb)
5164 {
5165         struct drm_device *dev = crtc->dev;
5166         struct drm_i915_private *dev_priv = dev->dev_private;
5167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168         int pipe = intel_crtc->pipe;
5169         int plane = intel_crtc->plane;
5170         int num_connectors = 0;
5171         intel_clock_t clock, reduced_clock;
5172         u32 dpll, fp = 0, fp2 = 0;
5173         bool ok, has_reduced_clock = false;
5174         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5175         struct intel_encoder *encoder;
5176         u32 temp;
5177         int ret;
5178         bool dither;
5179
5180         for_each_encoder_on_crtc(dev, crtc, encoder) {
5181                 switch (encoder->type) {
5182                 case INTEL_OUTPUT_LVDS:
5183                         is_lvds = true;
5184                         break;
5185                 case INTEL_OUTPUT_DISPLAYPORT:
5186                         is_dp = true;
5187                         break;
5188                 case INTEL_OUTPUT_EDP:
5189                         is_dp = true;
5190                         if (!intel_encoder_is_pch_edp(&encoder->base))
5191                                 is_cpu_edp = true;
5192                         break;
5193                 }
5194
5195                 num_connectors++;
5196         }
5197
5198         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5199              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5200
5201         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5202                                      &has_reduced_clock, &reduced_clock);
5203         if (!ok) {
5204                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5205                 return -EINVAL;
5206         }
5207
5208         /* Ensure that the cursor is valid for the new mode before changing... */
5209         intel_crtc_update_cursor(crtc, true);
5210
5211         /* determine panel color depth */
5212         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5213         if (is_lvds && dev_priv->lvds_dither)
5214                 dither = true;
5215
5216         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5217         if (has_reduced_clock)
5218                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5219                         reduced_clock.m2;
5220
5221         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5222
5223         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5224         drm_mode_debug_printmodeline(mode);
5225
5226         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5227         if (!is_cpu_edp) {
5228                 struct intel_pch_pll *pll;
5229
5230                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5231                 if (pll == NULL) {
5232                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5233                                          pipe);
5234                         return -EINVAL;
5235                 }
5236         } else
5237                 intel_put_pch_pll(intel_crtc);
5238
5239         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5240          * This is an exception to the general rule that mode_set doesn't turn
5241          * things on.
5242          */
5243         if (is_lvds) {
5244                 temp = I915_READ(PCH_LVDS);
5245                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5246                 if (HAS_PCH_CPT(dev)) {
5247                         temp &= ~PORT_TRANS_SEL_MASK;
5248                         temp |= PORT_TRANS_SEL_CPT(pipe);
5249                 } else {
5250                         if (pipe == 1)
5251                                 temp |= LVDS_PIPEB_SELECT;
5252                         else
5253                                 temp &= ~LVDS_PIPEB_SELECT;
5254                 }
5255
5256                 /* set the corresponsding LVDS_BORDER bit */
5257                 temp |= dev_priv->lvds_border_bits;
5258                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5259                  * set the DPLLs for dual-channel mode or not.
5260                  */
5261                 if (clock.p2 == 7)
5262                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5263                 else
5264                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5265
5266                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5267                  * appropriately here, but we need to look more thoroughly into how
5268                  * panels behave in the two modes.
5269                  */
5270                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5271                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5272                         temp |= LVDS_HSYNC_POLARITY;
5273                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5274                         temp |= LVDS_VSYNC_POLARITY;
5275                 I915_WRITE(PCH_LVDS, temp);
5276         }
5277
5278         if (is_dp && !is_cpu_edp) {
5279                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5280         } else {
5281                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5282                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5283                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5284                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5285                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5286         }
5287
5288         if (intel_crtc->pch_pll) {
5289                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5290
5291                 /* Wait for the clocks to stabilize. */
5292                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5293                 udelay(150);
5294
5295                 /* The pixel multiplier can only be updated once the
5296                  * DPLL is enabled and the clocks are stable.
5297                  *
5298                  * So write it again.
5299                  */
5300                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5301         }
5302
5303         intel_crtc->lowfreq_avail = false;
5304         if (intel_crtc->pch_pll) {
5305                 if (is_lvds && has_reduced_clock && i915_powersave) {
5306                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5307                         intel_crtc->lowfreq_avail = true;
5308                 } else {
5309                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5310                 }
5311         }
5312
5313         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5314
5315         ironlake_set_m_n(crtc, mode, adjusted_mode);
5316
5317         if (is_cpu_edp)
5318                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5319
5320         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5321
5322         intel_wait_for_vblank(dev, pipe);
5323
5324         /* Set up the display plane register */
5325         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5326         POSTING_READ(DSPCNTR(plane));
5327
5328         ret = intel_pipe_set_base(crtc, x, y, fb);
5329
5330         intel_update_watermarks(dev);
5331
5332         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5333
5334         return ret;
5335 }
5336
5337 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5338                                  struct drm_display_mode *mode,
5339                                  struct drm_display_mode *adjusted_mode,
5340                                  int x, int y,
5341                                  struct drm_framebuffer *fb)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346         int pipe = intel_crtc->pipe;
5347         int plane = intel_crtc->plane;
5348         int num_connectors = 0;
5349         intel_clock_t clock, reduced_clock;
5350         u32 dpll = 0, fp = 0, fp2 = 0;
5351         bool ok, has_reduced_clock = false;
5352         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5353         struct intel_encoder *encoder;
5354         u32 temp;
5355         int ret;
5356         bool dither;
5357
5358         for_each_encoder_on_crtc(dev, crtc, encoder) {
5359                 switch (encoder->type) {
5360                 case INTEL_OUTPUT_LVDS:
5361                         is_lvds = true;
5362                         break;
5363                 case INTEL_OUTPUT_DISPLAYPORT:
5364                         is_dp = true;
5365                         break;
5366                 case INTEL_OUTPUT_EDP:
5367                         is_dp = true;
5368                         if (!intel_encoder_is_pch_edp(&encoder->base))
5369                                 is_cpu_edp = true;
5370                         break;
5371                 }
5372
5373                 num_connectors++;
5374         }
5375
5376         if (is_cpu_edp)
5377                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5378         else
5379                 intel_crtc->cpu_transcoder = pipe;
5380
5381         /* We are not sure yet this won't happen. */
5382         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5383              INTEL_PCH_TYPE(dev));
5384
5385         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5386              num_connectors, pipe_name(pipe));
5387
5388         WARN_ON(I915_READ(PIPECONF(pipe)) &
5389                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5390
5391         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5392
5393         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5394                 return -EINVAL;
5395
5396         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5397                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5398                                              &has_reduced_clock,
5399                                              &reduced_clock);
5400                 if (!ok) {
5401                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5402                         return -EINVAL;
5403                 }
5404         }
5405
5406         /* Ensure that the cursor is valid for the new mode before changing... */
5407         intel_crtc_update_cursor(crtc, true);
5408
5409         /* determine panel color depth */
5410         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5411         if (is_lvds && dev_priv->lvds_dither)
5412                 dither = true;
5413
5414         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5415         drm_mode_debug_printmodeline(mode);
5416
5417         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5418                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5419                 if (has_reduced_clock)
5420                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5421                               reduced_clock.m2;
5422
5423                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5424                                              fp);
5425
5426                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5427                  * own on pre-Haswell/LPT generation */
5428                 if (!is_cpu_edp) {
5429                         struct intel_pch_pll *pll;
5430
5431                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5432                         if (pll == NULL) {
5433                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5434                                                  pipe);
5435                                 return -EINVAL;
5436                         }
5437                 } else
5438                         intel_put_pch_pll(intel_crtc);
5439
5440                 /* The LVDS pin pair needs to be on before the DPLLs are
5441                  * enabled.  This is an exception to the general rule that
5442                  * mode_set doesn't turn things on.
5443                  */
5444                 if (is_lvds) {
5445                         temp = I915_READ(PCH_LVDS);
5446                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5447                         if (HAS_PCH_CPT(dev)) {
5448                                 temp &= ~PORT_TRANS_SEL_MASK;
5449                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5450                         } else {
5451                                 if (pipe == 1)
5452                                         temp |= LVDS_PIPEB_SELECT;
5453                                 else
5454                                         temp &= ~LVDS_PIPEB_SELECT;
5455                         }
5456
5457                         /* set the corresponsding LVDS_BORDER bit */
5458                         temp |= dev_priv->lvds_border_bits;
5459                         /* Set the B0-B3 data pairs corresponding to whether
5460                          * we're going to set the DPLLs for dual-channel mode or
5461                          * not.
5462                          */
5463                         if (clock.p2 == 7)
5464                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5465                         else
5466                                 temp &= ~(LVDS_B0B3_POWER_UP |
5467                                           LVDS_CLKB_POWER_UP);
5468
5469                         /* It would be nice to set 24 vs 18-bit mode
5470                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5471                          * look more thoroughly into how panels behave in the
5472                          * two modes.
5473                          */
5474                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5475                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5476                                 temp |= LVDS_HSYNC_POLARITY;
5477                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5478                                 temp |= LVDS_VSYNC_POLARITY;
5479                         I915_WRITE(PCH_LVDS, temp);
5480                 }
5481         }
5482
5483         if (is_dp && !is_cpu_edp) {
5484                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5485         } else {
5486                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5487                         /* For non-DP output, clear any trans DP clock recovery
5488                          * setting.*/
5489                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5490                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5491                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5492                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5493                 }
5494         }
5495
5496         intel_crtc->lowfreq_avail = false;
5497         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5498                 if (intel_crtc->pch_pll) {
5499                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5500
5501                         /* Wait for the clocks to stabilize. */
5502                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5503                         udelay(150);
5504
5505                         /* The pixel multiplier can only be updated once the
5506                          * DPLL is enabled and the clocks are stable.
5507                          *
5508                          * So write it again.
5509                          */
5510                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5511                 }
5512
5513                 if (intel_crtc->pch_pll) {
5514                         if (is_lvds && has_reduced_clock && i915_powersave) {
5515                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5516                                 intel_crtc->lowfreq_avail = true;
5517                         } else {
5518                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5519                         }
5520                 }
5521         }
5522
5523         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5524
5525         if (!is_dp || is_cpu_edp)
5526                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5527
5528         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5529                 if (is_cpu_edp)
5530                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5531
5532         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5533
5534         /* Set up the display plane register */
5535         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5536         POSTING_READ(DSPCNTR(plane));
5537
5538         ret = intel_pipe_set_base(crtc, x, y, fb);
5539
5540         intel_update_watermarks(dev);
5541
5542         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5543
5544         return ret;
5545 }
5546
5547 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5548                                struct drm_display_mode *mode,
5549                                struct drm_display_mode *adjusted_mode,
5550                                int x, int y,
5551                                struct drm_framebuffer *fb)
5552 {
5553         struct drm_device *dev = crtc->dev;
5554         struct drm_i915_private *dev_priv = dev->dev_private;
5555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5556         int pipe = intel_crtc->pipe;
5557         int ret;
5558
5559         drm_vblank_pre_modeset(dev, pipe);
5560
5561         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5562                                               x, y, fb);
5563         drm_vblank_post_modeset(dev, pipe);
5564
5565         return ret;
5566 }
5567
5568 static bool intel_eld_uptodate(struct drm_connector *connector,
5569                                int reg_eldv, uint32_t bits_eldv,
5570                                int reg_elda, uint32_t bits_elda,
5571                                int reg_edid)
5572 {
5573         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5574         uint8_t *eld = connector->eld;
5575         uint32_t i;
5576
5577         i = I915_READ(reg_eldv);
5578         i &= bits_eldv;
5579
5580         if (!eld[0])
5581                 return !i;
5582
5583         if (!i)
5584                 return false;
5585
5586         i = I915_READ(reg_elda);
5587         i &= ~bits_elda;
5588         I915_WRITE(reg_elda, i);
5589
5590         for (i = 0; i < eld[2]; i++)
5591                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5592                         return false;
5593
5594         return true;
5595 }
5596
5597 static void g4x_write_eld(struct drm_connector *connector,
5598                           struct drm_crtc *crtc)
5599 {
5600         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5601         uint8_t *eld = connector->eld;
5602         uint32_t eldv;
5603         uint32_t len;
5604         uint32_t i;
5605
5606         i = I915_READ(G4X_AUD_VID_DID);
5607
5608         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5609                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5610         else
5611                 eldv = G4X_ELDV_DEVCTG;
5612
5613         if (intel_eld_uptodate(connector,
5614                                G4X_AUD_CNTL_ST, eldv,
5615                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5616                                G4X_HDMIW_HDMIEDID))
5617                 return;
5618
5619         i = I915_READ(G4X_AUD_CNTL_ST);
5620         i &= ~(eldv | G4X_ELD_ADDR);
5621         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5622         I915_WRITE(G4X_AUD_CNTL_ST, i);
5623
5624         if (!eld[0])
5625                 return;
5626
5627         len = min_t(uint8_t, eld[2], len);
5628         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5629         for (i = 0; i < len; i++)
5630                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5631
5632         i = I915_READ(G4X_AUD_CNTL_ST);
5633         i |= eldv;
5634         I915_WRITE(G4X_AUD_CNTL_ST, i);
5635 }
5636
5637 static void haswell_write_eld(struct drm_connector *connector,
5638                                      struct drm_crtc *crtc)
5639 {
5640         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5641         uint8_t *eld = connector->eld;
5642         struct drm_device *dev = crtc->dev;
5643         uint32_t eldv;
5644         uint32_t i;
5645         int len;
5646         int pipe = to_intel_crtc(crtc)->pipe;
5647         int tmp;
5648
5649         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5650         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5651         int aud_config = HSW_AUD_CFG(pipe);
5652         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5653
5654
5655         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5656
5657         /* Audio output enable */
5658         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5659         tmp = I915_READ(aud_cntrl_st2);
5660         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5661         I915_WRITE(aud_cntrl_st2, tmp);
5662
5663         /* Wait for 1 vertical blank */
5664         intel_wait_for_vblank(dev, pipe);
5665
5666         /* Set ELD valid state */
5667         tmp = I915_READ(aud_cntrl_st2);
5668         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5669         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5670         I915_WRITE(aud_cntrl_st2, tmp);
5671         tmp = I915_READ(aud_cntrl_st2);
5672         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5673
5674         /* Enable HDMI mode */
5675         tmp = I915_READ(aud_config);
5676         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5677         /* clear N_programing_enable and N_value_index */
5678         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5679         I915_WRITE(aud_config, tmp);
5680
5681         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5682
5683         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5684
5685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5686                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5687                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5688                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5689         } else
5690                 I915_WRITE(aud_config, 0);
5691
5692         if (intel_eld_uptodate(connector,
5693                                aud_cntrl_st2, eldv,
5694                                aud_cntl_st, IBX_ELD_ADDRESS,
5695                                hdmiw_hdmiedid))
5696                 return;
5697
5698         i = I915_READ(aud_cntrl_st2);
5699         i &= ~eldv;
5700         I915_WRITE(aud_cntrl_st2, i);
5701
5702         if (!eld[0])
5703                 return;
5704
5705         i = I915_READ(aud_cntl_st);
5706         i &= ~IBX_ELD_ADDRESS;
5707         I915_WRITE(aud_cntl_st, i);
5708         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5709         DRM_DEBUG_DRIVER("port num:%d\n", i);
5710
5711         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5712         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5713         for (i = 0; i < len; i++)
5714                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5715
5716         i = I915_READ(aud_cntrl_st2);
5717         i |= eldv;
5718         I915_WRITE(aud_cntrl_st2, i);
5719
5720 }
5721
5722 static void ironlake_write_eld(struct drm_connector *connector,
5723                                      struct drm_crtc *crtc)
5724 {
5725         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5726         uint8_t *eld = connector->eld;
5727         uint32_t eldv;
5728         uint32_t i;
5729         int len;
5730         int hdmiw_hdmiedid;
5731         int aud_config;
5732         int aud_cntl_st;
5733         int aud_cntrl_st2;
5734         int pipe = to_intel_crtc(crtc)->pipe;
5735
5736         if (HAS_PCH_IBX(connector->dev)) {
5737                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5738                 aud_config = IBX_AUD_CFG(pipe);
5739                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5740                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5741         } else {
5742                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5743                 aud_config = CPT_AUD_CFG(pipe);
5744                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5745                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5746         }
5747
5748         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5749
5750         i = I915_READ(aud_cntl_st);
5751         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5752         if (!i) {
5753                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5754                 /* operate blindly on all ports */
5755                 eldv = IBX_ELD_VALIDB;
5756                 eldv |= IBX_ELD_VALIDB << 4;
5757                 eldv |= IBX_ELD_VALIDB << 8;
5758         } else {
5759                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5760                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5761         }
5762
5763         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5764                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5765                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5766                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5767         } else
5768                 I915_WRITE(aud_config, 0);
5769
5770         if (intel_eld_uptodate(connector,
5771                                aud_cntrl_st2, eldv,
5772                                aud_cntl_st, IBX_ELD_ADDRESS,
5773                                hdmiw_hdmiedid))
5774                 return;
5775
5776         i = I915_READ(aud_cntrl_st2);
5777         i &= ~eldv;
5778         I915_WRITE(aud_cntrl_st2, i);
5779
5780         if (!eld[0])
5781                 return;
5782
5783         i = I915_READ(aud_cntl_st);
5784         i &= ~IBX_ELD_ADDRESS;
5785         I915_WRITE(aud_cntl_st, i);
5786
5787         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5788         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5789         for (i = 0; i < len; i++)
5790                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5791
5792         i = I915_READ(aud_cntrl_st2);
5793         i |= eldv;
5794         I915_WRITE(aud_cntrl_st2, i);
5795 }
5796
5797 void intel_write_eld(struct drm_encoder *encoder,
5798                      struct drm_display_mode *mode)
5799 {
5800         struct drm_crtc *crtc = encoder->crtc;
5801         struct drm_connector *connector;
5802         struct drm_device *dev = encoder->dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804
5805         connector = drm_select_eld(encoder, mode);
5806         if (!connector)
5807                 return;
5808
5809         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5810                          connector->base.id,
5811                          drm_get_connector_name(connector),
5812                          connector->encoder->base.id,
5813                          drm_get_encoder_name(connector->encoder));
5814
5815         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5816
5817         if (dev_priv->display.write_eld)
5818                 dev_priv->display.write_eld(connector, crtc);
5819 }
5820
5821 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5822 void intel_crtc_load_lut(struct drm_crtc *crtc)
5823 {
5824         struct drm_device *dev = crtc->dev;
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5827         int palreg = PALETTE(intel_crtc->pipe);
5828         int i;
5829
5830         /* The clocks have to be on to load the palette. */
5831         if (!crtc->enabled || !intel_crtc->active)
5832                 return;
5833
5834         /* use legacy palette for Ironlake */
5835         if (HAS_PCH_SPLIT(dev))
5836                 palreg = LGC_PALETTE(intel_crtc->pipe);
5837
5838         for (i = 0; i < 256; i++) {
5839                 I915_WRITE(palreg + 4 * i,
5840                            (intel_crtc->lut_r[i] << 16) |
5841                            (intel_crtc->lut_g[i] << 8) |
5842                            intel_crtc->lut_b[i]);
5843         }
5844 }
5845
5846 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5847 {
5848         struct drm_device *dev = crtc->dev;
5849         struct drm_i915_private *dev_priv = dev->dev_private;
5850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5851         bool visible = base != 0;
5852         u32 cntl;
5853
5854         if (intel_crtc->cursor_visible == visible)
5855                 return;
5856
5857         cntl = I915_READ(_CURACNTR);
5858         if (visible) {
5859                 /* On these chipsets we can only modify the base whilst
5860                  * the cursor is disabled.
5861                  */
5862                 I915_WRITE(_CURABASE, base);
5863
5864                 cntl &= ~(CURSOR_FORMAT_MASK);
5865                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5866                 cntl |= CURSOR_ENABLE |
5867                         CURSOR_GAMMA_ENABLE |
5868                         CURSOR_FORMAT_ARGB;
5869         } else
5870                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5871         I915_WRITE(_CURACNTR, cntl);
5872
5873         intel_crtc->cursor_visible = visible;
5874 }
5875
5876 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5877 {
5878         struct drm_device *dev = crtc->dev;
5879         struct drm_i915_private *dev_priv = dev->dev_private;
5880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5881         int pipe = intel_crtc->pipe;
5882         bool visible = base != 0;
5883
5884         if (intel_crtc->cursor_visible != visible) {
5885                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5886                 if (base) {
5887                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5888                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5889                         cntl |= pipe << 28; /* Connect to correct pipe */
5890                 } else {
5891                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5892                         cntl |= CURSOR_MODE_DISABLE;
5893                 }
5894                 I915_WRITE(CURCNTR(pipe), cntl);
5895
5896                 intel_crtc->cursor_visible = visible;
5897         }
5898         /* and commit changes on next vblank */
5899         I915_WRITE(CURBASE(pipe), base);
5900 }
5901
5902 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5903 {
5904         struct drm_device *dev = crtc->dev;
5905         struct drm_i915_private *dev_priv = dev->dev_private;
5906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5907         int pipe = intel_crtc->pipe;
5908         bool visible = base != 0;
5909
5910         if (intel_crtc->cursor_visible != visible) {
5911                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5912                 if (base) {
5913                         cntl &= ~CURSOR_MODE;
5914                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5915                 } else {
5916                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5917                         cntl |= CURSOR_MODE_DISABLE;
5918                 }
5919                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5920
5921                 intel_crtc->cursor_visible = visible;
5922         }
5923         /* and commit changes on next vblank */
5924         I915_WRITE(CURBASE_IVB(pipe), base);
5925 }
5926
5927 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5928 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5929                                      bool on)
5930 {
5931         struct drm_device *dev = crtc->dev;
5932         struct drm_i915_private *dev_priv = dev->dev_private;
5933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5934         int pipe = intel_crtc->pipe;
5935         int x = intel_crtc->cursor_x;
5936         int y = intel_crtc->cursor_y;
5937         u32 base, pos;
5938         bool visible;
5939
5940         pos = 0;
5941
5942         if (on && crtc->enabled && crtc->fb) {
5943                 base = intel_crtc->cursor_addr;
5944                 if (x > (int) crtc->fb->width)
5945                         base = 0;
5946
5947                 if (y > (int) crtc->fb->height)
5948                         base = 0;
5949         } else
5950                 base = 0;
5951
5952         if (x < 0) {
5953                 if (x + intel_crtc->cursor_width < 0)
5954                         base = 0;
5955
5956                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5957                 x = -x;
5958         }
5959         pos |= x << CURSOR_X_SHIFT;
5960
5961         if (y < 0) {
5962                 if (y + intel_crtc->cursor_height < 0)
5963                         base = 0;
5964
5965                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5966                 y = -y;
5967         }
5968         pos |= y << CURSOR_Y_SHIFT;
5969
5970         visible = base != 0;
5971         if (!visible && !intel_crtc->cursor_visible)
5972                 return;
5973
5974         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5975                 I915_WRITE(CURPOS_IVB(pipe), pos);
5976                 ivb_update_cursor(crtc, base);
5977         } else {
5978                 I915_WRITE(CURPOS(pipe), pos);
5979                 if (IS_845G(dev) || IS_I865G(dev))
5980                         i845_update_cursor(crtc, base);
5981                 else
5982                         i9xx_update_cursor(crtc, base);
5983         }
5984 }
5985
5986 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5987                                  struct drm_file *file,
5988                                  uint32_t handle,
5989                                  uint32_t width, uint32_t height)
5990 {
5991         struct drm_device *dev = crtc->dev;
5992         struct drm_i915_private *dev_priv = dev->dev_private;
5993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5994         struct drm_i915_gem_object *obj;
5995         uint32_t addr;
5996         int ret;
5997
5998         /* if we want to turn off the cursor ignore width and height */
5999         if (!handle) {
6000                 DRM_DEBUG_KMS("cursor off\n");
6001                 addr = 0;
6002                 obj = NULL;
6003                 mutex_lock(&dev->struct_mutex);
6004                 goto finish;
6005         }
6006
6007         /* Currently we only support 64x64 cursors */
6008         if (width != 64 || height != 64) {
6009                 DRM_ERROR("we currently only support 64x64 cursors\n");
6010                 return -EINVAL;
6011         }
6012
6013         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6014         if (&obj->base == NULL)
6015                 return -ENOENT;
6016
6017         if (obj->base.size < width * height * 4) {
6018                 DRM_ERROR("buffer is to small\n");
6019                 ret = -ENOMEM;
6020                 goto fail;
6021         }
6022
6023         /* we only need to pin inside GTT if cursor is non-phy */
6024         mutex_lock(&dev->struct_mutex);
6025         if (!dev_priv->info->cursor_needs_physical) {
6026                 if (obj->tiling_mode) {
6027                         DRM_ERROR("cursor cannot be tiled\n");
6028                         ret = -EINVAL;
6029                         goto fail_locked;
6030                 }
6031
6032                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6033                 if (ret) {
6034                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6035                         goto fail_locked;
6036                 }
6037
6038                 ret = i915_gem_object_put_fence(obj);
6039                 if (ret) {
6040                         DRM_ERROR("failed to release fence for cursor");
6041                         goto fail_unpin;
6042                 }
6043
6044                 addr = obj->gtt_offset;
6045         } else {
6046                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6047                 ret = i915_gem_attach_phys_object(dev, obj,
6048                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6049                                                   align);
6050                 if (ret) {
6051                         DRM_ERROR("failed to attach phys object\n");
6052                         goto fail_locked;
6053                 }
6054                 addr = obj->phys_obj->handle->busaddr;
6055         }
6056
6057         if (IS_GEN2(dev))
6058                 I915_WRITE(CURSIZE, (height << 12) | width);
6059
6060  finish:
6061         if (intel_crtc->cursor_bo) {
6062                 if (dev_priv->info->cursor_needs_physical) {
6063                         if (intel_crtc->cursor_bo != obj)
6064                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6065                 } else
6066                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6067                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6068         }
6069
6070         mutex_unlock(&dev->struct_mutex);
6071
6072         intel_crtc->cursor_addr = addr;
6073         intel_crtc->cursor_bo = obj;
6074         intel_crtc->cursor_width = width;
6075         intel_crtc->cursor_height = height;
6076
6077         intel_crtc_update_cursor(crtc, true);
6078
6079         return 0;
6080 fail_unpin:
6081         i915_gem_object_unpin(obj);
6082 fail_locked:
6083         mutex_unlock(&dev->struct_mutex);
6084 fail:
6085         drm_gem_object_unreference_unlocked(&obj->base);
6086         return ret;
6087 }
6088
6089 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6090 {
6091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092
6093         intel_crtc->cursor_x = x;
6094         intel_crtc->cursor_y = y;
6095
6096         intel_crtc_update_cursor(crtc, true);
6097
6098         return 0;
6099 }
6100
6101 /** Sets the color ramps on behalf of RandR */
6102 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6103                                  u16 blue, int regno)
6104 {
6105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6106
6107         intel_crtc->lut_r[regno] = red >> 8;
6108         intel_crtc->lut_g[regno] = green >> 8;
6109         intel_crtc->lut_b[regno] = blue >> 8;
6110 }
6111
6112 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6113                              u16 *blue, int regno)
6114 {
6115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6116
6117         *red = intel_crtc->lut_r[regno] << 8;
6118         *green = intel_crtc->lut_g[regno] << 8;
6119         *blue = intel_crtc->lut_b[regno] << 8;
6120 }
6121
6122 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6123                                  u16 *blue, uint32_t start, uint32_t size)
6124 {
6125         int end = (start + size > 256) ? 256 : start + size, i;
6126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6127
6128         for (i = start; i < end; i++) {
6129                 intel_crtc->lut_r[i] = red[i] >> 8;
6130                 intel_crtc->lut_g[i] = green[i] >> 8;
6131                 intel_crtc->lut_b[i] = blue[i] >> 8;
6132         }
6133
6134         intel_crtc_load_lut(crtc);
6135 }
6136
6137 /**
6138  * Get a pipe with a simple mode set on it for doing load-based monitor
6139  * detection.
6140  *
6141  * It will be up to the load-detect code to adjust the pipe as appropriate for
6142  * its requirements.  The pipe will be connected to no other encoders.
6143  *
6144  * Currently this code will only succeed if there is a pipe with no encoders
6145  * configured for it.  In the future, it could choose to temporarily disable
6146  * some outputs to free up a pipe for its use.
6147  *
6148  * \return crtc, or NULL if no pipes are available.
6149  */
6150
6151 /* VESA 640x480x72Hz mode to set on the pipe */
6152 static struct drm_display_mode load_detect_mode = {
6153         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6154                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6155 };
6156
6157 static struct drm_framebuffer *
6158 intel_framebuffer_create(struct drm_device *dev,
6159                          struct drm_mode_fb_cmd2 *mode_cmd,
6160                          struct drm_i915_gem_object *obj)
6161 {
6162         struct intel_framebuffer *intel_fb;
6163         int ret;
6164
6165         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6166         if (!intel_fb) {
6167                 drm_gem_object_unreference_unlocked(&obj->base);
6168                 return ERR_PTR(-ENOMEM);
6169         }
6170
6171         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6172         if (ret) {
6173                 drm_gem_object_unreference_unlocked(&obj->base);
6174                 kfree(intel_fb);
6175                 return ERR_PTR(ret);
6176         }
6177
6178         return &intel_fb->base;
6179 }
6180
6181 static u32
6182 intel_framebuffer_pitch_for_width(int width, int bpp)
6183 {
6184         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6185         return ALIGN(pitch, 64);
6186 }
6187
6188 static u32
6189 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6190 {
6191         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6192         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6193 }
6194
6195 static struct drm_framebuffer *
6196 intel_framebuffer_create_for_mode(struct drm_device *dev,
6197                                   struct drm_display_mode *mode,
6198                                   int depth, int bpp)
6199 {
6200         struct drm_i915_gem_object *obj;
6201         struct drm_mode_fb_cmd2 mode_cmd;
6202
6203         obj = i915_gem_alloc_object(dev,
6204                                     intel_framebuffer_size_for_mode(mode, bpp));
6205         if (obj == NULL)
6206                 return ERR_PTR(-ENOMEM);
6207
6208         mode_cmd.width = mode->hdisplay;
6209         mode_cmd.height = mode->vdisplay;
6210         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6211                                                                 bpp);
6212         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6213
6214         return intel_framebuffer_create(dev, &mode_cmd, obj);
6215 }
6216
6217 static struct drm_framebuffer *
6218 mode_fits_in_fbdev(struct drm_device *dev,
6219                    struct drm_display_mode *mode)
6220 {
6221         struct drm_i915_private *dev_priv = dev->dev_private;
6222         struct drm_i915_gem_object *obj;
6223         struct drm_framebuffer *fb;
6224
6225         if (dev_priv->fbdev == NULL)
6226                 return NULL;
6227
6228         obj = dev_priv->fbdev->ifb.obj;
6229         if (obj == NULL)
6230                 return NULL;
6231
6232         fb = &dev_priv->fbdev->ifb.base;
6233         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6234                                                                fb->bits_per_pixel))
6235                 return NULL;
6236
6237         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6238                 return NULL;
6239
6240         return fb;
6241 }
6242
6243 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6244                                 struct drm_display_mode *mode,
6245                                 struct intel_load_detect_pipe *old)
6246 {
6247         struct intel_crtc *intel_crtc;
6248         struct intel_encoder *intel_encoder =
6249                 intel_attached_encoder(connector);
6250         struct drm_crtc *possible_crtc;
6251         struct drm_encoder *encoder = &intel_encoder->base;
6252         struct drm_crtc *crtc = NULL;
6253         struct drm_device *dev = encoder->dev;
6254         struct drm_framebuffer *fb;
6255         int i = -1;
6256
6257         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6258                       connector->base.id, drm_get_connector_name(connector),
6259                       encoder->base.id, drm_get_encoder_name(encoder));
6260
6261         /*
6262          * Algorithm gets a little messy:
6263          *
6264          *   - if the connector already has an assigned crtc, use it (but make
6265          *     sure it's on first)
6266          *
6267          *   - try to find the first unused crtc that can drive this connector,
6268          *     and use that if we find one
6269          */
6270
6271         /* See if we already have a CRTC for this connector */
6272         if (encoder->crtc) {
6273                 crtc = encoder->crtc;
6274
6275                 old->dpms_mode = connector->dpms;
6276                 old->load_detect_temp = false;
6277
6278                 /* Make sure the crtc and connector are running */
6279                 if (connector->dpms != DRM_MODE_DPMS_ON)
6280                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6281
6282                 return true;
6283         }
6284
6285         /* Find an unused one (if possible) */
6286         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6287                 i++;
6288                 if (!(encoder->possible_crtcs & (1 << i)))
6289                         continue;
6290                 if (!possible_crtc->enabled) {
6291                         crtc = possible_crtc;
6292                         break;
6293                 }
6294         }
6295
6296         /*
6297          * If we didn't find an unused CRTC, don't use any.
6298          */
6299         if (!crtc) {
6300                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6301                 return false;
6302         }
6303
6304         intel_encoder->new_crtc = to_intel_crtc(crtc);
6305         to_intel_connector(connector)->new_encoder = intel_encoder;
6306
6307         intel_crtc = to_intel_crtc(crtc);
6308         old->dpms_mode = connector->dpms;
6309         old->load_detect_temp = true;
6310         old->release_fb = NULL;
6311
6312         if (!mode)
6313                 mode = &load_detect_mode;
6314
6315         /* We need a framebuffer large enough to accommodate all accesses
6316          * that the plane may generate whilst we perform load detection.
6317          * We can not rely on the fbcon either being present (we get called
6318          * during its initialisation to detect all boot displays, or it may
6319          * not even exist) or that it is large enough to satisfy the
6320          * requested mode.
6321          */
6322         fb = mode_fits_in_fbdev(dev, mode);
6323         if (fb == NULL) {
6324                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6325                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6326                 old->release_fb = fb;
6327         } else
6328                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6329         if (IS_ERR(fb)) {
6330                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6331                 goto fail;
6332         }
6333
6334         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6335                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6336                 if (old->release_fb)
6337                         old->release_fb->funcs->destroy(old->release_fb);
6338                 goto fail;
6339         }
6340
6341         /* let the connector get through one full cycle before testing */
6342         intel_wait_for_vblank(dev, intel_crtc->pipe);
6343
6344         return true;
6345 fail:
6346         connector->encoder = NULL;
6347         encoder->crtc = NULL;
6348         return false;
6349 }
6350
6351 void intel_release_load_detect_pipe(struct drm_connector *connector,
6352                                     struct intel_load_detect_pipe *old)
6353 {
6354         struct intel_encoder *intel_encoder =
6355                 intel_attached_encoder(connector);
6356         struct drm_encoder *encoder = &intel_encoder->base;
6357
6358         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6359                       connector->base.id, drm_get_connector_name(connector),
6360                       encoder->base.id, drm_get_encoder_name(encoder));
6361
6362         if (old->load_detect_temp) {
6363                 struct drm_crtc *crtc = encoder->crtc;
6364
6365                 to_intel_connector(connector)->new_encoder = NULL;
6366                 intel_encoder->new_crtc = NULL;
6367                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6368
6369                 if (old->release_fb)
6370                         old->release_fb->funcs->destroy(old->release_fb);
6371
6372                 return;
6373         }
6374
6375         /* Switch crtc and encoder back off if necessary */
6376         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6377                 connector->funcs->dpms(connector, old->dpms_mode);
6378 }
6379
6380 /* Returns the clock of the currently programmed mode of the given pipe. */
6381 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6382 {
6383         struct drm_i915_private *dev_priv = dev->dev_private;
6384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385         int pipe = intel_crtc->pipe;
6386         u32 dpll = I915_READ(DPLL(pipe));
6387         u32 fp;
6388         intel_clock_t clock;
6389
6390         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6391                 fp = I915_READ(FP0(pipe));
6392         else
6393                 fp = I915_READ(FP1(pipe));
6394
6395         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6396         if (IS_PINEVIEW(dev)) {
6397                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6398                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6399         } else {
6400                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6401                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6402         }
6403
6404         if (!IS_GEN2(dev)) {
6405                 if (IS_PINEVIEW(dev))
6406                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6407                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6408                 else
6409                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6410                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6411
6412                 switch (dpll & DPLL_MODE_MASK) {
6413                 case DPLLB_MODE_DAC_SERIAL:
6414                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6415                                 5 : 10;
6416                         break;
6417                 case DPLLB_MODE_LVDS:
6418                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6419                                 7 : 14;
6420                         break;
6421                 default:
6422                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6423                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6424                         return 0;
6425                 }
6426
6427                 /* XXX: Handle the 100Mhz refclk */
6428                 intel_clock(dev, 96000, &clock);
6429         } else {
6430                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6431
6432                 if (is_lvds) {
6433                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6434                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6435                         clock.p2 = 14;
6436
6437                         if ((dpll & PLL_REF_INPUT_MASK) ==
6438                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6439                                 /* XXX: might not be 66MHz */
6440                                 intel_clock(dev, 66000, &clock);
6441                         } else
6442                                 intel_clock(dev, 48000, &clock);
6443                 } else {
6444                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6445                                 clock.p1 = 2;
6446                         else {
6447                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6448                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6449                         }
6450                         if (dpll & PLL_P2_DIVIDE_BY_4)
6451                                 clock.p2 = 4;
6452                         else
6453                                 clock.p2 = 2;
6454
6455                         intel_clock(dev, 48000, &clock);
6456                 }
6457         }
6458
6459         /* XXX: It would be nice to validate the clocks, but we can't reuse
6460          * i830PllIsValid() because it relies on the xf86_config connector
6461          * configuration being accurate, which it isn't necessarily.
6462          */
6463
6464         return clock.dot;
6465 }
6466
6467 /** Returns the currently programmed mode of the given pipe. */
6468 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6469                                              struct drm_crtc *crtc)
6470 {
6471         struct drm_i915_private *dev_priv = dev->dev_private;
6472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473         int pipe = intel_crtc->pipe;
6474         struct drm_display_mode *mode;
6475         int htot = I915_READ(HTOTAL(pipe));
6476         int hsync = I915_READ(HSYNC(pipe));
6477         int vtot = I915_READ(VTOTAL(pipe));
6478         int vsync = I915_READ(VSYNC(pipe));
6479
6480         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6481         if (!mode)
6482                 return NULL;
6483
6484         mode->clock = intel_crtc_clock_get(dev, crtc);
6485         mode->hdisplay = (htot & 0xffff) + 1;
6486         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6487         mode->hsync_start = (hsync & 0xffff) + 1;
6488         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6489         mode->vdisplay = (vtot & 0xffff) + 1;
6490         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6491         mode->vsync_start = (vsync & 0xffff) + 1;
6492         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6493
6494         drm_mode_set_name(mode);
6495
6496         return mode;
6497 }
6498
6499 static void intel_increase_pllclock(struct drm_crtc *crtc)
6500 {
6501         struct drm_device *dev = crtc->dev;
6502         drm_i915_private_t *dev_priv = dev->dev_private;
6503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6504         int pipe = intel_crtc->pipe;
6505         int dpll_reg = DPLL(pipe);
6506         int dpll;
6507
6508         if (HAS_PCH_SPLIT(dev))
6509                 return;
6510
6511         if (!dev_priv->lvds_downclock_avail)
6512                 return;
6513
6514         dpll = I915_READ(dpll_reg);
6515         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6516                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6517
6518                 assert_panel_unlocked(dev_priv, pipe);
6519
6520                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6521                 I915_WRITE(dpll_reg, dpll);
6522                 intel_wait_for_vblank(dev, pipe);
6523
6524                 dpll = I915_READ(dpll_reg);
6525                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6526                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6527         }
6528 }
6529
6530 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6531 {
6532         struct drm_device *dev = crtc->dev;
6533         drm_i915_private_t *dev_priv = dev->dev_private;
6534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6535
6536         if (HAS_PCH_SPLIT(dev))
6537                 return;
6538
6539         if (!dev_priv->lvds_downclock_avail)
6540                 return;
6541
6542         /*
6543          * Since this is called by a timer, we should never get here in
6544          * the manual case.
6545          */
6546         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6547                 int pipe = intel_crtc->pipe;
6548                 int dpll_reg = DPLL(pipe);
6549                 int dpll;
6550
6551                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6552
6553                 assert_panel_unlocked(dev_priv, pipe);
6554
6555                 dpll = I915_READ(dpll_reg);
6556                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6557                 I915_WRITE(dpll_reg, dpll);
6558                 intel_wait_for_vblank(dev, pipe);
6559                 dpll = I915_READ(dpll_reg);
6560                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6561                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6562         }
6563
6564 }
6565
6566 void intel_mark_busy(struct drm_device *dev)
6567 {
6568         i915_update_gfx_val(dev->dev_private);
6569 }
6570
6571 void intel_mark_idle(struct drm_device *dev)
6572 {
6573 }
6574
6575 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6576 {
6577         struct drm_device *dev = obj->base.dev;
6578         struct drm_crtc *crtc;
6579
6580         if (!i915_powersave)
6581                 return;
6582
6583         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6584                 if (!crtc->fb)
6585                         continue;
6586
6587                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6588                         intel_increase_pllclock(crtc);
6589         }
6590 }
6591
6592 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6593 {
6594         struct drm_device *dev = obj->base.dev;
6595         struct drm_crtc *crtc;
6596
6597         if (!i915_powersave)
6598                 return;
6599
6600         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6601                 if (!crtc->fb)
6602                         continue;
6603
6604                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6605                         intel_decrease_pllclock(crtc);
6606         }
6607 }
6608
6609 static void intel_crtc_destroy(struct drm_crtc *crtc)
6610 {
6611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612         struct drm_device *dev = crtc->dev;
6613         struct intel_unpin_work *work;
6614         unsigned long flags;
6615
6616         spin_lock_irqsave(&dev->event_lock, flags);
6617         work = intel_crtc->unpin_work;
6618         intel_crtc->unpin_work = NULL;
6619         spin_unlock_irqrestore(&dev->event_lock, flags);
6620
6621         if (work) {
6622                 cancel_work_sync(&work->work);
6623                 kfree(work);
6624         }
6625
6626         drm_crtc_cleanup(crtc);
6627
6628         kfree(intel_crtc);
6629 }
6630
6631 static void intel_unpin_work_fn(struct work_struct *__work)
6632 {
6633         struct intel_unpin_work *work =
6634                 container_of(__work, struct intel_unpin_work, work);
6635
6636         mutex_lock(&work->dev->struct_mutex);
6637         intel_unpin_fb_obj(work->old_fb_obj);
6638         drm_gem_object_unreference(&work->pending_flip_obj->base);
6639         drm_gem_object_unreference(&work->old_fb_obj->base);
6640
6641         intel_update_fbc(work->dev);
6642         mutex_unlock(&work->dev->struct_mutex);
6643         kfree(work);
6644 }
6645
6646 static void do_intel_finish_page_flip(struct drm_device *dev,
6647                                       struct drm_crtc *crtc)
6648 {
6649         drm_i915_private_t *dev_priv = dev->dev_private;
6650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6651         struct intel_unpin_work *work;
6652         struct drm_i915_gem_object *obj;
6653         struct drm_pending_vblank_event *e;
6654         struct timeval tvbl;
6655         unsigned long flags;
6656
6657         /* Ignore early vblank irqs */
6658         if (intel_crtc == NULL)
6659                 return;
6660
6661         spin_lock_irqsave(&dev->event_lock, flags);
6662         work = intel_crtc->unpin_work;
6663         if (work == NULL || !work->pending) {
6664                 spin_unlock_irqrestore(&dev->event_lock, flags);
6665                 return;
6666         }
6667
6668         intel_crtc->unpin_work = NULL;
6669
6670         if (work->event) {
6671                 e = work->event;
6672                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6673
6674                 e->event.tv_sec = tvbl.tv_sec;
6675                 e->event.tv_usec = tvbl.tv_usec;
6676
6677                 list_add_tail(&e->base.link,
6678                               &e->base.file_priv->event_list);
6679                 wake_up_interruptible(&e->base.file_priv->event_wait);
6680         }
6681
6682         drm_vblank_put(dev, intel_crtc->pipe);
6683
6684         spin_unlock_irqrestore(&dev->event_lock, flags);
6685
6686         obj = work->old_fb_obj;
6687
6688         atomic_clear_mask(1 << intel_crtc->plane,
6689                           &obj->pending_flip.counter);
6690
6691         wake_up(&dev_priv->pending_flip_queue);
6692         schedule_work(&work->work);
6693
6694         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6695 }
6696
6697 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6698 {
6699         drm_i915_private_t *dev_priv = dev->dev_private;
6700         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6701
6702         do_intel_finish_page_flip(dev, crtc);
6703 }
6704
6705 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6706 {
6707         drm_i915_private_t *dev_priv = dev->dev_private;
6708         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6709
6710         do_intel_finish_page_flip(dev, crtc);
6711 }
6712
6713 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6714 {
6715         drm_i915_private_t *dev_priv = dev->dev_private;
6716         struct intel_crtc *intel_crtc =
6717                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6718         unsigned long flags;
6719
6720         spin_lock_irqsave(&dev->event_lock, flags);
6721         if (intel_crtc->unpin_work) {
6722                 if ((++intel_crtc->unpin_work->pending) > 1)
6723                         DRM_ERROR("Prepared flip multiple times\n");
6724         } else {
6725                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6726         }
6727         spin_unlock_irqrestore(&dev->event_lock, flags);
6728 }
6729
6730 static int intel_gen2_queue_flip(struct drm_device *dev,
6731                                  struct drm_crtc *crtc,
6732                                  struct drm_framebuffer *fb,
6733                                  struct drm_i915_gem_object *obj)
6734 {
6735         struct drm_i915_private *dev_priv = dev->dev_private;
6736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737         u32 flip_mask;
6738         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6739         int ret;
6740
6741         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6742         if (ret)
6743                 goto err;
6744
6745         ret = intel_ring_begin(ring, 6);
6746         if (ret)
6747                 goto err_unpin;
6748
6749         /* Can't queue multiple flips, so wait for the previous
6750          * one to finish before executing the next.
6751          */
6752         if (intel_crtc->plane)
6753                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6754         else
6755                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6756         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6757         intel_ring_emit(ring, MI_NOOP);
6758         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6759                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6760         intel_ring_emit(ring, fb->pitches[0]);
6761         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6762         intel_ring_emit(ring, 0); /* aux display base address, unused */
6763         intel_ring_advance(ring);
6764         return 0;
6765
6766 err_unpin:
6767         intel_unpin_fb_obj(obj);
6768 err:
6769         return ret;
6770 }
6771
6772 static int intel_gen3_queue_flip(struct drm_device *dev,
6773                                  struct drm_crtc *crtc,
6774                                  struct drm_framebuffer *fb,
6775                                  struct drm_i915_gem_object *obj)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6779         u32 flip_mask;
6780         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6781         int ret;
6782
6783         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6784         if (ret)
6785                 goto err;
6786
6787         ret = intel_ring_begin(ring, 6);
6788         if (ret)
6789                 goto err_unpin;
6790
6791         if (intel_crtc->plane)
6792                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6793         else
6794                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6795         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6796         intel_ring_emit(ring, MI_NOOP);
6797         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6798                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6799         intel_ring_emit(ring, fb->pitches[0]);
6800         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6801         intel_ring_emit(ring, MI_NOOP);
6802
6803         intel_ring_advance(ring);
6804         return 0;
6805
6806 err_unpin:
6807         intel_unpin_fb_obj(obj);
6808 err:
6809         return ret;
6810 }
6811
6812 static int intel_gen4_queue_flip(struct drm_device *dev,
6813                                  struct drm_crtc *crtc,
6814                                  struct drm_framebuffer *fb,
6815                                  struct drm_i915_gem_object *obj)
6816 {
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6819         uint32_t pf, pipesrc;
6820         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6821         int ret;
6822
6823         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6824         if (ret)
6825                 goto err;
6826
6827         ret = intel_ring_begin(ring, 4);
6828         if (ret)
6829                 goto err_unpin;
6830
6831         /* i965+ uses the linear or tiled offsets from the
6832          * Display Registers (which do not change across a page-flip)
6833          * so we need only reprogram the base address.
6834          */
6835         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6836                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6837         intel_ring_emit(ring, fb->pitches[0]);
6838         intel_ring_emit(ring,
6839                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6840                         obj->tiling_mode);
6841
6842         /* XXX Enabling the panel-fitter across page-flip is so far
6843          * untested on non-native modes, so ignore it for now.
6844          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6845          */
6846         pf = 0;
6847         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6848         intel_ring_emit(ring, pf | pipesrc);
6849         intel_ring_advance(ring);
6850         return 0;
6851
6852 err_unpin:
6853         intel_unpin_fb_obj(obj);
6854 err:
6855         return ret;
6856 }
6857
6858 static int intel_gen6_queue_flip(struct drm_device *dev,
6859                                  struct drm_crtc *crtc,
6860                                  struct drm_framebuffer *fb,
6861                                  struct drm_i915_gem_object *obj)
6862 {
6863         struct drm_i915_private *dev_priv = dev->dev_private;
6864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6865         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6866         uint32_t pf, pipesrc;
6867         int ret;
6868
6869         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6870         if (ret)
6871                 goto err;
6872
6873         ret = intel_ring_begin(ring, 4);
6874         if (ret)
6875                 goto err_unpin;
6876
6877         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6878                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6879         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6880         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6881
6882         /* Contrary to the suggestions in the documentation,
6883          * "Enable Panel Fitter" does not seem to be required when page
6884          * flipping with a non-native mode, and worse causes a normal
6885          * modeset to fail.
6886          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6887          */
6888         pf = 0;
6889         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6890         intel_ring_emit(ring, pf | pipesrc);
6891         intel_ring_advance(ring);
6892         return 0;
6893
6894 err_unpin:
6895         intel_unpin_fb_obj(obj);
6896 err:
6897         return ret;
6898 }
6899
6900 /*
6901  * On gen7 we currently use the blit ring because (in early silicon at least)
6902  * the render ring doesn't give us interrpts for page flip completion, which
6903  * means clients will hang after the first flip is queued.  Fortunately the
6904  * blit ring generates interrupts properly, so use it instead.
6905  */
6906 static int intel_gen7_queue_flip(struct drm_device *dev,
6907                                  struct drm_crtc *crtc,
6908                                  struct drm_framebuffer *fb,
6909                                  struct drm_i915_gem_object *obj)
6910 {
6911         struct drm_i915_private *dev_priv = dev->dev_private;
6912         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6913         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6914         uint32_t plane_bit = 0;
6915         int ret;
6916
6917         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6918         if (ret)
6919                 goto err;
6920
6921         switch(intel_crtc->plane) {
6922         case PLANE_A:
6923                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6924                 break;
6925         case PLANE_B:
6926                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6927                 break;
6928         case PLANE_C:
6929                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6930                 break;
6931         default:
6932                 WARN_ONCE(1, "unknown plane in flip command\n");
6933                 ret = -ENODEV;
6934                 goto err_unpin;
6935         }
6936
6937         ret = intel_ring_begin(ring, 4);
6938         if (ret)
6939                 goto err_unpin;
6940
6941         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6942         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6943         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6944         intel_ring_emit(ring, (MI_NOOP));
6945         intel_ring_advance(ring);
6946         return 0;
6947
6948 err_unpin:
6949         intel_unpin_fb_obj(obj);
6950 err:
6951         return ret;
6952 }
6953
6954 static int intel_default_queue_flip(struct drm_device *dev,
6955                                     struct drm_crtc *crtc,
6956                                     struct drm_framebuffer *fb,
6957                                     struct drm_i915_gem_object *obj)
6958 {
6959         return -ENODEV;
6960 }
6961
6962 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6963                                 struct drm_framebuffer *fb,
6964                                 struct drm_pending_vblank_event *event)
6965 {
6966         struct drm_device *dev = crtc->dev;
6967         struct drm_i915_private *dev_priv = dev->dev_private;
6968         struct intel_framebuffer *intel_fb;
6969         struct drm_i915_gem_object *obj;
6970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6971         struct intel_unpin_work *work;
6972         unsigned long flags;
6973         int ret;
6974
6975         /* Can't change pixel format via MI display flips. */
6976         if (fb->pixel_format != crtc->fb->pixel_format)
6977                 return -EINVAL;
6978
6979         /*
6980          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6981          * Note that pitch changes could also affect these register.
6982          */
6983         if (INTEL_INFO(dev)->gen > 3 &&
6984             (fb->offsets[0] != crtc->fb->offsets[0] ||
6985              fb->pitches[0] != crtc->fb->pitches[0]))
6986                 return -EINVAL;
6987
6988         work = kzalloc(sizeof *work, GFP_KERNEL);
6989         if (work == NULL)
6990                 return -ENOMEM;
6991
6992         work->event = event;
6993         work->dev = crtc->dev;
6994         intel_fb = to_intel_framebuffer(crtc->fb);
6995         work->old_fb_obj = intel_fb->obj;
6996         INIT_WORK(&work->work, intel_unpin_work_fn);
6997
6998         ret = drm_vblank_get(dev, intel_crtc->pipe);
6999         if (ret)
7000                 goto free_work;
7001
7002         /* We borrow the event spin lock for protecting unpin_work */
7003         spin_lock_irqsave(&dev->event_lock, flags);
7004         if (intel_crtc->unpin_work) {
7005                 spin_unlock_irqrestore(&dev->event_lock, flags);
7006                 kfree(work);
7007                 drm_vblank_put(dev, intel_crtc->pipe);
7008
7009                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7010                 return -EBUSY;
7011         }
7012         intel_crtc->unpin_work = work;
7013         spin_unlock_irqrestore(&dev->event_lock, flags);
7014
7015         intel_fb = to_intel_framebuffer(fb);
7016         obj = intel_fb->obj;
7017
7018         ret = i915_mutex_lock_interruptible(dev);
7019         if (ret)
7020                 goto cleanup;
7021
7022         /* Reference the objects for the scheduled work. */
7023         drm_gem_object_reference(&work->old_fb_obj->base);
7024         drm_gem_object_reference(&obj->base);
7025
7026         crtc->fb = fb;
7027
7028         work->pending_flip_obj = obj;
7029
7030         work->enable_stall_check = true;
7031
7032         /* Block clients from rendering to the new back buffer until
7033          * the flip occurs and the object is no longer visible.
7034          */
7035         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7036
7037         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7038         if (ret)
7039                 goto cleanup_pending;
7040
7041         intel_disable_fbc(dev);
7042         intel_mark_fb_busy(obj);
7043         mutex_unlock(&dev->struct_mutex);
7044
7045         trace_i915_flip_request(intel_crtc->plane, obj);
7046
7047         return 0;
7048
7049 cleanup_pending:
7050         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7051         drm_gem_object_unreference(&work->old_fb_obj->base);
7052         drm_gem_object_unreference(&obj->base);
7053         mutex_unlock(&dev->struct_mutex);
7054
7055 cleanup:
7056         spin_lock_irqsave(&dev->event_lock, flags);
7057         intel_crtc->unpin_work = NULL;
7058         spin_unlock_irqrestore(&dev->event_lock, flags);
7059
7060         drm_vblank_put(dev, intel_crtc->pipe);
7061 free_work:
7062         kfree(work);
7063
7064         return ret;
7065 }
7066
7067 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7068         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7069         .load_lut = intel_crtc_load_lut,
7070         .disable = intel_crtc_noop,
7071 };
7072
7073 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7074 {
7075         struct intel_encoder *other_encoder;
7076         struct drm_crtc *crtc = &encoder->new_crtc->base;
7077
7078         if (WARN_ON(!crtc))
7079                 return false;
7080
7081         list_for_each_entry(other_encoder,
7082                             &crtc->dev->mode_config.encoder_list,
7083                             base.head) {
7084
7085                 if (&other_encoder->new_crtc->base != crtc ||
7086                     encoder == other_encoder)
7087                         continue;
7088                 else
7089                         return true;
7090         }
7091
7092         return false;
7093 }
7094
7095 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7096                                   struct drm_crtc *crtc)
7097 {
7098         struct drm_device *dev;
7099         struct drm_crtc *tmp;
7100         int crtc_mask = 1;
7101
7102         WARN(!crtc, "checking null crtc?\n");
7103
7104         dev = crtc->dev;
7105
7106         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7107                 if (tmp == crtc)
7108                         break;
7109                 crtc_mask <<= 1;
7110         }
7111
7112         if (encoder->possible_crtcs & crtc_mask)
7113                 return true;
7114         return false;
7115 }
7116
7117 /**
7118  * intel_modeset_update_staged_output_state
7119  *
7120  * Updates the staged output configuration state, e.g. after we've read out the
7121  * current hw state.
7122  */
7123 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7124 {
7125         struct intel_encoder *encoder;
7126         struct intel_connector *connector;
7127
7128         list_for_each_entry(connector, &dev->mode_config.connector_list,
7129                             base.head) {
7130                 connector->new_encoder =
7131                         to_intel_encoder(connector->base.encoder);
7132         }
7133
7134         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7135                             base.head) {
7136                 encoder->new_crtc =
7137                         to_intel_crtc(encoder->base.crtc);
7138         }
7139 }
7140
7141 /**
7142  * intel_modeset_commit_output_state
7143  *
7144  * This function copies the stage display pipe configuration to the real one.
7145  */
7146 static void intel_modeset_commit_output_state(struct drm_device *dev)
7147 {
7148         struct intel_encoder *encoder;
7149         struct intel_connector *connector;
7150
7151         list_for_each_entry(connector, &dev->mode_config.connector_list,
7152                             base.head) {
7153                 connector->base.encoder = &connector->new_encoder->base;
7154         }
7155
7156         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7157                             base.head) {
7158                 encoder->base.crtc = &encoder->new_crtc->base;
7159         }
7160 }
7161
7162 static struct drm_display_mode *
7163 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7164                             struct drm_display_mode *mode)
7165 {
7166         struct drm_device *dev = crtc->dev;
7167         struct drm_display_mode *adjusted_mode;
7168         struct drm_encoder_helper_funcs *encoder_funcs;
7169         struct intel_encoder *encoder;
7170
7171         adjusted_mode = drm_mode_duplicate(dev, mode);
7172         if (!adjusted_mode)
7173                 return ERR_PTR(-ENOMEM);
7174
7175         /* Pass our mode to the connectors and the CRTC to give them a chance to
7176          * adjust it according to limitations or connector properties, and also
7177          * a chance to reject the mode entirely.
7178          */
7179         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7180                             base.head) {
7181
7182                 if (&encoder->new_crtc->base != crtc)
7183                         continue;
7184                 encoder_funcs = encoder->base.helper_private;
7185                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7186                                                 adjusted_mode))) {
7187                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7188                         goto fail;
7189                 }
7190         }
7191
7192         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7193                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7194                 goto fail;
7195         }
7196         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7197
7198         return adjusted_mode;
7199 fail:
7200         drm_mode_destroy(dev, adjusted_mode);
7201         return ERR_PTR(-EINVAL);
7202 }
7203
7204 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7205  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7206 static void
7207 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7208                              unsigned *prepare_pipes, unsigned *disable_pipes)
7209 {
7210         struct intel_crtc *intel_crtc;
7211         struct drm_device *dev = crtc->dev;
7212         struct intel_encoder *encoder;
7213         struct intel_connector *connector;
7214         struct drm_crtc *tmp_crtc;
7215
7216         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7217
7218         /* Check which crtcs have changed outputs connected to them, these need
7219          * to be part of the prepare_pipes mask. We don't (yet) support global
7220          * modeset across multiple crtcs, so modeset_pipes will only have one
7221          * bit set at most. */
7222         list_for_each_entry(connector, &dev->mode_config.connector_list,
7223                             base.head) {
7224                 if (connector->base.encoder == &connector->new_encoder->base)
7225                         continue;
7226
7227                 if (connector->base.encoder) {
7228                         tmp_crtc = connector->base.encoder->crtc;
7229
7230                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7231                 }
7232
7233                 if (connector->new_encoder)
7234                         *prepare_pipes |=
7235                                 1 << connector->new_encoder->new_crtc->pipe;
7236         }
7237
7238         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7239                             base.head) {
7240                 if (encoder->base.crtc == &encoder->new_crtc->base)
7241                         continue;
7242
7243                 if (encoder->base.crtc) {
7244                         tmp_crtc = encoder->base.crtc;
7245
7246                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7247                 }
7248
7249                 if (encoder->new_crtc)
7250                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7251         }
7252
7253         /* Check for any pipes that will be fully disabled ... */
7254         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7255                             base.head) {
7256                 bool used = false;
7257
7258                 /* Don't try to disable disabled crtcs. */
7259                 if (!intel_crtc->base.enabled)
7260                         continue;
7261
7262                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7263                                     base.head) {
7264                         if (encoder->new_crtc == intel_crtc)
7265                                 used = true;
7266                 }
7267
7268                 if (!used)
7269                         *disable_pipes |= 1 << intel_crtc->pipe;
7270         }
7271
7272
7273         /* set_mode is also used to update properties on life display pipes. */
7274         intel_crtc = to_intel_crtc(crtc);
7275         if (crtc->enabled)
7276                 *prepare_pipes |= 1 << intel_crtc->pipe;
7277
7278         /* We only support modeset on one single crtc, hence we need to do that
7279          * only for the passed in crtc iff we change anything else than just
7280          * disable crtcs.
7281          *
7282          * This is actually not true, to be fully compatible with the old crtc
7283          * helper we automatically disable _any_ output (i.e. doesn't need to be
7284          * connected to the crtc we're modesetting on) if it's disconnected.
7285          * Which is a rather nutty api (since changed the output configuration
7286          * without userspace's explicit request can lead to confusion), but
7287          * alas. Hence we currently need to modeset on all pipes we prepare. */
7288         if (*prepare_pipes)
7289                 *modeset_pipes = *prepare_pipes;
7290
7291         /* ... and mask these out. */
7292         *modeset_pipes &= ~(*disable_pipes);
7293         *prepare_pipes &= ~(*disable_pipes);
7294 }
7295
7296 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7297 {
7298         struct drm_encoder *encoder;
7299         struct drm_device *dev = crtc->dev;
7300
7301         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7302                 if (encoder->crtc == crtc)
7303                         return true;
7304
7305         return false;
7306 }
7307
7308 static void
7309 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7310 {
7311         struct intel_encoder *intel_encoder;
7312         struct intel_crtc *intel_crtc;
7313         struct drm_connector *connector;
7314
7315         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7316                             base.head) {
7317                 if (!intel_encoder->base.crtc)
7318                         continue;
7319
7320                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7321
7322                 if (prepare_pipes & (1 << intel_crtc->pipe))
7323                         intel_encoder->connectors_active = false;
7324         }
7325
7326         intel_modeset_commit_output_state(dev);
7327
7328         /* Update computed state. */
7329         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7330                             base.head) {
7331                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7332         }
7333
7334         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7335                 if (!connector->encoder || !connector->encoder->crtc)
7336                         continue;
7337
7338                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7339
7340                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7341                         struct drm_property *dpms_property =
7342                                 dev->mode_config.dpms_property;
7343
7344                         connector->dpms = DRM_MODE_DPMS_ON;
7345                         drm_connector_property_set_value(connector,
7346                                                          dpms_property,
7347                                                          DRM_MODE_DPMS_ON);
7348
7349                         intel_encoder = to_intel_encoder(connector->encoder);
7350                         intel_encoder->connectors_active = true;
7351                 }
7352         }
7353
7354 }
7355
7356 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7357         list_for_each_entry((intel_crtc), \
7358                             &(dev)->mode_config.crtc_list, \
7359                             base.head) \
7360                 if (mask & (1 <<(intel_crtc)->pipe)) \
7361
7362 void
7363 intel_modeset_check_state(struct drm_device *dev)
7364 {
7365         struct intel_crtc *crtc;
7366         struct intel_encoder *encoder;
7367         struct intel_connector *connector;
7368
7369         list_for_each_entry(connector, &dev->mode_config.connector_list,
7370                             base.head) {
7371                 /* This also checks the encoder/connector hw state with the
7372                  * ->get_hw_state callbacks. */
7373                 intel_connector_check_state(connector);
7374
7375                 WARN(&connector->new_encoder->base != connector->base.encoder,
7376                      "connector's staged encoder doesn't match current encoder\n");
7377         }
7378
7379         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7380                             base.head) {
7381                 bool enabled = false;
7382                 bool active = false;
7383                 enum pipe pipe, tracked_pipe;
7384
7385                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7386                               encoder->base.base.id,
7387                               drm_get_encoder_name(&encoder->base));
7388
7389                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7390                      "encoder's stage crtc doesn't match current crtc\n");
7391                 WARN(encoder->connectors_active && !encoder->base.crtc,
7392                      "encoder's active_connectors set, but no crtc\n");
7393
7394                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7395                                     base.head) {
7396                         if (connector->base.encoder != &encoder->base)
7397                                 continue;
7398                         enabled = true;
7399                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7400                                 active = true;
7401                 }
7402                 WARN(!!encoder->base.crtc != enabled,
7403                      "encoder's enabled state mismatch "
7404                      "(expected %i, found %i)\n",
7405                      !!encoder->base.crtc, enabled);
7406                 WARN(active && !encoder->base.crtc,
7407                      "active encoder with no crtc\n");
7408
7409                 WARN(encoder->connectors_active != active,
7410                      "encoder's computed active state doesn't match tracked active state "
7411                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7412
7413                 active = encoder->get_hw_state(encoder, &pipe);
7414                 WARN(active != encoder->connectors_active,
7415                      "encoder's hw state doesn't match sw tracking "
7416                      "(expected %i, found %i)\n",
7417                      encoder->connectors_active, active);
7418
7419                 if (!encoder->base.crtc)
7420                         continue;
7421
7422                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7423                 WARN(active && pipe != tracked_pipe,
7424                      "active encoder's pipe doesn't match"
7425                      "(expected %i, found %i)\n",
7426                      tracked_pipe, pipe);
7427
7428         }
7429
7430         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7431                             base.head) {
7432                 bool enabled = false;
7433                 bool active = false;
7434
7435                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7436                               crtc->base.base.id);
7437
7438                 WARN(crtc->active && !crtc->base.enabled,
7439                      "active crtc, but not enabled in sw tracking\n");
7440
7441                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7442                                     base.head) {
7443                         if (encoder->base.crtc != &crtc->base)
7444                                 continue;
7445                         enabled = true;
7446                         if (encoder->connectors_active)
7447                                 active = true;
7448                 }
7449                 WARN(active != crtc->active,
7450                      "crtc's computed active state doesn't match tracked active state "
7451                      "(expected %i, found %i)\n", active, crtc->active);
7452                 WARN(enabled != crtc->base.enabled,
7453                      "crtc's computed enabled state doesn't match tracked enabled state "
7454                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7455
7456                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7457         }
7458 }
7459
7460 bool intel_set_mode(struct drm_crtc *crtc,
7461                     struct drm_display_mode *mode,
7462                     int x, int y, struct drm_framebuffer *fb)
7463 {
7464         struct drm_device *dev = crtc->dev;
7465         drm_i915_private_t *dev_priv = dev->dev_private;
7466         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7467         struct drm_encoder_helper_funcs *encoder_funcs;
7468         struct drm_encoder *encoder;
7469         struct intel_crtc *intel_crtc;
7470         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7471         bool ret = true;
7472
7473         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7474                                      &prepare_pipes, &disable_pipes);
7475
7476         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7477                       modeset_pipes, prepare_pipes, disable_pipes);
7478
7479         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7480                 intel_crtc_disable(&intel_crtc->base);
7481
7482         saved_hwmode = crtc->hwmode;
7483         saved_mode = crtc->mode;
7484
7485         /* Hack: Because we don't (yet) support global modeset on multiple
7486          * crtcs, we don't keep track of the new mode for more than one crtc.
7487          * Hence simply check whether any bit is set in modeset_pipes in all the
7488          * pieces of code that are not yet converted to deal with mutliple crtcs
7489          * changing their mode at the same time. */
7490         adjusted_mode = NULL;
7491         if (modeset_pipes) {
7492                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7493                 if (IS_ERR(adjusted_mode)) {
7494                         return false;
7495                 }
7496         }
7497
7498         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7499                 if (intel_crtc->base.enabled)
7500                         dev_priv->display.crtc_disable(&intel_crtc->base);
7501         }
7502
7503         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7504          * to set it here already despite that we pass it down the callchain.
7505          */
7506         if (modeset_pipes)
7507                 crtc->mode = *mode;
7508
7509         /* Only after disabling all output pipelines that will be changed can we
7510          * update the the output configuration. */
7511         intel_modeset_update_state(dev, prepare_pipes);
7512
7513         /* Set up the DPLL and any encoders state that needs to adjust or depend
7514          * on the DPLL.
7515          */
7516         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7517                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7518                                            mode, adjusted_mode,
7519                                            x, y, fb);
7520                 if (!ret)
7521                     goto done;
7522
7523                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7524
7525                         if (encoder->crtc != &intel_crtc->base)
7526                                 continue;
7527
7528                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7529                                 encoder->base.id, drm_get_encoder_name(encoder),
7530                                 mode->base.id, mode->name);
7531                         encoder_funcs = encoder->helper_private;
7532                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7533                 }
7534         }
7535
7536         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7537         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7538                 dev_priv->display.crtc_enable(&intel_crtc->base);
7539
7540         if (modeset_pipes) {
7541                 /* Store real post-adjustment hardware mode. */
7542                 crtc->hwmode = *adjusted_mode;
7543
7544                 /* Calculate and store various constants which
7545                  * are later needed by vblank and swap-completion
7546                  * timestamping. They are derived from true hwmode.
7547                  */
7548                 drm_calc_timestamping_constants(crtc);
7549         }
7550
7551         /* FIXME: add subpixel order */
7552 done:
7553         drm_mode_destroy(dev, adjusted_mode);
7554         if (!ret && crtc->enabled) {
7555                 crtc->hwmode = saved_hwmode;
7556                 crtc->mode = saved_mode;
7557         } else {
7558                 intel_modeset_check_state(dev);
7559         }
7560
7561         return ret;
7562 }
7563
7564 #undef for_each_intel_crtc_masked
7565
7566 static void intel_set_config_free(struct intel_set_config *config)
7567 {
7568         if (!config)
7569                 return;
7570
7571         kfree(config->save_connector_encoders);
7572         kfree(config->save_encoder_crtcs);
7573         kfree(config);
7574 }
7575
7576 static int intel_set_config_save_state(struct drm_device *dev,
7577                                        struct intel_set_config *config)
7578 {
7579         struct drm_encoder *encoder;
7580         struct drm_connector *connector;
7581         int count;
7582
7583         config->save_encoder_crtcs =
7584                 kcalloc(dev->mode_config.num_encoder,
7585                         sizeof(struct drm_crtc *), GFP_KERNEL);
7586         if (!config->save_encoder_crtcs)
7587                 return -ENOMEM;
7588
7589         config->save_connector_encoders =
7590                 kcalloc(dev->mode_config.num_connector,
7591                         sizeof(struct drm_encoder *), GFP_KERNEL);
7592         if (!config->save_connector_encoders)
7593                 return -ENOMEM;
7594
7595         /* Copy data. Note that driver private data is not affected.
7596          * Should anything bad happen only the expected state is
7597          * restored, not the drivers personal bookkeeping.
7598          */
7599         count = 0;
7600         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7601                 config->save_encoder_crtcs[count++] = encoder->crtc;
7602         }
7603
7604         count = 0;
7605         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7606                 config->save_connector_encoders[count++] = connector->encoder;
7607         }
7608
7609         return 0;
7610 }
7611
7612 static void intel_set_config_restore_state(struct drm_device *dev,
7613                                            struct intel_set_config *config)
7614 {
7615         struct intel_encoder *encoder;
7616         struct intel_connector *connector;
7617         int count;
7618
7619         count = 0;
7620         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7621                 encoder->new_crtc =
7622                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7623         }
7624
7625         count = 0;
7626         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7627                 connector->new_encoder =
7628                         to_intel_encoder(config->save_connector_encoders[count++]);
7629         }
7630 }
7631
7632 static void
7633 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7634                                       struct intel_set_config *config)
7635 {
7636
7637         /* We should be able to check here if the fb has the same properties
7638          * and then just flip_or_move it */
7639         if (set->crtc->fb != set->fb) {
7640                 /* If we have no fb then treat it as a full mode set */
7641                 if (set->crtc->fb == NULL) {
7642                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7643                         config->mode_changed = true;
7644                 } else if (set->fb == NULL) {
7645                         config->mode_changed = true;
7646                 } else if (set->fb->depth != set->crtc->fb->depth) {
7647                         config->mode_changed = true;
7648                 } else if (set->fb->bits_per_pixel !=
7649                            set->crtc->fb->bits_per_pixel) {
7650                         config->mode_changed = true;
7651                 } else
7652                         config->fb_changed = true;
7653         }
7654
7655         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7656                 config->fb_changed = true;
7657
7658         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7659                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7660                 drm_mode_debug_printmodeline(&set->crtc->mode);
7661                 drm_mode_debug_printmodeline(set->mode);
7662                 config->mode_changed = true;
7663         }
7664 }
7665
7666 static int
7667 intel_modeset_stage_output_state(struct drm_device *dev,
7668                                  struct drm_mode_set *set,
7669                                  struct intel_set_config *config)
7670 {
7671         struct drm_crtc *new_crtc;
7672         struct intel_connector *connector;
7673         struct intel_encoder *encoder;
7674         int count, ro;
7675
7676         /* The upper layers ensure that we either disabl a crtc or have a list
7677          * of connectors. For paranoia, double-check this. */
7678         WARN_ON(!set->fb && (set->num_connectors != 0));
7679         WARN_ON(set->fb && (set->num_connectors == 0));
7680
7681         count = 0;
7682         list_for_each_entry(connector, &dev->mode_config.connector_list,
7683                             base.head) {
7684                 /* Otherwise traverse passed in connector list and get encoders
7685                  * for them. */
7686                 for (ro = 0; ro < set->num_connectors; ro++) {
7687                         if (set->connectors[ro] == &connector->base) {
7688                                 connector->new_encoder = connector->encoder;
7689                                 break;
7690                         }
7691                 }
7692
7693                 /* If we disable the crtc, disable all its connectors. Also, if
7694                  * the connector is on the changing crtc but not on the new
7695                  * connector list, disable it. */
7696                 if ((!set->fb || ro == set->num_connectors) &&
7697                     connector->base.encoder &&
7698                     connector->base.encoder->crtc == set->crtc) {
7699                         connector->new_encoder = NULL;
7700
7701                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7702                                 connector->base.base.id,
7703                                 drm_get_connector_name(&connector->base));
7704                 }
7705
7706
7707                 if (&connector->new_encoder->base != connector->base.encoder) {
7708                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7709                         config->mode_changed = true;
7710                 }
7711
7712                 /* Disable all disconnected encoders. */
7713                 if (connector->base.status == connector_status_disconnected)
7714                         connector->new_encoder = NULL;
7715         }
7716         /* connector->new_encoder is now updated for all connectors. */
7717
7718         /* Update crtc of enabled connectors. */
7719         count = 0;
7720         list_for_each_entry(connector, &dev->mode_config.connector_list,
7721                             base.head) {
7722                 if (!connector->new_encoder)
7723                         continue;
7724
7725                 new_crtc = connector->new_encoder->base.crtc;
7726
7727                 for (ro = 0; ro < set->num_connectors; ro++) {
7728                         if (set->connectors[ro] == &connector->base)
7729                                 new_crtc = set->crtc;
7730                 }
7731
7732                 /* Make sure the new CRTC will work with the encoder */
7733                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7734                                            new_crtc)) {
7735                         return -EINVAL;
7736                 }
7737                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7738
7739                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7740                         connector->base.base.id,
7741                         drm_get_connector_name(&connector->base),
7742                         new_crtc->base.id);
7743         }
7744
7745         /* Check for any encoders that needs to be disabled. */
7746         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7747                             base.head) {
7748                 list_for_each_entry(connector,
7749                                     &dev->mode_config.connector_list,
7750                                     base.head) {
7751                         if (connector->new_encoder == encoder) {
7752                                 WARN_ON(!connector->new_encoder->new_crtc);
7753
7754                                 goto next_encoder;
7755                         }
7756                 }
7757                 encoder->new_crtc = NULL;
7758 next_encoder:
7759                 /* Only now check for crtc changes so we don't miss encoders
7760                  * that will be disabled. */
7761                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7762                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7763                         config->mode_changed = true;
7764                 }
7765         }
7766         /* Now we've also updated encoder->new_crtc for all encoders. */
7767
7768         return 0;
7769 }
7770
7771 static int intel_crtc_set_config(struct drm_mode_set *set)
7772 {
7773         struct drm_device *dev;
7774         struct drm_mode_set save_set;
7775         struct intel_set_config *config;
7776         int ret;
7777
7778         BUG_ON(!set);
7779         BUG_ON(!set->crtc);
7780         BUG_ON(!set->crtc->helper_private);
7781
7782         if (!set->mode)
7783                 set->fb = NULL;
7784
7785         /* The fb helper likes to play gross jokes with ->mode_set_config.
7786          * Unfortunately the crtc helper doesn't do much at all for this case,
7787          * so we have to cope with this madness until the fb helper is fixed up. */
7788         if (set->fb && set->num_connectors == 0)
7789                 return 0;
7790
7791         if (set->fb) {
7792                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7793                                 set->crtc->base.id, set->fb->base.id,
7794                                 (int)set->num_connectors, set->x, set->y);
7795         } else {
7796                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7797         }
7798
7799         dev = set->crtc->dev;
7800
7801         ret = -ENOMEM;
7802         config = kzalloc(sizeof(*config), GFP_KERNEL);
7803         if (!config)
7804                 goto out_config;
7805
7806         ret = intel_set_config_save_state(dev, config);
7807         if (ret)
7808                 goto out_config;
7809
7810         save_set.crtc = set->crtc;
7811         save_set.mode = &set->crtc->mode;
7812         save_set.x = set->crtc->x;
7813         save_set.y = set->crtc->y;
7814         save_set.fb = set->crtc->fb;
7815
7816         /* Compute whether we need a full modeset, only an fb base update or no
7817          * change at all. In the future we might also check whether only the
7818          * mode changed, e.g. for LVDS where we only change the panel fitter in
7819          * such cases. */
7820         intel_set_config_compute_mode_changes(set, config);
7821
7822         ret = intel_modeset_stage_output_state(dev, set, config);
7823         if (ret)
7824                 goto fail;
7825
7826         if (config->mode_changed) {
7827                 if (set->mode) {
7828                         DRM_DEBUG_KMS("attempting to set mode from"
7829                                         " userspace\n");
7830                         drm_mode_debug_printmodeline(set->mode);
7831                 }
7832
7833                 if (!intel_set_mode(set->crtc, set->mode,
7834                                     set->x, set->y, set->fb)) {
7835                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7836                                   set->crtc->base.id);
7837                         ret = -EINVAL;
7838                         goto fail;
7839                 }
7840         } else if (config->fb_changed) {
7841                 ret = intel_pipe_set_base(set->crtc,
7842                                           set->x, set->y, set->fb);
7843         }
7844
7845         intel_set_config_free(config);
7846
7847         return 0;
7848
7849 fail:
7850         intel_set_config_restore_state(dev, config);
7851
7852         /* Try to restore the config */
7853         if (config->mode_changed &&
7854             !intel_set_mode(save_set.crtc, save_set.mode,
7855                             save_set.x, save_set.y, save_set.fb))
7856                 DRM_ERROR("failed to restore config after modeset failure\n");
7857
7858 out_config:
7859         intel_set_config_free(config);
7860         return ret;
7861 }
7862
7863 static const struct drm_crtc_funcs intel_crtc_funcs = {
7864         .cursor_set = intel_crtc_cursor_set,
7865         .cursor_move = intel_crtc_cursor_move,
7866         .gamma_set = intel_crtc_gamma_set,
7867         .set_config = intel_crtc_set_config,
7868         .destroy = intel_crtc_destroy,
7869         .page_flip = intel_crtc_page_flip,
7870 };
7871
7872 static void intel_cpu_pll_init(struct drm_device *dev)
7873 {
7874         if (IS_HASWELL(dev))
7875                 intel_ddi_pll_init(dev);
7876 }
7877
7878 static void intel_pch_pll_init(struct drm_device *dev)
7879 {
7880         drm_i915_private_t *dev_priv = dev->dev_private;
7881         int i;
7882
7883         if (dev_priv->num_pch_pll == 0) {
7884                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7885                 return;
7886         }
7887
7888         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7889                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7890                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7891                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7892         }
7893 }
7894
7895 static void intel_crtc_init(struct drm_device *dev, int pipe)
7896 {
7897         drm_i915_private_t *dev_priv = dev->dev_private;
7898         struct intel_crtc *intel_crtc;
7899         int i;
7900
7901         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7902         if (intel_crtc == NULL)
7903                 return;
7904
7905         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7906
7907         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7908         for (i = 0; i < 256; i++) {
7909                 intel_crtc->lut_r[i] = i;
7910                 intel_crtc->lut_g[i] = i;
7911                 intel_crtc->lut_b[i] = i;
7912         }
7913
7914         /* Swap pipes & planes for FBC on pre-965 */
7915         intel_crtc->pipe = pipe;
7916         intel_crtc->plane = pipe;
7917         intel_crtc->cpu_transcoder = pipe;
7918         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7919                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7920                 intel_crtc->plane = !pipe;
7921         }
7922
7923         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7924                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7925         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7926         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7927
7928         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7929
7930         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7931 }
7932
7933 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7934                                 struct drm_file *file)
7935 {
7936         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7937         struct drm_mode_object *drmmode_obj;
7938         struct intel_crtc *crtc;
7939
7940         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7941                 return -ENODEV;
7942
7943         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7944                         DRM_MODE_OBJECT_CRTC);
7945
7946         if (!drmmode_obj) {
7947                 DRM_ERROR("no such CRTC id\n");
7948                 return -EINVAL;
7949         }
7950
7951         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7952         pipe_from_crtc_id->pipe = crtc->pipe;
7953
7954         return 0;
7955 }
7956
7957 static int intel_encoder_clones(struct intel_encoder *encoder)
7958 {
7959         struct drm_device *dev = encoder->base.dev;
7960         struct intel_encoder *source_encoder;
7961         int index_mask = 0;
7962         int entry = 0;
7963
7964         list_for_each_entry(source_encoder,
7965                             &dev->mode_config.encoder_list, base.head) {
7966
7967                 if (encoder == source_encoder)
7968                         index_mask |= (1 << entry);
7969
7970                 /* Intel hw has only one MUX where enocoders could be cloned. */
7971                 if (encoder->cloneable && source_encoder->cloneable)
7972                         index_mask |= (1 << entry);
7973
7974                 entry++;
7975         }
7976
7977         return index_mask;
7978 }
7979
7980 static bool has_edp_a(struct drm_device *dev)
7981 {
7982         struct drm_i915_private *dev_priv = dev->dev_private;
7983
7984         if (!IS_MOBILE(dev))
7985                 return false;
7986
7987         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7988                 return false;
7989
7990         if (IS_GEN5(dev) &&
7991             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7992                 return false;
7993
7994         return true;
7995 }
7996
7997 static void intel_setup_outputs(struct drm_device *dev)
7998 {
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         struct intel_encoder *encoder;
8001         bool dpd_is_edp = false;
8002         bool has_lvds;
8003
8004         has_lvds = intel_lvds_init(dev);
8005         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8006                 /* disable the panel fitter on everything but LVDS */
8007                 I915_WRITE(PFIT_CONTROL, 0);
8008         }
8009
8010         if (HAS_PCH_SPLIT(dev)) {
8011                 dpd_is_edp = intel_dpd_is_edp(dev);
8012
8013                 if (has_edp_a(dev))
8014                         intel_dp_init(dev, DP_A, PORT_A);
8015
8016                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8017                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8018         }
8019
8020         intel_crt_init(dev);
8021
8022         if (IS_HASWELL(dev)) {
8023                 int found;
8024
8025                 /* Haswell uses DDI functions to detect digital outputs */
8026                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8027                 /* DDI A only supports eDP */
8028                 if (found)
8029                         intel_ddi_init(dev, PORT_A);
8030
8031                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8032                  * register */
8033                 found = I915_READ(SFUSE_STRAP);
8034
8035                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8036                         intel_ddi_init(dev, PORT_B);
8037                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8038                         intel_ddi_init(dev, PORT_C);
8039                 if (found & SFUSE_STRAP_DDID_DETECTED)
8040                         intel_ddi_init(dev, PORT_D);
8041         } else if (HAS_PCH_SPLIT(dev)) {
8042                 int found;
8043
8044                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8045                         /* PCH SDVOB multiplex with HDMIB */
8046                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8047                         if (!found)
8048                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8049                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8050                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8051                 }
8052
8053                 if (I915_READ(HDMIC) & PORT_DETECTED)
8054                         intel_hdmi_init(dev, HDMIC, PORT_C);
8055
8056                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8057                         intel_hdmi_init(dev, HDMID, PORT_D);
8058
8059                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8060                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8061
8062                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8063                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8064         } else if (IS_VALLEYVIEW(dev)) {
8065                 int found;
8066
8067                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8068                 if (I915_READ(DP_C) & DP_DETECTED)
8069                         intel_dp_init(dev, DP_C, PORT_C);
8070
8071                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8072                         /* SDVOB multiplex with HDMIB */
8073                         found = intel_sdvo_init(dev, SDVOB, true);
8074                         if (!found)
8075                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8076                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8077                                 intel_dp_init(dev, DP_B, PORT_B);
8078                 }
8079
8080                 if (I915_READ(SDVOC) & PORT_DETECTED)
8081                         intel_hdmi_init(dev, SDVOC, PORT_C);
8082
8083         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8084                 bool found = false;
8085
8086                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8087                         DRM_DEBUG_KMS("probing SDVOB\n");
8088                         found = intel_sdvo_init(dev, SDVOB, true);
8089                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8090                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8091                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8092                         }
8093
8094                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8095                                 DRM_DEBUG_KMS("probing DP_B\n");
8096                                 intel_dp_init(dev, DP_B, PORT_B);
8097                         }
8098                 }
8099
8100                 /* Before G4X SDVOC doesn't have its own detect register */
8101
8102                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8103                         DRM_DEBUG_KMS("probing SDVOC\n");
8104                         found = intel_sdvo_init(dev, SDVOC, false);
8105                 }
8106
8107                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8108
8109                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8110                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8111                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8112                         }
8113                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8114                                 DRM_DEBUG_KMS("probing DP_C\n");
8115                                 intel_dp_init(dev, DP_C, PORT_C);
8116                         }
8117                 }
8118
8119                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8120                     (I915_READ(DP_D) & DP_DETECTED)) {
8121                         DRM_DEBUG_KMS("probing DP_D\n");
8122                         intel_dp_init(dev, DP_D, PORT_D);
8123                 }
8124         } else if (IS_GEN2(dev))
8125                 intel_dvo_init(dev);
8126
8127         if (SUPPORTS_TV(dev))
8128                 intel_tv_init(dev);
8129
8130         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8131                 encoder->base.possible_crtcs = encoder->crtc_mask;
8132                 encoder->base.possible_clones =
8133                         intel_encoder_clones(encoder);
8134         }
8135
8136         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8137                 ironlake_init_pch_refclk(dev);
8138 }
8139
8140 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8141 {
8142         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8143
8144         drm_framebuffer_cleanup(fb);
8145         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8146
8147         kfree(intel_fb);
8148 }
8149
8150 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8151                                                 struct drm_file *file,
8152                                                 unsigned int *handle)
8153 {
8154         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8155         struct drm_i915_gem_object *obj = intel_fb->obj;
8156
8157         return drm_gem_handle_create(file, &obj->base, handle);
8158 }
8159
8160 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8161         .destroy = intel_user_framebuffer_destroy,
8162         .create_handle = intel_user_framebuffer_create_handle,
8163 };
8164
8165 int intel_framebuffer_init(struct drm_device *dev,
8166                            struct intel_framebuffer *intel_fb,
8167                            struct drm_mode_fb_cmd2 *mode_cmd,
8168                            struct drm_i915_gem_object *obj)
8169 {
8170         int ret;
8171
8172         if (obj->tiling_mode == I915_TILING_Y)
8173                 return -EINVAL;
8174
8175         if (mode_cmd->pitches[0] & 63)
8176                 return -EINVAL;
8177
8178         switch (mode_cmd->pixel_format) {
8179         case DRM_FORMAT_RGB332:
8180         case DRM_FORMAT_RGB565:
8181         case DRM_FORMAT_XRGB8888:
8182         case DRM_FORMAT_XBGR8888:
8183         case DRM_FORMAT_ARGB8888:
8184         case DRM_FORMAT_XRGB2101010:
8185         case DRM_FORMAT_ARGB2101010:
8186                 /* RGB formats are common across chipsets */
8187                 break;
8188         case DRM_FORMAT_YUYV:
8189         case DRM_FORMAT_UYVY:
8190         case DRM_FORMAT_YVYU:
8191         case DRM_FORMAT_VYUY:
8192                 break;
8193         default:
8194                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8195                                 mode_cmd->pixel_format);
8196                 return -EINVAL;
8197         }
8198
8199         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8200         if (ret) {
8201                 DRM_ERROR("framebuffer init failed %d\n", ret);
8202                 return ret;
8203         }
8204
8205         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8206         intel_fb->obj = obj;
8207         return 0;
8208 }
8209
8210 static struct drm_framebuffer *
8211 intel_user_framebuffer_create(struct drm_device *dev,
8212                               struct drm_file *filp,
8213                               struct drm_mode_fb_cmd2 *mode_cmd)
8214 {
8215         struct drm_i915_gem_object *obj;
8216
8217         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8218                                                 mode_cmd->handles[0]));
8219         if (&obj->base == NULL)
8220                 return ERR_PTR(-ENOENT);
8221
8222         return intel_framebuffer_create(dev, mode_cmd, obj);
8223 }
8224
8225 static const struct drm_mode_config_funcs intel_mode_funcs = {
8226         .fb_create = intel_user_framebuffer_create,
8227         .output_poll_changed = intel_fb_output_poll_changed,
8228 };
8229
8230 /* Set up chip specific display functions */
8231 static void intel_init_display(struct drm_device *dev)
8232 {
8233         struct drm_i915_private *dev_priv = dev->dev_private;
8234
8235         /* We always want a DPMS function */
8236         if (IS_HASWELL(dev)) {
8237                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8238                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8239                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8240                 dev_priv->display.off = haswell_crtc_off;
8241                 dev_priv->display.update_plane = ironlake_update_plane;
8242         } else if (HAS_PCH_SPLIT(dev)) {
8243                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8244                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8245                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8246                 dev_priv->display.off = ironlake_crtc_off;
8247                 dev_priv->display.update_plane = ironlake_update_plane;
8248         } else {
8249                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8250                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8251                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8252                 dev_priv->display.off = i9xx_crtc_off;
8253                 dev_priv->display.update_plane = i9xx_update_plane;
8254         }
8255
8256         /* Returns the core display clock speed */
8257         if (IS_VALLEYVIEW(dev))
8258                 dev_priv->display.get_display_clock_speed =
8259                         valleyview_get_display_clock_speed;
8260         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8261                 dev_priv->display.get_display_clock_speed =
8262                         i945_get_display_clock_speed;
8263         else if (IS_I915G(dev))
8264                 dev_priv->display.get_display_clock_speed =
8265                         i915_get_display_clock_speed;
8266         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8267                 dev_priv->display.get_display_clock_speed =
8268                         i9xx_misc_get_display_clock_speed;
8269         else if (IS_I915GM(dev))
8270                 dev_priv->display.get_display_clock_speed =
8271                         i915gm_get_display_clock_speed;
8272         else if (IS_I865G(dev))
8273                 dev_priv->display.get_display_clock_speed =
8274                         i865_get_display_clock_speed;
8275         else if (IS_I85X(dev))
8276                 dev_priv->display.get_display_clock_speed =
8277                         i855_get_display_clock_speed;
8278         else /* 852, 830 */
8279                 dev_priv->display.get_display_clock_speed =
8280                         i830_get_display_clock_speed;
8281
8282         if (HAS_PCH_SPLIT(dev)) {
8283                 if (IS_GEN5(dev)) {
8284                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8285                         dev_priv->display.write_eld = ironlake_write_eld;
8286                 } else if (IS_GEN6(dev)) {
8287                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8288                         dev_priv->display.write_eld = ironlake_write_eld;
8289                 } else if (IS_IVYBRIDGE(dev)) {
8290                         /* FIXME: detect B0+ stepping and use auto training */
8291                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8292                         dev_priv->display.write_eld = ironlake_write_eld;
8293                 } else if (IS_HASWELL(dev)) {
8294                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8295                         dev_priv->display.write_eld = haswell_write_eld;
8296                 } else
8297                         dev_priv->display.update_wm = NULL;
8298         } else if (IS_G4X(dev)) {
8299                 dev_priv->display.write_eld = g4x_write_eld;
8300         }
8301
8302         /* Default just returns -ENODEV to indicate unsupported */
8303         dev_priv->display.queue_flip = intel_default_queue_flip;
8304
8305         switch (INTEL_INFO(dev)->gen) {
8306         case 2:
8307                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8308                 break;
8309
8310         case 3:
8311                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8312                 break;
8313
8314         case 4:
8315         case 5:
8316                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8317                 break;
8318
8319         case 6:
8320                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8321                 break;
8322         case 7:
8323                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8324                 break;
8325         }
8326 }
8327
8328 /*
8329  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8330  * resume, or other times.  This quirk makes sure that's the case for
8331  * affected systems.
8332  */
8333 static void quirk_pipea_force(struct drm_device *dev)
8334 {
8335         struct drm_i915_private *dev_priv = dev->dev_private;
8336
8337         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8338         DRM_INFO("applying pipe a force quirk\n");
8339 }
8340
8341 /*
8342  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8343  */
8344 static void quirk_ssc_force_disable(struct drm_device *dev)
8345 {
8346         struct drm_i915_private *dev_priv = dev->dev_private;
8347         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8348         DRM_INFO("applying lvds SSC disable quirk\n");
8349 }
8350
8351 /*
8352  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8353  * brightness value
8354  */
8355 static void quirk_invert_brightness(struct drm_device *dev)
8356 {
8357         struct drm_i915_private *dev_priv = dev->dev_private;
8358         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8359         DRM_INFO("applying inverted panel brightness quirk\n");
8360 }
8361
8362 struct intel_quirk {
8363         int device;
8364         int subsystem_vendor;
8365         int subsystem_device;
8366         void (*hook)(struct drm_device *dev);
8367 };
8368
8369 static struct intel_quirk intel_quirks[] = {
8370         /* HP Mini needs pipe A force quirk (LP: #322104) */
8371         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8372
8373         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8374         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8375
8376         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8377         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8378
8379         /* 830/845 need to leave pipe A & dpll A up */
8380         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8381         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8382
8383         /* Lenovo U160 cannot use SSC on LVDS */
8384         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8385
8386         /* Sony Vaio Y cannot use SSC on LVDS */
8387         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8388
8389         /* Acer Aspire 5734Z must invert backlight brightness */
8390         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8391 };
8392
8393 static void intel_init_quirks(struct drm_device *dev)
8394 {
8395         struct pci_dev *d = dev->pdev;
8396         int i;
8397
8398         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8399                 struct intel_quirk *q = &intel_quirks[i];
8400
8401                 if (d->device == q->device &&
8402                     (d->subsystem_vendor == q->subsystem_vendor ||
8403                      q->subsystem_vendor == PCI_ANY_ID) &&
8404                     (d->subsystem_device == q->subsystem_device ||
8405                      q->subsystem_device == PCI_ANY_ID))
8406                         q->hook(dev);
8407         }
8408 }
8409
8410 /* Disable the VGA plane that we never use */
8411 static void i915_disable_vga(struct drm_device *dev)
8412 {
8413         struct drm_i915_private *dev_priv = dev->dev_private;
8414         u8 sr1;
8415         u32 vga_reg;
8416
8417         if (HAS_PCH_SPLIT(dev))
8418                 vga_reg = CPU_VGACNTRL;
8419         else
8420                 vga_reg = VGACNTRL;
8421
8422         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8423         outb(SR01, VGA_SR_INDEX);
8424         sr1 = inb(VGA_SR_DATA);
8425         outb(sr1 | 1<<5, VGA_SR_DATA);
8426         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8427         udelay(300);
8428
8429         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8430         POSTING_READ(vga_reg);
8431 }
8432
8433 void intel_modeset_init_hw(struct drm_device *dev)
8434 {
8435         /* We attempt to init the necessary power wells early in the initialization
8436          * time, so the subsystems that expect power to be enabled can work.
8437          */
8438         intel_init_power_wells(dev);
8439
8440         intel_prepare_ddi(dev);
8441
8442         intel_init_clock_gating(dev);
8443
8444         mutex_lock(&dev->struct_mutex);
8445         intel_enable_gt_powersave(dev);
8446         mutex_unlock(&dev->struct_mutex);
8447 }
8448
8449 void intel_modeset_init(struct drm_device *dev)
8450 {
8451         struct drm_i915_private *dev_priv = dev->dev_private;
8452         int i, ret;
8453
8454         drm_mode_config_init(dev);
8455
8456         dev->mode_config.min_width = 0;
8457         dev->mode_config.min_height = 0;
8458
8459         dev->mode_config.preferred_depth = 24;
8460         dev->mode_config.prefer_shadow = 1;
8461
8462         dev->mode_config.funcs = &intel_mode_funcs;
8463
8464         intel_init_quirks(dev);
8465
8466         intel_init_pm(dev);
8467
8468         intel_init_display(dev);
8469
8470         if (IS_GEN2(dev)) {
8471                 dev->mode_config.max_width = 2048;
8472                 dev->mode_config.max_height = 2048;
8473         } else if (IS_GEN3(dev)) {
8474                 dev->mode_config.max_width = 4096;
8475                 dev->mode_config.max_height = 4096;
8476         } else {
8477                 dev->mode_config.max_width = 8192;
8478                 dev->mode_config.max_height = 8192;
8479         }
8480         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8481
8482         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8483                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8484
8485         for (i = 0; i < dev_priv->num_pipe; i++) {
8486                 intel_crtc_init(dev, i);
8487                 ret = intel_plane_init(dev, i);
8488                 if (ret)
8489                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8490         }
8491
8492         intel_cpu_pll_init(dev);
8493         intel_pch_pll_init(dev);
8494
8495         /* Just disable it once at startup */
8496         i915_disable_vga(dev);
8497         intel_setup_outputs(dev);
8498 }
8499
8500 static void
8501 intel_connector_break_all_links(struct intel_connector *connector)
8502 {
8503         connector->base.dpms = DRM_MODE_DPMS_OFF;
8504         connector->base.encoder = NULL;
8505         connector->encoder->connectors_active = false;
8506         connector->encoder->base.crtc = NULL;
8507 }
8508
8509 static void intel_enable_pipe_a(struct drm_device *dev)
8510 {
8511         struct intel_connector *connector;
8512         struct drm_connector *crt = NULL;
8513         struct intel_load_detect_pipe load_detect_temp;
8514
8515         /* We can't just switch on the pipe A, we need to set things up with a
8516          * proper mode and output configuration. As a gross hack, enable pipe A
8517          * by enabling the load detect pipe once. */
8518         list_for_each_entry(connector,
8519                             &dev->mode_config.connector_list,
8520                             base.head) {
8521                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8522                         crt = &connector->base;
8523                         break;
8524                 }
8525         }
8526
8527         if (!crt)
8528                 return;
8529
8530         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8531                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8532
8533
8534 }
8535
8536 static bool
8537 intel_check_plane_mapping(struct intel_crtc *crtc)
8538 {
8539         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8540         u32 reg, val;
8541
8542         if (dev_priv->num_pipe == 1)
8543                 return true;
8544
8545         reg = DSPCNTR(!crtc->plane);
8546         val = I915_READ(reg);
8547
8548         if ((val & DISPLAY_PLANE_ENABLE) &&
8549             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8550                 return false;
8551
8552         return true;
8553 }
8554
8555 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8556 {
8557         struct drm_device *dev = crtc->base.dev;
8558         struct drm_i915_private *dev_priv = dev->dev_private;
8559         u32 reg;
8560
8561         /* Clear any frame start delays used for debugging left by the BIOS */
8562         reg = PIPECONF(crtc->pipe);
8563         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8564
8565         /* We need to sanitize the plane -> pipe mapping first because this will
8566          * disable the crtc (and hence change the state) if it is wrong. Note
8567          * that gen4+ has a fixed plane -> pipe mapping.  */
8568         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8569                 struct intel_connector *connector;
8570                 bool plane;
8571
8572                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8573                               crtc->base.base.id);
8574
8575                 /* Pipe has the wrong plane attached and the plane is active.
8576                  * Temporarily change the plane mapping and disable everything
8577                  * ...  */
8578                 plane = crtc->plane;
8579                 crtc->plane = !plane;
8580                 dev_priv->display.crtc_disable(&crtc->base);
8581                 crtc->plane = plane;
8582
8583                 /* ... and break all links. */
8584                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8585                                     base.head) {
8586                         if (connector->encoder->base.crtc != &crtc->base)
8587                                 continue;
8588
8589                         intel_connector_break_all_links(connector);
8590                 }
8591
8592                 WARN_ON(crtc->active);
8593                 crtc->base.enabled = false;
8594         }
8595
8596         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8597             crtc->pipe == PIPE_A && !crtc->active) {
8598                 /* BIOS forgot to enable pipe A, this mostly happens after
8599                  * resume. Force-enable the pipe to fix this, the update_dpms
8600                  * call below we restore the pipe to the right state, but leave
8601                  * the required bits on. */
8602                 intel_enable_pipe_a(dev);
8603         }
8604
8605         /* Adjust the state of the output pipe according to whether we
8606          * have active connectors/encoders. */
8607         intel_crtc_update_dpms(&crtc->base);
8608
8609         if (crtc->active != crtc->base.enabled) {
8610                 struct intel_encoder *encoder;
8611
8612                 /* This can happen either due to bugs in the get_hw_state
8613                  * functions or because the pipe is force-enabled due to the
8614                  * pipe A quirk. */
8615                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8616                               crtc->base.base.id,
8617                               crtc->base.enabled ? "enabled" : "disabled",
8618                               crtc->active ? "enabled" : "disabled");
8619
8620                 crtc->base.enabled = crtc->active;
8621
8622                 /* Because we only establish the connector -> encoder ->
8623                  * crtc links if something is active, this means the
8624                  * crtc is now deactivated. Break the links. connector
8625                  * -> encoder links are only establish when things are
8626                  *  actually up, hence no need to break them. */
8627                 WARN_ON(crtc->active);
8628
8629                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8630                         WARN_ON(encoder->connectors_active);
8631                         encoder->base.crtc = NULL;
8632                 }
8633         }
8634 }
8635
8636 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8637 {
8638         struct intel_connector *connector;
8639         struct drm_device *dev = encoder->base.dev;
8640
8641         /* We need to check both for a crtc link (meaning that the
8642          * encoder is active and trying to read from a pipe) and the
8643          * pipe itself being active. */
8644         bool has_active_crtc = encoder->base.crtc &&
8645                 to_intel_crtc(encoder->base.crtc)->active;
8646
8647         if (encoder->connectors_active && !has_active_crtc) {
8648                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8649                               encoder->base.base.id,
8650                               drm_get_encoder_name(&encoder->base));
8651
8652                 /* Connector is active, but has no active pipe. This is
8653                  * fallout from our resume register restoring. Disable
8654                  * the encoder manually again. */
8655                 if (encoder->base.crtc) {
8656                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8657                                       encoder->base.base.id,
8658                                       drm_get_encoder_name(&encoder->base));
8659                         encoder->disable(encoder);
8660                 }
8661
8662                 /* Inconsistent output/port/pipe state happens presumably due to
8663                  * a bug in one of the get_hw_state functions. Or someplace else
8664                  * in our code, like the register restore mess on resume. Clamp
8665                  * things to off as a safer default. */
8666                 list_for_each_entry(connector,
8667                                     &dev->mode_config.connector_list,
8668                                     base.head) {
8669                         if (connector->encoder != encoder)
8670                                 continue;
8671
8672                         intel_connector_break_all_links(connector);
8673                 }
8674         }
8675         /* Enabled encoders without active connectors will be fixed in
8676          * the crtc fixup. */
8677 }
8678
8679 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8680  * and i915 state tracking structures. */
8681 void intel_modeset_setup_hw_state(struct drm_device *dev)
8682 {
8683         struct drm_i915_private *dev_priv = dev->dev_private;
8684         enum pipe pipe;
8685         u32 tmp;
8686         struct intel_crtc *crtc;
8687         struct intel_encoder *encoder;
8688         struct intel_connector *connector;
8689
8690         for_each_pipe(pipe) {
8691                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8692
8693                 tmp = I915_READ(PIPECONF(pipe));
8694                 if (tmp & PIPECONF_ENABLE)
8695                         crtc->active = true;
8696                 else
8697                         crtc->active = false;
8698
8699                 crtc->base.enabled = crtc->active;
8700
8701                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8702                               crtc->base.base.id,
8703                               crtc->active ? "enabled" : "disabled");
8704         }
8705
8706         if (IS_HASWELL(dev))
8707                 intel_ddi_setup_hw_pll_state(dev);
8708
8709         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8710                             base.head) {
8711                 pipe = 0;
8712
8713                 if (encoder->get_hw_state(encoder, &pipe)) {
8714                         encoder->base.crtc =
8715                                 dev_priv->pipe_to_crtc_mapping[pipe];
8716                 } else {
8717                         encoder->base.crtc = NULL;
8718                 }
8719
8720                 encoder->connectors_active = false;
8721                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8722                               encoder->base.base.id,
8723                               drm_get_encoder_name(&encoder->base),
8724                               encoder->base.crtc ? "enabled" : "disabled",
8725                               pipe);
8726         }
8727
8728         list_for_each_entry(connector, &dev->mode_config.connector_list,
8729                             base.head) {
8730                 if (connector->get_hw_state(connector)) {
8731                         connector->base.dpms = DRM_MODE_DPMS_ON;
8732                         connector->encoder->connectors_active = true;
8733                         connector->base.encoder = &connector->encoder->base;
8734                 } else {
8735                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8736                         connector->base.encoder = NULL;
8737                 }
8738                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8739                               connector->base.base.id,
8740                               drm_get_connector_name(&connector->base),
8741                               connector->base.encoder ? "enabled" : "disabled");
8742         }
8743
8744         /* HW state is read out, now we need to sanitize this mess. */
8745         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8746                             base.head) {
8747                 intel_sanitize_encoder(encoder);
8748         }
8749
8750         for_each_pipe(pipe) {
8751                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8752                 intel_sanitize_crtc(crtc);
8753         }
8754
8755         intel_modeset_update_staged_output_state(dev);
8756
8757         intel_modeset_check_state(dev);
8758
8759         drm_mode_config_reset(dev);
8760 }
8761
8762 void intel_modeset_gem_init(struct drm_device *dev)
8763 {
8764         intel_modeset_init_hw(dev);
8765
8766         intel_setup_overlay(dev);
8767
8768         intel_modeset_setup_hw_state(dev);
8769 }
8770
8771 void intel_modeset_cleanup(struct drm_device *dev)
8772 {
8773         struct drm_i915_private *dev_priv = dev->dev_private;
8774         struct drm_crtc *crtc;
8775         struct intel_crtc *intel_crtc;
8776
8777         drm_kms_helper_poll_fini(dev);
8778         mutex_lock(&dev->struct_mutex);
8779
8780         intel_unregister_dsm_handler();
8781
8782
8783         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8784                 /* Skip inactive CRTCs */
8785                 if (!crtc->fb)
8786                         continue;
8787
8788                 intel_crtc = to_intel_crtc(crtc);
8789                 intel_increase_pllclock(crtc);
8790         }
8791
8792         intel_disable_fbc(dev);
8793
8794         intel_disable_gt_powersave(dev);
8795
8796         ironlake_teardown_rc6(dev);
8797
8798         if (IS_VALLEYVIEW(dev))
8799                 vlv_init_dpio(dev);
8800
8801         mutex_unlock(&dev->struct_mutex);
8802
8803         /* Disable the irq before mode object teardown, for the irq might
8804          * enqueue unpin/hotplug work. */
8805         drm_irq_uninstall(dev);
8806         cancel_work_sync(&dev_priv->hotplug_work);
8807         cancel_work_sync(&dev_priv->rps.work);
8808
8809         /* flush any delayed tasks or pending work */
8810         flush_scheduled_work();
8811
8812         drm_mode_config_cleanup(dev);
8813 }
8814
8815 /*
8816  * Return which encoder is currently attached for connector.
8817  */
8818 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8819 {
8820         return &intel_attached_encoder(connector)->base;
8821 }
8822
8823 void intel_connector_attach_encoder(struct intel_connector *connector,
8824                                     struct intel_encoder *encoder)
8825 {
8826         connector->encoder = encoder;
8827         drm_mode_connector_attach_encoder(&connector->base,
8828                                           &encoder->base);
8829 }
8830
8831 /*
8832  * set vga decode state - true == enable VGA decode
8833  */
8834 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8835 {
8836         struct drm_i915_private *dev_priv = dev->dev_private;
8837         u16 gmch_ctrl;
8838
8839         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8840         if (state)
8841                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8842         else
8843                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8844         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8845         return 0;
8846 }
8847
8848 #ifdef CONFIG_DEBUG_FS
8849 #include <linux/seq_file.h>
8850
8851 struct intel_display_error_state {
8852         struct intel_cursor_error_state {
8853                 u32 control;
8854                 u32 position;
8855                 u32 base;
8856                 u32 size;
8857         } cursor[I915_MAX_PIPES];
8858
8859         struct intel_pipe_error_state {
8860                 u32 conf;
8861                 u32 source;
8862
8863                 u32 htotal;
8864                 u32 hblank;
8865                 u32 hsync;
8866                 u32 vtotal;
8867                 u32 vblank;
8868                 u32 vsync;
8869         } pipe[I915_MAX_PIPES];
8870
8871         struct intel_plane_error_state {
8872                 u32 control;
8873                 u32 stride;
8874                 u32 size;
8875                 u32 pos;
8876                 u32 addr;
8877                 u32 surface;
8878                 u32 tile_offset;
8879         } plane[I915_MAX_PIPES];
8880 };
8881
8882 struct intel_display_error_state *
8883 intel_display_capture_error_state(struct drm_device *dev)
8884 {
8885         drm_i915_private_t *dev_priv = dev->dev_private;
8886         struct intel_display_error_state *error;
8887         int i;
8888
8889         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8890         if (error == NULL)
8891                 return NULL;
8892
8893         for_each_pipe(i) {
8894                 error->cursor[i].control = I915_READ(CURCNTR(i));
8895                 error->cursor[i].position = I915_READ(CURPOS(i));
8896                 error->cursor[i].base = I915_READ(CURBASE(i));
8897
8898                 error->plane[i].control = I915_READ(DSPCNTR(i));
8899                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8900                 error->plane[i].size = I915_READ(DSPSIZE(i));
8901                 error->plane[i].pos = I915_READ(DSPPOS(i));
8902                 error->plane[i].addr = I915_READ(DSPADDR(i));
8903                 if (INTEL_INFO(dev)->gen >= 4) {
8904                         error->plane[i].surface = I915_READ(DSPSURF(i));
8905                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8906                 }
8907
8908                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8909                 error->pipe[i].source = I915_READ(PIPESRC(i));
8910                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8911                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8912                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8913                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8914                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8915                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8916         }
8917
8918         return error;
8919 }
8920
8921 void
8922 intel_display_print_error_state(struct seq_file *m,
8923                                 struct drm_device *dev,
8924                                 struct intel_display_error_state *error)
8925 {
8926         drm_i915_private_t *dev_priv = dev->dev_private;
8927         int i;
8928
8929         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8930         for_each_pipe(i) {
8931                 seq_printf(m, "Pipe [%d]:\n", i);
8932                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8933                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8934                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8935                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8936                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8937                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8938                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8939                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8940
8941                 seq_printf(m, "Plane [%d]:\n", i);
8942                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8943                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8944                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8945                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8946                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8947                 if (INTEL_INFO(dev)->gen >= 4) {
8948                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8949                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8950                 }
8951
8952                 seq_printf(m, "Cursor [%d]:\n", i);
8953                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8954                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8955                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8956         }
8957 }
8958 #endif