Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum transcoder cpu_transcoder)
1722 {
1723         u32 val, pipeconf_val;
1724
1725         /* PCH only available on ILK+ */
1726         BUG_ON(dev_priv->info->gen < 5);
1727
1728         /* FDI must be feeding us bits for PCH ports */
1729         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1731
1732         val = TRANS_ENABLE;
1733         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1734
1735         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1736             PIPECONF_INTERLACED_ILK)
1737                 val |= TRANS_INTERLACED;
1738         else
1739                 val |= TRANS_PROGRESSIVE;
1740
1741         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1742         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1743                 DRM_ERROR("Failed to enable PCH transcoder\n");
1744 }
1745
1746 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1747                                             enum pipe pipe)
1748 {
1749         int reg;
1750         u32 val;
1751
1752         /* FDI relies on the transcoder */
1753         assert_fdi_tx_disabled(dev_priv, pipe);
1754         assert_fdi_rx_disabled(dev_priv, pipe);
1755
1756         /* Ports must be off as well */
1757         assert_pch_ports_disabled(dev_priv, pipe);
1758
1759         reg = TRANSCONF(pipe);
1760         val = I915_READ(reg);
1761         val &= ~TRANS_ENABLE;
1762         I915_WRITE(reg, val);
1763         /* wait for PCH transcoder off, transcoder state */
1764         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1765                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1766 }
1767
1768 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769                                        enum pipe pipe)
1770 {
1771         int reg;
1772         u32 val;
1773
1774         /* FDI relies on the transcoder */
1775         assert_fdi_tx_disabled(dev_priv, pipe);
1776         assert_fdi_rx_disabled(dev_priv, pipe);
1777
1778         reg = TRANSCONF(pipe);
1779         val = I915_READ(reg);
1780         val &= ~TRANS_ENABLE;
1781         I915_WRITE(reg, val);
1782         /* wait for PCH transcoder off, transcoder state */
1783         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1784                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1785 }
1786
1787 /**
1788  * intel_enable_pipe - enable a pipe, asserting requirements
1789  * @dev_priv: i915 private structure
1790  * @pipe: pipe to enable
1791  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1792  *
1793  * Enable @pipe, making sure that various hardware specific requirements
1794  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1795  *
1796  * @pipe should be %PIPE_A or %PIPE_B.
1797  *
1798  * Will wait until the pipe is actually running (i.e. first vblank) before
1799  * returning.
1800  */
1801 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1802                               bool pch_port)
1803 {
1804         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1805                                                                       pipe);
1806         int reg;
1807         u32 val;
1808
1809         /*
1810          * A pipe without a PLL won't actually be able to drive bits from
1811          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1812          * need the check.
1813          */
1814         if (!HAS_PCH_SPLIT(dev_priv->dev))
1815                 assert_pll_enabled(dev_priv, pipe);
1816         else {
1817                 if (pch_port) {
1818                         /* if driving the PCH, we need FDI enabled */
1819                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1820                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1821                 }
1822                 /* FIXME: assert CPU port conditions for SNB+ */
1823         }
1824
1825         reg = PIPECONF(cpu_transcoder);
1826         val = I915_READ(reg);
1827         if (val & PIPECONF_ENABLE)
1828                 return;
1829
1830         I915_WRITE(reg, val | PIPECONF_ENABLE);
1831         intel_wait_for_vblank(dev_priv->dev, pipe);
1832 }
1833
1834 /**
1835  * intel_disable_pipe - disable a pipe, asserting requirements
1836  * @dev_priv: i915 private structure
1837  * @pipe: pipe to disable
1838  *
1839  * Disable @pipe, making sure that various hardware specific requirements
1840  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1841  *
1842  * @pipe should be %PIPE_A or %PIPE_B.
1843  *
1844  * Will wait until the pipe has shut down before returning.
1845  */
1846 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1847                                enum pipe pipe)
1848 {
1849         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1850                                                                       pipe);
1851         int reg;
1852         u32 val;
1853
1854         /*
1855          * Make sure planes won't keep trying to pump pixels to us,
1856          * or we might hang the display.
1857          */
1858         assert_planes_disabled(dev_priv, pipe);
1859
1860         /* Don't disable pipe A or pipe A PLLs if needed */
1861         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1862                 return;
1863
1864         reg = PIPECONF(cpu_transcoder);
1865         val = I915_READ(reg);
1866         if ((val & PIPECONF_ENABLE) == 0)
1867                 return;
1868
1869         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1870         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1871 }
1872
1873 /*
1874  * Plane regs are double buffered, going from enabled->disabled needs a
1875  * trigger in order to latch.  The display address reg provides this.
1876  */
1877 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1878                                       enum plane plane)
1879 {
1880         if (dev_priv->info->gen >= 4)
1881                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1882         else
1883                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1884 }
1885
1886 /**
1887  * intel_enable_plane - enable a display plane on a given pipe
1888  * @dev_priv: i915 private structure
1889  * @plane: plane to enable
1890  * @pipe: pipe being fed
1891  *
1892  * Enable @plane on @pipe, making sure that @pipe is running first.
1893  */
1894 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1895                                enum plane plane, enum pipe pipe)
1896 {
1897         int reg;
1898         u32 val;
1899
1900         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1901         assert_pipe_enabled(dev_priv, pipe);
1902
1903         reg = DSPCNTR(plane);
1904         val = I915_READ(reg);
1905         if (val & DISPLAY_PLANE_ENABLE)
1906                 return;
1907
1908         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1909         intel_flush_display_plane(dev_priv, plane);
1910         intel_wait_for_vblank(dev_priv->dev, pipe);
1911 }
1912
1913 /**
1914  * intel_disable_plane - disable a display plane
1915  * @dev_priv: i915 private structure
1916  * @plane: plane to disable
1917  * @pipe: pipe consuming the data
1918  *
1919  * Disable @plane; should be an independent operation.
1920  */
1921 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1922                                 enum plane plane, enum pipe pipe)
1923 {
1924         int reg;
1925         u32 val;
1926
1927         reg = DSPCNTR(plane);
1928         val = I915_READ(reg);
1929         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1930                 return;
1931
1932         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1933         intel_flush_display_plane(dev_priv, plane);
1934         intel_wait_for_vblank(dev_priv->dev, pipe);
1935 }
1936
1937 int
1938 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1939                            struct drm_i915_gem_object *obj,
1940                            struct intel_ring_buffer *pipelined)
1941 {
1942         struct drm_i915_private *dev_priv = dev->dev_private;
1943         u32 alignment;
1944         int ret;
1945
1946         switch (obj->tiling_mode) {
1947         case I915_TILING_NONE:
1948                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1949                         alignment = 128 * 1024;
1950                 else if (INTEL_INFO(dev)->gen >= 4)
1951                         alignment = 4 * 1024;
1952                 else
1953                         alignment = 64 * 1024;
1954                 break;
1955         case I915_TILING_X:
1956                 /* pin() will align the object as required by fence */
1957                 alignment = 0;
1958                 break;
1959         case I915_TILING_Y:
1960                 /* FIXME: Is this true? */
1961                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1962                 return -EINVAL;
1963         default:
1964                 BUG();
1965         }
1966
1967         dev_priv->mm.interruptible = false;
1968         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1969         if (ret)
1970                 goto err_interruptible;
1971
1972         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1973          * fence, whereas 965+ only requires a fence if using
1974          * framebuffer compression.  For simplicity, we always install
1975          * a fence as the cost is not that onerous.
1976          */
1977         ret = i915_gem_object_get_fence(obj);
1978         if (ret)
1979                 goto err_unpin;
1980
1981         i915_gem_object_pin_fence(obj);
1982
1983         dev_priv->mm.interruptible = true;
1984         return 0;
1985
1986 err_unpin:
1987         i915_gem_object_unpin(obj);
1988 err_interruptible:
1989         dev_priv->mm.interruptible = true;
1990         return ret;
1991 }
1992
1993 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1994 {
1995         i915_gem_object_unpin_fence(obj);
1996         i915_gem_object_unpin(obj);
1997 }
1998
1999 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2000  * is assumed to be a power-of-two. */
2001 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2002                                                unsigned int bpp,
2003                                                unsigned int pitch)
2004 {
2005         int tile_rows, tiles;
2006
2007         tile_rows = *y / 8;
2008         *y %= 8;
2009         tiles = *x / (512/bpp);
2010         *x %= 512/bpp;
2011
2012         return tile_rows * pitch * 8 + tiles * 4096;
2013 }
2014
2015 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2016                              int x, int y)
2017 {
2018         struct drm_device *dev = crtc->dev;
2019         struct drm_i915_private *dev_priv = dev->dev_private;
2020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021         struct intel_framebuffer *intel_fb;
2022         struct drm_i915_gem_object *obj;
2023         int plane = intel_crtc->plane;
2024         unsigned long linear_offset;
2025         u32 dspcntr;
2026         u32 reg;
2027
2028         switch (plane) {
2029         case 0:
2030         case 1:
2031                 break;
2032         default:
2033                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2034                 return -EINVAL;
2035         }
2036
2037         intel_fb = to_intel_framebuffer(fb);
2038         obj = intel_fb->obj;
2039
2040         reg = DSPCNTR(plane);
2041         dspcntr = I915_READ(reg);
2042         /* Mask out pixel format bits in case we change it */
2043         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2044         switch (fb->pixel_format) {
2045         case DRM_FORMAT_C8:
2046                 dspcntr |= DISPPLANE_8BPP;
2047                 break;
2048         case DRM_FORMAT_XRGB1555:
2049         case DRM_FORMAT_ARGB1555:
2050                 dspcntr |= DISPPLANE_BGRX555;
2051                 break;
2052         case DRM_FORMAT_RGB565:
2053                 dspcntr |= DISPPLANE_BGRX565;
2054                 break;
2055         case DRM_FORMAT_XRGB8888:
2056         case DRM_FORMAT_ARGB8888:
2057                 dspcntr |= DISPPLANE_BGRX888;
2058                 break;
2059         case DRM_FORMAT_XBGR8888:
2060         case DRM_FORMAT_ABGR8888:
2061                 dspcntr |= DISPPLANE_RGBX888;
2062                 break;
2063         case DRM_FORMAT_XRGB2101010:
2064         case DRM_FORMAT_ARGB2101010:
2065                 dspcntr |= DISPPLANE_BGRX101010;
2066                 break;
2067         case DRM_FORMAT_XBGR2101010:
2068         case DRM_FORMAT_ABGR2101010:
2069                 dspcntr |= DISPPLANE_RGBX101010;
2070                 break;
2071         default:
2072                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2073                 return -EINVAL;
2074         }
2075
2076         if (INTEL_INFO(dev)->gen >= 4) {
2077                 if (obj->tiling_mode != I915_TILING_NONE)
2078                         dspcntr |= DISPPLANE_TILED;
2079                 else
2080                         dspcntr &= ~DISPPLANE_TILED;
2081         }
2082
2083         I915_WRITE(reg, dspcntr);
2084
2085         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2086
2087         if (INTEL_INFO(dev)->gen >= 4) {
2088                 intel_crtc->dspaddr_offset =
2089                         intel_gen4_compute_offset_xtiled(&x, &y,
2090                                                          fb->bits_per_pixel / 8,
2091                                                          fb->pitches[0]);
2092                 linear_offset -= intel_crtc->dspaddr_offset;
2093         } else {
2094                 intel_crtc->dspaddr_offset = linear_offset;
2095         }
2096
2097         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100         if (INTEL_INFO(dev)->gen >= 4) {
2101                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2102                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2103                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2104                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2105         } else
2106                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2107         POSTING_READ(reg);
2108
2109         return 0;
2110 }
2111
2112 static int ironlake_update_plane(struct drm_crtc *crtc,
2113                                  struct drm_framebuffer *fb, int x, int y)
2114 {
2115         struct drm_device *dev = crtc->dev;
2116         struct drm_i915_private *dev_priv = dev->dev_private;
2117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2118         struct intel_framebuffer *intel_fb;
2119         struct drm_i915_gem_object *obj;
2120         int plane = intel_crtc->plane;
2121         unsigned long linear_offset;
2122         u32 dspcntr;
2123         u32 reg;
2124
2125         switch (plane) {
2126         case 0:
2127         case 1:
2128         case 2:
2129                 break;
2130         default:
2131                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2132                 return -EINVAL;
2133         }
2134
2135         intel_fb = to_intel_framebuffer(fb);
2136         obj = intel_fb->obj;
2137
2138         reg = DSPCNTR(plane);
2139         dspcntr = I915_READ(reg);
2140         /* Mask out pixel format bits in case we change it */
2141         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2142         switch (fb->pixel_format) {
2143         case DRM_FORMAT_C8:
2144                 dspcntr |= DISPPLANE_8BPP;
2145                 break;
2146         case DRM_FORMAT_RGB565:
2147                 dspcntr |= DISPPLANE_BGRX565;
2148                 break;
2149         case DRM_FORMAT_XRGB8888:
2150         case DRM_FORMAT_ARGB8888:
2151                 dspcntr |= DISPPLANE_BGRX888;
2152                 break;
2153         case DRM_FORMAT_XBGR8888:
2154         case DRM_FORMAT_ABGR8888:
2155                 dspcntr |= DISPPLANE_RGBX888;
2156                 break;
2157         case DRM_FORMAT_XRGB2101010:
2158         case DRM_FORMAT_ARGB2101010:
2159                 dspcntr |= DISPPLANE_BGRX101010;
2160                 break;
2161         case DRM_FORMAT_XBGR2101010:
2162         case DRM_FORMAT_ABGR2101010:
2163                 dspcntr |= DISPPLANE_RGBX101010;
2164                 break;
2165         default:
2166                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2167                 return -EINVAL;
2168         }
2169
2170         if (obj->tiling_mode != I915_TILING_NONE)
2171                 dspcntr |= DISPPLANE_TILED;
2172         else
2173                 dspcntr &= ~DISPPLANE_TILED;
2174
2175         /* must disable */
2176         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2177
2178         I915_WRITE(reg, dspcntr);
2179
2180         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2181         intel_crtc->dspaddr_offset =
2182                 intel_gen4_compute_offset_xtiled(&x, &y,
2183                                                  fb->bits_per_pixel / 8,
2184                                                  fb->pitches[0]);
2185         linear_offset -= intel_crtc->dspaddr_offset;
2186
2187         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2188                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2189         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2190         I915_MODIFY_DISPBASE(DSPSURF(plane),
2191                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2192         if (IS_HASWELL(dev)) {
2193                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2194         } else {
2195                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2196                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2197         }
2198         POSTING_READ(reg);
2199
2200         return 0;
2201 }
2202
2203 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2204 static int
2205 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2206                            int x, int y, enum mode_set_atomic state)
2207 {
2208         struct drm_device *dev = crtc->dev;
2209         struct drm_i915_private *dev_priv = dev->dev_private;
2210
2211         if (dev_priv->display.disable_fbc)
2212                 dev_priv->display.disable_fbc(dev);
2213         intel_increase_pllclock(crtc);
2214
2215         return dev_priv->display.update_plane(crtc, fb, x, y);
2216 }
2217
2218 static int
2219 intel_finish_fb(struct drm_framebuffer *old_fb)
2220 {
2221         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2222         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2223         bool was_interruptible = dev_priv->mm.interruptible;
2224         int ret;
2225
2226         wait_event(dev_priv->pending_flip_queue,
2227                    atomic_read(&dev_priv->mm.wedged) ||
2228                    atomic_read(&obj->pending_flip) == 0);
2229
2230         /* Big Hammer, we also need to ensure that any pending
2231          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232          * current scanout is retired before unpinning the old
2233          * framebuffer.
2234          *
2235          * This should only fail upon a hung GPU, in which case we
2236          * can safely continue.
2237          */
2238         dev_priv->mm.interruptible = false;
2239         ret = i915_gem_object_finish_gpu(obj);
2240         dev_priv->mm.interruptible = was_interruptible;
2241
2242         return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247         struct drm_device *dev = crtc->dev;
2248         struct drm_i915_master_private *master_priv;
2249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251         if (!dev->primary->master)
2252                 return;
2253
2254         master_priv = dev->primary->master->driver_priv;
2255         if (!master_priv->sarea_priv)
2256                 return;
2257
2258         switch (intel_crtc->pipe) {
2259         case 0:
2260                 master_priv->sarea_priv->pipeA_x = x;
2261                 master_priv->sarea_priv->pipeA_y = y;
2262                 break;
2263         case 1:
2264                 master_priv->sarea_priv->pipeB_x = x;
2265                 master_priv->sarea_priv->pipeB_y = y;
2266                 break;
2267         default:
2268                 break;
2269         }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274                     struct drm_framebuffer *fb)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         struct drm_framebuffer *old_fb;
2280         int ret;
2281
2282         /* no fb bound */
2283         if (!fb) {
2284                 DRM_ERROR("No FB bound\n");
2285                 return 0;
2286         }
2287
2288         if(intel_crtc->plane > dev_priv->num_pipe) {
2289                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2290                                 intel_crtc->plane,
2291                                 dev_priv->num_pipe);
2292                 return -EINVAL;
2293         }
2294
2295         mutex_lock(&dev->struct_mutex);
2296         ret = intel_pin_and_fence_fb_obj(dev,
2297                                          to_intel_framebuffer(fb)->obj,
2298                                          NULL);
2299         if (ret != 0) {
2300                 mutex_unlock(&dev->struct_mutex);
2301                 DRM_ERROR("pin & fence failed\n");
2302                 return ret;
2303         }
2304
2305         if (crtc->fb)
2306                 intel_finish_fb(crtc->fb);
2307
2308         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2309         if (ret) {
2310                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2311                 mutex_unlock(&dev->struct_mutex);
2312                 DRM_ERROR("failed to update base address\n");
2313                 return ret;
2314         }
2315
2316         old_fb = crtc->fb;
2317         crtc->fb = fb;
2318         crtc->x = x;
2319         crtc->y = y;
2320
2321         if (old_fb) {
2322                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2323                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2324         }
2325
2326         intel_update_fbc(dev);
2327         mutex_unlock(&dev->struct_mutex);
2328
2329         intel_crtc_update_sarea_pos(crtc, x, y);
2330
2331         return 0;
2332 }
2333
2334 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2335 {
2336         struct drm_device *dev = crtc->dev;
2337         struct drm_i915_private *dev_priv = dev->dev_private;
2338         u32 dpa_ctl;
2339
2340         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2341         dpa_ctl = I915_READ(DP_A);
2342         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2343
2344         if (clock < 200000) {
2345                 u32 temp;
2346                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2347                 /* workaround for 160Mhz:
2348                    1) program 0x4600c bits 15:0 = 0x8124
2349                    2) program 0x46010 bit 0 = 1
2350                    3) program 0x46034 bit 24 = 1
2351                    4) program 0x64000 bit 14 = 1
2352                    */
2353                 temp = I915_READ(0x4600c);
2354                 temp &= 0xffff0000;
2355                 I915_WRITE(0x4600c, temp | 0x8124);
2356
2357                 temp = I915_READ(0x46010);
2358                 I915_WRITE(0x46010, temp | 1);
2359
2360                 temp = I915_READ(0x46034);
2361                 I915_WRITE(0x46034, temp | (1 << 24));
2362         } else {
2363                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2364         }
2365         I915_WRITE(DP_A, dpa_ctl);
2366
2367         POSTING_READ(DP_A);
2368         udelay(500);
2369 }
2370
2371 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2372 {
2373         struct drm_device *dev = crtc->dev;
2374         struct drm_i915_private *dev_priv = dev->dev_private;
2375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2376         int pipe = intel_crtc->pipe;
2377         u32 reg, temp;
2378
2379         /* enable normal train */
2380         reg = FDI_TX_CTL(pipe);
2381         temp = I915_READ(reg);
2382         if (IS_IVYBRIDGE(dev)) {
2383                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2384                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2385         } else {
2386                 temp &= ~FDI_LINK_TRAIN_NONE;
2387                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2388         }
2389         I915_WRITE(reg, temp);
2390
2391         reg = FDI_RX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         if (HAS_PCH_CPT(dev)) {
2394                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2395                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2396         } else {
2397                 temp &= ~FDI_LINK_TRAIN_NONE;
2398                 temp |= FDI_LINK_TRAIN_NONE;
2399         }
2400         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2401
2402         /* wait one idle pattern time */
2403         POSTING_READ(reg);
2404         udelay(1000);
2405
2406         /* IVB wants error correction enabled */
2407         if (IS_IVYBRIDGE(dev))
2408                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2409                            FDI_FE_ERRC_ENABLE);
2410 }
2411
2412 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2413 {
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         u32 flags = I915_READ(SOUTH_CHICKEN1);
2416
2417         flags |= FDI_PHASE_SYNC_OVR(pipe);
2418         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2419         flags |= FDI_PHASE_SYNC_EN(pipe);
2420         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2421         POSTING_READ(SOUTH_CHICKEN1);
2422 }
2423
2424 static void ivb_modeset_global_resources(struct drm_device *dev)
2425 {
2426         struct drm_i915_private *dev_priv = dev->dev_private;
2427         struct intel_crtc *pipe_B_crtc =
2428                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2429         struct intel_crtc *pipe_C_crtc =
2430                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2431         uint32_t temp;
2432
2433         /* When everything is off disable fdi C so that we could enable fdi B
2434          * with all lanes. XXX: This misses the case where a pipe is not using
2435          * any pch resources and so doesn't need any fdi lanes. */
2436         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2437                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2438                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2439
2440                 temp = I915_READ(SOUTH_CHICKEN1);
2441                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2442                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2443                 I915_WRITE(SOUTH_CHICKEN1, temp);
2444         }
2445 }
2446
2447 /* The FDI link training functions for ILK/Ibexpeak. */
2448 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2449 {
2450         struct drm_device *dev = crtc->dev;
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2453         int pipe = intel_crtc->pipe;
2454         int plane = intel_crtc->plane;
2455         u32 reg, temp, tries;
2456
2457         /* FDI needs bits from pipe & plane first */
2458         assert_pipe_enabled(dev_priv, pipe);
2459         assert_plane_enabled(dev_priv, plane);
2460
2461         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2462            for train result */
2463         reg = FDI_RX_IMR(pipe);
2464         temp = I915_READ(reg);
2465         temp &= ~FDI_RX_SYMBOL_LOCK;
2466         temp &= ~FDI_RX_BIT_LOCK;
2467         I915_WRITE(reg, temp);
2468         I915_READ(reg);
2469         udelay(150);
2470
2471         /* enable CPU FDI TX and PCH FDI RX */
2472         reg = FDI_TX_CTL(pipe);
2473         temp = I915_READ(reg);
2474         temp &= ~(7 << 19);
2475         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2476         temp &= ~FDI_LINK_TRAIN_NONE;
2477         temp |= FDI_LINK_TRAIN_PATTERN_1;
2478         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2479
2480         reg = FDI_RX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_LINK_TRAIN_NONE;
2483         temp |= FDI_LINK_TRAIN_PATTERN_1;
2484         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2485
2486         POSTING_READ(reg);
2487         udelay(150);
2488
2489         /* Ironlake workaround, enable clock pointer after FDI enable*/
2490         if (HAS_PCH_IBX(dev)) {
2491                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2492                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2493                            FDI_RX_PHASE_SYNC_POINTER_EN);
2494         }
2495
2496         reg = FDI_RX_IIR(pipe);
2497         for (tries = 0; tries < 5; tries++) {
2498                 temp = I915_READ(reg);
2499                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2500
2501                 if ((temp & FDI_RX_BIT_LOCK)) {
2502                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2503                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2504                         break;
2505                 }
2506         }
2507         if (tries == 5)
2508                 DRM_ERROR("FDI train 1 fail!\n");
2509
2510         /* Train 2 */
2511         reg = FDI_TX_CTL(pipe);
2512         temp = I915_READ(reg);
2513         temp &= ~FDI_LINK_TRAIN_NONE;
2514         temp |= FDI_LINK_TRAIN_PATTERN_2;
2515         I915_WRITE(reg, temp);
2516
2517         reg = FDI_RX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_2;
2521         I915_WRITE(reg, temp);
2522
2523         POSTING_READ(reg);
2524         udelay(150);
2525
2526         reg = FDI_RX_IIR(pipe);
2527         for (tries = 0; tries < 5; tries++) {
2528                 temp = I915_READ(reg);
2529                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530
2531                 if (temp & FDI_RX_SYMBOL_LOCK) {
2532                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2533                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2534                         break;
2535                 }
2536         }
2537         if (tries == 5)
2538                 DRM_ERROR("FDI train 2 fail!\n");
2539
2540         DRM_DEBUG_KMS("FDI train done\n");
2541
2542 }
2543
2544 static const int snb_b_fdi_train_param[] = {
2545         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2546         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2547         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2548         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2549 };
2550
2551 /* The FDI link training functions for SNB/Cougarpoint. */
2552 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2553 {
2554         struct drm_device *dev = crtc->dev;
2555         struct drm_i915_private *dev_priv = dev->dev_private;
2556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2557         int pipe = intel_crtc->pipe;
2558         u32 reg, temp, i, retry;
2559
2560         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2561            for train result */
2562         reg = FDI_RX_IMR(pipe);
2563         temp = I915_READ(reg);
2564         temp &= ~FDI_RX_SYMBOL_LOCK;
2565         temp &= ~FDI_RX_BIT_LOCK;
2566         I915_WRITE(reg, temp);
2567
2568         POSTING_READ(reg);
2569         udelay(150);
2570
2571         /* enable CPU FDI TX and PCH FDI RX */
2572         reg = FDI_TX_CTL(pipe);
2573         temp = I915_READ(reg);
2574         temp &= ~(7 << 19);
2575         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2576         temp &= ~FDI_LINK_TRAIN_NONE;
2577         temp |= FDI_LINK_TRAIN_PATTERN_1;
2578         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579         /* SNB-B */
2580         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2581         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2582
2583         I915_WRITE(FDI_RX_MISC(pipe),
2584                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2585
2586         reg = FDI_RX_CTL(pipe);
2587         temp = I915_READ(reg);
2588         if (HAS_PCH_CPT(dev)) {
2589                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2590                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2591         } else {
2592                 temp &= ~FDI_LINK_TRAIN_NONE;
2593                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594         }
2595         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2596
2597         POSTING_READ(reg);
2598         udelay(150);
2599
2600         if (HAS_PCH_CPT(dev))
2601                 cpt_phase_pointer_enable(dev, pipe);
2602
2603         for (i = 0; i < 4; i++) {
2604                 reg = FDI_TX_CTL(pipe);
2605                 temp = I915_READ(reg);
2606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607                 temp |= snb_b_fdi_train_param[i];
2608                 I915_WRITE(reg, temp);
2609
2610                 POSTING_READ(reg);
2611                 udelay(500);
2612
2613                 for (retry = 0; retry < 5; retry++) {
2614                         reg = FDI_RX_IIR(pipe);
2615                         temp = I915_READ(reg);
2616                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617                         if (temp & FDI_RX_BIT_LOCK) {
2618                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620                                 break;
2621                         }
2622                         udelay(50);
2623                 }
2624                 if (retry < 5)
2625                         break;
2626         }
2627         if (i == 4)
2628                 DRM_ERROR("FDI train 1 fail!\n");
2629
2630         /* Train 2 */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_NONE;
2634         temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         if (IS_GEN6(dev)) {
2636                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637                 /* SNB-B */
2638                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         }
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         if (HAS_PCH_CPT(dev)) {
2645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647         } else {
2648                 temp &= ~FDI_LINK_TRAIN_NONE;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650         }
2651         I915_WRITE(reg, temp);
2652
2653         POSTING_READ(reg);
2654         udelay(150);
2655
2656         for (i = 0; i < 4; i++) {
2657                 reg = FDI_TX_CTL(pipe);
2658                 temp = I915_READ(reg);
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 temp |= snb_b_fdi_train_param[i];
2661                 I915_WRITE(reg, temp);
2662
2663                 POSTING_READ(reg);
2664                 udelay(500);
2665
2666                 for (retry = 0; retry < 5; retry++) {
2667                         reg = FDI_RX_IIR(pipe);
2668                         temp = I915_READ(reg);
2669                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670                         if (temp & FDI_RX_SYMBOL_LOCK) {
2671                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673                                 break;
2674                         }
2675                         udelay(50);
2676                 }
2677                 if (retry < 5)
2678                         break;
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 2 fail!\n");
2682
2683         DRM_DEBUG_KMS("FDI train done.\n");
2684 }
2685
2686 /* Manual link training for Ivy Bridge A0 parts */
2687 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688 {
2689         struct drm_device *dev = crtc->dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp, i;
2694
2695         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696            for train result */
2697         reg = FDI_RX_IMR(pipe);
2698         temp = I915_READ(reg);
2699         temp &= ~FDI_RX_SYMBOL_LOCK;
2700         temp &= ~FDI_RX_BIT_LOCK;
2701         I915_WRITE(reg, temp);
2702
2703         POSTING_READ(reg);
2704         udelay(150);
2705
2706         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707                       I915_READ(FDI_RX_IIR(pipe)));
2708
2709         /* enable CPU FDI TX and PCH FDI RX */
2710         reg = FDI_TX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         temp &= ~(7 << 19);
2713         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2714         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2716         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2718         temp |= FDI_COMPOSITE_SYNC;
2719         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2720
2721         I915_WRITE(FDI_RX_MISC(pipe),
2722                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~FDI_LINK_TRAIN_AUTO;
2727         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2729         temp |= FDI_COMPOSITE_SYNC;
2730         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2731
2732         POSTING_READ(reg);
2733         udelay(150);
2734
2735         if (HAS_PCH_CPT(dev))
2736                 cpt_phase_pointer_enable(dev, pipe);
2737
2738         for (i = 0; i < 4; i++) {
2739                 reg = FDI_TX_CTL(pipe);
2740                 temp = I915_READ(reg);
2741                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2742                 temp |= snb_b_fdi_train_param[i];
2743                 I915_WRITE(reg, temp);
2744
2745                 POSTING_READ(reg);
2746                 udelay(500);
2747
2748                 reg = FDI_RX_IIR(pipe);
2749                 temp = I915_READ(reg);
2750                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2751
2752                 if (temp & FDI_RX_BIT_LOCK ||
2753                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2754                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2755                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2756                         break;
2757                 }
2758         }
2759         if (i == 4)
2760                 DRM_ERROR("FDI train 1 fail!\n");
2761
2762         /* Train 2 */
2763         reg = FDI_TX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2766         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2767         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2768         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2769         I915_WRITE(reg, temp);
2770
2771         reg = FDI_RX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2775         I915_WRITE(reg, temp);
2776
2777         POSTING_READ(reg);
2778         udelay(150);
2779
2780         for (i = 0; i < 4; i++) {
2781                 reg = FDI_TX_CTL(pipe);
2782                 temp = I915_READ(reg);
2783                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784                 temp |= snb_b_fdi_train_param[i];
2785                 I915_WRITE(reg, temp);
2786
2787                 POSTING_READ(reg);
2788                 udelay(500);
2789
2790                 reg = FDI_RX_IIR(pipe);
2791                 temp = I915_READ(reg);
2792                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2793
2794                 if (temp & FDI_RX_SYMBOL_LOCK) {
2795                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2796                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2797                         break;
2798                 }
2799         }
2800         if (i == 4)
2801                 DRM_ERROR("FDI train 2 fail!\n");
2802
2803         DRM_DEBUG_KMS("FDI train done.\n");
2804 }
2805
2806 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813
2814         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         temp &= ~((0x7 << 19) | (0x7 << 16));
2818         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2821
2822         POSTING_READ(reg);
2823         udelay(200);
2824
2825         /* Switch from Rawclk to PCDclk */
2826         temp = I915_READ(reg);
2827         I915_WRITE(reg, temp | FDI_PCDCLK);
2828
2829         POSTING_READ(reg);
2830         udelay(200);
2831
2832         /* On Haswell, the PLL configuration for ports and pipes is handled
2833          * separately, as part of DDI setup */
2834         if (!IS_HASWELL(dev)) {
2835                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2836                 reg = FDI_TX_CTL(pipe);
2837                 temp = I915_READ(reg);
2838                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2839                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2840
2841                         POSTING_READ(reg);
2842                         udelay(100);
2843                 }
2844         }
2845 }
2846
2847 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2848 {
2849         struct drm_device *dev = intel_crtc->base.dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853
2854         /* Switch from PCDclk to Rawclk */
2855         reg = FDI_RX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2858
2859         /* Disable CPU FDI TX PLL */
2860         reg = FDI_TX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2863
2864         POSTING_READ(reg);
2865         udelay(100);
2866
2867         reg = FDI_RX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2870
2871         /* Wait for the clocks to turn off. */
2872         POSTING_READ(reg);
2873         udelay(100);
2874 }
2875
2876 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2877 {
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         u32 flags = I915_READ(SOUTH_CHICKEN1);
2880
2881         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2882         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2883         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2884         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2885         POSTING_READ(SOUTH_CHICKEN1);
2886 }
2887 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2888 {
2889         struct drm_device *dev = crtc->dev;
2890         struct drm_i915_private *dev_priv = dev->dev_private;
2891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2892         int pipe = intel_crtc->pipe;
2893         u32 reg, temp;
2894
2895         /* disable CPU FDI tx and PCH FDI rx */
2896         reg = FDI_TX_CTL(pipe);
2897         temp = I915_READ(reg);
2898         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2899         POSTING_READ(reg);
2900
2901         reg = FDI_RX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         temp &= ~(0x7 << 16);
2904         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2905         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2906
2907         POSTING_READ(reg);
2908         udelay(100);
2909
2910         /* Ironlake workaround, disable clock pointer after downing FDI */
2911         if (HAS_PCH_IBX(dev)) {
2912                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2913                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2914                            I915_READ(FDI_RX_CHICKEN(pipe) &
2915                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2916         } else if (HAS_PCH_CPT(dev)) {
2917                 cpt_phase_pointer_disable(dev, pipe);
2918         }
2919
2920         /* still set train pattern 1 */
2921         reg = FDI_TX_CTL(pipe);
2922         temp = I915_READ(reg);
2923         temp &= ~FDI_LINK_TRAIN_NONE;
2924         temp |= FDI_LINK_TRAIN_PATTERN_1;
2925         I915_WRITE(reg, temp);
2926
2927         reg = FDI_RX_CTL(pipe);
2928         temp = I915_READ(reg);
2929         if (HAS_PCH_CPT(dev)) {
2930                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2931                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2932         } else {
2933                 temp &= ~FDI_LINK_TRAIN_NONE;
2934                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2935         }
2936         /* BPC in FDI rx is consistent with that in PIPECONF */
2937         temp &= ~(0x07 << 16);
2938         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2939         I915_WRITE(reg, temp);
2940
2941         POSTING_READ(reg);
2942         udelay(100);
2943 }
2944
2945 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         unsigned long flags;
2950         bool pending;
2951
2952         if (atomic_read(&dev_priv->mm.wedged))
2953                 return false;
2954
2955         spin_lock_irqsave(&dev->event_lock, flags);
2956         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2957         spin_unlock_irqrestore(&dev->event_lock, flags);
2958
2959         return pending;
2960 }
2961
2962 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2963 {
2964         struct drm_device *dev = crtc->dev;
2965         struct drm_i915_private *dev_priv = dev->dev_private;
2966
2967         if (crtc->fb == NULL)
2968                 return;
2969
2970         wait_event(dev_priv->pending_flip_queue,
2971                    !intel_crtc_has_pending_flip(crtc));
2972
2973         mutex_lock(&dev->struct_mutex);
2974         intel_finish_fb(crtc->fb);
2975         mutex_unlock(&dev->struct_mutex);
2976 }
2977
2978 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2979 {
2980         struct drm_device *dev = crtc->dev;
2981         struct intel_encoder *intel_encoder;
2982
2983         /*
2984          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2985          * must be driven by its own crtc; no sharing is possible.
2986          */
2987         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2988                 switch (intel_encoder->type) {
2989                 case INTEL_OUTPUT_EDP:
2990                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2991                                 return false;
2992                         continue;
2993                 }
2994         }
2995
2996         return true;
2997 }
2998
2999 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3000 {
3001         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3002 }
3003
3004 /* Program iCLKIP clock to the desired frequency */
3005 static void lpt_program_iclkip(struct drm_crtc *crtc)
3006 {
3007         struct drm_device *dev = crtc->dev;
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3010         u32 temp;
3011
3012         /* It is necessary to ungate the pixclk gate prior to programming
3013          * the divisors, and gate it back when it is done.
3014          */
3015         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3016
3017         /* Disable SSCCTL */
3018         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3019                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3020                                         SBI_SSCCTL_DISABLE);
3021
3022         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3023         if (crtc->mode.clock == 20000) {
3024                 auxdiv = 1;
3025                 divsel = 0x41;
3026                 phaseinc = 0x20;
3027         } else {
3028                 /* The iCLK virtual clock root frequency is in MHz,
3029                  * but the crtc->mode.clock in in KHz. To get the divisors,
3030                  * it is necessary to divide one by another, so we
3031                  * convert the virtual clock precision to KHz here for higher
3032                  * precision.
3033                  */
3034                 u32 iclk_virtual_root_freq = 172800 * 1000;
3035                 u32 iclk_pi_range = 64;
3036                 u32 desired_divisor, msb_divisor_value, pi_value;
3037
3038                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3039                 msb_divisor_value = desired_divisor / iclk_pi_range;
3040                 pi_value = desired_divisor % iclk_pi_range;
3041
3042                 auxdiv = 0;
3043                 divsel = msb_divisor_value - 2;
3044                 phaseinc = pi_value;
3045         }
3046
3047         /* This should not happen with any sane values */
3048         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3049                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3050         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3051                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3052
3053         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3054                         crtc->mode.clock,
3055                         auxdiv,
3056                         divsel,
3057                         phasedir,
3058                         phaseinc);
3059
3060         /* Program SSCDIVINTPHASE6 */
3061         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3062         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3063         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3064         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3065         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3066         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3067         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3068
3069         intel_sbi_write(dev_priv,
3070                         SBI_SSCDIVINTPHASE6,
3071                         temp);
3072
3073         /* Program SSCAUXDIV */
3074         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3075         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3076         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3077         intel_sbi_write(dev_priv,
3078                         SBI_SSCAUXDIV6,
3079                         temp);
3080
3081
3082         /* Enable modulator and associated divider */
3083         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3084         temp &= ~SBI_SSCCTL_DISABLE;
3085         intel_sbi_write(dev_priv,
3086                         SBI_SSCCTL6,
3087                         temp);
3088
3089         /* Wait for initialization time */
3090         udelay(24);
3091
3092         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3093 }
3094
3095 /*
3096  * Enable PCH resources required for PCH ports:
3097  *   - PCH PLLs
3098  *   - FDI training & RX/TX
3099  *   - update transcoder timings
3100  *   - DP transcoding bits
3101  *   - transcoder
3102  */
3103 static void ironlake_pch_enable(struct drm_crtc *crtc)
3104 {
3105         struct drm_device *dev = crtc->dev;
3106         struct drm_i915_private *dev_priv = dev->dev_private;
3107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108         int pipe = intel_crtc->pipe;
3109         u32 reg, temp;
3110
3111         assert_transcoder_disabled(dev_priv, pipe);
3112
3113         /* Write the TU size bits before fdi link training, so that error
3114          * detection works. */
3115         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3116                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3117
3118         /* For PCH output, training FDI link */
3119         dev_priv->display.fdi_link_train(crtc);
3120
3121         /* XXX: pch pll's can be enabled any time before we enable the PCH
3122          * transcoder, and we actually should do this to not upset any PCH
3123          * transcoder that already use the clock when we share it.
3124          *
3125          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3126          * unconditionally resets the pll - we need that to have the right LVDS
3127          * enable sequence. */
3128         ironlake_enable_pch_pll(intel_crtc);
3129
3130         if (HAS_PCH_CPT(dev)) {
3131                 u32 sel;
3132
3133                 temp = I915_READ(PCH_DPLL_SEL);
3134                 switch (pipe) {
3135                 default:
3136                 case 0:
3137                         temp |= TRANSA_DPLL_ENABLE;
3138                         sel = TRANSA_DPLLB_SEL;
3139                         break;
3140                 case 1:
3141                         temp |= TRANSB_DPLL_ENABLE;
3142                         sel = TRANSB_DPLLB_SEL;
3143                         break;
3144                 case 2:
3145                         temp |= TRANSC_DPLL_ENABLE;
3146                         sel = TRANSC_DPLLB_SEL;
3147                         break;
3148                 }
3149                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3150                         temp |= sel;
3151                 else
3152                         temp &= ~sel;
3153                 I915_WRITE(PCH_DPLL_SEL, temp);
3154         }
3155
3156         /* set transcoder timing, panel must allow it */
3157         assert_panel_unlocked(dev_priv, pipe);
3158         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3159         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3160         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3161
3162         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3163         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3164         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3165         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3166
3167         intel_fdi_normal_train(crtc);
3168
3169         /* For PCH DP, enable TRANS_DP_CTL */
3170         if (HAS_PCH_CPT(dev) &&
3171             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3172              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3173                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3174                 reg = TRANS_DP_CTL(pipe);
3175                 temp = I915_READ(reg);
3176                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3177                           TRANS_DP_SYNC_MASK |
3178                           TRANS_DP_BPC_MASK);
3179                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3180                          TRANS_DP_ENH_FRAMING);
3181                 temp |= bpc << 9; /* same format but at 11:9 */
3182
3183                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3184                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3185                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3186                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3187
3188                 switch (intel_trans_dp_port_sel(crtc)) {
3189                 case PCH_DP_B:
3190                         temp |= TRANS_DP_PORT_SEL_B;
3191                         break;
3192                 case PCH_DP_C:
3193                         temp |= TRANS_DP_PORT_SEL_C;
3194                         break;
3195                 case PCH_DP_D:
3196                         temp |= TRANS_DP_PORT_SEL_D;
3197                         break;
3198                 default:
3199                         BUG();
3200                 }
3201
3202                 I915_WRITE(reg, temp);
3203         }
3204
3205         ironlake_enable_pch_transcoder(dev_priv, pipe);
3206 }
3207
3208 static void lpt_pch_enable(struct drm_crtc *crtc)
3209 {
3210         struct drm_device *dev = crtc->dev;
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213         int pipe = intel_crtc->pipe;
3214         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3215
3216         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3217
3218         /* Write the TU size bits before fdi link training, so that error
3219          * detection works. */
3220         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3221                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3222
3223         /* For PCH output, training FDI link */
3224         dev_priv->display.fdi_link_train(crtc);
3225
3226         lpt_program_iclkip(crtc);
3227
3228         /* Set transcoder timing. */
3229         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3231         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3232
3233         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3236         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3237
3238         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3239 }
3240
3241 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3242 {
3243         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3244
3245         if (pll == NULL)
3246                 return;
3247
3248         if (pll->refcount == 0) {
3249                 WARN(1, "bad PCH PLL refcount\n");
3250                 return;
3251         }
3252
3253         --pll->refcount;
3254         intel_crtc->pch_pll = NULL;
3255 }
3256
3257 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3258 {
3259         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3260         struct intel_pch_pll *pll;
3261         int i;
3262
3263         pll = intel_crtc->pch_pll;
3264         if (pll) {
3265                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3266                               intel_crtc->base.base.id, pll->pll_reg);
3267                 goto prepare;
3268         }
3269
3270         if (HAS_PCH_IBX(dev_priv->dev)) {
3271                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3272                 i = intel_crtc->pipe;
3273                 pll = &dev_priv->pch_plls[i];
3274
3275                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3276                               intel_crtc->base.base.id, pll->pll_reg);
3277
3278                 goto found;
3279         }
3280
3281         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3282                 pll = &dev_priv->pch_plls[i];
3283
3284                 /* Only want to check enabled timings first */
3285                 if (pll->refcount == 0)
3286                         continue;
3287
3288                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3289                     fp == I915_READ(pll->fp0_reg)) {
3290                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3291                                       intel_crtc->base.base.id,
3292                                       pll->pll_reg, pll->refcount, pll->active);
3293
3294                         goto found;
3295                 }
3296         }
3297
3298         /* Ok no matching timings, maybe there's a free one? */
3299         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3300                 pll = &dev_priv->pch_plls[i];
3301                 if (pll->refcount == 0) {
3302                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3303                                       intel_crtc->base.base.id, pll->pll_reg);
3304                         goto found;
3305                 }
3306         }
3307
3308         return NULL;
3309
3310 found:
3311         intel_crtc->pch_pll = pll;
3312         pll->refcount++;
3313         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3314 prepare: /* separate function? */
3315         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3316
3317         /* Wait for the clocks to stabilize before rewriting the regs */
3318         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3319         POSTING_READ(pll->pll_reg);
3320         udelay(150);
3321
3322         I915_WRITE(pll->fp0_reg, fp);
3323         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3324         pll->on = false;
3325         return pll;
3326 }
3327
3328 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3329 {
3330         struct drm_i915_private *dev_priv = dev->dev_private;
3331         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3332         u32 temp;
3333
3334         temp = I915_READ(dslreg);
3335         udelay(500);
3336         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3337                 /* Without this, mode sets may fail silently on FDI */
3338                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3339                 udelay(250);
3340                 I915_WRITE(tc2reg, 0);
3341                 if (wait_for(I915_READ(dslreg) != temp, 5))
3342                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3343         }
3344 }
3345
3346 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         struct intel_encoder *encoder;
3352         int pipe = intel_crtc->pipe;
3353         int plane = intel_crtc->plane;
3354         u32 temp;
3355         bool is_pch_port;
3356
3357         WARN_ON(!crtc->enabled);
3358
3359         if (intel_crtc->active)
3360                 return;
3361
3362         intel_crtc->active = true;
3363         intel_update_watermarks(dev);
3364
3365         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3366                 temp = I915_READ(PCH_LVDS);
3367                 if ((temp & LVDS_PORT_EN) == 0)
3368                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3369         }
3370
3371         is_pch_port = ironlake_crtc_driving_pch(crtc);
3372
3373         if (is_pch_port) {
3374                 /* Note: FDI PLL enabling _must_ be done before we enable the
3375                  * cpu pipes, hence this is separate from all the other fdi/pch
3376                  * enabling. */
3377                 ironlake_fdi_pll_enable(intel_crtc);
3378         } else {
3379                 assert_fdi_tx_disabled(dev_priv, pipe);
3380                 assert_fdi_rx_disabled(dev_priv, pipe);
3381         }
3382
3383         for_each_encoder_on_crtc(dev, crtc, encoder)
3384                 if (encoder->pre_enable)
3385                         encoder->pre_enable(encoder);
3386
3387         /* Enable panel fitting for LVDS */
3388         if (dev_priv->pch_pf_size &&
3389             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3390                 /* Force use of hard-coded filter coefficients
3391                  * as some pre-programmed values are broken,
3392                  * e.g. x201.
3393                  */
3394                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3395                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3396                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3397         }
3398
3399         /*
3400          * On ILK+ LUT must be loaded before the pipe is running but with
3401          * clocks enabled
3402          */
3403         intel_crtc_load_lut(crtc);
3404
3405         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3406         intel_enable_plane(dev_priv, plane, pipe);
3407
3408         if (is_pch_port)
3409                 ironlake_pch_enable(crtc);
3410
3411         mutex_lock(&dev->struct_mutex);
3412         intel_update_fbc(dev);
3413         mutex_unlock(&dev->struct_mutex);
3414
3415         intel_crtc_update_cursor(crtc, true);
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 encoder->enable(encoder);
3419
3420         if (HAS_PCH_CPT(dev))
3421                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3422
3423         /*
3424          * There seems to be a race in PCH platform hw (at least on some
3425          * outputs) where an enabled pipe still completes any pageflip right
3426          * away (as if the pipe is off) instead of waiting for vblank. As soon
3427          * as the first vblank happend, everything works as expected. Hence just
3428          * wait for one vblank before returning to avoid strange things
3429          * happening.
3430          */
3431         intel_wait_for_vblank(dev, intel_crtc->pipe);
3432 }
3433
3434 static void haswell_crtc_enable(struct drm_crtc *crtc)
3435 {
3436         struct drm_device *dev = crtc->dev;
3437         struct drm_i915_private *dev_priv = dev->dev_private;
3438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439         struct intel_encoder *encoder;
3440         int pipe = intel_crtc->pipe;
3441         int plane = intel_crtc->plane;
3442         bool is_pch_port;
3443
3444         WARN_ON(!crtc->enabled);
3445
3446         if (intel_crtc->active)
3447                 return;
3448
3449         intel_crtc->active = true;
3450         intel_update_watermarks(dev);
3451
3452         is_pch_port = haswell_crtc_driving_pch(crtc);
3453
3454         if (is_pch_port)
3455                 ironlake_fdi_pll_enable(intel_crtc);
3456
3457         for_each_encoder_on_crtc(dev, crtc, encoder)
3458                 if (encoder->pre_enable)
3459                         encoder->pre_enable(encoder);
3460
3461         intel_ddi_enable_pipe_clock(intel_crtc);
3462
3463         /* Enable panel fitting for eDP */
3464         if (dev_priv->pch_pf_size && HAS_eDP) {
3465                 /* Force use of hard-coded filter coefficients
3466                  * as some pre-programmed values are broken,
3467                  * e.g. x201.
3468                  */
3469                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3470                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3471                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3472         }
3473
3474         /*
3475          * On ILK+ LUT must be loaded before the pipe is running but with
3476          * clocks enabled
3477          */
3478         intel_crtc_load_lut(crtc);
3479
3480         intel_ddi_set_pipe_settings(crtc);
3481         intel_ddi_enable_pipe_func(crtc);
3482
3483         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3484         intel_enable_plane(dev_priv, plane, pipe);
3485
3486         if (is_pch_port)
3487                 lpt_pch_enable(crtc);
3488
3489         mutex_lock(&dev->struct_mutex);
3490         intel_update_fbc(dev);
3491         mutex_unlock(&dev->struct_mutex);
3492
3493         intel_crtc_update_cursor(crtc, true);
3494
3495         for_each_encoder_on_crtc(dev, crtc, encoder)
3496                 encoder->enable(encoder);
3497
3498         /*
3499          * There seems to be a race in PCH platform hw (at least on some
3500          * outputs) where an enabled pipe still completes any pageflip right
3501          * away (as if the pipe is off) instead of waiting for vblank. As soon
3502          * as the first vblank happend, everything works as expected. Hence just
3503          * wait for one vblank before returning to avoid strange things
3504          * happening.
3505          */
3506         intel_wait_for_vblank(dev, intel_crtc->pipe);
3507 }
3508
3509 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3510 {
3511         struct drm_device *dev = crtc->dev;
3512         struct drm_i915_private *dev_priv = dev->dev_private;
3513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514         struct intel_encoder *encoder;
3515         int pipe = intel_crtc->pipe;
3516         int plane = intel_crtc->plane;
3517         u32 reg, temp;
3518
3519
3520         if (!intel_crtc->active)
3521                 return;
3522
3523         for_each_encoder_on_crtc(dev, crtc, encoder)
3524                 encoder->disable(encoder);
3525
3526         intel_crtc_wait_for_pending_flips(crtc);
3527         drm_vblank_off(dev, pipe);
3528         intel_crtc_update_cursor(crtc, false);
3529
3530         intel_disable_plane(dev_priv, plane, pipe);
3531
3532         if (dev_priv->cfb_plane == plane)
3533                 intel_disable_fbc(dev);
3534
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         /* Disable PF */
3538         I915_WRITE(PF_CTL(pipe), 0);
3539         I915_WRITE(PF_WIN_SZ(pipe), 0);
3540
3541         for_each_encoder_on_crtc(dev, crtc, encoder)
3542                 if (encoder->post_disable)
3543                         encoder->post_disable(encoder);
3544
3545         ironlake_fdi_disable(crtc);
3546
3547         ironlake_disable_pch_transcoder(dev_priv, pipe);
3548
3549         if (HAS_PCH_CPT(dev)) {
3550                 /* disable TRANS_DP_CTL */
3551                 reg = TRANS_DP_CTL(pipe);
3552                 temp = I915_READ(reg);
3553                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3554                 temp |= TRANS_DP_PORT_SEL_NONE;
3555                 I915_WRITE(reg, temp);
3556
3557                 /* disable DPLL_SEL */
3558                 temp = I915_READ(PCH_DPLL_SEL);
3559                 switch (pipe) {
3560                 case 0:
3561                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3562                         break;
3563                 case 1:
3564                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3565                         break;
3566                 case 2:
3567                         /* C shares PLL A or B */
3568                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3569                         break;
3570                 default:
3571                         BUG(); /* wtf */
3572                 }
3573                 I915_WRITE(PCH_DPLL_SEL, temp);
3574         }
3575
3576         /* disable PCH DPLL */
3577         intel_disable_pch_pll(intel_crtc);
3578
3579         ironlake_fdi_pll_disable(intel_crtc);
3580
3581         intel_crtc->active = false;
3582         intel_update_watermarks(dev);
3583
3584         mutex_lock(&dev->struct_mutex);
3585         intel_update_fbc(dev);
3586         mutex_unlock(&dev->struct_mutex);
3587 }
3588
3589 static void haswell_crtc_disable(struct drm_crtc *crtc)
3590 {
3591         struct drm_device *dev = crtc->dev;
3592         struct drm_i915_private *dev_priv = dev->dev_private;
3593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594         struct intel_encoder *encoder;
3595         int pipe = intel_crtc->pipe;
3596         int plane = intel_crtc->plane;
3597         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3598         bool is_pch_port;
3599
3600         if (!intel_crtc->active)
3601                 return;
3602
3603         is_pch_port = haswell_crtc_driving_pch(crtc);
3604
3605         for_each_encoder_on_crtc(dev, crtc, encoder)
3606                 encoder->disable(encoder);
3607
3608         intel_crtc_wait_for_pending_flips(crtc);
3609         drm_vblank_off(dev, pipe);
3610         intel_crtc_update_cursor(crtc, false);
3611
3612         intel_disable_plane(dev_priv, plane, pipe);
3613
3614         if (dev_priv->cfb_plane == plane)
3615                 intel_disable_fbc(dev);
3616
3617         intel_disable_pipe(dev_priv, pipe);
3618
3619         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3620
3621         /* Disable PF */
3622         I915_WRITE(PF_CTL(pipe), 0);
3623         I915_WRITE(PF_WIN_SZ(pipe), 0);
3624
3625         intel_ddi_disable_pipe_clock(intel_crtc);
3626
3627         for_each_encoder_on_crtc(dev, crtc, encoder)
3628                 if (encoder->post_disable)
3629                         encoder->post_disable(encoder);
3630
3631         if (is_pch_port) {
3632                 ironlake_fdi_disable(crtc);
3633                 lpt_disable_pch_transcoder(dev_priv, pipe);
3634                 intel_disable_pch_pll(intel_crtc);
3635                 ironlake_fdi_pll_disable(intel_crtc);
3636         }
3637
3638         intel_crtc->active = false;
3639         intel_update_watermarks(dev);
3640
3641         mutex_lock(&dev->struct_mutex);
3642         intel_update_fbc(dev);
3643         mutex_unlock(&dev->struct_mutex);
3644 }
3645
3646 static void ironlake_crtc_off(struct drm_crtc *crtc)
3647 {
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         intel_put_pch_pll(intel_crtc);
3650 }
3651
3652 static void haswell_crtc_off(struct drm_crtc *crtc)
3653 {
3654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655
3656         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3657          * start using it. */
3658         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3659
3660         intel_ddi_put_crtc_pll(crtc);
3661 }
3662
3663 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3664 {
3665         if (!enable && intel_crtc->overlay) {
3666                 struct drm_device *dev = intel_crtc->base.dev;
3667                 struct drm_i915_private *dev_priv = dev->dev_private;
3668
3669                 mutex_lock(&dev->struct_mutex);
3670                 dev_priv->mm.interruptible = false;
3671                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3672                 dev_priv->mm.interruptible = true;
3673                 mutex_unlock(&dev->struct_mutex);
3674         }
3675
3676         /* Let userspace switch the overlay on again. In most cases userspace
3677          * has to recompute where to put it anyway.
3678          */
3679 }
3680
3681 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3682 {
3683         struct drm_device *dev = crtc->dev;
3684         struct drm_i915_private *dev_priv = dev->dev_private;
3685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3686         struct intel_encoder *encoder;
3687         int pipe = intel_crtc->pipe;
3688         int plane = intel_crtc->plane;
3689
3690         WARN_ON(!crtc->enabled);
3691
3692         if (intel_crtc->active)
3693                 return;
3694
3695         intel_crtc->active = true;
3696         intel_update_watermarks(dev);
3697
3698         intel_enable_pll(dev_priv, pipe);
3699         intel_enable_pipe(dev_priv, pipe, false);
3700         intel_enable_plane(dev_priv, plane, pipe);
3701
3702         intel_crtc_load_lut(crtc);
3703         intel_update_fbc(dev);
3704
3705         /* Give the overlay scaler a chance to enable if it's on this pipe */
3706         intel_crtc_dpms_overlay(intel_crtc, true);
3707         intel_crtc_update_cursor(crtc, true);
3708
3709         for_each_encoder_on_crtc(dev, crtc, encoder)
3710                 encoder->enable(encoder);
3711 }
3712
3713 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3714 {
3715         struct drm_device *dev = crtc->dev;
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718         struct intel_encoder *encoder;
3719         int pipe = intel_crtc->pipe;
3720         int plane = intel_crtc->plane;
3721
3722
3723         if (!intel_crtc->active)
3724                 return;
3725
3726         for_each_encoder_on_crtc(dev, crtc, encoder)
3727                 encoder->disable(encoder);
3728
3729         /* Give the overlay scaler a chance to disable if it's on this pipe */
3730         intel_crtc_wait_for_pending_flips(crtc);
3731         drm_vblank_off(dev, pipe);
3732         intel_crtc_dpms_overlay(intel_crtc, false);
3733         intel_crtc_update_cursor(crtc, false);
3734
3735         if (dev_priv->cfb_plane == plane)
3736                 intel_disable_fbc(dev);
3737
3738         intel_disable_plane(dev_priv, plane, pipe);
3739         intel_disable_pipe(dev_priv, pipe);
3740         intel_disable_pll(dev_priv, pipe);
3741
3742         intel_crtc->active = false;
3743         intel_update_fbc(dev);
3744         intel_update_watermarks(dev);
3745 }
3746
3747 static void i9xx_crtc_off(struct drm_crtc *crtc)
3748 {
3749 }
3750
3751 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3752                                     bool enabled)
3753 {
3754         struct drm_device *dev = crtc->dev;
3755         struct drm_i915_master_private *master_priv;
3756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757         int pipe = intel_crtc->pipe;
3758
3759         if (!dev->primary->master)
3760                 return;
3761
3762         master_priv = dev->primary->master->driver_priv;
3763         if (!master_priv->sarea_priv)
3764                 return;
3765
3766         switch (pipe) {
3767         case 0:
3768                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3769                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3770                 break;
3771         case 1:
3772                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3773                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3774                 break;
3775         default:
3776                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3777                 break;
3778         }
3779 }
3780
3781 /**
3782  * Sets the power management mode of the pipe and plane.
3783  */
3784 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3785 {
3786         struct drm_device *dev = crtc->dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         struct intel_encoder *intel_encoder;
3789         bool enable = false;
3790
3791         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3792                 enable |= intel_encoder->connectors_active;
3793
3794         if (enable)
3795                 dev_priv->display.crtc_enable(crtc);
3796         else
3797                 dev_priv->display.crtc_disable(crtc);
3798
3799         intel_crtc_update_sarea(crtc, enable);
3800 }
3801
3802 static void intel_crtc_noop(struct drm_crtc *crtc)
3803 {
3804 }
3805
3806 static void intel_crtc_disable(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_connector *connector;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811
3812         /* crtc should still be enabled when we disable it. */
3813         WARN_ON(!crtc->enabled);
3814
3815         dev_priv->display.crtc_disable(crtc);
3816         intel_crtc_update_sarea(crtc, false);
3817         dev_priv->display.off(crtc);
3818
3819         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3820         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3821
3822         if (crtc->fb) {
3823                 mutex_lock(&dev->struct_mutex);
3824                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3825                 mutex_unlock(&dev->struct_mutex);
3826                 crtc->fb = NULL;
3827         }
3828
3829         /* Update computed state. */
3830         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3831                 if (!connector->encoder || !connector->encoder->crtc)
3832                         continue;
3833
3834                 if (connector->encoder->crtc != crtc)
3835                         continue;
3836
3837                 connector->dpms = DRM_MODE_DPMS_OFF;
3838                 to_intel_encoder(connector->encoder)->connectors_active = false;
3839         }
3840 }
3841
3842 void intel_modeset_disable(struct drm_device *dev)
3843 {
3844         struct drm_crtc *crtc;
3845
3846         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3847                 if (crtc->enabled)
3848                         intel_crtc_disable(crtc);
3849         }
3850 }
3851
3852 void intel_encoder_noop(struct drm_encoder *encoder)
3853 {
3854 }
3855
3856 void intel_encoder_destroy(struct drm_encoder *encoder)
3857 {
3858         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3859
3860         drm_encoder_cleanup(encoder);
3861         kfree(intel_encoder);
3862 }
3863
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866  * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3868 {
3869         if (mode == DRM_MODE_DPMS_ON) {
3870                 encoder->connectors_active = true;
3871
3872                 intel_crtc_update_dpms(encoder->base.crtc);
3873         } else {
3874                 encoder->connectors_active = false;
3875
3876                 intel_crtc_update_dpms(encoder->base.crtc);
3877         }
3878 }
3879
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881  * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector *connector)
3883 {
3884         if (connector->get_hw_state(connector)) {
3885                 struct intel_encoder *encoder = connector->encoder;
3886                 struct drm_crtc *crtc;
3887                 bool encoder_enabled;
3888                 enum pipe pipe;
3889
3890                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891                               connector->base.base.id,
3892                               drm_get_connector_name(&connector->base));
3893
3894                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895                      "wrong connector dpms state\n");
3896                 WARN(connector->base.encoder != &encoder->base,
3897                      "active connector not linked to encoder\n");
3898                 WARN(!encoder->connectors_active,
3899                      "encoder->connectors_active not set\n");
3900
3901                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902                 WARN(!encoder_enabled, "encoder not enabled\n");
3903                 if (WARN_ON(!encoder->base.crtc))
3904                         return;
3905
3906                 crtc = encoder->base.crtc;
3907
3908                 WARN(!crtc->enabled, "crtc not enabled\n");
3909                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911                      "encoder active on the wrong pipe\n");
3912         }
3913 }
3914
3915 /* Even simpler default implementation, if there's really no special case to
3916  * consider. */
3917 void intel_connector_dpms(struct drm_connector *connector, int mode)
3918 {
3919         struct intel_encoder *encoder = intel_attached_encoder(connector);
3920
3921         /* All the simple cases only support two dpms states. */
3922         if (mode != DRM_MODE_DPMS_ON)
3923                 mode = DRM_MODE_DPMS_OFF;
3924
3925         if (mode == connector->dpms)
3926                 return;
3927
3928         connector->dpms = mode;
3929
3930         /* Only need to change hw state when actually enabled */
3931         if (encoder->base.crtc)
3932                 intel_encoder_dpms(encoder, mode);
3933         else
3934                 WARN_ON(encoder->connectors_active != false);
3935
3936         intel_modeset_check_state(connector->dev);
3937 }
3938
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940  * one connector and no cloning and hence the encoder state determines the state
3941  * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 {
3944         enum pipe pipe = 0;
3945         struct intel_encoder *encoder = connector->encoder;
3946
3947         return encoder->get_hw_state(encoder, &pipe);
3948 }
3949
3950 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3951                                   const struct drm_display_mode *mode,
3952                                   struct drm_display_mode *adjusted_mode)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955
3956         if (HAS_PCH_SPLIT(dev)) {
3957                 /* FDI link clock is fixed at 2.7G */
3958                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3959                         return false;
3960         }
3961
3962         /* All interlaced capable intel hw wants timings in frames. Note though
3963          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964          * timings, so we need to be careful not to clobber these.*/
3965         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3966                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3967
3968         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969          * with a hsync front porch of 0.
3970          */
3971         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973                 return false;
3974
3975         return true;
3976 }
3977
3978 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3979 {
3980         return 400000; /* FIXME */
3981 }
3982
3983 static int i945_get_display_clock_speed(struct drm_device *dev)
3984 {
3985         return 400000;
3986 }
3987
3988 static int i915_get_display_clock_speed(struct drm_device *dev)
3989 {
3990         return 333000;
3991 }
3992
3993 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3994 {
3995         return 200000;
3996 }
3997
3998 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3999 {
4000         u16 gcfgc = 0;
4001
4002         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4003
4004         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4005                 return 133000;
4006         else {
4007                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4008                 case GC_DISPLAY_CLOCK_333_MHZ:
4009                         return 333000;
4010                 default:
4011                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4012                         return 190000;
4013                 }
4014         }
4015 }
4016
4017 static int i865_get_display_clock_speed(struct drm_device *dev)
4018 {
4019         return 266000;
4020 }
4021
4022 static int i855_get_display_clock_speed(struct drm_device *dev)
4023 {
4024         u16 hpllcc = 0;
4025         /* Assume that the hardware is in the high speed state.  This
4026          * should be the default.
4027          */
4028         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4029         case GC_CLOCK_133_200:
4030         case GC_CLOCK_100_200:
4031                 return 200000;
4032         case GC_CLOCK_166_250:
4033                 return 250000;
4034         case GC_CLOCK_100_133:
4035                 return 133000;
4036         }
4037
4038         /* Shouldn't happen */
4039         return 0;
4040 }
4041
4042 static int i830_get_display_clock_speed(struct drm_device *dev)
4043 {
4044         return 133000;
4045 }
4046
4047 struct fdi_m_n {
4048         u32        tu;
4049         u32        gmch_m;
4050         u32        gmch_n;
4051         u32        link_m;
4052         u32        link_n;
4053 };
4054
4055 static void
4056 fdi_reduce_ratio(u32 *num, u32 *den)
4057 {
4058         while (*num > 0xffffff || *den > 0xffffff) {
4059                 *num >>= 1;
4060                 *den >>= 1;
4061         }
4062 }
4063
4064 static void
4065 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4066                      int link_clock, struct fdi_m_n *m_n)
4067 {
4068         m_n->tu = 64; /* default size */
4069
4070         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4071         m_n->gmch_m = bits_per_pixel * pixel_clock;
4072         m_n->gmch_n = link_clock * nlanes * 8;
4073         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4074
4075         m_n->link_m = pixel_clock;
4076         m_n->link_n = link_clock;
4077         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4078 }
4079
4080 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4081 {
4082         if (i915_panel_use_ssc >= 0)
4083                 return i915_panel_use_ssc != 0;
4084         return dev_priv->lvds_use_ssc
4085                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4086 }
4087
4088 /**
4089  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4090  * @crtc: CRTC structure
4091  * @mode: requested mode
4092  *
4093  * A pipe may be connected to one or more outputs.  Based on the depth of the
4094  * attached framebuffer, choose a good color depth to use on the pipe.
4095  *
4096  * If possible, match the pipe depth to the fb depth.  In some cases, this
4097  * isn't ideal, because the connected output supports a lesser or restricted
4098  * set of depths.  Resolve that here:
4099  *    LVDS typically supports only 6bpc, so clamp down in that case
4100  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4101  *    Displays may support a restricted set as well, check EDID and clamp as
4102  *      appropriate.
4103  *    DP may want to dither down to 6bpc to fit larger modes
4104  *
4105  * RETURNS:
4106  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4107  * true if they don't match).
4108  */
4109 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4110                                          struct drm_framebuffer *fb,
4111                                          unsigned int *pipe_bpp,
4112                                          struct drm_display_mode *mode)
4113 {
4114         struct drm_device *dev = crtc->dev;
4115         struct drm_i915_private *dev_priv = dev->dev_private;
4116         struct drm_connector *connector;
4117         struct intel_encoder *intel_encoder;
4118         unsigned int display_bpc = UINT_MAX, bpc;
4119
4120         /* Walk the encoders & connectors on this crtc, get min bpc */
4121         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4122
4123                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4124                         unsigned int lvds_bpc;
4125
4126                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4127                             LVDS_A3_POWER_UP)
4128                                 lvds_bpc = 8;
4129                         else
4130                                 lvds_bpc = 6;
4131
4132                         if (lvds_bpc < display_bpc) {
4133                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4134                                 display_bpc = lvds_bpc;
4135                         }
4136                         continue;
4137                 }
4138
4139                 /* Not one of the known troublemakers, check the EDID */
4140                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4141                                     head) {
4142                         if (connector->encoder != &intel_encoder->base)
4143                                 continue;
4144
4145                         /* Don't use an invalid EDID bpc value */
4146                         if (connector->display_info.bpc &&
4147                             connector->display_info.bpc < display_bpc) {
4148                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4149                                 display_bpc = connector->display_info.bpc;
4150                         }
4151                 }
4152
4153                 /*
4154                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4155                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4156                  */
4157                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4158                         if (display_bpc > 8 && display_bpc < 12) {
4159                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4160                                 display_bpc = 12;
4161                         } else {
4162                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4163                                 display_bpc = 8;
4164                         }
4165                 }
4166         }
4167
4168         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4169                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4170                 display_bpc = 6;
4171         }
4172
4173         /*
4174          * We could just drive the pipe at the highest bpc all the time and
4175          * enable dithering as needed, but that costs bandwidth.  So choose
4176          * the minimum value that expresses the full color range of the fb but
4177          * also stays within the max display bpc discovered above.
4178          */
4179
4180         switch (fb->depth) {
4181         case 8:
4182                 bpc = 8; /* since we go through a colormap */
4183                 break;
4184         case 15:
4185         case 16:
4186                 bpc = 6; /* min is 18bpp */
4187                 break;
4188         case 24:
4189                 bpc = 8;
4190                 break;
4191         case 30:
4192                 bpc = 10;
4193                 break;
4194         case 48:
4195                 bpc = 12;
4196                 break;
4197         default:
4198                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4199                 bpc = min((unsigned int)8, display_bpc);
4200                 break;
4201         }
4202
4203         display_bpc = min(display_bpc, bpc);
4204
4205         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4206                       bpc, display_bpc);
4207
4208         *pipe_bpp = display_bpc * 3;
4209
4210         return display_bpc != bpc;
4211 }
4212
4213 static int vlv_get_refclk(struct drm_crtc *crtc)
4214 {
4215         struct drm_device *dev = crtc->dev;
4216         struct drm_i915_private *dev_priv = dev->dev_private;
4217         int refclk = 27000; /* for DP & HDMI */
4218
4219         return 100000; /* only one validated so far */
4220
4221         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4222                 refclk = 96000;
4223         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4224                 if (intel_panel_use_ssc(dev_priv))
4225                         refclk = 100000;
4226                 else
4227                         refclk = 96000;
4228         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4229                 refclk = 100000;
4230         }
4231
4232         return refclk;
4233 }
4234
4235 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239         int refclk;
4240
4241         if (IS_VALLEYVIEW(dev)) {
4242                 refclk = vlv_get_refclk(crtc);
4243         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4244             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4245                 refclk = dev_priv->lvds_ssc_freq * 1000;
4246                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4247                               refclk / 1000);
4248         } else if (!IS_GEN2(dev)) {
4249                 refclk = 96000;
4250         } else {
4251                 refclk = 48000;
4252         }
4253
4254         return refclk;
4255 }
4256
4257 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4258                                       intel_clock_t *clock)
4259 {
4260         /* SDVO TV has fixed PLL values depend on its clock range,
4261            this mirrors vbios setting. */
4262         if (adjusted_mode->clock >= 100000
4263             && adjusted_mode->clock < 140500) {
4264                 clock->p1 = 2;
4265                 clock->p2 = 10;
4266                 clock->n = 3;
4267                 clock->m1 = 16;
4268                 clock->m2 = 8;
4269         } else if (adjusted_mode->clock >= 140500
4270                    && adjusted_mode->clock <= 200000) {
4271                 clock->p1 = 1;
4272                 clock->p2 = 10;
4273                 clock->n = 6;
4274                 clock->m1 = 12;
4275                 clock->m2 = 8;
4276         }
4277 }
4278
4279 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4280                                      intel_clock_t *clock,
4281                                      intel_clock_t *reduced_clock)
4282 {
4283         struct drm_device *dev = crtc->dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         int pipe = intel_crtc->pipe;
4287         u32 fp, fp2 = 0;
4288
4289         if (IS_PINEVIEW(dev)) {
4290                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4291                 if (reduced_clock)
4292                         fp2 = (1 << reduced_clock->n) << 16 |
4293                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4294         } else {
4295                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4296                 if (reduced_clock)
4297                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4298                                 reduced_clock->m2;
4299         }
4300
4301         I915_WRITE(FP0(pipe), fp);
4302
4303         intel_crtc->lowfreq_avail = false;
4304         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4305             reduced_clock && i915_powersave) {
4306                 I915_WRITE(FP1(pipe), fp2);
4307                 intel_crtc->lowfreq_avail = true;
4308         } else {
4309                 I915_WRITE(FP1(pipe), fp);
4310         }
4311 }
4312
4313 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4314                               struct drm_display_mode *adjusted_mode)
4315 {
4316         struct drm_device *dev = crtc->dev;
4317         struct drm_i915_private *dev_priv = dev->dev_private;
4318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319         int pipe = intel_crtc->pipe;
4320         u32 temp;
4321
4322         temp = I915_READ(LVDS);
4323         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4324         if (pipe == 1) {
4325                 temp |= LVDS_PIPEB_SELECT;
4326         } else {
4327                 temp &= ~LVDS_PIPEB_SELECT;
4328         }
4329         /* set the corresponsding LVDS_BORDER bit */
4330         temp |= dev_priv->lvds_border_bits;
4331         /* Set the B0-B3 data pairs corresponding to whether we're going to
4332          * set the DPLLs for dual-channel mode or not.
4333          */
4334         if (clock->p2 == 7)
4335                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4336         else
4337                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4338
4339         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4340          * appropriately here, but we need to look more thoroughly into how
4341          * panels behave in the two modes.
4342          */
4343         /* set the dithering flag on LVDS as needed */
4344         if (INTEL_INFO(dev)->gen >= 4) {
4345                 if (dev_priv->lvds_dither)
4346                         temp |= LVDS_ENABLE_DITHER;
4347                 else
4348                         temp &= ~LVDS_ENABLE_DITHER;
4349         }
4350         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4351         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4352                 temp |= LVDS_HSYNC_POLARITY;
4353         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4354                 temp |= LVDS_VSYNC_POLARITY;
4355         I915_WRITE(LVDS, temp);
4356 }
4357
4358 static void vlv_update_pll(struct drm_crtc *crtc,
4359                            struct drm_display_mode *mode,
4360                            struct drm_display_mode *adjusted_mode,
4361                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4362                            int num_connectors)
4363 {
4364         struct drm_device *dev = crtc->dev;
4365         struct drm_i915_private *dev_priv = dev->dev_private;
4366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367         int pipe = intel_crtc->pipe;
4368         u32 dpll, mdiv, pdiv;
4369         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4370         bool is_sdvo;
4371         u32 temp;
4372
4373         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4374                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4375
4376         dpll = DPLL_VGA_MODE_DIS;
4377         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4378         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4379         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4380
4381         I915_WRITE(DPLL(pipe), dpll);
4382         POSTING_READ(DPLL(pipe));
4383
4384         bestn = clock->n;
4385         bestm1 = clock->m1;
4386         bestm2 = clock->m2;
4387         bestp1 = clock->p1;
4388         bestp2 = clock->p2;
4389
4390         /*
4391          * In Valleyview PLL and program lane counter registers are exposed
4392          * through DPIO interface
4393          */
4394         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4395         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4396         mdiv |= ((bestn << DPIO_N_SHIFT));
4397         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4398         mdiv |= (1 << DPIO_K_SHIFT);
4399         mdiv |= DPIO_ENABLE_CALIBRATION;
4400         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4403
4404         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4405                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4406                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4407                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4408         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4409
4410         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4411
4412         dpll |= DPLL_VCO_ENABLE;
4413         I915_WRITE(DPLL(pipe), dpll);
4414         POSTING_READ(DPLL(pipe));
4415         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4416                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4417
4418         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4419
4420         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4421                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4422
4423         I915_WRITE(DPLL(pipe), dpll);
4424
4425         /* Wait for the clocks to stabilize. */
4426         POSTING_READ(DPLL(pipe));
4427         udelay(150);
4428
4429         temp = 0;
4430         if (is_sdvo) {
4431                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4432                 if (temp > 1)
4433                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4434                 else
4435                         temp = 0;
4436         }
4437         I915_WRITE(DPLL_MD(pipe), temp);
4438         POSTING_READ(DPLL_MD(pipe));
4439
4440         /* Now program lane control registers */
4441         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4442                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4443         {
4444                 temp = 0x1000C4;
4445                 if(pipe == 1)
4446                         temp |= (1 << 21);
4447                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4448         }
4449         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4450         {
4451                 temp = 0x1000C4;
4452                 if(pipe == 1)
4453                         temp |= (1 << 21);
4454                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4455         }
4456 }
4457
4458 static void i9xx_update_pll(struct drm_crtc *crtc,
4459                             struct drm_display_mode *mode,
4460                             struct drm_display_mode *adjusted_mode,
4461                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4462                             int num_connectors)
4463 {
4464         struct drm_device *dev = crtc->dev;
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467         int pipe = intel_crtc->pipe;
4468         u32 dpll;
4469         bool is_sdvo;
4470
4471         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4472
4473         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4474                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4475
4476         dpll = DPLL_VGA_MODE_DIS;
4477
4478         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4479                 dpll |= DPLLB_MODE_LVDS;
4480         else
4481                 dpll |= DPLLB_MODE_DAC_SERIAL;
4482         if (is_sdvo) {
4483                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4484                 if (pixel_multiplier > 1) {
4485                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4486                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4487                 }
4488                 dpll |= DPLL_DVO_HIGH_SPEED;
4489         }
4490         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4491                 dpll |= DPLL_DVO_HIGH_SPEED;
4492
4493         /* compute bitmask from p1 value */
4494         if (IS_PINEVIEW(dev))
4495                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4496         else {
4497                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4498                 if (IS_G4X(dev) && reduced_clock)
4499                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4500         }
4501         switch (clock->p2) {
4502         case 5:
4503                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4504                 break;
4505         case 7:
4506                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4507                 break;
4508         case 10:
4509                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4510                 break;
4511         case 14:
4512                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4513                 break;
4514         }
4515         if (INTEL_INFO(dev)->gen >= 4)
4516                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4517
4518         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4520         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4521                 /* XXX: just matching BIOS for now */
4522                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4523                 dpll |= 3;
4524         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4525                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4526                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4527         else
4528                 dpll |= PLL_REF_INPUT_DREFCLK;
4529
4530         dpll |= DPLL_VCO_ENABLE;
4531         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4532         POSTING_READ(DPLL(pipe));
4533         udelay(150);
4534
4535         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4536          * This is an exception to the general rule that mode_set doesn't turn
4537          * things on.
4538          */
4539         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4540                 intel_update_lvds(crtc, clock, adjusted_mode);
4541
4542         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4543                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4544
4545         I915_WRITE(DPLL(pipe), dpll);
4546
4547         /* Wait for the clocks to stabilize. */
4548         POSTING_READ(DPLL(pipe));
4549         udelay(150);
4550
4551         if (INTEL_INFO(dev)->gen >= 4) {
4552                 u32 temp = 0;
4553                 if (is_sdvo) {
4554                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4555                         if (temp > 1)
4556                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4557                         else
4558                                 temp = 0;
4559                 }
4560                 I915_WRITE(DPLL_MD(pipe), temp);
4561         } else {
4562                 /* The pixel multiplier can only be updated once the
4563                  * DPLL is enabled and the clocks are stable.
4564                  *
4565                  * So write it again.
4566                  */
4567                 I915_WRITE(DPLL(pipe), dpll);
4568         }
4569 }
4570
4571 static void i8xx_update_pll(struct drm_crtc *crtc,
4572                             struct drm_display_mode *adjusted_mode,
4573                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4574                             int num_connectors)
4575 {
4576         struct drm_device *dev = crtc->dev;
4577         struct drm_i915_private *dev_priv = dev->dev_private;
4578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579         int pipe = intel_crtc->pipe;
4580         u32 dpll;
4581
4582         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4583
4584         dpll = DPLL_VGA_MODE_DIS;
4585
4586         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4587                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588         } else {
4589                 if (clock->p1 == 2)
4590                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4591                 else
4592                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593                 if (clock->p2 == 4)
4594                         dpll |= PLL_P2_DIVIDE_BY_4;
4595         }
4596
4597         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4598                 /* XXX: just matching BIOS for now */
4599                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4600                 dpll |= 3;
4601         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4602                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604         else
4605                 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607         dpll |= DPLL_VCO_ENABLE;
4608         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609         POSTING_READ(DPLL(pipe));
4610         udelay(150);
4611
4612         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4613          * This is an exception to the general rule that mode_set doesn't turn
4614          * things on.
4615          */
4616         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4617                 intel_update_lvds(crtc, clock, adjusted_mode);
4618
4619         I915_WRITE(DPLL(pipe), dpll);
4620
4621         /* Wait for the clocks to stabilize. */
4622         POSTING_READ(DPLL(pipe));
4623         udelay(150);
4624
4625         /* The pixel multiplier can only be updated once the
4626          * DPLL is enabled and the clocks are stable.
4627          *
4628          * So write it again.
4629          */
4630         I915_WRITE(DPLL(pipe), dpll);
4631 }
4632
4633 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4634                                    struct drm_display_mode *mode,
4635                                    struct drm_display_mode *adjusted_mode)
4636 {
4637         struct drm_device *dev = intel_crtc->base.dev;
4638         struct drm_i915_private *dev_priv = dev->dev_private;
4639         enum pipe pipe = intel_crtc->pipe;
4640         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4641         uint32_t vsyncshift;
4642
4643         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644                 /* the chip adds 2 halflines automatically */
4645                 adjusted_mode->crtc_vtotal -= 1;
4646                 adjusted_mode->crtc_vblank_end -= 1;
4647                 vsyncshift = adjusted_mode->crtc_hsync_start
4648                              - adjusted_mode->crtc_htotal / 2;
4649         } else {
4650                 vsyncshift = 0;
4651         }
4652
4653         if (INTEL_INFO(dev)->gen > 3)
4654                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4655
4656         I915_WRITE(HTOTAL(cpu_transcoder),
4657                    (adjusted_mode->crtc_hdisplay - 1) |
4658                    ((adjusted_mode->crtc_htotal - 1) << 16));
4659         I915_WRITE(HBLANK(cpu_transcoder),
4660                    (adjusted_mode->crtc_hblank_start - 1) |
4661                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4662         I915_WRITE(HSYNC(cpu_transcoder),
4663                    (adjusted_mode->crtc_hsync_start - 1) |
4664                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
4666         I915_WRITE(VTOTAL(cpu_transcoder),
4667                    (adjusted_mode->crtc_vdisplay - 1) |
4668                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4669         I915_WRITE(VBLANK(cpu_transcoder),
4670                    (adjusted_mode->crtc_vblank_start - 1) |
4671                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4672         I915_WRITE(VSYNC(cpu_transcoder),
4673                    (adjusted_mode->crtc_vsync_start - 1) |
4674                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
4676         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679          * bits. */
4680         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681             (pipe == PIPE_B || pipe == PIPE_C))
4682                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
4684         /* pipesrc controls the size that is scaled from, which should
4685          * always be the user's requested size.
4686          */
4687         I915_WRITE(PIPESRC(pipe),
4688                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689 }
4690
4691 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4692                               struct drm_display_mode *mode,
4693                               struct drm_display_mode *adjusted_mode,
4694                               int x, int y,
4695                               struct drm_framebuffer *fb)
4696 {
4697         struct drm_device *dev = crtc->dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700         int pipe = intel_crtc->pipe;
4701         int plane = intel_crtc->plane;
4702         int refclk, num_connectors = 0;
4703         intel_clock_t clock, reduced_clock;
4704         u32 dspcntr, pipeconf;
4705         bool ok, has_reduced_clock = false, is_sdvo = false;
4706         bool is_lvds = false, is_tv = false, is_dp = false;
4707         struct intel_encoder *encoder;
4708         const intel_limit_t *limit;
4709         int ret;
4710
4711         for_each_encoder_on_crtc(dev, crtc, encoder) {
4712                 switch (encoder->type) {
4713                 case INTEL_OUTPUT_LVDS:
4714                         is_lvds = true;
4715                         break;
4716                 case INTEL_OUTPUT_SDVO:
4717                 case INTEL_OUTPUT_HDMI:
4718                         is_sdvo = true;
4719                         if (encoder->needs_tv_clock)
4720                                 is_tv = true;
4721                         break;
4722                 case INTEL_OUTPUT_TVOUT:
4723                         is_tv = true;
4724                         break;
4725                 case INTEL_OUTPUT_DISPLAYPORT:
4726                         is_dp = true;
4727                         break;
4728                 }
4729
4730                 num_connectors++;
4731         }
4732
4733         refclk = i9xx_get_refclk(crtc, num_connectors);
4734
4735         /*
4736          * Returns a set of divisors for the desired target clock with the given
4737          * refclk, or FALSE.  The returned values represent the clock equation:
4738          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4739          */
4740         limit = intel_limit(crtc, refclk);
4741         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4742                              &clock);
4743         if (!ok) {
4744                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4745                 return -EINVAL;
4746         }
4747
4748         /* Ensure that the cursor is valid for the new mode before changing... */
4749         intel_crtc_update_cursor(crtc, true);
4750
4751         if (is_lvds && dev_priv->lvds_downclock_avail) {
4752                 /*
4753                  * Ensure we match the reduced clock's P to the target clock.
4754                  * If the clocks don't match, we can't switch the display clock
4755                  * by using the FP0/FP1. In such case we will disable the LVDS
4756                  * downclock feature.
4757                 */
4758                 has_reduced_clock = limit->find_pll(limit, crtc,
4759                                                     dev_priv->lvds_downclock,
4760                                                     refclk,
4761                                                     &clock,
4762                                                     &reduced_clock);
4763         }
4764
4765         if (is_sdvo && is_tv)
4766                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4767
4768         if (IS_GEN2(dev))
4769                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4770                                 has_reduced_clock ? &reduced_clock : NULL,
4771                                 num_connectors);
4772         else if (IS_VALLEYVIEW(dev))
4773                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4774                                 has_reduced_clock ? &reduced_clock : NULL,
4775                                 num_connectors);
4776         else
4777                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4778                                 has_reduced_clock ? &reduced_clock : NULL,
4779                                 num_connectors);
4780
4781         /* setup pipeconf */
4782         pipeconf = I915_READ(PIPECONF(pipe));
4783
4784         /* Set up the display plane register */
4785         dspcntr = DISPPLANE_GAMMA_ENABLE;
4786
4787         if (pipe == 0)
4788                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4789         else
4790                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4791
4792         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4793                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4794                  * core speed.
4795                  *
4796                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4797                  * pipe == 0 check?
4798                  */
4799                 if (mode->clock >
4800                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4801                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4802                 else
4803                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4804         }
4805
4806         /* default to 8bpc */
4807         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4808         if (is_dp) {
4809                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4810                         pipeconf |= PIPECONF_BPP_6 |
4811                                     PIPECONF_DITHER_EN |
4812                                     PIPECONF_DITHER_TYPE_SP;
4813                 }
4814         }
4815
4816         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4817                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4818                         pipeconf |= PIPECONF_BPP_6 |
4819                                         PIPECONF_ENABLE |
4820                                         I965_PIPECONF_ACTIVE;
4821                 }
4822         }
4823
4824         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4825         drm_mode_debug_printmodeline(mode);
4826
4827         if (HAS_PIPE_CXSR(dev)) {
4828                 if (intel_crtc->lowfreq_avail) {
4829                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4830                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4831                 } else {
4832                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4833                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4834                 }
4835         }
4836
4837         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4838         if (!IS_GEN2(dev) &&
4839             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4840                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4841         else
4842                 pipeconf |= PIPECONF_PROGRESSIVE;
4843
4844         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4845
4846         /* pipesrc and dspsize control the size that is scaled from,
4847          * which should always be the user's requested size.
4848          */
4849         I915_WRITE(DSPSIZE(plane),
4850                    ((mode->vdisplay - 1) << 16) |
4851                    (mode->hdisplay - 1));
4852         I915_WRITE(DSPPOS(plane), 0);
4853
4854         I915_WRITE(PIPECONF(pipe), pipeconf);
4855         POSTING_READ(PIPECONF(pipe));
4856         intel_enable_pipe(dev_priv, pipe, false);
4857
4858         intel_wait_for_vblank(dev, pipe);
4859
4860         I915_WRITE(DSPCNTR(plane), dspcntr);
4861         POSTING_READ(DSPCNTR(plane));
4862
4863         ret = intel_pipe_set_base(crtc, x, y, fb);
4864
4865         intel_update_watermarks(dev);
4866
4867         return ret;
4868 }
4869
4870 /*
4871  * Initialize reference clocks when the driver loads
4872  */
4873 void ironlake_init_pch_refclk(struct drm_device *dev)
4874 {
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876         struct drm_mode_config *mode_config = &dev->mode_config;
4877         struct intel_encoder *encoder;
4878         u32 temp;
4879         bool has_lvds = false;
4880         bool has_cpu_edp = false;
4881         bool has_pch_edp = false;
4882         bool has_panel = false;
4883         bool has_ck505 = false;
4884         bool can_ssc = false;
4885
4886         /* We need to take the global config into account */
4887         list_for_each_entry(encoder, &mode_config->encoder_list,
4888                             base.head) {
4889                 switch (encoder->type) {
4890                 case INTEL_OUTPUT_LVDS:
4891                         has_panel = true;
4892                         has_lvds = true;
4893                         break;
4894                 case INTEL_OUTPUT_EDP:
4895                         has_panel = true;
4896                         if (intel_encoder_is_pch_edp(&encoder->base))
4897                                 has_pch_edp = true;
4898                         else
4899                                 has_cpu_edp = true;
4900                         break;
4901                 }
4902         }
4903
4904         if (HAS_PCH_IBX(dev)) {
4905                 has_ck505 = dev_priv->display_clock_mode;
4906                 can_ssc = has_ck505;
4907         } else {
4908                 has_ck505 = false;
4909                 can_ssc = true;
4910         }
4911
4912         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4913                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4914                       has_ck505);
4915
4916         /* Ironlake: try to setup display ref clock before DPLL
4917          * enabling. This is only under driver's control after
4918          * PCH B stepping, previous chipset stepping should be
4919          * ignoring this setting.
4920          */
4921         temp = I915_READ(PCH_DREF_CONTROL);
4922         /* Always enable nonspread source */
4923         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4924
4925         if (has_ck505)
4926                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4927         else
4928                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4929
4930         if (has_panel) {
4931                 temp &= ~DREF_SSC_SOURCE_MASK;
4932                 temp |= DREF_SSC_SOURCE_ENABLE;
4933
4934                 /* SSC must be turned on before enabling the CPU output  */
4935                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4936                         DRM_DEBUG_KMS("Using SSC on panel\n");
4937                         temp |= DREF_SSC1_ENABLE;
4938                 } else
4939                         temp &= ~DREF_SSC1_ENABLE;
4940
4941                 /* Get SSC going before enabling the outputs */
4942                 I915_WRITE(PCH_DREF_CONTROL, temp);
4943                 POSTING_READ(PCH_DREF_CONTROL);
4944                 udelay(200);
4945
4946                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4947
4948                 /* Enable CPU source on CPU attached eDP */
4949                 if (has_cpu_edp) {
4950                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4951                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4952                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4953                         }
4954                         else
4955                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4956                 } else
4957                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4958
4959                 I915_WRITE(PCH_DREF_CONTROL, temp);
4960                 POSTING_READ(PCH_DREF_CONTROL);
4961                 udelay(200);
4962         } else {
4963                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4964
4965                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4966
4967                 /* Turn off CPU output */
4968                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4969
4970                 I915_WRITE(PCH_DREF_CONTROL, temp);
4971                 POSTING_READ(PCH_DREF_CONTROL);
4972                 udelay(200);
4973
4974                 /* Turn off the SSC source */
4975                 temp &= ~DREF_SSC_SOURCE_MASK;
4976                 temp |= DREF_SSC_SOURCE_DISABLE;
4977
4978                 /* Turn off SSC1 */
4979                 temp &= ~ DREF_SSC1_ENABLE;
4980
4981                 I915_WRITE(PCH_DREF_CONTROL, temp);
4982                 POSTING_READ(PCH_DREF_CONTROL);
4983                 udelay(200);
4984         }
4985 }
4986
4987 static int ironlake_get_refclk(struct drm_crtc *crtc)
4988 {
4989         struct drm_device *dev = crtc->dev;
4990         struct drm_i915_private *dev_priv = dev->dev_private;
4991         struct intel_encoder *encoder;
4992         struct intel_encoder *edp_encoder = NULL;
4993         int num_connectors = 0;
4994         bool is_lvds = false;
4995
4996         for_each_encoder_on_crtc(dev, crtc, encoder) {
4997                 switch (encoder->type) {
4998                 case INTEL_OUTPUT_LVDS:
4999                         is_lvds = true;
5000                         break;
5001                 case INTEL_OUTPUT_EDP:
5002                         edp_encoder = encoder;
5003                         break;
5004                 }
5005                 num_connectors++;
5006         }
5007
5008         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5009                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5010                               dev_priv->lvds_ssc_freq);
5011                 return dev_priv->lvds_ssc_freq * 1000;
5012         }
5013
5014         return 120000;
5015 }
5016
5017 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5018                                   struct drm_display_mode *adjusted_mode,
5019                                   bool dither)
5020 {
5021         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023         int pipe = intel_crtc->pipe;
5024         uint32_t val;
5025
5026         val = I915_READ(PIPECONF(pipe));
5027
5028         val &= ~PIPE_BPC_MASK;
5029         switch (intel_crtc->bpp) {
5030         case 18:
5031                 val |= PIPE_6BPC;
5032                 break;
5033         case 24:
5034                 val |= PIPE_8BPC;
5035                 break;
5036         case 30:
5037                 val |= PIPE_10BPC;
5038                 break;
5039         case 36:
5040                 val |= PIPE_12BPC;
5041                 break;
5042         default:
5043                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5044                 BUG();
5045         }
5046
5047         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5048         if (dither)
5049                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5050
5051         val &= ~PIPECONF_INTERLACE_MASK;
5052         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5053                 val |= PIPECONF_INTERLACED_ILK;
5054         else
5055                 val |= PIPECONF_PROGRESSIVE;
5056
5057         I915_WRITE(PIPECONF(pipe), val);
5058         POSTING_READ(PIPECONF(pipe));
5059 }
5060
5061 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5062                                  struct drm_display_mode *adjusted_mode,
5063                                  bool dither)
5064 {
5065         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5067         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5068         uint32_t val;
5069
5070         val = I915_READ(PIPECONF(cpu_transcoder));
5071
5072         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5073         if (dither)
5074                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5075
5076         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5077         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5078                 val |= PIPECONF_INTERLACED_ILK;
5079         else
5080                 val |= PIPECONF_PROGRESSIVE;
5081
5082         I915_WRITE(PIPECONF(cpu_transcoder), val);
5083         POSTING_READ(PIPECONF(cpu_transcoder));
5084 }
5085
5086 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5087                                     struct drm_display_mode *adjusted_mode,
5088                                     intel_clock_t *clock,
5089                                     bool *has_reduced_clock,
5090                                     intel_clock_t *reduced_clock)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         struct intel_encoder *intel_encoder;
5095         int refclk;
5096         const intel_limit_t *limit;
5097         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5098
5099         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5100                 switch (intel_encoder->type) {
5101                 case INTEL_OUTPUT_LVDS:
5102                         is_lvds = true;
5103                         break;
5104                 case INTEL_OUTPUT_SDVO:
5105                 case INTEL_OUTPUT_HDMI:
5106                         is_sdvo = true;
5107                         if (intel_encoder->needs_tv_clock)
5108                                 is_tv = true;
5109                         break;
5110                 case INTEL_OUTPUT_TVOUT:
5111                         is_tv = true;
5112                         break;
5113                 }
5114         }
5115
5116         refclk = ironlake_get_refclk(crtc);
5117
5118         /*
5119          * Returns a set of divisors for the desired target clock with the given
5120          * refclk, or FALSE.  The returned values represent the clock equation:
5121          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5122          */
5123         limit = intel_limit(crtc, refclk);
5124         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5125                               clock);
5126         if (!ret)
5127                 return false;
5128
5129         if (is_lvds && dev_priv->lvds_downclock_avail) {
5130                 /*
5131                  * Ensure we match the reduced clock's P to the target clock.
5132                  * If the clocks don't match, we can't switch the display clock
5133                  * by using the FP0/FP1. In such case we will disable the LVDS
5134                  * downclock feature.
5135                 */
5136                 *has_reduced_clock = limit->find_pll(limit, crtc,
5137                                                      dev_priv->lvds_downclock,
5138                                                      refclk,
5139                                                      clock,
5140                                                      reduced_clock);
5141         }
5142
5143         if (is_sdvo && is_tv)
5144                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5145
5146         return true;
5147 }
5148
5149 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5150 {
5151         struct drm_i915_private *dev_priv = dev->dev_private;
5152         uint32_t temp;
5153
5154         temp = I915_READ(SOUTH_CHICKEN1);
5155         if (temp & FDI_BC_BIFURCATION_SELECT)
5156                 return;
5157
5158         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5159         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5160
5161         temp |= FDI_BC_BIFURCATION_SELECT;
5162         DRM_DEBUG_KMS("enabling fdi C rx\n");
5163         I915_WRITE(SOUTH_CHICKEN1, temp);
5164         POSTING_READ(SOUTH_CHICKEN1);
5165 }
5166
5167 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5168 {
5169         struct drm_device *dev = intel_crtc->base.dev;
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         struct intel_crtc *pipe_B_crtc =
5172                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5173
5174         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5175                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5176         if (intel_crtc->fdi_lanes > 4) {
5177                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5178                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5179                 /* Clamp lanes to avoid programming the hw with bogus values. */
5180                 intel_crtc->fdi_lanes = 4;
5181
5182                 return false;
5183         }
5184
5185         if (dev_priv->num_pipe == 2)
5186                 return true;
5187
5188         switch (intel_crtc->pipe) {
5189         case PIPE_A:
5190                 return true;
5191         case PIPE_B:
5192                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5193                     intel_crtc->fdi_lanes > 2) {
5194                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5195                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5196                         /* Clamp lanes to avoid programming the hw with bogus values. */
5197                         intel_crtc->fdi_lanes = 2;
5198
5199                         return false;
5200                 }
5201
5202                 if (intel_crtc->fdi_lanes > 2)
5203                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5204                 else
5205                         cpt_enable_fdi_bc_bifurcation(dev);
5206
5207                 return true;
5208         case PIPE_C:
5209                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5210                         if (intel_crtc->fdi_lanes > 2) {
5211                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5212                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5213                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5214                                 intel_crtc->fdi_lanes = 2;
5215
5216                                 return false;
5217                         }
5218                 } else {
5219                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5220                         return false;
5221                 }
5222
5223                 cpt_enable_fdi_bc_bifurcation(dev);
5224
5225                 return true;
5226         default:
5227                 BUG();
5228         }
5229 }
5230
5231 static void ironlake_set_m_n(struct drm_crtc *crtc,
5232                              struct drm_display_mode *mode,
5233                              struct drm_display_mode *adjusted_mode)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct drm_i915_private *dev_priv = dev->dev_private;
5237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5239         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5240         struct fdi_m_n m_n = {0};
5241         int target_clock, pixel_multiplier, lane, link_bw;
5242         bool is_dp = false, is_cpu_edp = false;
5243
5244         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5245                 switch (intel_encoder->type) {
5246                 case INTEL_OUTPUT_DISPLAYPORT:
5247                         is_dp = true;
5248                         break;
5249                 case INTEL_OUTPUT_EDP:
5250                         is_dp = true;
5251                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5252                                 is_cpu_edp = true;
5253                         edp_encoder = intel_encoder;
5254                         break;
5255                 }
5256         }
5257
5258         /* FDI link */
5259         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5260         lane = 0;
5261         /* CPU eDP doesn't require FDI link, so just set DP M/N
5262            according to current link config */
5263         if (is_cpu_edp) {
5264                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5265         } else {
5266                 /* FDI is a binary signal running at ~2.7GHz, encoding
5267                  * each output octet as 10 bits. The actual frequency
5268                  * is stored as a divider into a 100MHz clock, and the
5269                  * mode pixel clock is stored in units of 1KHz.
5270                  * Hence the bw of each lane in terms of the mode signal
5271                  * is:
5272                  */
5273                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5274         }
5275
5276         /* [e]DP over FDI requires target mode clock instead of link clock. */
5277         if (edp_encoder)
5278                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5279         else if (is_dp)
5280                 target_clock = mode->clock;
5281         else
5282                 target_clock = adjusted_mode->clock;
5283
5284         if (!lane) {
5285                 /*
5286                  * Account for spread spectrum to avoid
5287                  * oversubscribing the link. Max center spread
5288                  * is 2.5%; use 5% for safety's sake.
5289                  */
5290                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5291                 lane = bps / (link_bw * 8) + 1;
5292         }
5293
5294         intel_crtc->fdi_lanes = lane;
5295
5296         if (pixel_multiplier > 1)
5297                 link_bw *= pixel_multiplier;
5298         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5299                              &m_n);
5300
5301         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5302         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5303         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5304         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5305 }
5306
5307 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5308                                       struct drm_display_mode *adjusted_mode,
5309                                       intel_clock_t *clock, u32 fp)
5310 {
5311         struct drm_crtc *crtc = &intel_crtc->base;
5312         struct drm_device *dev = crtc->dev;
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct intel_encoder *intel_encoder;
5315         uint32_t dpll;
5316         int factor, pixel_multiplier, num_connectors = 0;
5317         bool is_lvds = false, is_sdvo = false, is_tv = false;
5318         bool is_dp = false, is_cpu_edp = false;
5319
5320         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5321                 switch (intel_encoder->type) {
5322                 case INTEL_OUTPUT_LVDS:
5323                         is_lvds = true;
5324                         break;
5325                 case INTEL_OUTPUT_SDVO:
5326                 case INTEL_OUTPUT_HDMI:
5327                         is_sdvo = true;
5328                         if (intel_encoder->needs_tv_clock)
5329                                 is_tv = true;
5330                         break;
5331                 case INTEL_OUTPUT_TVOUT:
5332                         is_tv = true;
5333                         break;
5334                 case INTEL_OUTPUT_DISPLAYPORT:
5335                         is_dp = true;
5336                         break;
5337                 case INTEL_OUTPUT_EDP:
5338                         is_dp = true;
5339                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5340                                 is_cpu_edp = true;
5341                         break;
5342                 }
5343
5344                 num_connectors++;
5345         }
5346
5347         /* Enable autotuning of the PLL clock (if permissible) */
5348         factor = 21;
5349         if (is_lvds) {
5350                 if ((intel_panel_use_ssc(dev_priv) &&
5351                      dev_priv->lvds_ssc_freq == 100) ||
5352                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5353                         factor = 25;
5354         } else if (is_sdvo && is_tv)
5355                 factor = 20;
5356
5357         if (clock->m < factor * clock->n)
5358                 fp |= FP_CB_TUNE;
5359
5360         dpll = 0;
5361
5362         if (is_lvds)
5363                 dpll |= DPLLB_MODE_LVDS;
5364         else
5365                 dpll |= DPLLB_MODE_DAC_SERIAL;
5366         if (is_sdvo) {
5367                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5368                 if (pixel_multiplier > 1) {
5369                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5370                 }
5371                 dpll |= DPLL_DVO_HIGH_SPEED;
5372         }
5373         if (is_dp && !is_cpu_edp)
5374                 dpll |= DPLL_DVO_HIGH_SPEED;
5375
5376         /* compute bitmask from p1 value */
5377         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5378         /* also FPA1 */
5379         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5380
5381         switch (clock->p2) {
5382         case 5:
5383                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5384                 break;
5385         case 7:
5386                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5387                 break;
5388         case 10:
5389                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5390                 break;
5391         case 14:
5392                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5393                 break;
5394         }
5395
5396         if (is_sdvo && is_tv)
5397                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5398         else if (is_tv)
5399                 /* XXX: just matching BIOS for now */
5400                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5401                 dpll |= 3;
5402         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5403                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5404         else
5405                 dpll |= PLL_REF_INPUT_DREFCLK;
5406
5407         return dpll;
5408 }
5409
5410 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5411                                   struct drm_display_mode *mode,
5412                                   struct drm_display_mode *adjusted_mode,
5413                                   int x, int y,
5414                                   struct drm_framebuffer *fb)
5415 {
5416         struct drm_device *dev = crtc->dev;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419         int pipe = intel_crtc->pipe;
5420         int plane = intel_crtc->plane;
5421         int num_connectors = 0;
5422         intel_clock_t clock, reduced_clock;
5423         u32 dpll, fp = 0, fp2 = 0;
5424         bool ok, has_reduced_clock = false;
5425         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5426         struct intel_encoder *encoder;
5427         u32 temp;
5428         int ret;
5429         bool dither, fdi_config_ok;
5430
5431         for_each_encoder_on_crtc(dev, crtc, encoder) {
5432                 switch (encoder->type) {
5433                 case INTEL_OUTPUT_LVDS:
5434                         is_lvds = true;
5435                         break;
5436                 case INTEL_OUTPUT_DISPLAYPORT:
5437                         is_dp = true;
5438                         break;
5439                 case INTEL_OUTPUT_EDP:
5440                         is_dp = true;
5441                         if (!intel_encoder_is_pch_edp(&encoder->base))
5442                                 is_cpu_edp = true;
5443                         break;
5444                 }
5445
5446                 num_connectors++;
5447         }
5448
5449         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5450              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5451
5452         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5453                                      &has_reduced_clock, &reduced_clock);
5454         if (!ok) {
5455                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5456                 return -EINVAL;
5457         }
5458
5459         /* Ensure that the cursor is valid for the new mode before changing... */
5460         intel_crtc_update_cursor(crtc, true);
5461
5462         /* determine panel color depth */
5463         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5464                                               adjusted_mode);
5465         if (is_lvds && dev_priv->lvds_dither)
5466                 dither = true;
5467
5468         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5469         if (has_reduced_clock)
5470                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5471                         reduced_clock.m2;
5472
5473         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5474
5475         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5476         drm_mode_debug_printmodeline(mode);
5477
5478         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5479         if (!is_cpu_edp) {
5480                 struct intel_pch_pll *pll;
5481
5482                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5483                 if (pll == NULL) {
5484                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5485                                          pipe);
5486                         return -EINVAL;
5487                 }
5488         } else
5489                 intel_put_pch_pll(intel_crtc);
5490
5491         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5492          * This is an exception to the general rule that mode_set doesn't turn
5493          * things on.
5494          */
5495         if (is_lvds) {
5496                 temp = I915_READ(PCH_LVDS);
5497                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5498                 if (HAS_PCH_CPT(dev)) {
5499                         temp &= ~PORT_TRANS_SEL_MASK;
5500                         temp |= PORT_TRANS_SEL_CPT(pipe);
5501                 } else {
5502                         if (pipe == 1)
5503                                 temp |= LVDS_PIPEB_SELECT;
5504                         else
5505                                 temp &= ~LVDS_PIPEB_SELECT;
5506                 }
5507
5508                 /* set the corresponsding LVDS_BORDER bit */
5509                 temp |= dev_priv->lvds_border_bits;
5510                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5511                  * set the DPLLs for dual-channel mode or not.
5512                  */
5513                 if (clock.p2 == 7)
5514                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5515                 else
5516                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5517
5518                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5519                  * appropriately here, but we need to look more thoroughly into how
5520                  * panels behave in the two modes.
5521                  */
5522                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5523                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5524                         temp |= LVDS_HSYNC_POLARITY;
5525                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5526                         temp |= LVDS_VSYNC_POLARITY;
5527                 I915_WRITE(PCH_LVDS, temp);
5528         }
5529
5530         if (is_dp && !is_cpu_edp) {
5531                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5532         } else {
5533                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5534                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5535                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5536                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5537                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5538         }
5539
5540         if (intel_crtc->pch_pll) {
5541                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5542
5543                 /* Wait for the clocks to stabilize. */
5544                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5545                 udelay(150);
5546
5547                 /* The pixel multiplier can only be updated once the
5548                  * DPLL is enabled and the clocks are stable.
5549                  *
5550                  * So write it again.
5551                  */
5552                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5553         }
5554
5555         intel_crtc->lowfreq_avail = false;
5556         if (intel_crtc->pch_pll) {
5557                 if (is_lvds && has_reduced_clock && i915_powersave) {
5558                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5559                         intel_crtc->lowfreq_avail = true;
5560                 } else {
5561                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5562                 }
5563         }
5564
5565         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5566
5567         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5568          * ironlake_check_fdi_lanes. */
5569         ironlake_set_m_n(crtc, mode, adjusted_mode);
5570
5571         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5572
5573         if (is_cpu_edp)
5574                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5575
5576         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5577
5578         intel_wait_for_vblank(dev, pipe);
5579
5580         /* Set up the display plane register */
5581         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5582         POSTING_READ(DSPCNTR(plane));
5583
5584         ret = intel_pipe_set_base(crtc, x, y, fb);
5585
5586         intel_update_watermarks(dev);
5587
5588         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5589
5590         return fdi_config_ok ? ret : -EINVAL;
5591 }
5592
5593 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5594                                  struct drm_display_mode *mode,
5595                                  struct drm_display_mode *adjusted_mode,
5596                                  int x, int y,
5597                                  struct drm_framebuffer *fb)
5598 {
5599         struct drm_device *dev = crtc->dev;
5600         struct drm_i915_private *dev_priv = dev->dev_private;
5601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602         int pipe = intel_crtc->pipe;
5603         int plane = intel_crtc->plane;
5604         int num_connectors = 0;
5605         intel_clock_t clock, reduced_clock;
5606         u32 dpll = 0, fp = 0, fp2 = 0;
5607         bool ok, has_reduced_clock = false;
5608         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5609         struct intel_encoder *encoder;
5610         u32 temp;
5611         int ret;
5612         bool dither;
5613
5614         for_each_encoder_on_crtc(dev, crtc, encoder) {
5615                 switch (encoder->type) {
5616                 case INTEL_OUTPUT_LVDS:
5617                         is_lvds = true;
5618                         break;
5619                 case INTEL_OUTPUT_DISPLAYPORT:
5620                         is_dp = true;
5621                         break;
5622                 case INTEL_OUTPUT_EDP:
5623                         is_dp = true;
5624                         if (!intel_encoder_is_pch_edp(&encoder->base))
5625                                 is_cpu_edp = true;
5626                         break;
5627                 }
5628
5629                 num_connectors++;
5630         }
5631
5632         if (is_cpu_edp)
5633                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5634         else
5635                 intel_crtc->cpu_transcoder = pipe;
5636
5637         /* We are not sure yet this won't happen. */
5638         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5639              INTEL_PCH_TYPE(dev));
5640
5641         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5642              num_connectors, pipe_name(pipe));
5643
5644         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5645                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5646
5647         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5648
5649         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5650                 return -EINVAL;
5651
5652         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5653                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5654                                              &has_reduced_clock,
5655                                              &reduced_clock);
5656                 if (!ok) {
5657                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5658                         return -EINVAL;
5659                 }
5660         }
5661
5662         /* Ensure that the cursor is valid for the new mode before changing... */
5663         intel_crtc_update_cursor(crtc, true);
5664
5665         /* determine panel color depth */
5666         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5667                                               adjusted_mode);
5668         if (is_lvds && dev_priv->lvds_dither)
5669                 dither = true;
5670
5671         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5672         drm_mode_debug_printmodeline(mode);
5673
5674         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5675                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5676                 if (has_reduced_clock)
5677                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5678                               reduced_clock.m2;
5679
5680                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5681                                              fp);
5682
5683                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5684                  * own on pre-Haswell/LPT generation */
5685                 if (!is_cpu_edp) {
5686                         struct intel_pch_pll *pll;
5687
5688                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5689                         if (pll == NULL) {
5690                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5691                                                  pipe);
5692                                 return -EINVAL;
5693                         }
5694                 } else
5695                         intel_put_pch_pll(intel_crtc);
5696
5697                 /* The LVDS pin pair needs to be on before the DPLLs are
5698                  * enabled.  This is an exception to the general rule that
5699                  * mode_set doesn't turn things on.
5700                  */
5701                 if (is_lvds) {
5702                         temp = I915_READ(PCH_LVDS);
5703                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5704                         if (HAS_PCH_CPT(dev)) {
5705                                 temp &= ~PORT_TRANS_SEL_MASK;
5706                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5707                         } else {
5708                                 if (pipe == 1)
5709                                         temp |= LVDS_PIPEB_SELECT;
5710                                 else
5711                                         temp &= ~LVDS_PIPEB_SELECT;
5712                         }
5713
5714                         /* set the corresponsding LVDS_BORDER bit */
5715                         temp |= dev_priv->lvds_border_bits;
5716                         /* Set the B0-B3 data pairs corresponding to whether
5717                          * we're going to set the DPLLs for dual-channel mode or
5718                          * not.
5719                          */
5720                         if (clock.p2 == 7)
5721                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5722                         else
5723                                 temp &= ~(LVDS_B0B3_POWER_UP |
5724                                           LVDS_CLKB_POWER_UP);
5725
5726                         /* It would be nice to set 24 vs 18-bit mode
5727                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5728                          * look more thoroughly into how panels behave in the
5729                          * two modes.
5730                          */
5731                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5732                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5733                                 temp |= LVDS_HSYNC_POLARITY;
5734                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5735                                 temp |= LVDS_VSYNC_POLARITY;
5736                         I915_WRITE(PCH_LVDS, temp);
5737                 }
5738         }
5739
5740         if (is_dp && !is_cpu_edp) {
5741                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5742         } else {
5743                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5744                         /* For non-DP output, clear any trans DP clock recovery
5745                          * setting.*/
5746                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5747                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5748                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5749                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5750                 }
5751         }
5752
5753         intel_crtc->lowfreq_avail = false;
5754         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5755                 if (intel_crtc->pch_pll) {
5756                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5757
5758                         /* Wait for the clocks to stabilize. */
5759                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5760                         udelay(150);
5761
5762                         /* The pixel multiplier can only be updated once the
5763                          * DPLL is enabled and the clocks are stable.
5764                          *
5765                          * So write it again.
5766                          */
5767                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768                 }
5769
5770                 if (intel_crtc->pch_pll) {
5771                         if (is_lvds && has_reduced_clock && i915_powersave) {
5772                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5773                                 intel_crtc->lowfreq_avail = true;
5774                         } else {
5775                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5776                         }
5777                 }
5778         }
5779
5780         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5781
5782         if (!is_dp || is_cpu_edp)
5783                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5784
5785         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5786                 if (is_cpu_edp)
5787                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5788
5789         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5790
5791         /* Set up the display plane register */
5792         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5793         POSTING_READ(DSPCNTR(plane));
5794
5795         ret = intel_pipe_set_base(crtc, x, y, fb);
5796
5797         intel_update_watermarks(dev);
5798
5799         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5800
5801         return ret;
5802 }
5803
5804 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5805                                struct drm_display_mode *mode,
5806                                struct drm_display_mode *adjusted_mode,
5807                                int x, int y,
5808                                struct drm_framebuffer *fb)
5809 {
5810         struct drm_device *dev = crtc->dev;
5811         struct drm_i915_private *dev_priv = dev->dev_private;
5812         struct drm_encoder_helper_funcs *encoder_funcs;
5813         struct intel_encoder *encoder;
5814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815         int pipe = intel_crtc->pipe;
5816         int ret;
5817
5818         drm_vblank_pre_modeset(dev, pipe);
5819
5820         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5821                                               x, y, fb);
5822         drm_vblank_post_modeset(dev, pipe);
5823
5824         if (ret != 0)
5825                 return ret;
5826
5827         for_each_encoder_on_crtc(dev, crtc, encoder) {
5828                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5829                         encoder->base.base.id,
5830                         drm_get_encoder_name(&encoder->base),
5831                         mode->base.id, mode->name);
5832                 encoder_funcs = encoder->base.helper_private;
5833                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5834         }
5835
5836         return 0;
5837 }
5838
5839 static bool intel_eld_uptodate(struct drm_connector *connector,
5840                                int reg_eldv, uint32_t bits_eldv,
5841                                int reg_elda, uint32_t bits_elda,
5842                                int reg_edid)
5843 {
5844         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5845         uint8_t *eld = connector->eld;
5846         uint32_t i;
5847
5848         i = I915_READ(reg_eldv);
5849         i &= bits_eldv;
5850
5851         if (!eld[0])
5852                 return !i;
5853
5854         if (!i)
5855                 return false;
5856
5857         i = I915_READ(reg_elda);
5858         i &= ~bits_elda;
5859         I915_WRITE(reg_elda, i);
5860
5861         for (i = 0; i < eld[2]; i++)
5862                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5863                         return false;
5864
5865         return true;
5866 }
5867
5868 static void g4x_write_eld(struct drm_connector *connector,
5869                           struct drm_crtc *crtc)
5870 {
5871         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5872         uint8_t *eld = connector->eld;
5873         uint32_t eldv;
5874         uint32_t len;
5875         uint32_t i;
5876
5877         i = I915_READ(G4X_AUD_VID_DID);
5878
5879         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5880                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5881         else
5882                 eldv = G4X_ELDV_DEVCTG;
5883
5884         if (intel_eld_uptodate(connector,
5885                                G4X_AUD_CNTL_ST, eldv,
5886                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5887                                G4X_HDMIW_HDMIEDID))
5888                 return;
5889
5890         i = I915_READ(G4X_AUD_CNTL_ST);
5891         i &= ~(eldv | G4X_ELD_ADDR);
5892         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5893         I915_WRITE(G4X_AUD_CNTL_ST, i);
5894
5895         if (!eld[0])
5896                 return;
5897
5898         len = min_t(uint8_t, eld[2], len);
5899         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5900         for (i = 0; i < len; i++)
5901                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5902
5903         i = I915_READ(G4X_AUD_CNTL_ST);
5904         i |= eldv;
5905         I915_WRITE(G4X_AUD_CNTL_ST, i);
5906 }
5907
5908 static void haswell_write_eld(struct drm_connector *connector,
5909                                      struct drm_crtc *crtc)
5910 {
5911         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5912         uint8_t *eld = connector->eld;
5913         struct drm_device *dev = crtc->dev;
5914         uint32_t eldv;
5915         uint32_t i;
5916         int len;
5917         int pipe = to_intel_crtc(crtc)->pipe;
5918         int tmp;
5919
5920         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5921         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5922         int aud_config = HSW_AUD_CFG(pipe);
5923         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5924
5925
5926         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5927
5928         /* Audio output enable */
5929         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5930         tmp = I915_READ(aud_cntrl_st2);
5931         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5932         I915_WRITE(aud_cntrl_st2, tmp);
5933
5934         /* Wait for 1 vertical blank */
5935         intel_wait_for_vblank(dev, pipe);
5936
5937         /* Set ELD valid state */
5938         tmp = I915_READ(aud_cntrl_st2);
5939         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5940         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5941         I915_WRITE(aud_cntrl_st2, tmp);
5942         tmp = I915_READ(aud_cntrl_st2);
5943         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5944
5945         /* Enable HDMI mode */
5946         tmp = I915_READ(aud_config);
5947         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5948         /* clear N_programing_enable and N_value_index */
5949         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5950         I915_WRITE(aud_config, tmp);
5951
5952         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5953
5954         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5955
5956         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5957                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5958                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5959                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5960         } else
5961                 I915_WRITE(aud_config, 0);
5962
5963         if (intel_eld_uptodate(connector,
5964                                aud_cntrl_st2, eldv,
5965                                aud_cntl_st, IBX_ELD_ADDRESS,
5966                                hdmiw_hdmiedid))
5967                 return;
5968
5969         i = I915_READ(aud_cntrl_st2);
5970         i &= ~eldv;
5971         I915_WRITE(aud_cntrl_st2, i);
5972
5973         if (!eld[0])
5974                 return;
5975
5976         i = I915_READ(aud_cntl_st);
5977         i &= ~IBX_ELD_ADDRESS;
5978         I915_WRITE(aud_cntl_st, i);
5979         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5980         DRM_DEBUG_DRIVER("port num:%d\n", i);
5981
5982         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5983         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984         for (i = 0; i < len; i++)
5985                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5986
5987         i = I915_READ(aud_cntrl_st2);
5988         i |= eldv;
5989         I915_WRITE(aud_cntrl_st2, i);
5990
5991 }
5992
5993 static void ironlake_write_eld(struct drm_connector *connector,
5994                                      struct drm_crtc *crtc)
5995 {
5996         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997         uint8_t *eld = connector->eld;
5998         uint32_t eldv;
5999         uint32_t i;
6000         int len;
6001         int hdmiw_hdmiedid;
6002         int aud_config;
6003         int aud_cntl_st;
6004         int aud_cntrl_st2;
6005         int pipe = to_intel_crtc(crtc)->pipe;
6006
6007         if (HAS_PCH_IBX(connector->dev)) {
6008                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6009                 aud_config = IBX_AUD_CFG(pipe);
6010                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6011                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6012         } else {
6013                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6014                 aud_config = CPT_AUD_CFG(pipe);
6015                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6016                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6017         }
6018
6019         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6020
6021         i = I915_READ(aud_cntl_st);
6022         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6023         if (!i) {
6024                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6025                 /* operate blindly on all ports */
6026                 eldv = IBX_ELD_VALIDB;
6027                 eldv |= IBX_ELD_VALIDB << 4;
6028                 eldv |= IBX_ELD_VALIDB << 8;
6029         } else {
6030                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6031                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6032         }
6033
6034         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6035                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6036                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6037                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6038         } else
6039                 I915_WRITE(aud_config, 0);
6040
6041         if (intel_eld_uptodate(connector,
6042                                aud_cntrl_st2, eldv,
6043                                aud_cntl_st, IBX_ELD_ADDRESS,
6044                                hdmiw_hdmiedid))
6045                 return;
6046
6047         i = I915_READ(aud_cntrl_st2);
6048         i &= ~eldv;
6049         I915_WRITE(aud_cntrl_st2, i);
6050
6051         if (!eld[0])
6052                 return;
6053
6054         i = I915_READ(aud_cntl_st);
6055         i &= ~IBX_ELD_ADDRESS;
6056         I915_WRITE(aud_cntl_st, i);
6057
6058         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6059         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6060         for (i = 0; i < len; i++)
6061                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6062
6063         i = I915_READ(aud_cntrl_st2);
6064         i |= eldv;
6065         I915_WRITE(aud_cntrl_st2, i);
6066 }
6067
6068 void intel_write_eld(struct drm_encoder *encoder,
6069                      struct drm_display_mode *mode)
6070 {
6071         struct drm_crtc *crtc = encoder->crtc;
6072         struct drm_connector *connector;
6073         struct drm_device *dev = encoder->dev;
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075
6076         connector = drm_select_eld(encoder, mode);
6077         if (!connector)
6078                 return;
6079
6080         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6081                          connector->base.id,
6082                          drm_get_connector_name(connector),
6083                          connector->encoder->base.id,
6084                          drm_get_encoder_name(connector->encoder));
6085
6086         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6087
6088         if (dev_priv->display.write_eld)
6089                 dev_priv->display.write_eld(connector, crtc);
6090 }
6091
6092 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6093 void intel_crtc_load_lut(struct drm_crtc *crtc)
6094 {
6095         struct drm_device *dev = crtc->dev;
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098         int palreg = PALETTE(intel_crtc->pipe);
6099         int i;
6100
6101         /* The clocks have to be on to load the palette. */
6102         if (!crtc->enabled || !intel_crtc->active)
6103                 return;
6104
6105         /* use legacy palette for Ironlake */
6106         if (HAS_PCH_SPLIT(dev))
6107                 palreg = LGC_PALETTE(intel_crtc->pipe);
6108
6109         for (i = 0; i < 256; i++) {
6110                 I915_WRITE(palreg + 4 * i,
6111                            (intel_crtc->lut_r[i] << 16) |
6112                            (intel_crtc->lut_g[i] << 8) |
6113                            intel_crtc->lut_b[i]);
6114         }
6115 }
6116
6117 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6118 {
6119         struct drm_device *dev = crtc->dev;
6120         struct drm_i915_private *dev_priv = dev->dev_private;
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122         bool visible = base != 0;
6123         u32 cntl;
6124
6125         if (intel_crtc->cursor_visible == visible)
6126                 return;
6127
6128         cntl = I915_READ(_CURACNTR);
6129         if (visible) {
6130                 /* On these chipsets we can only modify the base whilst
6131                  * the cursor is disabled.
6132                  */
6133                 I915_WRITE(_CURABASE, base);
6134
6135                 cntl &= ~(CURSOR_FORMAT_MASK);
6136                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6137                 cntl |= CURSOR_ENABLE |
6138                         CURSOR_GAMMA_ENABLE |
6139                         CURSOR_FORMAT_ARGB;
6140         } else
6141                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6142         I915_WRITE(_CURACNTR, cntl);
6143
6144         intel_crtc->cursor_visible = visible;
6145 }
6146
6147 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6148 {
6149         struct drm_device *dev = crtc->dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152         int pipe = intel_crtc->pipe;
6153         bool visible = base != 0;
6154
6155         if (intel_crtc->cursor_visible != visible) {
6156                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6157                 if (base) {
6158                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6159                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6160                         cntl |= pipe << 28; /* Connect to correct pipe */
6161                 } else {
6162                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6163                         cntl |= CURSOR_MODE_DISABLE;
6164                 }
6165                 I915_WRITE(CURCNTR(pipe), cntl);
6166
6167                 intel_crtc->cursor_visible = visible;
6168         }
6169         /* and commit changes on next vblank */
6170         I915_WRITE(CURBASE(pipe), base);
6171 }
6172
6173 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6174 {
6175         struct drm_device *dev = crtc->dev;
6176         struct drm_i915_private *dev_priv = dev->dev_private;
6177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178         int pipe = intel_crtc->pipe;
6179         bool visible = base != 0;
6180
6181         if (intel_crtc->cursor_visible != visible) {
6182                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6183                 if (base) {
6184                         cntl &= ~CURSOR_MODE;
6185                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6186                 } else {
6187                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6188                         cntl |= CURSOR_MODE_DISABLE;
6189                 }
6190                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6191
6192                 intel_crtc->cursor_visible = visible;
6193         }
6194         /* and commit changes on next vblank */
6195         I915_WRITE(CURBASE_IVB(pipe), base);
6196 }
6197
6198 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6199 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6200                                      bool on)
6201 {
6202         struct drm_device *dev = crtc->dev;
6203         struct drm_i915_private *dev_priv = dev->dev_private;
6204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205         int pipe = intel_crtc->pipe;
6206         int x = intel_crtc->cursor_x;
6207         int y = intel_crtc->cursor_y;
6208         u32 base, pos;
6209         bool visible;
6210
6211         pos = 0;
6212
6213         if (on && crtc->enabled && crtc->fb) {
6214                 base = intel_crtc->cursor_addr;
6215                 if (x > (int) crtc->fb->width)
6216                         base = 0;
6217
6218                 if (y > (int) crtc->fb->height)
6219                         base = 0;
6220         } else
6221                 base = 0;
6222
6223         if (x < 0) {
6224                 if (x + intel_crtc->cursor_width < 0)
6225                         base = 0;
6226
6227                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6228                 x = -x;
6229         }
6230         pos |= x << CURSOR_X_SHIFT;
6231
6232         if (y < 0) {
6233                 if (y + intel_crtc->cursor_height < 0)
6234                         base = 0;
6235
6236                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6237                 y = -y;
6238         }
6239         pos |= y << CURSOR_Y_SHIFT;
6240
6241         visible = base != 0;
6242         if (!visible && !intel_crtc->cursor_visible)
6243                 return;
6244
6245         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6246                 I915_WRITE(CURPOS_IVB(pipe), pos);
6247                 ivb_update_cursor(crtc, base);
6248         } else {
6249                 I915_WRITE(CURPOS(pipe), pos);
6250                 if (IS_845G(dev) || IS_I865G(dev))
6251                         i845_update_cursor(crtc, base);
6252                 else
6253                         i9xx_update_cursor(crtc, base);
6254         }
6255 }
6256
6257 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6258                                  struct drm_file *file,
6259                                  uint32_t handle,
6260                                  uint32_t width, uint32_t height)
6261 {
6262         struct drm_device *dev = crtc->dev;
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265         struct drm_i915_gem_object *obj;
6266         uint32_t addr;
6267         int ret;
6268
6269         /* if we want to turn off the cursor ignore width and height */
6270         if (!handle) {
6271                 DRM_DEBUG_KMS("cursor off\n");
6272                 addr = 0;
6273                 obj = NULL;
6274                 mutex_lock(&dev->struct_mutex);
6275                 goto finish;
6276         }
6277
6278         /* Currently we only support 64x64 cursors */
6279         if (width != 64 || height != 64) {
6280                 DRM_ERROR("we currently only support 64x64 cursors\n");
6281                 return -EINVAL;
6282         }
6283
6284         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6285         if (&obj->base == NULL)
6286                 return -ENOENT;
6287
6288         if (obj->base.size < width * height * 4) {
6289                 DRM_ERROR("buffer is to small\n");
6290                 ret = -ENOMEM;
6291                 goto fail;
6292         }
6293
6294         /* we only need to pin inside GTT if cursor is non-phy */
6295         mutex_lock(&dev->struct_mutex);
6296         if (!dev_priv->info->cursor_needs_physical) {
6297                 if (obj->tiling_mode) {
6298                         DRM_ERROR("cursor cannot be tiled\n");
6299                         ret = -EINVAL;
6300                         goto fail_locked;
6301                 }
6302
6303                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6304                 if (ret) {
6305                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6306                         goto fail_locked;
6307                 }
6308
6309                 ret = i915_gem_object_put_fence(obj);
6310                 if (ret) {
6311                         DRM_ERROR("failed to release fence for cursor");
6312                         goto fail_unpin;
6313                 }
6314
6315                 addr = obj->gtt_offset;
6316         } else {
6317                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6318                 ret = i915_gem_attach_phys_object(dev, obj,
6319                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6320                                                   align);
6321                 if (ret) {
6322                         DRM_ERROR("failed to attach phys object\n");
6323                         goto fail_locked;
6324                 }
6325                 addr = obj->phys_obj->handle->busaddr;
6326         }
6327
6328         if (IS_GEN2(dev))
6329                 I915_WRITE(CURSIZE, (height << 12) | width);
6330
6331  finish:
6332         if (intel_crtc->cursor_bo) {
6333                 if (dev_priv->info->cursor_needs_physical) {
6334                         if (intel_crtc->cursor_bo != obj)
6335                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6336                 } else
6337                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6338                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6339         }
6340
6341         mutex_unlock(&dev->struct_mutex);
6342
6343         intel_crtc->cursor_addr = addr;
6344         intel_crtc->cursor_bo = obj;
6345         intel_crtc->cursor_width = width;
6346         intel_crtc->cursor_height = height;
6347
6348         intel_crtc_update_cursor(crtc, true);
6349
6350         return 0;
6351 fail_unpin:
6352         i915_gem_object_unpin(obj);
6353 fail_locked:
6354         mutex_unlock(&dev->struct_mutex);
6355 fail:
6356         drm_gem_object_unreference_unlocked(&obj->base);
6357         return ret;
6358 }
6359
6360 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6361 {
6362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363
6364         intel_crtc->cursor_x = x;
6365         intel_crtc->cursor_y = y;
6366
6367         intel_crtc_update_cursor(crtc, true);
6368
6369         return 0;
6370 }
6371
6372 /** Sets the color ramps on behalf of RandR */
6373 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6374                                  u16 blue, int regno)
6375 {
6376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377
6378         intel_crtc->lut_r[regno] = red >> 8;
6379         intel_crtc->lut_g[regno] = green >> 8;
6380         intel_crtc->lut_b[regno] = blue >> 8;
6381 }
6382
6383 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6384                              u16 *blue, int regno)
6385 {
6386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387
6388         *red = intel_crtc->lut_r[regno] << 8;
6389         *green = intel_crtc->lut_g[regno] << 8;
6390         *blue = intel_crtc->lut_b[regno] << 8;
6391 }
6392
6393 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6394                                  u16 *blue, uint32_t start, uint32_t size)
6395 {
6396         int end = (start + size > 256) ? 256 : start + size, i;
6397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399         for (i = start; i < end; i++) {
6400                 intel_crtc->lut_r[i] = red[i] >> 8;
6401                 intel_crtc->lut_g[i] = green[i] >> 8;
6402                 intel_crtc->lut_b[i] = blue[i] >> 8;
6403         }
6404
6405         intel_crtc_load_lut(crtc);
6406 }
6407
6408 /**
6409  * Get a pipe with a simple mode set on it for doing load-based monitor
6410  * detection.
6411  *
6412  * It will be up to the load-detect code to adjust the pipe as appropriate for
6413  * its requirements.  The pipe will be connected to no other encoders.
6414  *
6415  * Currently this code will only succeed if there is a pipe with no encoders
6416  * configured for it.  In the future, it could choose to temporarily disable
6417  * some outputs to free up a pipe for its use.
6418  *
6419  * \return crtc, or NULL if no pipes are available.
6420  */
6421
6422 /* VESA 640x480x72Hz mode to set on the pipe */
6423 static struct drm_display_mode load_detect_mode = {
6424         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6425                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6426 };
6427
6428 static struct drm_framebuffer *
6429 intel_framebuffer_create(struct drm_device *dev,
6430                          struct drm_mode_fb_cmd2 *mode_cmd,
6431                          struct drm_i915_gem_object *obj)
6432 {
6433         struct intel_framebuffer *intel_fb;
6434         int ret;
6435
6436         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6437         if (!intel_fb) {
6438                 drm_gem_object_unreference_unlocked(&obj->base);
6439                 return ERR_PTR(-ENOMEM);
6440         }
6441
6442         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6443         if (ret) {
6444                 drm_gem_object_unreference_unlocked(&obj->base);
6445                 kfree(intel_fb);
6446                 return ERR_PTR(ret);
6447         }
6448
6449         return &intel_fb->base;
6450 }
6451
6452 static u32
6453 intel_framebuffer_pitch_for_width(int width, int bpp)
6454 {
6455         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6456         return ALIGN(pitch, 64);
6457 }
6458
6459 static u32
6460 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6461 {
6462         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6463         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6464 }
6465
6466 static struct drm_framebuffer *
6467 intel_framebuffer_create_for_mode(struct drm_device *dev,
6468                                   struct drm_display_mode *mode,
6469                                   int depth, int bpp)
6470 {
6471         struct drm_i915_gem_object *obj;
6472         struct drm_mode_fb_cmd2 mode_cmd;
6473
6474         obj = i915_gem_alloc_object(dev,
6475                                     intel_framebuffer_size_for_mode(mode, bpp));
6476         if (obj == NULL)
6477                 return ERR_PTR(-ENOMEM);
6478
6479         mode_cmd.width = mode->hdisplay;
6480         mode_cmd.height = mode->vdisplay;
6481         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6482                                                                 bpp);
6483         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6484
6485         return intel_framebuffer_create(dev, &mode_cmd, obj);
6486 }
6487
6488 static struct drm_framebuffer *
6489 mode_fits_in_fbdev(struct drm_device *dev,
6490                    struct drm_display_mode *mode)
6491 {
6492         struct drm_i915_private *dev_priv = dev->dev_private;
6493         struct drm_i915_gem_object *obj;
6494         struct drm_framebuffer *fb;
6495
6496         if (dev_priv->fbdev == NULL)
6497                 return NULL;
6498
6499         obj = dev_priv->fbdev->ifb.obj;
6500         if (obj == NULL)
6501                 return NULL;
6502
6503         fb = &dev_priv->fbdev->ifb.base;
6504         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6505                                                                fb->bits_per_pixel))
6506                 return NULL;
6507
6508         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6509                 return NULL;
6510
6511         return fb;
6512 }
6513
6514 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6515                                 struct drm_display_mode *mode,
6516                                 struct intel_load_detect_pipe *old)
6517 {
6518         struct intel_crtc *intel_crtc;
6519         struct intel_encoder *intel_encoder =
6520                 intel_attached_encoder(connector);
6521         struct drm_crtc *possible_crtc;
6522         struct drm_encoder *encoder = &intel_encoder->base;
6523         struct drm_crtc *crtc = NULL;
6524         struct drm_device *dev = encoder->dev;
6525         struct drm_framebuffer *fb;
6526         int i = -1;
6527
6528         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6529                       connector->base.id, drm_get_connector_name(connector),
6530                       encoder->base.id, drm_get_encoder_name(encoder));
6531
6532         /*
6533          * Algorithm gets a little messy:
6534          *
6535          *   - if the connector already has an assigned crtc, use it (but make
6536          *     sure it's on first)
6537          *
6538          *   - try to find the first unused crtc that can drive this connector,
6539          *     and use that if we find one
6540          */
6541
6542         /* See if we already have a CRTC for this connector */
6543         if (encoder->crtc) {
6544                 crtc = encoder->crtc;
6545
6546                 old->dpms_mode = connector->dpms;
6547                 old->load_detect_temp = false;
6548
6549                 /* Make sure the crtc and connector are running */
6550                 if (connector->dpms != DRM_MODE_DPMS_ON)
6551                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6552
6553                 return true;
6554         }
6555
6556         /* Find an unused one (if possible) */
6557         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6558                 i++;
6559                 if (!(encoder->possible_crtcs & (1 << i)))
6560                         continue;
6561                 if (!possible_crtc->enabled) {
6562                         crtc = possible_crtc;
6563                         break;
6564                 }
6565         }
6566
6567         /*
6568          * If we didn't find an unused CRTC, don't use any.
6569          */
6570         if (!crtc) {
6571                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6572                 return false;
6573         }
6574
6575         intel_encoder->new_crtc = to_intel_crtc(crtc);
6576         to_intel_connector(connector)->new_encoder = intel_encoder;
6577
6578         intel_crtc = to_intel_crtc(crtc);
6579         old->dpms_mode = connector->dpms;
6580         old->load_detect_temp = true;
6581         old->release_fb = NULL;
6582
6583         if (!mode)
6584                 mode = &load_detect_mode;
6585
6586         /* We need a framebuffer large enough to accommodate all accesses
6587          * that the plane may generate whilst we perform load detection.
6588          * We can not rely on the fbcon either being present (we get called
6589          * during its initialisation to detect all boot displays, or it may
6590          * not even exist) or that it is large enough to satisfy the
6591          * requested mode.
6592          */
6593         fb = mode_fits_in_fbdev(dev, mode);
6594         if (fb == NULL) {
6595                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6596                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6597                 old->release_fb = fb;
6598         } else
6599                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6600         if (IS_ERR(fb)) {
6601                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6602                 goto fail;
6603         }
6604
6605         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6606                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6607                 if (old->release_fb)
6608                         old->release_fb->funcs->destroy(old->release_fb);
6609                 goto fail;
6610         }
6611
6612         /* let the connector get through one full cycle before testing */
6613         intel_wait_for_vblank(dev, intel_crtc->pipe);
6614
6615         return true;
6616 fail:
6617         connector->encoder = NULL;
6618         encoder->crtc = NULL;
6619         return false;
6620 }
6621
6622 void intel_release_load_detect_pipe(struct drm_connector *connector,
6623                                     struct intel_load_detect_pipe *old)
6624 {
6625         struct intel_encoder *intel_encoder =
6626                 intel_attached_encoder(connector);
6627         struct drm_encoder *encoder = &intel_encoder->base;
6628
6629         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6630                       connector->base.id, drm_get_connector_name(connector),
6631                       encoder->base.id, drm_get_encoder_name(encoder));
6632
6633         if (old->load_detect_temp) {
6634                 struct drm_crtc *crtc = encoder->crtc;
6635
6636                 to_intel_connector(connector)->new_encoder = NULL;
6637                 intel_encoder->new_crtc = NULL;
6638                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6639
6640                 if (old->release_fb)
6641                         old->release_fb->funcs->destroy(old->release_fb);
6642
6643                 return;
6644         }
6645
6646         /* Switch crtc and encoder back off if necessary */
6647         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6648                 connector->funcs->dpms(connector, old->dpms_mode);
6649 }
6650
6651 /* Returns the clock of the currently programmed mode of the given pipe. */
6652 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6653 {
6654         struct drm_i915_private *dev_priv = dev->dev_private;
6655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6656         int pipe = intel_crtc->pipe;
6657         u32 dpll = I915_READ(DPLL(pipe));
6658         u32 fp;
6659         intel_clock_t clock;
6660
6661         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6662                 fp = I915_READ(FP0(pipe));
6663         else
6664                 fp = I915_READ(FP1(pipe));
6665
6666         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6667         if (IS_PINEVIEW(dev)) {
6668                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6669                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6670         } else {
6671                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6672                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6673         }
6674
6675         if (!IS_GEN2(dev)) {
6676                 if (IS_PINEVIEW(dev))
6677                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6678                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6679                 else
6680                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6681                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6682
6683                 switch (dpll & DPLL_MODE_MASK) {
6684                 case DPLLB_MODE_DAC_SERIAL:
6685                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6686                                 5 : 10;
6687                         break;
6688                 case DPLLB_MODE_LVDS:
6689                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6690                                 7 : 14;
6691                         break;
6692                 default:
6693                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6694                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6695                         return 0;
6696                 }
6697
6698                 /* XXX: Handle the 100Mhz refclk */
6699                 intel_clock(dev, 96000, &clock);
6700         } else {
6701                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6702
6703                 if (is_lvds) {
6704                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6705                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6706                         clock.p2 = 14;
6707
6708                         if ((dpll & PLL_REF_INPUT_MASK) ==
6709                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6710                                 /* XXX: might not be 66MHz */
6711                                 intel_clock(dev, 66000, &clock);
6712                         } else
6713                                 intel_clock(dev, 48000, &clock);
6714                 } else {
6715                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6716                                 clock.p1 = 2;
6717                         else {
6718                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6719                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6720                         }
6721                         if (dpll & PLL_P2_DIVIDE_BY_4)
6722                                 clock.p2 = 4;
6723                         else
6724                                 clock.p2 = 2;
6725
6726                         intel_clock(dev, 48000, &clock);
6727                 }
6728         }
6729
6730         /* XXX: It would be nice to validate the clocks, but we can't reuse
6731          * i830PllIsValid() because it relies on the xf86_config connector
6732          * configuration being accurate, which it isn't necessarily.
6733          */
6734
6735         return clock.dot;
6736 }
6737
6738 /** Returns the currently programmed mode of the given pipe. */
6739 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6740                                              struct drm_crtc *crtc)
6741 {
6742         struct drm_i915_private *dev_priv = dev->dev_private;
6743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6744         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6745         struct drm_display_mode *mode;
6746         int htot = I915_READ(HTOTAL(cpu_transcoder));
6747         int hsync = I915_READ(HSYNC(cpu_transcoder));
6748         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6749         int vsync = I915_READ(VSYNC(cpu_transcoder));
6750
6751         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6752         if (!mode)
6753                 return NULL;
6754
6755         mode->clock = intel_crtc_clock_get(dev, crtc);
6756         mode->hdisplay = (htot & 0xffff) + 1;
6757         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6758         mode->hsync_start = (hsync & 0xffff) + 1;
6759         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6760         mode->vdisplay = (vtot & 0xffff) + 1;
6761         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6762         mode->vsync_start = (vsync & 0xffff) + 1;
6763         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6764
6765         drm_mode_set_name(mode);
6766
6767         return mode;
6768 }
6769
6770 static void intel_increase_pllclock(struct drm_crtc *crtc)
6771 {
6772         struct drm_device *dev = crtc->dev;
6773         drm_i915_private_t *dev_priv = dev->dev_private;
6774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6775         int pipe = intel_crtc->pipe;
6776         int dpll_reg = DPLL(pipe);
6777         int dpll;
6778
6779         if (HAS_PCH_SPLIT(dev))
6780                 return;
6781
6782         if (!dev_priv->lvds_downclock_avail)
6783                 return;
6784
6785         dpll = I915_READ(dpll_reg);
6786         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6787                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6788
6789                 assert_panel_unlocked(dev_priv, pipe);
6790
6791                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6792                 I915_WRITE(dpll_reg, dpll);
6793                 intel_wait_for_vblank(dev, pipe);
6794
6795                 dpll = I915_READ(dpll_reg);
6796                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6797                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6798         }
6799 }
6800
6801 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6802 {
6803         struct drm_device *dev = crtc->dev;
6804         drm_i915_private_t *dev_priv = dev->dev_private;
6805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6806
6807         if (HAS_PCH_SPLIT(dev))
6808                 return;
6809
6810         if (!dev_priv->lvds_downclock_avail)
6811                 return;
6812
6813         /*
6814          * Since this is called by a timer, we should never get here in
6815          * the manual case.
6816          */
6817         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6818                 int pipe = intel_crtc->pipe;
6819                 int dpll_reg = DPLL(pipe);
6820                 int dpll;
6821
6822                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6823
6824                 assert_panel_unlocked(dev_priv, pipe);
6825
6826                 dpll = I915_READ(dpll_reg);
6827                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6828                 I915_WRITE(dpll_reg, dpll);
6829                 intel_wait_for_vblank(dev, pipe);
6830                 dpll = I915_READ(dpll_reg);
6831                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6832                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6833         }
6834
6835 }
6836
6837 void intel_mark_busy(struct drm_device *dev)
6838 {
6839         i915_update_gfx_val(dev->dev_private);
6840 }
6841
6842 void intel_mark_idle(struct drm_device *dev)
6843 {
6844 }
6845
6846 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6847 {
6848         struct drm_device *dev = obj->base.dev;
6849         struct drm_crtc *crtc;
6850
6851         if (!i915_powersave)
6852                 return;
6853
6854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6855                 if (!crtc->fb)
6856                         continue;
6857
6858                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6859                         intel_increase_pllclock(crtc);
6860         }
6861 }
6862
6863 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6864 {
6865         struct drm_device *dev = obj->base.dev;
6866         struct drm_crtc *crtc;
6867
6868         if (!i915_powersave)
6869                 return;
6870
6871         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6872                 if (!crtc->fb)
6873                         continue;
6874
6875                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6876                         intel_decrease_pllclock(crtc);
6877         }
6878 }
6879
6880 static void intel_crtc_destroy(struct drm_crtc *crtc)
6881 {
6882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6883         struct drm_device *dev = crtc->dev;
6884         struct intel_unpin_work *work;
6885         unsigned long flags;
6886
6887         spin_lock_irqsave(&dev->event_lock, flags);
6888         work = intel_crtc->unpin_work;
6889         intel_crtc->unpin_work = NULL;
6890         spin_unlock_irqrestore(&dev->event_lock, flags);
6891
6892         if (work) {
6893                 cancel_work_sync(&work->work);
6894                 kfree(work);
6895         }
6896
6897         drm_crtc_cleanup(crtc);
6898
6899         kfree(intel_crtc);
6900 }
6901
6902 static void intel_unpin_work_fn(struct work_struct *__work)
6903 {
6904         struct intel_unpin_work *work =
6905                 container_of(__work, struct intel_unpin_work, work);
6906
6907         mutex_lock(&work->dev->struct_mutex);
6908         intel_unpin_fb_obj(work->old_fb_obj);
6909         drm_gem_object_unreference(&work->pending_flip_obj->base);
6910         drm_gem_object_unreference(&work->old_fb_obj->base);
6911
6912         intel_update_fbc(work->dev);
6913         mutex_unlock(&work->dev->struct_mutex);
6914         kfree(work);
6915 }
6916
6917 static void do_intel_finish_page_flip(struct drm_device *dev,
6918                                       struct drm_crtc *crtc)
6919 {
6920         drm_i915_private_t *dev_priv = dev->dev_private;
6921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6922         struct intel_unpin_work *work;
6923         struct drm_i915_gem_object *obj;
6924         struct drm_pending_vblank_event *e;
6925         struct timeval tvbl;
6926         unsigned long flags;
6927
6928         /* Ignore early vblank irqs */
6929         if (intel_crtc == NULL)
6930                 return;
6931
6932         spin_lock_irqsave(&dev->event_lock, flags);
6933         work = intel_crtc->unpin_work;
6934         if (work == NULL || !work->pending) {
6935                 spin_unlock_irqrestore(&dev->event_lock, flags);
6936                 return;
6937         }
6938
6939         intel_crtc->unpin_work = NULL;
6940
6941         if (work->event) {
6942                 e = work->event;
6943                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6944
6945                 e->event.tv_sec = tvbl.tv_sec;
6946                 e->event.tv_usec = tvbl.tv_usec;
6947
6948                 list_add_tail(&e->base.link,
6949                               &e->base.file_priv->event_list);
6950                 wake_up_interruptible(&e->base.file_priv->event_wait);
6951         }
6952
6953         drm_vblank_put(dev, intel_crtc->pipe);
6954
6955         spin_unlock_irqrestore(&dev->event_lock, flags);
6956
6957         obj = work->old_fb_obj;
6958
6959         atomic_clear_mask(1 << intel_crtc->plane,
6960                           &obj->pending_flip.counter);
6961
6962         wake_up(&dev_priv->pending_flip_queue);
6963         schedule_work(&work->work);
6964
6965         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6966 }
6967
6968 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6969 {
6970         drm_i915_private_t *dev_priv = dev->dev_private;
6971         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6972
6973         do_intel_finish_page_flip(dev, crtc);
6974 }
6975
6976 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6977 {
6978         drm_i915_private_t *dev_priv = dev->dev_private;
6979         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6980
6981         do_intel_finish_page_flip(dev, crtc);
6982 }
6983
6984 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6985 {
6986         drm_i915_private_t *dev_priv = dev->dev_private;
6987         struct intel_crtc *intel_crtc =
6988                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6989         unsigned long flags;
6990
6991         spin_lock_irqsave(&dev->event_lock, flags);
6992         if (intel_crtc->unpin_work) {
6993                 if ((++intel_crtc->unpin_work->pending) > 1)
6994                         DRM_ERROR("Prepared flip multiple times\n");
6995         } else {
6996                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6997         }
6998         spin_unlock_irqrestore(&dev->event_lock, flags);
6999 }
7000
7001 static int intel_gen2_queue_flip(struct drm_device *dev,
7002                                  struct drm_crtc *crtc,
7003                                  struct drm_framebuffer *fb,
7004                                  struct drm_i915_gem_object *obj)
7005 {
7006         struct drm_i915_private *dev_priv = dev->dev_private;
7007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7008         u32 flip_mask;
7009         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7010         int ret;
7011
7012         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7013         if (ret)
7014                 goto err;
7015
7016         ret = intel_ring_begin(ring, 6);
7017         if (ret)
7018                 goto err_unpin;
7019
7020         /* Can't queue multiple flips, so wait for the previous
7021          * one to finish before executing the next.
7022          */
7023         if (intel_crtc->plane)
7024                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7025         else
7026                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7027         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7028         intel_ring_emit(ring, MI_NOOP);
7029         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7030                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7031         intel_ring_emit(ring, fb->pitches[0]);
7032         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7033         intel_ring_emit(ring, 0); /* aux display base address, unused */
7034         intel_ring_advance(ring);
7035         return 0;
7036
7037 err_unpin:
7038         intel_unpin_fb_obj(obj);
7039 err:
7040         return ret;
7041 }
7042
7043 static int intel_gen3_queue_flip(struct drm_device *dev,
7044                                  struct drm_crtc *crtc,
7045                                  struct drm_framebuffer *fb,
7046                                  struct drm_i915_gem_object *obj)
7047 {
7048         struct drm_i915_private *dev_priv = dev->dev_private;
7049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050         u32 flip_mask;
7051         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7052         int ret;
7053
7054         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7055         if (ret)
7056                 goto err;
7057
7058         ret = intel_ring_begin(ring, 6);
7059         if (ret)
7060                 goto err_unpin;
7061
7062         if (intel_crtc->plane)
7063                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7064         else
7065                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7066         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7067         intel_ring_emit(ring, MI_NOOP);
7068         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7069                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7070         intel_ring_emit(ring, fb->pitches[0]);
7071         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7072         intel_ring_emit(ring, MI_NOOP);
7073
7074         intel_ring_advance(ring);
7075         return 0;
7076
7077 err_unpin:
7078         intel_unpin_fb_obj(obj);
7079 err:
7080         return ret;
7081 }
7082
7083 static int intel_gen4_queue_flip(struct drm_device *dev,
7084                                  struct drm_crtc *crtc,
7085                                  struct drm_framebuffer *fb,
7086                                  struct drm_i915_gem_object *obj)
7087 {
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090         uint32_t pf, pipesrc;
7091         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7092         int ret;
7093
7094         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7095         if (ret)
7096                 goto err;
7097
7098         ret = intel_ring_begin(ring, 4);
7099         if (ret)
7100                 goto err_unpin;
7101
7102         /* i965+ uses the linear or tiled offsets from the
7103          * Display Registers (which do not change across a page-flip)
7104          * so we need only reprogram the base address.
7105          */
7106         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7107                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7108         intel_ring_emit(ring, fb->pitches[0]);
7109         intel_ring_emit(ring,
7110                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7111                         obj->tiling_mode);
7112
7113         /* XXX Enabling the panel-fitter across page-flip is so far
7114          * untested on non-native modes, so ignore it for now.
7115          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7116          */
7117         pf = 0;
7118         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7119         intel_ring_emit(ring, pf | pipesrc);
7120         intel_ring_advance(ring);
7121         return 0;
7122
7123 err_unpin:
7124         intel_unpin_fb_obj(obj);
7125 err:
7126         return ret;
7127 }
7128
7129 static int intel_gen6_queue_flip(struct drm_device *dev,
7130                                  struct drm_crtc *crtc,
7131                                  struct drm_framebuffer *fb,
7132                                  struct drm_i915_gem_object *obj)
7133 {
7134         struct drm_i915_private *dev_priv = dev->dev_private;
7135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7136         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7137         uint32_t pf, pipesrc;
7138         int ret;
7139
7140         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7141         if (ret)
7142                 goto err;
7143
7144         ret = intel_ring_begin(ring, 4);
7145         if (ret)
7146                 goto err_unpin;
7147
7148         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7149                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7150         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7151         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7152
7153         /* Contrary to the suggestions in the documentation,
7154          * "Enable Panel Fitter" does not seem to be required when page
7155          * flipping with a non-native mode, and worse causes a normal
7156          * modeset to fail.
7157          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7158          */
7159         pf = 0;
7160         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7161         intel_ring_emit(ring, pf | pipesrc);
7162         intel_ring_advance(ring);
7163         return 0;
7164
7165 err_unpin:
7166         intel_unpin_fb_obj(obj);
7167 err:
7168         return ret;
7169 }
7170
7171 /*
7172  * On gen7 we currently use the blit ring because (in early silicon at least)
7173  * the render ring doesn't give us interrpts for page flip completion, which
7174  * means clients will hang after the first flip is queued.  Fortunately the
7175  * blit ring generates interrupts properly, so use it instead.
7176  */
7177 static int intel_gen7_queue_flip(struct drm_device *dev,
7178                                  struct drm_crtc *crtc,
7179                                  struct drm_framebuffer *fb,
7180                                  struct drm_i915_gem_object *obj)
7181 {
7182         struct drm_i915_private *dev_priv = dev->dev_private;
7183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7185         uint32_t plane_bit = 0;
7186         int ret;
7187
7188         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7189         if (ret)
7190                 goto err;
7191
7192         switch(intel_crtc->plane) {
7193         case PLANE_A:
7194                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7195                 break;
7196         case PLANE_B:
7197                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7198                 break;
7199         case PLANE_C:
7200                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7201                 break;
7202         default:
7203                 WARN_ONCE(1, "unknown plane in flip command\n");
7204                 ret = -ENODEV;
7205                 goto err_unpin;
7206         }
7207
7208         ret = intel_ring_begin(ring, 4);
7209         if (ret)
7210                 goto err_unpin;
7211
7212         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7213         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7214         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7215         intel_ring_emit(ring, (MI_NOOP));
7216         intel_ring_advance(ring);
7217         return 0;
7218
7219 err_unpin:
7220         intel_unpin_fb_obj(obj);
7221 err:
7222         return ret;
7223 }
7224
7225 static int intel_default_queue_flip(struct drm_device *dev,
7226                                     struct drm_crtc *crtc,
7227                                     struct drm_framebuffer *fb,
7228                                     struct drm_i915_gem_object *obj)
7229 {
7230         return -ENODEV;
7231 }
7232
7233 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7234                                 struct drm_framebuffer *fb,
7235                                 struct drm_pending_vblank_event *event)
7236 {
7237         struct drm_device *dev = crtc->dev;
7238         struct drm_i915_private *dev_priv = dev->dev_private;
7239         struct intel_framebuffer *intel_fb;
7240         struct drm_i915_gem_object *obj;
7241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7242         struct intel_unpin_work *work;
7243         unsigned long flags;
7244         int ret;
7245
7246         /* Can't change pixel format via MI display flips. */
7247         if (fb->pixel_format != crtc->fb->pixel_format)
7248                 return -EINVAL;
7249
7250         /*
7251          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7252          * Note that pitch changes could also affect these register.
7253          */
7254         if (INTEL_INFO(dev)->gen > 3 &&
7255             (fb->offsets[0] != crtc->fb->offsets[0] ||
7256              fb->pitches[0] != crtc->fb->pitches[0]))
7257                 return -EINVAL;
7258
7259         work = kzalloc(sizeof *work, GFP_KERNEL);
7260         if (work == NULL)
7261                 return -ENOMEM;
7262
7263         work->event = event;
7264         work->dev = crtc->dev;
7265         intel_fb = to_intel_framebuffer(crtc->fb);
7266         work->old_fb_obj = intel_fb->obj;
7267         INIT_WORK(&work->work, intel_unpin_work_fn);
7268
7269         ret = drm_vblank_get(dev, intel_crtc->pipe);
7270         if (ret)
7271                 goto free_work;
7272
7273         /* We borrow the event spin lock for protecting unpin_work */
7274         spin_lock_irqsave(&dev->event_lock, flags);
7275         if (intel_crtc->unpin_work) {
7276                 spin_unlock_irqrestore(&dev->event_lock, flags);
7277                 kfree(work);
7278                 drm_vblank_put(dev, intel_crtc->pipe);
7279
7280                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7281                 return -EBUSY;
7282         }
7283         intel_crtc->unpin_work = work;
7284         spin_unlock_irqrestore(&dev->event_lock, flags);
7285
7286         intel_fb = to_intel_framebuffer(fb);
7287         obj = intel_fb->obj;
7288
7289         ret = i915_mutex_lock_interruptible(dev);
7290         if (ret)
7291                 goto cleanup;
7292
7293         /* Reference the objects for the scheduled work. */
7294         drm_gem_object_reference(&work->old_fb_obj->base);
7295         drm_gem_object_reference(&obj->base);
7296
7297         crtc->fb = fb;
7298
7299         work->pending_flip_obj = obj;
7300
7301         work->enable_stall_check = true;
7302
7303         /* Block clients from rendering to the new back buffer until
7304          * the flip occurs and the object is no longer visible.
7305          */
7306         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7307
7308         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7309         if (ret)
7310                 goto cleanup_pending;
7311
7312         intel_disable_fbc(dev);
7313         intel_mark_fb_busy(obj);
7314         mutex_unlock(&dev->struct_mutex);
7315
7316         trace_i915_flip_request(intel_crtc->plane, obj);
7317
7318         return 0;
7319
7320 cleanup_pending:
7321         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7322         drm_gem_object_unreference(&work->old_fb_obj->base);
7323         drm_gem_object_unreference(&obj->base);
7324         mutex_unlock(&dev->struct_mutex);
7325
7326 cleanup:
7327         spin_lock_irqsave(&dev->event_lock, flags);
7328         intel_crtc->unpin_work = NULL;
7329         spin_unlock_irqrestore(&dev->event_lock, flags);
7330
7331         drm_vblank_put(dev, intel_crtc->pipe);
7332 free_work:
7333         kfree(work);
7334
7335         return ret;
7336 }
7337
7338 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7339         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7340         .load_lut = intel_crtc_load_lut,
7341         .disable = intel_crtc_noop,
7342 };
7343
7344 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7345 {
7346         struct intel_encoder *other_encoder;
7347         struct drm_crtc *crtc = &encoder->new_crtc->base;
7348
7349         if (WARN_ON(!crtc))
7350                 return false;
7351
7352         list_for_each_entry(other_encoder,
7353                             &crtc->dev->mode_config.encoder_list,
7354                             base.head) {
7355
7356                 if (&other_encoder->new_crtc->base != crtc ||
7357                     encoder == other_encoder)
7358                         continue;
7359                 else
7360                         return true;
7361         }
7362
7363         return false;
7364 }
7365
7366 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7367                                   struct drm_crtc *crtc)
7368 {
7369         struct drm_device *dev;
7370         struct drm_crtc *tmp;
7371         int crtc_mask = 1;
7372
7373         WARN(!crtc, "checking null crtc?\n");
7374
7375         dev = crtc->dev;
7376
7377         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7378                 if (tmp == crtc)
7379                         break;
7380                 crtc_mask <<= 1;
7381         }
7382
7383         if (encoder->possible_crtcs & crtc_mask)
7384                 return true;
7385         return false;
7386 }
7387
7388 /**
7389  * intel_modeset_update_staged_output_state
7390  *
7391  * Updates the staged output configuration state, e.g. after we've read out the
7392  * current hw state.
7393  */
7394 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7395 {
7396         struct intel_encoder *encoder;
7397         struct intel_connector *connector;
7398
7399         list_for_each_entry(connector, &dev->mode_config.connector_list,
7400                             base.head) {
7401                 connector->new_encoder =
7402                         to_intel_encoder(connector->base.encoder);
7403         }
7404
7405         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7406                             base.head) {
7407                 encoder->new_crtc =
7408                         to_intel_crtc(encoder->base.crtc);
7409         }
7410 }
7411
7412 /**
7413  * intel_modeset_commit_output_state
7414  *
7415  * This function copies the stage display pipe configuration to the real one.
7416  */
7417 static void intel_modeset_commit_output_state(struct drm_device *dev)
7418 {
7419         struct intel_encoder *encoder;
7420         struct intel_connector *connector;
7421
7422         list_for_each_entry(connector, &dev->mode_config.connector_list,
7423                             base.head) {
7424                 connector->base.encoder = &connector->new_encoder->base;
7425         }
7426
7427         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7428                             base.head) {
7429                 encoder->base.crtc = &encoder->new_crtc->base;
7430         }
7431 }
7432
7433 static struct drm_display_mode *
7434 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7435                             struct drm_display_mode *mode)
7436 {
7437         struct drm_device *dev = crtc->dev;
7438         struct drm_display_mode *adjusted_mode;
7439         struct drm_encoder_helper_funcs *encoder_funcs;
7440         struct intel_encoder *encoder;
7441
7442         adjusted_mode = drm_mode_duplicate(dev, mode);
7443         if (!adjusted_mode)
7444                 return ERR_PTR(-ENOMEM);
7445
7446         /* Pass our mode to the connectors and the CRTC to give them a chance to
7447          * adjust it according to limitations or connector properties, and also
7448          * a chance to reject the mode entirely.
7449          */
7450         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7451                             base.head) {
7452
7453                 if (&encoder->new_crtc->base != crtc)
7454                         continue;
7455                 encoder_funcs = encoder->base.helper_private;
7456                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7457                                                 adjusted_mode))) {
7458                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7459                         goto fail;
7460                 }
7461         }
7462
7463         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7464                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7465                 goto fail;
7466         }
7467         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7468
7469         return adjusted_mode;
7470 fail:
7471         drm_mode_destroy(dev, adjusted_mode);
7472         return ERR_PTR(-EINVAL);
7473 }
7474
7475 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7476  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7477 static void
7478 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7479                              unsigned *prepare_pipes, unsigned *disable_pipes)
7480 {
7481         struct intel_crtc *intel_crtc;
7482         struct drm_device *dev = crtc->dev;
7483         struct intel_encoder *encoder;
7484         struct intel_connector *connector;
7485         struct drm_crtc *tmp_crtc;
7486
7487         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7488
7489         /* Check which crtcs have changed outputs connected to them, these need
7490          * to be part of the prepare_pipes mask. We don't (yet) support global
7491          * modeset across multiple crtcs, so modeset_pipes will only have one
7492          * bit set at most. */
7493         list_for_each_entry(connector, &dev->mode_config.connector_list,
7494                             base.head) {
7495                 if (connector->base.encoder == &connector->new_encoder->base)
7496                         continue;
7497
7498                 if (connector->base.encoder) {
7499                         tmp_crtc = connector->base.encoder->crtc;
7500
7501                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7502                 }
7503
7504                 if (connector->new_encoder)
7505                         *prepare_pipes |=
7506                                 1 << connector->new_encoder->new_crtc->pipe;
7507         }
7508
7509         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7510                             base.head) {
7511                 if (encoder->base.crtc == &encoder->new_crtc->base)
7512                         continue;
7513
7514                 if (encoder->base.crtc) {
7515                         tmp_crtc = encoder->base.crtc;
7516
7517                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7518                 }
7519
7520                 if (encoder->new_crtc)
7521                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7522         }
7523
7524         /* Check for any pipes that will be fully disabled ... */
7525         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7526                             base.head) {
7527                 bool used = false;
7528
7529                 /* Don't try to disable disabled crtcs. */
7530                 if (!intel_crtc->base.enabled)
7531                         continue;
7532
7533                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7534                                     base.head) {
7535                         if (encoder->new_crtc == intel_crtc)
7536                                 used = true;
7537                 }
7538
7539                 if (!used)
7540                         *disable_pipes |= 1 << intel_crtc->pipe;
7541         }
7542
7543
7544         /* set_mode is also used to update properties on life display pipes. */
7545         intel_crtc = to_intel_crtc(crtc);
7546         if (crtc->enabled)
7547                 *prepare_pipes |= 1 << intel_crtc->pipe;
7548
7549         /* We only support modeset on one single crtc, hence we need to do that
7550          * only for the passed in crtc iff we change anything else than just
7551          * disable crtcs.
7552          *
7553          * This is actually not true, to be fully compatible with the old crtc
7554          * helper we automatically disable _any_ output (i.e. doesn't need to be
7555          * connected to the crtc we're modesetting on) if it's disconnected.
7556          * Which is a rather nutty api (since changed the output configuration
7557          * without userspace's explicit request can lead to confusion), but
7558          * alas. Hence we currently need to modeset on all pipes we prepare. */
7559         if (*prepare_pipes)
7560                 *modeset_pipes = *prepare_pipes;
7561
7562         /* ... and mask these out. */
7563         *modeset_pipes &= ~(*disable_pipes);
7564         *prepare_pipes &= ~(*disable_pipes);
7565 }
7566
7567 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7568 {
7569         struct drm_encoder *encoder;
7570         struct drm_device *dev = crtc->dev;
7571
7572         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7573                 if (encoder->crtc == crtc)
7574                         return true;
7575
7576         return false;
7577 }
7578
7579 static void
7580 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7581 {
7582         struct intel_encoder *intel_encoder;
7583         struct intel_crtc *intel_crtc;
7584         struct drm_connector *connector;
7585
7586         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7587                             base.head) {
7588                 if (!intel_encoder->base.crtc)
7589                         continue;
7590
7591                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7592
7593                 if (prepare_pipes & (1 << intel_crtc->pipe))
7594                         intel_encoder->connectors_active = false;
7595         }
7596
7597         intel_modeset_commit_output_state(dev);
7598
7599         /* Update computed state. */
7600         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7601                             base.head) {
7602                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7603         }
7604
7605         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7606                 if (!connector->encoder || !connector->encoder->crtc)
7607                         continue;
7608
7609                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7610
7611                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7612                         struct drm_property *dpms_property =
7613                                 dev->mode_config.dpms_property;
7614
7615                         connector->dpms = DRM_MODE_DPMS_ON;
7616                         drm_connector_property_set_value(connector,
7617                                                          dpms_property,
7618                                                          DRM_MODE_DPMS_ON);
7619
7620                         intel_encoder = to_intel_encoder(connector->encoder);
7621                         intel_encoder->connectors_active = true;
7622                 }
7623         }
7624
7625 }
7626
7627 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7628         list_for_each_entry((intel_crtc), \
7629                             &(dev)->mode_config.crtc_list, \
7630                             base.head) \
7631                 if (mask & (1 <<(intel_crtc)->pipe)) \
7632
7633 void
7634 intel_modeset_check_state(struct drm_device *dev)
7635 {
7636         struct intel_crtc *crtc;
7637         struct intel_encoder *encoder;
7638         struct intel_connector *connector;
7639
7640         list_for_each_entry(connector, &dev->mode_config.connector_list,
7641                             base.head) {
7642                 /* This also checks the encoder/connector hw state with the
7643                  * ->get_hw_state callbacks. */
7644                 intel_connector_check_state(connector);
7645
7646                 WARN(&connector->new_encoder->base != connector->base.encoder,
7647                      "connector's staged encoder doesn't match current encoder\n");
7648         }
7649
7650         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7651                             base.head) {
7652                 bool enabled = false;
7653                 bool active = false;
7654                 enum pipe pipe, tracked_pipe;
7655
7656                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7657                               encoder->base.base.id,
7658                               drm_get_encoder_name(&encoder->base));
7659
7660                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7661                      "encoder's stage crtc doesn't match current crtc\n");
7662                 WARN(encoder->connectors_active && !encoder->base.crtc,
7663                      "encoder's active_connectors set, but no crtc\n");
7664
7665                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7666                                     base.head) {
7667                         if (connector->base.encoder != &encoder->base)
7668                                 continue;
7669                         enabled = true;
7670                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7671                                 active = true;
7672                 }
7673                 WARN(!!encoder->base.crtc != enabled,
7674                      "encoder's enabled state mismatch "
7675                      "(expected %i, found %i)\n",
7676                      !!encoder->base.crtc, enabled);
7677                 WARN(active && !encoder->base.crtc,
7678                      "active encoder with no crtc\n");
7679
7680                 WARN(encoder->connectors_active != active,
7681                      "encoder's computed active state doesn't match tracked active state "
7682                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7683
7684                 active = encoder->get_hw_state(encoder, &pipe);
7685                 WARN(active != encoder->connectors_active,
7686                      "encoder's hw state doesn't match sw tracking "
7687                      "(expected %i, found %i)\n",
7688                      encoder->connectors_active, active);
7689
7690                 if (!encoder->base.crtc)
7691                         continue;
7692
7693                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7694                 WARN(active && pipe != tracked_pipe,
7695                      "active encoder's pipe doesn't match"
7696                      "(expected %i, found %i)\n",
7697                      tracked_pipe, pipe);
7698
7699         }
7700
7701         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7702                             base.head) {
7703                 bool enabled = false;
7704                 bool active = false;
7705
7706                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7707                               crtc->base.base.id);
7708
7709                 WARN(crtc->active && !crtc->base.enabled,
7710                      "active crtc, but not enabled in sw tracking\n");
7711
7712                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7713                                     base.head) {
7714                         if (encoder->base.crtc != &crtc->base)
7715                                 continue;
7716                         enabled = true;
7717                         if (encoder->connectors_active)
7718                                 active = true;
7719                 }
7720                 WARN(active != crtc->active,
7721                      "crtc's computed active state doesn't match tracked active state "
7722                      "(expected %i, found %i)\n", active, crtc->active);
7723                 WARN(enabled != crtc->base.enabled,
7724                      "crtc's computed enabled state doesn't match tracked enabled state "
7725                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7726
7727                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7728         }
7729 }
7730
7731 bool intel_set_mode(struct drm_crtc *crtc,
7732                     struct drm_display_mode *mode,
7733                     int x, int y, struct drm_framebuffer *fb)
7734 {
7735         struct drm_device *dev = crtc->dev;
7736         drm_i915_private_t *dev_priv = dev->dev_private;
7737         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7738         struct intel_crtc *intel_crtc;
7739         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7740         bool ret = true;
7741
7742         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7743                                      &prepare_pipes, &disable_pipes);
7744
7745         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7746                       modeset_pipes, prepare_pipes, disable_pipes);
7747
7748         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7749                 intel_crtc_disable(&intel_crtc->base);
7750
7751         saved_hwmode = crtc->hwmode;
7752         saved_mode = crtc->mode;
7753
7754         /* Hack: Because we don't (yet) support global modeset on multiple
7755          * crtcs, we don't keep track of the new mode for more than one crtc.
7756          * Hence simply check whether any bit is set in modeset_pipes in all the
7757          * pieces of code that are not yet converted to deal with mutliple crtcs
7758          * changing their mode at the same time. */
7759         adjusted_mode = NULL;
7760         if (modeset_pipes) {
7761                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7762                 if (IS_ERR(adjusted_mode)) {
7763                         return false;
7764                 }
7765         }
7766
7767         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7768                 if (intel_crtc->base.enabled)
7769                         dev_priv->display.crtc_disable(&intel_crtc->base);
7770         }
7771
7772         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7773          * to set it here already despite that we pass it down the callchain.
7774          */
7775         if (modeset_pipes)
7776                 crtc->mode = *mode;
7777
7778         /* Only after disabling all output pipelines that will be changed can we
7779          * update the the output configuration. */
7780         intel_modeset_update_state(dev, prepare_pipes);
7781
7782         if (dev_priv->display.modeset_global_resources)
7783                 dev_priv->display.modeset_global_resources(dev);
7784
7785         /* Set up the DPLL and any encoders state that needs to adjust or depend
7786          * on the DPLL.
7787          */
7788         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7789                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7790                                            mode, adjusted_mode,
7791                                            x, y, fb);
7792                 if (!ret)
7793                     goto done;
7794         }
7795
7796         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7797         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7798                 dev_priv->display.crtc_enable(&intel_crtc->base);
7799
7800         if (modeset_pipes) {
7801                 /* Store real post-adjustment hardware mode. */
7802                 crtc->hwmode = *adjusted_mode;
7803
7804                 /* Calculate and store various constants which
7805                  * are later needed by vblank and swap-completion
7806                  * timestamping. They are derived from true hwmode.
7807                  */
7808                 drm_calc_timestamping_constants(crtc);
7809         }
7810
7811         /* FIXME: add subpixel order */
7812 done:
7813         drm_mode_destroy(dev, adjusted_mode);
7814         if (!ret && crtc->enabled) {
7815                 crtc->hwmode = saved_hwmode;
7816                 crtc->mode = saved_mode;
7817         } else {
7818                 intel_modeset_check_state(dev);
7819         }
7820
7821         return ret;
7822 }
7823
7824 #undef for_each_intel_crtc_masked
7825
7826 static void intel_set_config_free(struct intel_set_config *config)
7827 {
7828         if (!config)
7829                 return;
7830
7831         kfree(config->save_connector_encoders);
7832         kfree(config->save_encoder_crtcs);
7833         kfree(config);
7834 }
7835
7836 static int intel_set_config_save_state(struct drm_device *dev,
7837                                        struct intel_set_config *config)
7838 {
7839         struct drm_encoder *encoder;
7840         struct drm_connector *connector;
7841         int count;
7842
7843         config->save_encoder_crtcs =
7844                 kcalloc(dev->mode_config.num_encoder,
7845                         sizeof(struct drm_crtc *), GFP_KERNEL);
7846         if (!config->save_encoder_crtcs)
7847                 return -ENOMEM;
7848
7849         config->save_connector_encoders =
7850                 kcalloc(dev->mode_config.num_connector,
7851                         sizeof(struct drm_encoder *), GFP_KERNEL);
7852         if (!config->save_connector_encoders)
7853                 return -ENOMEM;
7854
7855         /* Copy data. Note that driver private data is not affected.
7856          * Should anything bad happen only the expected state is
7857          * restored, not the drivers personal bookkeeping.
7858          */
7859         count = 0;
7860         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7861                 config->save_encoder_crtcs[count++] = encoder->crtc;
7862         }
7863
7864         count = 0;
7865         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7866                 config->save_connector_encoders[count++] = connector->encoder;
7867         }
7868
7869         return 0;
7870 }
7871
7872 static void intel_set_config_restore_state(struct drm_device *dev,
7873                                            struct intel_set_config *config)
7874 {
7875         struct intel_encoder *encoder;
7876         struct intel_connector *connector;
7877         int count;
7878
7879         count = 0;
7880         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7881                 encoder->new_crtc =
7882                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7883         }
7884
7885         count = 0;
7886         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7887                 connector->new_encoder =
7888                         to_intel_encoder(config->save_connector_encoders[count++]);
7889         }
7890 }
7891
7892 static void
7893 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7894                                       struct intel_set_config *config)
7895 {
7896
7897         /* We should be able to check here if the fb has the same properties
7898          * and then just flip_or_move it */
7899         if (set->crtc->fb != set->fb) {
7900                 /* If we have no fb then treat it as a full mode set */
7901                 if (set->crtc->fb == NULL) {
7902                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7903                         config->mode_changed = true;
7904                 } else if (set->fb == NULL) {
7905                         config->mode_changed = true;
7906                 } else if (set->fb->depth != set->crtc->fb->depth) {
7907                         config->mode_changed = true;
7908                 } else if (set->fb->bits_per_pixel !=
7909                            set->crtc->fb->bits_per_pixel) {
7910                         config->mode_changed = true;
7911                 } else
7912                         config->fb_changed = true;
7913         }
7914
7915         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7916                 config->fb_changed = true;
7917
7918         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7919                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7920                 drm_mode_debug_printmodeline(&set->crtc->mode);
7921                 drm_mode_debug_printmodeline(set->mode);
7922                 config->mode_changed = true;
7923         }
7924 }
7925
7926 static int
7927 intel_modeset_stage_output_state(struct drm_device *dev,
7928                                  struct drm_mode_set *set,
7929                                  struct intel_set_config *config)
7930 {
7931         struct drm_crtc *new_crtc;
7932         struct intel_connector *connector;
7933         struct intel_encoder *encoder;
7934         int count, ro;
7935
7936         /* The upper layers ensure that we either disabl a crtc or have a list
7937          * of connectors. For paranoia, double-check this. */
7938         WARN_ON(!set->fb && (set->num_connectors != 0));
7939         WARN_ON(set->fb && (set->num_connectors == 0));
7940
7941         count = 0;
7942         list_for_each_entry(connector, &dev->mode_config.connector_list,
7943                             base.head) {
7944                 /* Otherwise traverse passed in connector list and get encoders
7945                  * for them. */
7946                 for (ro = 0; ro < set->num_connectors; ro++) {
7947                         if (set->connectors[ro] == &connector->base) {
7948                                 connector->new_encoder = connector->encoder;
7949                                 break;
7950                         }
7951                 }
7952
7953                 /* If we disable the crtc, disable all its connectors. Also, if
7954                  * the connector is on the changing crtc but not on the new
7955                  * connector list, disable it. */
7956                 if ((!set->fb || ro == set->num_connectors) &&
7957                     connector->base.encoder &&
7958                     connector->base.encoder->crtc == set->crtc) {
7959                         connector->new_encoder = NULL;
7960
7961                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7962                                 connector->base.base.id,
7963                                 drm_get_connector_name(&connector->base));
7964                 }
7965
7966
7967                 if (&connector->new_encoder->base != connector->base.encoder) {
7968                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7969                         config->mode_changed = true;
7970                 }
7971
7972                 /* Disable all disconnected encoders. */
7973                 if (connector->base.status == connector_status_disconnected)
7974                         connector->new_encoder = NULL;
7975         }
7976         /* connector->new_encoder is now updated for all connectors. */
7977
7978         /* Update crtc of enabled connectors. */
7979         count = 0;
7980         list_for_each_entry(connector, &dev->mode_config.connector_list,
7981                             base.head) {
7982                 if (!connector->new_encoder)
7983                         continue;
7984
7985                 new_crtc = connector->new_encoder->base.crtc;
7986
7987                 for (ro = 0; ro < set->num_connectors; ro++) {
7988                         if (set->connectors[ro] == &connector->base)
7989                                 new_crtc = set->crtc;
7990                 }
7991
7992                 /* Make sure the new CRTC will work with the encoder */
7993                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7994                                            new_crtc)) {
7995                         return -EINVAL;
7996                 }
7997                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7998
7999                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8000                         connector->base.base.id,
8001                         drm_get_connector_name(&connector->base),
8002                         new_crtc->base.id);
8003         }
8004
8005         /* Check for any encoders that needs to be disabled. */
8006         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8007                             base.head) {
8008                 list_for_each_entry(connector,
8009                                     &dev->mode_config.connector_list,
8010                                     base.head) {
8011                         if (connector->new_encoder == encoder) {
8012                                 WARN_ON(!connector->new_encoder->new_crtc);
8013
8014                                 goto next_encoder;
8015                         }
8016                 }
8017                 encoder->new_crtc = NULL;
8018 next_encoder:
8019                 /* Only now check for crtc changes so we don't miss encoders
8020                  * that will be disabled. */
8021                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8022                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8023                         config->mode_changed = true;
8024                 }
8025         }
8026         /* Now we've also updated encoder->new_crtc for all encoders. */
8027
8028         return 0;
8029 }
8030
8031 static int intel_crtc_set_config(struct drm_mode_set *set)
8032 {
8033         struct drm_device *dev;
8034         struct drm_mode_set save_set;
8035         struct intel_set_config *config;
8036         int ret;
8037
8038         BUG_ON(!set);
8039         BUG_ON(!set->crtc);
8040         BUG_ON(!set->crtc->helper_private);
8041
8042         if (!set->mode)
8043                 set->fb = NULL;
8044
8045         /* The fb helper likes to play gross jokes with ->mode_set_config.
8046          * Unfortunately the crtc helper doesn't do much at all for this case,
8047          * so we have to cope with this madness until the fb helper is fixed up. */
8048         if (set->fb && set->num_connectors == 0)
8049                 return 0;
8050
8051         if (set->fb) {
8052                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8053                                 set->crtc->base.id, set->fb->base.id,
8054                                 (int)set->num_connectors, set->x, set->y);
8055         } else {
8056                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8057         }
8058
8059         dev = set->crtc->dev;
8060
8061         ret = -ENOMEM;
8062         config = kzalloc(sizeof(*config), GFP_KERNEL);
8063         if (!config)
8064                 goto out_config;
8065
8066         ret = intel_set_config_save_state(dev, config);
8067         if (ret)
8068                 goto out_config;
8069
8070         save_set.crtc = set->crtc;
8071         save_set.mode = &set->crtc->mode;
8072         save_set.x = set->crtc->x;
8073         save_set.y = set->crtc->y;
8074         save_set.fb = set->crtc->fb;
8075
8076         /* Compute whether we need a full modeset, only an fb base update or no
8077          * change at all. In the future we might also check whether only the
8078          * mode changed, e.g. for LVDS where we only change the panel fitter in
8079          * such cases. */
8080         intel_set_config_compute_mode_changes(set, config);
8081
8082         ret = intel_modeset_stage_output_state(dev, set, config);
8083         if (ret)
8084                 goto fail;
8085
8086         if (config->mode_changed) {
8087                 if (set->mode) {
8088                         DRM_DEBUG_KMS("attempting to set mode from"
8089                                         " userspace\n");
8090                         drm_mode_debug_printmodeline(set->mode);
8091                 }
8092
8093                 if (!intel_set_mode(set->crtc, set->mode,
8094                                     set->x, set->y, set->fb)) {
8095                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8096                                   set->crtc->base.id);
8097                         ret = -EINVAL;
8098                         goto fail;
8099                 }
8100         } else if (config->fb_changed) {
8101                 ret = intel_pipe_set_base(set->crtc,
8102                                           set->x, set->y, set->fb);
8103         }
8104
8105         intel_set_config_free(config);
8106
8107         return 0;
8108
8109 fail:
8110         intel_set_config_restore_state(dev, config);
8111
8112         /* Try to restore the config */
8113         if (config->mode_changed &&
8114             !intel_set_mode(save_set.crtc, save_set.mode,
8115                             save_set.x, save_set.y, save_set.fb))
8116                 DRM_ERROR("failed to restore config after modeset failure\n");
8117
8118 out_config:
8119         intel_set_config_free(config);
8120         return ret;
8121 }
8122
8123 static const struct drm_crtc_funcs intel_crtc_funcs = {
8124         .cursor_set = intel_crtc_cursor_set,
8125         .cursor_move = intel_crtc_cursor_move,
8126         .gamma_set = intel_crtc_gamma_set,
8127         .set_config = intel_crtc_set_config,
8128         .destroy = intel_crtc_destroy,
8129         .page_flip = intel_crtc_page_flip,
8130 };
8131
8132 static void intel_cpu_pll_init(struct drm_device *dev)
8133 {
8134         if (IS_HASWELL(dev))
8135                 intel_ddi_pll_init(dev);
8136 }
8137
8138 static void intel_pch_pll_init(struct drm_device *dev)
8139 {
8140         drm_i915_private_t *dev_priv = dev->dev_private;
8141         int i;
8142
8143         if (dev_priv->num_pch_pll == 0) {
8144                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8145                 return;
8146         }
8147
8148         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8149                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8150                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8151                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8152         }
8153 }
8154
8155 static void intel_crtc_init(struct drm_device *dev, int pipe)
8156 {
8157         drm_i915_private_t *dev_priv = dev->dev_private;
8158         struct intel_crtc *intel_crtc;
8159         int i;
8160
8161         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8162         if (intel_crtc == NULL)
8163                 return;
8164
8165         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8166
8167         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8168         for (i = 0; i < 256; i++) {
8169                 intel_crtc->lut_r[i] = i;
8170                 intel_crtc->lut_g[i] = i;
8171                 intel_crtc->lut_b[i] = i;
8172         }
8173
8174         /* Swap pipes & planes for FBC on pre-965 */
8175         intel_crtc->pipe = pipe;
8176         intel_crtc->plane = pipe;
8177         intel_crtc->cpu_transcoder = pipe;
8178         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8179                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8180                 intel_crtc->plane = !pipe;
8181         }
8182
8183         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8184                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8185         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8186         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8187
8188         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8189
8190         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8191 }
8192
8193 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8194                                 struct drm_file *file)
8195 {
8196         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8197         struct drm_mode_object *drmmode_obj;
8198         struct intel_crtc *crtc;
8199
8200         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8201                 return -ENODEV;
8202
8203         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8204                         DRM_MODE_OBJECT_CRTC);
8205
8206         if (!drmmode_obj) {
8207                 DRM_ERROR("no such CRTC id\n");
8208                 return -EINVAL;
8209         }
8210
8211         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8212         pipe_from_crtc_id->pipe = crtc->pipe;
8213
8214         return 0;
8215 }
8216
8217 static int intel_encoder_clones(struct intel_encoder *encoder)
8218 {
8219         struct drm_device *dev = encoder->base.dev;
8220         struct intel_encoder *source_encoder;
8221         int index_mask = 0;
8222         int entry = 0;
8223
8224         list_for_each_entry(source_encoder,
8225                             &dev->mode_config.encoder_list, base.head) {
8226
8227                 if (encoder == source_encoder)
8228                         index_mask |= (1 << entry);
8229
8230                 /* Intel hw has only one MUX where enocoders could be cloned. */
8231                 if (encoder->cloneable && source_encoder->cloneable)
8232                         index_mask |= (1 << entry);
8233
8234                 entry++;
8235         }
8236
8237         return index_mask;
8238 }
8239
8240 static bool has_edp_a(struct drm_device *dev)
8241 {
8242         struct drm_i915_private *dev_priv = dev->dev_private;
8243
8244         if (!IS_MOBILE(dev))
8245                 return false;
8246
8247         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8248                 return false;
8249
8250         if (IS_GEN5(dev) &&
8251             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8252                 return false;
8253
8254         return true;
8255 }
8256
8257 static void intel_setup_outputs(struct drm_device *dev)
8258 {
8259         struct drm_i915_private *dev_priv = dev->dev_private;
8260         struct intel_encoder *encoder;
8261         bool dpd_is_edp = false;
8262         bool has_lvds;
8263
8264         has_lvds = intel_lvds_init(dev);
8265         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8266                 /* disable the panel fitter on everything but LVDS */
8267                 I915_WRITE(PFIT_CONTROL, 0);
8268         }
8269
8270         if (HAS_PCH_SPLIT(dev)) {
8271                 dpd_is_edp = intel_dpd_is_edp(dev);
8272
8273                 if (has_edp_a(dev))
8274                         intel_dp_init(dev, DP_A, PORT_A);
8275
8276                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8277                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8278         }
8279
8280         intel_crt_init(dev);
8281
8282         if (IS_HASWELL(dev)) {
8283                 int found;
8284
8285                 /* Haswell uses DDI functions to detect digital outputs */
8286                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8287                 /* DDI A only supports eDP */
8288                 if (found)
8289                         intel_ddi_init(dev, PORT_A);
8290
8291                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8292                  * register */
8293                 found = I915_READ(SFUSE_STRAP);
8294
8295                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8296                         intel_ddi_init(dev, PORT_B);
8297                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8298                         intel_ddi_init(dev, PORT_C);
8299                 if (found & SFUSE_STRAP_DDID_DETECTED)
8300                         intel_ddi_init(dev, PORT_D);
8301         } else if (HAS_PCH_SPLIT(dev)) {
8302                 int found;
8303
8304                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8305                         /* PCH SDVOB multiplex with HDMIB */
8306                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8307                         if (!found)
8308                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8309                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8310                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8311                 }
8312
8313                 if (I915_READ(HDMIC) & PORT_DETECTED)
8314                         intel_hdmi_init(dev, HDMIC, PORT_C);
8315
8316                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8317                         intel_hdmi_init(dev, HDMID, PORT_D);
8318
8319                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8320                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8321
8322                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8323                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8324         } else if (IS_VALLEYVIEW(dev)) {
8325                 int found;
8326
8327                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8328                 if (I915_READ(DP_C) & DP_DETECTED)
8329                         intel_dp_init(dev, DP_C, PORT_C);
8330
8331                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8332                         /* SDVOB multiplex with HDMIB */
8333                         found = intel_sdvo_init(dev, SDVOB, true);
8334                         if (!found)
8335                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8336                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8337                                 intel_dp_init(dev, DP_B, PORT_B);
8338                 }
8339
8340                 if (I915_READ(SDVOC) & PORT_DETECTED)
8341                         intel_hdmi_init(dev, SDVOC, PORT_C);
8342
8343         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8344                 bool found = false;
8345
8346                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8347                         DRM_DEBUG_KMS("probing SDVOB\n");
8348                         found = intel_sdvo_init(dev, SDVOB, true);
8349                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8350                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8351                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8352                         }
8353
8354                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8355                                 DRM_DEBUG_KMS("probing DP_B\n");
8356                                 intel_dp_init(dev, DP_B, PORT_B);
8357                         }
8358                 }
8359
8360                 /* Before G4X SDVOC doesn't have its own detect register */
8361
8362                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8363                         DRM_DEBUG_KMS("probing SDVOC\n");
8364                         found = intel_sdvo_init(dev, SDVOC, false);
8365                 }
8366
8367                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8368
8369                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8370                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8371                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8372                         }
8373                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8374                                 DRM_DEBUG_KMS("probing DP_C\n");
8375                                 intel_dp_init(dev, DP_C, PORT_C);
8376                         }
8377                 }
8378
8379                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8380                     (I915_READ(DP_D) & DP_DETECTED)) {
8381                         DRM_DEBUG_KMS("probing DP_D\n");
8382                         intel_dp_init(dev, DP_D, PORT_D);
8383                 }
8384         } else if (IS_GEN2(dev))
8385                 intel_dvo_init(dev);
8386
8387         if (SUPPORTS_TV(dev))
8388                 intel_tv_init(dev);
8389
8390         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8391                 encoder->base.possible_crtcs = encoder->crtc_mask;
8392                 encoder->base.possible_clones =
8393                         intel_encoder_clones(encoder);
8394         }
8395
8396         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8397                 ironlake_init_pch_refclk(dev);
8398 }
8399
8400 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8401 {
8402         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8403
8404         drm_framebuffer_cleanup(fb);
8405         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8406
8407         kfree(intel_fb);
8408 }
8409
8410 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8411                                                 struct drm_file *file,
8412                                                 unsigned int *handle)
8413 {
8414         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8415         struct drm_i915_gem_object *obj = intel_fb->obj;
8416
8417         return drm_gem_handle_create(file, &obj->base, handle);
8418 }
8419
8420 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8421         .destroy = intel_user_framebuffer_destroy,
8422         .create_handle = intel_user_framebuffer_create_handle,
8423 };
8424
8425 int intel_framebuffer_init(struct drm_device *dev,
8426                            struct intel_framebuffer *intel_fb,
8427                            struct drm_mode_fb_cmd2 *mode_cmd,
8428                            struct drm_i915_gem_object *obj)
8429 {
8430         int ret;
8431
8432         if (obj->tiling_mode == I915_TILING_Y)
8433                 return -EINVAL;
8434
8435         if (mode_cmd->pitches[0] & 63)
8436                 return -EINVAL;
8437
8438         /* FIXME <= Gen4 stride limits are bit unclear */
8439         if (mode_cmd->pitches[0] > 32768)
8440                 return -EINVAL;
8441
8442         if (obj->tiling_mode != I915_TILING_NONE &&
8443             mode_cmd->pitches[0] != obj->stride)
8444                 return -EINVAL;
8445
8446         /* Reject formats not supported by any plane early. */
8447         switch (mode_cmd->pixel_format) {
8448         case DRM_FORMAT_C8:
8449         case DRM_FORMAT_RGB565:
8450         case DRM_FORMAT_XRGB8888:
8451         case DRM_FORMAT_ARGB8888:
8452                 break;
8453         case DRM_FORMAT_XRGB1555:
8454         case DRM_FORMAT_ARGB1555:
8455                 if (INTEL_INFO(dev)->gen > 3)
8456                         return -EINVAL;
8457                 break;
8458         case DRM_FORMAT_XBGR8888:
8459         case DRM_FORMAT_ABGR8888:
8460         case DRM_FORMAT_XRGB2101010:
8461         case DRM_FORMAT_ARGB2101010:
8462         case DRM_FORMAT_XBGR2101010:
8463         case DRM_FORMAT_ABGR2101010:
8464                 if (INTEL_INFO(dev)->gen < 4)
8465                         return -EINVAL;
8466                 break;
8467         case DRM_FORMAT_YUYV:
8468         case DRM_FORMAT_UYVY:
8469         case DRM_FORMAT_YVYU:
8470         case DRM_FORMAT_VYUY:
8471                 if (INTEL_INFO(dev)->gen < 6)
8472                         return -EINVAL;
8473                 break;
8474         default:
8475                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8476                 return -EINVAL;
8477         }
8478
8479         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8480         if (mode_cmd->offsets[0] != 0)
8481                 return -EINVAL;
8482
8483         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8484         if (ret) {
8485                 DRM_ERROR("framebuffer init failed %d\n", ret);
8486                 return ret;
8487         }
8488
8489         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8490         intel_fb->obj = obj;
8491         return 0;
8492 }
8493
8494 static struct drm_framebuffer *
8495 intel_user_framebuffer_create(struct drm_device *dev,
8496                               struct drm_file *filp,
8497                               struct drm_mode_fb_cmd2 *mode_cmd)
8498 {
8499         struct drm_i915_gem_object *obj;
8500
8501         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8502                                                 mode_cmd->handles[0]));
8503         if (&obj->base == NULL)
8504                 return ERR_PTR(-ENOENT);
8505
8506         return intel_framebuffer_create(dev, mode_cmd, obj);
8507 }
8508
8509 static const struct drm_mode_config_funcs intel_mode_funcs = {
8510         .fb_create = intel_user_framebuffer_create,
8511         .output_poll_changed = intel_fb_output_poll_changed,
8512 };
8513
8514 /* Set up chip specific display functions */
8515 static void intel_init_display(struct drm_device *dev)
8516 {
8517         struct drm_i915_private *dev_priv = dev->dev_private;
8518
8519         /* We always want a DPMS function */
8520         if (IS_HASWELL(dev)) {
8521                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8522                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8523                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8524                 dev_priv->display.off = haswell_crtc_off;
8525                 dev_priv->display.update_plane = ironlake_update_plane;
8526         } else if (HAS_PCH_SPLIT(dev)) {
8527                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8528                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8529                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8530                 dev_priv->display.off = ironlake_crtc_off;
8531                 dev_priv->display.update_plane = ironlake_update_plane;
8532         } else {
8533                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8534                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8535                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8536                 dev_priv->display.off = i9xx_crtc_off;
8537                 dev_priv->display.update_plane = i9xx_update_plane;
8538         }
8539
8540         /* Returns the core display clock speed */
8541         if (IS_VALLEYVIEW(dev))
8542                 dev_priv->display.get_display_clock_speed =
8543                         valleyview_get_display_clock_speed;
8544         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8545                 dev_priv->display.get_display_clock_speed =
8546                         i945_get_display_clock_speed;
8547         else if (IS_I915G(dev))
8548                 dev_priv->display.get_display_clock_speed =
8549                         i915_get_display_clock_speed;
8550         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8551                 dev_priv->display.get_display_clock_speed =
8552                         i9xx_misc_get_display_clock_speed;
8553         else if (IS_I915GM(dev))
8554                 dev_priv->display.get_display_clock_speed =
8555                         i915gm_get_display_clock_speed;
8556         else if (IS_I865G(dev))
8557                 dev_priv->display.get_display_clock_speed =
8558                         i865_get_display_clock_speed;
8559         else if (IS_I85X(dev))
8560                 dev_priv->display.get_display_clock_speed =
8561                         i855_get_display_clock_speed;
8562         else /* 852, 830 */
8563                 dev_priv->display.get_display_clock_speed =
8564                         i830_get_display_clock_speed;
8565
8566         if (HAS_PCH_SPLIT(dev)) {
8567                 if (IS_GEN5(dev)) {
8568                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8569                         dev_priv->display.write_eld = ironlake_write_eld;
8570                 } else if (IS_GEN6(dev)) {
8571                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8572                         dev_priv->display.write_eld = ironlake_write_eld;
8573                 } else if (IS_IVYBRIDGE(dev)) {
8574                         /* FIXME: detect B0+ stepping and use auto training */
8575                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8576                         dev_priv->display.write_eld = ironlake_write_eld;
8577                         dev_priv->display.modeset_global_resources =
8578                                 ivb_modeset_global_resources;
8579                 } else if (IS_HASWELL(dev)) {
8580                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8581                         dev_priv->display.write_eld = haswell_write_eld;
8582                 } else
8583                         dev_priv->display.update_wm = NULL;
8584         } else if (IS_G4X(dev)) {
8585                 dev_priv->display.write_eld = g4x_write_eld;
8586         }
8587
8588         /* Default just returns -ENODEV to indicate unsupported */
8589         dev_priv->display.queue_flip = intel_default_queue_flip;
8590
8591         switch (INTEL_INFO(dev)->gen) {
8592         case 2:
8593                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8594                 break;
8595
8596         case 3:
8597                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8598                 break;
8599
8600         case 4:
8601         case 5:
8602                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8603                 break;
8604
8605         case 6:
8606                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8607                 break;
8608         case 7:
8609                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8610                 break;
8611         }
8612 }
8613
8614 /*
8615  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8616  * resume, or other times.  This quirk makes sure that's the case for
8617  * affected systems.
8618  */
8619 static void quirk_pipea_force(struct drm_device *dev)
8620 {
8621         struct drm_i915_private *dev_priv = dev->dev_private;
8622
8623         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8624         DRM_INFO("applying pipe a force quirk\n");
8625 }
8626
8627 /*
8628  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8629  */
8630 static void quirk_ssc_force_disable(struct drm_device *dev)
8631 {
8632         struct drm_i915_private *dev_priv = dev->dev_private;
8633         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8634         DRM_INFO("applying lvds SSC disable quirk\n");
8635 }
8636
8637 /*
8638  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8639  * brightness value
8640  */
8641 static void quirk_invert_brightness(struct drm_device *dev)
8642 {
8643         struct drm_i915_private *dev_priv = dev->dev_private;
8644         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8645         DRM_INFO("applying inverted panel brightness quirk\n");
8646 }
8647
8648 struct intel_quirk {
8649         int device;
8650         int subsystem_vendor;
8651         int subsystem_device;
8652         void (*hook)(struct drm_device *dev);
8653 };
8654
8655 static struct intel_quirk intel_quirks[] = {
8656         /* HP Mini needs pipe A force quirk (LP: #322104) */
8657         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8658
8659         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8660         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8661
8662         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8663         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8664
8665         /* 830/845 need to leave pipe A & dpll A up */
8666         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8667         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8668
8669         /* Lenovo U160 cannot use SSC on LVDS */
8670         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8671
8672         /* Sony Vaio Y cannot use SSC on LVDS */
8673         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8674
8675         /* Acer Aspire 5734Z must invert backlight brightness */
8676         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8677 };
8678
8679 static void intel_init_quirks(struct drm_device *dev)
8680 {
8681         struct pci_dev *d = dev->pdev;
8682         int i;
8683
8684         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8685                 struct intel_quirk *q = &intel_quirks[i];
8686
8687                 if (d->device == q->device &&
8688                     (d->subsystem_vendor == q->subsystem_vendor ||
8689                      q->subsystem_vendor == PCI_ANY_ID) &&
8690                     (d->subsystem_device == q->subsystem_device ||
8691                      q->subsystem_device == PCI_ANY_ID))
8692                         q->hook(dev);
8693         }
8694 }
8695
8696 /* Disable the VGA plane that we never use */
8697 static void i915_disable_vga(struct drm_device *dev)
8698 {
8699         struct drm_i915_private *dev_priv = dev->dev_private;
8700         u8 sr1;
8701         u32 vga_reg;
8702
8703         if (HAS_PCH_SPLIT(dev))
8704                 vga_reg = CPU_VGACNTRL;
8705         else
8706                 vga_reg = VGACNTRL;
8707
8708         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8709         outb(SR01, VGA_SR_INDEX);
8710         sr1 = inb(VGA_SR_DATA);
8711         outb(sr1 | 1<<5, VGA_SR_DATA);
8712         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8713         udelay(300);
8714
8715         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8716         POSTING_READ(vga_reg);
8717 }
8718
8719 void intel_modeset_init_hw(struct drm_device *dev)
8720 {
8721         /* We attempt to init the necessary power wells early in the initialization
8722          * time, so the subsystems that expect power to be enabled can work.
8723          */
8724         intel_init_power_wells(dev);
8725
8726         intel_prepare_ddi(dev);
8727
8728         intel_init_clock_gating(dev);
8729
8730         mutex_lock(&dev->struct_mutex);
8731         intel_enable_gt_powersave(dev);
8732         mutex_unlock(&dev->struct_mutex);
8733 }
8734
8735 void intel_modeset_init(struct drm_device *dev)
8736 {
8737         struct drm_i915_private *dev_priv = dev->dev_private;
8738         int i, ret;
8739
8740         drm_mode_config_init(dev);
8741
8742         dev->mode_config.min_width = 0;
8743         dev->mode_config.min_height = 0;
8744
8745         dev->mode_config.preferred_depth = 24;
8746         dev->mode_config.prefer_shadow = 1;
8747
8748         dev->mode_config.funcs = &intel_mode_funcs;
8749
8750         intel_init_quirks(dev);
8751
8752         intel_init_pm(dev);
8753
8754         intel_init_display(dev);
8755
8756         if (IS_GEN2(dev)) {
8757                 dev->mode_config.max_width = 2048;
8758                 dev->mode_config.max_height = 2048;
8759         } else if (IS_GEN3(dev)) {
8760                 dev->mode_config.max_width = 4096;
8761                 dev->mode_config.max_height = 4096;
8762         } else {
8763                 dev->mode_config.max_width = 8192;
8764                 dev->mode_config.max_height = 8192;
8765         }
8766         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8767
8768         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8769                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8770
8771         for (i = 0; i < dev_priv->num_pipe; i++) {
8772                 intel_crtc_init(dev, i);
8773                 ret = intel_plane_init(dev, i);
8774                 if (ret)
8775                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8776         }
8777
8778         intel_cpu_pll_init(dev);
8779         intel_pch_pll_init(dev);
8780
8781         /* Just disable it once at startup */
8782         i915_disable_vga(dev);
8783         intel_setup_outputs(dev);
8784 }
8785
8786 static void
8787 intel_connector_break_all_links(struct intel_connector *connector)
8788 {
8789         connector->base.dpms = DRM_MODE_DPMS_OFF;
8790         connector->base.encoder = NULL;
8791         connector->encoder->connectors_active = false;
8792         connector->encoder->base.crtc = NULL;
8793 }
8794
8795 static void intel_enable_pipe_a(struct drm_device *dev)
8796 {
8797         struct intel_connector *connector;
8798         struct drm_connector *crt = NULL;
8799         struct intel_load_detect_pipe load_detect_temp;
8800
8801         /* We can't just switch on the pipe A, we need to set things up with a
8802          * proper mode and output configuration. As a gross hack, enable pipe A
8803          * by enabling the load detect pipe once. */
8804         list_for_each_entry(connector,
8805                             &dev->mode_config.connector_list,
8806                             base.head) {
8807                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8808                         crt = &connector->base;
8809                         break;
8810                 }
8811         }
8812
8813         if (!crt)
8814                 return;
8815
8816         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8817                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8818
8819
8820 }
8821
8822 static bool
8823 intel_check_plane_mapping(struct intel_crtc *crtc)
8824 {
8825         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8826         u32 reg, val;
8827
8828         if (dev_priv->num_pipe == 1)
8829                 return true;
8830
8831         reg = DSPCNTR(!crtc->plane);
8832         val = I915_READ(reg);
8833
8834         if ((val & DISPLAY_PLANE_ENABLE) &&
8835             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8836                 return false;
8837
8838         return true;
8839 }
8840
8841 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8842 {
8843         struct drm_device *dev = crtc->base.dev;
8844         struct drm_i915_private *dev_priv = dev->dev_private;
8845         u32 reg;
8846
8847         /* Clear any frame start delays used for debugging left by the BIOS */
8848         reg = PIPECONF(crtc->cpu_transcoder);
8849         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8850
8851         /* We need to sanitize the plane -> pipe mapping first because this will
8852          * disable the crtc (and hence change the state) if it is wrong. Note
8853          * that gen4+ has a fixed plane -> pipe mapping.  */
8854         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8855                 struct intel_connector *connector;
8856                 bool plane;
8857
8858                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8859                               crtc->base.base.id);
8860
8861                 /* Pipe has the wrong plane attached and the plane is active.
8862                  * Temporarily change the plane mapping and disable everything
8863                  * ...  */
8864                 plane = crtc->plane;
8865                 crtc->plane = !plane;
8866                 dev_priv->display.crtc_disable(&crtc->base);
8867                 crtc->plane = plane;
8868
8869                 /* ... and break all links. */
8870                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8871                                     base.head) {
8872                         if (connector->encoder->base.crtc != &crtc->base)
8873                                 continue;
8874
8875                         intel_connector_break_all_links(connector);
8876                 }
8877
8878                 WARN_ON(crtc->active);
8879                 crtc->base.enabled = false;
8880         }
8881
8882         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8883             crtc->pipe == PIPE_A && !crtc->active) {
8884                 /* BIOS forgot to enable pipe A, this mostly happens after
8885                  * resume. Force-enable the pipe to fix this, the update_dpms
8886                  * call below we restore the pipe to the right state, but leave
8887                  * the required bits on. */
8888                 intel_enable_pipe_a(dev);
8889         }
8890
8891         /* Adjust the state of the output pipe according to whether we
8892          * have active connectors/encoders. */
8893         intel_crtc_update_dpms(&crtc->base);
8894
8895         if (crtc->active != crtc->base.enabled) {
8896                 struct intel_encoder *encoder;
8897
8898                 /* This can happen either due to bugs in the get_hw_state
8899                  * functions or because the pipe is force-enabled due to the
8900                  * pipe A quirk. */
8901                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8902                               crtc->base.base.id,
8903                               crtc->base.enabled ? "enabled" : "disabled",
8904                               crtc->active ? "enabled" : "disabled");
8905
8906                 crtc->base.enabled = crtc->active;
8907
8908                 /* Because we only establish the connector -> encoder ->
8909                  * crtc links if something is active, this means the
8910                  * crtc is now deactivated. Break the links. connector
8911                  * -> encoder links are only establish when things are
8912                  *  actually up, hence no need to break them. */
8913                 WARN_ON(crtc->active);
8914
8915                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8916                         WARN_ON(encoder->connectors_active);
8917                         encoder->base.crtc = NULL;
8918                 }
8919         }
8920 }
8921
8922 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8923 {
8924         struct intel_connector *connector;
8925         struct drm_device *dev = encoder->base.dev;
8926
8927         /* We need to check both for a crtc link (meaning that the
8928          * encoder is active and trying to read from a pipe) and the
8929          * pipe itself being active. */
8930         bool has_active_crtc = encoder->base.crtc &&
8931                 to_intel_crtc(encoder->base.crtc)->active;
8932
8933         if (encoder->connectors_active && !has_active_crtc) {
8934                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8935                               encoder->base.base.id,
8936                               drm_get_encoder_name(&encoder->base));
8937
8938                 /* Connector is active, but has no active pipe. This is
8939                  * fallout from our resume register restoring. Disable
8940                  * the encoder manually again. */
8941                 if (encoder->base.crtc) {
8942                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8943                                       encoder->base.base.id,
8944                                       drm_get_encoder_name(&encoder->base));
8945                         encoder->disable(encoder);
8946                 }
8947
8948                 /* Inconsistent output/port/pipe state happens presumably due to
8949                  * a bug in one of the get_hw_state functions. Or someplace else
8950                  * in our code, like the register restore mess on resume. Clamp
8951                  * things to off as a safer default. */
8952                 list_for_each_entry(connector,
8953                                     &dev->mode_config.connector_list,
8954                                     base.head) {
8955                         if (connector->encoder != encoder)
8956                                 continue;
8957
8958                         intel_connector_break_all_links(connector);
8959                 }
8960         }
8961         /* Enabled encoders without active connectors will be fixed in
8962          * the crtc fixup. */
8963 }
8964
8965 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8966  * and i915 state tracking structures. */
8967 void intel_modeset_setup_hw_state(struct drm_device *dev)
8968 {
8969         struct drm_i915_private *dev_priv = dev->dev_private;
8970         enum pipe pipe;
8971         u32 tmp;
8972         struct intel_crtc *crtc;
8973         struct intel_encoder *encoder;
8974         struct intel_connector *connector;
8975
8976         if (IS_HASWELL(dev)) {
8977                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8978
8979                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8980                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8981                         case TRANS_DDI_EDP_INPUT_A_ON:
8982                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8983                                 pipe = PIPE_A;
8984                                 break;
8985                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8986                                 pipe = PIPE_B;
8987                                 break;
8988                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8989                                 pipe = PIPE_C;
8990                                 break;
8991                         }
8992
8993                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8994                         crtc->cpu_transcoder = TRANSCODER_EDP;
8995
8996                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8997                                       pipe_name(pipe));
8998                 }
8999         }
9000
9001         for_each_pipe(pipe) {
9002                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9003
9004                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9005                 if (tmp & PIPECONF_ENABLE)
9006                         crtc->active = true;
9007                 else
9008                         crtc->active = false;
9009
9010                 crtc->base.enabled = crtc->active;
9011
9012                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9013                               crtc->base.base.id,
9014                               crtc->active ? "enabled" : "disabled");
9015         }
9016
9017         if (IS_HASWELL(dev))
9018                 intel_ddi_setup_hw_pll_state(dev);
9019
9020         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9021                             base.head) {
9022                 pipe = 0;
9023
9024                 if (encoder->get_hw_state(encoder, &pipe)) {
9025                         encoder->base.crtc =
9026                                 dev_priv->pipe_to_crtc_mapping[pipe];
9027                 } else {
9028                         encoder->base.crtc = NULL;
9029                 }
9030
9031                 encoder->connectors_active = false;
9032                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9033                               encoder->base.base.id,
9034                               drm_get_encoder_name(&encoder->base),
9035                               encoder->base.crtc ? "enabled" : "disabled",
9036                               pipe);
9037         }
9038
9039         list_for_each_entry(connector, &dev->mode_config.connector_list,
9040                             base.head) {
9041                 if (connector->get_hw_state(connector)) {
9042                         connector->base.dpms = DRM_MODE_DPMS_ON;
9043                         connector->encoder->connectors_active = true;
9044                         connector->base.encoder = &connector->encoder->base;
9045                 } else {
9046                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9047                         connector->base.encoder = NULL;
9048                 }
9049                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9050                               connector->base.base.id,
9051                               drm_get_connector_name(&connector->base),
9052                               connector->base.encoder ? "enabled" : "disabled");
9053         }
9054
9055         /* HW state is read out, now we need to sanitize this mess. */
9056         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9057                             base.head) {
9058                 intel_sanitize_encoder(encoder);
9059         }
9060
9061         for_each_pipe(pipe) {
9062                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9063                 intel_sanitize_crtc(crtc);
9064         }
9065
9066         intel_modeset_update_staged_output_state(dev);
9067
9068         intel_modeset_check_state(dev);
9069
9070         drm_mode_config_reset(dev);
9071 }
9072
9073 void intel_modeset_gem_init(struct drm_device *dev)
9074 {
9075         intel_modeset_init_hw(dev);
9076
9077         intel_setup_overlay(dev);
9078
9079         intel_modeset_setup_hw_state(dev);
9080 }
9081
9082 void intel_modeset_cleanup(struct drm_device *dev)
9083 {
9084         struct drm_i915_private *dev_priv = dev->dev_private;
9085         struct drm_crtc *crtc;
9086         struct intel_crtc *intel_crtc;
9087
9088         drm_kms_helper_poll_fini(dev);
9089         mutex_lock(&dev->struct_mutex);
9090
9091         intel_unregister_dsm_handler();
9092
9093
9094         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9095                 /* Skip inactive CRTCs */
9096                 if (!crtc->fb)
9097                         continue;
9098
9099                 intel_crtc = to_intel_crtc(crtc);
9100                 intel_increase_pllclock(crtc);
9101         }
9102
9103         intel_disable_fbc(dev);
9104
9105         intel_disable_gt_powersave(dev);
9106
9107         ironlake_teardown_rc6(dev);
9108
9109         if (IS_VALLEYVIEW(dev))
9110                 vlv_init_dpio(dev);
9111
9112         mutex_unlock(&dev->struct_mutex);
9113
9114         /* Disable the irq before mode object teardown, for the irq might
9115          * enqueue unpin/hotplug work. */
9116         drm_irq_uninstall(dev);
9117         cancel_work_sync(&dev_priv->hotplug_work);
9118         cancel_work_sync(&dev_priv->rps.work);
9119
9120         /* flush any delayed tasks or pending work */
9121         flush_scheduled_work();
9122
9123         drm_mode_config_cleanup(dev);
9124 }
9125
9126 /*
9127  * Return which encoder is currently attached for connector.
9128  */
9129 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9130 {
9131         return &intel_attached_encoder(connector)->base;
9132 }
9133
9134 void intel_connector_attach_encoder(struct intel_connector *connector,
9135                                     struct intel_encoder *encoder)
9136 {
9137         connector->encoder = encoder;
9138         drm_mode_connector_attach_encoder(&connector->base,
9139                                           &encoder->base);
9140 }
9141
9142 /*
9143  * set vga decode state - true == enable VGA decode
9144  */
9145 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9146 {
9147         struct drm_i915_private *dev_priv = dev->dev_private;
9148         u16 gmch_ctrl;
9149
9150         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9151         if (state)
9152                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9153         else
9154                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9155         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9156         return 0;
9157 }
9158
9159 #ifdef CONFIG_DEBUG_FS
9160 #include <linux/seq_file.h>
9161
9162 struct intel_display_error_state {
9163         struct intel_cursor_error_state {
9164                 u32 control;
9165                 u32 position;
9166                 u32 base;
9167                 u32 size;
9168         } cursor[I915_MAX_PIPES];
9169
9170         struct intel_pipe_error_state {
9171                 u32 conf;
9172                 u32 source;
9173
9174                 u32 htotal;
9175                 u32 hblank;
9176                 u32 hsync;
9177                 u32 vtotal;
9178                 u32 vblank;
9179                 u32 vsync;
9180         } pipe[I915_MAX_PIPES];
9181
9182         struct intel_plane_error_state {
9183                 u32 control;
9184                 u32 stride;
9185                 u32 size;
9186                 u32 pos;
9187                 u32 addr;
9188                 u32 surface;
9189                 u32 tile_offset;
9190         } plane[I915_MAX_PIPES];
9191 };
9192
9193 struct intel_display_error_state *
9194 intel_display_capture_error_state(struct drm_device *dev)
9195 {
9196         drm_i915_private_t *dev_priv = dev->dev_private;
9197         struct intel_display_error_state *error;
9198         enum transcoder cpu_transcoder;
9199         int i;
9200
9201         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9202         if (error == NULL)
9203                 return NULL;
9204
9205         for_each_pipe(i) {
9206                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9207
9208                 error->cursor[i].control = I915_READ(CURCNTR(i));
9209                 error->cursor[i].position = I915_READ(CURPOS(i));
9210                 error->cursor[i].base = I915_READ(CURBASE(i));
9211
9212                 error->plane[i].control = I915_READ(DSPCNTR(i));
9213                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9214                 error->plane[i].size = I915_READ(DSPSIZE(i));
9215                 error->plane[i].pos = I915_READ(DSPPOS(i));
9216                 error->plane[i].addr = I915_READ(DSPADDR(i));
9217                 if (INTEL_INFO(dev)->gen >= 4) {
9218                         error->plane[i].surface = I915_READ(DSPSURF(i));
9219                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9220                 }
9221
9222                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9223                 error->pipe[i].source = I915_READ(PIPESRC(i));
9224                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9225                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9226                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9227                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9228                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9229                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9230         }
9231
9232         return error;
9233 }
9234
9235 void
9236 intel_display_print_error_state(struct seq_file *m,
9237                                 struct drm_device *dev,
9238                                 struct intel_display_error_state *error)
9239 {
9240         drm_i915_private_t *dev_priv = dev->dev_private;
9241         int i;
9242
9243         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9244         for_each_pipe(i) {
9245                 seq_printf(m, "Pipe [%d]:\n", i);
9246                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9247                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9248                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9249                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9250                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9251                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9252                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9253                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9254
9255                 seq_printf(m, "Plane [%d]:\n", i);
9256                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9257                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9258                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9259                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9260                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9261                 if (INTEL_INFO(dev)->gen >= 4) {
9262                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9263                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9264                 }
9265
9266                 seq_printf(m, "Cursor [%d]:\n", i);
9267                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9268                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9269                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9270         }
9271 }
9272 #endif