2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_pch_rawclk(struct drm_device *dev)
86 struct drm_i915_private *dev_priv = dev->dev_private;
88 WARN_ON(!HAS_PCH_SPLIT(dev));
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
116 static inline u32 /* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
126 static const intel_limit_t intel_limits_i8xx_dvo = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
137 .find_pll = intel_find_best_PLL,
140 static const intel_limit_t intel_limits_i8xx_lvds = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i9xx_sdvo = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_lvds = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
179 .find_pll = intel_find_best_PLL,
183 static const intel_limit_t intel_limits_g4x_sdvo = {
184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
196 .find_pll = intel_g4x_find_best_PLL,
199 static const intel_limit_t intel_limits_g4x_hdmi = {
200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
225 .find_pll = intel_g4x_find_best_PLL,
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
240 .find_pll = intel_g4x_find_best_PLL,
243 static const intel_limit_t intel_limits_g4x_display_port = {
244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 10, .p2_fast = 10 },
254 .find_pll = intel_find_pll_g4x_dp,
257 static const intel_limit_t intel_limits_pineview_sdvo = {
258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
270 .find_pll = intel_find_best_PLL,
273 static const intel_limit_t intel_limits_pineview_lvds = {
274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
284 .find_pll = intel_find_best_PLL,
287 /* Ironlake / Sandybridge
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
292 static const intel_limit_t intel_limits_ironlake_dac = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
303 .find_pll = intel_g4x_find_best_PLL,
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 .find_pll = intel_g4x_find_best_PLL,
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
346 .find_pll = intel_g4x_find_best_PLL,
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
357 .p1 = { .min = 2, .max = 6 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_display_port = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
373 .p2_slow = 10, .p2_fast = 10 },
374 .find_pll = intel_find_pll_ironlake_dp,
377 static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
391 static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
393 .vco = { .min = 4000000, .max = 5994000},
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_dp = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 22, .max = 450 },
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
437 val = I915_READ(DPIO_DATA);
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
466 static void vlv_init_dpio(struct drm_device *dev)
468 struct drm_i915_private *dev_priv = dev->dev_private;
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
483 static const struct dmi_system_id intel_dual_link_lvds[] = {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
492 { } /* terminating entry */
495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
504 if (dmi_check_system(intel_dual_link_lvds))
507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
515 val = I915_READ(reg);
516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 const intel_limit_t *limit;
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
532 /* LVDS dual channel */
533 if (refclk == 100000)
534 limit = &intel_limits_ironlake_dual_lvds_100m;
536 limit = &intel_limits_ironlake_dual_lvds;
538 if (refclk == 100000)
539 limit = &intel_limits_ironlake_single_lvds_100m;
541 limit = &intel_limits_ironlake_single_lvds;
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
545 limit = &intel_limits_ironlake_display_port;
547 limit = &intel_limits_ironlake_dac;
552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
559 if (is_dual_link_lvds(dev_priv, LVDS))
560 /* LVDS with dual channel */
561 limit = &intel_limits_g4x_dual_channel_lvds;
563 /* LVDS with dual channel */
564 limit = &intel_limits_g4x_single_channel_lvds;
565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
567 limit = &intel_limits_g4x_hdmi;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
569 limit = &intel_limits_g4x_sdvo;
570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
571 limit = &intel_limits_g4x_display_port;
572 } else /* The option is for other outputs */
573 limit = &intel_limits_i9xx_sdvo;
578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
583 if (HAS_PCH_SPLIT(dev))
584 limit = intel_ironlake_limit(crtc, refclk);
585 else if (IS_G4X(dev)) {
586 limit = intel_g4x_limit(crtc);
587 } else if (IS_PINEVIEW(dev)) {
588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
589 limit = &intel_limits_pineview_lvds;
591 limit = &intel_limits_pineview_sdvo;
592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
598 limit = &intel_limits_vlv_dp;
599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
603 limit = &intel_limits_i9xx_sdvo;
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
606 limit = &intel_limits_i8xx_lvds;
608 limit = &intel_limits_i8xx_dvo;
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk, intel_clock_t *clock)
616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
635 * Returns whether any output on the specified pipe is of the specified type
637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
639 struct drm_device *dev = crtc->dev;
640 struct intel_encoder *encoder;
642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
655 static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock->p < limit->p.min || limit->p.max < clock->p)
662 INTELPllInvalid("p out of range\n");
663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 if (clock->n < limit->n.min || limit->n.max < clock->n)
672 INTELPllInvalid("n out of range\n");
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
696 (I915_READ(LVDS)) != 0) {
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
703 if (is_dual_link_lvds(dev_priv, LVDS))
704 clock.p2 = limit->p2.p2_fast;
706 clock.p2 = limit->p2.p2_slow;
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
711 clock.p2 = limit->p2.p2_fast;
714 memset(best_clock, 0, sizeof(*best_clock));
716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
729 intel_clock(dev, refclk, &clock);
730 if (!intel_PLL_is_valid(dev, limit,
734 clock.p != match_clock->p)
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
747 return (err != target);
751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if (HAS_PCH_SPLIT(dev))
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
773 clock.p2 = limit->p2.p2_fast;
775 clock.p2 = limit->p2.p2_slow;
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
780 clock.p2 = limit->p2.p2_fast;
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
796 intel_clock(dev, refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
801 clock.p != match_clock->p)
804 this_err = abs(clock.dot - target);
805 if (this_err < err_most) {
819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
823 struct drm_device *dev = crtc->dev;
826 if (target < 200000) {
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
851 if (target < 200000) {
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
883 dotclk = target * 1000;
886 fastclk = dotclk / (2*100);
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
914 if (absppm < bestppm - 10) {
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
946 return intel_crtc->cpu_transcoder;
949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
954 frame = I915_READ(frame_reg);
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
961 * intel_wait_for_vblank - wait for vblank on a given pipe
963 * @pipe: pipe to wait for
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 int pipestat_reg = PIPESTAT(pipe);
973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
998 DRM_DEBUG_KMS("vblank wait timed out\n");
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1004 * @pipe: pipe to wait for
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1024 if (INTEL_INFO(dev)->gen >= 4) {
1025 int reg = PIPECONF(cpu_transcoder);
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1030 WARN(1, "pipe_off wait timed out\n");
1032 u32 last_line, line_mask;
1033 int reg = PIPEDSL(pipe);
1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037 line_mask = DSL_LINEMASK_GEN2;
1039 line_mask = DSL_LINEMASK_GEN3;
1041 /* Wait for the display line to settle */
1043 last_line = I915_READ(reg) & line_mask;
1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
1048 WARN(1, "pipe_off wait timed out\n");
1052 static const char *state_string(bool enabled)
1054 return enabled ? "on" : "off";
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1206 int pp_reg, lvds_reg;
1208 enum pipe panel_pipe = PIPE_A;
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1215 pp_reg = PP_CONTROL;
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1245 reg = PIPECONF(cpu_transcoder);
1246 val = I915_READ(reg);
1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1334 if ((val & DP_PORT_EN) == 0)
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1352 if ((val & PORT_ENABLE) == 0)
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1368 if ((val & LVDS_PORT_EN) == 0)
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, int reg, u32 port_sel)
1399 u32 val = I915_READ(reg);
1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg, pipe_name(pipe));
1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
1406 "IBX PCH dp port still using transcoder B\n");
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1412 u32 val = I915_READ(reg);
1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg, pipe_name(pipe));
1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
1419 "IBX PCH hdmi port still using transcoder B\n");
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1433 val = I915_READ(reg);
1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1439 val = I915_READ(reg);
1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1458 * Note! This is for pre-ILK only.
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1487 udelay(150); /* wait for warmup */
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1497 * Note! This is for pre-ILK only.
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1522 unsigned long flags;
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 I915_WRITE(SBI_ADDR,
1533 I915_WRITE(SBI_DATA,
1535 I915_WRITE(SBI_CTL_STAT,
1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1552 unsigned long flags;
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1562 I915_WRITE(SBI_ADDR,
1564 I915_WRITE(SBI_CTL_STAT,
1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1574 value = I915_READ(SBI_DATA);
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1582 * ironlake_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592 struct intel_pch_pll *pll;
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv->info->gen < 5);
1598 pll = intel_crtc->pch_pll;
1602 if (WARN_ON(pll->refcount == 0))
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1612 if (pll->active++ && pll->on) {
1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1641 if (WARN_ON(pll->refcount == 0))
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
1648 if (WARN_ON(pll->active == 0)) {
1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
1653 if (--pll->active) {
1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1677 u32 val, pipeconf_val;
1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1701 val &= ~PIPE_BPC_MASK;
1702 val |= pipeconf_val & PIPE_BPC_MASK;
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1711 val |= TRANS_INTERLACED;
1713 val |= TRANS_PROGRESSIVE;
1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721 enum transcoder cpu_transcoder)
1723 u32 val, pipeconf_val;
1725 /* PCH only available on ILK+ */
1726 BUG_ON(dev_priv->info->gen < 5);
1728 /* FDI must be feeding us bits for PCH ports */
1729 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1732 val = I915_READ(_TRANSACONF);
1733 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1735 val &= ~TRANS_INTERLACE_MASK;
1736 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1737 val |= TRANS_INTERLACED;
1739 val |= TRANS_PROGRESSIVE;
1741 I915_WRITE(_TRANSACONF, val | TRANS_ENABLE);
1742 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1743 DRM_ERROR("Failed to enable PCH transcoder\n");
1746 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752 /* FDI relies on the transcoder */
1753 assert_fdi_tx_disabled(dev_priv, pipe);
1754 assert_fdi_rx_disabled(dev_priv, pipe);
1756 /* Ports must be off as well */
1757 assert_pch_ports_disabled(dev_priv, pipe);
1759 reg = TRANSCONF(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_ENABLE;
1762 I915_WRITE(reg, val);
1763 /* wait for PCH transcoder off, transcoder state */
1764 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1765 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1768 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1791 * intel_enable_pipe - enable a pipe, asserting requirements
1792 * @dev_priv: i915 private structure
1793 * @pipe: pipe to enable
1794 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1796 * Enable @pipe, making sure that various hardware specific requirements
1797 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1799 * @pipe should be %PIPE_A or %PIPE_B.
1801 * Will wait until the pipe is actually running (i.e. first vblank) before
1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1807 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1813 * A pipe without a PLL won't actually be able to drive bits from
1814 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1817 if (!HAS_PCH_SPLIT(dev_priv->dev))
1818 assert_pll_enabled(dev_priv, pipe);
1821 /* if driving the PCH, we need FDI enabled */
1822 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1823 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1825 /* FIXME: assert CPU port conditions for SNB+ */
1828 reg = PIPECONF(cpu_transcoder);
1829 val = I915_READ(reg);
1830 if (val & PIPECONF_ENABLE)
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1838 * intel_disable_pipe - disable a pipe, asserting requirements
1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1845 * @pipe should be %PIPE_A or %PIPE_B.
1847 * Will wait until the pipe has shut down before returning.
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1861 assert_planes_disabled(dev_priv, pipe);
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1867 reg = PIPECONF(cpu_transcoder);
1868 val = I915_READ(reg);
1869 if ((val & PIPECONF_ENABLE) == 0)
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
1908 if (val & DISPLAY_PLANE_ENABLE)
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912 intel_flush_display_plane(dev_priv, plane);
1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1922 * Disable @plane; should be an independent operation.
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942 struct drm_i915_gem_object *obj,
1943 struct intel_ring_buffer *pipelined)
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1949 switch (obj->tiling_mode) {
1950 case I915_TILING_NONE:
1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
1953 else if (INTEL_INFO(dev)->gen >= 4)
1954 alignment = 4 * 1024;
1956 alignment = 64 * 1024;
1959 /* pin() will align the object as required by fence */
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1970 dev_priv->mm.interruptible = false;
1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1973 goto err_interruptible;
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1980 ret = i915_gem_object_get_fence(obj);
1984 i915_gem_object_pin_fence(obj);
1986 dev_priv->mm.interruptible = true;
1990 i915_gem_object_unpin(obj);
1992 dev_priv->mm.interruptible = true;
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2008 int tile_rows, tiles;
2012 tiles = *x / (512/bpp);
2015 return tile_rows * pitch * 8 + tiles * 4096;
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047 switch (fb->pixel_format) {
2049 dspcntr |= DISPPLANE_8BPP;
2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2079 if (INTEL_INFO(dev)->gen >= 4) {
2080 if (obj->tiling_mode != I915_TILING_NONE)
2081 dspcntr |= DISPPLANE_TILED;
2083 dspcntr &= ~DISPPLANE_TILED;
2086 I915_WRITE(reg, dspcntr);
2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2095 linear_offset -= intel_crtc->dspaddr_offset;
2097 intel_crtc->dspaddr_offset = linear_offset;
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103 if (INTEL_INFO(dev)->gen >= 4) {
2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
2124 unsigned long linear_offset;
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145 switch (fb->pixel_format) {
2147 dspcntr |= DISPPLANE_8BPP;
2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2176 dspcntr &= ~DISPPLANE_TILED;
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2181 I915_WRITE(reg, dspcntr);
2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184 intel_crtc->dspaddr_offset =
2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2188 linear_offset -= intel_crtc->dspaddr_offset;
2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
2216 intel_increase_pllclock(crtc);
2218 return dev_priv->display.update_plane(crtc, fb, x, y);
2222 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2229 wait_event(dev_priv->pending_flip_queue,
2230 atomic_read(&dev_priv->mm.wedged) ||
2231 atomic_read(&obj->pending_flip) == 0);
2233 /* Big Hammer, we also need to ensure that any pending
2234 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235 * current scanout is retired before unpinning the old
2238 * This should only fail upon a hung GPU, in which case we
2239 * can safely continue.
2241 dev_priv->mm.interruptible = false;
2242 ret = i915_gem_object_finish_gpu(obj);
2243 dev_priv->mm.interruptible = was_interruptible;
2248 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2250 struct drm_device *dev = crtc->dev;
2251 struct drm_i915_master_private *master_priv;
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2254 if (!dev->primary->master)
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2261 switch (intel_crtc->pipe) {
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
2267 master_priv->sarea_priv->pipeB_x = x;
2268 master_priv->sarea_priv->pipeB_y = y;
2276 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2277 struct drm_framebuffer *fb)
2279 struct drm_device *dev = crtc->dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2282 struct drm_framebuffer *old_fb;
2287 DRM_ERROR("No FB bound\n");
2291 if(intel_crtc->plane > dev_priv->num_pipe) {
2292 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2294 dev_priv->num_pipe);
2298 mutex_lock(&dev->struct_mutex);
2299 ret = intel_pin_and_fence_fb_obj(dev,
2300 to_intel_framebuffer(fb)->obj,
2303 mutex_unlock(&dev->struct_mutex);
2304 DRM_ERROR("pin & fence failed\n");
2309 intel_finish_fb(crtc->fb);
2311 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2313 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2314 mutex_unlock(&dev->struct_mutex);
2315 DRM_ERROR("failed to update base address\n");
2325 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2329 intel_update_fbc(dev);
2330 mutex_unlock(&dev->struct_mutex);
2332 intel_crtc_update_sarea_pos(crtc, x, y);
2337 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2339 struct drm_device *dev = crtc->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2343 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2344 dpa_ctl = I915_READ(DP_A);
2345 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2347 if (clock < 200000) {
2349 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2350 /* workaround for 160Mhz:
2351 1) program 0x4600c bits 15:0 = 0x8124
2352 2) program 0x46010 bit 0 = 1
2353 3) program 0x46034 bit 24 = 1
2354 4) program 0x64000 bit 14 = 1
2356 temp = I915_READ(0x4600c);
2358 I915_WRITE(0x4600c, temp | 0x8124);
2360 temp = I915_READ(0x46010);
2361 I915_WRITE(0x46010, temp | 1);
2363 temp = I915_READ(0x46034);
2364 I915_WRITE(0x46034, temp | (1 << 24));
2366 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2368 I915_WRITE(DP_A, dpa_ctl);
2374 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2376 struct drm_device *dev = crtc->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 int pipe = intel_crtc->pipe;
2382 /* enable normal train */
2383 reg = FDI_TX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 if (IS_IVYBRIDGE(dev)) {
2386 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2387 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2392 I915_WRITE(reg, temp);
2394 reg = FDI_RX_CTL(pipe);
2395 temp = I915_READ(reg);
2396 if (HAS_PCH_CPT(dev)) {
2397 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2398 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_NONE;
2403 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2405 /* wait one idle pattern time */
2409 /* IVB wants error correction enabled */
2410 if (IS_IVYBRIDGE(dev))
2411 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2412 FDI_FE_ERRC_ENABLE);
2415 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 u32 flags = I915_READ(SOUTH_CHICKEN1);
2420 flags |= FDI_PHASE_SYNC_OVR(pipe);
2421 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2422 flags |= FDI_PHASE_SYNC_EN(pipe);
2423 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2424 POSTING_READ(SOUTH_CHICKEN1);
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *pipe_B_crtc =
2431 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432 struct intel_crtc *pipe_C_crtc =
2433 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2436 /* When everything is off disable fdi C so that we could enable fdi B
2437 * with all lanes. XXX: This misses the case where a pipe is not using
2438 * any pch resources and so doesn't need any fdi lanes. */
2439 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2441 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2443 temp = I915_READ(SOUTH_CHICKEN1);
2444 temp &= ~FDI_BC_BIFURCATION_SELECT;
2445 DRM_DEBUG_KMS("disabling fdi C rx\n");
2446 I915_WRITE(SOUTH_CHICKEN1, temp);
2450 /* The FDI link training functions for ILK/Ibexpeak. */
2451 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
2457 int plane = intel_crtc->plane;
2458 u32 reg, temp, tries;
2460 /* FDI needs bits from pipe & plane first */
2461 assert_pipe_enabled(dev_priv, pipe);
2462 assert_plane_enabled(dev_priv, plane);
2464 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2466 reg = FDI_RX_IMR(pipe);
2467 temp = I915_READ(reg);
2468 temp &= ~FDI_RX_SYMBOL_LOCK;
2469 temp &= ~FDI_RX_BIT_LOCK;
2470 I915_WRITE(reg, temp);
2474 /* enable CPU FDI TX and PCH FDI RX */
2475 reg = FDI_TX_CTL(pipe);
2476 temp = I915_READ(reg);
2478 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2479 temp &= ~FDI_LINK_TRAIN_NONE;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1;
2481 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2483 reg = FDI_RX_CTL(pipe);
2484 temp = I915_READ(reg);
2485 temp &= ~FDI_LINK_TRAIN_NONE;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1;
2487 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492 /* Ironlake workaround, enable clock pointer after FDI enable*/
2493 if (HAS_PCH_IBX(dev)) {
2494 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2495 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2496 FDI_RX_PHASE_SYNC_POINTER_EN);
2499 reg = FDI_RX_IIR(pipe);
2500 for (tries = 0; tries < 5; tries++) {
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504 if ((temp & FDI_RX_BIT_LOCK)) {
2505 DRM_DEBUG_KMS("FDI train 1 done.\n");
2506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2511 DRM_ERROR("FDI train 1 fail!\n");
2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
2516 temp &= ~FDI_LINK_TRAIN_NONE;
2517 temp |= FDI_LINK_TRAIN_PATTERN_2;
2518 I915_WRITE(reg, temp);
2520 reg = FDI_RX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_2;
2524 I915_WRITE(reg, temp);
2529 reg = FDI_RX_IIR(pipe);
2530 for (tries = 0; tries < 5; tries++) {
2531 temp = I915_READ(reg);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534 if (temp & FDI_RX_SYMBOL_LOCK) {
2535 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2536 DRM_DEBUG_KMS("FDI train 2 done.\n");
2541 DRM_ERROR("FDI train 2 fail!\n");
2543 DRM_DEBUG_KMS("FDI train done\n");
2547 static const int snb_b_fdi_train_param[] = {
2548 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2554 /* The FDI link training functions for SNB/Cougarpoint. */
2555 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 struct drm_device *dev = crtc->dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560 int pipe = intel_crtc->pipe;
2561 u32 reg, temp, i, retry;
2563 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565 reg = FDI_RX_IMR(pipe);
2566 temp = I915_READ(reg);
2567 temp &= ~FDI_RX_SYMBOL_LOCK;
2568 temp &= ~FDI_RX_BIT_LOCK;
2569 I915_WRITE(reg, temp);
2574 /* enable CPU FDI TX and PCH FDI RX */
2575 reg = FDI_TX_CTL(pipe);
2576 temp = I915_READ(reg);
2578 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2579 temp &= ~FDI_LINK_TRAIN_NONE;
2580 temp |= FDI_LINK_TRAIN_PATTERN_1;
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586 I915_WRITE(FDI_RX_MISC(pipe),
2587 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589 reg = FDI_RX_CTL(pipe);
2590 temp = I915_READ(reg);
2591 if (HAS_PCH_CPT(dev)) {
2592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_1;
2598 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2603 if (HAS_PCH_CPT(dev))
2604 cpt_phase_pointer_enable(dev, pipe);
2606 for (i = 0; i < 4; i++) {
2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
2611 I915_WRITE(reg, temp);
2616 for (retry = 0; retry < 5; retry++) {
2617 reg = FDI_RX_IIR(pipe);
2618 temp = I915_READ(reg);
2619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620 if (temp & FDI_RX_BIT_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622 DRM_DEBUG_KMS("FDI train 1 done.\n");
2631 DRM_ERROR("FDI train 1 fail!\n");
2634 reg = FDI_TX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2643 I915_WRITE(reg, temp);
2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 if (HAS_PCH_CPT(dev)) {
2648 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 temp &= ~FDI_LINK_TRAIN_NONE;
2652 temp |= FDI_LINK_TRAIN_PATTERN_2;
2654 I915_WRITE(reg, temp);
2659 for (i = 0; i < 4; i++) {
2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663 temp |= snb_b_fdi_train_param[i];
2664 I915_WRITE(reg, temp);
2669 for (retry = 0; retry < 5; retry++) {
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673 if (temp & FDI_RX_SYMBOL_LOCK) {
2674 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675 DRM_DEBUG_KMS("FDI train 2 done.\n");
2684 DRM_ERROR("FDI train 2 fail!\n");
2686 DRM_DEBUG_KMS("FDI train done.\n");
2689 /* Manual link training for Ivy Bridge A0 parts */
2690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2692 struct drm_device *dev = crtc->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695 int pipe = intel_crtc->pipe;
2698 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2700 reg = FDI_RX_IMR(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~FDI_RX_SYMBOL_LOCK;
2703 temp &= ~FDI_RX_BIT_LOCK;
2704 I915_WRITE(reg, temp);
2709 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710 I915_READ(FDI_RX_IIR(pipe)));
2712 /* enable CPU FDI TX and PCH FDI RX */
2713 reg = FDI_TX_CTL(pipe);
2714 temp = I915_READ(reg);
2716 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2717 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721 temp |= FDI_COMPOSITE_SYNC;
2722 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2724 I915_WRITE(FDI_RX_MISC(pipe),
2725 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2727 reg = FDI_RX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 temp &= ~FDI_LINK_TRAIN_AUTO;
2730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2732 temp |= FDI_COMPOSITE_SYNC;
2733 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2738 if (HAS_PCH_CPT(dev))
2739 cpt_phase_pointer_enable(dev, pipe);
2741 for (i = 0; i < 4; i++) {
2742 reg = FDI_TX_CTL(pipe);
2743 temp = I915_READ(reg);
2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= snb_b_fdi_train_param[i];
2746 I915_WRITE(reg, temp);
2751 reg = FDI_RX_IIR(pipe);
2752 temp = I915_READ(reg);
2753 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2755 if (temp & FDI_RX_BIT_LOCK ||
2756 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2757 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2758 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2763 DRM_ERROR("FDI train 1 fail!\n");
2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2769 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2770 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2771 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2772 I915_WRITE(reg, temp);
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2778 I915_WRITE(reg, temp);
2783 for (i = 0; i < 4; i++) {
2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787 temp |= snb_b_fdi_train_param[i];
2788 I915_WRITE(reg, temp);
2793 reg = FDI_RX_IIR(pipe);
2794 temp = I915_READ(reg);
2795 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2797 if (temp & FDI_RX_SYMBOL_LOCK) {
2798 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2799 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2804 DRM_ERROR("FDI train 2 fail!\n");
2806 DRM_DEBUG_KMS("FDI train done.\n");
2809 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2811 struct drm_device *dev = intel_crtc->base.dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 int pipe = intel_crtc->pipe;
2817 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 temp &= ~((0x7 << 19) | (0x7 << 16));
2821 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2828 /* Switch from Rawclk to PCDclk */
2829 temp = I915_READ(reg);
2830 I915_WRITE(reg, temp | FDI_PCDCLK);
2835 /* On Haswell, the PLL configuration for ports and pipes is handled
2836 * separately, as part of DDI setup */
2837 if (!IS_HASWELL(dev)) {
2838 /* Enable CPU FDI TX PLL, always on for Ironlake */
2839 reg = FDI_TX_CTL(pipe);
2840 temp = I915_READ(reg);
2841 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2842 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2850 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2852 struct drm_device *dev = intel_crtc->base.dev;
2853 struct drm_i915_private *dev_priv = dev->dev_private;
2854 int pipe = intel_crtc->pipe;
2857 /* Switch from PCDclk to Rawclk */
2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2862 /* Disable CPU FDI TX PLL */
2863 reg = FDI_TX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2870 reg = FDI_RX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2874 /* Wait for the clocks to turn off. */
2879 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 u32 flags = I915_READ(SOUTH_CHICKEN1);
2884 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2885 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2886 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2887 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2888 POSTING_READ(SOUTH_CHICKEN1);
2890 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2898 /* disable CPU FDI tx and PCH FDI rx */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2904 reg = FDI_RX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 temp &= ~(0x7 << 16);
2907 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2908 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2913 /* Ironlake workaround, disable clock pointer after downing FDI */
2914 if (HAS_PCH_IBX(dev)) {
2915 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2916 I915_WRITE(FDI_RX_CHICKEN(pipe),
2917 I915_READ(FDI_RX_CHICKEN(pipe) &
2918 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2919 } else if (HAS_PCH_CPT(dev)) {
2920 cpt_phase_pointer_disable(dev, pipe);
2923 /* still set train pattern 1 */
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 temp &= ~FDI_LINK_TRAIN_NONE;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1;
2928 I915_WRITE(reg, temp);
2930 reg = FDI_RX_CTL(pipe);
2931 temp = I915_READ(reg);
2932 if (HAS_PCH_CPT(dev)) {
2933 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2934 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2936 temp &= ~FDI_LINK_TRAIN_NONE;
2937 temp |= FDI_LINK_TRAIN_PATTERN_1;
2939 /* BPC in FDI rx is consistent with that in PIPECONF */
2940 temp &= ~(0x07 << 16);
2941 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2942 I915_WRITE(reg, temp);
2948 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2950 struct drm_device *dev = crtc->dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 unsigned long flags;
2955 if (atomic_read(&dev_priv->mm.wedged))
2958 spin_lock_irqsave(&dev->event_lock, flags);
2959 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2960 spin_unlock_irqrestore(&dev->event_lock, flags);
2965 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2970 if (crtc->fb == NULL)
2973 wait_event(dev_priv->pending_flip_queue,
2974 !intel_crtc_has_pending_flip(crtc));
2976 mutex_lock(&dev->struct_mutex);
2977 intel_finish_fb(crtc->fb);
2978 mutex_unlock(&dev->struct_mutex);
2981 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2983 struct drm_device *dev = crtc->dev;
2984 struct intel_encoder *intel_encoder;
2987 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2988 * must be driven by its own crtc; no sharing is possible.
2990 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2991 switch (intel_encoder->type) {
2992 case INTEL_OUTPUT_EDP:
2993 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3002 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3004 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3007 /* Program iCLKIP clock to the desired frequency */
3008 static void lpt_program_iclkip(struct drm_crtc *crtc)
3010 struct drm_device *dev = crtc->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3015 /* It is necessary to ungate the pixclk gate prior to programming
3016 * the divisors, and gate it back when it is done.
3018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3020 /* Disable SSCCTL */
3021 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3022 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3023 SBI_SSCCTL_DISABLE);
3025 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3026 if (crtc->mode.clock == 20000) {
3031 /* The iCLK virtual clock root frequency is in MHz,
3032 * but the crtc->mode.clock in in KHz. To get the divisors,
3033 * it is necessary to divide one by another, so we
3034 * convert the virtual clock precision to KHz here for higher
3037 u32 iclk_virtual_root_freq = 172800 * 1000;
3038 u32 iclk_pi_range = 64;
3039 u32 desired_divisor, msb_divisor_value, pi_value;
3041 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3042 msb_divisor_value = desired_divisor / iclk_pi_range;
3043 pi_value = desired_divisor % iclk_pi_range;
3046 divsel = msb_divisor_value - 2;
3047 phaseinc = pi_value;
3050 /* This should not happen with any sane values */
3051 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3052 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3053 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3054 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3056 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3063 /* Program SSCDIVINTPHASE6 */
3064 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3065 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3066 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3067 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3068 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3069 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3070 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3072 intel_sbi_write(dev_priv,
3073 SBI_SSCDIVINTPHASE6,
3076 /* Program SSCAUXDIV */
3077 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3078 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3080 intel_sbi_write(dev_priv,
3085 /* Enable modulator and associated divider */
3086 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3087 temp &= ~SBI_SSCCTL_DISABLE;
3088 intel_sbi_write(dev_priv,
3092 /* Wait for initialization time */
3095 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3099 * Enable PCH resources required for PCH ports:
3101 * - FDI training & RX/TX
3102 * - update transcoder timings
3103 * - DP transcoding bits
3106 static void ironlake_pch_enable(struct drm_crtc *crtc)
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3111 int pipe = intel_crtc->pipe;
3114 assert_transcoder_disabled(dev_priv, pipe);
3116 /* Write the TU size bits before fdi link training, so that error
3117 * detection works. */
3118 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3119 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3121 /* For PCH output, training FDI link */
3122 dev_priv->display.fdi_link_train(crtc);
3124 /* XXX: pch pll's can be enabled any time before we enable the PCH
3125 * transcoder, and we actually should do this to not upset any PCH
3126 * transcoder that already use the clock when we share it.
3128 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3129 * unconditionally resets the pll - we need that to have the right LVDS
3130 * enable sequence. */
3131 ironlake_enable_pch_pll(intel_crtc);
3133 if (HAS_PCH_CPT(dev)) {
3136 temp = I915_READ(PCH_DPLL_SEL);
3140 temp |= TRANSA_DPLL_ENABLE;
3141 sel = TRANSA_DPLLB_SEL;
3144 temp |= TRANSB_DPLL_ENABLE;
3145 sel = TRANSB_DPLLB_SEL;
3148 temp |= TRANSC_DPLL_ENABLE;
3149 sel = TRANSC_DPLLB_SEL;
3152 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3156 I915_WRITE(PCH_DPLL_SEL, temp);
3159 /* set transcoder timing, panel must allow it */
3160 assert_panel_unlocked(dev_priv, pipe);
3161 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3162 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3163 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3165 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3166 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3167 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3168 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3170 intel_fdi_normal_train(crtc);
3172 /* For PCH DP, enable TRANS_DP_CTL */
3173 if (HAS_PCH_CPT(dev) &&
3174 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3175 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3176 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3177 reg = TRANS_DP_CTL(pipe);
3178 temp = I915_READ(reg);
3179 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3180 TRANS_DP_SYNC_MASK |
3182 temp |= (TRANS_DP_OUTPUT_ENABLE |
3183 TRANS_DP_ENH_FRAMING);
3184 temp |= bpc << 9; /* same format but at 11:9 */
3186 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3187 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3188 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3189 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3191 switch (intel_trans_dp_port_sel(crtc)) {
3193 temp |= TRANS_DP_PORT_SEL_B;
3196 temp |= TRANS_DP_PORT_SEL_C;
3199 temp |= TRANS_DP_PORT_SEL_D;
3205 I915_WRITE(reg, temp);
3208 ironlake_enable_pch_transcoder(dev_priv, pipe);
3211 static void lpt_pch_enable(struct drm_crtc *crtc)
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 int pipe = intel_crtc->pipe;
3217 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3219 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3221 /* Write the TU size bits before fdi link training, so that error
3222 * detection works. */
3223 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3224 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3226 /* For PCH output, training FDI link */
3227 dev_priv->display.fdi_link_train(crtc);
3229 lpt_program_iclkip(crtc);
3231 /* Set transcoder timing. */
3232 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3233 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3234 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3236 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3237 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3238 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3239 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3241 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3244 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3246 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3251 if (pll->refcount == 0) {
3252 WARN(1, "bad PCH PLL refcount\n");
3257 intel_crtc->pch_pll = NULL;
3260 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3262 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3263 struct intel_pch_pll *pll;
3266 pll = intel_crtc->pch_pll;
3268 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3269 intel_crtc->base.base.id, pll->pll_reg);
3273 if (HAS_PCH_IBX(dev_priv->dev)) {
3274 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3275 i = intel_crtc->pipe;
3276 pll = &dev_priv->pch_plls[i];
3278 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3279 intel_crtc->base.base.id, pll->pll_reg);
3284 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3285 pll = &dev_priv->pch_plls[i];
3287 /* Only want to check enabled timings first */
3288 if (pll->refcount == 0)
3291 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3292 fp == I915_READ(pll->fp0_reg)) {
3293 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3294 intel_crtc->base.base.id,
3295 pll->pll_reg, pll->refcount, pll->active);
3301 /* Ok no matching timings, maybe there's a free one? */
3302 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3303 pll = &dev_priv->pch_plls[i];
3304 if (pll->refcount == 0) {
3305 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3306 intel_crtc->base.base.id, pll->pll_reg);
3314 intel_crtc->pch_pll = pll;
3316 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3317 prepare: /* separate function? */
3318 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3320 /* Wait for the clocks to stabilize before rewriting the regs */
3321 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3322 POSTING_READ(pll->pll_reg);
3325 I915_WRITE(pll->fp0_reg, fp);
3326 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3331 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3337 temp = I915_READ(dslreg);
3339 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3340 /* Without this, mode sets may fail silently on FDI */
3341 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3343 I915_WRITE(tc2reg, 0);
3344 if (wait_for(I915_READ(dslreg) != temp, 5))
3345 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3349 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
3360 WARN_ON(!crtc->enabled);
3362 if (intel_crtc->active)
3365 intel_crtc->active = true;
3366 intel_update_watermarks(dev);
3368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3369 temp = I915_READ(PCH_LVDS);
3370 if ((temp & LVDS_PORT_EN) == 0)
3371 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3374 is_pch_port = ironlake_crtc_driving_pch(crtc);
3377 /* Note: FDI PLL enabling _must_ be done before we enable the
3378 * cpu pipes, hence this is separate from all the other fdi/pch
3380 ironlake_fdi_pll_enable(intel_crtc);
3382 assert_fdi_tx_disabled(dev_priv, pipe);
3383 assert_fdi_rx_disabled(dev_priv, pipe);
3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 if (encoder->pre_enable)
3388 encoder->pre_enable(encoder);
3390 /* Enable panel fitting for LVDS */
3391 if (dev_priv->pch_pf_size &&
3392 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3393 /* Force use of hard-coded filter coefficients
3394 * as some pre-programmed values are broken,
3397 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3398 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3399 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3403 * On ILK+ LUT must be loaded before the pipe is running but with
3406 intel_crtc_load_lut(crtc);
3408 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3409 intel_enable_plane(dev_priv, plane, pipe);
3412 ironlake_pch_enable(crtc);
3414 mutex_lock(&dev->struct_mutex);
3415 intel_update_fbc(dev);
3416 mutex_unlock(&dev->struct_mutex);
3418 intel_crtc_update_cursor(crtc, true);
3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 encoder->enable(encoder);
3423 if (HAS_PCH_CPT(dev))
3424 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3427 * There seems to be a race in PCH platform hw (at least on some
3428 * outputs) where an enabled pipe still completes any pageflip right
3429 * away (as if the pipe is off) instead of waiting for vblank. As soon
3430 * as the first vblank happend, everything works as expected. Hence just
3431 * wait for one vblank before returning to avoid strange things
3434 intel_wait_for_vblank(dev, intel_crtc->pipe);
3437 static void haswell_crtc_enable(struct drm_crtc *crtc)
3439 struct drm_device *dev = crtc->dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442 struct intel_encoder *encoder;
3443 int pipe = intel_crtc->pipe;
3444 int plane = intel_crtc->plane;
3447 WARN_ON(!crtc->enabled);
3449 if (intel_crtc->active)
3452 intel_crtc->active = true;
3453 intel_update_watermarks(dev);
3455 is_pch_port = haswell_crtc_driving_pch(crtc);
3458 ironlake_fdi_pll_enable(intel_crtc);
3460 for_each_encoder_on_crtc(dev, crtc, encoder)
3461 if (encoder->pre_enable)
3462 encoder->pre_enable(encoder);
3464 intel_ddi_enable_pipe_clock(intel_crtc);
3466 /* Enable panel fitting for eDP */
3467 if (dev_priv->pch_pf_size && HAS_eDP) {
3468 /* Force use of hard-coded filter coefficients
3469 * as some pre-programmed values are broken,
3472 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3473 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3474 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3478 * On ILK+ LUT must be loaded before the pipe is running but with
3481 intel_crtc_load_lut(crtc);
3483 intel_ddi_set_pipe_settings(crtc);
3484 intel_ddi_enable_pipe_func(crtc);
3486 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3487 intel_enable_plane(dev_priv, plane, pipe);
3490 lpt_pch_enable(crtc);
3492 mutex_lock(&dev->struct_mutex);
3493 intel_update_fbc(dev);
3494 mutex_unlock(&dev->struct_mutex);
3496 intel_crtc_update_cursor(crtc, true);
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->enable(encoder);
3502 * There seems to be a race in PCH platform hw (at least on some
3503 * outputs) where an enabled pipe still completes any pageflip right
3504 * away (as if the pipe is off) instead of waiting for vblank. As soon
3505 * as the first vblank happend, everything works as expected. Hence just
3506 * wait for one vblank before returning to avoid strange things
3509 intel_wait_for_vblank(dev, intel_crtc->pipe);
3512 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 struct intel_encoder *encoder;
3518 int pipe = intel_crtc->pipe;
3519 int plane = intel_crtc->plane;
3523 if (!intel_crtc->active)
3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 encoder->disable(encoder);
3529 intel_crtc_wait_for_pending_flips(crtc);
3530 drm_vblank_off(dev, pipe);
3531 intel_crtc_update_cursor(crtc, false);
3533 intel_disable_plane(dev_priv, plane, pipe);
3535 if (dev_priv->cfb_plane == plane)
3536 intel_disable_fbc(dev);
3538 intel_disable_pipe(dev_priv, pipe);
3541 I915_WRITE(PF_CTL(pipe), 0);
3542 I915_WRITE(PF_WIN_SZ(pipe), 0);
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3548 ironlake_fdi_disable(crtc);
3550 ironlake_disable_pch_transcoder(dev_priv, pipe);
3552 if (HAS_PCH_CPT(dev)) {
3553 /* disable TRANS_DP_CTL */
3554 reg = TRANS_DP_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3557 temp |= TRANS_DP_PORT_SEL_NONE;
3558 I915_WRITE(reg, temp);
3560 /* disable DPLL_SEL */
3561 temp = I915_READ(PCH_DPLL_SEL);
3564 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3567 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3570 /* C shares PLL A or B */
3571 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3576 I915_WRITE(PCH_DPLL_SEL, temp);
3579 /* disable PCH DPLL */
3580 intel_disable_pch_pll(intel_crtc);
3582 ironlake_fdi_pll_disable(intel_crtc);
3584 intel_crtc->active = false;
3585 intel_update_watermarks(dev);
3587 mutex_lock(&dev->struct_mutex);
3588 intel_update_fbc(dev);
3589 mutex_unlock(&dev->struct_mutex);
3592 static void haswell_crtc_disable(struct drm_crtc *crtc)
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 struct intel_encoder *encoder;
3598 int pipe = intel_crtc->pipe;
3599 int plane = intel_crtc->plane;
3600 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3603 if (!intel_crtc->active)
3606 is_pch_port = haswell_crtc_driving_pch(crtc);
3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->disable(encoder);
3611 intel_crtc_wait_for_pending_flips(crtc);
3612 drm_vblank_off(dev, pipe);
3613 intel_crtc_update_cursor(crtc, false);
3615 intel_disable_plane(dev_priv, plane, pipe);
3617 if (dev_priv->cfb_plane == plane)
3618 intel_disable_fbc(dev);
3620 intel_disable_pipe(dev_priv, pipe);
3622 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3625 I915_WRITE(PF_CTL(pipe), 0);
3626 I915_WRITE(PF_WIN_SZ(pipe), 0);
3628 intel_ddi_disable_pipe_clock(intel_crtc);
3630 for_each_encoder_on_crtc(dev, crtc, encoder)
3631 if (encoder->post_disable)
3632 encoder->post_disable(encoder);
3635 ironlake_fdi_disable(crtc);
3636 lpt_disable_pch_transcoder(dev_priv, pipe);
3637 intel_disable_pch_pll(intel_crtc);
3638 ironlake_fdi_pll_disable(intel_crtc);
3641 intel_crtc->active = false;
3642 intel_update_watermarks(dev);
3644 mutex_lock(&dev->struct_mutex);
3645 intel_update_fbc(dev);
3646 mutex_unlock(&dev->struct_mutex);
3649 static void ironlake_crtc_off(struct drm_crtc *crtc)
3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652 intel_put_pch_pll(intel_crtc);
3655 static void haswell_crtc_off(struct drm_crtc *crtc)
3657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3660 * start using it. */
3661 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3663 intel_ddi_put_crtc_pll(crtc);
3666 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3668 if (!enable && intel_crtc->overlay) {
3669 struct drm_device *dev = intel_crtc->base.dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3672 mutex_lock(&dev->struct_mutex);
3673 dev_priv->mm.interruptible = false;
3674 (void) intel_overlay_switch_off(intel_crtc->overlay);
3675 dev_priv->mm.interruptible = true;
3676 mutex_unlock(&dev->struct_mutex);
3679 /* Let userspace switch the overlay on again. In most cases userspace
3680 * has to recompute where to put it anyway.
3684 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3686 struct drm_device *dev = crtc->dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 struct intel_encoder *encoder;
3690 int pipe = intel_crtc->pipe;
3691 int plane = intel_crtc->plane;
3693 WARN_ON(!crtc->enabled);
3695 if (intel_crtc->active)
3698 intel_crtc->active = true;
3699 intel_update_watermarks(dev);
3701 intel_enable_pll(dev_priv, pipe);
3702 intel_enable_pipe(dev_priv, pipe, false);
3703 intel_enable_plane(dev_priv, plane, pipe);
3705 intel_crtc_load_lut(crtc);
3706 intel_update_fbc(dev);
3708 /* Give the overlay scaler a chance to enable if it's on this pipe */
3709 intel_crtc_dpms_overlay(intel_crtc, true);
3710 intel_crtc_update_cursor(crtc, true);
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->enable(encoder);
3716 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721 struct intel_encoder *encoder;
3722 int pipe = intel_crtc->pipe;
3723 int plane = intel_crtc->plane;
3726 if (!intel_crtc->active)
3729 for_each_encoder_on_crtc(dev, crtc, encoder)
3730 encoder->disable(encoder);
3732 /* Give the overlay scaler a chance to disable if it's on this pipe */
3733 intel_crtc_wait_for_pending_flips(crtc);
3734 drm_vblank_off(dev, pipe);
3735 intel_crtc_dpms_overlay(intel_crtc, false);
3736 intel_crtc_update_cursor(crtc, false);
3738 if (dev_priv->cfb_plane == plane)
3739 intel_disable_fbc(dev);
3741 intel_disable_plane(dev_priv, plane, pipe);
3742 intel_disable_pipe(dev_priv, pipe);
3743 intel_disable_pll(dev_priv, pipe);
3745 intel_crtc->active = false;
3746 intel_update_fbc(dev);
3747 intel_update_watermarks(dev);
3750 static void i9xx_crtc_off(struct drm_crtc *crtc)
3754 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_master_private *master_priv;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760 int pipe = intel_crtc->pipe;
3762 if (!dev->primary->master)
3765 master_priv = dev->primary->master->driver_priv;
3766 if (!master_priv->sarea_priv)
3771 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3772 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3775 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3776 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3779 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3785 * Sets the power management mode of the pipe and plane.
3787 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789 struct drm_device *dev = crtc->dev;
3790 struct drm_i915_private *dev_priv = dev->dev_private;
3791 struct intel_encoder *intel_encoder;
3792 bool enable = false;
3794 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3795 enable |= intel_encoder->connectors_active;
3798 dev_priv->display.crtc_enable(crtc);
3800 dev_priv->display.crtc_disable(crtc);
3802 intel_crtc_update_sarea(crtc, enable);
3805 static void intel_crtc_noop(struct drm_crtc *crtc)
3809 static void intel_crtc_disable(struct drm_crtc *crtc)
3811 struct drm_device *dev = crtc->dev;
3812 struct drm_connector *connector;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3815 /* crtc should still be enabled when we disable it. */
3816 WARN_ON(!crtc->enabled);
3818 dev_priv->display.crtc_disable(crtc);
3819 intel_crtc_update_sarea(crtc, false);
3820 dev_priv->display.off(crtc);
3822 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3823 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3826 mutex_lock(&dev->struct_mutex);
3827 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3828 mutex_unlock(&dev->struct_mutex);
3832 /* Update computed state. */
3833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3834 if (!connector->encoder || !connector->encoder->crtc)
3837 if (connector->encoder->crtc != crtc)
3840 connector->dpms = DRM_MODE_DPMS_OFF;
3841 to_intel_encoder(connector->encoder)->connectors_active = false;
3845 void intel_modeset_disable(struct drm_device *dev)
3847 struct drm_crtc *crtc;
3849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3851 intel_crtc_disable(crtc);
3855 void intel_encoder_noop(struct drm_encoder *encoder)
3859 void intel_encoder_destroy(struct drm_encoder *encoder)
3861 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3863 drm_encoder_cleanup(encoder);
3864 kfree(intel_encoder);
3867 /* Simple dpms helper for encodres with just one connector, no cloning and only
3868 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3869 * state of the entire output pipe. */
3870 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3872 if (mode == DRM_MODE_DPMS_ON) {
3873 encoder->connectors_active = true;
3875 intel_crtc_update_dpms(encoder->base.crtc);
3877 encoder->connectors_active = false;
3879 intel_crtc_update_dpms(encoder->base.crtc);
3883 /* Cross check the actual hw state with our own modeset state tracking (and it's
3884 * internal consistency). */
3885 static void intel_connector_check_state(struct intel_connector *connector)
3887 if (connector->get_hw_state(connector)) {
3888 struct intel_encoder *encoder = connector->encoder;
3889 struct drm_crtc *crtc;
3890 bool encoder_enabled;
3893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3894 connector->base.base.id,
3895 drm_get_connector_name(&connector->base));
3897 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3898 "wrong connector dpms state\n");
3899 WARN(connector->base.encoder != &encoder->base,
3900 "active connector not linked to encoder\n");
3901 WARN(!encoder->connectors_active,
3902 "encoder->connectors_active not set\n");
3904 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3905 WARN(!encoder_enabled, "encoder not enabled\n");
3906 if (WARN_ON(!encoder->base.crtc))
3909 crtc = encoder->base.crtc;
3911 WARN(!crtc->enabled, "crtc not enabled\n");
3912 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3913 WARN(pipe != to_intel_crtc(crtc)->pipe,
3914 "encoder active on the wrong pipe\n");
3918 /* Even simpler default implementation, if there's really no special case to
3920 void intel_connector_dpms(struct drm_connector *connector, int mode)
3922 struct intel_encoder *encoder = intel_attached_encoder(connector);
3924 /* All the simple cases only support two dpms states. */
3925 if (mode != DRM_MODE_DPMS_ON)
3926 mode = DRM_MODE_DPMS_OFF;
3928 if (mode == connector->dpms)
3931 connector->dpms = mode;
3933 /* Only need to change hw state when actually enabled */
3934 if (encoder->base.crtc)
3935 intel_encoder_dpms(encoder, mode);
3937 WARN_ON(encoder->connectors_active != false);
3939 intel_modeset_check_state(connector->dev);
3942 /* Simple connector->get_hw_state implementation for encoders that support only
3943 * one connector and no cloning and hence the encoder state determines the state
3944 * of the connector. */
3945 bool intel_connector_get_hw_state(struct intel_connector *connector)
3948 struct intel_encoder *encoder = connector->encoder;
3950 return encoder->get_hw_state(encoder, &pipe);
3953 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3954 const struct drm_display_mode *mode,
3955 struct drm_display_mode *adjusted_mode)
3957 struct drm_device *dev = crtc->dev;
3959 if (HAS_PCH_SPLIT(dev)) {
3960 /* FDI link clock is fixed at 2.7G */
3961 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3965 /* All interlaced capable intel hw wants timings in frames. Note though
3966 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3967 * timings, so we need to be careful not to clobber these.*/
3968 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3969 drm_mode_set_crtcinfo(adjusted_mode, 0);
3971 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3972 * with a hsync front porch of 0.
3974 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3975 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3981 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3983 return 400000; /* FIXME */
3986 static int i945_get_display_clock_speed(struct drm_device *dev)
3991 static int i915_get_display_clock_speed(struct drm_device *dev)
3996 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4001 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4005 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4007 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4010 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4011 case GC_DISPLAY_CLOCK_333_MHZ:
4014 case GC_DISPLAY_CLOCK_190_200_MHZ:
4020 static int i865_get_display_clock_speed(struct drm_device *dev)
4025 static int i855_get_display_clock_speed(struct drm_device *dev)
4028 /* Assume that the hardware is in the high speed state. This
4029 * should be the default.
4031 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4032 case GC_CLOCK_133_200:
4033 case GC_CLOCK_100_200:
4035 case GC_CLOCK_166_250:
4037 case GC_CLOCK_100_133:
4041 /* Shouldn't happen */
4045 static int i830_get_display_clock_speed(struct drm_device *dev)
4059 fdi_reduce_ratio(u32 *num, u32 *den)
4061 while (*num > 0xffffff || *den > 0xffffff) {
4068 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4069 int link_clock, struct fdi_m_n *m_n)
4071 m_n->tu = 64; /* default size */
4073 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4074 m_n->gmch_m = bits_per_pixel * pixel_clock;
4075 m_n->gmch_n = link_clock * nlanes * 8;
4076 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4078 m_n->link_m = pixel_clock;
4079 m_n->link_n = link_clock;
4080 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4083 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4085 if (i915_panel_use_ssc >= 0)
4086 return i915_panel_use_ssc != 0;
4087 return dev_priv->lvds_use_ssc
4088 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4092 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4093 * @crtc: CRTC structure
4094 * @mode: requested mode
4096 * A pipe may be connected to one or more outputs. Based on the depth of the
4097 * attached framebuffer, choose a good color depth to use on the pipe.
4099 * If possible, match the pipe depth to the fb depth. In some cases, this
4100 * isn't ideal, because the connected output supports a lesser or restricted
4101 * set of depths. Resolve that here:
4102 * LVDS typically supports only 6bpc, so clamp down in that case
4103 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4104 * Displays may support a restricted set as well, check EDID and clamp as
4106 * DP may want to dither down to 6bpc to fit larger modes
4109 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4110 * true if they don't match).
4112 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4113 struct drm_framebuffer *fb,
4114 unsigned int *pipe_bpp,
4115 struct drm_display_mode *mode)
4117 struct drm_device *dev = crtc->dev;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119 struct drm_connector *connector;
4120 struct intel_encoder *intel_encoder;
4121 unsigned int display_bpc = UINT_MAX, bpc;
4123 /* Walk the encoders & connectors on this crtc, get min bpc */
4124 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4126 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4127 unsigned int lvds_bpc;
4129 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4135 if (lvds_bpc < display_bpc) {
4136 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4137 display_bpc = lvds_bpc;
4142 /* Not one of the known troublemakers, check the EDID */
4143 list_for_each_entry(connector, &dev->mode_config.connector_list,
4145 if (connector->encoder != &intel_encoder->base)
4148 /* Don't use an invalid EDID bpc value */
4149 if (connector->display_info.bpc &&
4150 connector->display_info.bpc < display_bpc) {
4151 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4152 display_bpc = connector->display_info.bpc;
4157 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4158 * through, clamp it down. (Note: >12bpc will be caught below.)
4160 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4161 if (display_bpc > 8 && display_bpc < 12) {
4162 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4165 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4171 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4172 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4177 * We could just drive the pipe at the highest bpc all the time and
4178 * enable dithering as needed, but that costs bandwidth. So choose
4179 * the minimum value that expresses the full color range of the fb but
4180 * also stays within the max display bpc discovered above.
4183 switch (fb->depth) {
4185 bpc = 8; /* since we go through a colormap */
4189 bpc = 6; /* min is 18bpp */
4201 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4202 bpc = min((unsigned int)8, display_bpc);
4206 display_bpc = min(display_bpc, bpc);
4208 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4211 *pipe_bpp = display_bpc * 3;
4213 return display_bpc != bpc;
4216 static int vlv_get_refclk(struct drm_crtc *crtc)
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 int refclk = 27000; /* for DP & HDMI */
4222 return 100000; /* only one validated so far */
4224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4227 if (intel_panel_use_ssc(dev_priv))
4231 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4238 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4240 struct drm_device *dev = crtc->dev;
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4244 if (IS_VALLEYVIEW(dev)) {
4245 refclk = vlv_get_refclk(crtc);
4246 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4247 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4248 refclk = dev_priv->lvds_ssc_freq * 1000;
4249 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4251 } else if (!IS_GEN2(dev)) {
4260 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4261 intel_clock_t *clock)
4263 /* SDVO TV has fixed PLL values depend on its clock range,
4264 this mirrors vbios setting. */
4265 if (adjusted_mode->clock >= 100000
4266 && adjusted_mode->clock < 140500) {
4272 } else if (adjusted_mode->clock >= 140500
4273 && adjusted_mode->clock <= 200000) {
4282 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4283 intel_clock_t *clock,
4284 intel_clock_t *reduced_clock)
4286 struct drm_device *dev = crtc->dev;
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4289 int pipe = intel_crtc->pipe;
4292 if (IS_PINEVIEW(dev)) {
4293 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4295 fp2 = (1 << reduced_clock->n) << 16 |
4296 reduced_clock->m1 << 8 | reduced_clock->m2;
4298 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4300 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4304 I915_WRITE(FP0(pipe), fp);
4306 intel_crtc->lowfreq_avail = false;
4307 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4308 reduced_clock && i915_powersave) {
4309 I915_WRITE(FP1(pipe), fp2);
4310 intel_crtc->lowfreq_avail = true;
4312 I915_WRITE(FP1(pipe), fp);
4316 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4317 struct drm_display_mode *adjusted_mode)
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 int pipe = intel_crtc->pipe;
4325 temp = I915_READ(LVDS);
4326 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4328 temp |= LVDS_PIPEB_SELECT;
4330 temp &= ~LVDS_PIPEB_SELECT;
4332 /* set the corresponsding LVDS_BORDER bit */
4333 temp |= dev_priv->lvds_border_bits;
4334 /* Set the B0-B3 data pairs corresponding to whether we're going to
4335 * set the DPLLs for dual-channel mode or not.
4338 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4340 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4342 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4343 * appropriately here, but we need to look more thoroughly into how
4344 * panels behave in the two modes.
4346 /* set the dithering flag on LVDS as needed */
4347 if (INTEL_INFO(dev)->gen >= 4) {
4348 if (dev_priv->lvds_dither)
4349 temp |= LVDS_ENABLE_DITHER;
4351 temp &= ~LVDS_ENABLE_DITHER;
4353 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4354 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4355 temp |= LVDS_HSYNC_POLARITY;
4356 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4357 temp |= LVDS_VSYNC_POLARITY;
4358 I915_WRITE(LVDS, temp);
4361 static void vlv_update_pll(struct drm_crtc *crtc,
4362 struct drm_display_mode *mode,
4363 struct drm_display_mode *adjusted_mode,
4364 intel_clock_t *clock, intel_clock_t *reduced_clock,
4367 struct drm_device *dev = crtc->dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 int pipe = intel_crtc->pipe;
4371 u32 dpll, mdiv, pdiv;
4372 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4376 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4377 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4379 dpll = DPLL_VGA_MODE_DIS;
4380 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4381 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4382 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4384 I915_WRITE(DPLL(pipe), dpll);
4385 POSTING_READ(DPLL(pipe));
4394 * In Valleyview PLL and program lane counter registers are exposed
4395 * through DPIO interface
4397 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4398 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4399 mdiv |= ((bestn << DPIO_N_SHIFT));
4400 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4401 mdiv |= (1 << DPIO_K_SHIFT);
4402 mdiv |= DPIO_ENABLE_CALIBRATION;
4403 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4405 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4407 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4408 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4409 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4410 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4411 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4413 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4415 dpll |= DPLL_VCO_ENABLE;
4416 I915_WRITE(DPLL(pipe), dpll);
4417 POSTING_READ(DPLL(pipe));
4418 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4419 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4421 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4424 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4426 I915_WRITE(DPLL(pipe), dpll);
4428 /* Wait for the clocks to stabilize. */
4429 POSTING_READ(DPLL(pipe));
4434 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4436 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4440 I915_WRITE(DPLL_MD(pipe), temp);
4441 POSTING_READ(DPLL_MD(pipe));
4443 /* Now program lane control registers */
4444 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4445 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4450 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4452 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4457 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4461 static void i9xx_update_pll(struct drm_crtc *crtc,
4462 struct drm_display_mode *mode,
4463 struct drm_display_mode *adjusted_mode,
4464 intel_clock_t *clock, intel_clock_t *reduced_clock,
4467 struct drm_device *dev = crtc->dev;
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4470 int pipe = intel_crtc->pipe;
4474 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4476 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4477 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4479 dpll = DPLL_VGA_MODE_DIS;
4481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4482 dpll |= DPLLB_MODE_LVDS;
4484 dpll |= DPLLB_MODE_DAC_SERIAL;
4486 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4487 if (pixel_multiplier > 1) {
4488 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4489 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4491 dpll |= DPLL_DVO_HIGH_SPEED;
4493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4494 dpll |= DPLL_DVO_HIGH_SPEED;
4496 /* compute bitmask from p1 value */
4497 if (IS_PINEVIEW(dev))
4498 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4500 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4501 if (IS_G4X(dev) && reduced_clock)
4502 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4504 switch (clock->p2) {
4506 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4509 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4512 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4515 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4518 if (INTEL_INFO(dev)->gen >= 4)
4519 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4521 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4522 dpll |= PLL_REF_INPUT_TVCLKINBC;
4523 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4524 /* XXX: just matching BIOS for now */
4525 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4527 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4528 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4529 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4531 dpll |= PLL_REF_INPUT_DREFCLK;
4533 dpll |= DPLL_VCO_ENABLE;
4534 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4535 POSTING_READ(DPLL(pipe));
4538 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4539 * This is an exception to the general rule that mode_set doesn't turn
4542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4543 intel_update_lvds(crtc, clock, adjusted_mode);
4545 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4546 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4548 I915_WRITE(DPLL(pipe), dpll);
4550 /* Wait for the clocks to stabilize. */
4551 POSTING_READ(DPLL(pipe));
4554 if (INTEL_INFO(dev)->gen >= 4) {
4557 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4559 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4563 I915_WRITE(DPLL_MD(pipe), temp);
4565 /* The pixel multiplier can only be updated once the
4566 * DPLL is enabled and the clocks are stable.
4568 * So write it again.
4570 I915_WRITE(DPLL(pipe), dpll);
4574 static void i8xx_update_pll(struct drm_crtc *crtc,
4575 struct drm_display_mode *adjusted_mode,
4576 intel_clock_t *clock, intel_clock_t *reduced_clock,
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 int pipe = intel_crtc->pipe;
4585 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4587 dpll = DPLL_VGA_MODE_DIS;
4589 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593 dpll |= PLL_P1_DIVIDE_BY_TWO;
4595 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 dpll |= PLL_P2_DIVIDE_BY_4;
4600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4601 /* XXX: just matching BIOS for now */
4602 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4604 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4605 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4608 dpll |= PLL_REF_INPUT_DREFCLK;
4610 dpll |= DPLL_VCO_ENABLE;
4611 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4612 POSTING_READ(DPLL(pipe));
4615 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4616 * This is an exception to the general rule that mode_set doesn't turn
4619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4620 intel_update_lvds(crtc, clock, adjusted_mode);
4622 I915_WRITE(DPLL(pipe), dpll);
4624 /* Wait for the clocks to stabilize. */
4625 POSTING_READ(DPLL(pipe));
4628 /* The pixel multiplier can only be updated once the
4629 * DPLL is enabled and the clocks are stable.
4631 * So write it again.
4633 I915_WRITE(DPLL(pipe), dpll);
4636 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4637 struct drm_display_mode *mode,
4638 struct drm_display_mode *adjusted_mode)
4640 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 enum pipe pipe = intel_crtc->pipe;
4643 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4644 uint32_t vsyncshift;
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
4648 adjusted_mode->crtc_vtotal -= 1;
4649 adjusted_mode->crtc_vblank_end -= 1;
4650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4656 if (INTEL_INFO(dev)->gen > 3)
4657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4659 I915_WRITE(HTOTAL(cpu_transcoder),
4660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
4662 I915_WRITE(HBLANK(cpu_transcoder),
4663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665 I915_WRITE(HSYNC(cpu_transcoder),
4666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4669 I915_WRITE(VTOTAL(cpu_transcoder),
4670 (adjusted_mode->crtc_vdisplay - 1) |
4671 ((adjusted_mode->crtc_vtotal - 1) << 16));
4672 I915_WRITE(VBLANK(cpu_transcoder),
4673 (adjusted_mode->crtc_vblank_start - 1) |
4674 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4675 I915_WRITE(VSYNC(cpu_transcoder),
4676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4694 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4695 struct drm_display_mode *mode,
4696 struct drm_display_mode *adjusted_mode,
4698 struct drm_framebuffer *fb)
4700 struct drm_device *dev = crtc->dev;
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int pipe = intel_crtc->pipe;
4704 int plane = intel_crtc->plane;
4705 int refclk, num_connectors = 0;
4706 intel_clock_t clock, reduced_clock;
4707 u32 dspcntr, pipeconf;
4708 bool ok, has_reduced_clock = false, is_sdvo = false;
4709 bool is_lvds = false, is_tv = false, is_dp = false;
4710 struct intel_encoder *encoder;
4711 const intel_limit_t *limit;
4714 for_each_encoder_on_crtc(dev, crtc, encoder) {
4715 switch (encoder->type) {
4716 case INTEL_OUTPUT_LVDS:
4719 case INTEL_OUTPUT_SDVO:
4720 case INTEL_OUTPUT_HDMI:
4722 if (encoder->needs_tv_clock)
4725 case INTEL_OUTPUT_TVOUT:
4728 case INTEL_OUTPUT_DISPLAYPORT:
4736 refclk = i9xx_get_refclk(crtc, num_connectors);
4739 * Returns a set of divisors for the desired target clock with the given
4740 * refclk, or FALSE. The returned values represent the clock equation:
4741 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4743 limit = intel_limit(crtc, refclk);
4744 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4747 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4751 /* Ensure that the cursor is valid for the new mode before changing... */
4752 intel_crtc_update_cursor(crtc, true);
4754 if (is_lvds && dev_priv->lvds_downclock_avail) {
4756 * Ensure we match the reduced clock's P to the target clock.
4757 * If the clocks don't match, we can't switch the display clock
4758 * by using the FP0/FP1. In such case we will disable the LVDS
4759 * downclock feature.
4761 has_reduced_clock = limit->find_pll(limit, crtc,
4762 dev_priv->lvds_downclock,
4768 if (is_sdvo && is_tv)
4769 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4772 i8xx_update_pll(crtc, adjusted_mode, &clock,
4773 has_reduced_clock ? &reduced_clock : NULL,
4775 else if (IS_VALLEYVIEW(dev))
4776 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4777 has_reduced_clock ? &reduced_clock : NULL,
4780 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4781 has_reduced_clock ? &reduced_clock : NULL,
4784 /* setup pipeconf */
4785 pipeconf = I915_READ(PIPECONF(pipe));
4787 /* Set up the display plane register */
4788 dspcntr = DISPPLANE_GAMMA_ENABLE;
4791 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4793 dspcntr |= DISPPLANE_SEL_PIPE_B;
4795 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4796 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4799 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4803 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4804 pipeconf |= PIPECONF_DOUBLE_WIDE;
4806 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4809 /* default to 8bpc */
4810 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4812 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4813 pipeconf |= PIPECONF_BPP_6 |
4814 PIPECONF_DITHER_EN |
4815 PIPECONF_DITHER_TYPE_SP;
4819 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4820 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4821 pipeconf |= PIPECONF_BPP_6 |
4823 I965_PIPECONF_ACTIVE;
4827 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4828 drm_mode_debug_printmodeline(mode);
4830 if (HAS_PIPE_CXSR(dev)) {
4831 if (intel_crtc->lowfreq_avail) {
4832 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4833 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4835 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4836 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4840 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4841 if (!IS_GEN2(dev) &&
4842 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4843 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4845 pipeconf |= PIPECONF_PROGRESSIVE;
4847 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4849 /* pipesrc and dspsize control the size that is scaled from,
4850 * which should always be the user's requested size.
4852 I915_WRITE(DSPSIZE(plane),
4853 ((mode->vdisplay - 1) << 16) |
4854 (mode->hdisplay - 1));
4855 I915_WRITE(DSPPOS(plane), 0);
4857 I915_WRITE(PIPECONF(pipe), pipeconf);
4858 POSTING_READ(PIPECONF(pipe));
4859 intel_enable_pipe(dev_priv, pipe, false);
4861 intel_wait_for_vblank(dev, pipe);
4863 I915_WRITE(DSPCNTR(plane), dspcntr);
4864 POSTING_READ(DSPCNTR(plane));
4866 ret = intel_pipe_set_base(crtc, x, y, fb);
4868 intel_update_watermarks(dev);
4874 * Initialize reference clocks when the driver loads
4876 void ironlake_init_pch_refclk(struct drm_device *dev)
4878 struct drm_i915_private *dev_priv = dev->dev_private;
4879 struct drm_mode_config *mode_config = &dev->mode_config;
4880 struct intel_encoder *encoder;
4882 bool has_lvds = false;
4883 bool has_cpu_edp = false;
4884 bool has_pch_edp = false;
4885 bool has_panel = false;
4886 bool has_ck505 = false;
4887 bool can_ssc = false;
4889 /* We need to take the global config into account */
4890 list_for_each_entry(encoder, &mode_config->encoder_list,
4892 switch (encoder->type) {
4893 case INTEL_OUTPUT_LVDS:
4897 case INTEL_OUTPUT_EDP:
4899 if (intel_encoder_is_pch_edp(&encoder->base))
4907 if (HAS_PCH_IBX(dev)) {
4908 has_ck505 = dev_priv->display_clock_mode;
4909 can_ssc = has_ck505;
4915 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4916 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4919 /* Ironlake: try to setup display ref clock before DPLL
4920 * enabling. This is only under driver's control after
4921 * PCH B stepping, previous chipset stepping should be
4922 * ignoring this setting.
4924 temp = I915_READ(PCH_DREF_CONTROL);
4925 /* Always enable nonspread source */
4926 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4929 temp |= DREF_NONSPREAD_CK505_ENABLE;
4931 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4934 temp &= ~DREF_SSC_SOURCE_MASK;
4935 temp |= DREF_SSC_SOURCE_ENABLE;
4937 /* SSC must be turned on before enabling the CPU output */
4938 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4939 DRM_DEBUG_KMS("Using SSC on panel\n");
4940 temp |= DREF_SSC1_ENABLE;
4942 temp &= ~DREF_SSC1_ENABLE;
4944 /* Get SSC going before enabling the outputs */
4945 I915_WRITE(PCH_DREF_CONTROL, temp);
4946 POSTING_READ(PCH_DREF_CONTROL);
4949 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4951 /* Enable CPU source on CPU attached eDP */
4953 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4954 DRM_DEBUG_KMS("Using SSC on eDP\n");
4955 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4958 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4960 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4962 I915_WRITE(PCH_DREF_CONTROL, temp);
4963 POSTING_READ(PCH_DREF_CONTROL);
4966 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4968 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4970 /* Turn off CPU output */
4971 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4973 I915_WRITE(PCH_DREF_CONTROL, temp);
4974 POSTING_READ(PCH_DREF_CONTROL);
4977 /* Turn off the SSC source */
4978 temp &= ~DREF_SSC_SOURCE_MASK;
4979 temp |= DREF_SSC_SOURCE_DISABLE;
4982 temp &= ~ DREF_SSC1_ENABLE;
4984 I915_WRITE(PCH_DREF_CONTROL, temp);
4985 POSTING_READ(PCH_DREF_CONTROL);
4990 static int ironlake_get_refclk(struct drm_crtc *crtc)
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_encoder *encoder;
4995 struct intel_encoder *edp_encoder = NULL;
4996 int num_connectors = 0;
4997 bool is_lvds = false;
4999 for_each_encoder_on_crtc(dev, crtc, encoder) {
5000 switch (encoder->type) {
5001 case INTEL_OUTPUT_LVDS:
5004 case INTEL_OUTPUT_EDP:
5005 edp_encoder = encoder;
5011 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5012 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5013 dev_priv->lvds_ssc_freq);
5014 return dev_priv->lvds_ssc_freq * 1000;
5020 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5021 struct drm_display_mode *adjusted_mode,
5024 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5026 int pipe = intel_crtc->pipe;
5029 val = I915_READ(PIPECONF(pipe));
5031 val &= ~PIPE_BPC_MASK;
5032 switch (intel_crtc->bpp) {
5046 /* Case prevented by intel_choose_pipe_bpp_dither. */
5050 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5052 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5054 val &= ~PIPECONF_INTERLACE_MASK;
5055 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5056 val |= PIPECONF_INTERLACED_ILK;
5058 val |= PIPECONF_PROGRESSIVE;
5060 I915_WRITE(PIPECONF(pipe), val);
5061 POSTING_READ(PIPECONF(pipe));
5064 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5065 struct drm_display_mode *adjusted_mode,
5068 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5070 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5073 val = I915_READ(PIPECONF(cpu_transcoder));
5075 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5077 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5079 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5080 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5081 val |= PIPECONF_INTERLACED_ILK;
5083 val |= PIPECONF_PROGRESSIVE;
5085 I915_WRITE(PIPECONF(cpu_transcoder), val);
5086 POSTING_READ(PIPECONF(cpu_transcoder));
5089 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5090 struct drm_display_mode *adjusted_mode,
5091 intel_clock_t *clock,
5092 bool *has_reduced_clock,
5093 intel_clock_t *reduced_clock)
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 struct intel_encoder *intel_encoder;
5099 const intel_limit_t *limit;
5100 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5102 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5103 switch (intel_encoder->type) {
5104 case INTEL_OUTPUT_LVDS:
5107 case INTEL_OUTPUT_SDVO:
5108 case INTEL_OUTPUT_HDMI:
5110 if (intel_encoder->needs_tv_clock)
5113 case INTEL_OUTPUT_TVOUT:
5119 refclk = ironlake_get_refclk(crtc);
5122 * Returns a set of divisors for the desired target clock with the given
5123 * refclk, or FALSE. The returned values represent the clock equation:
5124 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5126 limit = intel_limit(crtc, refclk);
5127 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5132 if (is_lvds && dev_priv->lvds_downclock_avail) {
5134 * Ensure we match the reduced clock's P to the target clock.
5135 * If the clocks don't match, we can't switch the display clock
5136 * by using the FP0/FP1. In such case we will disable the LVDS
5137 * downclock feature.
5139 *has_reduced_clock = limit->find_pll(limit, crtc,
5140 dev_priv->lvds_downclock,
5146 if (is_sdvo && is_tv)
5147 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5152 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5157 temp = I915_READ(SOUTH_CHICKEN1);
5158 if (temp & FDI_BC_BIFURCATION_SELECT)
5161 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5162 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5164 temp |= FDI_BC_BIFURCATION_SELECT;
5165 DRM_DEBUG_KMS("enabling fdi C rx\n");
5166 I915_WRITE(SOUTH_CHICKEN1, temp);
5167 POSTING_READ(SOUTH_CHICKEN1);
5170 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5172 struct drm_device *dev = intel_crtc->base.dev;
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 struct intel_crtc *pipe_B_crtc =
5175 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5177 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5178 intel_crtc->pipe, intel_crtc->fdi_lanes);
5179 if (intel_crtc->fdi_lanes > 4) {
5180 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5181 intel_crtc->pipe, intel_crtc->fdi_lanes);
5182 /* Clamp lanes to avoid programming the hw with bogus values. */
5183 intel_crtc->fdi_lanes = 4;
5188 if (dev_priv->num_pipe == 2)
5191 switch (intel_crtc->pipe) {
5195 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5196 intel_crtc->fdi_lanes > 2) {
5197 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5198 intel_crtc->pipe, intel_crtc->fdi_lanes);
5199 /* Clamp lanes to avoid programming the hw with bogus values. */
5200 intel_crtc->fdi_lanes = 2;
5205 if (intel_crtc->fdi_lanes > 2)
5206 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5208 cpt_enable_fdi_bc_bifurcation(dev);
5212 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5213 if (intel_crtc->fdi_lanes > 2) {
5214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5215 intel_crtc->pipe, intel_crtc->fdi_lanes);
5216 /* Clamp lanes to avoid programming the hw with bogus values. */
5217 intel_crtc->fdi_lanes = 2;
5222 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5226 cpt_enable_fdi_bc_bifurcation(dev);
5234 static void ironlake_set_m_n(struct drm_crtc *crtc,
5235 struct drm_display_mode *mode,
5236 struct drm_display_mode *adjusted_mode)
5238 struct drm_device *dev = crtc->dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5241 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5242 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5243 struct fdi_m_n m_n = {0};
5244 int target_clock, pixel_multiplier, lane, link_bw;
5245 bool is_dp = false, is_cpu_edp = false;
5247 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5248 switch (intel_encoder->type) {
5249 case INTEL_OUTPUT_DISPLAYPORT:
5252 case INTEL_OUTPUT_EDP:
5254 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5256 edp_encoder = intel_encoder;
5262 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5264 /* CPU eDP doesn't require FDI link, so just set DP M/N
5265 according to current link config */
5267 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5269 /* FDI is a binary signal running at ~2.7GHz, encoding
5270 * each output octet as 10 bits. The actual frequency
5271 * is stored as a divider into a 100MHz clock, and the
5272 * mode pixel clock is stored in units of 1KHz.
5273 * Hence the bw of each lane in terms of the mode signal
5276 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5279 /* [e]DP over FDI requires target mode clock instead of link clock. */
5281 target_clock = intel_edp_target_clock(edp_encoder, mode);
5283 target_clock = mode->clock;
5285 target_clock = adjusted_mode->clock;
5289 * Account for spread spectrum to avoid
5290 * oversubscribing the link. Max center spread
5291 * is 2.5%; use 5% for safety's sake.
5293 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5294 lane = bps / (link_bw * 8) + 1;
5297 intel_crtc->fdi_lanes = lane;
5299 if (pixel_multiplier > 1)
5300 link_bw *= pixel_multiplier;
5301 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5304 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5305 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5306 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5307 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5310 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5311 struct drm_display_mode *adjusted_mode,
5312 intel_clock_t *clock, u32 fp)
5314 struct drm_crtc *crtc = &intel_crtc->base;
5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 struct intel_encoder *intel_encoder;
5319 int factor, pixel_multiplier, num_connectors = 0;
5320 bool is_lvds = false, is_sdvo = false, is_tv = false;
5321 bool is_dp = false, is_cpu_edp = false;
5323 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5324 switch (intel_encoder->type) {
5325 case INTEL_OUTPUT_LVDS:
5328 case INTEL_OUTPUT_SDVO:
5329 case INTEL_OUTPUT_HDMI:
5331 if (intel_encoder->needs_tv_clock)
5334 case INTEL_OUTPUT_TVOUT:
5337 case INTEL_OUTPUT_DISPLAYPORT:
5340 case INTEL_OUTPUT_EDP:
5342 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5350 /* Enable autotuning of the PLL clock (if permissible) */
5353 if ((intel_panel_use_ssc(dev_priv) &&
5354 dev_priv->lvds_ssc_freq == 100) ||
5355 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5357 } else if (is_sdvo && is_tv)
5360 if (clock->m < factor * clock->n)
5366 dpll |= DPLLB_MODE_LVDS;
5368 dpll |= DPLLB_MODE_DAC_SERIAL;
5370 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5371 if (pixel_multiplier > 1) {
5372 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5374 dpll |= DPLL_DVO_HIGH_SPEED;
5376 if (is_dp && !is_cpu_edp)
5377 dpll |= DPLL_DVO_HIGH_SPEED;
5379 /* compute bitmask from p1 value */
5380 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5382 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5384 switch (clock->p2) {
5386 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5389 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5392 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5395 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5399 if (is_sdvo && is_tv)
5400 dpll |= PLL_REF_INPUT_TVCLKINBC;
5402 /* XXX: just matching BIOS for now */
5403 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5405 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5406 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5408 dpll |= PLL_REF_INPUT_DREFCLK;
5413 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5414 struct drm_display_mode *mode,
5415 struct drm_display_mode *adjusted_mode,
5417 struct drm_framebuffer *fb)
5419 struct drm_device *dev = crtc->dev;
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5422 int pipe = intel_crtc->pipe;
5423 int plane = intel_crtc->plane;
5424 int num_connectors = 0;
5425 intel_clock_t clock, reduced_clock;
5426 u32 dpll, fp = 0, fp2 = 0;
5427 bool ok, has_reduced_clock = false;
5428 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5429 struct intel_encoder *encoder;
5432 bool dither, fdi_config_ok;
5434 for_each_encoder_on_crtc(dev, crtc, encoder) {
5435 switch (encoder->type) {
5436 case INTEL_OUTPUT_LVDS:
5439 case INTEL_OUTPUT_DISPLAYPORT:
5442 case INTEL_OUTPUT_EDP:
5444 if (!intel_encoder_is_pch_edp(&encoder->base))
5452 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5453 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5455 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5456 &has_reduced_clock, &reduced_clock);
5458 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5462 /* Ensure that the cursor is valid for the new mode before changing... */
5463 intel_crtc_update_cursor(crtc, true);
5465 /* determine panel color depth */
5466 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5468 if (is_lvds && dev_priv->lvds_dither)
5471 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5472 if (has_reduced_clock)
5473 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5476 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5478 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5479 drm_mode_debug_printmodeline(mode);
5481 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5483 struct intel_pch_pll *pll;
5485 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5487 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5492 intel_put_pch_pll(intel_crtc);
5494 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5495 * This is an exception to the general rule that mode_set doesn't turn
5499 temp = I915_READ(PCH_LVDS);
5500 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5501 if (HAS_PCH_CPT(dev)) {
5502 temp &= ~PORT_TRANS_SEL_MASK;
5503 temp |= PORT_TRANS_SEL_CPT(pipe);
5506 temp |= LVDS_PIPEB_SELECT;
5508 temp &= ~LVDS_PIPEB_SELECT;
5511 /* set the corresponsding LVDS_BORDER bit */
5512 temp |= dev_priv->lvds_border_bits;
5513 /* Set the B0-B3 data pairs corresponding to whether we're going to
5514 * set the DPLLs for dual-channel mode or not.
5517 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5519 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5521 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5522 * appropriately here, but we need to look more thoroughly into how
5523 * panels behave in the two modes.
5525 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5526 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5527 temp |= LVDS_HSYNC_POLARITY;
5528 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5529 temp |= LVDS_VSYNC_POLARITY;
5530 I915_WRITE(PCH_LVDS, temp);
5533 if (is_dp && !is_cpu_edp) {
5534 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5536 /* For non-DP output, clear any trans DP clock recovery setting.*/
5537 I915_WRITE(TRANSDATA_M1(pipe), 0);
5538 I915_WRITE(TRANSDATA_N1(pipe), 0);
5539 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5540 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5543 if (intel_crtc->pch_pll) {
5544 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5546 /* Wait for the clocks to stabilize. */
5547 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5550 /* The pixel multiplier can only be updated once the
5551 * DPLL is enabled and the clocks are stable.
5553 * So write it again.
5555 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5558 intel_crtc->lowfreq_avail = false;
5559 if (intel_crtc->pch_pll) {
5560 if (is_lvds && has_reduced_clock && i915_powersave) {
5561 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5562 intel_crtc->lowfreq_avail = true;
5564 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5568 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5570 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5571 * ironlake_check_fdi_lanes. */
5572 ironlake_set_m_n(crtc, mode, adjusted_mode);
5574 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5577 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5579 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5581 intel_wait_for_vblank(dev, pipe);
5583 /* Set up the display plane register */
5584 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5585 POSTING_READ(DSPCNTR(plane));
5587 ret = intel_pipe_set_base(crtc, x, y, fb);
5589 intel_update_watermarks(dev);
5591 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5593 return fdi_config_ok ? ret : -EINVAL;
5596 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5597 struct drm_display_mode *mode,
5598 struct drm_display_mode *adjusted_mode,
5600 struct drm_framebuffer *fb)
5602 struct drm_device *dev = crtc->dev;
5603 struct drm_i915_private *dev_priv = dev->dev_private;
5604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5605 int pipe = intel_crtc->pipe;
5606 int plane = intel_crtc->plane;
5607 int num_connectors = 0;
5608 intel_clock_t clock, reduced_clock;
5609 u32 dpll = 0, fp = 0, fp2 = 0;
5610 bool ok, has_reduced_clock = false;
5611 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5612 struct intel_encoder *encoder;
5617 for_each_encoder_on_crtc(dev, crtc, encoder) {
5618 switch (encoder->type) {
5619 case INTEL_OUTPUT_LVDS:
5622 case INTEL_OUTPUT_DISPLAYPORT:
5625 case INTEL_OUTPUT_EDP:
5627 if (!intel_encoder_is_pch_edp(&encoder->base))
5636 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5638 intel_crtc->cpu_transcoder = pipe;
5640 /* We are not sure yet this won't happen. */
5641 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5642 INTEL_PCH_TYPE(dev));
5644 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5645 num_connectors, pipe_name(pipe));
5647 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5648 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5650 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5652 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5655 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5656 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5660 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5665 /* Ensure that the cursor is valid for the new mode before changing... */
5666 intel_crtc_update_cursor(crtc, true);
5668 /* determine panel color depth */
5669 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5671 if (is_lvds && dev_priv->lvds_dither)
5674 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5675 drm_mode_debug_printmodeline(mode);
5677 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5678 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5679 if (has_reduced_clock)
5680 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5683 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5686 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5687 * own on pre-Haswell/LPT generation */
5689 struct intel_pch_pll *pll;
5691 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5693 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5698 intel_put_pch_pll(intel_crtc);
5700 /* The LVDS pin pair needs to be on before the DPLLs are
5701 * enabled. This is an exception to the general rule that
5702 * mode_set doesn't turn things on.
5705 temp = I915_READ(PCH_LVDS);
5706 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5707 if (HAS_PCH_CPT(dev)) {
5708 temp &= ~PORT_TRANS_SEL_MASK;
5709 temp |= PORT_TRANS_SEL_CPT(pipe);
5712 temp |= LVDS_PIPEB_SELECT;
5714 temp &= ~LVDS_PIPEB_SELECT;
5717 /* set the corresponsding LVDS_BORDER bit */
5718 temp |= dev_priv->lvds_border_bits;
5719 /* Set the B0-B3 data pairs corresponding to whether
5720 * we're going to set the DPLLs for dual-channel mode or
5724 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5726 temp &= ~(LVDS_B0B3_POWER_UP |
5727 LVDS_CLKB_POWER_UP);
5729 /* It would be nice to set 24 vs 18-bit mode
5730 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5731 * look more thoroughly into how panels behave in the
5734 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5735 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5736 temp |= LVDS_HSYNC_POLARITY;
5737 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5738 temp |= LVDS_VSYNC_POLARITY;
5739 I915_WRITE(PCH_LVDS, temp);
5743 if (is_dp && !is_cpu_edp) {
5744 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5746 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5747 /* For non-DP output, clear any trans DP clock recovery
5749 I915_WRITE(TRANSDATA_M1(pipe), 0);
5750 I915_WRITE(TRANSDATA_N1(pipe), 0);
5751 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5752 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5756 intel_crtc->lowfreq_avail = false;
5757 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5758 if (intel_crtc->pch_pll) {
5759 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5761 /* Wait for the clocks to stabilize. */
5762 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5765 /* The pixel multiplier can only be updated once the
5766 * DPLL is enabled and the clocks are stable.
5768 * So write it again.
5770 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5773 if (intel_crtc->pch_pll) {
5774 if (is_lvds && has_reduced_clock && i915_powersave) {
5775 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5776 intel_crtc->lowfreq_avail = true;
5778 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5783 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5785 if (!is_dp || is_cpu_edp)
5786 ironlake_set_m_n(crtc, mode, adjusted_mode);
5788 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5790 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5792 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5794 /* Set up the display plane register */
5795 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5796 POSTING_READ(DSPCNTR(plane));
5798 ret = intel_pipe_set_base(crtc, x, y, fb);
5800 intel_update_watermarks(dev);
5802 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5807 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5808 struct drm_display_mode *mode,
5809 struct drm_display_mode *adjusted_mode,
5811 struct drm_framebuffer *fb)
5813 struct drm_device *dev = crtc->dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 struct drm_encoder_helper_funcs *encoder_funcs;
5816 struct intel_encoder *encoder;
5817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5818 int pipe = intel_crtc->pipe;
5821 drm_vblank_pre_modeset(dev, pipe);
5823 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5825 drm_vblank_post_modeset(dev, pipe);
5830 for_each_encoder_on_crtc(dev, crtc, encoder) {
5831 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5832 encoder->base.base.id,
5833 drm_get_encoder_name(&encoder->base),
5834 mode->base.id, mode->name);
5835 encoder_funcs = encoder->base.helper_private;
5836 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5842 static bool intel_eld_uptodate(struct drm_connector *connector,
5843 int reg_eldv, uint32_t bits_eldv,
5844 int reg_elda, uint32_t bits_elda,
5847 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5848 uint8_t *eld = connector->eld;
5851 i = I915_READ(reg_eldv);
5860 i = I915_READ(reg_elda);
5862 I915_WRITE(reg_elda, i);
5864 for (i = 0; i < eld[2]; i++)
5865 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5871 static void g4x_write_eld(struct drm_connector *connector,
5872 struct drm_crtc *crtc)
5874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5875 uint8_t *eld = connector->eld;
5880 i = I915_READ(G4X_AUD_VID_DID);
5882 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5883 eldv = G4X_ELDV_DEVCL_DEVBLC;
5885 eldv = G4X_ELDV_DEVCTG;
5887 if (intel_eld_uptodate(connector,
5888 G4X_AUD_CNTL_ST, eldv,
5889 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5890 G4X_HDMIW_HDMIEDID))
5893 i = I915_READ(G4X_AUD_CNTL_ST);
5894 i &= ~(eldv | G4X_ELD_ADDR);
5895 len = (i >> 9) & 0x1f; /* ELD buffer size */
5896 I915_WRITE(G4X_AUD_CNTL_ST, i);
5901 len = min_t(uint8_t, eld[2], len);
5902 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5903 for (i = 0; i < len; i++)
5904 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5906 i = I915_READ(G4X_AUD_CNTL_ST);
5908 I915_WRITE(G4X_AUD_CNTL_ST, i);
5911 static void haswell_write_eld(struct drm_connector *connector,
5912 struct drm_crtc *crtc)
5914 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5915 uint8_t *eld = connector->eld;
5916 struct drm_device *dev = crtc->dev;
5920 int pipe = to_intel_crtc(crtc)->pipe;
5923 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5924 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5925 int aud_config = HSW_AUD_CFG(pipe);
5926 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5929 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5931 /* Audio output enable */
5932 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5933 tmp = I915_READ(aud_cntrl_st2);
5934 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5935 I915_WRITE(aud_cntrl_st2, tmp);
5937 /* Wait for 1 vertical blank */
5938 intel_wait_for_vblank(dev, pipe);
5940 /* Set ELD valid state */
5941 tmp = I915_READ(aud_cntrl_st2);
5942 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5943 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5944 I915_WRITE(aud_cntrl_st2, tmp);
5945 tmp = I915_READ(aud_cntrl_st2);
5946 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5948 /* Enable HDMI mode */
5949 tmp = I915_READ(aud_config);
5950 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5951 /* clear N_programing_enable and N_value_index */
5952 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5953 I915_WRITE(aud_config, tmp);
5955 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5957 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5959 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5960 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5961 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5962 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5964 I915_WRITE(aud_config, 0);
5966 if (intel_eld_uptodate(connector,
5967 aud_cntrl_st2, eldv,
5968 aud_cntl_st, IBX_ELD_ADDRESS,
5972 i = I915_READ(aud_cntrl_st2);
5974 I915_WRITE(aud_cntrl_st2, i);
5979 i = I915_READ(aud_cntl_st);
5980 i &= ~IBX_ELD_ADDRESS;
5981 I915_WRITE(aud_cntl_st, i);
5982 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5983 DRM_DEBUG_DRIVER("port num:%d\n", i);
5985 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5986 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5987 for (i = 0; i < len; i++)
5988 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5990 i = I915_READ(aud_cntrl_st2);
5992 I915_WRITE(aud_cntrl_st2, i);
5996 static void ironlake_write_eld(struct drm_connector *connector,
5997 struct drm_crtc *crtc)
5999 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6000 uint8_t *eld = connector->eld;
6008 int pipe = to_intel_crtc(crtc)->pipe;
6010 if (HAS_PCH_IBX(connector->dev)) {
6011 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6012 aud_config = IBX_AUD_CFG(pipe);
6013 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6014 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6016 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6017 aud_config = CPT_AUD_CFG(pipe);
6018 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6019 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6022 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6024 i = I915_READ(aud_cntl_st);
6025 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6027 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6028 /* operate blindly on all ports */
6029 eldv = IBX_ELD_VALIDB;
6030 eldv |= IBX_ELD_VALIDB << 4;
6031 eldv |= IBX_ELD_VALIDB << 8;
6033 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6034 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6037 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6038 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6039 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6040 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6042 I915_WRITE(aud_config, 0);
6044 if (intel_eld_uptodate(connector,
6045 aud_cntrl_st2, eldv,
6046 aud_cntl_st, IBX_ELD_ADDRESS,
6050 i = I915_READ(aud_cntrl_st2);
6052 I915_WRITE(aud_cntrl_st2, i);
6057 i = I915_READ(aud_cntl_st);
6058 i &= ~IBX_ELD_ADDRESS;
6059 I915_WRITE(aud_cntl_st, i);
6061 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6062 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6063 for (i = 0; i < len; i++)
6064 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6066 i = I915_READ(aud_cntrl_st2);
6068 I915_WRITE(aud_cntrl_st2, i);
6071 void intel_write_eld(struct drm_encoder *encoder,
6072 struct drm_display_mode *mode)
6074 struct drm_crtc *crtc = encoder->crtc;
6075 struct drm_connector *connector;
6076 struct drm_device *dev = encoder->dev;
6077 struct drm_i915_private *dev_priv = dev->dev_private;
6079 connector = drm_select_eld(encoder, mode);
6083 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6085 drm_get_connector_name(connector),
6086 connector->encoder->base.id,
6087 drm_get_encoder_name(connector->encoder));
6089 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6091 if (dev_priv->display.write_eld)
6092 dev_priv->display.write_eld(connector, crtc);
6095 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6096 void intel_crtc_load_lut(struct drm_crtc *crtc)
6098 struct drm_device *dev = crtc->dev;
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101 int palreg = PALETTE(intel_crtc->pipe);
6104 /* The clocks have to be on to load the palette. */
6105 if (!crtc->enabled || !intel_crtc->active)
6108 /* use legacy palette for Ironlake */
6109 if (HAS_PCH_SPLIT(dev))
6110 palreg = LGC_PALETTE(intel_crtc->pipe);
6112 for (i = 0; i < 256; i++) {
6113 I915_WRITE(palreg + 4 * i,
6114 (intel_crtc->lut_r[i] << 16) |
6115 (intel_crtc->lut_g[i] << 8) |
6116 intel_crtc->lut_b[i]);
6120 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6122 struct drm_device *dev = crtc->dev;
6123 struct drm_i915_private *dev_priv = dev->dev_private;
6124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125 bool visible = base != 0;
6128 if (intel_crtc->cursor_visible == visible)
6131 cntl = I915_READ(_CURACNTR);
6133 /* On these chipsets we can only modify the base whilst
6134 * the cursor is disabled.
6136 I915_WRITE(_CURABASE, base);
6138 cntl &= ~(CURSOR_FORMAT_MASK);
6139 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6140 cntl |= CURSOR_ENABLE |
6141 CURSOR_GAMMA_ENABLE |
6144 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6145 I915_WRITE(_CURACNTR, cntl);
6147 intel_crtc->cursor_visible = visible;
6150 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6152 struct drm_device *dev = crtc->dev;
6153 struct drm_i915_private *dev_priv = dev->dev_private;
6154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6155 int pipe = intel_crtc->pipe;
6156 bool visible = base != 0;
6158 if (intel_crtc->cursor_visible != visible) {
6159 uint32_t cntl = I915_READ(CURCNTR(pipe));
6161 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6162 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6163 cntl |= pipe << 28; /* Connect to correct pipe */
6165 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6166 cntl |= CURSOR_MODE_DISABLE;
6168 I915_WRITE(CURCNTR(pipe), cntl);
6170 intel_crtc->cursor_visible = visible;
6172 /* and commit changes on next vblank */
6173 I915_WRITE(CURBASE(pipe), base);
6176 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6178 struct drm_device *dev = crtc->dev;
6179 struct drm_i915_private *dev_priv = dev->dev_private;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 int pipe = intel_crtc->pipe;
6182 bool visible = base != 0;
6184 if (intel_crtc->cursor_visible != visible) {
6185 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6187 cntl &= ~CURSOR_MODE;
6188 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6190 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6191 cntl |= CURSOR_MODE_DISABLE;
6193 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6195 intel_crtc->cursor_visible = visible;
6197 /* and commit changes on next vblank */
6198 I915_WRITE(CURBASE_IVB(pipe), base);
6201 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6202 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6205 struct drm_device *dev = crtc->dev;
6206 struct drm_i915_private *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 int pipe = intel_crtc->pipe;
6209 int x = intel_crtc->cursor_x;
6210 int y = intel_crtc->cursor_y;
6216 if (on && crtc->enabled && crtc->fb) {
6217 base = intel_crtc->cursor_addr;
6218 if (x > (int) crtc->fb->width)
6221 if (y > (int) crtc->fb->height)
6227 if (x + intel_crtc->cursor_width < 0)
6230 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6233 pos |= x << CURSOR_X_SHIFT;
6236 if (y + intel_crtc->cursor_height < 0)
6239 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6242 pos |= y << CURSOR_Y_SHIFT;
6244 visible = base != 0;
6245 if (!visible && !intel_crtc->cursor_visible)
6248 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6249 I915_WRITE(CURPOS_IVB(pipe), pos);
6250 ivb_update_cursor(crtc, base);
6252 I915_WRITE(CURPOS(pipe), pos);
6253 if (IS_845G(dev) || IS_I865G(dev))
6254 i845_update_cursor(crtc, base);
6256 i9xx_update_cursor(crtc, base);
6260 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6261 struct drm_file *file,
6263 uint32_t width, uint32_t height)
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268 struct drm_i915_gem_object *obj;
6272 /* if we want to turn off the cursor ignore width and height */
6274 DRM_DEBUG_KMS("cursor off\n");
6277 mutex_lock(&dev->struct_mutex);
6281 /* Currently we only support 64x64 cursors */
6282 if (width != 64 || height != 64) {
6283 DRM_ERROR("we currently only support 64x64 cursors\n");
6287 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6288 if (&obj->base == NULL)
6291 if (obj->base.size < width * height * 4) {
6292 DRM_ERROR("buffer is to small\n");
6297 /* we only need to pin inside GTT if cursor is non-phy */
6298 mutex_lock(&dev->struct_mutex);
6299 if (!dev_priv->info->cursor_needs_physical) {
6300 if (obj->tiling_mode) {
6301 DRM_ERROR("cursor cannot be tiled\n");
6306 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6308 DRM_ERROR("failed to move cursor bo into the GTT\n");
6312 ret = i915_gem_object_put_fence(obj);
6314 DRM_ERROR("failed to release fence for cursor");
6318 addr = obj->gtt_offset;
6320 int align = IS_I830(dev) ? 16 * 1024 : 256;
6321 ret = i915_gem_attach_phys_object(dev, obj,
6322 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6325 DRM_ERROR("failed to attach phys object\n");
6328 addr = obj->phys_obj->handle->busaddr;
6332 I915_WRITE(CURSIZE, (height << 12) | width);
6335 if (intel_crtc->cursor_bo) {
6336 if (dev_priv->info->cursor_needs_physical) {
6337 if (intel_crtc->cursor_bo != obj)
6338 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6340 i915_gem_object_unpin(intel_crtc->cursor_bo);
6341 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6344 mutex_unlock(&dev->struct_mutex);
6346 intel_crtc->cursor_addr = addr;
6347 intel_crtc->cursor_bo = obj;
6348 intel_crtc->cursor_width = width;
6349 intel_crtc->cursor_height = height;
6351 intel_crtc_update_cursor(crtc, true);
6355 i915_gem_object_unpin(obj);
6357 mutex_unlock(&dev->struct_mutex);
6359 drm_gem_object_unreference_unlocked(&obj->base);
6363 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 intel_crtc->cursor_x = x;
6368 intel_crtc->cursor_y = y;
6370 intel_crtc_update_cursor(crtc, true);
6375 /** Sets the color ramps on behalf of RandR */
6376 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6377 u16 blue, int regno)
6379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381 intel_crtc->lut_r[regno] = red >> 8;
6382 intel_crtc->lut_g[regno] = green >> 8;
6383 intel_crtc->lut_b[regno] = blue >> 8;
6386 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6387 u16 *blue, int regno)
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6391 *red = intel_crtc->lut_r[regno] << 8;
6392 *green = intel_crtc->lut_g[regno] << 8;
6393 *blue = intel_crtc->lut_b[regno] << 8;
6396 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6397 u16 *blue, uint32_t start, uint32_t size)
6399 int end = (start + size > 256) ? 256 : start + size, i;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402 for (i = start; i < end; i++) {
6403 intel_crtc->lut_r[i] = red[i] >> 8;
6404 intel_crtc->lut_g[i] = green[i] >> 8;
6405 intel_crtc->lut_b[i] = blue[i] >> 8;
6408 intel_crtc_load_lut(crtc);
6412 * Get a pipe with a simple mode set on it for doing load-based monitor
6415 * It will be up to the load-detect code to adjust the pipe as appropriate for
6416 * its requirements. The pipe will be connected to no other encoders.
6418 * Currently this code will only succeed if there is a pipe with no encoders
6419 * configured for it. In the future, it could choose to temporarily disable
6420 * some outputs to free up a pipe for its use.
6422 * \return crtc, or NULL if no pipes are available.
6425 /* VESA 640x480x72Hz mode to set on the pipe */
6426 static struct drm_display_mode load_detect_mode = {
6427 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6428 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6431 static struct drm_framebuffer *
6432 intel_framebuffer_create(struct drm_device *dev,
6433 struct drm_mode_fb_cmd2 *mode_cmd,
6434 struct drm_i915_gem_object *obj)
6436 struct intel_framebuffer *intel_fb;
6439 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6441 drm_gem_object_unreference_unlocked(&obj->base);
6442 return ERR_PTR(-ENOMEM);
6445 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6447 drm_gem_object_unreference_unlocked(&obj->base);
6449 return ERR_PTR(ret);
6452 return &intel_fb->base;
6456 intel_framebuffer_pitch_for_width(int width, int bpp)
6458 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6459 return ALIGN(pitch, 64);
6463 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6465 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6466 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6469 static struct drm_framebuffer *
6470 intel_framebuffer_create_for_mode(struct drm_device *dev,
6471 struct drm_display_mode *mode,
6474 struct drm_i915_gem_object *obj;
6475 struct drm_mode_fb_cmd2 mode_cmd;
6477 obj = i915_gem_alloc_object(dev,
6478 intel_framebuffer_size_for_mode(mode, bpp));
6480 return ERR_PTR(-ENOMEM);
6482 mode_cmd.width = mode->hdisplay;
6483 mode_cmd.height = mode->vdisplay;
6484 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6486 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6488 return intel_framebuffer_create(dev, &mode_cmd, obj);
6491 static struct drm_framebuffer *
6492 mode_fits_in_fbdev(struct drm_device *dev,
6493 struct drm_display_mode *mode)
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 struct drm_i915_gem_object *obj;
6497 struct drm_framebuffer *fb;
6499 if (dev_priv->fbdev == NULL)
6502 obj = dev_priv->fbdev->ifb.obj;
6506 fb = &dev_priv->fbdev->ifb.base;
6507 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6508 fb->bits_per_pixel))
6511 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6517 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6518 struct drm_display_mode *mode,
6519 struct intel_load_detect_pipe *old)
6521 struct intel_crtc *intel_crtc;
6522 struct intel_encoder *intel_encoder =
6523 intel_attached_encoder(connector);
6524 struct drm_crtc *possible_crtc;
6525 struct drm_encoder *encoder = &intel_encoder->base;
6526 struct drm_crtc *crtc = NULL;
6527 struct drm_device *dev = encoder->dev;
6528 struct drm_framebuffer *fb;
6531 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6532 connector->base.id, drm_get_connector_name(connector),
6533 encoder->base.id, drm_get_encoder_name(encoder));
6536 * Algorithm gets a little messy:
6538 * - if the connector already has an assigned crtc, use it (but make
6539 * sure it's on first)
6541 * - try to find the first unused crtc that can drive this connector,
6542 * and use that if we find one
6545 /* See if we already have a CRTC for this connector */
6546 if (encoder->crtc) {
6547 crtc = encoder->crtc;
6549 old->dpms_mode = connector->dpms;
6550 old->load_detect_temp = false;
6552 /* Make sure the crtc and connector are running */
6553 if (connector->dpms != DRM_MODE_DPMS_ON)
6554 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6559 /* Find an unused one (if possible) */
6560 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6562 if (!(encoder->possible_crtcs & (1 << i)))
6564 if (!possible_crtc->enabled) {
6565 crtc = possible_crtc;
6571 * If we didn't find an unused CRTC, don't use any.
6574 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6578 intel_encoder->new_crtc = to_intel_crtc(crtc);
6579 to_intel_connector(connector)->new_encoder = intel_encoder;
6581 intel_crtc = to_intel_crtc(crtc);
6582 old->dpms_mode = connector->dpms;
6583 old->load_detect_temp = true;
6584 old->release_fb = NULL;
6587 mode = &load_detect_mode;
6589 /* We need a framebuffer large enough to accommodate all accesses
6590 * that the plane may generate whilst we perform load detection.
6591 * We can not rely on the fbcon either being present (we get called
6592 * during its initialisation to detect all boot displays, or it may
6593 * not even exist) or that it is large enough to satisfy the
6596 fb = mode_fits_in_fbdev(dev, mode);
6598 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6599 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6600 old->release_fb = fb;
6602 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6604 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6608 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6609 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6610 if (old->release_fb)
6611 old->release_fb->funcs->destroy(old->release_fb);
6615 /* let the connector get through one full cycle before testing */
6616 intel_wait_for_vblank(dev, intel_crtc->pipe);
6620 connector->encoder = NULL;
6621 encoder->crtc = NULL;
6625 void intel_release_load_detect_pipe(struct drm_connector *connector,
6626 struct intel_load_detect_pipe *old)
6628 struct intel_encoder *intel_encoder =
6629 intel_attached_encoder(connector);
6630 struct drm_encoder *encoder = &intel_encoder->base;
6632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6633 connector->base.id, drm_get_connector_name(connector),
6634 encoder->base.id, drm_get_encoder_name(encoder));
6636 if (old->load_detect_temp) {
6637 struct drm_crtc *crtc = encoder->crtc;
6639 to_intel_connector(connector)->new_encoder = NULL;
6640 intel_encoder->new_crtc = NULL;
6641 intel_set_mode(crtc, NULL, 0, 0, NULL);
6643 if (old->release_fb)
6644 old->release_fb->funcs->destroy(old->release_fb);
6649 /* Switch crtc and encoder back off if necessary */
6650 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6651 connector->funcs->dpms(connector, old->dpms_mode);
6654 /* Returns the clock of the currently programmed mode of the given pipe. */
6655 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659 int pipe = intel_crtc->pipe;
6660 u32 dpll = I915_READ(DPLL(pipe));
6662 intel_clock_t clock;
6664 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6665 fp = I915_READ(FP0(pipe));
6667 fp = I915_READ(FP1(pipe));
6669 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6670 if (IS_PINEVIEW(dev)) {
6671 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6672 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6674 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6675 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6678 if (!IS_GEN2(dev)) {
6679 if (IS_PINEVIEW(dev))
6680 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6681 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6684 DPLL_FPA01_P1_POST_DIV_SHIFT);
6686 switch (dpll & DPLL_MODE_MASK) {
6687 case DPLLB_MODE_DAC_SERIAL:
6688 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6691 case DPLLB_MODE_LVDS:
6692 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6696 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6697 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6701 /* XXX: Handle the 100Mhz refclk */
6702 intel_clock(dev, 96000, &clock);
6704 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6707 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6708 DPLL_FPA01_P1_POST_DIV_SHIFT);
6711 if ((dpll & PLL_REF_INPUT_MASK) ==
6712 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6713 /* XXX: might not be 66MHz */
6714 intel_clock(dev, 66000, &clock);
6716 intel_clock(dev, 48000, &clock);
6718 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6721 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6722 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6724 if (dpll & PLL_P2_DIVIDE_BY_4)
6729 intel_clock(dev, 48000, &clock);
6733 /* XXX: It would be nice to validate the clocks, but we can't reuse
6734 * i830PllIsValid() because it relies on the xf86_config connector
6735 * configuration being accurate, which it isn't necessarily.
6741 /** Returns the currently programmed mode of the given pipe. */
6742 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6743 struct drm_crtc *crtc)
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6747 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6748 struct drm_display_mode *mode;
6749 int htot = I915_READ(HTOTAL(cpu_transcoder));
6750 int hsync = I915_READ(HSYNC(cpu_transcoder));
6751 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6752 int vsync = I915_READ(VSYNC(cpu_transcoder));
6754 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6758 mode->clock = intel_crtc_clock_get(dev, crtc);
6759 mode->hdisplay = (htot & 0xffff) + 1;
6760 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6761 mode->hsync_start = (hsync & 0xffff) + 1;
6762 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6763 mode->vdisplay = (vtot & 0xffff) + 1;
6764 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6765 mode->vsync_start = (vsync & 0xffff) + 1;
6766 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6768 drm_mode_set_name(mode);
6773 static void intel_increase_pllclock(struct drm_crtc *crtc)
6775 struct drm_device *dev = crtc->dev;
6776 drm_i915_private_t *dev_priv = dev->dev_private;
6777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778 int pipe = intel_crtc->pipe;
6779 int dpll_reg = DPLL(pipe);
6782 if (HAS_PCH_SPLIT(dev))
6785 if (!dev_priv->lvds_downclock_avail)
6788 dpll = I915_READ(dpll_reg);
6789 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6790 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6792 assert_panel_unlocked(dev_priv, pipe);
6794 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6795 I915_WRITE(dpll_reg, dpll);
6796 intel_wait_for_vblank(dev, pipe);
6798 dpll = I915_READ(dpll_reg);
6799 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6800 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6804 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6806 struct drm_device *dev = crtc->dev;
6807 drm_i915_private_t *dev_priv = dev->dev_private;
6808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810 if (HAS_PCH_SPLIT(dev))
6813 if (!dev_priv->lvds_downclock_avail)
6817 * Since this is called by a timer, we should never get here in
6820 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6821 int pipe = intel_crtc->pipe;
6822 int dpll_reg = DPLL(pipe);
6825 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6827 assert_panel_unlocked(dev_priv, pipe);
6829 dpll = I915_READ(dpll_reg);
6830 dpll |= DISPLAY_RATE_SELECT_FPA1;
6831 I915_WRITE(dpll_reg, dpll);
6832 intel_wait_for_vblank(dev, pipe);
6833 dpll = I915_READ(dpll_reg);
6834 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6835 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6840 void intel_mark_busy(struct drm_device *dev)
6842 i915_update_gfx_val(dev->dev_private);
6845 void intel_mark_idle(struct drm_device *dev)
6849 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6851 struct drm_device *dev = obj->base.dev;
6852 struct drm_crtc *crtc;
6854 if (!i915_powersave)
6857 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6861 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6862 intel_increase_pllclock(crtc);
6866 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6868 struct drm_device *dev = obj->base.dev;
6869 struct drm_crtc *crtc;
6871 if (!i915_powersave)
6874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6878 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6879 intel_decrease_pllclock(crtc);
6883 static void intel_crtc_destroy(struct drm_crtc *crtc)
6885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6886 struct drm_device *dev = crtc->dev;
6887 struct intel_unpin_work *work;
6888 unsigned long flags;
6890 spin_lock_irqsave(&dev->event_lock, flags);
6891 work = intel_crtc->unpin_work;
6892 intel_crtc->unpin_work = NULL;
6893 spin_unlock_irqrestore(&dev->event_lock, flags);
6896 cancel_work_sync(&work->work);
6900 drm_crtc_cleanup(crtc);
6905 static void intel_unpin_work_fn(struct work_struct *__work)
6907 struct intel_unpin_work *work =
6908 container_of(__work, struct intel_unpin_work, work);
6910 mutex_lock(&work->dev->struct_mutex);
6911 intel_unpin_fb_obj(work->old_fb_obj);
6912 drm_gem_object_unreference(&work->pending_flip_obj->base);
6913 drm_gem_object_unreference(&work->old_fb_obj->base);
6915 intel_update_fbc(work->dev);
6916 mutex_unlock(&work->dev->struct_mutex);
6920 static void do_intel_finish_page_flip(struct drm_device *dev,
6921 struct drm_crtc *crtc)
6923 drm_i915_private_t *dev_priv = dev->dev_private;
6924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6925 struct intel_unpin_work *work;
6926 struct drm_i915_gem_object *obj;
6927 struct drm_pending_vblank_event *e;
6928 struct timeval tvbl;
6929 unsigned long flags;
6931 /* Ignore early vblank irqs */
6932 if (intel_crtc == NULL)
6935 spin_lock_irqsave(&dev->event_lock, flags);
6936 work = intel_crtc->unpin_work;
6937 if (work == NULL || !work->pending) {
6938 spin_unlock_irqrestore(&dev->event_lock, flags);
6942 intel_crtc->unpin_work = NULL;
6946 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6948 e->event.tv_sec = tvbl.tv_sec;
6949 e->event.tv_usec = tvbl.tv_usec;
6951 list_add_tail(&e->base.link,
6952 &e->base.file_priv->event_list);
6953 wake_up_interruptible(&e->base.file_priv->event_wait);
6956 drm_vblank_put(dev, intel_crtc->pipe);
6958 spin_unlock_irqrestore(&dev->event_lock, flags);
6960 obj = work->old_fb_obj;
6962 atomic_clear_mask(1 << intel_crtc->plane,
6963 &obj->pending_flip.counter);
6965 wake_up(&dev_priv->pending_flip_queue);
6966 schedule_work(&work->work);
6968 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6971 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6976 do_intel_finish_page_flip(dev, crtc);
6979 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6981 drm_i915_private_t *dev_priv = dev->dev_private;
6982 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6984 do_intel_finish_page_flip(dev, crtc);
6987 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6989 drm_i915_private_t *dev_priv = dev->dev_private;
6990 struct intel_crtc *intel_crtc =
6991 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6992 unsigned long flags;
6994 spin_lock_irqsave(&dev->event_lock, flags);
6995 if (intel_crtc->unpin_work) {
6996 if ((++intel_crtc->unpin_work->pending) > 1)
6997 DRM_ERROR("Prepared flip multiple times\n");
6999 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7001 spin_unlock_irqrestore(&dev->event_lock, flags);
7004 static int intel_gen2_queue_flip(struct drm_device *dev,
7005 struct drm_crtc *crtc,
7006 struct drm_framebuffer *fb,
7007 struct drm_i915_gem_object *obj)
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7012 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7015 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7019 ret = intel_ring_begin(ring, 6);
7023 /* Can't queue multiple flips, so wait for the previous
7024 * one to finish before executing the next.
7026 if (intel_crtc->plane)
7027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7030 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7031 intel_ring_emit(ring, MI_NOOP);
7032 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7033 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7034 intel_ring_emit(ring, fb->pitches[0]);
7035 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7036 intel_ring_emit(ring, 0); /* aux display base address, unused */
7037 intel_ring_advance(ring);
7041 intel_unpin_fb_obj(obj);
7046 static int intel_gen3_queue_flip(struct drm_device *dev,
7047 struct drm_crtc *crtc,
7048 struct drm_framebuffer *fb,
7049 struct drm_i915_gem_object *obj)
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7057 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7061 ret = intel_ring_begin(ring, 6);
7065 if (intel_crtc->plane)
7066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7069 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7070 intel_ring_emit(ring, MI_NOOP);
7071 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7073 intel_ring_emit(ring, fb->pitches[0]);
7074 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7075 intel_ring_emit(ring, MI_NOOP);
7077 intel_ring_advance(ring);
7081 intel_unpin_fb_obj(obj);
7086 static int intel_gen4_queue_flip(struct drm_device *dev,
7087 struct drm_crtc *crtc,
7088 struct drm_framebuffer *fb,
7089 struct drm_i915_gem_object *obj)
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7093 uint32_t pf, pipesrc;
7094 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7097 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7101 ret = intel_ring_begin(ring, 4);
7105 /* i965+ uses the linear or tiled offsets from the
7106 * Display Registers (which do not change across a page-flip)
7107 * so we need only reprogram the base address.
7109 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7110 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7111 intel_ring_emit(ring, fb->pitches[0]);
7112 intel_ring_emit(ring,
7113 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7116 /* XXX Enabling the panel-fitter across page-flip is so far
7117 * untested on non-native modes, so ignore it for now.
7118 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7121 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7122 intel_ring_emit(ring, pf | pipesrc);
7123 intel_ring_advance(ring);
7127 intel_unpin_fb_obj(obj);
7132 static int intel_gen6_queue_flip(struct drm_device *dev,
7133 struct drm_crtc *crtc,
7134 struct drm_framebuffer *fb,
7135 struct drm_i915_gem_object *obj)
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7139 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7140 uint32_t pf, pipesrc;
7143 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7147 ret = intel_ring_begin(ring, 4);
7151 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7152 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7153 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7154 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7156 /* Contrary to the suggestions in the documentation,
7157 * "Enable Panel Fitter" does not seem to be required when page
7158 * flipping with a non-native mode, and worse causes a normal
7160 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7163 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7164 intel_ring_emit(ring, pf | pipesrc);
7165 intel_ring_advance(ring);
7169 intel_unpin_fb_obj(obj);
7175 * On gen7 we currently use the blit ring because (in early silicon at least)
7176 * the render ring doesn't give us interrpts for page flip completion, which
7177 * means clients will hang after the first flip is queued. Fortunately the
7178 * blit ring generates interrupts properly, so use it instead.
7180 static int intel_gen7_queue_flip(struct drm_device *dev,
7181 struct drm_crtc *crtc,
7182 struct drm_framebuffer *fb,
7183 struct drm_i915_gem_object *obj)
7185 struct drm_i915_private *dev_priv = dev->dev_private;
7186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7187 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7188 uint32_t plane_bit = 0;
7191 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7195 switch(intel_crtc->plane) {
7197 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7200 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7203 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7206 WARN_ONCE(1, "unknown plane in flip command\n");
7211 ret = intel_ring_begin(ring, 4);
7215 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7216 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7217 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7218 intel_ring_emit(ring, (MI_NOOP));
7219 intel_ring_advance(ring);
7223 intel_unpin_fb_obj(obj);
7228 static int intel_default_queue_flip(struct drm_device *dev,
7229 struct drm_crtc *crtc,
7230 struct drm_framebuffer *fb,
7231 struct drm_i915_gem_object *obj)
7236 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7237 struct drm_framebuffer *fb,
7238 struct drm_pending_vblank_event *event)
7240 struct drm_device *dev = crtc->dev;
7241 struct drm_i915_private *dev_priv = dev->dev_private;
7242 struct intel_framebuffer *intel_fb;
7243 struct drm_i915_gem_object *obj;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245 struct intel_unpin_work *work;
7246 unsigned long flags;
7249 /* Can't change pixel format via MI display flips. */
7250 if (fb->pixel_format != crtc->fb->pixel_format)
7254 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7255 * Note that pitch changes could also affect these register.
7257 if (INTEL_INFO(dev)->gen > 3 &&
7258 (fb->offsets[0] != crtc->fb->offsets[0] ||
7259 fb->pitches[0] != crtc->fb->pitches[0]))
7262 work = kzalloc(sizeof *work, GFP_KERNEL);
7266 work->event = event;
7267 work->dev = crtc->dev;
7268 intel_fb = to_intel_framebuffer(crtc->fb);
7269 work->old_fb_obj = intel_fb->obj;
7270 INIT_WORK(&work->work, intel_unpin_work_fn);
7272 ret = drm_vblank_get(dev, intel_crtc->pipe);
7276 /* We borrow the event spin lock for protecting unpin_work */
7277 spin_lock_irqsave(&dev->event_lock, flags);
7278 if (intel_crtc->unpin_work) {
7279 spin_unlock_irqrestore(&dev->event_lock, flags);
7281 drm_vblank_put(dev, intel_crtc->pipe);
7283 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7286 intel_crtc->unpin_work = work;
7287 spin_unlock_irqrestore(&dev->event_lock, flags);
7289 intel_fb = to_intel_framebuffer(fb);
7290 obj = intel_fb->obj;
7292 ret = i915_mutex_lock_interruptible(dev);
7296 /* Reference the objects for the scheduled work. */
7297 drm_gem_object_reference(&work->old_fb_obj->base);
7298 drm_gem_object_reference(&obj->base);
7302 work->pending_flip_obj = obj;
7304 work->enable_stall_check = true;
7306 /* Block clients from rendering to the new back buffer until
7307 * the flip occurs and the object is no longer visible.
7309 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7311 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7313 goto cleanup_pending;
7315 intel_disable_fbc(dev);
7316 intel_mark_fb_busy(obj);
7317 mutex_unlock(&dev->struct_mutex);
7319 trace_i915_flip_request(intel_crtc->plane, obj);
7324 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7325 drm_gem_object_unreference(&work->old_fb_obj->base);
7326 drm_gem_object_unreference(&obj->base);
7327 mutex_unlock(&dev->struct_mutex);
7330 spin_lock_irqsave(&dev->event_lock, flags);
7331 intel_crtc->unpin_work = NULL;
7332 spin_unlock_irqrestore(&dev->event_lock, flags);
7334 drm_vblank_put(dev, intel_crtc->pipe);
7341 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7342 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7343 .load_lut = intel_crtc_load_lut,
7344 .disable = intel_crtc_noop,
7347 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7349 struct intel_encoder *other_encoder;
7350 struct drm_crtc *crtc = &encoder->new_crtc->base;
7355 list_for_each_entry(other_encoder,
7356 &crtc->dev->mode_config.encoder_list,
7359 if (&other_encoder->new_crtc->base != crtc ||
7360 encoder == other_encoder)
7369 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7370 struct drm_crtc *crtc)
7372 struct drm_device *dev;
7373 struct drm_crtc *tmp;
7376 WARN(!crtc, "checking null crtc?\n");
7380 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7386 if (encoder->possible_crtcs & crtc_mask)
7392 * intel_modeset_update_staged_output_state
7394 * Updates the staged output configuration state, e.g. after we've read out the
7397 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7399 struct intel_encoder *encoder;
7400 struct intel_connector *connector;
7402 list_for_each_entry(connector, &dev->mode_config.connector_list,
7404 connector->new_encoder =
7405 to_intel_encoder(connector->base.encoder);
7408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7411 to_intel_crtc(encoder->base.crtc);
7416 * intel_modeset_commit_output_state
7418 * This function copies the stage display pipe configuration to the real one.
7420 static void intel_modeset_commit_output_state(struct drm_device *dev)
7422 struct intel_encoder *encoder;
7423 struct intel_connector *connector;
7425 list_for_each_entry(connector, &dev->mode_config.connector_list,
7427 connector->base.encoder = &connector->new_encoder->base;
7430 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7432 encoder->base.crtc = &encoder->new_crtc->base;
7436 static struct drm_display_mode *
7437 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7438 struct drm_display_mode *mode)
7440 struct drm_device *dev = crtc->dev;
7441 struct drm_display_mode *adjusted_mode;
7442 struct drm_encoder_helper_funcs *encoder_funcs;
7443 struct intel_encoder *encoder;
7445 adjusted_mode = drm_mode_duplicate(dev, mode);
7447 return ERR_PTR(-ENOMEM);
7449 /* Pass our mode to the connectors and the CRTC to give them a chance to
7450 * adjust it according to limitations or connector properties, and also
7451 * a chance to reject the mode entirely.
7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7456 if (&encoder->new_crtc->base != crtc)
7458 encoder_funcs = encoder->base.helper_private;
7459 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7461 DRM_DEBUG_KMS("Encoder fixup failed\n");
7466 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7467 DRM_DEBUG_KMS("CRTC fixup failed\n");
7470 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7472 return adjusted_mode;
7474 drm_mode_destroy(dev, adjusted_mode);
7475 return ERR_PTR(-EINVAL);
7478 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7479 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7481 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7482 unsigned *prepare_pipes, unsigned *disable_pipes)
7484 struct intel_crtc *intel_crtc;
7485 struct drm_device *dev = crtc->dev;
7486 struct intel_encoder *encoder;
7487 struct intel_connector *connector;
7488 struct drm_crtc *tmp_crtc;
7490 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7492 /* Check which crtcs have changed outputs connected to them, these need
7493 * to be part of the prepare_pipes mask. We don't (yet) support global
7494 * modeset across multiple crtcs, so modeset_pipes will only have one
7495 * bit set at most. */
7496 list_for_each_entry(connector, &dev->mode_config.connector_list,
7498 if (connector->base.encoder == &connector->new_encoder->base)
7501 if (connector->base.encoder) {
7502 tmp_crtc = connector->base.encoder->crtc;
7504 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7507 if (connector->new_encoder)
7509 1 << connector->new_encoder->new_crtc->pipe;
7512 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7514 if (encoder->base.crtc == &encoder->new_crtc->base)
7517 if (encoder->base.crtc) {
7518 tmp_crtc = encoder->base.crtc;
7520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7523 if (encoder->new_crtc)
7524 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7527 /* Check for any pipes that will be fully disabled ... */
7528 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7532 /* Don't try to disable disabled crtcs. */
7533 if (!intel_crtc->base.enabled)
7536 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7538 if (encoder->new_crtc == intel_crtc)
7543 *disable_pipes |= 1 << intel_crtc->pipe;
7547 /* set_mode is also used to update properties on life display pipes. */
7548 intel_crtc = to_intel_crtc(crtc);
7550 *prepare_pipes |= 1 << intel_crtc->pipe;
7552 /* We only support modeset on one single crtc, hence we need to do that
7553 * only for the passed in crtc iff we change anything else than just
7556 * This is actually not true, to be fully compatible with the old crtc
7557 * helper we automatically disable _any_ output (i.e. doesn't need to be
7558 * connected to the crtc we're modesetting on) if it's disconnected.
7559 * Which is a rather nutty api (since changed the output configuration
7560 * without userspace's explicit request can lead to confusion), but
7561 * alas. Hence we currently need to modeset on all pipes we prepare. */
7563 *modeset_pipes = *prepare_pipes;
7565 /* ... and mask these out. */
7566 *modeset_pipes &= ~(*disable_pipes);
7567 *prepare_pipes &= ~(*disable_pipes);
7570 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7572 struct drm_encoder *encoder;
7573 struct drm_device *dev = crtc->dev;
7575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7576 if (encoder->crtc == crtc)
7583 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7585 struct intel_encoder *intel_encoder;
7586 struct intel_crtc *intel_crtc;
7587 struct drm_connector *connector;
7589 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7591 if (!intel_encoder->base.crtc)
7594 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7596 if (prepare_pipes & (1 << intel_crtc->pipe))
7597 intel_encoder->connectors_active = false;
7600 intel_modeset_commit_output_state(dev);
7602 /* Update computed state. */
7603 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7605 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7609 if (!connector->encoder || !connector->encoder->crtc)
7612 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7614 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7615 struct drm_property *dpms_property =
7616 dev->mode_config.dpms_property;
7618 connector->dpms = DRM_MODE_DPMS_ON;
7619 drm_connector_property_set_value(connector,
7623 intel_encoder = to_intel_encoder(connector->encoder);
7624 intel_encoder->connectors_active = true;
7630 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7631 list_for_each_entry((intel_crtc), \
7632 &(dev)->mode_config.crtc_list, \
7634 if (mask & (1 <<(intel_crtc)->pipe)) \
7637 intel_modeset_check_state(struct drm_device *dev)
7639 struct intel_crtc *crtc;
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7645 /* This also checks the encoder/connector hw state with the
7646 * ->get_hw_state callbacks. */
7647 intel_connector_check_state(connector);
7649 WARN(&connector->new_encoder->base != connector->base.encoder,
7650 "connector's staged encoder doesn't match current encoder\n");
7653 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7655 bool enabled = false;
7656 bool active = false;
7657 enum pipe pipe, tracked_pipe;
7659 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7660 encoder->base.base.id,
7661 drm_get_encoder_name(&encoder->base));
7663 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7664 "encoder's stage crtc doesn't match current crtc\n");
7665 WARN(encoder->connectors_active && !encoder->base.crtc,
7666 "encoder's active_connectors set, but no crtc\n");
7668 list_for_each_entry(connector, &dev->mode_config.connector_list,
7670 if (connector->base.encoder != &encoder->base)
7673 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7676 WARN(!!encoder->base.crtc != enabled,
7677 "encoder's enabled state mismatch "
7678 "(expected %i, found %i)\n",
7679 !!encoder->base.crtc, enabled);
7680 WARN(active && !encoder->base.crtc,
7681 "active encoder with no crtc\n");
7683 WARN(encoder->connectors_active != active,
7684 "encoder's computed active state doesn't match tracked active state "
7685 "(expected %i, found %i)\n", active, encoder->connectors_active);
7687 active = encoder->get_hw_state(encoder, &pipe);
7688 WARN(active != encoder->connectors_active,
7689 "encoder's hw state doesn't match sw tracking "
7690 "(expected %i, found %i)\n",
7691 encoder->connectors_active, active);
7693 if (!encoder->base.crtc)
7696 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7697 WARN(active && pipe != tracked_pipe,
7698 "active encoder's pipe doesn't match"
7699 "(expected %i, found %i)\n",
7700 tracked_pipe, pipe);
7704 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7706 bool enabled = false;
7707 bool active = false;
7709 DRM_DEBUG_KMS("[CRTC:%d]\n",
7710 crtc->base.base.id);
7712 WARN(crtc->active && !crtc->base.enabled,
7713 "active crtc, but not enabled in sw tracking\n");
7715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7717 if (encoder->base.crtc != &crtc->base)
7720 if (encoder->connectors_active)
7723 WARN(active != crtc->active,
7724 "crtc's computed active state doesn't match tracked active state "
7725 "(expected %i, found %i)\n", active, crtc->active);
7726 WARN(enabled != crtc->base.enabled,
7727 "crtc's computed enabled state doesn't match tracked enabled state "
7728 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7730 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7734 bool intel_set_mode(struct drm_crtc *crtc,
7735 struct drm_display_mode *mode,
7736 int x, int y, struct drm_framebuffer *fb)
7738 struct drm_device *dev = crtc->dev;
7739 drm_i915_private_t *dev_priv = dev->dev_private;
7740 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7741 struct intel_crtc *intel_crtc;
7742 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7745 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7746 &prepare_pipes, &disable_pipes);
7748 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7749 modeset_pipes, prepare_pipes, disable_pipes);
7751 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7752 intel_crtc_disable(&intel_crtc->base);
7754 saved_hwmode = crtc->hwmode;
7755 saved_mode = crtc->mode;
7757 /* Hack: Because we don't (yet) support global modeset on multiple
7758 * crtcs, we don't keep track of the new mode for more than one crtc.
7759 * Hence simply check whether any bit is set in modeset_pipes in all the
7760 * pieces of code that are not yet converted to deal with mutliple crtcs
7761 * changing their mode at the same time. */
7762 adjusted_mode = NULL;
7763 if (modeset_pipes) {
7764 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7765 if (IS_ERR(adjusted_mode)) {
7770 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7771 if (intel_crtc->base.enabled)
7772 dev_priv->display.crtc_disable(&intel_crtc->base);
7775 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7776 * to set it here already despite that we pass it down the callchain.
7781 /* Only after disabling all output pipelines that will be changed can we
7782 * update the the output configuration. */
7783 intel_modeset_update_state(dev, prepare_pipes);
7785 if (dev_priv->display.modeset_global_resources)
7786 dev_priv->display.modeset_global_resources(dev);
7788 /* Set up the DPLL and any encoders state that needs to adjust or depend
7791 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7792 ret = !intel_crtc_mode_set(&intel_crtc->base,
7793 mode, adjusted_mode,
7799 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7800 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7801 dev_priv->display.crtc_enable(&intel_crtc->base);
7803 if (modeset_pipes) {
7804 /* Store real post-adjustment hardware mode. */
7805 crtc->hwmode = *adjusted_mode;
7807 /* Calculate and store various constants which
7808 * are later needed by vblank and swap-completion
7809 * timestamping. They are derived from true hwmode.
7811 drm_calc_timestamping_constants(crtc);
7814 /* FIXME: add subpixel order */
7816 drm_mode_destroy(dev, adjusted_mode);
7817 if (!ret && crtc->enabled) {
7818 crtc->hwmode = saved_hwmode;
7819 crtc->mode = saved_mode;
7821 intel_modeset_check_state(dev);
7827 #undef for_each_intel_crtc_masked
7829 static void intel_set_config_free(struct intel_set_config *config)
7834 kfree(config->save_connector_encoders);
7835 kfree(config->save_encoder_crtcs);
7839 static int intel_set_config_save_state(struct drm_device *dev,
7840 struct intel_set_config *config)
7842 struct drm_encoder *encoder;
7843 struct drm_connector *connector;
7846 config->save_encoder_crtcs =
7847 kcalloc(dev->mode_config.num_encoder,
7848 sizeof(struct drm_crtc *), GFP_KERNEL);
7849 if (!config->save_encoder_crtcs)
7852 config->save_connector_encoders =
7853 kcalloc(dev->mode_config.num_connector,
7854 sizeof(struct drm_encoder *), GFP_KERNEL);
7855 if (!config->save_connector_encoders)
7858 /* Copy data. Note that driver private data is not affected.
7859 * Should anything bad happen only the expected state is
7860 * restored, not the drivers personal bookkeeping.
7863 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7864 config->save_encoder_crtcs[count++] = encoder->crtc;
7868 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7869 config->save_connector_encoders[count++] = connector->encoder;
7875 static void intel_set_config_restore_state(struct drm_device *dev,
7876 struct intel_set_config *config)
7878 struct intel_encoder *encoder;
7879 struct intel_connector *connector;
7883 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7885 to_intel_crtc(config->save_encoder_crtcs[count++]);
7889 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7890 connector->new_encoder =
7891 to_intel_encoder(config->save_connector_encoders[count++]);
7896 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7897 struct intel_set_config *config)
7900 /* We should be able to check here if the fb has the same properties
7901 * and then just flip_or_move it */
7902 if (set->crtc->fb != set->fb) {
7903 /* If we have no fb then treat it as a full mode set */
7904 if (set->crtc->fb == NULL) {
7905 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7906 config->mode_changed = true;
7907 } else if (set->fb == NULL) {
7908 config->mode_changed = true;
7909 } else if (set->fb->depth != set->crtc->fb->depth) {
7910 config->mode_changed = true;
7911 } else if (set->fb->bits_per_pixel !=
7912 set->crtc->fb->bits_per_pixel) {
7913 config->mode_changed = true;
7915 config->fb_changed = true;
7918 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7919 config->fb_changed = true;
7921 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7922 DRM_DEBUG_KMS("modes are different, full mode set\n");
7923 drm_mode_debug_printmodeline(&set->crtc->mode);
7924 drm_mode_debug_printmodeline(set->mode);
7925 config->mode_changed = true;
7930 intel_modeset_stage_output_state(struct drm_device *dev,
7931 struct drm_mode_set *set,
7932 struct intel_set_config *config)
7934 struct drm_crtc *new_crtc;
7935 struct intel_connector *connector;
7936 struct intel_encoder *encoder;
7939 /* The upper layers ensure that we either disabl a crtc or have a list
7940 * of connectors. For paranoia, double-check this. */
7941 WARN_ON(!set->fb && (set->num_connectors != 0));
7942 WARN_ON(set->fb && (set->num_connectors == 0));
7945 list_for_each_entry(connector, &dev->mode_config.connector_list,
7947 /* Otherwise traverse passed in connector list and get encoders
7949 for (ro = 0; ro < set->num_connectors; ro++) {
7950 if (set->connectors[ro] == &connector->base) {
7951 connector->new_encoder = connector->encoder;
7956 /* If we disable the crtc, disable all its connectors. Also, if
7957 * the connector is on the changing crtc but not on the new
7958 * connector list, disable it. */
7959 if ((!set->fb || ro == set->num_connectors) &&
7960 connector->base.encoder &&
7961 connector->base.encoder->crtc == set->crtc) {
7962 connector->new_encoder = NULL;
7964 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7965 connector->base.base.id,
7966 drm_get_connector_name(&connector->base));
7970 if (&connector->new_encoder->base != connector->base.encoder) {
7971 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7972 config->mode_changed = true;
7975 /* Disable all disconnected encoders. */
7976 if (connector->base.status == connector_status_disconnected)
7977 connector->new_encoder = NULL;
7979 /* connector->new_encoder is now updated for all connectors. */
7981 /* Update crtc of enabled connectors. */
7983 list_for_each_entry(connector, &dev->mode_config.connector_list,
7985 if (!connector->new_encoder)
7988 new_crtc = connector->new_encoder->base.crtc;
7990 for (ro = 0; ro < set->num_connectors; ro++) {
7991 if (set->connectors[ro] == &connector->base)
7992 new_crtc = set->crtc;
7995 /* Make sure the new CRTC will work with the encoder */
7996 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8000 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8002 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8003 connector->base.base.id,
8004 drm_get_connector_name(&connector->base),
8008 /* Check for any encoders that needs to be disabled. */
8009 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8011 list_for_each_entry(connector,
8012 &dev->mode_config.connector_list,
8014 if (connector->new_encoder == encoder) {
8015 WARN_ON(!connector->new_encoder->new_crtc);
8020 encoder->new_crtc = NULL;
8022 /* Only now check for crtc changes so we don't miss encoders
8023 * that will be disabled. */
8024 if (&encoder->new_crtc->base != encoder->base.crtc) {
8025 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8026 config->mode_changed = true;
8029 /* Now we've also updated encoder->new_crtc for all encoders. */
8034 static int intel_crtc_set_config(struct drm_mode_set *set)
8036 struct drm_device *dev;
8037 struct drm_mode_set save_set;
8038 struct intel_set_config *config;
8043 BUG_ON(!set->crtc->helper_private);
8048 /* The fb helper likes to play gross jokes with ->mode_set_config.
8049 * Unfortunately the crtc helper doesn't do much at all for this case,
8050 * so we have to cope with this madness until the fb helper is fixed up. */
8051 if (set->fb && set->num_connectors == 0)
8055 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8056 set->crtc->base.id, set->fb->base.id,
8057 (int)set->num_connectors, set->x, set->y);
8059 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8062 dev = set->crtc->dev;
8065 config = kzalloc(sizeof(*config), GFP_KERNEL);
8069 ret = intel_set_config_save_state(dev, config);
8073 save_set.crtc = set->crtc;
8074 save_set.mode = &set->crtc->mode;
8075 save_set.x = set->crtc->x;
8076 save_set.y = set->crtc->y;
8077 save_set.fb = set->crtc->fb;
8079 /* Compute whether we need a full modeset, only an fb base update or no
8080 * change at all. In the future we might also check whether only the
8081 * mode changed, e.g. for LVDS where we only change the panel fitter in
8083 intel_set_config_compute_mode_changes(set, config);
8085 ret = intel_modeset_stage_output_state(dev, set, config);
8089 if (config->mode_changed) {
8091 DRM_DEBUG_KMS("attempting to set mode from"
8093 drm_mode_debug_printmodeline(set->mode);
8096 if (!intel_set_mode(set->crtc, set->mode,
8097 set->x, set->y, set->fb)) {
8098 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8099 set->crtc->base.id);
8103 } else if (config->fb_changed) {
8104 ret = intel_pipe_set_base(set->crtc,
8105 set->x, set->y, set->fb);
8108 intel_set_config_free(config);
8113 intel_set_config_restore_state(dev, config);
8115 /* Try to restore the config */
8116 if (config->mode_changed &&
8117 !intel_set_mode(save_set.crtc, save_set.mode,
8118 save_set.x, save_set.y, save_set.fb))
8119 DRM_ERROR("failed to restore config after modeset failure\n");
8122 intel_set_config_free(config);
8126 static const struct drm_crtc_funcs intel_crtc_funcs = {
8127 .cursor_set = intel_crtc_cursor_set,
8128 .cursor_move = intel_crtc_cursor_move,
8129 .gamma_set = intel_crtc_gamma_set,
8130 .set_config = intel_crtc_set_config,
8131 .destroy = intel_crtc_destroy,
8132 .page_flip = intel_crtc_page_flip,
8135 static void intel_cpu_pll_init(struct drm_device *dev)
8137 if (IS_HASWELL(dev))
8138 intel_ddi_pll_init(dev);
8141 static void intel_pch_pll_init(struct drm_device *dev)
8143 drm_i915_private_t *dev_priv = dev->dev_private;
8146 if (dev_priv->num_pch_pll == 0) {
8147 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8151 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8152 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8153 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8154 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8158 static void intel_crtc_init(struct drm_device *dev, int pipe)
8160 drm_i915_private_t *dev_priv = dev->dev_private;
8161 struct intel_crtc *intel_crtc;
8164 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8165 if (intel_crtc == NULL)
8168 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8170 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8171 for (i = 0; i < 256; i++) {
8172 intel_crtc->lut_r[i] = i;
8173 intel_crtc->lut_g[i] = i;
8174 intel_crtc->lut_b[i] = i;
8177 /* Swap pipes & planes for FBC on pre-965 */
8178 intel_crtc->pipe = pipe;
8179 intel_crtc->plane = pipe;
8180 intel_crtc->cpu_transcoder = pipe;
8181 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8182 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8183 intel_crtc->plane = !pipe;
8186 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8187 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8188 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8189 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8191 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8193 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8196 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8197 struct drm_file *file)
8199 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8200 struct drm_mode_object *drmmode_obj;
8201 struct intel_crtc *crtc;
8203 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8206 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8207 DRM_MODE_OBJECT_CRTC);
8210 DRM_ERROR("no such CRTC id\n");
8214 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8215 pipe_from_crtc_id->pipe = crtc->pipe;
8220 static int intel_encoder_clones(struct intel_encoder *encoder)
8222 struct drm_device *dev = encoder->base.dev;
8223 struct intel_encoder *source_encoder;
8227 list_for_each_entry(source_encoder,
8228 &dev->mode_config.encoder_list, base.head) {
8230 if (encoder == source_encoder)
8231 index_mask |= (1 << entry);
8233 /* Intel hw has only one MUX where enocoders could be cloned. */
8234 if (encoder->cloneable && source_encoder->cloneable)
8235 index_mask |= (1 << entry);
8243 static bool has_edp_a(struct drm_device *dev)
8245 struct drm_i915_private *dev_priv = dev->dev_private;
8247 if (!IS_MOBILE(dev))
8250 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8254 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8260 static void intel_setup_outputs(struct drm_device *dev)
8262 struct drm_i915_private *dev_priv = dev->dev_private;
8263 struct intel_encoder *encoder;
8264 bool dpd_is_edp = false;
8267 has_lvds = intel_lvds_init(dev);
8268 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8269 /* disable the panel fitter on everything but LVDS */
8270 I915_WRITE(PFIT_CONTROL, 0);
8273 if (HAS_PCH_SPLIT(dev)) {
8274 dpd_is_edp = intel_dpd_is_edp(dev);
8277 intel_dp_init(dev, DP_A, PORT_A);
8279 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8280 intel_dp_init(dev, PCH_DP_D, PORT_D);
8283 intel_crt_init(dev);
8285 if (IS_HASWELL(dev)) {
8288 /* Haswell uses DDI functions to detect digital outputs */
8289 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8290 /* DDI A only supports eDP */
8292 intel_ddi_init(dev, PORT_A);
8294 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8296 found = I915_READ(SFUSE_STRAP);
8298 if (found & SFUSE_STRAP_DDIB_DETECTED)
8299 intel_ddi_init(dev, PORT_B);
8300 if (found & SFUSE_STRAP_DDIC_DETECTED)
8301 intel_ddi_init(dev, PORT_C);
8302 if (found & SFUSE_STRAP_DDID_DETECTED)
8303 intel_ddi_init(dev, PORT_D);
8304 } else if (HAS_PCH_SPLIT(dev)) {
8307 if (I915_READ(HDMIB) & PORT_DETECTED) {
8308 /* PCH SDVOB multiplex with HDMIB */
8309 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8311 intel_hdmi_init(dev, HDMIB, PORT_B);
8312 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8313 intel_dp_init(dev, PCH_DP_B, PORT_B);
8316 if (I915_READ(HDMIC) & PORT_DETECTED)
8317 intel_hdmi_init(dev, HDMIC, PORT_C);
8319 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8320 intel_hdmi_init(dev, HDMID, PORT_D);
8322 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8323 intel_dp_init(dev, PCH_DP_C, PORT_C);
8325 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8326 intel_dp_init(dev, PCH_DP_D, PORT_D);
8327 } else if (IS_VALLEYVIEW(dev)) {
8330 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8331 if (I915_READ(DP_C) & DP_DETECTED)
8332 intel_dp_init(dev, DP_C, PORT_C);
8334 if (I915_READ(SDVOB) & PORT_DETECTED) {
8335 /* SDVOB multiplex with HDMIB */
8336 found = intel_sdvo_init(dev, SDVOB, true);
8338 intel_hdmi_init(dev, SDVOB, PORT_B);
8339 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8340 intel_dp_init(dev, DP_B, PORT_B);
8343 if (I915_READ(SDVOC) & PORT_DETECTED)
8344 intel_hdmi_init(dev, SDVOC, PORT_C);
8346 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8349 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8350 DRM_DEBUG_KMS("probing SDVOB\n");
8351 found = intel_sdvo_init(dev, SDVOB, true);
8352 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8353 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8354 intel_hdmi_init(dev, SDVOB, PORT_B);
8357 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8358 DRM_DEBUG_KMS("probing DP_B\n");
8359 intel_dp_init(dev, DP_B, PORT_B);
8363 /* Before G4X SDVOC doesn't have its own detect register */
8365 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8366 DRM_DEBUG_KMS("probing SDVOC\n");
8367 found = intel_sdvo_init(dev, SDVOC, false);
8370 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8372 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8373 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8374 intel_hdmi_init(dev, SDVOC, PORT_C);
8376 if (SUPPORTS_INTEGRATED_DP(dev)) {
8377 DRM_DEBUG_KMS("probing DP_C\n");
8378 intel_dp_init(dev, DP_C, PORT_C);
8382 if (SUPPORTS_INTEGRATED_DP(dev) &&
8383 (I915_READ(DP_D) & DP_DETECTED)) {
8384 DRM_DEBUG_KMS("probing DP_D\n");
8385 intel_dp_init(dev, DP_D, PORT_D);
8387 } else if (IS_GEN2(dev))
8388 intel_dvo_init(dev);
8390 if (SUPPORTS_TV(dev))
8393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8394 encoder->base.possible_crtcs = encoder->crtc_mask;
8395 encoder->base.possible_clones =
8396 intel_encoder_clones(encoder);
8399 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8400 ironlake_init_pch_refclk(dev);
8403 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8405 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8407 drm_framebuffer_cleanup(fb);
8408 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8413 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8414 struct drm_file *file,
8415 unsigned int *handle)
8417 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8418 struct drm_i915_gem_object *obj = intel_fb->obj;
8420 return drm_gem_handle_create(file, &obj->base, handle);
8423 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8424 .destroy = intel_user_framebuffer_destroy,
8425 .create_handle = intel_user_framebuffer_create_handle,
8428 int intel_framebuffer_init(struct drm_device *dev,
8429 struct intel_framebuffer *intel_fb,
8430 struct drm_mode_fb_cmd2 *mode_cmd,
8431 struct drm_i915_gem_object *obj)
8435 if (obj->tiling_mode == I915_TILING_Y)
8438 if (mode_cmd->pitches[0] & 63)
8441 /* FIXME <= Gen4 stride limits are bit unclear */
8442 if (mode_cmd->pitches[0] > 32768)
8445 if (obj->tiling_mode != I915_TILING_NONE &&
8446 mode_cmd->pitches[0] != obj->stride)
8449 /* Reject formats not supported by any plane early. */
8450 switch (mode_cmd->pixel_format) {
8452 case DRM_FORMAT_RGB565:
8453 case DRM_FORMAT_XRGB8888:
8454 case DRM_FORMAT_ARGB8888:
8456 case DRM_FORMAT_XRGB1555:
8457 case DRM_FORMAT_ARGB1555:
8458 if (INTEL_INFO(dev)->gen > 3)
8461 case DRM_FORMAT_XBGR8888:
8462 case DRM_FORMAT_ABGR8888:
8463 case DRM_FORMAT_XRGB2101010:
8464 case DRM_FORMAT_ARGB2101010:
8465 case DRM_FORMAT_XBGR2101010:
8466 case DRM_FORMAT_ABGR2101010:
8467 if (INTEL_INFO(dev)->gen < 4)
8470 case DRM_FORMAT_YUYV:
8471 case DRM_FORMAT_UYVY:
8472 case DRM_FORMAT_YVYU:
8473 case DRM_FORMAT_VYUY:
8474 if (INTEL_INFO(dev)->gen < 6)
8478 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8482 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8483 if (mode_cmd->offsets[0] != 0)
8486 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8488 DRM_ERROR("framebuffer init failed %d\n", ret);
8492 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8493 intel_fb->obj = obj;
8497 static struct drm_framebuffer *
8498 intel_user_framebuffer_create(struct drm_device *dev,
8499 struct drm_file *filp,
8500 struct drm_mode_fb_cmd2 *mode_cmd)
8502 struct drm_i915_gem_object *obj;
8504 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8505 mode_cmd->handles[0]));
8506 if (&obj->base == NULL)
8507 return ERR_PTR(-ENOENT);
8509 return intel_framebuffer_create(dev, mode_cmd, obj);
8512 static const struct drm_mode_config_funcs intel_mode_funcs = {
8513 .fb_create = intel_user_framebuffer_create,
8514 .output_poll_changed = intel_fb_output_poll_changed,
8517 /* Set up chip specific display functions */
8518 static void intel_init_display(struct drm_device *dev)
8520 struct drm_i915_private *dev_priv = dev->dev_private;
8522 /* We always want a DPMS function */
8523 if (IS_HASWELL(dev)) {
8524 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8525 dev_priv->display.crtc_enable = haswell_crtc_enable;
8526 dev_priv->display.crtc_disable = haswell_crtc_disable;
8527 dev_priv->display.off = haswell_crtc_off;
8528 dev_priv->display.update_plane = ironlake_update_plane;
8529 } else if (HAS_PCH_SPLIT(dev)) {
8530 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8531 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8532 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8533 dev_priv->display.off = ironlake_crtc_off;
8534 dev_priv->display.update_plane = ironlake_update_plane;
8536 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8537 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8538 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8539 dev_priv->display.off = i9xx_crtc_off;
8540 dev_priv->display.update_plane = i9xx_update_plane;
8543 /* Returns the core display clock speed */
8544 if (IS_VALLEYVIEW(dev))
8545 dev_priv->display.get_display_clock_speed =
8546 valleyview_get_display_clock_speed;
8547 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8548 dev_priv->display.get_display_clock_speed =
8549 i945_get_display_clock_speed;
8550 else if (IS_I915G(dev))
8551 dev_priv->display.get_display_clock_speed =
8552 i915_get_display_clock_speed;
8553 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8554 dev_priv->display.get_display_clock_speed =
8555 i9xx_misc_get_display_clock_speed;
8556 else if (IS_I915GM(dev))
8557 dev_priv->display.get_display_clock_speed =
8558 i915gm_get_display_clock_speed;
8559 else if (IS_I865G(dev))
8560 dev_priv->display.get_display_clock_speed =
8561 i865_get_display_clock_speed;
8562 else if (IS_I85X(dev))
8563 dev_priv->display.get_display_clock_speed =
8564 i855_get_display_clock_speed;
8566 dev_priv->display.get_display_clock_speed =
8567 i830_get_display_clock_speed;
8569 if (HAS_PCH_SPLIT(dev)) {
8571 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8572 dev_priv->display.write_eld = ironlake_write_eld;
8573 } else if (IS_GEN6(dev)) {
8574 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8575 dev_priv->display.write_eld = ironlake_write_eld;
8576 } else if (IS_IVYBRIDGE(dev)) {
8577 /* FIXME: detect B0+ stepping and use auto training */
8578 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8579 dev_priv->display.write_eld = ironlake_write_eld;
8580 dev_priv->display.modeset_global_resources =
8581 ivb_modeset_global_resources;
8582 } else if (IS_HASWELL(dev)) {
8583 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8584 dev_priv->display.write_eld = haswell_write_eld;
8586 dev_priv->display.update_wm = NULL;
8587 } else if (IS_G4X(dev)) {
8588 dev_priv->display.write_eld = g4x_write_eld;
8591 /* Default just returns -ENODEV to indicate unsupported */
8592 dev_priv->display.queue_flip = intel_default_queue_flip;
8594 switch (INTEL_INFO(dev)->gen) {
8596 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8600 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8605 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8609 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8612 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8618 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8619 * resume, or other times. This quirk makes sure that's the case for
8622 static void quirk_pipea_force(struct drm_device *dev)
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8626 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8627 DRM_INFO("applying pipe a force quirk\n");
8631 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8633 static void quirk_ssc_force_disable(struct drm_device *dev)
8635 struct drm_i915_private *dev_priv = dev->dev_private;
8636 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8637 DRM_INFO("applying lvds SSC disable quirk\n");
8641 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8644 static void quirk_invert_brightness(struct drm_device *dev)
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8648 DRM_INFO("applying inverted panel brightness quirk\n");
8651 struct intel_quirk {
8653 int subsystem_vendor;
8654 int subsystem_device;
8655 void (*hook)(struct drm_device *dev);
8658 static struct intel_quirk intel_quirks[] = {
8659 /* HP Mini needs pipe A force quirk (LP: #322104) */
8660 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8662 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8663 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8665 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8666 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8668 /* 830/845 need to leave pipe A & dpll A up */
8669 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8670 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8672 /* Lenovo U160 cannot use SSC on LVDS */
8673 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8675 /* Sony Vaio Y cannot use SSC on LVDS */
8676 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8678 /* Acer Aspire 5734Z must invert backlight brightness */
8679 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8682 static void intel_init_quirks(struct drm_device *dev)
8684 struct pci_dev *d = dev->pdev;
8687 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8688 struct intel_quirk *q = &intel_quirks[i];
8690 if (d->device == q->device &&
8691 (d->subsystem_vendor == q->subsystem_vendor ||
8692 q->subsystem_vendor == PCI_ANY_ID) &&
8693 (d->subsystem_device == q->subsystem_device ||
8694 q->subsystem_device == PCI_ANY_ID))
8699 /* Disable the VGA plane that we never use */
8700 static void i915_disable_vga(struct drm_device *dev)
8702 struct drm_i915_private *dev_priv = dev->dev_private;
8706 if (HAS_PCH_SPLIT(dev))
8707 vga_reg = CPU_VGACNTRL;
8711 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8712 outb(SR01, VGA_SR_INDEX);
8713 sr1 = inb(VGA_SR_DATA);
8714 outb(sr1 | 1<<5, VGA_SR_DATA);
8715 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8718 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8719 POSTING_READ(vga_reg);
8722 void intel_modeset_init_hw(struct drm_device *dev)
8724 /* We attempt to init the necessary power wells early in the initialization
8725 * time, so the subsystems that expect power to be enabled can work.
8727 intel_init_power_wells(dev);
8729 intel_prepare_ddi(dev);
8731 intel_init_clock_gating(dev);
8733 mutex_lock(&dev->struct_mutex);
8734 intel_enable_gt_powersave(dev);
8735 mutex_unlock(&dev->struct_mutex);
8738 void intel_modeset_init(struct drm_device *dev)
8740 struct drm_i915_private *dev_priv = dev->dev_private;
8743 drm_mode_config_init(dev);
8745 dev->mode_config.min_width = 0;
8746 dev->mode_config.min_height = 0;
8748 dev->mode_config.preferred_depth = 24;
8749 dev->mode_config.prefer_shadow = 1;
8751 dev->mode_config.funcs = &intel_mode_funcs;
8753 intel_init_quirks(dev);
8757 intel_init_display(dev);
8760 dev->mode_config.max_width = 2048;
8761 dev->mode_config.max_height = 2048;
8762 } else if (IS_GEN3(dev)) {
8763 dev->mode_config.max_width = 4096;
8764 dev->mode_config.max_height = 4096;
8766 dev->mode_config.max_width = 8192;
8767 dev->mode_config.max_height = 8192;
8769 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8771 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8772 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8774 for (i = 0; i < dev_priv->num_pipe; i++) {
8775 intel_crtc_init(dev, i);
8776 ret = intel_plane_init(dev, i);
8778 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8781 intel_cpu_pll_init(dev);
8782 intel_pch_pll_init(dev);
8784 /* Just disable it once at startup */
8785 i915_disable_vga(dev);
8786 intel_setup_outputs(dev);
8790 intel_connector_break_all_links(struct intel_connector *connector)
8792 connector->base.dpms = DRM_MODE_DPMS_OFF;
8793 connector->base.encoder = NULL;
8794 connector->encoder->connectors_active = false;
8795 connector->encoder->base.crtc = NULL;
8798 static void intel_enable_pipe_a(struct drm_device *dev)
8800 struct intel_connector *connector;
8801 struct drm_connector *crt = NULL;
8802 struct intel_load_detect_pipe load_detect_temp;
8804 /* We can't just switch on the pipe A, we need to set things up with a
8805 * proper mode and output configuration. As a gross hack, enable pipe A
8806 * by enabling the load detect pipe once. */
8807 list_for_each_entry(connector,
8808 &dev->mode_config.connector_list,
8810 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8811 crt = &connector->base;
8819 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8820 intel_release_load_detect_pipe(crt, &load_detect_temp);
8826 intel_check_plane_mapping(struct intel_crtc *crtc)
8828 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8831 if (dev_priv->num_pipe == 1)
8834 reg = DSPCNTR(!crtc->plane);
8835 val = I915_READ(reg);
8837 if ((val & DISPLAY_PLANE_ENABLE) &&
8838 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8844 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8846 struct drm_device *dev = crtc->base.dev;
8847 struct drm_i915_private *dev_priv = dev->dev_private;
8850 /* Clear any frame start delays used for debugging left by the BIOS */
8851 reg = PIPECONF(crtc->cpu_transcoder);
8852 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8854 /* We need to sanitize the plane -> pipe mapping first because this will
8855 * disable the crtc (and hence change the state) if it is wrong. Note
8856 * that gen4+ has a fixed plane -> pipe mapping. */
8857 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8858 struct intel_connector *connector;
8861 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8862 crtc->base.base.id);
8864 /* Pipe has the wrong plane attached and the plane is active.
8865 * Temporarily change the plane mapping and disable everything
8867 plane = crtc->plane;
8868 crtc->plane = !plane;
8869 dev_priv->display.crtc_disable(&crtc->base);
8870 crtc->plane = plane;
8872 /* ... and break all links. */
8873 list_for_each_entry(connector, &dev->mode_config.connector_list,
8875 if (connector->encoder->base.crtc != &crtc->base)
8878 intel_connector_break_all_links(connector);
8881 WARN_ON(crtc->active);
8882 crtc->base.enabled = false;
8885 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8886 crtc->pipe == PIPE_A && !crtc->active) {
8887 /* BIOS forgot to enable pipe A, this mostly happens after
8888 * resume. Force-enable the pipe to fix this, the update_dpms
8889 * call below we restore the pipe to the right state, but leave
8890 * the required bits on. */
8891 intel_enable_pipe_a(dev);
8894 /* Adjust the state of the output pipe according to whether we
8895 * have active connectors/encoders. */
8896 intel_crtc_update_dpms(&crtc->base);
8898 if (crtc->active != crtc->base.enabled) {
8899 struct intel_encoder *encoder;
8901 /* This can happen either due to bugs in the get_hw_state
8902 * functions or because the pipe is force-enabled due to the
8904 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8906 crtc->base.enabled ? "enabled" : "disabled",
8907 crtc->active ? "enabled" : "disabled");
8909 crtc->base.enabled = crtc->active;
8911 /* Because we only establish the connector -> encoder ->
8912 * crtc links if something is active, this means the
8913 * crtc is now deactivated. Break the links. connector
8914 * -> encoder links are only establish when things are
8915 * actually up, hence no need to break them. */
8916 WARN_ON(crtc->active);
8918 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8919 WARN_ON(encoder->connectors_active);
8920 encoder->base.crtc = NULL;
8925 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8927 struct intel_connector *connector;
8928 struct drm_device *dev = encoder->base.dev;
8930 /* We need to check both for a crtc link (meaning that the
8931 * encoder is active and trying to read from a pipe) and the
8932 * pipe itself being active. */
8933 bool has_active_crtc = encoder->base.crtc &&
8934 to_intel_crtc(encoder->base.crtc)->active;
8936 if (encoder->connectors_active && !has_active_crtc) {
8937 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8938 encoder->base.base.id,
8939 drm_get_encoder_name(&encoder->base));
8941 /* Connector is active, but has no active pipe. This is
8942 * fallout from our resume register restoring. Disable
8943 * the encoder manually again. */
8944 if (encoder->base.crtc) {
8945 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8946 encoder->base.base.id,
8947 drm_get_encoder_name(&encoder->base));
8948 encoder->disable(encoder);
8951 /* Inconsistent output/port/pipe state happens presumably due to
8952 * a bug in one of the get_hw_state functions. Or someplace else
8953 * in our code, like the register restore mess on resume. Clamp
8954 * things to off as a safer default. */
8955 list_for_each_entry(connector,
8956 &dev->mode_config.connector_list,
8958 if (connector->encoder != encoder)
8961 intel_connector_break_all_links(connector);
8964 /* Enabled encoders without active connectors will be fixed in
8965 * the crtc fixup. */
8968 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8969 * and i915 state tracking structures. */
8970 void intel_modeset_setup_hw_state(struct drm_device *dev)
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8975 struct intel_crtc *crtc;
8976 struct intel_encoder *encoder;
8977 struct intel_connector *connector;
8979 if (IS_HASWELL(dev)) {
8980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8982 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8983 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8984 case TRANS_DDI_EDP_INPUT_A_ON:
8985 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8988 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8991 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8996 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8997 crtc->cpu_transcoder = TRANSCODER_EDP;
8999 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9004 for_each_pipe(pipe) {
9005 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9007 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9008 if (tmp & PIPECONF_ENABLE)
9009 crtc->active = true;
9011 crtc->active = false;
9013 crtc->base.enabled = crtc->active;
9015 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9017 crtc->active ? "enabled" : "disabled");
9020 if (IS_HASWELL(dev))
9021 intel_ddi_setup_hw_pll_state(dev);
9023 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9027 if (encoder->get_hw_state(encoder, &pipe)) {
9028 encoder->base.crtc =
9029 dev_priv->pipe_to_crtc_mapping[pipe];
9031 encoder->base.crtc = NULL;
9034 encoder->connectors_active = false;
9035 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9036 encoder->base.base.id,
9037 drm_get_encoder_name(&encoder->base),
9038 encoder->base.crtc ? "enabled" : "disabled",
9042 list_for_each_entry(connector, &dev->mode_config.connector_list,
9044 if (connector->get_hw_state(connector)) {
9045 connector->base.dpms = DRM_MODE_DPMS_ON;
9046 connector->encoder->connectors_active = true;
9047 connector->base.encoder = &connector->encoder->base;
9049 connector->base.dpms = DRM_MODE_DPMS_OFF;
9050 connector->base.encoder = NULL;
9052 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9053 connector->base.base.id,
9054 drm_get_connector_name(&connector->base),
9055 connector->base.encoder ? "enabled" : "disabled");
9058 /* HW state is read out, now we need to sanitize this mess. */
9059 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9061 intel_sanitize_encoder(encoder);
9064 for_each_pipe(pipe) {
9065 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9066 intel_sanitize_crtc(crtc);
9069 intel_modeset_update_staged_output_state(dev);
9071 intel_modeset_check_state(dev);
9073 drm_mode_config_reset(dev);
9076 void intel_modeset_gem_init(struct drm_device *dev)
9078 intel_modeset_init_hw(dev);
9080 intel_setup_overlay(dev);
9082 intel_modeset_setup_hw_state(dev);
9085 void intel_modeset_cleanup(struct drm_device *dev)
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 struct drm_crtc *crtc;
9089 struct intel_crtc *intel_crtc;
9091 drm_kms_helper_poll_fini(dev);
9092 mutex_lock(&dev->struct_mutex);
9094 intel_unregister_dsm_handler();
9097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9098 /* Skip inactive CRTCs */
9102 intel_crtc = to_intel_crtc(crtc);
9103 intel_increase_pllclock(crtc);
9106 intel_disable_fbc(dev);
9108 intel_disable_gt_powersave(dev);
9110 ironlake_teardown_rc6(dev);
9112 if (IS_VALLEYVIEW(dev))
9115 mutex_unlock(&dev->struct_mutex);
9117 /* Disable the irq before mode object teardown, for the irq might
9118 * enqueue unpin/hotplug work. */
9119 drm_irq_uninstall(dev);
9120 cancel_work_sync(&dev_priv->hotplug_work);
9121 cancel_work_sync(&dev_priv->rps.work);
9123 /* flush any delayed tasks or pending work */
9124 flush_scheduled_work();
9126 drm_mode_config_cleanup(dev);
9130 * Return which encoder is currently attached for connector.
9132 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9134 return &intel_attached_encoder(connector)->base;
9137 void intel_connector_attach_encoder(struct intel_connector *connector,
9138 struct intel_encoder *encoder)
9140 connector->encoder = encoder;
9141 drm_mode_connector_attach_encoder(&connector->base,
9146 * set vga decode state - true == enable VGA decode
9148 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9153 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9155 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9157 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9158 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9162 #ifdef CONFIG_DEBUG_FS
9163 #include <linux/seq_file.h>
9165 struct intel_display_error_state {
9166 struct intel_cursor_error_state {
9171 } cursor[I915_MAX_PIPES];
9173 struct intel_pipe_error_state {
9183 } pipe[I915_MAX_PIPES];
9185 struct intel_plane_error_state {
9193 } plane[I915_MAX_PIPES];
9196 struct intel_display_error_state *
9197 intel_display_capture_error_state(struct drm_device *dev)
9199 drm_i915_private_t *dev_priv = dev->dev_private;
9200 struct intel_display_error_state *error;
9201 enum transcoder cpu_transcoder;
9204 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9209 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9211 error->cursor[i].control = I915_READ(CURCNTR(i));
9212 error->cursor[i].position = I915_READ(CURPOS(i));
9213 error->cursor[i].base = I915_READ(CURBASE(i));
9215 error->plane[i].control = I915_READ(DSPCNTR(i));
9216 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9217 error->plane[i].size = I915_READ(DSPSIZE(i));
9218 error->plane[i].pos = I915_READ(DSPPOS(i));
9219 error->plane[i].addr = I915_READ(DSPADDR(i));
9220 if (INTEL_INFO(dev)->gen >= 4) {
9221 error->plane[i].surface = I915_READ(DSPSURF(i));
9222 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9225 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9226 error->pipe[i].source = I915_READ(PIPESRC(i));
9227 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9228 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9229 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9230 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9231 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9232 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9239 intel_display_print_error_state(struct seq_file *m,
9240 struct drm_device *dev,
9241 struct intel_display_error_state *error)
9243 drm_i915_private_t *dev_priv = dev->dev_private;
9246 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9248 seq_printf(m, "Pipe [%d]:\n", i);
9249 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9250 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9251 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9252 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9253 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9254 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9255 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9256 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9258 seq_printf(m, "Plane [%d]:\n", i);
9259 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9260 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9261 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9262 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9263 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9264 if (INTEL_INFO(dev)->gen >= 4) {
9265 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9266 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9269 seq_printf(m, "Cursor [%d]:\n", i);
9270 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9271 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9272 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);