Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  */
1433 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1434 {
1435         int reg;
1436         u32 val;
1437
1438         /* No really, not for ILK+ */
1439         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1440
1441         /* PLL is protected by panel, make sure we can write it */
1442         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1443                 assert_panel_unlocked(dev_priv, pipe);
1444
1445         reg = DPLL(pipe);
1446         val = I915_READ(reg);
1447         val |= DPLL_VCO_ENABLE;
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, val);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, val);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, val);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * intel_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         int reg;
1473         u32 val;
1474
1475         /* Don't disable pipe A or pipe A PLLs if needed */
1476         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1477                 return;
1478
1479         /* Make sure the pipe isn't still relying on us */
1480         assert_pipe_disabled(dev_priv, pipe);
1481
1482         reg = DPLL(pipe);
1483         val = I915_READ(reg);
1484         val &= ~DPLL_VCO_ENABLE;
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487 }
1488
1489 /* SBI access */
1490 static void
1491 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1492 {
1493         unsigned long flags;
1494
1495         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1496         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1497                                 100)) {
1498                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1499                 goto out_unlock;
1500         }
1501
1502         I915_WRITE(SBI_ADDR,
1503                         (reg << 16));
1504         I915_WRITE(SBI_DATA,
1505                         value);
1506         I915_WRITE(SBI_CTL_STAT,
1507                         SBI_BUSY |
1508                         SBI_CTL_OP_CRWR);
1509
1510         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1511                                 100)) {
1512                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1513                 goto out_unlock;
1514         }
1515
1516 out_unlock:
1517         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1518 }
1519
1520 static u32
1521 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1522 {
1523         unsigned long flags;
1524         u32 value = 0;
1525
1526         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1527         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1528                                 100)) {
1529                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1530                 goto out_unlock;
1531         }
1532
1533         I915_WRITE(SBI_ADDR,
1534                         (reg << 16));
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRRD);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545         value = I915_READ(SBI_DATA);
1546
1547 out_unlock:
1548         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1549         return value;
1550 }
1551
1552 /**
1553  * intel_enable_pch_pll - enable PCH PLL
1554  * @dev_priv: i915 private structure
1555  * @pipe: pipe PLL to enable
1556  *
1557  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1558  * drives the transcoder clock.
1559  */
1560 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1561 {
1562         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1563         struct intel_pch_pll *pll;
1564         int reg;
1565         u32 val;
1566
1567         /* PCH PLLs only available on ILK, SNB and IVB */
1568         BUG_ON(dev_priv->info->gen < 5);
1569         pll = intel_crtc->pch_pll;
1570         if (pll == NULL)
1571                 return;
1572
1573         if (WARN_ON(pll->refcount == 0))
1574                 return;
1575
1576         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1577                       pll->pll_reg, pll->active, pll->on,
1578                       intel_crtc->base.base.id);
1579
1580         /* PCH refclock must be enabled first */
1581         assert_pch_refclk_enabled(dev_priv);
1582
1583         if (pll->active++ && pll->on) {
1584                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1585                 return;
1586         }
1587
1588         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1589
1590         reg = pll->pll_reg;
1591         val = I915_READ(reg);
1592         val |= DPLL_VCO_ENABLE;
1593         I915_WRITE(reg, val);
1594         POSTING_READ(reg);
1595         udelay(200);
1596
1597         pll->on = true;
1598 }
1599
1600 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1601 {
1602         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1603         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1604         int reg;
1605         u32 val;
1606
1607         /* PCH only available on ILK+ */
1608         BUG_ON(dev_priv->info->gen < 5);
1609         if (pll == NULL)
1610                return;
1611
1612         if (WARN_ON(pll->refcount == 0))
1613                 return;
1614
1615         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1616                       pll->pll_reg, pll->active, pll->on,
1617                       intel_crtc->base.base.id);
1618
1619         if (WARN_ON(pll->active == 0)) {
1620                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1621                 return;
1622         }
1623
1624         if (--pll->active) {
1625                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1630
1631         /* Make sure transcoder isn't still depending on us */
1632         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1633
1634         reg = pll->pll_reg;
1635         val = I915_READ(reg);
1636         val &= ~DPLL_VCO_ENABLE;
1637         I915_WRITE(reg, val);
1638         POSTING_READ(reg);
1639         udelay(200);
1640
1641         pll->on = false;
1642 }
1643
1644 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1645                                     enum pipe pipe)
1646 {
1647         int reg;
1648         u32 val, pipeconf_val;
1649         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1650
1651         /* PCH only available on ILK+ */
1652         BUG_ON(dev_priv->info->gen < 5);
1653
1654         /* Make sure PCH DPLL is enabled */
1655         assert_pch_pll_enabled(dev_priv,
1656                                to_intel_crtc(crtc)->pch_pll,
1657                                to_intel_crtc(crtc));
1658
1659         /* FDI must be feeding us bits for PCH ports */
1660         assert_fdi_tx_enabled(dev_priv, pipe);
1661         assert_fdi_rx_enabled(dev_priv, pipe);
1662
1663         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1664                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1665                 return;
1666         }
1667         reg = TRANSCONF(pipe);
1668         val = I915_READ(reg);
1669         pipeconf_val = I915_READ(PIPECONF(pipe));
1670
1671         if (HAS_PCH_IBX(dev_priv->dev)) {
1672                 /*
1673                  * make the BPC in transcoder be consistent with
1674                  * that in pipeconf reg.
1675                  */
1676                 val &= ~PIPE_BPC_MASK;
1677                 val |= pipeconf_val & PIPE_BPC_MASK;
1678         }
1679
1680         val &= ~TRANS_INTERLACE_MASK;
1681         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1682                 if (HAS_PCH_IBX(dev_priv->dev) &&
1683                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1684                         val |= TRANS_LEGACY_INTERLACED_ILK;
1685                 else
1686                         val |= TRANS_INTERLACED;
1687         else
1688                 val |= TRANS_PROGRESSIVE;
1689
1690         I915_WRITE(reg, val | TRANS_ENABLE);
1691         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1692                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1693 }
1694
1695 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1696                                      enum pipe pipe)
1697 {
1698         int reg;
1699         u32 val;
1700
1701         /* FDI relies on the transcoder */
1702         assert_fdi_tx_disabled(dev_priv, pipe);
1703         assert_fdi_rx_disabled(dev_priv, pipe);
1704
1705         /* Ports must be off as well */
1706         assert_pch_ports_disabled(dev_priv, pipe);
1707
1708         reg = TRANSCONF(pipe);
1709         val = I915_READ(reg);
1710         val &= ~TRANS_ENABLE;
1711         I915_WRITE(reg, val);
1712         /* wait for PCH transcoder off, transcoder state */
1713         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1714                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1715 }
1716
1717 /**
1718  * intel_enable_pipe - enable a pipe, asserting requirements
1719  * @dev_priv: i915 private structure
1720  * @pipe: pipe to enable
1721  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1722  *
1723  * Enable @pipe, making sure that various hardware specific requirements
1724  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725  *
1726  * @pipe should be %PIPE_A or %PIPE_B.
1727  *
1728  * Will wait until the pipe is actually running (i.e. first vblank) before
1729  * returning.
1730  */
1731 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732                               bool pch_port)
1733 {
1734         int reg;
1735         u32 val;
1736
1737         /*
1738          * A pipe without a PLL won't actually be able to drive bits from
1739          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1740          * need the check.
1741          */
1742         if (!HAS_PCH_SPLIT(dev_priv->dev))
1743                 assert_pll_enabled(dev_priv, pipe);
1744         else {
1745                 if (pch_port) {
1746                         /* if driving the PCH, we need FDI enabled */
1747                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1748                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1749                 }
1750                 /* FIXME: assert CPU port conditions for SNB+ */
1751         }
1752
1753         reg = PIPECONF(pipe);
1754         val = I915_READ(reg);
1755         if (val & PIPECONF_ENABLE)
1756                 return;
1757
1758         I915_WRITE(reg, val | PIPECONF_ENABLE);
1759         intel_wait_for_vblank(dev_priv->dev, pipe);
1760 }
1761
1762 /**
1763  * intel_disable_pipe - disable a pipe, asserting requirements
1764  * @dev_priv: i915 private structure
1765  * @pipe: pipe to disable
1766  *
1767  * Disable @pipe, making sure that various hardware specific requirements
1768  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1769  *
1770  * @pipe should be %PIPE_A or %PIPE_B.
1771  *
1772  * Will wait until the pipe has shut down before returning.
1773  */
1774 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1775                                enum pipe pipe)
1776 {
1777         int reg;
1778         u32 val;
1779
1780         /*
1781          * Make sure planes won't keep trying to pump pixels to us,
1782          * or we might hang the display.
1783          */
1784         assert_planes_disabled(dev_priv, pipe);
1785
1786         /* Don't disable pipe A or pipe A PLLs if needed */
1787         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1788                 return;
1789
1790         reg = PIPECONF(pipe);
1791         val = I915_READ(reg);
1792         if ((val & PIPECONF_ENABLE) == 0)
1793                 return;
1794
1795         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1796         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1797 }
1798
1799 /*
1800  * Plane regs are double buffered, going from enabled->disabled needs a
1801  * trigger in order to latch.  The display address reg provides this.
1802  */
1803 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1804                                       enum plane plane)
1805 {
1806         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1807         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1808 }
1809
1810 /**
1811  * intel_enable_plane - enable a display plane on a given pipe
1812  * @dev_priv: i915 private structure
1813  * @plane: plane to enable
1814  * @pipe: pipe being fed
1815  *
1816  * Enable @plane on @pipe, making sure that @pipe is running first.
1817  */
1818 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1819                                enum plane plane, enum pipe pipe)
1820 {
1821         int reg;
1822         u32 val;
1823
1824         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1825         assert_pipe_enabled(dev_priv, pipe);
1826
1827         reg = DSPCNTR(plane);
1828         val = I915_READ(reg);
1829         if (val & DISPLAY_PLANE_ENABLE)
1830                 return;
1831
1832         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1833         intel_flush_display_plane(dev_priv, plane);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_plane - disable a display plane
1839  * @dev_priv: i915 private structure
1840  * @plane: plane to disable
1841  * @pipe: pipe consuming the data
1842  *
1843  * Disable @plane; should be an independent operation.
1844  */
1845 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1846                                 enum plane plane, enum pipe pipe)
1847 {
1848         int reg;
1849         u32 val;
1850
1851         reg = DSPCNTR(plane);
1852         val = I915_READ(reg);
1853         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1857         intel_flush_display_plane(dev_priv, plane);
1858         intel_wait_for_vblank(dev_priv->dev, pipe);
1859 }
1860
1861 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1862                            enum pipe pipe, int reg, u32 port_sel)
1863 {
1864         u32 val = I915_READ(reg);
1865         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1866                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1867                 I915_WRITE(reg, val & ~DP_PORT_EN);
1868         }
1869 }
1870
1871 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1872                              enum pipe pipe, int reg)
1873 {
1874         u32 val = I915_READ(reg);
1875         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1876                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877                               reg, pipe);
1878                 I915_WRITE(reg, val & ~PORT_ENABLE);
1879         }
1880 }
1881
1882 /* Disable any ports connected to this transcoder */
1883 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1884                                     enum pipe pipe)
1885 {
1886         u32 reg, val;
1887
1888         val = I915_READ(PCH_PP_CONTROL);
1889         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1890
1891         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1892         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1894
1895         reg = PCH_ADPA;
1896         val = I915_READ(reg);
1897         if (adpa_pipe_enabled(dev_priv, val, pipe))
1898                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899
1900         reg = PCH_LVDS;
1901         val = I915_READ(reg);
1902         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1903                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1904                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905                 POSTING_READ(reg);
1906                 udelay(100);
1907         }
1908
1909         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1910         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1911         disable_pch_hdmi(dev_priv, pipe, HDMID);
1912 }
1913
1914 int
1915 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1916                            struct drm_i915_gem_object *obj,
1917                            struct intel_ring_buffer *pipelined)
1918 {
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         u32 alignment;
1921         int ret;
1922
1923         switch (obj->tiling_mode) {
1924         case I915_TILING_NONE:
1925                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1926                         alignment = 128 * 1024;
1927                 else if (INTEL_INFO(dev)->gen >= 4)
1928                         alignment = 4 * 1024;
1929                 else
1930                         alignment = 64 * 1024;
1931                 break;
1932         case I915_TILING_X:
1933                 /* pin() will align the object as required by fence */
1934                 alignment = 0;
1935                 break;
1936         case I915_TILING_Y:
1937                 /* FIXME: Is this true? */
1938                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1939                 return -EINVAL;
1940         default:
1941                 BUG();
1942         }
1943
1944         dev_priv->mm.interruptible = false;
1945         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1946         if (ret)
1947                 goto err_interruptible;
1948
1949         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950          * fence, whereas 965+ only requires a fence if using
1951          * framebuffer compression.  For simplicity, we always install
1952          * a fence as the cost is not that onerous.
1953          */
1954         ret = i915_gem_object_get_fence(obj);
1955         if (ret)
1956                 goto err_unpin;
1957
1958         i915_gem_object_pin_fence(obj);
1959
1960         dev_priv->mm.interruptible = true;
1961         return 0;
1962
1963 err_unpin:
1964         i915_gem_object_unpin(obj);
1965 err_interruptible:
1966         dev_priv->mm.interruptible = true;
1967         return ret;
1968 }
1969
1970 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1971 {
1972         i915_gem_object_unpin_fence(obj);
1973         i915_gem_object_unpin(obj);
1974 }
1975
1976 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1977  * is assumed to be a power-of-two. */
1978 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1979                                                         unsigned int bpp,
1980                                                         unsigned int pitch)
1981 {
1982         int tile_rows, tiles;
1983
1984         tile_rows = *y / 8;
1985         *y %= 8;
1986         tiles = *x / (512/bpp);
1987         *x %= 512/bpp;
1988
1989         return tile_rows * pitch * 8 + tiles * 4096;
1990 }
1991
1992 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993                              int x, int y)
1994 {
1995         struct drm_device *dev = crtc->dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998         struct intel_framebuffer *intel_fb;
1999         struct drm_i915_gem_object *obj;
2000         int plane = intel_crtc->plane;
2001         unsigned long linear_offset;
2002         u32 dspcntr;
2003         u32 reg;
2004
2005         switch (plane) {
2006         case 0:
2007         case 1:
2008                 break;
2009         default:
2010                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011                 return -EINVAL;
2012         }
2013
2014         intel_fb = to_intel_framebuffer(fb);
2015         obj = intel_fb->obj;
2016
2017         reg = DSPCNTR(plane);
2018         dspcntr = I915_READ(reg);
2019         /* Mask out pixel format bits in case we change it */
2020         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021         switch (fb->bits_per_pixel) {
2022         case 8:
2023                 dspcntr |= DISPPLANE_8BPP;
2024                 break;
2025         case 16:
2026                 if (fb->depth == 15)
2027                         dspcntr |= DISPPLANE_15_16BPP;
2028                 else
2029                         dspcntr |= DISPPLANE_16BPP;
2030                 break;
2031         case 24:
2032         case 32:
2033                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2034                 break;
2035         default:
2036                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2037                 return -EINVAL;
2038         }
2039         if (INTEL_INFO(dev)->gen >= 4) {
2040                 if (obj->tiling_mode != I915_TILING_NONE)
2041                         dspcntr |= DISPPLANE_TILED;
2042                 else
2043                         dspcntr &= ~DISPPLANE_TILED;
2044         }
2045
2046         I915_WRITE(reg, dspcntr);
2047
2048         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2049
2050         if (INTEL_INFO(dev)->gen >= 4) {
2051                 intel_crtc->dspaddr_offset =
2052                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2053                                                            fb->bits_per_pixel / 8,
2054                                                            fb->pitches[0]);
2055                 linear_offset -= intel_crtc->dspaddr_offset;
2056         } else {
2057                 intel_crtc->dspaddr_offset = linear_offset;
2058         }
2059
2060         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2061                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2062         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2063         if (INTEL_INFO(dev)->gen >= 4) {
2064                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2065                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2066                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2067                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2068         } else
2069                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2070         POSTING_READ(reg);
2071
2072         return 0;
2073 }
2074
2075 static int ironlake_update_plane(struct drm_crtc *crtc,
2076                                  struct drm_framebuffer *fb, int x, int y)
2077 {
2078         struct drm_device *dev = crtc->dev;
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081         struct intel_framebuffer *intel_fb;
2082         struct drm_i915_gem_object *obj;
2083         int plane = intel_crtc->plane;
2084         unsigned long linear_offset;
2085         u32 dspcntr;
2086         u32 reg;
2087
2088         switch (plane) {
2089         case 0:
2090         case 1:
2091         case 2:
2092                 break;
2093         default:
2094                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2095                 return -EINVAL;
2096         }
2097
2098         intel_fb = to_intel_framebuffer(fb);
2099         obj = intel_fb->obj;
2100
2101         reg = DSPCNTR(plane);
2102         dspcntr = I915_READ(reg);
2103         /* Mask out pixel format bits in case we change it */
2104         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2105         switch (fb->bits_per_pixel) {
2106         case 8:
2107                 dspcntr |= DISPPLANE_8BPP;
2108                 break;
2109         case 16:
2110                 if (fb->depth != 16)
2111                         return -EINVAL;
2112
2113                 dspcntr |= DISPPLANE_16BPP;
2114                 break;
2115         case 24:
2116         case 32:
2117                 if (fb->depth == 24)
2118                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119                 else if (fb->depth == 30)
2120                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2121                 else
2122                         return -EINVAL;
2123                 break;
2124         default:
2125                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2126                 return -EINVAL;
2127         }
2128
2129         if (obj->tiling_mode != I915_TILING_NONE)
2130                 dspcntr |= DISPPLANE_TILED;
2131         else
2132                 dspcntr &= ~DISPPLANE_TILED;
2133
2134         /* must disable */
2135         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137         I915_WRITE(reg, dspcntr);
2138
2139         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2140         intel_crtc->dspaddr_offset =
2141                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2142                                                    fb->bits_per_pixel / 8,
2143                                                    fb->pitches[0]);
2144         linear_offset -= intel_crtc->dspaddr_offset;
2145
2146         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2148         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2149         I915_MODIFY_DISPBASE(DSPSURF(plane),
2150                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2151         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2152         I915_WRITE(DSPLINOFF(plane), linear_offset);
2153         POSTING_READ(reg);
2154
2155         return 0;
2156 }
2157
2158 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2159 static int
2160 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2161                            int x, int y, enum mode_set_atomic state)
2162 {
2163         struct drm_device *dev = crtc->dev;
2164         struct drm_i915_private *dev_priv = dev->dev_private;
2165
2166         if (dev_priv->display.disable_fbc)
2167                 dev_priv->display.disable_fbc(dev);
2168         intel_increase_pllclock(crtc);
2169
2170         return dev_priv->display.update_plane(crtc, fb, x, y);
2171 }
2172
2173 static int
2174 intel_finish_fb(struct drm_framebuffer *old_fb)
2175 {
2176         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2177         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2178         bool was_interruptible = dev_priv->mm.interruptible;
2179         int ret;
2180
2181         wait_event(dev_priv->pending_flip_queue,
2182                    atomic_read(&dev_priv->mm.wedged) ||
2183                    atomic_read(&obj->pending_flip) == 0);
2184
2185         /* Big Hammer, we also need to ensure that any pending
2186          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2187          * current scanout is retired before unpinning the old
2188          * framebuffer.
2189          *
2190          * This should only fail upon a hung GPU, in which case we
2191          * can safely continue.
2192          */
2193         dev_priv->mm.interruptible = false;
2194         ret = i915_gem_object_finish_gpu(obj);
2195         dev_priv->mm.interruptible = was_interruptible;
2196
2197         return ret;
2198 }
2199
2200 static int
2201 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2202                     struct drm_framebuffer *old_fb)
2203 {
2204         struct drm_device *dev = crtc->dev;
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         struct drm_i915_master_private *master_priv;
2207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2208         int ret;
2209
2210         /* no fb bound */
2211         if (!crtc->fb) {
2212                 DRM_ERROR("No FB bound\n");
2213                 return 0;
2214         }
2215
2216         if(intel_crtc->plane > dev_priv->num_pipe) {
2217                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2218                                 intel_crtc->plane,
2219                                 dev_priv->num_pipe);
2220                 return -EINVAL;
2221         }
2222
2223         mutex_lock(&dev->struct_mutex);
2224         ret = intel_pin_and_fence_fb_obj(dev,
2225                                          to_intel_framebuffer(crtc->fb)->obj,
2226                                          NULL);
2227         if (ret != 0) {
2228                 mutex_unlock(&dev->struct_mutex);
2229                 DRM_ERROR("pin & fence failed\n");
2230                 return ret;
2231         }
2232
2233         if (old_fb)
2234                 intel_finish_fb(old_fb);
2235
2236         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2237         if (ret) {
2238                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2239                 mutex_unlock(&dev->struct_mutex);
2240                 DRM_ERROR("failed to update base address\n");
2241                 return ret;
2242         }
2243
2244         if (old_fb) {
2245                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2246                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2247         }
2248
2249         intel_update_fbc(dev);
2250         mutex_unlock(&dev->struct_mutex);
2251
2252         if (!dev->primary->master)
2253                 return 0;
2254
2255         master_priv = dev->primary->master->driver_priv;
2256         if (!master_priv->sarea_priv)
2257                 return 0;
2258
2259         if (intel_crtc->pipe) {
2260                 master_priv->sarea_priv->pipeB_x = x;
2261                 master_priv->sarea_priv->pipeB_y = y;
2262         } else {
2263                 master_priv->sarea_priv->pipeA_x = x;
2264                 master_priv->sarea_priv->pipeA_y = y;
2265         }
2266
2267         return 0;
2268 }
2269
2270 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2271 {
2272         struct drm_device *dev = crtc->dev;
2273         struct drm_i915_private *dev_priv = dev->dev_private;
2274         u32 dpa_ctl;
2275
2276         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2277         dpa_ctl = I915_READ(DP_A);
2278         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2279
2280         if (clock < 200000) {
2281                 u32 temp;
2282                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2283                 /* workaround for 160Mhz:
2284                    1) program 0x4600c bits 15:0 = 0x8124
2285                    2) program 0x46010 bit 0 = 1
2286                    3) program 0x46034 bit 24 = 1
2287                    4) program 0x64000 bit 14 = 1
2288                    */
2289                 temp = I915_READ(0x4600c);
2290                 temp &= 0xffff0000;
2291                 I915_WRITE(0x4600c, temp | 0x8124);
2292
2293                 temp = I915_READ(0x46010);
2294                 I915_WRITE(0x46010, temp | 1);
2295
2296                 temp = I915_READ(0x46034);
2297                 I915_WRITE(0x46034, temp | (1 << 24));
2298         } else {
2299                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2300         }
2301         I915_WRITE(DP_A, dpa_ctl);
2302
2303         POSTING_READ(DP_A);
2304         udelay(500);
2305 }
2306
2307 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2308 {
2309         struct drm_device *dev = crtc->dev;
2310         struct drm_i915_private *dev_priv = dev->dev_private;
2311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2312         int pipe = intel_crtc->pipe;
2313         u32 reg, temp;
2314
2315         /* enable normal train */
2316         reg = FDI_TX_CTL(pipe);
2317         temp = I915_READ(reg);
2318         if (IS_IVYBRIDGE(dev)) {
2319                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2320                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2321         } else {
2322                 temp &= ~FDI_LINK_TRAIN_NONE;
2323                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2324         }
2325         I915_WRITE(reg, temp);
2326
2327         reg = FDI_RX_CTL(pipe);
2328         temp = I915_READ(reg);
2329         if (HAS_PCH_CPT(dev)) {
2330                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2331                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2332         } else {
2333                 temp &= ~FDI_LINK_TRAIN_NONE;
2334                 temp |= FDI_LINK_TRAIN_NONE;
2335         }
2336         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2337
2338         /* wait one idle pattern time */
2339         POSTING_READ(reg);
2340         udelay(1000);
2341
2342         /* IVB wants error correction enabled */
2343         if (IS_IVYBRIDGE(dev))
2344                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2345                            FDI_FE_ERRC_ENABLE);
2346 }
2347
2348 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2349 {
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         u32 flags = I915_READ(SOUTH_CHICKEN1);
2352
2353         flags |= FDI_PHASE_SYNC_OVR(pipe);
2354         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2355         flags |= FDI_PHASE_SYNC_EN(pipe);
2356         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2357         POSTING_READ(SOUTH_CHICKEN1);
2358 }
2359
2360 /* The FDI link training functions for ILK/Ibexpeak. */
2361 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366         int pipe = intel_crtc->pipe;
2367         int plane = intel_crtc->plane;
2368         u32 reg, temp, tries;
2369
2370         /* FDI needs bits from pipe & plane first */
2371         assert_pipe_enabled(dev_priv, pipe);
2372         assert_plane_enabled(dev_priv, plane);
2373
2374         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375            for train result */
2376         reg = FDI_RX_IMR(pipe);
2377         temp = I915_READ(reg);
2378         temp &= ~FDI_RX_SYMBOL_LOCK;
2379         temp &= ~FDI_RX_BIT_LOCK;
2380         I915_WRITE(reg, temp);
2381         I915_READ(reg);
2382         udelay(150);
2383
2384         /* enable CPU FDI TX and PCH FDI RX */
2385         reg = FDI_TX_CTL(pipe);
2386         temp = I915_READ(reg);
2387         temp &= ~(7 << 19);
2388         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_1;
2391         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2392
2393         reg = FDI_RX_CTL(pipe);
2394         temp = I915_READ(reg);
2395         temp &= ~FDI_LINK_TRAIN_NONE;
2396         temp |= FDI_LINK_TRAIN_PATTERN_1;
2397         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399         POSTING_READ(reg);
2400         udelay(150);
2401
2402         /* Ironlake workaround, enable clock pointer after FDI enable*/
2403         if (HAS_PCH_IBX(dev)) {
2404                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406                            FDI_RX_PHASE_SYNC_POINTER_EN);
2407         }
2408
2409         reg = FDI_RX_IIR(pipe);
2410         for (tries = 0; tries < 5; tries++) {
2411                 temp = I915_READ(reg);
2412                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2413
2414                 if ((temp & FDI_RX_BIT_LOCK)) {
2415                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2416                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2417                         break;
2418                 }
2419         }
2420         if (tries == 5)
2421                 DRM_ERROR("FDI train 1 fail!\n");
2422
2423         /* Train 2 */
2424         reg = FDI_TX_CTL(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_2;
2428         I915_WRITE(reg, temp);
2429
2430         reg = FDI_RX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_2;
2434         I915_WRITE(reg, temp);
2435
2436         POSTING_READ(reg);
2437         udelay(150);
2438
2439         reg = FDI_RX_IIR(pipe);
2440         for (tries = 0; tries < 5; tries++) {
2441                 temp = I915_READ(reg);
2442                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2443
2444                 if (temp & FDI_RX_SYMBOL_LOCK) {
2445                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2446                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2447                         break;
2448                 }
2449         }
2450         if (tries == 5)
2451                 DRM_ERROR("FDI train 2 fail!\n");
2452
2453         DRM_DEBUG_KMS("FDI train done\n");
2454
2455 }
2456
2457 static const int snb_b_fdi_train_param[] = {
2458         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2459         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2460         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2461         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2462 };
2463
2464 /* The FDI link training functions for SNB/Cougarpoint. */
2465 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2466 {
2467         struct drm_device *dev = crtc->dev;
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470         int pipe = intel_crtc->pipe;
2471         u32 reg, temp, i, retry;
2472
2473         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474            for train result */
2475         reg = FDI_RX_IMR(pipe);
2476         temp = I915_READ(reg);
2477         temp &= ~FDI_RX_SYMBOL_LOCK;
2478         temp &= ~FDI_RX_BIT_LOCK;
2479         I915_WRITE(reg, temp);
2480
2481         POSTING_READ(reg);
2482         udelay(150);
2483
2484         /* enable CPU FDI TX and PCH FDI RX */
2485         reg = FDI_TX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         temp &= ~(7 << 19);
2488         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2489         temp &= ~FDI_LINK_TRAIN_NONE;
2490         temp |= FDI_LINK_TRAIN_PATTERN_1;
2491         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492         /* SNB-B */
2493         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2494         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2495
2496         reg = FDI_RX_CTL(pipe);
2497         temp = I915_READ(reg);
2498         if (HAS_PCH_CPT(dev)) {
2499                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501         } else {
2502                 temp &= ~FDI_LINK_TRAIN_NONE;
2503                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504         }
2505         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507         POSTING_READ(reg);
2508         udelay(150);
2509
2510         if (HAS_PCH_CPT(dev))
2511                 cpt_phase_pointer_enable(dev, pipe);
2512
2513         for (i = 0; i < 4; i++) {
2514                 reg = FDI_TX_CTL(pipe);
2515                 temp = I915_READ(reg);
2516                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517                 temp |= snb_b_fdi_train_param[i];
2518                 I915_WRITE(reg, temp);
2519
2520                 POSTING_READ(reg);
2521                 udelay(500);
2522
2523                 for (retry = 0; retry < 5; retry++) {
2524                         reg = FDI_RX_IIR(pipe);
2525                         temp = I915_READ(reg);
2526                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2527                         if (temp & FDI_RX_BIT_LOCK) {
2528                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2529                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2530                                 break;
2531                         }
2532                         udelay(50);
2533                 }
2534                 if (retry < 5)
2535                         break;
2536         }
2537         if (i == 4)
2538                 DRM_ERROR("FDI train 1 fail!\n");
2539
2540         /* Train 2 */
2541         reg = FDI_TX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         temp &= ~FDI_LINK_TRAIN_NONE;
2544         temp |= FDI_LINK_TRAIN_PATTERN_2;
2545         if (IS_GEN6(dev)) {
2546                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547                 /* SNB-B */
2548                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2549         }
2550         I915_WRITE(reg, temp);
2551
2552         reg = FDI_RX_CTL(pipe);
2553         temp = I915_READ(reg);
2554         if (HAS_PCH_CPT(dev)) {
2555                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2557         } else {
2558                 temp &= ~FDI_LINK_TRAIN_NONE;
2559                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560         }
2561         I915_WRITE(reg, temp);
2562
2563         POSTING_READ(reg);
2564         udelay(150);
2565
2566         for (i = 0; i < 4; i++) {
2567                 reg = FDI_TX_CTL(pipe);
2568                 temp = I915_READ(reg);
2569                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2570                 temp |= snb_b_fdi_train_param[i];
2571                 I915_WRITE(reg, temp);
2572
2573                 POSTING_READ(reg);
2574                 udelay(500);
2575
2576                 for (retry = 0; retry < 5; retry++) {
2577                         reg = FDI_RX_IIR(pipe);
2578                         temp = I915_READ(reg);
2579                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2580                         if (temp & FDI_RX_SYMBOL_LOCK) {
2581                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2582                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583                                 break;
2584                         }
2585                         udelay(50);
2586                 }
2587                 if (retry < 5)
2588                         break;
2589         }
2590         if (i == 4)
2591                 DRM_ERROR("FDI train 2 fail!\n");
2592
2593         DRM_DEBUG_KMS("FDI train done.\n");
2594 }
2595
2596 /* Manual link training for Ivy Bridge A0 parts */
2597 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2598 {
2599         struct drm_device *dev = crtc->dev;
2600         struct drm_i915_private *dev_priv = dev->dev_private;
2601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602         int pipe = intel_crtc->pipe;
2603         u32 reg, temp, i;
2604
2605         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606            for train result */
2607         reg = FDI_RX_IMR(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_RX_SYMBOL_LOCK;
2610         temp &= ~FDI_RX_BIT_LOCK;
2611         I915_WRITE(reg, temp);
2612
2613         POSTING_READ(reg);
2614         udelay(150);
2615
2616         /* enable CPU FDI TX and PCH FDI RX */
2617         reg = FDI_TX_CTL(pipe);
2618         temp = I915_READ(reg);
2619         temp &= ~(7 << 19);
2620         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2621         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2623         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2625         temp |= FDI_COMPOSITE_SYNC;
2626         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_AUTO;
2631         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         temp |= FDI_COMPOSITE_SYNC;
2634         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636         POSTING_READ(reg);
2637         udelay(150);
2638
2639         if (HAS_PCH_CPT(dev))
2640                 cpt_phase_pointer_enable(dev, pipe);
2641
2642         for (i = 0; i < 4; i++) {
2643                 reg = FDI_TX_CTL(pipe);
2644                 temp = I915_READ(reg);
2645                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646                 temp |= snb_b_fdi_train_param[i];
2647                 I915_WRITE(reg, temp);
2648
2649                 POSTING_READ(reg);
2650                 udelay(500);
2651
2652                 reg = FDI_RX_IIR(pipe);
2653                 temp = I915_READ(reg);
2654                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655
2656                 if (temp & FDI_RX_BIT_LOCK ||
2657                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2658                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2659                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2660                         break;
2661                 }
2662         }
2663         if (i == 4)
2664                 DRM_ERROR("FDI train 1 fail!\n");
2665
2666         /* Train 2 */
2667         reg = FDI_TX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2670         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2671         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673         I915_WRITE(reg, temp);
2674
2675         reg = FDI_RX_CTL(pipe);
2676         temp = I915_READ(reg);
2677         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2678         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2679         I915_WRITE(reg, temp);
2680
2681         POSTING_READ(reg);
2682         udelay(150);
2683
2684         for (i = 0; i < 4; i++) {
2685                 reg = FDI_TX_CTL(pipe);
2686                 temp = I915_READ(reg);
2687                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688                 temp |= snb_b_fdi_train_param[i];
2689                 I915_WRITE(reg, temp);
2690
2691                 POSTING_READ(reg);
2692                 udelay(500);
2693
2694                 reg = FDI_RX_IIR(pipe);
2695                 temp = I915_READ(reg);
2696                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697
2698                 if (temp & FDI_RX_SYMBOL_LOCK) {
2699                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2701                         break;
2702                 }
2703         }
2704         if (i == 4)
2705                 DRM_ERROR("FDI train 2 fail!\n");
2706
2707         DRM_DEBUG_KMS("FDI train done.\n");
2708 }
2709
2710 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* Write the TU size bits so error detection works */
2719         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2720                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2721
2722         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2723         reg = FDI_RX_CTL(pipe);
2724         temp = I915_READ(reg);
2725         temp &= ~((0x7 << 19) | (0x7 << 16));
2726         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2727         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2728         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Switch from Rawclk to PCDclk */
2734         temp = I915_READ(reg);
2735         I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737         POSTING_READ(reg);
2738         udelay(200);
2739
2740         /* On Haswell, the PLL configuration for ports and pipes is handled
2741          * separately, as part of DDI setup */
2742         if (!IS_HASWELL(dev)) {
2743                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744                 reg = FDI_TX_CTL(pipe);
2745                 temp = I915_READ(reg);
2746                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749                         POSTING_READ(reg);
2750                         udelay(100);
2751                 }
2752         }
2753 }
2754
2755 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2756 {
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         u32 flags = I915_READ(SOUTH_CHICKEN1);
2759
2760         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2761         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2762         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2763         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2764         POSTING_READ(SOUTH_CHICKEN1);
2765 }
2766 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2767 {
2768         struct drm_device *dev = crtc->dev;
2769         struct drm_i915_private *dev_priv = dev->dev_private;
2770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771         int pipe = intel_crtc->pipe;
2772         u32 reg, temp;
2773
2774         /* disable CPU FDI tx and PCH FDI rx */
2775         reg = FDI_TX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2778         POSTING_READ(reg);
2779
2780         reg = FDI_RX_CTL(pipe);
2781         temp = I915_READ(reg);
2782         temp &= ~(0x7 << 16);
2783         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2784         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2785
2786         POSTING_READ(reg);
2787         udelay(100);
2788
2789         /* Ironlake workaround, disable clock pointer after downing FDI */
2790         if (HAS_PCH_IBX(dev)) {
2791                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2792                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2793                            I915_READ(FDI_RX_CHICKEN(pipe) &
2794                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2795         } else if (HAS_PCH_CPT(dev)) {
2796                 cpt_phase_pointer_disable(dev, pipe);
2797         }
2798
2799         /* still set train pattern 1 */
2800         reg = FDI_TX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         temp &= ~FDI_LINK_TRAIN_NONE;
2803         temp |= FDI_LINK_TRAIN_PATTERN_1;
2804         I915_WRITE(reg, temp);
2805
2806         reg = FDI_RX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         if (HAS_PCH_CPT(dev)) {
2809                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2811         } else {
2812                 temp &= ~FDI_LINK_TRAIN_NONE;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2814         }
2815         /* BPC in FDI rx is consistent with that in PIPECONF */
2816         temp &= ~(0x07 << 16);
2817         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818         I915_WRITE(reg, temp);
2819
2820         POSTING_READ(reg);
2821         udelay(100);
2822 }
2823
2824 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2825 {
2826         struct drm_device *dev = crtc->dev;
2827
2828         if (crtc->fb == NULL)
2829                 return;
2830
2831         mutex_lock(&dev->struct_mutex);
2832         intel_finish_fb(crtc->fb);
2833         mutex_unlock(&dev->struct_mutex);
2834 }
2835
2836 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct intel_encoder *encoder;
2840
2841         /*
2842          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2843          * must be driven by its own crtc; no sharing is possible.
2844          */
2845         for_each_encoder_on_crtc(dev, crtc, encoder) {
2846
2847                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2848                  * CPU handles all others */
2849                 if (IS_HASWELL(dev)) {
2850                         /* It is still unclear how this will work on PPT, so throw up a warning */
2851                         WARN_ON(!HAS_PCH_LPT(dev));
2852
2853                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2854                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2855                                 return true;
2856                         } else {
2857                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2858                                                 encoder->type);
2859                                 return false;
2860                         }
2861                 }
2862
2863                 switch (encoder->type) {
2864                 case INTEL_OUTPUT_EDP:
2865                         if (!intel_encoder_is_pch_edp(&encoder->base))
2866                                 return false;
2867                         continue;
2868                 }
2869         }
2870
2871         return true;
2872 }
2873
2874 /* Program iCLKIP clock to the desired frequency */
2875 static void lpt_program_iclkip(struct drm_crtc *crtc)
2876 {
2877         struct drm_device *dev = crtc->dev;
2878         struct drm_i915_private *dev_priv = dev->dev_private;
2879         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2880         u32 temp;
2881
2882         /* It is necessary to ungate the pixclk gate prior to programming
2883          * the divisors, and gate it back when it is done.
2884          */
2885         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2886
2887         /* Disable SSCCTL */
2888         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2889                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2890                                         SBI_SSCCTL_DISABLE);
2891
2892         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2893         if (crtc->mode.clock == 20000) {
2894                 auxdiv = 1;
2895                 divsel = 0x41;
2896                 phaseinc = 0x20;
2897         } else {
2898                 /* The iCLK virtual clock root frequency is in MHz,
2899                  * but the crtc->mode.clock in in KHz. To get the divisors,
2900                  * it is necessary to divide one by another, so we
2901                  * convert the virtual clock precision to KHz here for higher
2902                  * precision.
2903                  */
2904                 u32 iclk_virtual_root_freq = 172800 * 1000;
2905                 u32 iclk_pi_range = 64;
2906                 u32 desired_divisor, msb_divisor_value, pi_value;
2907
2908                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2909                 msb_divisor_value = desired_divisor / iclk_pi_range;
2910                 pi_value = desired_divisor % iclk_pi_range;
2911
2912                 auxdiv = 0;
2913                 divsel = msb_divisor_value - 2;
2914                 phaseinc = pi_value;
2915         }
2916
2917         /* This should not happen with any sane values */
2918         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2919                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2920         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2921                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2922
2923         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2924                         crtc->mode.clock,
2925                         auxdiv,
2926                         divsel,
2927                         phasedir,
2928                         phaseinc);
2929
2930         /* Program SSCDIVINTPHASE6 */
2931         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2932         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2933         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2934         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2935         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2936         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2937         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2938
2939         intel_sbi_write(dev_priv,
2940                         SBI_SSCDIVINTPHASE6,
2941                         temp);
2942
2943         /* Program SSCAUXDIV */
2944         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2945         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2946         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2947         intel_sbi_write(dev_priv,
2948                         SBI_SSCAUXDIV6,
2949                         temp);
2950
2951
2952         /* Enable modulator and associated divider */
2953         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2954         temp &= ~SBI_SSCCTL_DISABLE;
2955         intel_sbi_write(dev_priv,
2956                         SBI_SSCCTL6,
2957                         temp);
2958
2959         /* Wait for initialization time */
2960         udelay(24);
2961
2962         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2963 }
2964
2965 /*
2966  * Enable PCH resources required for PCH ports:
2967  *   - PCH PLLs
2968  *   - FDI training & RX/TX
2969  *   - update transcoder timings
2970  *   - DP transcoding bits
2971  *   - transcoder
2972  */
2973 static void ironlake_pch_enable(struct drm_crtc *crtc)
2974 {
2975         struct drm_device *dev = crtc->dev;
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2978         int pipe = intel_crtc->pipe;
2979         u32 reg, temp;
2980
2981         assert_transcoder_disabled(dev_priv, pipe);
2982
2983         /* For PCH output, training FDI link */
2984         dev_priv->display.fdi_link_train(crtc);
2985
2986         intel_enable_pch_pll(intel_crtc);
2987
2988         if (HAS_PCH_LPT(dev)) {
2989                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2990                 lpt_program_iclkip(crtc);
2991         } else if (HAS_PCH_CPT(dev)) {
2992                 u32 sel;
2993
2994                 temp = I915_READ(PCH_DPLL_SEL);
2995                 switch (pipe) {
2996                 default:
2997                 case 0:
2998                         temp |= TRANSA_DPLL_ENABLE;
2999                         sel = TRANSA_DPLLB_SEL;
3000                         break;
3001                 case 1:
3002                         temp |= TRANSB_DPLL_ENABLE;
3003                         sel = TRANSB_DPLLB_SEL;
3004                         break;
3005                 case 2:
3006                         temp |= TRANSC_DPLL_ENABLE;
3007                         sel = TRANSC_DPLLB_SEL;
3008                         break;
3009                 }
3010                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3011                         temp |= sel;
3012                 else
3013                         temp &= ~sel;
3014                 I915_WRITE(PCH_DPLL_SEL, temp);
3015         }
3016
3017         /* set transcoder timing, panel must allow it */
3018         assert_panel_unlocked(dev_priv, pipe);
3019         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3020         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3021         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3022
3023         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3024         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3025         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3026         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3027
3028         if (!IS_HASWELL(dev))
3029                 intel_fdi_normal_train(crtc);
3030
3031         /* For PCH DP, enable TRANS_DP_CTL */
3032         if (HAS_PCH_CPT(dev) &&
3033             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3035                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3036                 reg = TRANS_DP_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3039                           TRANS_DP_SYNC_MASK |
3040                           TRANS_DP_BPC_MASK);
3041                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042                          TRANS_DP_ENH_FRAMING);
3043                 temp |= bpc << 9; /* same format but at 11:9 */
3044
3045                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3046                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3048                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3049
3050                 switch (intel_trans_dp_port_sel(crtc)) {
3051                 case PCH_DP_B:
3052                         temp |= TRANS_DP_PORT_SEL_B;
3053                         break;
3054                 case PCH_DP_C:
3055                         temp |= TRANS_DP_PORT_SEL_C;
3056                         break;
3057                 case PCH_DP_D:
3058                         temp |= TRANS_DP_PORT_SEL_D;
3059                         break;
3060                 default:
3061                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3062                         temp |= TRANS_DP_PORT_SEL_B;
3063                         break;
3064                 }
3065
3066                 I915_WRITE(reg, temp);
3067         }
3068
3069         intel_enable_transcoder(dev_priv, pipe);
3070 }
3071
3072 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3073 {
3074         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3075
3076         if (pll == NULL)
3077                 return;
3078
3079         if (pll->refcount == 0) {
3080                 WARN(1, "bad PCH PLL refcount\n");
3081                 return;
3082         }
3083
3084         --pll->refcount;
3085         intel_crtc->pch_pll = NULL;
3086 }
3087
3088 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3089 {
3090         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3091         struct intel_pch_pll *pll;
3092         int i;
3093
3094         pll = intel_crtc->pch_pll;
3095         if (pll) {
3096                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3097                               intel_crtc->base.base.id, pll->pll_reg);
3098                 goto prepare;
3099         }
3100
3101         if (HAS_PCH_IBX(dev_priv->dev)) {
3102                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3103                 i = intel_crtc->pipe;
3104                 pll = &dev_priv->pch_plls[i];
3105
3106                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3107                               intel_crtc->base.base.id, pll->pll_reg);
3108
3109                 goto found;
3110         }
3111
3112         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3113                 pll = &dev_priv->pch_plls[i];
3114
3115                 /* Only want to check enabled timings first */
3116                 if (pll->refcount == 0)
3117                         continue;
3118
3119                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3120                     fp == I915_READ(pll->fp0_reg)) {
3121                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3122                                       intel_crtc->base.base.id,
3123                                       pll->pll_reg, pll->refcount, pll->active);
3124
3125                         goto found;
3126                 }
3127         }
3128
3129         /* Ok no matching timings, maybe there's a free one? */
3130         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3131                 pll = &dev_priv->pch_plls[i];
3132                 if (pll->refcount == 0) {
3133                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3134                                       intel_crtc->base.base.id, pll->pll_reg);
3135                         goto found;
3136                 }
3137         }
3138
3139         return NULL;
3140
3141 found:
3142         intel_crtc->pch_pll = pll;
3143         pll->refcount++;
3144         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3145 prepare: /* separate function? */
3146         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3147
3148         /* Wait for the clocks to stabilize before rewriting the regs */
3149         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3150         POSTING_READ(pll->pll_reg);
3151         udelay(150);
3152
3153         I915_WRITE(pll->fp0_reg, fp);
3154         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3155         pll->on = false;
3156         return pll;
3157 }
3158
3159 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3160 {
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3163         u32 temp;
3164
3165         temp = I915_READ(dslreg);
3166         udelay(500);
3167         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3168                 /* Without this, mode sets may fail silently on FDI */
3169                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3170                 udelay(250);
3171                 I915_WRITE(tc2reg, 0);
3172                 if (wait_for(I915_READ(dslreg) != temp, 5))
3173                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3174         }
3175 }
3176
3177 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3178 {
3179         struct drm_device *dev = crtc->dev;
3180         struct drm_i915_private *dev_priv = dev->dev_private;
3181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182         int pipe = intel_crtc->pipe;
3183         int plane = intel_crtc->plane;
3184         u32 temp;
3185         bool is_pch_port;
3186
3187         if (intel_crtc->active)
3188                 return;
3189
3190         intel_crtc->active = true;
3191         intel_update_watermarks(dev);
3192
3193         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3194                 temp = I915_READ(PCH_LVDS);
3195                 if ((temp & LVDS_PORT_EN) == 0)
3196                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3197         }
3198
3199         is_pch_port = intel_crtc_driving_pch(crtc);
3200
3201         if (is_pch_port)
3202                 ironlake_fdi_pll_enable(crtc);
3203         else
3204                 ironlake_fdi_disable(crtc);
3205
3206         /* Enable panel fitting for LVDS */
3207         if (dev_priv->pch_pf_size &&
3208             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3209                 /* Force use of hard-coded filter coefficients
3210                  * as some pre-programmed values are broken,
3211                  * e.g. x201.
3212                  */
3213                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3214                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3215                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3216         }
3217
3218         /*
3219          * On ILK+ LUT must be loaded before the pipe is running but with
3220          * clocks enabled
3221          */
3222         intel_crtc_load_lut(crtc);
3223
3224         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3225         intel_enable_plane(dev_priv, plane, pipe);
3226
3227         if (is_pch_port)
3228                 ironlake_pch_enable(crtc);
3229
3230         mutex_lock(&dev->struct_mutex);
3231         intel_update_fbc(dev);
3232         mutex_unlock(&dev->struct_mutex);
3233
3234         intel_crtc_update_cursor(crtc, true);
3235 }
3236
3237 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         int pipe = intel_crtc->pipe;
3243         int plane = intel_crtc->plane;
3244         u32 reg, temp;
3245
3246         if (!intel_crtc->active)
3247                 return;
3248
3249         intel_crtc_wait_for_pending_flips(crtc);
3250         drm_vblank_off(dev, pipe);
3251         intel_crtc_update_cursor(crtc, false);
3252
3253         intel_disable_plane(dev_priv, plane, pipe);
3254
3255         if (dev_priv->cfb_plane == plane)
3256                 intel_disable_fbc(dev);
3257
3258         intel_disable_pipe(dev_priv, pipe);
3259
3260         /* Disable PF */
3261         I915_WRITE(PF_CTL(pipe), 0);
3262         I915_WRITE(PF_WIN_SZ(pipe), 0);
3263
3264         ironlake_fdi_disable(crtc);
3265
3266         /* This is a horrible layering violation; we should be doing this in
3267          * the connector/encoder ->prepare instead, but we don't always have
3268          * enough information there about the config to know whether it will
3269          * actually be necessary or just cause undesired flicker.
3270          */
3271         intel_disable_pch_ports(dev_priv, pipe);
3272
3273         intel_disable_transcoder(dev_priv, pipe);
3274
3275         if (HAS_PCH_CPT(dev)) {
3276                 /* disable TRANS_DP_CTL */
3277                 reg = TRANS_DP_CTL(pipe);
3278                 temp = I915_READ(reg);
3279                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3280                 temp |= TRANS_DP_PORT_SEL_NONE;
3281                 I915_WRITE(reg, temp);
3282
3283                 /* disable DPLL_SEL */
3284                 temp = I915_READ(PCH_DPLL_SEL);
3285                 switch (pipe) {
3286                 case 0:
3287                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3288                         break;
3289                 case 1:
3290                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3291                         break;
3292                 case 2:
3293                         /* C shares PLL A or B */
3294                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3295                         break;
3296                 default:
3297                         BUG(); /* wtf */
3298                 }
3299                 I915_WRITE(PCH_DPLL_SEL, temp);
3300         }
3301
3302         /* disable PCH DPLL */
3303         intel_disable_pch_pll(intel_crtc);
3304
3305         /* Switch from PCDclk to Rawclk */
3306         reg = FDI_RX_CTL(pipe);
3307         temp = I915_READ(reg);
3308         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3309
3310         /* Disable CPU FDI TX PLL */
3311         reg = FDI_TX_CTL(pipe);
3312         temp = I915_READ(reg);
3313         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3314
3315         POSTING_READ(reg);
3316         udelay(100);
3317
3318         reg = FDI_RX_CTL(pipe);
3319         temp = I915_READ(reg);
3320         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3321
3322         /* Wait for the clocks to turn off. */
3323         POSTING_READ(reg);
3324         udelay(100);
3325
3326         intel_crtc->active = false;
3327         intel_update_watermarks(dev);
3328
3329         mutex_lock(&dev->struct_mutex);
3330         intel_update_fbc(dev);
3331         mutex_unlock(&dev->struct_mutex);
3332 }
3333
3334 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3335 {
3336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337         int pipe = intel_crtc->pipe;
3338         int plane = intel_crtc->plane;
3339
3340         /* XXX: When our outputs are all unaware of DPMS modes other than off
3341          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3342          */
3343         switch (mode) {
3344         case DRM_MODE_DPMS_ON:
3345         case DRM_MODE_DPMS_STANDBY:
3346         case DRM_MODE_DPMS_SUSPEND:
3347                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3348                 ironlake_crtc_enable(crtc);
3349                 break;
3350
3351         case DRM_MODE_DPMS_OFF:
3352                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3353                 ironlake_crtc_disable(crtc);
3354                 break;
3355         }
3356 }
3357
3358 static void ironlake_crtc_off(struct drm_crtc *crtc)
3359 {
3360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361         intel_put_pch_pll(intel_crtc);
3362 }
3363
3364 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3365 {
3366         if (!enable && intel_crtc->overlay) {
3367                 struct drm_device *dev = intel_crtc->base.dev;
3368                 struct drm_i915_private *dev_priv = dev->dev_private;
3369
3370                 mutex_lock(&dev->struct_mutex);
3371                 dev_priv->mm.interruptible = false;
3372                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3373                 dev_priv->mm.interruptible = true;
3374                 mutex_unlock(&dev->struct_mutex);
3375         }
3376
3377         /* Let userspace switch the overlay on again. In most cases userspace
3378          * has to recompute where to put it anyway.
3379          */
3380 }
3381
3382 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3383 {
3384         struct drm_device *dev = crtc->dev;
3385         struct drm_i915_private *dev_priv = dev->dev_private;
3386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3387         int pipe = intel_crtc->pipe;
3388         int plane = intel_crtc->plane;
3389
3390         if (intel_crtc->active)
3391                 return;
3392
3393         intel_crtc->active = true;
3394         intel_update_watermarks(dev);
3395
3396         intel_enable_pll(dev_priv, pipe);
3397         intel_enable_pipe(dev_priv, pipe, false);
3398         intel_enable_plane(dev_priv, plane, pipe);
3399
3400         intel_crtc_load_lut(crtc);
3401         intel_update_fbc(dev);
3402
3403         /* Give the overlay scaler a chance to enable if it's on this pipe */
3404         intel_crtc_dpms_overlay(intel_crtc, true);
3405         intel_crtc_update_cursor(crtc, true);
3406 }
3407
3408 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3409 {
3410         struct drm_device *dev = crtc->dev;
3411         struct drm_i915_private *dev_priv = dev->dev_private;
3412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3413         int pipe = intel_crtc->pipe;
3414         int plane = intel_crtc->plane;
3415
3416         if (!intel_crtc->active)
3417                 return;
3418
3419         /* Give the overlay scaler a chance to disable if it's on this pipe */
3420         intel_crtc_wait_for_pending_flips(crtc);
3421         drm_vblank_off(dev, pipe);
3422         intel_crtc_dpms_overlay(intel_crtc, false);
3423         intel_crtc_update_cursor(crtc, false);
3424
3425         if (dev_priv->cfb_plane == plane)
3426                 intel_disable_fbc(dev);
3427
3428         intel_disable_plane(dev_priv, plane, pipe);
3429         intel_disable_pipe(dev_priv, pipe);
3430         intel_disable_pll(dev_priv, pipe);
3431
3432         intel_crtc->active = false;
3433         intel_update_fbc(dev);
3434         intel_update_watermarks(dev);
3435 }
3436
3437 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3438 {
3439         /* XXX: When our outputs are all unaware of DPMS modes other than off
3440          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3441          */
3442         switch (mode) {
3443         case DRM_MODE_DPMS_ON:
3444         case DRM_MODE_DPMS_STANDBY:
3445         case DRM_MODE_DPMS_SUSPEND:
3446                 i9xx_crtc_enable(crtc);
3447                 break;
3448         case DRM_MODE_DPMS_OFF:
3449                 i9xx_crtc_disable(crtc);
3450                 break;
3451         }
3452 }
3453
3454 static void i9xx_crtc_off(struct drm_crtc *crtc)
3455 {
3456 }
3457
3458 /**
3459  * Sets the power management mode of the pipe and plane.
3460  */
3461 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3462 {
3463         struct drm_device *dev = crtc->dev;
3464         struct drm_i915_private *dev_priv = dev->dev_private;
3465         struct drm_i915_master_private *master_priv;
3466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467         int pipe = intel_crtc->pipe;
3468         bool enabled;
3469
3470         if (intel_crtc->dpms_mode == mode)
3471                 return;
3472
3473         intel_crtc->dpms_mode = mode;
3474
3475         dev_priv->display.dpms(crtc, mode);
3476
3477         if (!dev->primary->master)
3478                 return;
3479
3480         master_priv = dev->primary->master->driver_priv;
3481         if (!master_priv->sarea_priv)
3482                 return;
3483
3484         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3485
3486         switch (pipe) {
3487         case 0:
3488                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3489                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3490                 break;
3491         case 1:
3492                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3493                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3494                 break;
3495         default:
3496                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3497                 break;
3498         }
3499 }
3500
3501 static void intel_crtc_disable(struct drm_crtc *crtc)
3502 {
3503         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506
3507         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3508         dev_priv->display.off(crtc);
3509
3510         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3511         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3512
3513         if (crtc->fb) {
3514                 mutex_lock(&dev->struct_mutex);
3515                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3516                 mutex_unlock(&dev->struct_mutex);
3517         }
3518 }
3519
3520 /* Prepare for a mode set.
3521  *
3522  * Note we could be a lot smarter here.  We need to figure out which outputs
3523  * will be enabled, which disabled (in short, how the config will changes)
3524  * and perform the minimum necessary steps to accomplish that, e.g. updating
3525  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3526  * panel fitting is in the proper state, etc.
3527  */
3528 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3529 {
3530         i9xx_crtc_disable(crtc);
3531 }
3532
3533 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3534 {
3535         i9xx_crtc_enable(crtc);
3536 }
3537
3538 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3539 {
3540         ironlake_crtc_disable(crtc);
3541 }
3542
3543 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3544 {
3545         ironlake_crtc_enable(crtc);
3546 }
3547
3548 void intel_encoder_prepare(struct drm_encoder *encoder)
3549 {
3550         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3551         /* lvds has its own version of prepare see intel_lvds_prepare */
3552         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3553 }
3554
3555 void intel_encoder_commit(struct drm_encoder *encoder)
3556 {
3557         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3558         struct drm_device *dev = encoder->dev;
3559         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3560
3561         /* lvds has its own version of commit see intel_lvds_commit */
3562         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3563
3564         if (HAS_PCH_CPT(dev))
3565                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3566 }
3567
3568 void intel_encoder_destroy(struct drm_encoder *encoder)
3569 {
3570         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3571
3572         drm_encoder_cleanup(encoder);
3573         kfree(intel_encoder);
3574 }
3575
3576 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3577                                   const struct drm_display_mode *mode,
3578                                   struct drm_display_mode *adjusted_mode)
3579 {
3580         struct drm_device *dev = crtc->dev;
3581
3582         if (HAS_PCH_SPLIT(dev)) {
3583                 /* FDI link clock is fixed at 2.7G */
3584                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3585                         return false;
3586         }
3587
3588         /* All interlaced capable intel hw wants timings in frames. Note though
3589          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3590          * timings, so we need to be careful not to clobber these.*/
3591         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3592                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3593
3594         return true;
3595 }
3596
3597 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3598 {
3599         return 400000; /* FIXME */
3600 }
3601
3602 static int i945_get_display_clock_speed(struct drm_device *dev)
3603 {
3604         return 400000;
3605 }
3606
3607 static int i915_get_display_clock_speed(struct drm_device *dev)
3608 {
3609         return 333000;
3610 }
3611
3612 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3613 {
3614         return 200000;
3615 }
3616
3617 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3618 {
3619         u16 gcfgc = 0;
3620
3621         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3622
3623         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3624                 return 133000;
3625         else {
3626                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3627                 case GC_DISPLAY_CLOCK_333_MHZ:
3628                         return 333000;
3629                 default:
3630                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3631                         return 190000;
3632                 }
3633         }
3634 }
3635
3636 static int i865_get_display_clock_speed(struct drm_device *dev)
3637 {
3638         return 266000;
3639 }
3640
3641 static int i855_get_display_clock_speed(struct drm_device *dev)
3642 {
3643         u16 hpllcc = 0;
3644         /* Assume that the hardware is in the high speed state.  This
3645          * should be the default.
3646          */
3647         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3648         case GC_CLOCK_133_200:
3649         case GC_CLOCK_100_200:
3650                 return 200000;
3651         case GC_CLOCK_166_250:
3652                 return 250000;
3653         case GC_CLOCK_100_133:
3654                 return 133000;
3655         }
3656
3657         /* Shouldn't happen */
3658         return 0;
3659 }
3660
3661 static int i830_get_display_clock_speed(struct drm_device *dev)
3662 {
3663         return 133000;
3664 }
3665
3666 struct fdi_m_n {
3667         u32        tu;
3668         u32        gmch_m;
3669         u32        gmch_n;
3670         u32        link_m;
3671         u32        link_n;
3672 };
3673
3674 static void
3675 fdi_reduce_ratio(u32 *num, u32 *den)
3676 {
3677         while (*num > 0xffffff || *den > 0xffffff) {
3678                 *num >>= 1;
3679                 *den >>= 1;
3680         }
3681 }
3682
3683 static void
3684 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3685                      int link_clock, struct fdi_m_n *m_n)
3686 {
3687         m_n->tu = 64; /* default size */
3688
3689         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3690         m_n->gmch_m = bits_per_pixel * pixel_clock;
3691         m_n->gmch_n = link_clock * nlanes * 8;
3692         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3693
3694         m_n->link_m = pixel_clock;
3695         m_n->link_n = link_clock;
3696         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3697 }
3698
3699 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3700 {
3701         if (i915_panel_use_ssc >= 0)
3702                 return i915_panel_use_ssc != 0;
3703         return dev_priv->lvds_use_ssc
3704                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3705 }
3706
3707 /**
3708  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3709  * @crtc: CRTC structure
3710  * @mode: requested mode
3711  *
3712  * A pipe may be connected to one or more outputs.  Based on the depth of the
3713  * attached framebuffer, choose a good color depth to use on the pipe.
3714  *
3715  * If possible, match the pipe depth to the fb depth.  In some cases, this
3716  * isn't ideal, because the connected output supports a lesser or restricted
3717  * set of depths.  Resolve that here:
3718  *    LVDS typically supports only 6bpc, so clamp down in that case
3719  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3720  *    Displays may support a restricted set as well, check EDID and clamp as
3721  *      appropriate.
3722  *    DP may want to dither down to 6bpc to fit larger modes
3723  *
3724  * RETURNS:
3725  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3726  * true if they don't match).
3727  */
3728 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3729                                          unsigned int *pipe_bpp,
3730                                          struct drm_display_mode *mode)
3731 {
3732         struct drm_device *dev = crtc->dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         struct drm_connector *connector;
3735         struct intel_encoder *intel_encoder;
3736         unsigned int display_bpc = UINT_MAX, bpc;
3737
3738         /* Walk the encoders & connectors on this crtc, get min bpc */
3739         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3740
3741                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3742                         unsigned int lvds_bpc;
3743
3744                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3745                             LVDS_A3_POWER_UP)
3746                                 lvds_bpc = 8;
3747                         else
3748                                 lvds_bpc = 6;
3749
3750                         if (lvds_bpc < display_bpc) {
3751                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3752                                 display_bpc = lvds_bpc;
3753                         }
3754                         continue;
3755                 }
3756
3757                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3758                         /* Use VBT settings if we have an eDP panel */
3759                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3760
3761                         if (edp_bpc < display_bpc) {
3762                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3763                                 display_bpc = edp_bpc;
3764                         }
3765                         continue;
3766                 }
3767
3768                 /* Not one of the known troublemakers, check the EDID */
3769                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3770                                     head) {
3771                         if (connector->encoder != &intel_encoder->base)
3772                                 continue;
3773
3774                         /* Don't use an invalid EDID bpc value */
3775                         if (connector->display_info.bpc &&
3776                             connector->display_info.bpc < display_bpc) {
3777                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3778                                 display_bpc = connector->display_info.bpc;
3779                         }
3780                 }
3781
3782                 /*
3783                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3784                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3785                  */
3786                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3787                         if (display_bpc > 8 && display_bpc < 12) {
3788                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3789                                 display_bpc = 12;
3790                         } else {
3791                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3792                                 display_bpc = 8;
3793                         }
3794                 }
3795         }
3796
3797         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3798                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3799                 display_bpc = 6;
3800         }
3801
3802         /*
3803          * We could just drive the pipe at the highest bpc all the time and
3804          * enable dithering as needed, but that costs bandwidth.  So choose
3805          * the minimum value that expresses the full color range of the fb but
3806          * also stays within the max display bpc discovered above.
3807          */
3808
3809         switch (crtc->fb->depth) {
3810         case 8:
3811                 bpc = 8; /* since we go through a colormap */
3812                 break;
3813         case 15:
3814         case 16:
3815                 bpc = 6; /* min is 18bpp */
3816                 break;
3817         case 24:
3818                 bpc = 8;
3819                 break;
3820         case 30:
3821                 bpc = 10;
3822                 break;
3823         case 48:
3824                 bpc = 12;
3825                 break;
3826         default:
3827                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3828                 bpc = min((unsigned int)8, display_bpc);
3829                 break;
3830         }
3831
3832         display_bpc = min(display_bpc, bpc);
3833
3834         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3835                       bpc, display_bpc);
3836
3837         *pipe_bpp = display_bpc * 3;
3838
3839         return display_bpc != bpc;
3840 }
3841
3842 static int vlv_get_refclk(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         int refclk = 27000; /* for DP & HDMI */
3847
3848         return 100000; /* only one validated so far */
3849
3850         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3851                 refclk = 96000;
3852         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3853                 if (intel_panel_use_ssc(dev_priv))
3854                         refclk = 100000;
3855                 else
3856                         refclk = 96000;
3857         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3858                 refclk = 100000;
3859         }
3860
3861         return refclk;
3862 }
3863
3864 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868         int refclk;
3869
3870         if (IS_VALLEYVIEW(dev)) {
3871                 refclk = vlv_get_refclk(crtc);
3872         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3873             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3874                 refclk = dev_priv->lvds_ssc_freq * 1000;
3875                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3876                               refclk / 1000);
3877         } else if (!IS_GEN2(dev)) {
3878                 refclk = 96000;
3879         } else {
3880                 refclk = 48000;
3881         }
3882
3883         return refclk;
3884 }
3885
3886 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3887                                       intel_clock_t *clock)
3888 {
3889         /* SDVO TV has fixed PLL values depend on its clock range,
3890            this mirrors vbios setting. */
3891         if (adjusted_mode->clock >= 100000
3892             && adjusted_mode->clock < 140500) {
3893                 clock->p1 = 2;
3894                 clock->p2 = 10;
3895                 clock->n = 3;
3896                 clock->m1 = 16;
3897                 clock->m2 = 8;
3898         } else if (adjusted_mode->clock >= 140500
3899                    && adjusted_mode->clock <= 200000) {
3900                 clock->p1 = 1;
3901                 clock->p2 = 10;
3902                 clock->n = 6;
3903                 clock->m1 = 12;
3904                 clock->m2 = 8;
3905         }
3906 }
3907
3908 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3909                                      intel_clock_t *clock,
3910                                      intel_clock_t *reduced_clock)
3911 {
3912         struct drm_device *dev = crtc->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915         int pipe = intel_crtc->pipe;
3916         u32 fp, fp2 = 0;
3917
3918         if (IS_PINEVIEW(dev)) {
3919                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3920                 if (reduced_clock)
3921                         fp2 = (1 << reduced_clock->n) << 16 |
3922                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3923         } else {
3924                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3925                 if (reduced_clock)
3926                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3927                                 reduced_clock->m2;
3928         }
3929
3930         I915_WRITE(FP0(pipe), fp);
3931
3932         intel_crtc->lowfreq_avail = false;
3933         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3934             reduced_clock && i915_powersave) {
3935                 I915_WRITE(FP1(pipe), fp2);
3936                 intel_crtc->lowfreq_avail = true;
3937         } else {
3938                 I915_WRITE(FP1(pipe), fp);
3939         }
3940 }
3941
3942 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3943                               struct drm_display_mode *adjusted_mode)
3944 {
3945         struct drm_device *dev = crtc->dev;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948         int pipe = intel_crtc->pipe;
3949         u32 temp;
3950
3951         temp = I915_READ(LVDS);
3952         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3953         if (pipe == 1) {
3954                 temp |= LVDS_PIPEB_SELECT;
3955         } else {
3956                 temp &= ~LVDS_PIPEB_SELECT;
3957         }
3958         /* set the corresponsding LVDS_BORDER bit */
3959         temp |= dev_priv->lvds_border_bits;
3960         /* Set the B0-B3 data pairs corresponding to whether we're going to
3961          * set the DPLLs for dual-channel mode or not.
3962          */
3963         if (clock->p2 == 7)
3964                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3965         else
3966                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3967
3968         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3969          * appropriately here, but we need to look more thoroughly into how
3970          * panels behave in the two modes.
3971          */
3972         /* set the dithering flag on LVDS as needed */
3973         if (INTEL_INFO(dev)->gen >= 4) {
3974                 if (dev_priv->lvds_dither)
3975                         temp |= LVDS_ENABLE_DITHER;
3976                 else
3977                         temp &= ~LVDS_ENABLE_DITHER;
3978         }
3979         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3980         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3981                 temp |= LVDS_HSYNC_POLARITY;
3982         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3983                 temp |= LVDS_VSYNC_POLARITY;
3984         I915_WRITE(LVDS, temp);
3985 }
3986
3987 static void vlv_update_pll(struct drm_crtc *crtc,
3988                            struct drm_display_mode *mode,
3989                            struct drm_display_mode *adjusted_mode,
3990                            intel_clock_t *clock, intel_clock_t *reduced_clock,
3991                            int refclk, int num_connectors)
3992 {
3993         struct drm_device *dev = crtc->dev;
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996         int pipe = intel_crtc->pipe;
3997         u32 dpll, mdiv, pdiv;
3998         u32 bestn, bestm1, bestm2, bestp1, bestp2;
3999         bool is_hdmi;
4000
4001         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4002
4003         bestn = clock->n;
4004         bestm1 = clock->m1;
4005         bestm2 = clock->m2;
4006         bestp1 = clock->p1;
4007         bestp2 = clock->p2;
4008
4009         /* Enable DPIO clock input */
4010         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4011                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4012         I915_WRITE(DPLL(pipe), dpll);
4013         POSTING_READ(DPLL(pipe));
4014
4015         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4016         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4017         mdiv |= ((bestn << DPIO_N_SHIFT));
4018         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4019         mdiv |= (1 << DPIO_K_SHIFT);
4020         mdiv |= DPIO_ENABLE_CALIBRATION;
4021         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4022
4023         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4024
4025         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4026                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4027                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4028         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4029
4030         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4031
4032         dpll |= DPLL_VCO_ENABLE;
4033         I915_WRITE(DPLL(pipe), dpll);
4034         POSTING_READ(DPLL(pipe));
4035         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4036                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4037
4038         if (is_hdmi) {
4039                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4040
4041                 if (temp > 1)
4042                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4043                 else
4044                         temp = 0;
4045
4046                 I915_WRITE(DPLL_MD(pipe), temp);
4047                 POSTING_READ(DPLL_MD(pipe));
4048         }
4049
4050         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4051 }
4052
4053 static void i9xx_update_pll(struct drm_crtc *crtc,
4054                             struct drm_display_mode *mode,
4055                             struct drm_display_mode *adjusted_mode,
4056                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4057                             int num_connectors)
4058 {
4059         struct drm_device *dev = crtc->dev;
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4062         int pipe = intel_crtc->pipe;
4063         u32 dpll;
4064         bool is_sdvo;
4065
4066         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4067                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4068
4069         dpll = DPLL_VGA_MODE_DIS;
4070
4071         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4072                 dpll |= DPLLB_MODE_LVDS;
4073         else
4074                 dpll |= DPLLB_MODE_DAC_SERIAL;
4075         if (is_sdvo) {
4076                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4077                 if (pixel_multiplier > 1) {
4078                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4079                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4080                 }
4081                 dpll |= DPLL_DVO_HIGH_SPEED;
4082         }
4083         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4084                 dpll |= DPLL_DVO_HIGH_SPEED;
4085
4086         /* compute bitmask from p1 value */
4087         if (IS_PINEVIEW(dev))
4088                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4089         else {
4090                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4091                 if (IS_G4X(dev) && reduced_clock)
4092                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4093         }
4094         switch (clock->p2) {
4095         case 5:
4096                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4097                 break;
4098         case 7:
4099                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4100                 break;
4101         case 10:
4102                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4103                 break;
4104         case 14:
4105                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4106                 break;
4107         }
4108         if (INTEL_INFO(dev)->gen >= 4)
4109                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4110
4111         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4112                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4113         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4114                 /* XXX: just matching BIOS for now */
4115                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4116                 dpll |= 3;
4117         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4118                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4119                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4120         else
4121                 dpll |= PLL_REF_INPUT_DREFCLK;
4122
4123         dpll |= DPLL_VCO_ENABLE;
4124         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4125         POSTING_READ(DPLL(pipe));
4126         udelay(150);
4127
4128         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4129          * This is an exception to the general rule that mode_set doesn't turn
4130          * things on.
4131          */
4132         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4133                 intel_update_lvds(crtc, clock, adjusted_mode);
4134
4135         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4136                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4137
4138         I915_WRITE(DPLL(pipe), dpll);
4139
4140         /* Wait for the clocks to stabilize. */
4141         POSTING_READ(DPLL(pipe));
4142         udelay(150);
4143
4144         if (INTEL_INFO(dev)->gen >= 4) {
4145                 u32 temp = 0;
4146                 if (is_sdvo) {
4147                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4148                         if (temp > 1)
4149                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4150                         else
4151                                 temp = 0;
4152                 }
4153                 I915_WRITE(DPLL_MD(pipe), temp);
4154         } else {
4155                 /* The pixel multiplier can only be updated once the
4156                  * DPLL is enabled and the clocks are stable.
4157                  *
4158                  * So write it again.
4159                  */
4160                 I915_WRITE(DPLL(pipe), dpll);
4161         }
4162 }
4163
4164 static void i8xx_update_pll(struct drm_crtc *crtc,
4165                             struct drm_display_mode *adjusted_mode,
4166                             intel_clock_t *clock,
4167                             int num_connectors)
4168 {
4169         struct drm_device *dev = crtc->dev;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172         int pipe = intel_crtc->pipe;
4173         u32 dpll;
4174
4175         dpll = DPLL_VGA_MODE_DIS;
4176
4177         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4178                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4179         } else {
4180                 if (clock->p1 == 2)
4181                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4182                 else
4183                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4184                 if (clock->p2 == 4)
4185                         dpll |= PLL_P2_DIVIDE_BY_4;
4186         }
4187
4188         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4189                 /* XXX: just matching BIOS for now */
4190                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4191                 dpll |= 3;
4192         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4193                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4194                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4195         else
4196                 dpll |= PLL_REF_INPUT_DREFCLK;
4197
4198         dpll |= DPLL_VCO_ENABLE;
4199         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4200         POSTING_READ(DPLL(pipe));
4201         udelay(150);
4202
4203         I915_WRITE(DPLL(pipe), dpll);
4204
4205         /* Wait for the clocks to stabilize. */
4206         POSTING_READ(DPLL(pipe));
4207         udelay(150);
4208
4209         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4210          * This is an exception to the general rule that mode_set doesn't turn
4211          * things on.
4212          */
4213         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4214                 intel_update_lvds(crtc, clock, adjusted_mode);
4215
4216         /* The pixel multiplier can only be updated once the
4217          * DPLL is enabled and the clocks are stable.
4218          *
4219          * So write it again.
4220          */
4221         I915_WRITE(DPLL(pipe), dpll);
4222 }
4223
4224 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4225                               struct drm_display_mode *mode,
4226                               struct drm_display_mode *adjusted_mode,
4227                               int x, int y,
4228                               struct drm_framebuffer *old_fb)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         int plane = intel_crtc->plane;
4235         int refclk, num_connectors = 0;
4236         intel_clock_t clock, reduced_clock;
4237         u32 dspcntr, pipeconf, vsyncshift;
4238         bool ok, has_reduced_clock = false, is_sdvo = false;
4239         bool is_lvds = false, is_tv = false, is_dp = false;
4240         struct intel_encoder *encoder;
4241         const intel_limit_t *limit;
4242         int ret;
4243
4244         for_each_encoder_on_crtc(dev, crtc, encoder) {
4245                 switch (encoder->type) {
4246                 case INTEL_OUTPUT_LVDS:
4247                         is_lvds = true;
4248                         break;
4249                 case INTEL_OUTPUT_SDVO:
4250                 case INTEL_OUTPUT_HDMI:
4251                         is_sdvo = true;
4252                         if (encoder->needs_tv_clock)
4253                                 is_tv = true;
4254                         break;
4255                 case INTEL_OUTPUT_TVOUT:
4256                         is_tv = true;
4257                         break;
4258                 case INTEL_OUTPUT_DISPLAYPORT:
4259                         is_dp = true;
4260                         break;
4261                 }
4262
4263                 num_connectors++;
4264         }
4265
4266         refclk = i9xx_get_refclk(crtc, num_connectors);
4267
4268         /*
4269          * Returns a set of divisors for the desired target clock with the given
4270          * refclk, or FALSE.  The returned values represent the clock equation:
4271          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4272          */
4273         limit = intel_limit(crtc, refclk);
4274         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4275                              &clock);
4276         if (!ok) {
4277                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4278                 return -EINVAL;
4279         }
4280
4281         /* Ensure that the cursor is valid for the new mode before changing... */
4282         intel_crtc_update_cursor(crtc, true);
4283
4284         if (is_lvds && dev_priv->lvds_downclock_avail) {
4285                 /*
4286                  * Ensure we match the reduced clock's P to the target clock.
4287                  * If the clocks don't match, we can't switch the display clock
4288                  * by using the FP0/FP1. In such case we will disable the LVDS
4289                  * downclock feature.
4290                 */
4291                 has_reduced_clock = limit->find_pll(limit, crtc,
4292                                                     dev_priv->lvds_downclock,
4293                                                     refclk,
4294                                                     &clock,
4295                                                     &reduced_clock);
4296         }
4297
4298         if (is_sdvo && is_tv)
4299                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4300
4301         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4302                                  &reduced_clock : NULL);
4303
4304         if (IS_GEN2(dev))
4305                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4306         else if (IS_VALLEYVIEW(dev))
4307                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4308                                refclk, num_connectors);
4309         else
4310                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4311                                 has_reduced_clock ? &reduced_clock : NULL,
4312                                 num_connectors);
4313
4314         /* setup pipeconf */
4315         pipeconf = I915_READ(PIPECONF(pipe));
4316
4317         /* Set up the display plane register */
4318         dspcntr = DISPPLANE_GAMMA_ENABLE;
4319
4320         if (pipe == 0)
4321                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4322         else
4323                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4324
4325         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4326                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4327                  * core speed.
4328                  *
4329                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4330                  * pipe == 0 check?
4331                  */
4332                 if (mode->clock >
4333                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4334                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4335                 else
4336                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4337         }
4338
4339         /* default to 8bpc */
4340         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4341         if (is_dp) {
4342                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4343                         pipeconf |= PIPECONF_BPP_6 |
4344                                     PIPECONF_DITHER_EN |
4345                                     PIPECONF_DITHER_TYPE_SP;
4346                 }
4347         }
4348
4349         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4350         drm_mode_debug_printmodeline(mode);
4351
4352         if (HAS_PIPE_CXSR(dev)) {
4353                 if (intel_crtc->lowfreq_avail) {
4354                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4355                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4356                 } else {
4357                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4358                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4359                 }
4360         }
4361
4362         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4363         if (!IS_GEN2(dev) &&
4364             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4365                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4366                 /* the chip adds 2 halflines automatically */
4367                 adjusted_mode->crtc_vtotal -= 1;
4368                 adjusted_mode->crtc_vblank_end -= 1;
4369                 vsyncshift = adjusted_mode->crtc_hsync_start
4370                              - adjusted_mode->crtc_htotal/2;
4371         } else {
4372                 pipeconf |= PIPECONF_PROGRESSIVE;
4373                 vsyncshift = 0;
4374         }
4375
4376         if (!IS_GEN3(dev))
4377                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4378
4379         I915_WRITE(HTOTAL(pipe),
4380                    (adjusted_mode->crtc_hdisplay - 1) |
4381                    ((adjusted_mode->crtc_htotal - 1) << 16));
4382         I915_WRITE(HBLANK(pipe),
4383                    (adjusted_mode->crtc_hblank_start - 1) |
4384                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4385         I915_WRITE(HSYNC(pipe),
4386                    (adjusted_mode->crtc_hsync_start - 1) |
4387                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4388
4389         I915_WRITE(VTOTAL(pipe),
4390                    (adjusted_mode->crtc_vdisplay - 1) |
4391                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4392         I915_WRITE(VBLANK(pipe),
4393                    (adjusted_mode->crtc_vblank_start - 1) |
4394                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4395         I915_WRITE(VSYNC(pipe),
4396                    (adjusted_mode->crtc_vsync_start - 1) |
4397                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4398
4399         /* pipesrc and dspsize control the size that is scaled from,
4400          * which should always be the user's requested size.
4401          */
4402         I915_WRITE(DSPSIZE(plane),
4403                    ((mode->vdisplay - 1) << 16) |
4404                    (mode->hdisplay - 1));
4405         I915_WRITE(DSPPOS(plane), 0);
4406         I915_WRITE(PIPESRC(pipe),
4407                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4408
4409         I915_WRITE(PIPECONF(pipe), pipeconf);
4410         POSTING_READ(PIPECONF(pipe));
4411         intel_enable_pipe(dev_priv, pipe, false);
4412
4413         intel_wait_for_vblank(dev, pipe);
4414
4415         I915_WRITE(DSPCNTR(plane), dspcntr);
4416         POSTING_READ(DSPCNTR(plane));
4417
4418         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4419
4420         intel_update_watermarks(dev);
4421
4422         return ret;
4423 }
4424
4425 /*
4426  * Initialize reference clocks when the driver loads
4427  */
4428 void ironlake_init_pch_refclk(struct drm_device *dev)
4429 {
4430         struct drm_i915_private *dev_priv = dev->dev_private;
4431         struct drm_mode_config *mode_config = &dev->mode_config;
4432         struct intel_encoder *encoder;
4433         u32 temp;
4434         bool has_lvds = false;
4435         bool has_cpu_edp = false;
4436         bool has_pch_edp = false;
4437         bool has_panel = false;
4438         bool has_ck505 = false;
4439         bool can_ssc = false;
4440
4441         /* We need to take the global config into account */
4442         list_for_each_entry(encoder, &mode_config->encoder_list,
4443                             base.head) {
4444                 switch (encoder->type) {
4445                 case INTEL_OUTPUT_LVDS:
4446                         has_panel = true;
4447                         has_lvds = true;
4448                         break;
4449                 case INTEL_OUTPUT_EDP:
4450                         has_panel = true;
4451                         if (intel_encoder_is_pch_edp(&encoder->base))
4452                                 has_pch_edp = true;
4453                         else
4454                                 has_cpu_edp = true;
4455                         break;
4456                 }
4457         }
4458
4459         if (HAS_PCH_IBX(dev)) {
4460                 has_ck505 = dev_priv->display_clock_mode;
4461                 can_ssc = has_ck505;
4462         } else {
4463                 has_ck505 = false;
4464                 can_ssc = true;
4465         }
4466
4467         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4468                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4469                       has_ck505);
4470
4471         /* Ironlake: try to setup display ref clock before DPLL
4472          * enabling. This is only under driver's control after
4473          * PCH B stepping, previous chipset stepping should be
4474          * ignoring this setting.
4475          */
4476         temp = I915_READ(PCH_DREF_CONTROL);
4477         /* Always enable nonspread source */
4478         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4479
4480         if (has_ck505)
4481                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4482         else
4483                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4484
4485         if (has_panel) {
4486                 temp &= ~DREF_SSC_SOURCE_MASK;
4487                 temp |= DREF_SSC_SOURCE_ENABLE;
4488
4489                 /* SSC must be turned on before enabling the CPU output  */
4490                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4491                         DRM_DEBUG_KMS("Using SSC on panel\n");
4492                         temp |= DREF_SSC1_ENABLE;
4493                 } else
4494                         temp &= ~DREF_SSC1_ENABLE;
4495
4496                 /* Get SSC going before enabling the outputs */
4497                 I915_WRITE(PCH_DREF_CONTROL, temp);
4498                 POSTING_READ(PCH_DREF_CONTROL);
4499                 udelay(200);
4500
4501                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4502
4503                 /* Enable CPU source on CPU attached eDP */
4504                 if (has_cpu_edp) {
4505                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4506                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4507                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4508                         }
4509                         else
4510                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4511                 } else
4512                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4513
4514                 I915_WRITE(PCH_DREF_CONTROL, temp);
4515                 POSTING_READ(PCH_DREF_CONTROL);
4516                 udelay(200);
4517         } else {
4518                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4519
4520                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4521
4522                 /* Turn off CPU output */
4523                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4524
4525                 I915_WRITE(PCH_DREF_CONTROL, temp);
4526                 POSTING_READ(PCH_DREF_CONTROL);
4527                 udelay(200);
4528
4529                 /* Turn off the SSC source */
4530                 temp &= ~DREF_SSC_SOURCE_MASK;
4531                 temp |= DREF_SSC_SOURCE_DISABLE;
4532
4533                 /* Turn off SSC1 */
4534                 temp &= ~ DREF_SSC1_ENABLE;
4535
4536                 I915_WRITE(PCH_DREF_CONTROL, temp);
4537                 POSTING_READ(PCH_DREF_CONTROL);
4538                 udelay(200);
4539         }
4540 }
4541
4542 static int ironlake_get_refclk(struct drm_crtc *crtc)
4543 {
4544         struct drm_device *dev = crtc->dev;
4545         struct drm_i915_private *dev_priv = dev->dev_private;
4546         struct intel_encoder *encoder;
4547         struct intel_encoder *edp_encoder = NULL;
4548         int num_connectors = 0;
4549         bool is_lvds = false;
4550
4551         for_each_encoder_on_crtc(dev, crtc, encoder) {
4552                 switch (encoder->type) {
4553                 case INTEL_OUTPUT_LVDS:
4554                         is_lvds = true;
4555                         break;
4556                 case INTEL_OUTPUT_EDP:
4557                         edp_encoder = encoder;
4558                         break;
4559                 }
4560                 num_connectors++;
4561         }
4562
4563         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4564                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4565                               dev_priv->lvds_ssc_freq);
4566                 return dev_priv->lvds_ssc_freq * 1000;
4567         }
4568
4569         return 120000;
4570 }
4571
4572 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4573                                   struct drm_display_mode *mode,
4574                                   struct drm_display_mode *adjusted_mode,
4575                                   int x, int y,
4576                                   struct drm_framebuffer *old_fb)
4577 {
4578         struct drm_device *dev = crtc->dev;
4579         struct drm_i915_private *dev_priv = dev->dev_private;
4580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581         int pipe = intel_crtc->pipe;
4582         int plane = intel_crtc->plane;
4583         int refclk, num_connectors = 0;
4584         intel_clock_t clock, reduced_clock;
4585         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4586         bool ok, has_reduced_clock = false, is_sdvo = false;
4587         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4588         struct intel_encoder *encoder, *edp_encoder = NULL;
4589         const intel_limit_t *limit;
4590         int ret;
4591         struct fdi_m_n m_n = {0};
4592         u32 temp;
4593         int target_clock, pixel_multiplier, lane, link_bw, factor;
4594         unsigned int pipe_bpp;
4595         bool dither;
4596         bool is_cpu_edp = false, is_pch_edp = false;
4597
4598         for_each_encoder_on_crtc(dev, crtc, encoder) {
4599                 switch (encoder->type) {
4600                 case INTEL_OUTPUT_LVDS:
4601                         is_lvds = true;
4602                         break;
4603                 case INTEL_OUTPUT_SDVO:
4604                 case INTEL_OUTPUT_HDMI:
4605                         is_sdvo = true;
4606                         if (encoder->needs_tv_clock)
4607                                 is_tv = true;
4608                         break;
4609                 case INTEL_OUTPUT_TVOUT:
4610                         is_tv = true;
4611                         break;
4612                 case INTEL_OUTPUT_ANALOG:
4613                         is_crt = true;
4614                         break;
4615                 case INTEL_OUTPUT_DISPLAYPORT:
4616                         is_dp = true;
4617                         break;
4618                 case INTEL_OUTPUT_EDP:
4619                         is_dp = true;
4620                         if (intel_encoder_is_pch_edp(&encoder->base))
4621                                 is_pch_edp = true;
4622                         else
4623                                 is_cpu_edp = true;
4624                         edp_encoder = encoder;
4625                         break;
4626                 }
4627
4628                 num_connectors++;
4629         }
4630
4631         refclk = ironlake_get_refclk(crtc);
4632
4633         /*
4634          * Returns a set of divisors for the desired target clock with the given
4635          * refclk, or FALSE.  The returned values represent the clock equation:
4636          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4637          */
4638         limit = intel_limit(crtc, refclk);
4639         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4640                              &clock);
4641         if (!ok) {
4642                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4643                 return -EINVAL;
4644         }
4645
4646         /* Ensure that the cursor is valid for the new mode before changing... */
4647         intel_crtc_update_cursor(crtc, true);
4648
4649         if (is_lvds && dev_priv->lvds_downclock_avail) {
4650                 /*
4651                  * Ensure we match the reduced clock's P to the target clock.
4652                  * If the clocks don't match, we can't switch the display clock
4653                  * by using the FP0/FP1. In such case we will disable the LVDS
4654                  * downclock feature.
4655                 */
4656                 has_reduced_clock = limit->find_pll(limit, crtc,
4657                                                     dev_priv->lvds_downclock,
4658                                                     refclk,
4659                                                     &clock,
4660                                                     &reduced_clock);
4661         }
4662
4663         if (is_sdvo && is_tv)
4664                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4665
4666
4667         /* FDI link */
4668         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4669         lane = 0;
4670         /* CPU eDP doesn't require FDI link, so just set DP M/N
4671            according to current link config */
4672         if (is_cpu_edp) {
4673                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4674         } else {
4675                 /* FDI is a binary signal running at ~2.7GHz, encoding
4676                  * each output octet as 10 bits. The actual frequency
4677                  * is stored as a divider into a 100MHz clock, and the
4678                  * mode pixel clock is stored in units of 1KHz.
4679                  * Hence the bw of each lane in terms of the mode signal
4680                  * is:
4681                  */
4682                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4683         }
4684
4685         /* [e]DP over FDI requires target mode clock instead of link clock. */
4686         if (edp_encoder)
4687                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4688         else if (is_dp)
4689                 target_clock = mode->clock;
4690         else
4691                 target_clock = adjusted_mode->clock;
4692
4693         /* determine panel color depth */
4694         temp = I915_READ(PIPECONF(pipe));
4695         temp &= ~PIPE_BPC_MASK;
4696         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4697         switch (pipe_bpp) {
4698         case 18:
4699                 temp |= PIPE_6BPC;
4700                 break;
4701         case 24:
4702                 temp |= PIPE_8BPC;
4703                 break;
4704         case 30:
4705                 temp |= PIPE_10BPC;
4706                 break;
4707         case 36:
4708                 temp |= PIPE_12BPC;
4709                 break;
4710         default:
4711                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4712                         pipe_bpp);
4713                 temp |= PIPE_8BPC;
4714                 pipe_bpp = 24;
4715                 break;
4716         }
4717
4718         intel_crtc->bpp = pipe_bpp;
4719         I915_WRITE(PIPECONF(pipe), temp);
4720
4721         if (!lane) {
4722                 /*
4723                  * Account for spread spectrum to avoid
4724                  * oversubscribing the link. Max center spread
4725                  * is 2.5%; use 5% for safety's sake.
4726                  */
4727                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4728                 lane = bps / (link_bw * 8) + 1;
4729         }
4730
4731         intel_crtc->fdi_lanes = lane;
4732
4733         if (pixel_multiplier > 1)
4734                 link_bw *= pixel_multiplier;
4735         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4736                              &m_n);
4737
4738         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4739         if (has_reduced_clock)
4740                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4741                         reduced_clock.m2;
4742
4743         /* Enable autotuning of the PLL clock (if permissible) */
4744         factor = 21;
4745         if (is_lvds) {
4746                 if ((intel_panel_use_ssc(dev_priv) &&
4747                      dev_priv->lvds_ssc_freq == 100) ||
4748                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4749                         factor = 25;
4750         } else if (is_sdvo && is_tv)
4751                 factor = 20;
4752
4753         if (clock.m < factor * clock.n)
4754                 fp |= FP_CB_TUNE;
4755
4756         dpll = 0;
4757
4758         if (is_lvds)
4759                 dpll |= DPLLB_MODE_LVDS;
4760         else
4761                 dpll |= DPLLB_MODE_DAC_SERIAL;
4762         if (is_sdvo) {
4763                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4764                 if (pixel_multiplier > 1) {
4765                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4766                 }
4767                 dpll |= DPLL_DVO_HIGH_SPEED;
4768         }
4769         if (is_dp && !is_cpu_edp)
4770                 dpll |= DPLL_DVO_HIGH_SPEED;
4771
4772         /* compute bitmask from p1 value */
4773         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4774         /* also FPA1 */
4775         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4776
4777         switch (clock.p2) {
4778         case 5:
4779                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4780                 break;
4781         case 7:
4782                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4783                 break;
4784         case 10:
4785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4786                 break;
4787         case 14:
4788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4789                 break;
4790         }
4791
4792         if (is_sdvo && is_tv)
4793                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4794         else if (is_tv)
4795                 /* XXX: just matching BIOS for now */
4796                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4797                 dpll |= 3;
4798         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4799                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4800         else
4801                 dpll |= PLL_REF_INPUT_DREFCLK;
4802
4803         /* setup pipeconf */
4804         pipeconf = I915_READ(PIPECONF(pipe));
4805
4806         /* Set up the display plane register */
4807         dspcntr = DISPPLANE_GAMMA_ENABLE;
4808
4809         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4810         drm_mode_debug_printmodeline(mode);
4811
4812         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4813          * pre-Haswell/LPT generation */
4814         if (HAS_PCH_LPT(dev)) {
4815                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4816                                 pipe);
4817         } else if (!is_cpu_edp) {
4818                 struct intel_pch_pll *pll;
4819
4820                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4821                 if (pll == NULL) {
4822                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4823                                          pipe);
4824                         return -EINVAL;
4825                 }
4826         } else
4827                 intel_put_pch_pll(intel_crtc);
4828
4829         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4830          * This is an exception to the general rule that mode_set doesn't turn
4831          * things on.
4832          */
4833         if (is_lvds) {
4834                 temp = I915_READ(PCH_LVDS);
4835                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4836                 if (HAS_PCH_CPT(dev)) {
4837                         temp &= ~PORT_TRANS_SEL_MASK;
4838                         temp |= PORT_TRANS_SEL_CPT(pipe);
4839                 } else {
4840                         if (pipe == 1)
4841                                 temp |= LVDS_PIPEB_SELECT;
4842                         else
4843                                 temp &= ~LVDS_PIPEB_SELECT;
4844                 }
4845
4846                 /* set the corresponsding LVDS_BORDER bit */
4847                 temp |= dev_priv->lvds_border_bits;
4848                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4849                  * set the DPLLs for dual-channel mode or not.
4850                  */
4851                 if (clock.p2 == 7)
4852                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4853                 else
4854                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4855
4856                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4857                  * appropriately here, but we need to look more thoroughly into how
4858                  * panels behave in the two modes.
4859                  */
4860                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4861                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4862                         temp |= LVDS_HSYNC_POLARITY;
4863                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4864                         temp |= LVDS_VSYNC_POLARITY;
4865                 I915_WRITE(PCH_LVDS, temp);
4866         }
4867
4868         pipeconf &= ~PIPECONF_DITHER_EN;
4869         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4870         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4871                 pipeconf |= PIPECONF_DITHER_EN;
4872                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4873         }
4874         if (is_dp && !is_cpu_edp) {
4875                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4876         } else {
4877                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4878                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4879                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4880                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4881                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4882         }
4883
4884         if (intel_crtc->pch_pll) {
4885                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4886
4887                 /* Wait for the clocks to stabilize. */
4888                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4889                 udelay(150);
4890
4891                 /* The pixel multiplier can only be updated once the
4892                  * DPLL is enabled and the clocks are stable.
4893                  *
4894                  * So write it again.
4895                  */
4896                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4897         }
4898
4899         intel_crtc->lowfreq_avail = false;
4900         if (intel_crtc->pch_pll) {
4901                 if (is_lvds && has_reduced_clock && i915_powersave) {
4902                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4903                         intel_crtc->lowfreq_avail = true;
4904                 } else {
4905                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4906                 }
4907         }
4908
4909         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4910         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4911                 pipeconf |= PIPECONF_INTERLACED_ILK;
4912                 /* the chip adds 2 halflines automatically */
4913                 adjusted_mode->crtc_vtotal -= 1;
4914                 adjusted_mode->crtc_vblank_end -= 1;
4915                 I915_WRITE(VSYNCSHIFT(pipe),
4916                            adjusted_mode->crtc_hsync_start
4917                            - adjusted_mode->crtc_htotal/2);
4918         } else {
4919                 pipeconf |= PIPECONF_PROGRESSIVE;
4920                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4921         }
4922
4923         I915_WRITE(HTOTAL(pipe),
4924                    (adjusted_mode->crtc_hdisplay - 1) |
4925                    ((adjusted_mode->crtc_htotal - 1) << 16));
4926         I915_WRITE(HBLANK(pipe),
4927                    (adjusted_mode->crtc_hblank_start - 1) |
4928                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4929         I915_WRITE(HSYNC(pipe),
4930                    (adjusted_mode->crtc_hsync_start - 1) |
4931                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4932
4933         I915_WRITE(VTOTAL(pipe),
4934                    (adjusted_mode->crtc_vdisplay - 1) |
4935                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4936         I915_WRITE(VBLANK(pipe),
4937                    (adjusted_mode->crtc_vblank_start - 1) |
4938                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4939         I915_WRITE(VSYNC(pipe),
4940                    (adjusted_mode->crtc_vsync_start - 1) |
4941                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4942
4943         /* pipesrc controls the size that is scaled from, which should
4944          * always be the user's requested size.
4945          */
4946         I915_WRITE(PIPESRC(pipe),
4947                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4948
4949         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4950         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4951         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4952         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4953
4954         if (is_cpu_edp)
4955                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4956
4957         I915_WRITE(PIPECONF(pipe), pipeconf);
4958         POSTING_READ(PIPECONF(pipe));
4959
4960         intel_wait_for_vblank(dev, pipe);
4961
4962         I915_WRITE(DSPCNTR(plane), dspcntr);
4963         POSTING_READ(DSPCNTR(plane));
4964
4965         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4966
4967         intel_update_watermarks(dev);
4968
4969         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4970
4971         return ret;
4972 }
4973
4974 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4975                                struct drm_display_mode *mode,
4976                                struct drm_display_mode *adjusted_mode,
4977                                int x, int y,
4978                                struct drm_framebuffer *old_fb)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         int pipe = intel_crtc->pipe;
4984         int ret;
4985
4986         drm_vblank_pre_modeset(dev, pipe);
4987
4988         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4989                                               x, y, old_fb);
4990         drm_vblank_post_modeset(dev, pipe);
4991
4992         if (ret)
4993                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4994         else
4995                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4996
4997         return ret;
4998 }
4999
5000 static bool intel_eld_uptodate(struct drm_connector *connector,
5001                                int reg_eldv, uint32_t bits_eldv,
5002                                int reg_elda, uint32_t bits_elda,
5003                                int reg_edid)
5004 {
5005         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5006         uint8_t *eld = connector->eld;
5007         uint32_t i;
5008
5009         i = I915_READ(reg_eldv);
5010         i &= bits_eldv;
5011
5012         if (!eld[0])
5013                 return !i;
5014
5015         if (!i)
5016                 return false;
5017
5018         i = I915_READ(reg_elda);
5019         i &= ~bits_elda;
5020         I915_WRITE(reg_elda, i);
5021
5022         for (i = 0; i < eld[2]; i++)
5023                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5024                         return false;
5025
5026         return true;
5027 }
5028
5029 static void g4x_write_eld(struct drm_connector *connector,
5030                           struct drm_crtc *crtc)
5031 {
5032         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5033         uint8_t *eld = connector->eld;
5034         uint32_t eldv;
5035         uint32_t len;
5036         uint32_t i;
5037
5038         i = I915_READ(G4X_AUD_VID_DID);
5039
5040         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5041                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5042         else
5043                 eldv = G4X_ELDV_DEVCTG;
5044
5045         if (intel_eld_uptodate(connector,
5046                                G4X_AUD_CNTL_ST, eldv,
5047                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5048                                G4X_HDMIW_HDMIEDID))
5049                 return;
5050
5051         i = I915_READ(G4X_AUD_CNTL_ST);
5052         i &= ~(eldv | G4X_ELD_ADDR);
5053         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5054         I915_WRITE(G4X_AUD_CNTL_ST, i);
5055
5056         if (!eld[0])
5057                 return;
5058
5059         len = min_t(uint8_t, eld[2], len);
5060         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5061         for (i = 0; i < len; i++)
5062                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5063
5064         i = I915_READ(G4X_AUD_CNTL_ST);
5065         i |= eldv;
5066         I915_WRITE(G4X_AUD_CNTL_ST, i);
5067 }
5068
5069 static void ironlake_write_eld(struct drm_connector *connector,
5070                                      struct drm_crtc *crtc)
5071 {
5072         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073         uint8_t *eld = connector->eld;
5074         uint32_t eldv;
5075         uint32_t i;
5076         int len;
5077         int hdmiw_hdmiedid;
5078         int aud_config;
5079         int aud_cntl_st;
5080         int aud_cntrl_st2;
5081
5082         if (HAS_PCH_IBX(connector->dev)) {
5083                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
5084                 aud_config = IBX_AUD_CONFIG_A;
5085                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5086                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5087         } else {
5088                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
5089                 aud_config = CPT_AUD_CONFIG_A;
5090                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5091                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5092         }
5093
5094         i = to_intel_crtc(crtc)->pipe;
5095         hdmiw_hdmiedid += i * 0x100;
5096         aud_cntl_st += i * 0x100;
5097         aud_config += i * 0x100;
5098
5099         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5100
5101         i = I915_READ(aud_cntl_st);
5102         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5103         if (!i) {
5104                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5105                 /* operate blindly on all ports */
5106                 eldv = IBX_ELD_VALIDB;
5107                 eldv |= IBX_ELD_VALIDB << 4;
5108                 eldv |= IBX_ELD_VALIDB << 8;
5109         } else {
5110                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5111                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5112         }
5113
5114         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5115                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5116                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5117                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5118         } else
5119                 I915_WRITE(aud_config, 0);
5120
5121         if (intel_eld_uptodate(connector,
5122                                aud_cntrl_st2, eldv,
5123                                aud_cntl_st, IBX_ELD_ADDRESS,
5124                                hdmiw_hdmiedid))
5125                 return;
5126
5127         i = I915_READ(aud_cntrl_st2);
5128         i &= ~eldv;
5129         I915_WRITE(aud_cntrl_st2, i);
5130
5131         if (!eld[0])
5132                 return;
5133
5134         i = I915_READ(aud_cntl_st);
5135         i &= ~IBX_ELD_ADDRESS;
5136         I915_WRITE(aud_cntl_st, i);
5137
5138         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5139         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5140         for (i = 0; i < len; i++)
5141                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5142
5143         i = I915_READ(aud_cntrl_st2);
5144         i |= eldv;
5145         I915_WRITE(aud_cntrl_st2, i);
5146 }
5147
5148 void intel_write_eld(struct drm_encoder *encoder,
5149                      struct drm_display_mode *mode)
5150 {
5151         struct drm_crtc *crtc = encoder->crtc;
5152         struct drm_connector *connector;
5153         struct drm_device *dev = encoder->dev;
5154         struct drm_i915_private *dev_priv = dev->dev_private;
5155
5156         connector = drm_select_eld(encoder, mode);
5157         if (!connector)
5158                 return;
5159
5160         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5161                          connector->base.id,
5162                          drm_get_connector_name(connector),
5163                          connector->encoder->base.id,
5164                          drm_get_encoder_name(connector->encoder));
5165
5166         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5167
5168         if (dev_priv->display.write_eld)
5169                 dev_priv->display.write_eld(connector, crtc);
5170 }
5171
5172 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5173 void intel_crtc_load_lut(struct drm_crtc *crtc)
5174 {
5175         struct drm_device *dev = crtc->dev;
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5178         int palreg = PALETTE(intel_crtc->pipe);
5179         int i;
5180
5181         /* The clocks have to be on to load the palette. */
5182         if (!crtc->enabled || !intel_crtc->active)
5183                 return;
5184
5185         /* use legacy palette for Ironlake */
5186         if (HAS_PCH_SPLIT(dev))
5187                 palreg = LGC_PALETTE(intel_crtc->pipe);
5188
5189         for (i = 0; i < 256; i++) {
5190                 I915_WRITE(palreg + 4 * i,
5191                            (intel_crtc->lut_r[i] << 16) |
5192                            (intel_crtc->lut_g[i] << 8) |
5193                            intel_crtc->lut_b[i]);
5194         }
5195 }
5196
5197 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5198 {
5199         struct drm_device *dev = crtc->dev;
5200         struct drm_i915_private *dev_priv = dev->dev_private;
5201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5202         bool visible = base != 0;
5203         u32 cntl;
5204
5205         if (intel_crtc->cursor_visible == visible)
5206                 return;
5207
5208         cntl = I915_READ(_CURACNTR);
5209         if (visible) {
5210                 /* On these chipsets we can only modify the base whilst
5211                  * the cursor is disabled.
5212                  */
5213                 I915_WRITE(_CURABASE, base);
5214
5215                 cntl &= ~(CURSOR_FORMAT_MASK);
5216                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5217                 cntl |= CURSOR_ENABLE |
5218                         CURSOR_GAMMA_ENABLE |
5219                         CURSOR_FORMAT_ARGB;
5220         } else
5221                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5222         I915_WRITE(_CURACNTR, cntl);
5223
5224         intel_crtc->cursor_visible = visible;
5225 }
5226
5227 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5228 {
5229         struct drm_device *dev = crtc->dev;
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232         int pipe = intel_crtc->pipe;
5233         bool visible = base != 0;
5234
5235         if (intel_crtc->cursor_visible != visible) {
5236                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5237                 if (base) {
5238                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5239                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5240                         cntl |= pipe << 28; /* Connect to correct pipe */
5241                 } else {
5242                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5243                         cntl |= CURSOR_MODE_DISABLE;
5244                 }
5245                 I915_WRITE(CURCNTR(pipe), cntl);
5246
5247                 intel_crtc->cursor_visible = visible;
5248         }
5249         /* and commit changes on next vblank */
5250         I915_WRITE(CURBASE(pipe), base);
5251 }
5252
5253 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5254 {
5255         struct drm_device *dev = crtc->dev;
5256         struct drm_i915_private *dev_priv = dev->dev_private;
5257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258         int pipe = intel_crtc->pipe;
5259         bool visible = base != 0;
5260
5261         if (intel_crtc->cursor_visible != visible) {
5262                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5263                 if (base) {
5264                         cntl &= ~CURSOR_MODE;
5265                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5266                 } else {
5267                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5268                         cntl |= CURSOR_MODE_DISABLE;
5269                 }
5270                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5271
5272                 intel_crtc->cursor_visible = visible;
5273         }
5274         /* and commit changes on next vblank */
5275         I915_WRITE(CURBASE_IVB(pipe), base);
5276 }
5277
5278 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5279 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5280                                      bool on)
5281 {
5282         struct drm_device *dev = crtc->dev;
5283         struct drm_i915_private *dev_priv = dev->dev_private;
5284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5285         int pipe = intel_crtc->pipe;
5286         int x = intel_crtc->cursor_x;
5287         int y = intel_crtc->cursor_y;
5288         u32 base, pos;
5289         bool visible;
5290
5291         pos = 0;
5292
5293         if (on && crtc->enabled && crtc->fb) {
5294                 base = intel_crtc->cursor_addr;
5295                 if (x > (int) crtc->fb->width)
5296                         base = 0;
5297
5298                 if (y > (int) crtc->fb->height)
5299                         base = 0;
5300         } else
5301                 base = 0;
5302
5303         if (x < 0) {
5304                 if (x + intel_crtc->cursor_width < 0)
5305                         base = 0;
5306
5307                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5308                 x = -x;
5309         }
5310         pos |= x << CURSOR_X_SHIFT;
5311
5312         if (y < 0) {
5313                 if (y + intel_crtc->cursor_height < 0)
5314                         base = 0;
5315
5316                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5317                 y = -y;
5318         }
5319         pos |= y << CURSOR_Y_SHIFT;
5320
5321         visible = base != 0;
5322         if (!visible && !intel_crtc->cursor_visible)
5323                 return;
5324
5325         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5326                 I915_WRITE(CURPOS_IVB(pipe), pos);
5327                 ivb_update_cursor(crtc, base);
5328         } else {
5329                 I915_WRITE(CURPOS(pipe), pos);
5330                 if (IS_845G(dev) || IS_I865G(dev))
5331                         i845_update_cursor(crtc, base);
5332                 else
5333                         i9xx_update_cursor(crtc, base);
5334         }
5335 }
5336
5337 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5338                                  struct drm_file *file,
5339                                  uint32_t handle,
5340                                  uint32_t width, uint32_t height)
5341 {
5342         struct drm_device *dev = crtc->dev;
5343         struct drm_i915_private *dev_priv = dev->dev_private;
5344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5345         struct drm_i915_gem_object *obj;
5346         uint32_t addr;
5347         int ret;
5348
5349         DRM_DEBUG_KMS("\n");
5350
5351         /* if we want to turn off the cursor ignore width and height */
5352         if (!handle) {
5353                 DRM_DEBUG_KMS("cursor off\n");
5354                 addr = 0;
5355                 obj = NULL;
5356                 mutex_lock(&dev->struct_mutex);
5357                 goto finish;
5358         }
5359
5360         /* Currently we only support 64x64 cursors */
5361         if (width != 64 || height != 64) {
5362                 DRM_ERROR("we currently only support 64x64 cursors\n");
5363                 return -EINVAL;
5364         }
5365
5366         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5367         if (&obj->base == NULL)
5368                 return -ENOENT;
5369
5370         if (obj->base.size < width * height * 4) {
5371                 DRM_ERROR("buffer is to small\n");
5372                 ret = -ENOMEM;
5373                 goto fail;
5374         }
5375
5376         /* we only need to pin inside GTT if cursor is non-phy */
5377         mutex_lock(&dev->struct_mutex);
5378         if (!dev_priv->info->cursor_needs_physical) {
5379                 if (obj->tiling_mode) {
5380                         DRM_ERROR("cursor cannot be tiled\n");
5381                         ret = -EINVAL;
5382                         goto fail_locked;
5383                 }
5384
5385                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5386                 if (ret) {
5387                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5388                         goto fail_locked;
5389                 }
5390
5391                 ret = i915_gem_object_put_fence(obj);
5392                 if (ret) {
5393                         DRM_ERROR("failed to release fence for cursor");
5394                         goto fail_unpin;
5395                 }
5396
5397                 addr = obj->gtt_offset;
5398         } else {
5399                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5400                 ret = i915_gem_attach_phys_object(dev, obj,
5401                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5402                                                   align);
5403                 if (ret) {
5404                         DRM_ERROR("failed to attach phys object\n");
5405                         goto fail_locked;
5406                 }
5407                 addr = obj->phys_obj->handle->busaddr;
5408         }
5409
5410         if (IS_GEN2(dev))
5411                 I915_WRITE(CURSIZE, (height << 12) | width);
5412
5413  finish:
5414         if (intel_crtc->cursor_bo) {
5415                 if (dev_priv->info->cursor_needs_physical) {
5416                         if (intel_crtc->cursor_bo != obj)
5417                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5418                 } else
5419                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5420                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5421         }
5422
5423         mutex_unlock(&dev->struct_mutex);
5424
5425         intel_crtc->cursor_addr = addr;
5426         intel_crtc->cursor_bo = obj;
5427         intel_crtc->cursor_width = width;
5428         intel_crtc->cursor_height = height;
5429
5430         intel_crtc_update_cursor(crtc, true);
5431
5432         return 0;
5433 fail_unpin:
5434         i915_gem_object_unpin(obj);
5435 fail_locked:
5436         mutex_unlock(&dev->struct_mutex);
5437 fail:
5438         drm_gem_object_unreference_unlocked(&obj->base);
5439         return ret;
5440 }
5441
5442 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5443 {
5444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5445
5446         intel_crtc->cursor_x = x;
5447         intel_crtc->cursor_y = y;
5448
5449         intel_crtc_update_cursor(crtc, true);
5450
5451         return 0;
5452 }
5453
5454 /** Sets the color ramps on behalf of RandR */
5455 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5456                                  u16 blue, int regno)
5457 {
5458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5459
5460         intel_crtc->lut_r[regno] = red >> 8;
5461         intel_crtc->lut_g[regno] = green >> 8;
5462         intel_crtc->lut_b[regno] = blue >> 8;
5463 }
5464
5465 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5466                              u16 *blue, int regno)
5467 {
5468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5469
5470         *red = intel_crtc->lut_r[regno] << 8;
5471         *green = intel_crtc->lut_g[regno] << 8;
5472         *blue = intel_crtc->lut_b[regno] << 8;
5473 }
5474
5475 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5476                                  u16 *blue, uint32_t start, uint32_t size)
5477 {
5478         int end = (start + size > 256) ? 256 : start + size, i;
5479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480
5481         for (i = start; i < end; i++) {
5482                 intel_crtc->lut_r[i] = red[i] >> 8;
5483                 intel_crtc->lut_g[i] = green[i] >> 8;
5484                 intel_crtc->lut_b[i] = blue[i] >> 8;
5485         }
5486
5487         intel_crtc_load_lut(crtc);
5488 }
5489
5490 /**
5491  * Get a pipe with a simple mode set on it for doing load-based monitor
5492  * detection.
5493  *
5494  * It will be up to the load-detect code to adjust the pipe as appropriate for
5495  * its requirements.  The pipe will be connected to no other encoders.
5496  *
5497  * Currently this code will only succeed if there is a pipe with no encoders
5498  * configured for it.  In the future, it could choose to temporarily disable
5499  * some outputs to free up a pipe for its use.
5500  *
5501  * \return crtc, or NULL if no pipes are available.
5502  */
5503
5504 /* VESA 640x480x72Hz mode to set on the pipe */
5505 static struct drm_display_mode load_detect_mode = {
5506         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5507                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5508 };
5509
5510 static struct drm_framebuffer *
5511 intel_framebuffer_create(struct drm_device *dev,
5512                          struct drm_mode_fb_cmd2 *mode_cmd,
5513                          struct drm_i915_gem_object *obj)
5514 {
5515         struct intel_framebuffer *intel_fb;
5516         int ret;
5517
5518         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5519         if (!intel_fb) {
5520                 drm_gem_object_unreference_unlocked(&obj->base);
5521                 return ERR_PTR(-ENOMEM);
5522         }
5523
5524         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5525         if (ret) {
5526                 drm_gem_object_unreference_unlocked(&obj->base);
5527                 kfree(intel_fb);
5528                 return ERR_PTR(ret);
5529         }
5530
5531         return &intel_fb->base;
5532 }
5533
5534 static u32
5535 intel_framebuffer_pitch_for_width(int width, int bpp)
5536 {
5537         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5538         return ALIGN(pitch, 64);
5539 }
5540
5541 static u32
5542 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5543 {
5544         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5545         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5546 }
5547
5548 static struct drm_framebuffer *
5549 intel_framebuffer_create_for_mode(struct drm_device *dev,
5550                                   struct drm_display_mode *mode,
5551                                   int depth, int bpp)
5552 {
5553         struct drm_i915_gem_object *obj;
5554         struct drm_mode_fb_cmd2 mode_cmd;
5555
5556         obj = i915_gem_alloc_object(dev,
5557                                     intel_framebuffer_size_for_mode(mode, bpp));
5558         if (obj == NULL)
5559                 return ERR_PTR(-ENOMEM);
5560
5561         mode_cmd.width = mode->hdisplay;
5562         mode_cmd.height = mode->vdisplay;
5563         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5564                                                                 bpp);
5565         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5566
5567         return intel_framebuffer_create(dev, &mode_cmd, obj);
5568 }
5569
5570 static struct drm_framebuffer *
5571 mode_fits_in_fbdev(struct drm_device *dev,
5572                    struct drm_display_mode *mode)
5573 {
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         struct drm_i915_gem_object *obj;
5576         struct drm_framebuffer *fb;
5577
5578         if (dev_priv->fbdev == NULL)
5579                 return NULL;
5580
5581         obj = dev_priv->fbdev->ifb.obj;
5582         if (obj == NULL)
5583                 return NULL;
5584
5585         fb = &dev_priv->fbdev->ifb.base;
5586         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5587                                                                fb->bits_per_pixel))
5588                 return NULL;
5589
5590         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5591                 return NULL;
5592
5593         return fb;
5594 }
5595
5596 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5597                                 struct drm_connector *connector,
5598                                 struct drm_display_mode *mode,
5599                                 struct intel_load_detect_pipe *old)
5600 {
5601         struct intel_crtc *intel_crtc;
5602         struct drm_crtc *possible_crtc;
5603         struct drm_encoder *encoder = &intel_encoder->base;
5604         struct drm_crtc *crtc = NULL;
5605         struct drm_device *dev = encoder->dev;
5606         struct drm_framebuffer *old_fb;
5607         int i = -1;
5608
5609         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5610                       connector->base.id, drm_get_connector_name(connector),
5611                       encoder->base.id, drm_get_encoder_name(encoder));
5612
5613         /*
5614          * Algorithm gets a little messy:
5615          *
5616          *   - if the connector already has an assigned crtc, use it (but make
5617          *     sure it's on first)
5618          *
5619          *   - try to find the first unused crtc that can drive this connector,
5620          *     and use that if we find one
5621          */
5622
5623         /* See if we already have a CRTC for this connector */
5624         if (encoder->crtc) {
5625                 crtc = encoder->crtc;
5626
5627                 intel_crtc = to_intel_crtc(crtc);
5628                 old->dpms_mode = intel_crtc->dpms_mode;
5629                 old->load_detect_temp = false;
5630
5631                 /* Make sure the crtc and connector are running */
5632                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5633                         struct drm_encoder_helper_funcs *encoder_funcs;
5634                         struct drm_crtc_helper_funcs *crtc_funcs;
5635
5636                         crtc_funcs = crtc->helper_private;
5637                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5638
5639                         encoder_funcs = encoder->helper_private;
5640                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5641                 }
5642
5643                 return true;
5644         }
5645
5646         /* Find an unused one (if possible) */
5647         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5648                 i++;
5649                 if (!(encoder->possible_crtcs & (1 << i)))
5650                         continue;
5651                 if (!possible_crtc->enabled) {
5652                         crtc = possible_crtc;
5653                         break;
5654                 }
5655         }
5656
5657         /*
5658          * If we didn't find an unused CRTC, don't use any.
5659          */
5660         if (!crtc) {
5661                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5662                 return false;
5663         }
5664
5665         encoder->crtc = crtc;
5666         connector->encoder = encoder;
5667
5668         intel_crtc = to_intel_crtc(crtc);
5669         old->dpms_mode = intel_crtc->dpms_mode;
5670         old->load_detect_temp = true;
5671         old->release_fb = NULL;
5672
5673         if (!mode)
5674                 mode = &load_detect_mode;
5675
5676         old_fb = crtc->fb;
5677
5678         /* We need a framebuffer large enough to accommodate all accesses
5679          * that the plane may generate whilst we perform load detection.
5680          * We can not rely on the fbcon either being present (we get called
5681          * during its initialisation to detect all boot displays, or it may
5682          * not even exist) or that it is large enough to satisfy the
5683          * requested mode.
5684          */
5685         crtc->fb = mode_fits_in_fbdev(dev, mode);
5686         if (crtc->fb == NULL) {
5687                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5688                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5689                 old->release_fb = crtc->fb;
5690         } else
5691                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5692         if (IS_ERR(crtc->fb)) {
5693                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5694                 crtc->fb = old_fb;
5695                 return false;
5696         }
5697
5698         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5699                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5700                 if (old->release_fb)
5701                         old->release_fb->funcs->destroy(old->release_fb);
5702                 crtc->fb = old_fb;
5703                 return false;
5704         }
5705
5706         /* let the connector get through one full cycle before testing */
5707         intel_wait_for_vblank(dev, intel_crtc->pipe);
5708
5709         return true;
5710 }
5711
5712 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5713                                     struct drm_connector *connector,
5714                                     struct intel_load_detect_pipe *old)
5715 {
5716         struct drm_encoder *encoder = &intel_encoder->base;
5717         struct drm_device *dev = encoder->dev;
5718         struct drm_crtc *crtc = encoder->crtc;
5719         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5720         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5721
5722         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5723                       connector->base.id, drm_get_connector_name(connector),
5724                       encoder->base.id, drm_get_encoder_name(encoder));
5725
5726         if (old->load_detect_temp) {
5727                 connector->encoder = NULL;
5728                 drm_helper_disable_unused_functions(dev);
5729
5730                 if (old->release_fb)
5731                         old->release_fb->funcs->destroy(old->release_fb);
5732
5733                 return;
5734         }
5735
5736         /* Switch crtc and encoder back off if necessary */
5737         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5738                 encoder_funcs->dpms(encoder, old->dpms_mode);
5739                 crtc_funcs->dpms(crtc, old->dpms_mode);
5740         }
5741 }
5742
5743 /* Returns the clock of the currently programmed mode of the given pipe. */
5744 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5745 {
5746         struct drm_i915_private *dev_priv = dev->dev_private;
5747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5748         int pipe = intel_crtc->pipe;
5749         u32 dpll = I915_READ(DPLL(pipe));
5750         u32 fp;
5751         intel_clock_t clock;
5752
5753         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5754                 fp = I915_READ(FP0(pipe));
5755         else
5756                 fp = I915_READ(FP1(pipe));
5757
5758         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5759         if (IS_PINEVIEW(dev)) {
5760                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5761                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5762         } else {
5763                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5764                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5765         }
5766
5767         if (!IS_GEN2(dev)) {
5768                 if (IS_PINEVIEW(dev))
5769                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5770                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5771                 else
5772                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5773                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5774
5775                 switch (dpll & DPLL_MODE_MASK) {
5776                 case DPLLB_MODE_DAC_SERIAL:
5777                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5778                                 5 : 10;
5779                         break;
5780                 case DPLLB_MODE_LVDS:
5781                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5782                                 7 : 14;
5783                         break;
5784                 default:
5785                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5786                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5787                         return 0;
5788                 }
5789
5790                 /* XXX: Handle the 100Mhz refclk */
5791                 intel_clock(dev, 96000, &clock);
5792         } else {
5793                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5794
5795                 if (is_lvds) {
5796                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5797                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5798                         clock.p2 = 14;
5799
5800                         if ((dpll & PLL_REF_INPUT_MASK) ==
5801                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5802                                 /* XXX: might not be 66MHz */
5803                                 intel_clock(dev, 66000, &clock);
5804                         } else
5805                                 intel_clock(dev, 48000, &clock);
5806                 } else {
5807                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5808                                 clock.p1 = 2;
5809                         else {
5810                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5811                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5812                         }
5813                         if (dpll & PLL_P2_DIVIDE_BY_4)
5814                                 clock.p2 = 4;
5815                         else
5816                                 clock.p2 = 2;
5817
5818                         intel_clock(dev, 48000, &clock);
5819                 }
5820         }
5821
5822         /* XXX: It would be nice to validate the clocks, but we can't reuse
5823          * i830PllIsValid() because it relies on the xf86_config connector
5824          * configuration being accurate, which it isn't necessarily.
5825          */
5826
5827         return clock.dot;
5828 }
5829
5830 /** Returns the currently programmed mode of the given pipe. */
5831 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5832                                              struct drm_crtc *crtc)
5833 {
5834         struct drm_i915_private *dev_priv = dev->dev_private;
5835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836         int pipe = intel_crtc->pipe;
5837         struct drm_display_mode *mode;
5838         int htot = I915_READ(HTOTAL(pipe));
5839         int hsync = I915_READ(HSYNC(pipe));
5840         int vtot = I915_READ(VTOTAL(pipe));
5841         int vsync = I915_READ(VSYNC(pipe));
5842
5843         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5844         if (!mode)
5845                 return NULL;
5846
5847         mode->clock = intel_crtc_clock_get(dev, crtc);
5848         mode->hdisplay = (htot & 0xffff) + 1;
5849         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5850         mode->hsync_start = (hsync & 0xffff) + 1;
5851         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5852         mode->vdisplay = (vtot & 0xffff) + 1;
5853         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5854         mode->vsync_start = (vsync & 0xffff) + 1;
5855         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5856
5857         drm_mode_set_name(mode);
5858
5859         return mode;
5860 }
5861
5862 #define GPU_IDLE_TIMEOUT 500 /* ms */
5863
5864 /* When this timer fires, we've been idle for awhile */
5865 static void intel_gpu_idle_timer(unsigned long arg)
5866 {
5867         struct drm_device *dev = (struct drm_device *)arg;
5868         drm_i915_private_t *dev_priv = dev->dev_private;
5869
5870         if (!list_empty(&dev_priv->mm.active_list)) {
5871                 /* Still processing requests, so just re-arm the timer. */
5872                 mod_timer(&dev_priv->idle_timer, jiffies +
5873                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5874                 return;
5875         }
5876
5877         dev_priv->busy = false;
5878         queue_work(dev_priv->wq, &dev_priv->idle_work);
5879 }
5880
5881 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5882
5883 static void intel_crtc_idle_timer(unsigned long arg)
5884 {
5885         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5886         struct drm_crtc *crtc = &intel_crtc->base;
5887         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5888         struct intel_framebuffer *intel_fb;
5889
5890         intel_fb = to_intel_framebuffer(crtc->fb);
5891         if (intel_fb && intel_fb->obj->active) {
5892                 /* The framebuffer is still being accessed by the GPU. */
5893                 mod_timer(&intel_crtc->idle_timer, jiffies +
5894                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5895                 return;
5896         }
5897
5898         intel_crtc->busy = false;
5899         queue_work(dev_priv->wq, &dev_priv->idle_work);
5900 }
5901
5902 static void intel_increase_pllclock(struct drm_crtc *crtc)
5903 {
5904         struct drm_device *dev = crtc->dev;
5905         drm_i915_private_t *dev_priv = dev->dev_private;
5906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5907         int pipe = intel_crtc->pipe;
5908         int dpll_reg = DPLL(pipe);
5909         int dpll;
5910
5911         if (HAS_PCH_SPLIT(dev))
5912                 return;
5913
5914         if (!dev_priv->lvds_downclock_avail)
5915                 return;
5916
5917         dpll = I915_READ(dpll_reg);
5918         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5919                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5920
5921                 assert_panel_unlocked(dev_priv, pipe);
5922
5923                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5924                 I915_WRITE(dpll_reg, dpll);
5925                 intel_wait_for_vblank(dev, pipe);
5926
5927                 dpll = I915_READ(dpll_reg);
5928                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5929                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5930         }
5931
5932         /* Schedule downclock */
5933         mod_timer(&intel_crtc->idle_timer, jiffies +
5934                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5935 }
5936
5937 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5938 {
5939         struct drm_device *dev = crtc->dev;
5940         drm_i915_private_t *dev_priv = dev->dev_private;
5941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942
5943         if (HAS_PCH_SPLIT(dev))
5944                 return;
5945
5946         if (!dev_priv->lvds_downclock_avail)
5947                 return;
5948
5949         /*
5950          * Since this is called by a timer, we should never get here in
5951          * the manual case.
5952          */
5953         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5954                 int pipe = intel_crtc->pipe;
5955                 int dpll_reg = DPLL(pipe);
5956                 int dpll;
5957
5958                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5959
5960                 assert_panel_unlocked(dev_priv, pipe);
5961
5962                 dpll = I915_READ(dpll_reg);
5963                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5964                 I915_WRITE(dpll_reg, dpll);
5965                 intel_wait_for_vblank(dev, pipe);
5966                 dpll = I915_READ(dpll_reg);
5967                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5968                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5969         }
5970
5971 }
5972
5973 /**
5974  * intel_idle_update - adjust clocks for idleness
5975  * @work: work struct
5976  *
5977  * Either the GPU or display (or both) went idle.  Check the busy status
5978  * here and adjust the CRTC and GPU clocks as necessary.
5979  */
5980 static void intel_idle_update(struct work_struct *work)
5981 {
5982         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5983                                                     idle_work);
5984         struct drm_device *dev = dev_priv->dev;
5985         struct drm_crtc *crtc;
5986         struct intel_crtc *intel_crtc;
5987
5988         if (!i915_powersave)
5989                 return;
5990
5991         mutex_lock(&dev->struct_mutex);
5992
5993         i915_update_gfx_val(dev_priv);
5994
5995         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5996                 /* Skip inactive CRTCs */
5997                 if (!crtc->fb)
5998                         continue;
5999
6000                 intel_crtc = to_intel_crtc(crtc);
6001                 if (!intel_crtc->busy)
6002                         intel_decrease_pllclock(crtc);
6003         }
6004
6005
6006         mutex_unlock(&dev->struct_mutex);
6007 }
6008
6009 /**
6010  * intel_mark_busy - mark the GPU and possibly the display busy
6011  * @dev: drm device
6012  * @obj: object we're operating on
6013  *
6014  * Callers can use this function to indicate that the GPU is busy processing
6015  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6016  * buffer), we'll also mark the display as busy, so we know to increase its
6017  * clock frequency.
6018  */
6019 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6020 {
6021         drm_i915_private_t *dev_priv = dev->dev_private;
6022         struct drm_crtc *crtc = NULL;
6023         struct intel_framebuffer *intel_fb;
6024         struct intel_crtc *intel_crtc;
6025
6026         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6027                 return;
6028
6029         if (!dev_priv->busy) {
6030                 intel_sanitize_pm(dev);
6031                 dev_priv->busy = true;
6032         } else
6033                 mod_timer(&dev_priv->idle_timer, jiffies +
6034                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6035
6036         if (obj == NULL)
6037                 return;
6038
6039         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6040                 if (!crtc->fb)
6041                         continue;
6042
6043                 intel_crtc = to_intel_crtc(crtc);
6044                 intel_fb = to_intel_framebuffer(crtc->fb);
6045                 if (intel_fb->obj == obj) {
6046                         if (!intel_crtc->busy) {
6047                                 /* Non-busy -> busy, upclock */
6048                                 intel_increase_pllclock(crtc);
6049                                 intel_crtc->busy = true;
6050                         } else {
6051                                 /* Busy -> busy, put off timer */
6052                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6053                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6054                         }
6055                 }
6056         }
6057 }
6058
6059 static void intel_crtc_destroy(struct drm_crtc *crtc)
6060 {
6061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6062         struct drm_device *dev = crtc->dev;
6063         struct intel_unpin_work *work;
6064         unsigned long flags;
6065
6066         spin_lock_irqsave(&dev->event_lock, flags);
6067         work = intel_crtc->unpin_work;
6068         intel_crtc->unpin_work = NULL;
6069         spin_unlock_irqrestore(&dev->event_lock, flags);
6070
6071         if (work) {
6072                 cancel_work_sync(&work->work);
6073                 kfree(work);
6074         }
6075
6076         drm_crtc_cleanup(crtc);
6077
6078         kfree(intel_crtc);
6079 }
6080
6081 static void intel_unpin_work_fn(struct work_struct *__work)
6082 {
6083         struct intel_unpin_work *work =
6084                 container_of(__work, struct intel_unpin_work, work);
6085
6086         mutex_lock(&work->dev->struct_mutex);
6087         intel_unpin_fb_obj(work->old_fb_obj);
6088         drm_gem_object_unreference(&work->pending_flip_obj->base);
6089         drm_gem_object_unreference(&work->old_fb_obj->base);
6090
6091         intel_update_fbc(work->dev);
6092         mutex_unlock(&work->dev->struct_mutex);
6093         kfree(work);
6094 }
6095
6096 static void do_intel_finish_page_flip(struct drm_device *dev,
6097                                       struct drm_crtc *crtc)
6098 {
6099         drm_i915_private_t *dev_priv = dev->dev_private;
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101         struct intel_unpin_work *work;
6102         struct drm_i915_gem_object *obj;
6103         struct drm_pending_vblank_event *e;
6104         struct timeval tnow, tvbl;
6105         unsigned long flags;
6106
6107         /* Ignore early vblank irqs */
6108         if (intel_crtc == NULL)
6109                 return;
6110
6111         do_gettimeofday(&tnow);
6112
6113         spin_lock_irqsave(&dev->event_lock, flags);
6114         work = intel_crtc->unpin_work;
6115         if (work == NULL || !work->pending) {
6116                 spin_unlock_irqrestore(&dev->event_lock, flags);
6117                 return;
6118         }
6119
6120         intel_crtc->unpin_work = NULL;
6121
6122         if (work->event) {
6123                 e = work->event;
6124                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6125
6126                 /* Called before vblank count and timestamps have
6127                  * been updated for the vblank interval of flip
6128                  * completion? Need to increment vblank count and
6129                  * add one videorefresh duration to returned timestamp
6130                  * to account for this. We assume this happened if we
6131                  * get called over 0.9 frame durations after the last
6132                  * timestamped vblank.
6133                  *
6134                  * This calculation can not be used with vrefresh rates
6135                  * below 5Hz (10Hz to be on the safe side) without
6136                  * promoting to 64 integers.
6137                  */
6138                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6139                     9 * crtc->framedur_ns) {
6140                         e->event.sequence++;
6141                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6142                                              crtc->framedur_ns);
6143                 }
6144
6145                 e->event.tv_sec = tvbl.tv_sec;
6146                 e->event.tv_usec = tvbl.tv_usec;
6147
6148                 list_add_tail(&e->base.link,
6149                               &e->base.file_priv->event_list);
6150                 wake_up_interruptible(&e->base.file_priv->event_wait);
6151         }
6152
6153         drm_vblank_put(dev, intel_crtc->pipe);
6154
6155         spin_unlock_irqrestore(&dev->event_lock, flags);
6156
6157         obj = work->old_fb_obj;
6158
6159         atomic_clear_mask(1 << intel_crtc->plane,
6160                           &obj->pending_flip.counter);
6161         if (atomic_read(&obj->pending_flip) == 0)
6162                 wake_up(&dev_priv->pending_flip_queue);
6163
6164         schedule_work(&work->work);
6165
6166         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6167 }
6168
6169 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6170 {
6171         drm_i915_private_t *dev_priv = dev->dev_private;
6172         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6173
6174         do_intel_finish_page_flip(dev, crtc);
6175 }
6176
6177 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6178 {
6179         drm_i915_private_t *dev_priv = dev->dev_private;
6180         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6181
6182         do_intel_finish_page_flip(dev, crtc);
6183 }
6184
6185 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6186 {
6187         drm_i915_private_t *dev_priv = dev->dev_private;
6188         struct intel_crtc *intel_crtc =
6189                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6190         unsigned long flags;
6191
6192         spin_lock_irqsave(&dev->event_lock, flags);
6193         if (intel_crtc->unpin_work) {
6194                 if ((++intel_crtc->unpin_work->pending) > 1)
6195                         DRM_ERROR("Prepared flip multiple times\n");
6196         } else {
6197                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6198         }
6199         spin_unlock_irqrestore(&dev->event_lock, flags);
6200 }
6201
6202 static int intel_gen2_queue_flip(struct drm_device *dev,
6203                                  struct drm_crtc *crtc,
6204                                  struct drm_framebuffer *fb,
6205                                  struct drm_i915_gem_object *obj)
6206 {
6207         struct drm_i915_private *dev_priv = dev->dev_private;
6208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209         u32 flip_mask;
6210         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6211         int ret;
6212
6213         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6214         if (ret)
6215                 goto err;
6216
6217         ret = intel_ring_begin(ring, 6);
6218         if (ret)
6219                 goto err_unpin;
6220
6221         /* Can't queue multiple flips, so wait for the previous
6222          * one to finish before executing the next.
6223          */
6224         if (intel_crtc->plane)
6225                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6226         else
6227                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6228         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6229         intel_ring_emit(ring, MI_NOOP);
6230         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6231                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6232         intel_ring_emit(ring, fb->pitches[0]);
6233         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6234         intel_ring_emit(ring, 0); /* aux display base address, unused */
6235         intel_ring_advance(ring);
6236         return 0;
6237
6238 err_unpin:
6239         intel_unpin_fb_obj(obj);
6240 err:
6241         return ret;
6242 }
6243
6244 static int intel_gen3_queue_flip(struct drm_device *dev,
6245                                  struct drm_crtc *crtc,
6246                                  struct drm_framebuffer *fb,
6247                                  struct drm_i915_gem_object *obj)
6248 {
6249         struct drm_i915_private *dev_priv = dev->dev_private;
6250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251         u32 flip_mask;
6252         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6253         int ret;
6254
6255         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6256         if (ret)
6257                 goto err;
6258
6259         ret = intel_ring_begin(ring, 6);
6260         if (ret)
6261                 goto err_unpin;
6262
6263         if (intel_crtc->plane)
6264                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6265         else
6266                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6267         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6268         intel_ring_emit(ring, MI_NOOP);
6269         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6270                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6271         intel_ring_emit(ring, fb->pitches[0]);
6272         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6273         intel_ring_emit(ring, MI_NOOP);
6274
6275         intel_ring_advance(ring);
6276         return 0;
6277
6278 err_unpin:
6279         intel_unpin_fb_obj(obj);
6280 err:
6281         return ret;
6282 }
6283
6284 static int intel_gen4_queue_flip(struct drm_device *dev,
6285                                  struct drm_crtc *crtc,
6286                                  struct drm_framebuffer *fb,
6287                                  struct drm_i915_gem_object *obj)
6288 {
6289         struct drm_i915_private *dev_priv = dev->dev_private;
6290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6291         uint32_t pf, pipesrc;
6292         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6293         int ret;
6294
6295         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6296         if (ret)
6297                 goto err;
6298
6299         ret = intel_ring_begin(ring, 4);
6300         if (ret)
6301                 goto err_unpin;
6302
6303         /* i965+ uses the linear or tiled offsets from the
6304          * Display Registers (which do not change across a page-flip)
6305          * so we need only reprogram the base address.
6306          */
6307         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6308                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6309         intel_ring_emit(ring, fb->pitches[0]);
6310         intel_ring_emit(ring,
6311                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6312                         obj->tiling_mode);
6313
6314         /* XXX Enabling the panel-fitter across page-flip is so far
6315          * untested on non-native modes, so ignore it for now.
6316          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6317          */
6318         pf = 0;
6319         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6320         intel_ring_emit(ring, pf | pipesrc);
6321         intel_ring_advance(ring);
6322         return 0;
6323
6324 err_unpin:
6325         intel_unpin_fb_obj(obj);
6326 err:
6327         return ret;
6328 }
6329
6330 static int intel_gen6_queue_flip(struct drm_device *dev,
6331                                  struct drm_crtc *crtc,
6332                                  struct drm_framebuffer *fb,
6333                                  struct drm_i915_gem_object *obj)
6334 {
6335         struct drm_i915_private *dev_priv = dev->dev_private;
6336         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6338         uint32_t pf, pipesrc;
6339         int ret;
6340
6341         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6342         if (ret)
6343                 goto err;
6344
6345         ret = intel_ring_begin(ring, 4);
6346         if (ret)
6347                 goto err_unpin;
6348
6349         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6350                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6351         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6352         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6353
6354         /* Contrary to the suggestions in the documentation,
6355          * "Enable Panel Fitter" does not seem to be required when page
6356          * flipping with a non-native mode, and worse causes a normal
6357          * modeset to fail.
6358          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6359          */
6360         pf = 0;
6361         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6362         intel_ring_emit(ring, pf | pipesrc);
6363         intel_ring_advance(ring);
6364         return 0;
6365
6366 err_unpin:
6367         intel_unpin_fb_obj(obj);
6368 err:
6369         return ret;
6370 }
6371
6372 /*
6373  * On gen7 we currently use the blit ring because (in early silicon at least)
6374  * the render ring doesn't give us interrpts for page flip completion, which
6375  * means clients will hang after the first flip is queued.  Fortunately the
6376  * blit ring generates interrupts properly, so use it instead.
6377  */
6378 static int intel_gen7_queue_flip(struct drm_device *dev,
6379                                  struct drm_crtc *crtc,
6380                                  struct drm_framebuffer *fb,
6381                                  struct drm_i915_gem_object *obj)
6382 {
6383         struct drm_i915_private *dev_priv = dev->dev_private;
6384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6386         uint32_t plane_bit = 0;
6387         int ret;
6388
6389         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6390         if (ret)
6391                 goto err;
6392
6393         switch(intel_crtc->plane) {
6394         case PLANE_A:
6395                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6396                 break;
6397         case PLANE_B:
6398                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6399                 break;
6400         case PLANE_C:
6401                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6402                 break;
6403         default:
6404                 WARN_ONCE(1, "unknown plane in flip command\n");
6405                 ret = -ENODEV;
6406                 goto err;
6407         }
6408
6409         ret = intel_ring_begin(ring, 4);
6410         if (ret)
6411                 goto err_unpin;
6412
6413         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6414         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6415         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6416         intel_ring_emit(ring, (MI_NOOP));
6417         intel_ring_advance(ring);
6418         return 0;
6419
6420 err_unpin:
6421         intel_unpin_fb_obj(obj);
6422 err:
6423         return ret;
6424 }
6425
6426 static int intel_default_queue_flip(struct drm_device *dev,
6427                                     struct drm_crtc *crtc,
6428                                     struct drm_framebuffer *fb,
6429                                     struct drm_i915_gem_object *obj)
6430 {
6431         return -ENODEV;
6432 }
6433
6434 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6435                                 struct drm_framebuffer *fb,
6436                                 struct drm_pending_vblank_event *event)
6437 {
6438         struct drm_device *dev = crtc->dev;
6439         struct drm_i915_private *dev_priv = dev->dev_private;
6440         struct intel_framebuffer *intel_fb;
6441         struct drm_i915_gem_object *obj;
6442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6443         struct intel_unpin_work *work;
6444         unsigned long flags;
6445         int ret;
6446
6447         /* Can't change pixel format via MI display flips. */
6448         if (fb->pixel_format != crtc->fb->pixel_format)
6449                 return -EINVAL;
6450
6451         /*
6452          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6453          * Note that pitch changes could also affect these register.
6454          */
6455         if (INTEL_INFO(dev)->gen > 3 &&
6456             (fb->offsets[0] != crtc->fb->offsets[0] ||
6457              fb->pitches[0] != crtc->fb->pitches[0]))
6458                 return -EINVAL;
6459
6460         work = kzalloc(sizeof *work, GFP_KERNEL);
6461         if (work == NULL)
6462                 return -ENOMEM;
6463
6464         work->event = event;
6465         work->dev = crtc->dev;
6466         intel_fb = to_intel_framebuffer(crtc->fb);
6467         work->old_fb_obj = intel_fb->obj;
6468         INIT_WORK(&work->work, intel_unpin_work_fn);
6469
6470         ret = drm_vblank_get(dev, intel_crtc->pipe);
6471         if (ret)
6472                 goto free_work;
6473
6474         /* We borrow the event spin lock for protecting unpin_work */
6475         spin_lock_irqsave(&dev->event_lock, flags);
6476         if (intel_crtc->unpin_work) {
6477                 spin_unlock_irqrestore(&dev->event_lock, flags);
6478                 kfree(work);
6479                 drm_vblank_put(dev, intel_crtc->pipe);
6480
6481                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6482                 return -EBUSY;
6483         }
6484         intel_crtc->unpin_work = work;
6485         spin_unlock_irqrestore(&dev->event_lock, flags);
6486
6487         intel_fb = to_intel_framebuffer(fb);
6488         obj = intel_fb->obj;
6489
6490         ret = i915_mutex_lock_interruptible(dev);
6491         if (ret)
6492                 goto cleanup;
6493
6494         /* Reference the objects for the scheduled work. */
6495         drm_gem_object_reference(&work->old_fb_obj->base);
6496         drm_gem_object_reference(&obj->base);
6497
6498         crtc->fb = fb;
6499
6500         work->pending_flip_obj = obj;
6501
6502         work->enable_stall_check = true;
6503
6504         /* Block clients from rendering to the new back buffer until
6505          * the flip occurs and the object is no longer visible.
6506          */
6507         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6508
6509         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6510         if (ret)
6511                 goto cleanup_pending;
6512
6513         intel_disable_fbc(dev);
6514         intel_mark_busy(dev, obj);
6515         mutex_unlock(&dev->struct_mutex);
6516
6517         trace_i915_flip_request(intel_crtc->plane, obj);
6518
6519         return 0;
6520
6521 cleanup_pending:
6522         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6523         drm_gem_object_unreference(&work->old_fb_obj->base);
6524         drm_gem_object_unreference(&obj->base);
6525         mutex_unlock(&dev->struct_mutex);
6526
6527 cleanup:
6528         spin_lock_irqsave(&dev->event_lock, flags);
6529         intel_crtc->unpin_work = NULL;
6530         spin_unlock_irqrestore(&dev->event_lock, flags);
6531
6532         drm_vblank_put(dev, intel_crtc->pipe);
6533 free_work:
6534         kfree(work);
6535
6536         return ret;
6537 }
6538
6539 static void intel_sanitize_modesetting(struct drm_device *dev,
6540                                        int pipe, int plane)
6541 {
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         u32 reg, val;
6544         int i;
6545
6546         /* Clear any frame start delays used for debugging left by the BIOS */
6547         for_each_pipe(i) {
6548                 reg = PIPECONF(i);
6549                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6550         }
6551
6552         if (HAS_PCH_SPLIT(dev))
6553                 return;
6554
6555         /* Who knows what state these registers were left in by the BIOS or
6556          * grub?
6557          *
6558          * If we leave the registers in a conflicting state (e.g. with the
6559          * display plane reading from the other pipe than the one we intend
6560          * to use) then when we attempt to teardown the active mode, we will
6561          * not disable the pipes and planes in the correct order -- leaving
6562          * a plane reading from a disabled pipe and possibly leading to
6563          * undefined behaviour.
6564          */
6565
6566         reg = DSPCNTR(plane);
6567         val = I915_READ(reg);
6568
6569         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6570                 return;
6571         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6572                 return;
6573
6574         /* This display plane is active and attached to the other CPU pipe. */
6575         pipe = !pipe;
6576
6577         /* Disable the plane and wait for it to stop reading from the pipe. */
6578         intel_disable_plane(dev_priv, plane, pipe);
6579         intel_disable_pipe(dev_priv, pipe);
6580 }
6581
6582 static void intel_crtc_reset(struct drm_crtc *crtc)
6583 {
6584         struct drm_device *dev = crtc->dev;
6585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586
6587         /* Reset flags back to the 'unknown' status so that they
6588          * will be correctly set on the initial modeset.
6589          */
6590         intel_crtc->dpms_mode = -1;
6591
6592         /* We need to fix up any BIOS configuration that conflicts with
6593          * our expectations.
6594          */
6595         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6596 }
6597
6598 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6599         .dpms = intel_crtc_dpms,
6600         .mode_fixup = intel_crtc_mode_fixup,
6601         .mode_set = intel_crtc_mode_set,
6602         .mode_set_base = intel_pipe_set_base,
6603         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6604         .load_lut = intel_crtc_load_lut,
6605         .disable = intel_crtc_disable,
6606 };
6607
6608 static const struct drm_crtc_funcs intel_crtc_funcs = {
6609         .reset = intel_crtc_reset,
6610         .cursor_set = intel_crtc_cursor_set,
6611         .cursor_move = intel_crtc_cursor_move,
6612         .gamma_set = intel_crtc_gamma_set,
6613         .set_config = drm_crtc_helper_set_config,
6614         .destroy = intel_crtc_destroy,
6615         .page_flip = intel_crtc_page_flip,
6616 };
6617
6618 static void intel_pch_pll_init(struct drm_device *dev)
6619 {
6620         drm_i915_private_t *dev_priv = dev->dev_private;
6621         int i;
6622
6623         if (dev_priv->num_pch_pll == 0) {
6624                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6625                 return;
6626         }
6627
6628         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6629                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6630                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6631                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6632         }
6633 }
6634
6635 static void intel_crtc_init(struct drm_device *dev, int pipe)
6636 {
6637         drm_i915_private_t *dev_priv = dev->dev_private;
6638         struct intel_crtc *intel_crtc;
6639         int i;
6640
6641         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6642         if (intel_crtc == NULL)
6643                 return;
6644
6645         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6646
6647         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6648         for (i = 0; i < 256; i++) {
6649                 intel_crtc->lut_r[i] = i;
6650                 intel_crtc->lut_g[i] = i;
6651                 intel_crtc->lut_b[i] = i;
6652         }
6653
6654         /* Swap pipes & planes for FBC on pre-965 */
6655         intel_crtc->pipe = pipe;
6656         intel_crtc->plane = pipe;
6657         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6658                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6659                 intel_crtc->plane = !pipe;
6660         }
6661
6662         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6663                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6664         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6665         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6666
6667         intel_crtc_reset(&intel_crtc->base);
6668         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6669         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6670
6671         if (HAS_PCH_SPLIT(dev)) {
6672                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6673                 intel_helper_funcs.commit = ironlake_crtc_commit;
6674         } else {
6675                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6676                 intel_helper_funcs.commit = i9xx_crtc_commit;
6677         }
6678
6679         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6680
6681         intel_crtc->busy = false;
6682
6683         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6684                     (unsigned long)intel_crtc);
6685 }
6686
6687 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6688                                 struct drm_file *file)
6689 {
6690         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6691         struct drm_mode_object *drmmode_obj;
6692         struct intel_crtc *crtc;
6693
6694         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6695                 return -ENODEV;
6696
6697         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6698                         DRM_MODE_OBJECT_CRTC);
6699
6700         if (!drmmode_obj) {
6701                 DRM_ERROR("no such CRTC id\n");
6702                 return -EINVAL;
6703         }
6704
6705         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6706         pipe_from_crtc_id->pipe = crtc->pipe;
6707
6708         return 0;
6709 }
6710
6711 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6712 {
6713         struct intel_encoder *encoder;
6714         int index_mask = 0;
6715         int entry = 0;
6716
6717         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6718                 if (type_mask & encoder->clone_mask)
6719                         index_mask |= (1 << entry);
6720                 entry++;
6721         }
6722
6723         return index_mask;
6724 }
6725
6726 static bool has_edp_a(struct drm_device *dev)
6727 {
6728         struct drm_i915_private *dev_priv = dev->dev_private;
6729
6730         if (!IS_MOBILE(dev))
6731                 return false;
6732
6733         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6734                 return false;
6735
6736         if (IS_GEN5(dev) &&
6737             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6738                 return false;
6739
6740         return true;
6741 }
6742
6743 static void intel_setup_outputs(struct drm_device *dev)
6744 {
6745         struct drm_i915_private *dev_priv = dev->dev_private;
6746         struct intel_encoder *encoder;
6747         bool dpd_is_edp = false;
6748         bool has_lvds;
6749
6750         has_lvds = intel_lvds_init(dev);
6751         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6752                 /* disable the panel fitter on everything but LVDS */
6753                 I915_WRITE(PFIT_CONTROL, 0);
6754         }
6755
6756         if (HAS_PCH_SPLIT(dev)) {
6757                 dpd_is_edp = intel_dpd_is_edp(dev);
6758
6759                 if (has_edp_a(dev))
6760                         intel_dp_init(dev, DP_A);
6761
6762                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6763                         intel_dp_init(dev, PCH_DP_D);
6764         }
6765
6766         intel_crt_init(dev);
6767
6768         if (IS_HASWELL(dev)) {
6769                 int found;
6770
6771                 /* Haswell uses DDI functions to detect digital outputs */
6772                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6773                 /* DDI A only supports eDP */
6774                 if (found)
6775                         intel_ddi_init(dev, PORT_A);
6776
6777                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6778                  * register */
6779                 found = I915_READ(SFUSE_STRAP);
6780
6781                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6782                         intel_ddi_init(dev, PORT_B);
6783                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6784                         intel_ddi_init(dev, PORT_C);
6785                 if (found & SFUSE_STRAP_DDID_DETECTED)
6786                         intel_ddi_init(dev, PORT_D);
6787         } else if (HAS_PCH_SPLIT(dev)) {
6788                 int found;
6789
6790                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6791                         /* PCH SDVOB multiplex with HDMIB */
6792                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6793                         if (!found)
6794                                 intel_hdmi_init(dev, HDMIB);
6795                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6796                                 intel_dp_init(dev, PCH_DP_B);
6797                 }
6798
6799                 if (I915_READ(HDMIC) & PORT_DETECTED)
6800                         intel_hdmi_init(dev, HDMIC);
6801
6802                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6803                         intel_hdmi_init(dev, HDMID);
6804
6805                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6806                         intel_dp_init(dev, PCH_DP_C);
6807
6808                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6809                         intel_dp_init(dev, PCH_DP_D);
6810         } else if (IS_VALLEYVIEW(dev)) {
6811                 int found;
6812
6813                 if (I915_READ(SDVOB) & PORT_DETECTED) {
6814                         /* SDVOB multiplex with HDMIB */
6815                         found = intel_sdvo_init(dev, SDVOB, true);
6816                         if (!found)
6817                                 intel_hdmi_init(dev, SDVOB);
6818                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
6819                                 intel_dp_init(dev, DP_B);
6820                 }
6821
6822                 if (I915_READ(SDVOC) & PORT_DETECTED)
6823                         intel_hdmi_init(dev, SDVOC);
6824
6825                 /* Shares lanes with HDMI on SDVOC */
6826                 if (I915_READ(DP_C) & DP_DETECTED)
6827                         intel_dp_init(dev, DP_C);
6828         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6829                 bool found = false;
6830
6831                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6832                         DRM_DEBUG_KMS("probing SDVOB\n");
6833                         found = intel_sdvo_init(dev, SDVOB, true);
6834                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6835                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6836                                 intel_hdmi_init(dev, SDVOB);
6837                         }
6838
6839                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6840                                 DRM_DEBUG_KMS("probing DP_B\n");
6841                                 intel_dp_init(dev, DP_B);
6842                         }
6843                 }
6844
6845                 /* Before G4X SDVOC doesn't have its own detect register */
6846
6847                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6848                         DRM_DEBUG_KMS("probing SDVOC\n");
6849                         found = intel_sdvo_init(dev, SDVOC, false);
6850                 }
6851
6852                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6853
6854                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6855                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6856                                 intel_hdmi_init(dev, SDVOC);
6857                         }
6858                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6859                                 DRM_DEBUG_KMS("probing DP_C\n");
6860                                 intel_dp_init(dev, DP_C);
6861                         }
6862                 }
6863
6864                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6865                     (I915_READ(DP_D) & DP_DETECTED)) {
6866                         DRM_DEBUG_KMS("probing DP_D\n");
6867                         intel_dp_init(dev, DP_D);
6868                 }
6869         } else if (IS_GEN2(dev))
6870                 intel_dvo_init(dev);
6871
6872         if (SUPPORTS_TV(dev))
6873                 intel_tv_init(dev);
6874
6875         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6876                 encoder->base.possible_crtcs = encoder->crtc_mask;
6877                 encoder->base.possible_clones =
6878                         intel_encoder_clones(dev, encoder->clone_mask);
6879         }
6880
6881         /* disable all the possible outputs/crtcs before entering KMS mode */
6882         drm_helper_disable_unused_functions(dev);
6883
6884         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6885                 ironlake_init_pch_refclk(dev);
6886 }
6887
6888 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6889 {
6890         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6891
6892         drm_framebuffer_cleanup(fb);
6893         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6894
6895         kfree(intel_fb);
6896 }
6897
6898 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6899                                                 struct drm_file *file,
6900                                                 unsigned int *handle)
6901 {
6902         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6903         struct drm_i915_gem_object *obj = intel_fb->obj;
6904
6905         return drm_gem_handle_create(file, &obj->base, handle);
6906 }
6907
6908 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6909         .destroy = intel_user_framebuffer_destroy,
6910         .create_handle = intel_user_framebuffer_create_handle,
6911 };
6912
6913 int intel_framebuffer_init(struct drm_device *dev,
6914                            struct intel_framebuffer *intel_fb,
6915                            struct drm_mode_fb_cmd2 *mode_cmd,
6916                            struct drm_i915_gem_object *obj)
6917 {
6918         int ret;
6919
6920         if (obj->tiling_mode == I915_TILING_Y)
6921                 return -EINVAL;
6922
6923         if (mode_cmd->pitches[0] & 63)
6924                 return -EINVAL;
6925
6926         switch (mode_cmd->pixel_format) {
6927         case DRM_FORMAT_RGB332:
6928         case DRM_FORMAT_RGB565:
6929         case DRM_FORMAT_XRGB8888:
6930         case DRM_FORMAT_XBGR8888:
6931         case DRM_FORMAT_ARGB8888:
6932         case DRM_FORMAT_XRGB2101010:
6933         case DRM_FORMAT_ARGB2101010:
6934                 /* RGB formats are common across chipsets */
6935                 break;
6936         case DRM_FORMAT_YUYV:
6937         case DRM_FORMAT_UYVY:
6938         case DRM_FORMAT_YVYU:
6939         case DRM_FORMAT_VYUY:
6940                 break;
6941         default:
6942                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6943                                 mode_cmd->pixel_format);
6944                 return -EINVAL;
6945         }
6946
6947         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6948         if (ret) {
6949                 DRM_ERROR("framebuffer init failed %d\n", ret);
6950                 return ret;
6951         }
6952
6953         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6954         intel_fb->obj = obj;
6955         return 0;
6956 }
6957
6958 static struct drm_framebuffer *
6959 intel_user_framebuffer_create(struct drm_device *dev,
6960                               struct drm_file *filp,
6961                               struct drm_mode_fb_cmd2 *mode_cmd)
6962 {
6963         struct drm_i915_gem_object *obj;
6964
6965         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6966                                                 mode_cmd->handles[0]));
6967         if (&obj->base == NULL)
6968                 return ERR_PTR(-ENOENT);
6969
6970         return intel_framebuffer_create(dev, mode_cmd, obj);
6971 }
6972
6973 static const struct drm_mode_config_funcs intel_mode_funcs = {
6974         .fb_create = intel_user_framebuffer_create,
6975         .output_poll_changed = intel_fb_output_poll_changed,
6976 };
6977
6978 /* Set up chip specific display functions */
6979 static void intel_init_display(struct drm_device *dev)
6980 {
6981         struct drm_i915_private *dev_priv = dev->dev_private;
6982
6983         /* We always want a DPMS function */
6984         if (HAS_PCH_SPLIT(dev)) {
6985                 dev_priv->display.dpms = ironlake_crtc_dpms;
6986                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6987                 dev_priv->display.off = ironlake_crtc_off;
6988                 dev_priv->display.update_plane = ironlake_update_plane;
6989         } else {
6990                 dev_priv->display.dpms = i9xx_crtc_dpms;
6991                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6992                 dev_priv->display.off = i9xx_crtc_off;
6993                 dev_priv->display.update_plane = i9xx_update_plane;
6994         }
6995
6996         /* Returns the core display clock speed */
6997         if (IS_VALLEYVIEW(dev))
6998                 dev_priv->display.get_display_clock_speed =
6999                         valleyview_get_display_clock_speed;
7000         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7001                 dev_priv->display.get_display_clock_speed =
7002                         i945_get_display_clock_speed;
7003         else if (IS_I915G(dev))
7004                 dev_priv->display.get_display_clock_speed =
7005                         i915_get_display_clock_speed;
7006         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7007                 dev_priv->display.get_display_clock_speed =
7008                         i9xx_misc_get_display_clock_speed;
7009         else if (IS_I915GM(dev))
7010                 dev_priv->display.get_display_clock_speed =
7011                         i915gm_get_display_clock_speed;
7012         else if (IS_I865G(dev))
7013                 dev_priv->display.get_display_clock_speed =
7014                         i865_get_display_clock_speed;
7015         else if (IS_I85X(dev))
7016                 dev_priv->display.get_display_clock_speed =
7017                         i855_get_display_clock_speed;
7018         else /* 852, 830 */
7019                 dev_priv->display.get_display_clock_speed =
7020                         i830_get_display_clock_speed;
7021
7022         if (HAS_PCH_SPLIT(dev)) {
7023                 if (IS_GEN5(dev)) {
7024                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7025                         dev_priv->display.write_eld = ironlake_write_eld;
7026                 } else if (IS_GEN6(dev)) {
7027                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7028                         dev_priv->display.write_eld = ironlake_write_eld;
7029                 } else if (IS_IVYBRIDGE(dev)) {
7030                         /* FIXME: detect B0+ stepping and use auto training */
7031                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7032                         dev_priv->display.write_eld = ironlake_write_eld;
7033                 } else if (IS_HASWELL(dev)) {
7034                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7035                         dev_priv->display.write_eld = ironlake_write_eld;
7036                 } else
7037                         dev_priv->display.update_wm = NULL;
7038         } else if (IS_G4X(dev)) {
7039                 dev_priv->display.write_eld = g4x_write_eld;
7040         }
7041
7042         /* Default just returns -ENODEV to indicate unsupported */
7043         dev_priv->display.queue_flip = intel_default_queue_flip;
7044
7045         switch (INTEL_INFO(dev)->gen) {
7046         case 2:
7047                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7048                 break;
7049
7050         case 3:
7051                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7052                 break;
7053
7054         case 4:
7055         case 5:
7056                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7057                 break;
7058
7059         case 6:
7060                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7061                 break;
7062         case 7:
7063                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7064                 break;
7065         }
7066 }
7067
7068 /*
7069  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7070  * resume, or other times.  This quirk makes sure that's the case for
7071  * affected systems.
7072  */
7073 static void quirk_pipea_force(struct drm_device *dev)
7074 {
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076
7077         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7078         DRM_INFO("applying pipe a force quirk\n");
7079 }
7080
7081 /*
7082  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7083  */
7084 static void quirk_ssc_force_disable(struct drm_device *dev)
7085 {
7086         struct drm_i915_private *dev_priv = dev->dev_private;
7087         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7088         DRM_INFO("applying lvds SSC disable quirk\n");
7089 }
7090
7091 /*
7092  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7093  * brightness value
7094  */
7095 static void quirk_invert_brightness(struct drm_device *dev)
7096 {
7097         struct drm_i915_private *dev_priv = dev->dev_private;
7098         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7099         DRM_INFO("applying inverted panel brightness quirk\n");
7100 }
7101
7102 struct intel_quirk {
7103         int device;
7104         int subsystem_vendor;
7105         int subsystem_device;
7106         void (*hook)(struct drm_device *dev);
7107 };
7108
7109 static struct intel_quirk intel_quirks[] = {
7110         /* HP Mini needs pipe A force quirk (LP: #322104) */
7111         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7112
7113         /* Thinkpad R31 needs pipe A force quirk */
7114         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7115         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7116         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7117
7118         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7119         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7120         /* ThinkPad X40 needs pipe A force quirk */
7121
7122         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7123         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7124
7125         /* 855 & before need to leave pipe A & dpll A up */
7126         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7127         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7128
7129         /* Lenovo U160 cannot use SSC on LVDS */
7130         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7131
7132         /* Sony Vaio Y cannot use SSC on LVDS */
7133         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7134
7135         /* Acer Aspire 5734Z must invert backlight brightness */
7136         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7137 };
7138
7139 static void intel_init_quirks(struct drm_device *dev)
7140 {
7141         struct pci_dev *d = dev->pdev;
7142         int i;
7143
7144         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7145                 struct intel_quirk *q = &intel_quirks[i];
7146
7147                 if (d->device == q->device &&
7148                     (d->subsystem_vendor == q->subsystem_vendor ||
7149                      q->subsystem_vendor == PCI_ANY_ID) &&
7150                     (d->subsystem_device == q->subsystem_device ||
7151                      q->subsystem_device == PCI_ANY_ID))
7152                         q->hook(dev);
7153         }
7154 }
7155
7156 /* Disable the VGA plane that we never use */
7157 static void i915_disable_vga(struct drm_device *dev)
7158 {
7159         struct drm_i915_private *dev_priv = dev->dev_private;
7160         u8 sr1;
7161         u32 vga_reg;
7162
7163         if (HAS_PCH_SPLIT(dev))
7164                 vga_reg = CPU_VGACNTRL;
7165         else
7166                 vga_reg = VGACNTRL;
7167
7168         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7169         outb(SR01, VGA_SR_INDEX);
7170         sr1 = inb(VGA_SR_DATA);
7171         outb(sr1 | 1<<5, VGA_SR_DATA);
7172         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7173         udelay(300);
7174
7175         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7176         POSTING_READ(vga_reg);
7177 }
7178
7179 void intel_modeset_init_hw(struct drm_device *dev)
7180 {
7181         /* We attempt to init the necessary power wells early in the initialization
7182          * time, so the subsystems that expect power to be enabled can work.
7183          */
7184         intel_init_power_wells(dev);
7185
7186         intel_prepare_ddi(dev);
7187
7188         intel_init_clock_gating(dev);
7189
7190         mutex_lock(&dev->struct_mutex);
7191         intel_enable_gt_powersave(dev);
7192         mutex_unlock(&dev->struct_mutex);
7193 }
7194
7195 void intel_modeset_init(struct drm_device *dev)
7196 {
7197         struct drm_i915_private *dev_priv = dev->dev_private;
7198         int i, ret;
7199
7200         drm_mode_config_init(dev);
7201
7202         dev->mode_config.min_width = 0;
7203         dev->mode_config.min_height = 0;
7204
7205         dev->mode_config.preferred_depth = 24;
7206         dev->mode_config.prefer_shadow = 1;
7207
7208         dev->mode_config.funcs = &intel_mode_funcs;
7209
7210         intel_init_quirks(dev);
7211
7212         intel_init_pm(dev);
7213
7214         intel_init_display(dev);
7215
7216         if (IS_GEN2(dev)) {
7217                 dev->mode_config.max_width = 2048;
7218                 dev->mode_config.max_height = 2048;
7219         } else if (IS_GEN3(dev)) {
7220                 dev->mode_config.max_width = 4096;
7221                 dev->mode_config.max_height = 4096;
7222         } else {
7223                 dev->mode_config.max_width = 8192;
7224                 dev->mode_config.max_height = 8192;
7225         }
7226         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7227
7228         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7229                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7230
7231         for (i = 0; i < dev_priv->num_pipe; i++) {
7232                 intel_crtc_init(dev, i);
7233                 ret = intel_plane_init(dev, i);
7234                 if (ret)
7235                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7236         }
7237
7238         intel_pch_pll_init(dev);
7239
7240         /* Just disable it once at startup */
7241         i915_disable_vga(dev);
7242         intel_setup_outputs(dev);
7243
7244         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7245         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7246                     (unsigned long)dev);
7247 }
7248
7249 void intel_modeset_gem_init(struct drm_device *dev)
7250 {
7251         intel_modeset_init_hw(dev);
7252
7253         intel_setup_overlay(dev);
7254 }
7255
7256 void intel_modeset_cleanup(struct drm_device *dev)
7257 {
7258         struct drm_i915_private *dev_priv = dev->dev_private;
7259         struct drm_crtc *crtc;
7260         struct intel_crtc *intel_crtc;
7261
7262         drm_kms_helper_poll_fini(dev);
7263         mutex_lock(&dev->struct_mutex);
7264
7265         intel_unregister_dsm_handler();
7266
7267
7268         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7269                 /* Skip inactive CRTCs */
7270                 if (!crtc->fb)
7271                         continue;
7272
7273                 intel_crtc = to_intel_crtc(crtc);
7274                 intel_increase_pllclock(crtc);
7275         }
7276
7277         intel_disable_fbc(dev);
7278
7279         intel_disable_gt_powersave(dev);
7280
7281         ironlake_teardown_rc6(dev);
7282
7283         if (IS_VALLEYVIEW(dev))
7284                 vlv_init_dpio(dev);
7285
7286         mutex_unlock(&dev->struct_mutex);
7287
7288         /* Disable the irq before mode object teardown, for the irq might
7289          * enqueue unpin/hotplug work. */
7290         drm_irq_uninstall(dev);
7291         cancel_work_sync(&dev_priv->hotplug_work);
7292         cancel_work_sync(&dev_priv->rps_work);
7293
7294         /* flush any delayed tasks or pending work */
7295         flush_scheduled_work();
7296
7297         /* Shut off idle work before the crtcs get freed. */
7298         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7299                 intel_crtc = to_intel_crtc(crtc);
7300                 del_timer_sync(&intel_crtc->idle_timer);
7301         }
7302         del_timer_sync(&dev_priv->idle_timer);
7303         cancel_work_sync(&dev_priv->idle_work);
7304
7305         drm_mode_config_cleanup(dev);
7306 }
7307
7308 /*
7309  * Return which encoder is currently attached for connector.
7310  */
7311 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7312 {
7313         return &intel_attached_encoder(connector)->base;
7314 }
7315
7316 void intel_connector_attach_encoder(struct intel_connector *connector,
7317                                     struct intel_encoder *encoder)
7318 {
7319         connector->encoder = encoder;
7320         drm_mode_connector_attach_encoder(&connector->base,
7321                                           &encoder->base);
7322 }
7323
7324 /*
7325  * set vga decode state - true == enable VGA decode
7326  */
7327 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7328 {
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         u16 gmch_ctrl;
7331
7332         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7333         if (state)
7334                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7335         else
7336                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7337         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7338         return 0;
7339 }
7340
7341 #ifdef CONFIG_DEBUG_FS
7342 #include <linux/seq_file.h>
7343
7344 struct intel_display_error_state {
7345         struct intel_cursor_error_state {
7346                 u32 control;
7347                 u32 position;
7348                 u32 base;
7349                 u32 size;
7350         } cursor[2];
7351
7352         struct intel_pipe_error_state {
7353                 u32 conf;
7354                 u32 source;
7355
7356                 u32 htotal;
7357                 u32 hblank;
7358                 u32 hsync;
7359                 u32 vtotal;
7360                 u32 vblank;
7361                 u32 vsync;
7362         } pipe[2];
7363
7364         struct intel_plane_error_state {
7365                 u32 control;
7366                 u32 stride;
7367                 u32 size;
7368                 u32 pos;
7369                 u32 addr;
7370                 u32 surface;
7371                 u32 tile_offset;
7372         } plane[2];
7373 };
7374
7375 struct intel_display_error_state *
7376 intel_display_capture_error_state(struct drm_device *dev)
7377 {
7378         drm_i915_private_t *dev_priv = dev->dev_private;
7379         struct intel_display_error_state *error;
7380         int i;
7381
7382         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7383         if (error == NULL)
7384                 return NULL;
7385
7386         for (i = 0; i < 2; i++) {
7387                 error->cursor[i].control = I915_READ(CURCNTR(i));
7388                 error->cursor[i].position = I915_READ(CURPOS(i));
7389                 error->cursor[i].base = I915_READ(CURBASE(i));
7390
7391                 error->plane[i].control = I915_READ(DSPCNTR(i));
7392                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7393                 error->plane[i].size = I915_READ(DSPSIZE(i));
7394                 error->plane[i].pos = I915_READ(DSPPOS(i));
7395                 error->plane[i].addr = I915_READ(DSPADDR(i));
7396                 if (INTEL_INFO(dev)->gen >= 4) {
7397                         error->plane[i].surface = I915_READ(DSPSURF(i));
7398                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7399                 }
7400
7401                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7402                 error->pipe[i].source = I915_READ(PIPESRC(i));
7403                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7404                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7405                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7406                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7407                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7408                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7409         }
7410
7411         return error;
7412 }
7413
7414 void
7415 intel_display_print_error_state(struct seq_file *m,
7416                                 struct drm_device *dev,
7417                                 struct intel_display_error_state *error)
7418 {
7419         int i;
7420
7421         for (i = 0; i < 2; i++) {
7422                 seq_printf(m, "Pipe [%d]:\n", i);
7423                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7424                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7425                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7426                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7427                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7428                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7429                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7430                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7431
7432                 seq_printf(m, "Plane [%d]:\n", i);
7433                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7434                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7435                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7436                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7437                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7438                 if (INTEL_INFO(dev)->gen >= 4) {
7439                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7440                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7441                 }
7442
7443                 seq_printf(m, "Cursor [%d]:\n", i);
7444                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7445                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7446                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7447         }
7448 }
7449 #endif