Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         if (dev_priv->info->gen >= 4)
1840                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841         else
1842                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1843 }
1844
1845 /**
1846  * intel_enable_plane - enable a display plane on a given pipe
1847  * @dev_priv: i915 private structure
1848  * @plane: plane to enable
1849  * @pipe: pipe being fed
1850  *
1851  * Enable @plane on @pipe, making sure that @pipe is running first.
1852  */
1853 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854                                enum plane plane, enum pipe pipe)
1855 {
1856         int reg;
1857         u32 val;
1858
1859         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860         assert_pipe_enabled(dev_priv, pipe);
1861
1862         reg = DSPCNTR(plane);
1863         val = I915_READ(reg);
1864         if (val & DISPLAY_PLANE_ENABLE)
1865                 return;
1866
1867         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1868         intel_flush_display_plane(dev_priv, plane);
1869         intel_wait_for_vblank(dev_priv->dev, pipe);
1870 }
1871
1872 /**
1873  * intel_disable_plane - disable a display plane
1874  * @dev_priv: i915 private structure
1875  * @plane: plane to disable
1876  * @pipe: pipe consuming the data
1877  *
1878  * Disable @plane; should be an independent operation.
1879  */
1880 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881                                 enum plane plane, enum pipe pipe)
1882 {
1883         int reg;
1884         u32 val;
1885
1886         reg = DSPCNTR(plane);
1887         val = I915_READ(reg);
1888         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889                 return;
1890
1891         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1892         intel_flush_display_plane(dev_priv, plane);
1893         intel_wait_for_vblank(dev_priv->dev, pipe);
1894 }
1895
1896 int
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898                            struct drm_i915_gem_object *obj,
1899                            struct intel_ring_buffer *pipelined)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 alignment;
1903         int ret;
1904
1905         switch (obj->tiling_mode) {
1906         case I915_TILING_NONE:
1907                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908                         alignment = 128 * 1024;
1909                 else if (INTEL_INFO(dev)->gen >= 4)
1910                         alignment = 4 * 1024;
1911                 else
1912                         alignment = 64 * 1024;
1913                 break;
1914         case I915_TILING_X:
1915                 /* pin() will align the object as required by fence */
1916                 alignment = 0;
1917                 break;
1918         case I915_TILING_Y:
1919                 /* FIXME: Is this true? */
1920                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921                 return -EINVAL;
1922         default:
1923                 BUG();
1924         }
1925
1926         dev_priv->mm.interruptible = false;
1927         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1928         if (ret)
1929                 goto err_interruptible;
1930
1931         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932          * fence, whereas 965+ only requires a fence if using
1933          * framebuffer compression.  For simplicity, we always install
1934          * a fence as the cost is not that onerous.
1935          */
1936         ret = i915_gem_object_get_fence(obj);
1937         if (ret)
1938                 goto err_unpin;
1939
1940         i915_gem_object_pin_fence(obj);
1941
1942         dev_priv->mm.interruptible = true;
1943         return 0;
1944
1945 err_unpin:
1946         i915_gem_object_unpin(obj);
1947 err_interruptible:
1948         dev_priv->mm.interruptible = true;
1949         return ret;
1950 }
1951
1952 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953 {
1954         i915_gem_object_unpin_fence(obj);
1955         i915_gem_object_unpin(obj);
1956 }
1957
1958 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959  * is assumed to be a power-of-two. */
1960 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961                                                unsigned int bpp,
1962                                                unsigned int pitch)
1963 {
1964         int tile_rows, tiles;
1965
1966         tile_rows = *y / 8;
1967         *y %= 8;
1968         tiles = *x / (512/bpp);
1969         *x %= 512/bpp;
1970
1971         return tile_rows * pitch * 8 + tiles * 4096;
1972 }
1973
1974 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975                              int x, int y)
1976 {
1977         struct drm_device *dev = crtc->dev;
1978         struct drm_i915_private *dev_priv = dev->dev_private;
1979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980         struct intel_framebuffer *intel_fb;
1981         struct drm_i915_gem_object *obj;
1982         int plane = intel_crtc->plane;
1983         unsigned long linear_offset;
1984         u32 dspcntr;
1985         u32 reg;
1986
1987         switch (plane) {
1988         case 0:
1989         case 1:
1990                 break;
1991         default:
1992                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993                 return -EINVAL;
1994         }
1995
1996         intel_fb = to_intel_framebuffer(fb);
1997         obj = intel_fb->obj;
1998
1999         reg = DSPCNTR(plane);
2000         dspcntr = I915_READ(reg);
2001         /* Mask out pixel format bits in case we change it */
2002         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2003         switch (fb->pixel_format) {
2004         case DRM_FORMAT_C8:
2005                 dspcntr |= DISPPLANE_8BPP;
2006                 break;
2007         case DRM_FORMAT_XRGB1555:
2008         case DRM_FORMAT_ARGB1555:
2009                 dspcntr |= DISPPLANE_BGRX555;
2010                 break;
2011         case DRM_FORMAT_RGB565:
2012                 dspcntr |= DISPPLANE_BGRX565;
2013                 break;
2014         case DRM_FORMAT_XRGB8888:
2015         case DRM_FORMAT_ARGB8888:
2016                 dspcntr |= DISPPLANE_BGRX888;
2017                 break;
2018         case DRM_FORMAT_XBGR8888:
2019         case DRM_FORMAT_ABGR8888:
2020                 dspcntr |= DISPPLANE_RGBX888;
2021                 break;
2022         case DRM_FORMAT_XRGB2101010:
2023         case DRM_FORMAT_ARGB2101010:
2024                 dspcntr |= DISPPLANE_BGRX101010;
2025                 break;
2026         case DRM_FORMAT_XBGR2101010:
2027         case DRM_FORMAT_ABGR2101010:
2028                 dspcntr |= DISPPLANE_RGBX101010;
2029                 break;
2030         default:
2031                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2032                 return -EINVAL;
2033         }
2034
2035         if (INTEL_INFO(dev)->gen >= 4) {
2036                 if (obj->tiling_mode != I915_TILING_NONE)
2037                         dspcntr |= DISPPLANE_TILED;
2038                 else
2039                         dspcntr &= ~DISPPLANE_TILED;
2040         }
2041
2042         I915_WRITE(reg, dspcntr);
2043
2044         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2045
2046         if (INTEL_INFO(dev)->gen >= 4) {
2047                 intel_crtc->dspaddr_offset =
2048                         intel_gen4_compute_offset_xtiled(&x, &y,
2049                                                          fb->bits_per_pixel / 8,
2050                                                          fb->pitches[0]);
2051                 linear_offset -= intel_crtc->dspaddr_offset;
2052         } else {
2053                 intel_crtc->dspaddr_offset = linear_offset;
2054         }
2055
2056         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2058         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2059         if (INTEL_INFO(dev)->gen >= 4) {
2060                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2062                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2064         } else
2065                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2066         POSTING_READ(reg);
2067
2068         return 0;
2069 }
2070
2071 static int ironlake_update_plane(struct drm_crtc *crtc,
2072                                  struct drm_framebuffer *fb, int x, int y)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077         struct intel_framebuffer *intel_fb;
2078         struct drm_i915_gem_object *obj;
2079         int plane = intel_crtc->plane;
2080         unsigned long linear_offset;
2081         u32 dspcntr;
2082         u32 reg;
2083
2084         switch (plane) {
2085         case 0:
2086         case 1:
2087         case 2:
2088                 break;
2089         default:
2090                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091                 return -EINVAL;
2092         }
2093
2094         intel_fb = to_intel_framebuffer(fb);
2095         obj = intel_fb->obj;
2096
2097         reg = DSPCNTR(plane);
2098         dspcntr = I915_READ(reg);
2099         /* Mask out pixel format bits in case we change it */
2100         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101         switch (fb->pixel_format) {
2102         case DRM_FORMAT_C8:
2103                 dspcntr |= DISPPLANE_8BPP;
2104                 break;
2105         case DRM_FORMAT_RGB565:
2106                 dspcntr |= DISPPLANE_BGRX565;
2107                 break;
2108         case DRM_FORMAT_XRGB8888:
2109         case DRM_FORMAT_ARGB8888:
2110                 dspcntr |= DISPPLANE_BGRX888;
2111                 break;
2112         case DRM_FORMAT_XBGR8888:
2113         case DRM_FORMAT_ABGR8888:
2114                 dspcntr |= DISPPLANE_RGBX888;
2115                 break;
2116         case DRM_FORMAT_XRGB2101010:
2117         case DRM_FORMAT_ARGB2101010:
2118                 dspcntr |= DISPPLANE_BGRX101010;
2119                 break;
2120         case DRM_FORMAT_XBGR2101010:
2121         case DRM_FORMAT_ABGR2101010:
2122                 dspcntr |= DISPPLANE_RGBX101010;
2123                 break;
2124         default:
2125                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2126                 return -EINVAL;
2127         }
2128
2129         if (obj->tiling_mode != I915_TILING_NONE)
2130                 dspcntr |= DISPPLANE_TILED;
2131         else
2132                 dspcntr &= ~DISPPLANE_TILED;
2133
2134         /* must disable */
2135         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137         I915_WRITE(reg, dspcntr);
2138
2139         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2140         intel_crtc->dspaddr_offset =
2141                 intel_gen4_compute_offset_xtiled(&x, &y,
2142                                                  fb->bits_per_pixel / 8,
2143                                                  fb->pitches[0]);
2144         linear_offset -= intel_crtc->dspaddr_offset;
2145
2146         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2148         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2149         I915_MODIFY_DISPBASE(DSPSURF(plane),
2150                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2151         if (IS_HASWELL(dev)) {
2152                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153         } else {
2154                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156         }
2157         POSTING_READ(reg);
2158
2159         return 0;
2160 }
2161
2162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2163 static int
2164 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165                            int x, int y, enum mode_set_atomic state)
2166 {
2167         struct drm_device *dev = crtc->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169
2170         if (dev_priv->display.disable_fbc)
2171                 dev_priv->display.disable_fbc(dev);
2172         intel_increase_pllclock(crtc);
2173
2174         return dev_priv->display.update_plane(crtc, fb, x, y);
2175 }
2176
2177 static int
2178 intel_finish_fb(struct drm_framebuffer *old_fb)
2179 {
2180         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182         bool was_interruptible = dev_priv->mm.interruptible;
2183         int ret;
2184
2185         wait_event(dev_priv->pending_flip_queue,
2186                    atomic_read(&dev_priv->mm.wedged) ||
2187                    atomic_read(&obj->pending_flip) == 0);
2188
2189         /* Big Hammer, we also need to ensure that any pending
2190          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191          * current scanout is retired before unpinning the old
2192          * framebuffer.
2193          *
2194          * This should only fail upon a hung GPU, in which case we
2195          * can safely continue.
2196          */
2197         dev_priv->mm.interruptible = false;
2198         ret = i915_gem_object_finish_gpu(obj);
2199         dev_priv->mm.interruptible = was_interruptible;
2200
2201         return ret;
2202 }
2203
2204 static int
2205 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2206                     struct drm_framebuffer *fb)
2207 {
2208         struct drm_device *dev = crtc->dev;
2209         struct drm_i915_private *dev_priv = dev->dev_private;
2210         struct drm_i915_master_private *master_priv;
2211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212         struct drm_framebuffer *old_fb;
2213         int ret;
2214
2215         /* no fb bound */
2216         if (!fb) {
2217                 DRM_ERROR("No FB bound\n");
2218                 return 0;
2219         }
2220
2221         if(intel_crtc->plane > dev_priv->num_pipe) {
2222                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2223                                 intel_crtc->plane,
2224                                 dev_priv->num_pipe);
2225                 return -EINVAL;
2226         }
2227
2228         mutex_lock(&dev->struct_mutex);
2229         ret = intel_pin_and_fence_fb_obj(dev,
2230                                          to_intel_framebuffer(fb)->obj,
2231                                          NULL);
2232         if (ret != 0) {
2233                 mutex_unlock(&dev->struct_mutex);
2234                 DRM_ERROR("pin & fence failed\n");
2235                 return ret;
2236         }
2237
2238         if (crtc->fb)
2239                 intel_finish_fb(crtc->fb);
2240
2241         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2242         if (ret) {
2243                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2244                 mutex_unlock(&dev->struct_mutex);
2245                 DRM_ERROR("failed to update base address\n");
2246                 return ret;
2247         }
2248
2249         old_fb = crtc->fb;
2250         crtc->fb = fb;
2251         crtc->x = x;
2252         crtc->y = y;
2253
2254         if (old_fb) {
2255                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2256                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2257         }
2258
2259         intel_update_fbc(dev);
2260         mutex_unlock(&dev->struct_mutex);
2261
2262         if (!dev->primary->master)
2263                 return 0;
2264
2265         master_priv = dev->primary->master->driver_priv;
2266         if (!master_priv->sarea_priv)
2267                 return 0;
2268
2269         if (intel_crtc->pipe) {
2270                 master_priv->sarea_priv->pipeB_x = x;
2271                 master_priv->sarea_priv->pipeB_y = y;
2272         } else {
2273                 master_priv->sarea_priv->pipeA_x = x;
2274                 master_priv->sarea_priv->pipeA_y = y;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2281 {
2282         struct drm_device *dev = crtc->dev;
2283         struct drm_i915_private *dev_priv = dev->dev_private;
2284         u32 dpa_ctl;
2285
2286         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2287         dpa_ctl = I915_READ(DP_A);
2288         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2289
2290         if (clock < 200000) {
2291                 u32 temp;
2292                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2293                 /* workaround for 160Mhz:
2294                    1) program 0x4600c bits 15:0 = 0x8124
2295                    2) program 0x46010 bit 0 = 1
2296                    3) program 0x46034 bit 24 = 1
2297                    4) program 0x64000 bit 14 = 1
2298                    */
2299                 temp = I915_READ(0x4600c);
2300                 temp &= 0xffff0000;
2301                 I915_WRITE(0x4600c, temp | 0x8124);
2302
2303                 temp = I915_READ(0x46010);
2304                 I915_WRITE(0x46010, temp | 1);
2305
2306                 temp = I915_READ(0x46034);
2307                 I915_WRITE(0x46034, temp | (1 << 24));
2308         } else {
2309                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2310         }
2311         I915_WRITE(DP_A, dpa_ctl);
2312
2313         POSTING_READ(DP_A);
2314         udelay(500);
2315 }
2316
2317 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2318 {
2319         struct drm_device *dev = crtc->dev;
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2322         int pipe = intel_crtc->pipe;
2323         u32 reg, temp;
2324
2325         /* enable normal train */
2326         reg = FDI_TX_CTL(pipe);
2327         temp = I915_READ(reg);
2328         if (IS_IVYBRIDGE(dev)) {
2329                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2330                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2331         } else {
2332                 temp &= ~FDI_LINK_TRAIN_NONE;
2333                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2334         }
2335         I915_WRITE(reg, temp);
2336
2337         reg = FDI_RX_CTL(pipe);
2338         temp = I915_READ(reg);
2339         if (HAS_PCH_CPT(dev)) {
2340                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2341                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2342         } else {
2343                 temp &= ~FDI_LINK_TRAIN_NONE;
2344                 temp |= FDI_LINK_TRAIN_NONE;
2345         }
2346         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2347
2348         /* wait one idle pattern time */
2349         POSTING_READ(reg);
2350         udelay(1000);
2351
2352         /* IVB wants error correction enabled */
2353         if (IS_IVYBRIDGE(dev))
2354                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2355                            FDI_FE_ERRC_ENABLE);
2356 }
2357
2358 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         u32 flags = I915_READ(SOUTH_CHICKEN1);
2362
2363         flags |= FDI_PHASE_SYNC_OVR(pipe);
2364         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2365         flags |= FDI_PHASE_SYNC_EN(pipe);
2366         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2367         POSTING_READ(SOUTH_CHICKEN1);
2368 }
2369
2370 static void ivb_modeset_global_resources(struct drm_device *dev)
2371 {
2372         struct drm_i915_private *dev_priv = dev->dev_private;
2373         struct intel_crtc *pipe_B_crtc =
2374                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2375         struct intel_crtc *pipe_C_crtc =
2376                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2377         uint32_t temp;
2378
2379         /* When everything is off disable fdi C so that we could enable fdi B
2380          * with all lanes. XXX: This misses the case where a pipe is not using
2381          * any pch resources and so doesn't need any fdi lanes. */
2382         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2383                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2384                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2385
2386                 temp = I915_READ(SOUTH_CHICKEN1);
2387                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2388                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2389                 I915_WRITE(SOUTH_CHICKEN1, temp);
2390         }
2391 }
2392
2393 /* The FDI link training functions for ILK/Ibexpeak. */
2394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2395 {
2396         struct drm_device *dev = crtc->dev;
2397         struct drm_i915_private *dev_priv = dev->dev_private;
2398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2399         int pipe = intel_crtc->pipe;
2400         int plane = intel_crtc->plane;
2401         u32 reg, temp, tries;
2402
2403         /* FDI needs bits from pipe & plane first */
2404         assert_pipe_enabled(dev_priv, pipe);
2405         assert_plane_enabled(dev_priv, plane);
2406
2407         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2408            for train result */
2409         reg = FDI_RX_IMR(pipe);
2410         temp = I915_READ(reg);
2411         temp &= ~FDI_RX_SYMBOL_LOCK;
2412         temp &= ~FDI_RX_BIT_LOCK;
2413         I915_WRITE(reg, temp);
2414         I915_READ(reg);
2415         udelay(150);
2416
2417         /* enable CPU FDI TX and PCH FDI RX */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~(7 << 19);
2421         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2422         temp &= ~FDI_LINK_TRAIN_NONE;
2423         temp |= FDI_LINK_TRAIN_PATTERN_1;
2424         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2425
2426         reg = FDI_RX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_LINK_TRAIN_NONE;
2429         temp |= FDI_LINK_TRAIN_PATTERN_1;
2430         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2431
2432         POSTING_READ(reg);
2433         udelay(150);
2434
2435         /* Ironlake workaround, enable clock pointer after FDI enable*/
2436         if (HAS_PCH_IBX(dev)) {
2437                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2438                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2439                            FDI_RX_PHASE_SYNC_POINTER_EN);
2440         }
2441
2442         reg = FDI_RX_IIR(pipe);
2443         for (tries = 0; tries < 5; tries++) {
2444                 temp = I915_READ(reg);
2445                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447                 if ((temp & FDI_RX_BIT_LOCK)) {
2448                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2449                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2450                         break;
2451                 }
2452         }
2453         if (tries == 5)
2454                 DRM_ERROR("FDI train 1 fail!\n");
2455
2456         /* Train 2 */
2457         reg = FDI_TX_CTL(pipe);
2458         temp = I915_READ(reg);
2459         temp &= ~FDI_LINK_TRAIN_NONE;
2460         temp |= FDI_LINK_TRAIN_PATTERN_2;
2461         I915_WRITE(reg, temp);
2462
2463         reg = FDI_RX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         temp &= ~FDI_LINK_TRAIN_NONE;
2466         temp |= FDI_LINK_TRAIN_PATTERN_2;
2467         I915_WRITE(reg, temp);
2468
2469         POSTING_READ(reg);
2470         udelay(150);
2471
2472         reg = FDI_RX_IIR(pipe);
2473         for (tries = 0; tries < 5; tries++) {
2474                 temp = I915_READ(reg);
2475                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477                 if (temp & FDI_RX_SYMBOL_LOCK) {
2478                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2479                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2480                         break;
2481                 }
2482         }
2483         if (tries == 5)
2484                 DRM_ERROR("FDI train 2 fail!\n");
2485
2486         DRM_DEBUG_KMS("FDI train done\n");
2487
2488 }
2489
2490 static const int snb_b_fdi_train_param[] = {
2491         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495 };
2496
2497 /* The FDI link training functions for SNB/Cougarpoint. */
2498 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499 {
2500         struct drm_device *dev = crtc->dev;
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503         int pipe = intel_crtc->pipe;
2504         u32 reg, temp, i, retry;
2505
2506         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507            for train result */
2508         reg = FDI_RX_IMR(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_RX_SYMBOL_LOCK;
2511         temp &= ~FDI_RX_BIT_LOCK;
2512         I915_WRITE(reg, temp);
2513
2514         POSTING_READ(reg);
2515         udelay(150);
2516
2517         /* enable CPU FDI TX and PCH FDI RX */
2518         reg = FDI_TX_CTL(pipe);
2519         temp = I915_READ(reg);
2520         temp &= ~(7 << 19);
2521         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2522         temp &= ~FDI_LINK_TRAIN_NONE;
2523         temp |= FDI_LINK_TRAIN_PATTERN_1;
2524         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525         /* SNB-B */
2526         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2527         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2528
2529         I915_WRITE(FDI_RX_MISC(pipe),
2530                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
2532         reg = FDI_RX_CTL(pipe);
2533         temp = I915_READ(reg);
2534         if (HAS_PCH_CPT(dev)) {
2535                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537         } else {
2538                 temp &= ~FDI_LINK_TRAIN_NONE;
2539                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540         }
2541         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543         POSTING_READ(reg);
2544         udelay(150);
2545
2546         if (HAS_PCH_CPT(dev))
2547                 cpt_phase_pointer_enable(dev, pipe);
2548
2549         for (i = 0; i < 4; i++) {
2550                 reg = FDI_TX_CTL(pipe);
2551                 temp = I915_READ(reg);
2552                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553                 temp |= snb_b_fdi_train_param[i];
2554                 I915_WRITE(reg, temp);
2555
2556                 POSTING_READ(reg);
2557                 udelay(500);
2558
2559                 for (retry = 0; retry < 5; retry++) {
2560                         reg = FDI_RX_IIR(pipe);
2561                         temp = I915_READ(reg);
2562                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2563                         if (temp & FDI_RX_BIT_LOCK) {
2564                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2565                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2566                                 break;
2567                         }
2568                         udelay(50);
2569                 }
2570                 if (retry < 5)
2571                         break;
2572         }
2573         if (i == 4)
2574                 DRM_ERROR("FDI train 1 fail!\n");
2575
2576         /* Train 2 */
2577         reg = FDI_TX_CTL(pipe);
2578         temp = I915_READ(reg);
2579         temp &= ~FDI_LINK_TRAIN_NONE;
2580         temp |= FDI_LINK_TRAIN_PATTERN_2;
2581         if (IS_GEN6(dev)) {
2582                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583                 /* SNB-B */
2584                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         }
2586         I915_WRITE(reg, temp);
2587
2588         reg = FDI_RX_CTL(pipe);
2589         temp = I915_READ(reg);
2590         if (HAS_PCH_CPT(dev)) {
2591                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2592                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2593         } else {
2594                 temp &= ~FDI_LINK_TRAIN_NONE;
2595                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2596         }
2597         I915_WRITE(reg, temp);
2598
2599         POSTING_READ(reg);
2600         udelay(150);
2601
2602         for (i = 0; i < 4; i++) {
2603                 reg = FDI_TX_CTL(pipe);
2604                 temp = I915_READ(reg);
2605                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2606                 temp |= snb_b_fdi_train_param[i];
2607                 I915_WRITE(reg, temp);
2608
2609                 POSTING_READ(reg);
2610                 udelay(500);
2611
2612                 for (retry = 0; retry < 5; retry++) {
2613                         reg = FDI_RX_IIR(pipe);
2614                         temp = I915_READ(reg);
2615                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2616                         if (temp & FDI_RX_SYMBOL_LOCK) {
2617                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2618                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2619                                 break;
2620                         }
2621                         udelay(50);
2622                 }
2623                 if (retry < 5)
2624                         break;
2625         }
2626         if (i == 4)
2627                 DRM_ERROR("FDI train 2 fail!\n");
2628
2629         DRM_DEBUG_KMS("FDI train done.\n");
2630 }
2631
2632 /* Manual link training for Ivy Bridge A0 parts */
2633 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634 {
2635         struct drm_device *dev = crtc->dev;
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638         int pipe = intel_crtc->pipe;
2639         u32 reg, temp, i;
2640
2641         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642            for train result */
2643         reg = FDI_RX_IMR(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_RX_SYMBOL_LOCK;
2646         temp &= ~FDI_RX_BIT_LOCK;
2647         I915_WRITE(reg, temp);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2653                       I915_READ(FDI_RX_IIR(pipe)));
2654
2655         /* enable CPU FDI TX and PCH FDI RX */
2656         reg = FDI_TX_CTL(pipe);
2657         temp = I915_READ(reg);
2658         temp &= ~(7 << 19);
2659         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2660         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2661         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2662         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2664         temp |= FDI_COMPOSITE_SYNC;
2665         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2666
2667         I915_WRITE(FDI_RX_MISC(pipe),
2668                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2669
2670         reg = FDI_RX_CTL(pipe);
2671         temp = I915_READ(reg);
2672         temp &= ~FDI_LINK_TRAIN_AUTO;
2673         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2674         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2675         temp |= FDI_COMPOSITE_SYNC;
2676         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2677
2678         POSTING_READ(reg);
2679         udelay(150);
2680
2681         if (HAS_PCH_CPT(dev))
2682                 cpt_phase_pointer_enable(dev, pipe);
2683
2684         for (i = 0; i < 4; i++) {
2685                 reg = FDI_TX_CTL(pipe);
2686                 temp = I915_READ(reg);
2687                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688                 temp |= snb_b_fdi_train_param[i];
2689                 I915_WRITE(reg, temp);
2690
2691                 POSTING_READ(reg);
2692                 udelay(500);
2693
2694                 reg = FDI_RX_IIR(pipe);
2695                 temp = I915_READ(reg);
2696                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697
2698                 if (temp & FDI_RX_BIT_LOCK ||
2699                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2700                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2701                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2702                         break;
2703                 }
2704         }
2705         if (i == 4)
2706                 DRM_ERROR("FDI train 1 fail!\n");
2707
2708         /* Train 2 */
2709         reg = FDI_TX_CTL(pipe);
2710         temp = I915_READ(reg);
2711         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2712         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2713         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2714         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2715         I915_WRITE(reg, temp);
2716
2717         reg = FDI_RX_CTL(pipe);
2718         temp = I915_READ(reg);
2719         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2720         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2721         I915_WRITE(reg, temp);
2722
2723         POSTING_READ(reg);
2724         udelay(150);
2725
2726         for (i = 0; i < 4; i++) {
2727                 reg = FDI_TX_CTL(pipe);
2728                 temp = I915_READ(reg);
2729                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2730                 temp |= snb_b_fdi_train_param[i];
2731                 I915_WRITE(reg, temp);
2732
2733                 POSTING_READ(reg);
2734                 udelay(500);
2735
2736                 reg = FDI_RX_IIR(pipe);
2737                 temp = I915_READ(reg);
2738                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2739
2740                 if (temp & FDI_RX_SYMBOL_LOCK) {
2741                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2743                         break;
2744                 }
2745         }
2746         if (i == 4)
2747                 DRM_ERROR("FDI train 2 fail!\n");
2748
2749         DRM_DEBUG_KMS("FDI train done.\n");
2750 }
2751
2752 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2753 {
2754         struct drm_device *dev = intel_crtc->base.dev;
2755         struct drm_i915_private *dev_priv = dev->dev_private;
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759
2760         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2761         reg = FDI_RX_CTL(pipe);
2762         temp = I915_READ(reg);
2763         temp &= ~((0x7 << 19) | (0x7 << 16));
2764         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2765         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2766         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2767
2768         POSTING_READ(reg);
2769         udelay(200);
2770
2771         /* Switch from Rawclk to PCDclk */
2772         temp = I915_READ(reg);
2773         I915_WRITE(reg, temp | FDI_PCDCLK);
2774
2775         POSTING_READ(reg);
2776         udelay(200);
2777
2778         /* On Haswell, the PLL configuration for ports and pipes is handled
2779          * separately, as part of DDI setup */
2780         if (!IS_HASWELL(dev)) {
2781                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2782                 reg = FDI_TX_CTL(pipe);
2783                 temp = I915_READ(reg);
2784                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2785                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2786
2787                         POSTING_READ(reg);
2788                         udelay(100);
2789                 }
2790         }
2791 }
2792
2793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794 {
2795         struct drm_device *dev = intel_crtc->base.dev;
2796         struct drm_i915_private *dev_priv = dev->dev_private;
2797         int pipe = intel_crtc->pipe;
2798         u32 reg, temp;
2799
2800         /* Switch from PCDclk to Rawclk */
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805         /* Disable CPU FDI TX PLL */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810         POSTING_READ(reg);
2811         udelay(100);
2812
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817         /* Wait for the clocks to turn off. */
2818         POSTING_READ(reg);
2819         udelay(100);
2820 }
2821
2822 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2823 {
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         u32 flags = I915_READ(SOUTH_CHICKEN1);
2826
2827         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2828         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2829         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2830         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2831         POSTING_READ(SOUTH_CHICKEN1);
2832 }
2833 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2834 {
2835         struct drm_device *dev = crtc->dev;
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2838         int pipe = intel_crtc->pipe;
2839         u32 reg, temp;
2840
2841         /* disable CPU FDI tx and PCH FDI rx */
2842         reg = FDI_TX_CTL(pipe);
2843         temp = I915_READ(reg);
2844         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2845         POSTING_READ(reg);
2846
2847         reg = FDI_RX_CTL(pipe);
2848         temp = I915_READ(reg);
2849         temp &= ~(0x7 << 16);
2850         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2851         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2852
2853         POSTING_READ(reg);
2854         udelay(100);
2855
2856         /* Ironlake workaround, disable clock pointer after downing FDI */
2857         if (HAS_PCH_IBX(dev)) {
2858                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2859                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2860                            I915_READ(FDI_RX_CHICKEN(pipe) &
2861                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2862         } else if (HAS_PCH_CPT(dev)) {
2863                 cpt_phase_pointer_disable(dev, pipe);
2864         }
2865
2866         /* still set train pattern 1 */
2867         reg = FDI_TX_CTL(pipe);
2868         temp = I915_READ(reg);
2869         temp &= ~FDI_LINK_TRAIN_NONE;
2870         temp |= FDI_LINK_TRAIN_PATTERN_1;
2871         I915_WRITE(reg, temp);
2872
2873         reg = FDI_RX_CTL(pipe);
2874         temp = I915_READ(reg);
2875         if (HAS_PCH_CPT(dev)) {
2876                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2877                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2878         } else {
2879                 temp &= ~FDI_LINK_TRAIN_NONE;
2880                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2881         }
2882         /* BPC in FDI rx is consistent with that in PIPECONF */
2883         temp &= ~(0x07 << 16);
2884         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2885         I915_WRITE(reg, temp);
2886
2887         POSTING_READ(reg);
2888         udelay(100);
2889 }
2890
2891 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2892 {
2893         struct drm_device *dev = crtc->dev;
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         unsigned long flags;
2896         bool pending;
2897
2898         if (atomic_read(&dev_priv->mm.wedged))
2899                 return false;
2900
2901         spin_lock_irqsave(&dev->event_lock, flags);
2902         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2903         spin_unlock_irqrestore(&dev->event_lock, flags);
2904
2905         return pending;
2906 }
2907
2908 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2909 {
2910         struct drm_device *dev = crtc->dev;
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912
2913         if (crtc->fb == NULL)
2914                 return;
2915
2916         wait_event(dev_priv->pending_flip_queue,
2917                    !intel_crtc_has_pending_flip(crtc));
2918
2919         mutex_lock(&dev->struct_mutex);
2920         intel_finish_fb(crtc->fb);
2921         mutex_unlock(&dev->struct_mutex);
2922 }
2923
2924 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2925 {
2926         struct drm_device *dev = crtc->dev;
2927         struct intel_encoder *intel_encoder;
2928
2929         /*
2930          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2931          * must be driven by its own crtc; no sharing is possible.
2932          */
2933         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2934                 switch (intel_encoder->type) {
2935                 case INTEL_OUTPUT_EDP:
2936                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2937                                 return false;
2938                         continue;
2939                 }
2940         }
2941
2942         return true;
2943 }
2944
2945 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2946 {
2947         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2948 }
2949
2950 /* Program iCLKIP clock to the desired frequency */
2951 static void lpt_program_iclkip(struct drm_crtc *crtc)
2952 {
2953         struct drm_device *dev = crtc->dev;
2954         struct drm_i915_private *dev_priv = dev->dev_private;
2955         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2956         u32 temp;
2957
2958         /* It is necessary to ungate the pixclk gate prior to programming
2959          * the divisors, and gate it back when it is done.
2960          */
2961         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2962
2963         /* Disable SSCCTL */
2964         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2965                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2966                                         SBI_SSCCTL_DISABLE);
2967
2968         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2969         if (crtc->mode.clock == 20000) {
2970                 auxdiv = 1;
2971                 divsel = 0x41;
2972                 phaseinc = 0x20;
2973         } else {
2974                 /* The iCLK virtual clock root frequency is in MHz,
2975                  * but the crtc->mode.clock in in KHz. To get the divisors,
2976                  * it is necessary to divide one by another, so we
2977                  * convert the virtual clock precision to KHz here for higher
2978                  * precision.
2979                  */
2980                 u32 iclk_virtual_root_freq = 172800 * 1000;
2981                 u32 iclk_pi_range = 64;
2982                 u32 desired_divisor, msb_divisor_value, pi_value;
2983
2984                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2985                 msb_divisor_value = desired_divisor / iclk_pi_range;
2986                 pi_value = desired_divisor % iclk_pi_range;
2987
2988                 auxdiv = 0;
2989                 divsel = msb_divisor_value - 2;
2990                 phaseinc = pi_value;
2991         }
2992
2993         /* This should not happen with any sane values */
2994         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2995                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2996         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2997                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2998
2999         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3000                         crtc->mode.clock,
3001                         auxdiv,
3002                         divsel,
3003                         phasedir,
3004                         phaseinc);
3005
3006         /* Program SSCDIVINTPHASE6 */
3007         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3008         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3009         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3010         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3011         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3012         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3013         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3014
3015         intel_sbi_write(dev_priv,
3016                         SBI_SSCDIVINTPHASE6,
3017                         temp);
3018
3019         /* Program SSCAUXDIV */
3020         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3021         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3022         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3023         intel_sbi_write(dev_priv,
3024                         SBI_SSCAUXDIV6,
3025                         temp);
3026
3027
3028         /* Enable modulator and associated divider */
3029         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3030         temp &= ~SBI_SSCCTL_DISABLE;
3031         intel_sbi_write(dev_priv,
3032                         SBI_SSCCTL6,
3033                         temp);
3034
3035         /* Wait for initialization time */
3036         udelay(24);
3037
3038         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3039 }
3040
3041 /*
3042  * Enable PCH resources required for PCH ports:
3043  *   - PCH PLLs
3044  *   - FDI training & RX/TX
3045  *   - update transcoder timings
3046  *   - DP transcoding bits
3047  *   - transcoder
3048  */
3049 static void ironlake_pch_enable(struct drm_crtc *crtc)
3050 {
3051         struct drm_device *dev = crtc->dev;
3052         struct drm_i915_private *dev_priv = dev->dev_private;
3053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054         int pipe = intel_crtc->pipe;
3055         u32 reg, temp;
3056
3057         assert_transcoder_disabled(dev_priv, pipe);
3058
3059         /* Write the TU size bits before fdi link training, so that error
3060          * detection works. */
3061         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3062                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3063
3064         /* For PCH output, training FDI link */
3065         dev_priv->display.fdi_link_train(crtc);
3066
3067         /* XXX: pch pll's can be enabled any time before we enable the PCH
3068          * transcoder, and we actually should do this to not upset any PCH
3069          * transcoder that already use the clock when we share it.
3070          *
3071          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3072          * unconditionally resets the pll - we need that to have the right LVDS
3073          * enable sequence. */
3074         intel_enable_pch_pll(intel_crtc);
3075
3076         if (HAS_PCH_LPT(dev)) {
3077                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3078                 lpt_program_iclkip(crtc);
3079         } else if (HAS_PCH_CPT(dev)) {
3080                 u32 sel;
3081
3082                 temp = I915_READ(PCH_DPLL_SEL);
3083                 switch (pipe) {
3084                 default:
3085                 case 0:
3086                         temp |= TRANSA_DPLL_ENABLE;
3087                         sel = TRANSA_DPLLB_SEL;
3088                         break;
3089                 case 1:
3090                         temp |= TRANSB_DPLL_ENABLE;
3091                         sel = TRANSB_DPLLB_SEL;
3092                         break;
3093                 case 2:
3094                         temp |= TRANSC_DPLL_ENABLE;
3095                         sel = TRANSC_DPLLB_SEL;
3096                         break;
3097                 }
3098                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3099                         temp |= sel;
3100                 else
3101                         temp &= ~sel;
3102                 I915_WRITE(PCH_DPLL_SEL, temp);
3103         }
3104
3105         /* set transcoder timing, panel must allow it */
3106         assert_panel_unlocked(dev_priv, pipe);
3107         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3108         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3109         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3110
3111         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3112         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3113         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3114         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3115
3116         if (!IS_HASWELL(dev))
3117                 intel_fdi_normal_train(crtc);
3118
3119         /* For PCH DP, enable TRANS_DP_CTL */
3120         if (HAS_PCH_CPT(dev) &&
3121             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3122              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3123                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3124                 reg = TRANS_DP_CTL(pipe);
3125                 temp = I915_READ(reg);
3126                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3127                           TRANS_DP_SYNC_MASK |
3128                           TRANS_DP_BPC_MASK);
3129                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3130                          TRANS_DP_ENH_FRAMING);
3131                 temp |= bpc << 9; /* same format but at 11:9 */
3132
3133                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3134                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3135                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3136                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3137
3138                 switch (intel_trans_dp_port_sel(crtc)) {
3139                 case PCH_DP_B:
3140                         temp |= TRANS_DP_PORT_SEL_B;
3141                         break;
3142                 case PCH_DP_C:
3143                         temp |= TRANS_DP_PORT_SEL_C;
3144                         break;
3145                 case PCH_DP_D:
3146                         temp |= TRANS_DP_PORT_SEL_D;
3147                         break;
3148                 default:
3149                         BUG();
3150                 }
3151
3152                 I915_WRITE(reg, temp);
3153         }
3154
3155         intel_enable_transcoder(dev_priv, pipe);
3156 }
3157
3158 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3159 {
3160         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3161
3162         if (pll == NULL)
3163                 return;
3164
3165         if (pll->refcount == 0) {
3166                 WARN(1, "bad PCH PLL refcount\n");
3167                 return;
3168         }
3169
3170         --pll->refcount;
3171         intel_crtc->pch_pll = NULL;
3172 }
3173
3174 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3175 {
3176         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3177         struct intel_pch_pll *pll;
3178         int i;
3179
3180         pll = intel_crtc->pch_pll;
3181         if (pll) {
3182                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3183                               intel_crtc->base.base.id, pll->pll_reg);
3184                 goto prepare;
3185         }
3186
3187         if (HAS_PCH_IBX(dev_priv->dev)) {
3188                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3189                 i = intel_crtc->pipe;
3190                 pll = &dev_priv->pch_plls[i];
3191
3192                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3193                               intel_crtc->base.base.id, pll->pll_reg);
3194
3195                 goto found;
3196         }
3197
3198         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3199                 pll = &dev_priv->pch_plls[i];
3200
3201                 /* Only want to check enabled timings first */
3202                 if (pll->refcount == 0)
3203                         continue;
3204
3205                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3206                     fp == I915_READ(pll->fp0_reg)) {
3207                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3208                                       intel_crtc->base.base.id,
3209                                       pll->pll_reg, pll->refcount, pll->active);
3210
3211                         goto found;
3212                 }
3213         }
3214
3215         /* Ok no matching timings, maybe there's a free one? */
3216         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3217                 pll = &dev_priv->pch_plls[i];
3218                 if (pll->refcount == 0) {
3219                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3220                                       intel_crtc->base.base.id, pll->pll_reg);
3221                         goto found;
3222                 }
3223         }
3224
3225         return NULL;
3226
3227 found:
3228         intel_crtc->pch_pll = pll;
3229         pll->refcount++;
3230         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3231 prepare: /* separate function? */
3232         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3233
3234         /* Wait for the clocks to stabilize before rewriting the regs */
3235         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3236         POSTING_READ(pll->pll_reg);
3237         udelay(150);
3238
3239         I915_WRITE(pll->fp0_reg, fp);
3240         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3241         pll->on = false;
3242         return pll;
3243 }
3244
3245 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3246 {
3247         struct drm_i915_private *dev_priv = dev->dev_private;
3248         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3249         u32 temp;
3250
3251         temp = I915_READ(dslreg);
3252         udelay(500);
3253         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3254                 /* Without this, mode sets may fail silently on FDI */
3255                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3256                 udelay(250);
3257                 I915_WRITE(tc2reg, 0);
3258                 if (wait_for(I915_READ(dslreg) != temp, 5))
3259                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3260         }
3261 }
3262
3263 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3264 {
3265         struct drm_device *dev = crtc->dev;
3266         struct drm_i915_private *dev_priv = dev->dev_private;
3267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3268         struct intel_encoder *encoder;
3269         int pipe = intel_crtc->pipe;
3270         int plane = intel_crtc->plane;
3271         u32 temp;
3272         bool is_pch_port;
3273
3274         WARN_ON(!crtc->enabled);
3275
3276         if (intel_crtc->active)
3277                 return;
3278
3279         intel_crtc->active = true;
3280         intel_update_watermarks(dev);
3281
3282         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3283                 temp = I915_READ(PCH_LVDS);
3284                 if ((temp & LVDS_PORT_EN) == 0)
3285                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3286         }
3287
3288         is_pch_port = ironlake_crtc_driving_pch(crtc);
3289
3290         if (is_pch_port) {
3291                 /* Note: FDI PLL enabling _must_ be done before we enable the
3292                  * cpu pipes, hence this is separate from all the other fdi/pch
3293                  * enabling. */
3294                 ironlake_fdi_pll_enable(intel_crtc);
3295         } else {
3296                 assert_fdi_tx_disabled(dev_priv, pipe);
3297                 assert_fdi_rx_disabled(dev_priv, pipe);
3298         }
3299
3300         for_each_encoder_on_crtc(dev, crtc, encoder)
3301                 if (encoder->pre_enable)
3302                         encoder->pre_enable(encoder);
3303
3304         /* Enable panel fitting for LVDS */
3305         if (dev_priv->pch_pf_size &&
3306             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3307                 /* Force use of hard-coded filter coefficients
3308                  * as some pre-programmed values are broken,
3309                  * e.g. x201.
3310                  */
3311                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3312                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3313                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3314         }
3315
3316         /*
3317          * On ILK+ LUT must be loaded before the pipe is running but with
3318          * clocks enabled
3319          */
3320         intel_crtc_load_lut(crtc);
3321
3322         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3323         intel_enable_plane(dev_priv, plane, pipe);
3324
3325         if (is_pch_port)
3326                 ironlake_pch_enable(crtc);
3327
3328         mutex_lock(&dev->struct_mutex);
3329         intel_update_fbc(dev);
3330         mutex_unlock(&dev->struct_mutex);
3331
3332         intel_crtc_update_cursor(crtc, true);
3333
3334         for_each_encoder_on_crtc(dev, crtc, encoder)
3335                 encoder->enable(encoder);
3336
3337         if (HAS_PCH_CPT(dev))
3338                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3339
3340         /*
3341          * There seems to be a race in PCH platform hw (at least on some
3342          * outputs) where an enabled pipe still completes any pageflip right
3343          * away (as if the pipe is off) instead of waiting for vblank. As soon
3344          * as the first vblank happend, everything works as expected. Hence just
3345          * wait for one vblank before returning to avoid strange things
3346          * happening.
3347          */
3348         intel_wait_for_vblank(dev, intel_crtc->pipe);
3349 }
3350
3351 static void haswell_crtc_enable(struct drm_crtc *crtc)
3352 {
3353         struct drm_device *dev = crtc->dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356         struct intel_encoder *encoder;
3357         int pipe = intel_crtc->pipe;
3358         int plane = intel_crtc->plane;
3359         bool is_pch_port;
3360
3361         WARN_ON(!crtc->enabled);
3362
3363         if (intel_crtc->active)
3364                 return;
3365
3366         intel_crtc->active = true;
3367         intel_update_watermarks(dev);
3368
3369         is_pch_port = haswell_crtc_driving_pch(crtc);
3370
3371         if (is_pch_port)
3372                 ironlake_fdi_pll_enable(intel_crtc);
3373
3374         for_each_encoder_on_crtc(dev, crtc, encoder)
3375                 if (encoder->pre_enable)
3376                         encoder->pre_enable(encoder);
3377
3378         intel_ddi_enable_pipe_clock(intel_crtc);
3379
3380         /* Enable panel fitting for eDP */
3381         if (dev_priv->pch_pf_size && HAS_eDP) {
3382                 /* Force use of hard-coded filter coefficients
3383                  * as some pre-programmed values are broken,
3384                  * e.g. x201.
3385                  */
3386                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3387                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3388                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3389         }
3390
3391         /*
3392          * On ILK+ LUT must be loaded before the pipe is running but with
3393          * clocks enabled
3394          */
3395         intel_crtc_load_lut(crtc);
3396
3397         intel_ddi_set_pipe_settings(crtc);
3398         intel_ddi_enable_pipe_func(crtc);
3399
3400         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3401         intel_enable_plane(dev_priv, plane, pipe);
3402
3403         if (is_pch_port)
3404                 ironlake_pch_enable(crtc);
3405
3406         mutex_lock(&dev->struct_mutex);
3407         intel_update_fbc(dev);
3408         mutex_unlock(&dev->struct_mutex);
3409
3410         intel_crtc_update_cursor(crtc, true);
3411
3412         for_each_encoder_on_crtc(dev, crtc, encoder)
3413                 encoder->enable(encoder);
3414
3415         /*
3416          * There seems to be a race in PCH platform hw (at least on some
3417          * outputs) where an enabled pipe still completes any pageflip right
3418          * away (as if the pipe is off) instead of waiting for vblank. As soon
3419          * as the first vblank happend, everything works as expected. Hence just
3420          * wait for one vblank before returning to avoid strange things
3421          * happening.
3422          */
3423         intel_wait_for_vblank(dev, intel_crtc->pipe);
3424 }
3425
3426 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3427 {
3428         struct drm_device *dev = crtc->dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431         struct intel_encoder *encoder;
3432         int pipe = intel_crtc->pipe;
3433         int plane = intel_crtc->plane;
3434         u32 reg, temp;
3435
3436
3437         if (!intel_crtc->active)
3438                 return;
3439
3440         for_each_encoder_on_crtc(dev, crtc, encoder)
3441                 encoder->disable(encoder);
3442
3443         intel_crtc_wait_for_pending_flips(crtc);
3444         drm_vblank_off(dev, pipe);
3445         intel_crtc_update_cursor(crtc, false);
3446
3447         intel_disable_plane(dev_priv, plane, pipe);
3448
3449         if (dev_priv->cfb_plane == plane)
3450                 intel_disable_fbc(dev);
3451
3452         intel_disable_pipe(dev_priv, pipe);
3453
3454         /* Disable PF */
3455         I915_WRITE(PF_CTL(pipe), 0);
3456         I915_WRITE(PF_WIN_SZ(pipe), 0);
3457
3458         for_each_encoder_on_crtc(dev, crtc, encoder)
3459                 if (encoder->post_disable)
3460                         encoder->post_disable(encoder);
3461
3462         ironlake_fdi_disable(crtc);
3463
3464         intel_disable_transcoder(dev_priv, pipe);
3465
3466         if (HAS_PCH_CPT(dev)) {
3467                 /* disable TRANS_DP_CTL */
3468                 reg = TRANS_DP_CTL(pipe);
3469                 temp = I915_READ(reg);
3470                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3471                 temp |= TRANS_DP_PORT_SEL_NONE;
3472                 I915_WRITE(reg, temp);
3473
3474                 /* disable DPLL_SEL */
3475                 temp = I915_READ(PCH_DPLL_SEL);
3476                 switch (pipe) {
3477                 case 0:
3478                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3479                         break;
3480                 case 1:
3481                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3482                         break;
3483                 case 2:
3484                         /* C shares PLL A or B */
3485                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3486                         break;
3487                 default:
3488                         BUG(); /* wtf */
3489                 }
3490                 I915_WRITE(PCH_DPLL_SEL, temp);
3491         }
3492
3493         /* disable PCH DPLL */
3494         intel_disable_pch_pll(intel_crtc);
3495
3496         ironlake_fdi_pll_disable(intel_crtc);
3497
3498         intel_crtc->active = false;
3499         intel_update_watermarks(dev);
3500
3501         mutex_lock(&dev->struct_mutex);
3502         intel_update_fbc(dev);
3503         mutex_unlock(&dev->struct_mutex);
3504 }
3505
3506 static void haswell_crtc_disable(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         struct intel_encoder *encoder;
3512         int pipe = intel_crtc->pipe;
3513         int plane = intel_crtc->plane;
3514         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3515         bool is_pch_port;
3516
3517         if (!intel_crtc->active)
3518                 return;
3519
3520         is_pch_port = haswell_crtc_driving_pch(crtc);
3521
3522         for_each_encoder_on_crtc(dev, crtc, encoder)
3523                 encoder->disable(encoder);
3524
3525         intel_crtc_wait_for_pending_flips(crtc);
3526         drm_vblank_off(dev, pipe);
3527         intel_crtc_update_cursor(crtc, false);
3528
3529         intel_disable_plane(dev_priv, plane, pipe);
3530
3531         if (dev_priv->cfb_plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         intel_disable_pipe(dev_priv, pipe);
3535
3536         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3537
3538         /* Disable PF */
3539         I915_WRITE(PF_CTL(pipe), 0);
3540         I915_WRITE(PF_WIN_SZ(pipe), 0);
3541
3542         intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         if (is_pch_port) {
3549                 ironlake_fdi_disable(crtc);
3550                 intel_disable_transcoder(dev_priv, pipe);
3551                 intel_disable_pch_pll(intel_crtc);
3552                 ironlake_fdi_pll_disable(intel_crtc);
3553         }
3554
3555         intel_crtc->active = false;
3556         intel_update_watermarks(dev);
3557
3558         mutex_lock(&dev->struct_mutex);
3559         intel_update_fbc(dev);
3560         mutex_unlock(&dev->struct_mutex);
3561 }
3562
3563 static void ironlake_crtc_off(struct drm_crtc *crtc)
3564 {
3565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566         intel_put_pch_pll(intel_crtc);
3567 }
3568
3569 static void haswell_crtc_off(struct drm_crtc *crtc)
3570 {
3571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572
3573         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3574          * start using it. */
3575         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3576
3577         intel_ddi_put_crtc_pll(crtc);
3578 }
3579
3580 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3581 {
3582         if (!enable && intel_crtc->overlay) {
3583                 struct drm_device *dev = intel_crtc->base.dev;
3584                 struct drm_i915_private *dev_priv = dev->dev_private;
3585
3586                 mutex_lock(&dev->struct_mutex);
3587                 dev_priv->mm.interruptible = false;
3588                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3589                 dev_priv->mm.interruptible = true;
3590                 mutex_unlock(&dev->struct_mutex);
3591         }
3592
3593         /* Let userspace switch the overlay on again. In most cases userspace
3594          * has to recompute where to put it anyway.
3595          */
3596 }
3597
3598 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3599 {
3600         struct drm_device *dev = crtc->dev;
3601         struct drm_i915_private *dev_priv = dev->dev_private;
3602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603         struct intel_encoder *encoder;
3604         int pipe = intel_crtc->pipe;
3605         int plane = intel_crtc->plane;
3606
3607         WARN_ON(!crtc->enabled);
3608
3609         if (intel_crtc->active)
3610                 return;
3611
3612         intel_crtc->active = true;
3613         intel_update_watermarks(dev);
3614
3615         intel_enable_pll(dev_priv, pipe);
3616         intel_enable_pipe(dev_priv, pipe, false);
3617         intel_enable_plane(dev_priv, plane, pipe);
3618
3619         intel_crtc_load_lut(crtc);
3620         intel_update_fbc(dev);
3621
3622         /* Give the overlay scaler a chance to enable if it's on this pipe */
3623         intel_crtc_dpms_overlay(intel_crtc, true);
3624         intel_crtc_update_cursor(crtc, true);
3625
3626         for_each_encoder_on_crtc(dev, crtc, encoder)
3627                 encoder->enable(encoder);
3628 }
3629
3630 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3631 {
3632         struct drm_device *dev = crtc->dev;
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635         struct intel_encoder *encoder;
3636         int pipe = intel_crtc->pipe;
3637         int plane = intel_crtc->plane;
3638
3639
3640         if (!intel_crtc->active)
3641                 return;
3642
3643         for_each_encoder_on_crtc(dev, crtc, encoder)
3644                 encoder->disable(encoder);
3645
3646         /* Give the overlay scaler a chance to disable if it's on this pipe */
3647         intel_crtc_wait_for_pending_flips(crtc);
3648         drm_vblank_off(dev, pipe);
3649         intel_crtc_dpms_overlay(intel_crtc, false);
3650         intel_crtc_update_cursor(crtc, false);
3651
3652         if (dev_priv->cfb_plane == plane)
3653                 intel_disable_fbc(dev);
3654
3655         intel_disable_plane(dev_priv, plane, pipe);
3656         intel_disable_pipe(dev_priv, pipe);
3657         intel_disable_pll(dev_priv, pipe);
3658
3659         intel_crtc->active = false;
3660         intel_update_fbc(dev);
3661         intel_update_watermarks(dev);
3662 }
3663
3664 static void i9xx_crtc_off(struct drm_crtc *crtc)
3665 {
3666 }
3667
3668 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3669                                     bool enabled)
3670 {
3671         struct drm_device *dev = crtc->dev;
3672         struct drm_i915_master_private *master_priv;
3673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3674         int pipe = intel_crtc->pipe;
3675
3676         if (!dev->primary->master)
3677                 return;
3678
3679         master_priv = dev->primary->master->driver_priv;
3680         if (!master_priv->sarea_priv)
3681                 return;
3682
3683         switch (pipe) {
3684         case 0:
3685                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3686                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3687                 break;
3688         case 1:
3689                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3690                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3691                 break;
3692         default:
3693                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3694                 break;
3695         }
3696 }
3697
3698 /**
3699  * Sets the power management mode of the pipe and plane.
3700  */
3701 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3702 {
3703         struct drm_device *dev = crtc->dev;
3704         struct drm_i915_private *dev_priv = dev->dev_private;
3705         struct intel_encoder *intel_encoder;
3706         bool enable = false;
3707
3708         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3709                 enable |= intel_encoder->connectors_active;
3710
3711         if (enable)
3712                 dev_priv->display.crtc_enable(crtc);
3713         else
3714                 dev_priv->display.crtc_disable(crtc);
3715
3716         intel_crtc_update_sarea(crtc, enable);
3717 }
3718
3719 static void intel_crtc_noop(struct drm_crtc *crtc)
3720 {
3721 }
3722
3723 static void intel_crtc_disable(struct drm_crtc *crtc)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_connector *connector;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728
3729         /* crtc should still be enabled when we disable it. */
3730         WARN_ON(!crtc->enabled);
3731
3732         dev_priv->display.crtc_disable(crtc);
3733         intel_crtc_update_sarea(crtc, false);
3734         dev_priv->display.off(crtc);
3735
3736         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3737         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3738
3739         if (crtc->fb) {
3740                 mutex_lock(&dev->struct_mutex);
3741                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3742                 mutex_unlock(&dev->struct_mutex);
3743                 crtc->fb = NULL;
3744         }
3745
3746         /* Update computed state. */
3747         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3748                 if (!connector->encoder || !connector->encoder->crtc)
3749                         continue;
3750
3751                 if (connector->encoder->crtc != crtc)
3752                         continue;
3753
3754                 connector->dpms = DRM_MODE_DPMS_OFF;
3755                 to_intel_encoder(connector->encoder)->connectors_active = false;
3756         }
3757 }
3758
3759 void intel_modeset_disable(struct drm_device *dev)
3760 {
3761         struct drm_crtc *crtc;
3762
3763         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3764                 if (crtc->enabled)
3765                         intel_crtc_disable(crtc);
3766         }
3767 }
3768
3769 void intel_encoder_noop(struct drm_encoder *encoder)
3770 {
3771 }
3772
3773 void intel_encoder_destroy(struct drm_encoder *encoder)
3774 {
3775         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3776
3777         drm_encoder_cleanup(encoder);
3778         kfree(intel_encoder);
3779 }
3780
3781 /* Simple dpms helper for encodres with just one connector, no cloning and only
3782  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3783  * state of the entire output pipe. */
3784 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3785 {
3786         if (mode == DRM_MODE_DPMS_ON) {
3787                 encoder->connectors_active = true;
3788
3789                 intel_crtc_update_dpms(encoder->base.crtc);
3790         } else {
3791                 encoder->connectors_active = false;
3792
3793                 intel_crtc_update_dpms(encoder->base.crtc);
3794         }
3795 }
3796
3797 /* Cross check the actual hw state with our own modeset state tracking (and it's
3798  * internal consistency). */
3799 static void intel_connector_check_state(struct intel_connector *connector)
3800 {
3801         if (connector->get_hw_state(connector)) {
3802                 struct intel_encoder *encoder = connector->encoder;
3803                 struct drm_crtc *crtc;
3804                 bool encoder_enabled;
3805                 enum pipe pipe;
3806
3807                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3808                               connector->base.base.id,
3809                               drm_get_connector_name(&connector->base));
3810
3811                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3812                      "wrong connector dpms state\n");
3813                 WARN(connector->base.encoder != &encoder->base,
3814                      "active connector not linked to encoder\n");
3815                 WARN(!encoder->connectors_active,
3816                      "encoder->connectors_active not set\n");
3817
3818                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3819                 WARN(!encoder_enabled, "encoder not enabled\n");
3820                 if (WARN_ON(!encoder->base.crtc))
3821                         return;
3822
3823                 crtc = encoder->base.crtc;
3824
3825                 WARN(!crtc->enabled, "crtc not enabled\n");
3826                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3827                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3828                      "encoder active on the wrong pipe\n");
3829         }
3830 }
3831
3832 /* Even simpler default implementation, if there's really no special case to
3833  * consider. */
3834 void intel_connector_dpms(struct drm_connector *connector, int mode)
3835 {
3836         struct intel_encoder *encoder = intel_attached_encoder(connector);
3837
3838         /* All the simple cases only support two dpms states. */
3839         if (mode != DRM_MODE_DPMS_ON)
3840                 mode = DRM_MODE_DPMS_OFF;
3841
3842         if (mode == connector->dpms)
3843                 return;
3844
3845         connector->dpms = mode;
3846
3847         /* Only need to change hw state when actually enabled */
3848         if (encoder->base.crtc)
3849                 intel_encoder_dpms(encoder, mode);
3850         else
3851                 WARN_ON(encoder->connectors_active != false);
3852
3853         intel_modeset_check_state(connector->dev);
3854 }
3855
3856 /* Simple connector->get_hw_state implementation for encoders that support only
3857  * one connector and no cloning and hence the encoder state determines the state
3858  * of the connector. */
3859 bool intel_connector_get_hw_state(struct intel_connector *connector)
3860 {
3861         enum pipe pipe = 0;
3862         struct intel_encoder *encoder = connector->encoder;
3863
3864         return encoder->get_hw_state(encoder, &pipe);
3865 }
3866
3867 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3868                                   const struct drm_display_mode *mode,
3869                                   struct drm_display_mode *adjusted_mode)
3870 {
3871         struct drm_device *dev = crtc->dev;
3872
3873         if (HAS_PCH_SPLIT(dev)) {
3874                 /* FDI link clock is fixed at 2.7G */
3875                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3876                         return false;
3877         }
3878
3879         /* All interlaced capable intel hw wants timings in frames. Note though
3880          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3881          * timings, so we need to be careful not to clobber these.*/
3882         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3883                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3884
3885         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3886          * with a hsync front porch of 0.
3887          */
3888         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3889                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3890                 return false;
3891
3892         return true;
3893 }
3894
3895 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3896 {
3897         return 400000; /* FIXME */
3898 }
3899
3900 static int i945_get_display_clock_speed(struct drm_device *dev)
3901 {
3902         return 400000;
3903 }
3904
3905 static int i915_get_display_clock_speed(struct drm_device *dev)
3906 {
3907         return 333000;
3908 }
3909
3910 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3911 {
3912         return 200000;
3913 }
3914
3915 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3916 {
3917         u16 gcfgc = 0;
3918
3919         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3920
3921         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3922                 return 133000;
3923         else {
3924                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3925                 case GC_DISPLAY_CLOCK_333_MHZ:
3926                         return 333000;
3927                 default:
3928                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3929                         return 190000;
3930                 }
3931         }
3932 }
3933
3934 static int i865_get_display_clock_speed(struct drm_device *dev)
3935 {
3936         return 266000;
3937 }
3938
3939 static int i855_get_display_clock_speed(struct drm_device *dev)
3940 {
3941         u16 hpllcc = 0;
3942         /* Assume that the hardware is in the high speed state.  This
3943          * should be the default.
3944          */
3945         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3946         case GC_CLOCK_133_200:
3947         case GC_CLOCK_100_200:
3948                 return 200000;
3949         case GC_CLOCK_166_250:
3950                 return 250000;
3951         case GC_CLOCK_100_133:
3952                 return 133000;
3953         }
3954
3955         /* Shouldn't happen */
3956         return 0;
3957 }
3958
3959 static int i830_get_display_clock_speed(struct drm_device *dev)
3960 {
3961         return 133000;
3962 }
3963
3964 struct fdi_m_n {
3965         u32        tu;
3966         u32        gmch_m;
3967         u32        gmch_n;
3968         u32        link_m;
3969         u32        link_n;
3970 };
3971
3972 static void
3973 fdi_reduce_ratio(u32 *num, u32 *den)
3974 {
3975         while (*num > 0xffffff || *den > 0xffffff) {
3976                 *num >>= 1;
3977                 *den >>= 1;
3978         }
3979 }
3980
3981 static void
3982 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3983                      int link_clock, struct fdi_m_n *m_n)
3984 {
3985         m_n->tu = 64; /* default size */
3986
3987         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3988         m_n->gmch_m = bits_per_pixel * pixel_clock;
3989         m_n->gmch_n = link_clock * nlanes * 8;
3990         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3991
3992         m_n->link_m = pixel_clock;
3993         m_n->link_n = link_clock;
3994         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3995 }
3996
3997 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3998 {
3999         if (i915_panel_use_ssc >= 0)
4000                 return i915_panel_use_ssc != 0;
4001         return dev_priv->lvds_use_ssc
4002                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4003 }
4004
4005 /**
4006  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4007  * @crtc: CRTC structure
4008  * @mode: requested mode
4009  *
4010  * A pipe may be connected to one or more outputs.  Based on the depth of the
4011  * attached framebuffer, choose a good color depth to use on the pipe.
4012  *
4013  * If possible, match the pipe depth to the fb depth.  In some cases, this
4014  * isn't ideal, because the connected output supports a lesser or restricted
4015  * set of depths.  Resolve that here:
4016  *    LVDS typically supports only 6bpc, so clamp down in that case
4017  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4018  *    Displays may support a restricted set as well, check EDID and clamp as
4019  *      appropriate.
4020  *    DP may want to dither down to 6bpc to fit larger modes
4021  *
4022  * RETURNS:
4023  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4024  * true if they don't match).
4025  */
4026 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4027                                          struct drm_framebuffer *fb,
4028                                          unsigned int *pipe_bpp,
4029                                          struct drm_display_mode *mode)
4030 {
4031         struct drm_device *dev = crtc->dev;
4032         struct drm_i915_private *dev_priv = dev->dev_private;
4033         struct drm_connector *connector;
4034         struct intel_encoder *intel_encoder;
4035         unsigned int display_bpc = UINT_MAX, bpc;
4036
4037         /* Walk the encoders & connectors on this crtc, get min bpc */
4038         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4039
4040                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4041                         unsigned int lvds_bpc;
4042
4043                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4044                             LVDS_A3_POWER_UP)
4045                                 lvds_bpc = 8;
4046                         else
4047                                 lvds_bpc = 6;
4048
4049                         if (lvds_bpc < display_bpc) {
4050                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4051                                 display_bpc = lvds_bpc;
4052                         }
4053                         continue;
4054                 }
4055
4056                 /* Not one of the known troublemakers, check the EDID */
4057                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4058                                     head) {
4059                         if (connector->encoder != &intel_encoder->base)
4060                                 continue;
4061
4062                         /* Don't use an invalid EDID bpc value */
4063                         if (connector->display_info.bpc &&
4064                             connector->display_info.bpc < display_bpc) {
4065                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4066                                 display_bpc = connector->display_info.bpc;
4067                         }
4068                 }
4069
4070                 /*
4071                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4072                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4073                  */
4074                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4075                         if (display_bpc > 8 && display_bpc < 12) {
4076                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4077                                 display_bpc = 12;
4078                         } else {
4079                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4080                                 display_bpc = 8;
4081                         }
4082                 }
4083         }
4084
4085         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4086                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4087                 display_bpc = 6;
4088         }
4089
4090         /*
4091          * We could just drive the pipe at the highest bpc all the time and
4092          * enable dithering as needed, but that costs bandwidth.  So choose
4093          * the minimum value that expresses the full color range of the fb but
4094          * also stays within the max display bpc discovered above.
4095          */
4096
4097         switch (fb->depth) {
4098         case 8:
4099                 bpc = 8; /* since we go through a colormap */
4100                 break;
4101         case 15:
4102         case 16:
4103                 bpc = 6; /* min is 18bpp */
4104                 break;
4105         case 24:
4106                 bpc = 8;
4107                 break;
4108         case 30:
4109                 bpc = 10;
4110                 break;
4111         case 48:
4112                 bpc = 12;
4113                 break;
4114         default:
4115                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4116                 bpc = min((unsigned int)8, display_bpc);
4117                 break;
4118         }
4119
4120         display_bpc = min(display_bpc, bpc);
4121
4122         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4123                       bpc, display_bpc);
4124
4125         *pipe_bpp = display_bpc * 3;
4126
4127         return display_bpc != bpc;
4128 }
4129
4130 static int vlv_get_refclk(struct drm_crtc *crtc)
4131 {
4132         struct drm_device *dev = crtc->dev;
4133         struct drm_i915_private *dev_priv = dev->dev_private;
4134         int refclk = 27000; /* for DP & HDMI */
4135
4136         return 100000; /* only one validated so far */
4137
4138         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4139                 refclk = 96000;
4140         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4141                 if (intel_panel_use_ssc(dev_priv))
4142                         refclk = 100000;
4143                 else
4144                         refclk = 96000;
4145         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4146                 refclk = 100000;
4147         }
4148
4149         return refclk;
4150 }
4151
4152 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4153 {
4154         struct drm_device *dev = crtc->dev;
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         int refclk;
4157
4158         if (IS_VALLEYVIEW(dev)) {
4159                 refclk = vlv_get_refclk(crtc);
4160         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4161             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4162                 refclk = dev_priv->lvds_ssc_freq * 1000;
4163                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4164                               refclk / 1000);
4165         } else if (!IS_GEN2(dev)) {
4166                 refclk = 96000;
4167         } else {
4168                 refclk = 48000;
4169         }
4170
4171         return refclk;
4172 }
4173
4174 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4175                                       intel_clock_t *clock)
4176 {
4177         /* SDVO TV has fixed PLL values depend on its clock range,
4178            this mirrors vbios setting. */
4179         if (adjusted_mode->clock >= 100000
4180             && adjusted_mode->clock < 140500) {
4181                 clock->p1 = 2;
4182                 clock->p2 = 10;
4183                 clock->n = 3;
4184                 clock->m1 = 16;
4185                 clock->m2 = 8;
4186         } else if (adjusted_mode->clock >= 140500
4187                    && adjusted_mode->clock <= 200000) {
4188                 clock->p1 = 1;
4189                 clock->p2 = 10;
4190                 clock->n = 6;
4191                 clock->m1 = 12;
4192                 clock->m2 = 8;
4193         }
4194 }
4195
4196 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4197                                      intel_clock_t *clock,
4198                                      intel_clock_t *reduced_clock)
4199 {
4200         struct drm_device *dev = crtc->dev;
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203         int pipe = intel_crtc->pipe;
4204         u32 fp, fp2 = 0;
4205
4206         if (IS_PINEVIEW(dev)) {
4207                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4208                 if (reduced_clock)
4209                         fp2 = (1 << reduced_clock->n) << 16 |
4210                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4211         } else {
4212                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4213                 if (reduced_clock)
4214                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4215                                 reduced_clock->m2;
4216         }
4217
4218         I915_WRITE(FP0(pipe), fp);
4219
4220         intel_crtc->lowfreq_avail = false;
4221         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4222             reduced_clock && i915_powersave) {
4223                 I915_WRITE(FP1(pipe), fp2);
4224                 intel_crtc->lowfreq_avail = true;
4225         } else {
4226                 I915_WRITE(FP1(pipe), fp);
4227         }
4228 }
4229
4230 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4231                               struct drm_display_mode *adjusted_mode)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236         int pipe = intel_crtc->pipe;
4237         u32 temp;
4238
4239         temp = I915_READ(LVDS);
4240         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4241         if (pipe == 1) {
4242                 temp |= LVDS_PIPEB_SELECT;
4243         } else {
4244                 temp &= ~LVDS_PIPEB_SELECT;
4245         }
4246         /* set the corresponsding LVDS_BORDER bit */
4247         temp |= dev_priv->lvds_border_bits;
4248         /* Set the B0-B3 data pairs corresponding to whether we're going to
4249          * set the DPLLs for dual-channel mode or not.
4250          */
4251         if (clock->p2 == 7)
4252                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4253         else
4254                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4255
4256         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4257          * appropriately here, but we need to look more thoroughly into how
4258          * panels behave in the two modes.
4259          */
4260         /* set the dithering flag on LVDS as needed */
4261         if (INTEL_INFO(dev)->gen >= 4) {
4262                 if (dev_priv->lvds_dither)
4263                         temp |= LVDS_ENABLE_DITHER;
4264                 else
4265                         temp &= ~LVDS_ENABLE_DITHER;
4266         }
4267         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4268         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4269                 temp |= LVDS_HSYNC_POLARITY;
4270         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4271                 temp |= LVDS_VSYNC_POLARITY;
4272         I915_WRITE(LVDS, temp);
4273 }
4274
4275 static void vlv_update_pll(struct drm_crtc *crtc,
4276                            struct drm_display_mode *mode,
4277                            struct drm_display_mode *adjusted_mode,
4278                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4279                            int num_connectors)
4280 {
4281         struct drm_device *dev = crtc->dev;
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284         int pipe = intel_crtc->pipe;
4285         u32 dpll, mdiv, pdiv;
4286         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4287         bool is_sdvo;
4288         u32 temp;
4289
4290         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4291                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4292
4293         dpll = DPLL_VGA_MODE_DIS;
4294         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4295         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4296         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4297
4298         I915_WRITE(DPLL(pipe), dpll);
4299         POSTING_READ(DPLL(pipe));
4300
4301         bestn = clock->n;
4302         bestm1 = clock->m1;
4303         bestm2 = clock->m2;
4304         bestp1 = clock->p1;
4305         bestp2 = clock->p2;
4306
4307         /*
4308          * In Valleyview PLL and program lane counter registers are exposed
4309          * through DPIO interface
4310          */
4311         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4312         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4313         mdiv |= ((bestn << DPIO_N_SHIFT));
4314         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4315         mdiv |= (1 << DPIO_K_SHIFT);
4316         mdiv |= DPIO_ENABLE_CALIBRATION;
4317         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4318
4319         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4320
4321         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4322                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4323                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4324                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4325         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4326
4327         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4328
4329         dpll |= DPLL_VCO_ENABLE;
4330         I915_WRITE(DPLL(pipe), dpll);
4331         POSTING_READ(DPLL(pipe));
4332         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4333                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4334
4335         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4336
4337         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4338                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4339
4340         I915_WRITE(DPLL(pipe), dpll);
4341
4342         /* Wait for the clocks to stabilize. */
4343         POSTING_READ(DPLL(pipe));
4344         udelay(150);
4345
4346         temp = 0;
4347         if (is_sdvo) {
4348                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4349                 if (temp > 1)
4350                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4351                 else
4352                         temp = 0;
4353         }
4354         I915_WRITE(DPLL_MD(pipe), temp);
4355         POSTING_READ(DPLL_MD(pipe));
4356
4357         /* Now program lane control registers */
4358         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4359                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4360         {
4361                 temp = 0x1000C4;
4362                 if(pipe == 1)
4363                         temp |= (1 << 21);
4364                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4365         }
4366         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4367         {
4368                 temp = 0x1000C4;
4369                 if(pipe == 1)
4370                         temp |= (1 << 21);
4371                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4372         }
4373 }
4374
4375 static void i9xx_update_pll(struct drm_crtc *crtc,
4376                             struct drm_display_mode *mode,
4377                             struct drm_display_mode *adjusted_mode,
4378                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4379                             int num_connectors)
4380 {
4381         struct drm_device *dev = crtc->dev;
4382         struct drm_i915_private *dev_priv = dev->dev_private;
4383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4384         int pipe = intel_crtc->pipe;
4385         u32 dpll;
4386         bool is_sdvo;
4387
4388         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4389
4390         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4391                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4392
4393         dpll = DPLL_VGA_MODE_DIS;
4394
4395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4396                 dpll |= DPLLB_MODE_LVDS;
4397         else
4398                 dpll |= DPLLB_MODE_DAC_SERIAL;
4399         if (is_sdvo) {
4400                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4401                 if (pixel_multiplier > 1) {
4402                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4403                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4404                 }
4405                 dpll |= DPLL_DVO_HIGH_SPEED;
4406         }
4407         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4408                 dpll |= DPLL_DVO_HIGH_SPEED;
4409
4410         /* compute bitmask from p1 value */
4411         if (IS_PINEVIEW(dev))
4412                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4413         else {
4414                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4415                 if (IS_G4X(dev) && reduced_clock)
4416                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4417         }
4418         switch (clock->p2) {
4419         case 5:
4420                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4421                 break;
4422         case 7:
4423                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4424                 break;
4425         case 10:
4426                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4427                 break;
4428         case 14:
4429                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4430                 break;
4431         }
4432         if (INTEL_INFO(dev)->gen >= 4)
4433                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4434
4435         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4436                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4437         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4438                 /* XXX: just matching BIOS for now */
4439                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4440                 dpll |= 3;
4441         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4442                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4443                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4444         else
4445                 dpll |= PLL_REF_INPUT_DREFCLK;
4446
4447         dpll |= DPLL_VCO_ENABLE;
4448         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4449         POSTING_READ(DPLL(pipe));
4450         udelay(150);
4451
4452         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4453          * This is an exception to the general rule that mode_set doesn't turn
4454          * things on.
4455          */
4456         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4457                 intel_update_lvds(crtc, clock, adjusted_mode);
4458
4459         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4460                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4461
4462         I915_WRITE(DPLL(pipe), dpll);
4463
4464         /* Wait for the clocks to stabilize. */
4465         POSTING_READ(DPLL(pipe));
4466         udelay(150);
4467
4468         if (INTEL_INFO(dev)->gen >= 4) {
4469                 u32 temp = 0;
4470                 if (is_sdvo) {
4471                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4472                         if (temp > 1)
4473                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4474                         else
4475                                 temp = 0;
4476                 }
4477                 I915_WRITE(DPLL_MD(pipe), temp);
4478         } else {
4479                 /* The pixel multiplier can only be updated once the
4480                  * DPLL is enabled and the clocks are stable.
4481                  *
4482                  * So write it again.
4483                  */
4484                 I915_WRITE(DPLL(pipe), dpll);
4485         }
4486 }
4487
4488 static void i8xx_update_pll(struct drm_crtc *crtc,
4489                             struct drm_display_mode *adjusted_mode,
4490                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4491                             int num_connectors)
4492 {
4493         struct drm_device *dev = crtc->dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4496         int pipe = intel_crtc->pipe;
4497         u32 dpll;
4498
4499         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4500
4501         dpll = DPLL_VGA_MODE_DIS;
4502
4503         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4504                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4505         } else {
4506                 if (clock->p1 == 2)
4507                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4508                 else
4509                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4510                 if (clock->p2 == 4)
4511                         dpll |= PLL_P2_DIVIDE_BY_4;
4512         }
4513
4514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4515                 /* XXX: just matching BIOS for now */
4516                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4517                 dpll |= 3;
4518         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4519                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4520                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4521         else
4522                 dpll |= PLL_REF_INPUT_DREFCLK;
4523
4524         dpll |= DPLL_VCO_ENABLE;
4525         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4526         POSTING_READ(DPLL(pipe));
4527         udelay(150);
4528
4529         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4530          * This is an exception to the general rule that mode_set doesn't turn
4531          * things on.
4532          */
4533         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4534                 intel_update_lvds(crtc, clock, adjusted_mode);
4535
4536         I915_WRITE(DPLL(pipe), dpll);
4537
4538         /* Wait for the clocks to stabilize. */
4539         POSTING_READ(DPLL(pipe));
4540         udelay(150);
4541
4542         /* The pixel multiplier can only be updated once the
4543          * DPLL is enabled and the clocks are stable.
4544          *
4545          * So write it again.
4546          */
4547         I915_WRITE(DPLL(pipe), dpll);
4548 }
4549
4550 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4551                                    struct drm_display_mode *mode,
4552                                    struct drm_display_mode *adjusted_mode)
4553 {
4554         struct drm_device *dev = intel_crtc->base.dev;
4555         struct drm_i915_private *dev_priv = dev->dev_private;
4556         enum pipe pipe = intel_crtc->pipe;
4557         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4558         uint32_t vsyncshift;
4559
4560         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4561                 /* the chip adds 2 halflines automatically */
4562                 adjusted_mode->crtc_vtotal -= 1;
4563                 adjusted_mode->crtc_vblank_end -= 1;
4564                 vsyncshift = adjusted_mode->crtc_hsync_start
4565                              - adjusted_mode->crtc_htotal / 2;
4566         } else {
4567                 vsyncshift = 0;
4568         }
4569
4570         if (INTEL_INFO(dev)->gen > 3)
4571                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4572
4573         I915_WRITE(HTOTAL(cpu_transcoder),
4574                    (adjusted_mode->crtc_hdisplay - 1) |
4575                    ((adjusted_mode->crtc_htotal - 1) << 16));
4576         I915_WRITE(HBLANK(cpu_transcoder),
4577                    (adjusted_mode->crtc_hblank_start - 1) |
4578                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4579         I915_WRITE(HSYNC(cpu_transcoder),
4580                    (adjusted_mode->crtc_hsync_start - 1) |
4581                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4582
4583         I915_WRITE(VTOTAL(cpu_transcoder),
4584                    (adjusted_mode->crtc_vdisplay - 1) |
4585                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4586         I915_WRITE(VBLANK(cpu_transcoder),
4587                    (adjusted_mode->crtc_vblank_start - 1) |
4588                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4589         I915_WRITE(VSYNC(cpu_transcoder),
4590                    (adjusted_mode->crtc_vsync_start - 1) |
4591                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4592
4593         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4594          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4595          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4596          * bits. */
4597         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4598             (pipe == PIPE_B || pipe == PIPE_C))
4599                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4600
4601         /* pipesrc controls the size that is scaled from, which should
4602          * always be the user's requested size.
4603          */
4604         I915_WRITE(PIPESRC(pipe),
4605                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4606 }
4607
4608 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4609                               struct drm_display_mode *mode,
4610                               struct drm_display_mode *adjusted_mode,
4611                               int x, int y,
4612                               struct drm_framebuffer *fb)
4613 {
4614         struct drm_device *dev = crtc->dev;
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4617         int pipe = intel_crtc->pipe;
4618         int plane = intel_crtc->plane;
4619         int refclk, num_connectors = 0;
4620         intel_clock_t clock, reduced_clock;
4621         u32 dspcntr, pipeconf;
4622         bool ok, has_reduced_clock = false, is_sdvo = false;
4623         bool is_lvds = false, is_tv = false, is_dp = false;
4624         struct intel_encoder *encoder;
4625         const intel_limit_t *limit;
4626         int ret;
4627
4628         for_each_encoder_on_crtc(dev, crtc, encoder) {
4629                 switch (encoder->type) {
4630                 case INTEL_OUTPUT_LVDS:
4631                         is_lvds = true;
4632                         break;
4633                 case INTEL_OUTPUT_SDVO:
4634                 case INTEL_OUTPUT_HDMI:
4635                         is_sdvo = true;
4636                         if (encoder->needs_tv_clock)
4637                                 is_tv = true;
4638                         break;
4639                 case INTEL_OUTPUT_TVOUT:
4640                         is_tv = true;
4641                         break;
4642                 case INTEL_OUTPUT_DISPLAYPORT:
4643                         is_dp = true;
4644                         break;
4645                 }
4646
4647                 num_connectors++;
4648         }
4649
4650         refclk = i9xx_get_refclk(crtc, num_connectors);
4651
4652         /*
4653          * Returns a set of divisors for the desired target clock with the given
4654          * refclk, or FALSE.  The returned values represent the clock equation:
4655          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4656          */
4657         limit = intel_limit(crtc, refclk);
4658         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4659                              &clock);
4660         if (!ok) {
4661                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4662                 return -EINVAL;
4663         }
4664
4665         /* Ensure that the cursor is valid for the new mode before changing... */
4666         intel_crtc_update_cursor(crtc, true);
4667
4668         if (is_lvds && dev_priv->lvds_downclock_avail) {
4669                 /*
4670                  * Ensure we match the reduced clock's P to the target clock.
4671                  * If the clocks don't match, we can't switch the display clock
4672                  * by using the FP0/FP1. In such case we will disable the LVDS
4673                  * downclock feature.
4674                 */
4675                 has_reduced_clock = limit->find_pll(limit, crtc,
4676                                                     dev_priv->lvds_downclock,
4677                                                     refclk,
4678                                                     &clock,
4679                                                     &reduced_clock);
4680         }
4681
4682         if (is_sdvo && is_tv)
4683                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4684
4685         if (IS_GEN2(dev))
4686                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4687                                 has_reduced_clock ? &reduced_clock : NULL,
4688                                 num_connectors);
4689         else if (IS_VALLEYVIEW(dev))
4690                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4691                                 has_reduced_clock ? &reduced_clock : NULL,
4692                                 num_connectors);
4693         else
4694                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4695                                 has_reduced_clock ? &reduced_clock : NULL,
4696                                 num_connectors);
4697
4698         /* setup pipeconf */
4699         pipeconf = I915_READ(PIPECONF(pipe));
4700
4701         /* Set up the display plane register */
4702         dspcntr = DISPPLANE_GAMMA_ENABLE;
4703
4704         if (pipe == 0)
4705                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4706         else
4707                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4708
4709         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4710                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4711                  * core speed.
4712                  *
4713                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4714                  * pipe == 0 check?
4715                  */
4716                 if (mode->clock >
4717                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4718                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4719                 else
4720                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4721         }
4722
4723         /* default to 8bpc */
4724         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4725         if (is_dp) {
4726                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4727                         pipeconf |= PIPECONF_BPP_6 |
4728                                     PIPECONF_DITHER_EN |
4729                                     PIPECONF_DITHER_TYPE_SP;
4730                 }
4731         }
4732
4733         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4734                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4735                         pipeconf |= PIPECONF_BPP_6 |
4736                                         PIPECONF_ENABLE |
4737                                         I965_PIPECONF_ACTIVE;
4738                 }
4739         }
4740
4741         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4742         drm_mode_debug_printmodeline(mode);
4743
4744         if (HAS_PIPE_CXSR(dev)) {
4745                 if (intel_crtc->lowfreq_avail) {
4746                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4747                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4748                 } else {
4749                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4750                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4751                 }
4752         }
4753
4754         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4755         if (!IS_GEN2(dev) &&
4756             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4757                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4758         else
4759                 pipeconf |= PIPECONF_PROGRESSIVE;
4760
4761         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4762
4763         /* pipesrc and dspsize control the size that is scaled from,
4764          * which should always be the user's requested size.
4765          */
4766         I915_WRITE(DSPSIZE(plane),
4767                    ((mode->vdisplay - 1) << 16) |
4768                    (mode->hdisplay - 1));
4769         I915_WRITE(DSPPOS(plane), 0);
4770
4771         I915_WRITE(PIPECONF(pipe), pipeconf);
4772         POSTING_READ(PIPECONF(pipe));
4773         intel_enable_pipe(dev_priv, pipe, false);
4774
4775         intel_wait_for_vblank(dev, pipe);
4776
4777         I915_WRITE(DSPCNTR(plane), dspcntr);
4778         POSTING_READ(DSPCNTR(plane));
4779
4780         ret = intel_pipe_set_base(crtc, x, y, fb);
4781
4782         intel_update_watermarks(dev);
4783
4784         return ret;
4785 }
4786
4787 /*
4788  * Initialize reference clocks when the driver loads
4789  */
4790 void ironlake_init_pch_refclk(struct drm_device *dev)
4791 {
4792         struct drm_i915_private *dev_priv = dev->dev_private;
4793         struct drm_mode_config *mode_config = &dev->mode_config;
4794         struct intel_encoder *encoder;
4795         u32 temp;
4796         bool has_lvds = false;
4797         bool has_cpu_edp = false;
4798         bool has_pch_edp = false;
4799         bool has_panel = false;
4800         bool has_ck505 = false;
4801         bool can_ssc = false;
4802
4803         /* We need to take the global config into account */
4804         list_for_each_entry(encoder, &mode_config->encoder_list,
4805                             base.head) {
4806                 switch (encoder->type) {
4807                 case INTEL_OUTPUT_LVDS:
4808                         has_panel = true;
4809                         has_lvds = true;
4810                         break;
4811                 case INTEL_OUTPUT_EDP:
4812                         has_panel = true;
4813                         if (intel_encoder_is_pch_edp(&encoder->base))
4814                                 has_pch_edp = true;
4815                         else
4816                                 has_cpu_edp = true;
4817                         break;
4818                 }
4819         }
4820
4821         if (HAS_PCH_IBX(dev)) {
4822                 has_ck505 = dev_priv->display_clock_mode;
4823                 can_ssc = has_ck505;
4824         } else {
4825                 has_ck505 = false;
4826                 can_ssc = true;
4827         }
4828
4829         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4830                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4831                       has_ck505);
4832
4833         /* Ironlake: try to setup display ref clock before DPLL
4834          * enabling. This is only under driver's control after
4835          * PCH B stepping, previous chipset stepping should be
4836          * ignoring this setting.
4837          */
4838         temp = I915_READ(PCH_DREF_CONTROL);
4839         /* Always enable nonspread source */
4840         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4841
4842         if (has_ck505)
4843                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4844         else
4845                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4846
4847         if (has_panel) {
4848                 temp &= ~DREF_SSC_SOURCE_MASK;
4849                 temp |= DREF_SSC_SOURCE_ENABLE;
4850
4851                 /* SSC must be turned on before enabling the CPU output  */
4852                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4853                         DRM_DEBUG_KMS("Using SSC on panel\n");
4854                         temp |= DREF_SSC1_ENABLE;
4855                 } else
4856                         temp &= ~DREF_SSC1_ENABLE;
4857
4858                 /* Get SSC going before enabling the outputs */
4859                 I915_WRITE(PCH_DREF_CONTROL, temp);
4860                 POSTING_READ(PCH_DREF_CONTROL);
4861                 udelay(200);
4862
4863                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4864
4865                 /* Enable CPU source on CPU attached eDP */
4866                 if (has_cpu_edp) {
4867                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4868                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4869                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4870                         }
4871                         else
4872                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4873                 } else
4874                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4875
4876                 I915_WRITE(PCH_DREF_CONTROL, temp);
4877                 POSTING_READ(PCH_DREF_CONTROL);
4878                 udelay(200);
4879         } else {
4880                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4881
4882                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4883
4884                 /* Turn off CPU output */
4885                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4886
4887                 I915_WRITE(PCH_DREF_CONTROL, temp);
4888                 POSTING_READ(PCH_DREF_CONTROL);
4889                 udelay(200);
4890
4891                 /* Turn off the SSC source */
4892                 temp &= ~DREF_SSC_SOURCE_MASK;
4893                 temp |= DREF_SSC_SOURCE_DISABLE;
4894
4895                 /* Turn off SSC1 */
4896                 temp &= ~ DREF_SSC1_ENABLE;
4897
4898                 I915_WRITE(PCH_DREF_CONTROL, temp);
4899                 POSTING_READ(PCH_DREF_CONTROL);
4900                 udelay(200);
4901         }
4902 }
4903
4904 static int ironlake_get_refclk(struct drm_crtc *crtc)
4905 {
4906         struct drm_device *dev = crtc->dev;
4907         struct drm_i915_private *dev_priv = dev->dev_private;
4908         struct intel_encoder *encoder;
4909         struct intel_encoder *edp_encoder = NULL;
4910         int num_connectors = 0;
4911         bool is_lvds = false;
4912
4913         for_each_encoder_on_crtc(dev, crtc, encoder) {
4914                 switch (encoder->type) {
4915                 case INTEL_OUTPUT_LVDS:
4916                         is_lvds = true;
4917                         break;
4918                 case INTEL_OUTPUT_EDP:
4919                         edp_encoder = encoder;
4920                         break;
4921                 }
4922                 num_connectors++;
4923         }
4924
4925         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4926                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4927                               dev_priv->lvds_ssc_freq);
4928                 return dev_priv->lvds_ssc_freq * 1000;
4929         }
4930
4931         return 120000;
4932 }
4933
4934 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4935                                   struct drm_display_mode *adjusted_mode,
4936                                   bool dither)
4937 {
4938         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4940         int pipe = intel_crtc->pipe;
4941         uint32_t val;
4942
4943         val = I915_READ(PIPECONF(pipe));
4944
4945         val &= ~PIPE_BPC_MASK;
4946         switch (intel_crtc->bpp) {
4947         case 18:
4948                 val |= PIPE_6BPC;
4949                 break;
4950         case 24:
4951                 val |= PIPE_8BPC;
4952                 break;
4953         case 30:
4954                 val |= PIPE_10BPC;
4955                 break;
4956         case 36:
4957                 val |= PIPE_12BPC;
4958                 break;
4959         default:
4960                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4961                 BUG();
4962         }
4963
4964         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4965         if (dither)
4966                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4967
4968         val &= ~PIPECONF_INTERLACE_MASK;
4969         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4970                 val |= PIPECONF_INTERLACED_ILK;
4971         else
4972                 val |= PIPECONF_PROGRESSIVE;
4973
4974         I915_WRITE(PIPECONF(pipe), val);
4975         POSTING_READ(PIPECONF(pipe));
4976 }
4977
4978 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4979                                  struct drm_display_mode *adjusted_mode,
4980                                  bool dither)
4981 {
4982         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4985         uint32_t val;
4986
4987         val = I915_READ(PIPECONF(cpu_transcoder));
4988
4989         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4990         if (dither)
4991                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4992
4993         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4994         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4995                 val |= PIPECONF_INTERLACED_ILK;
4996         else
4997                 val |= PIPECONF_PROGRESSIVE;
4998
4999         I915_WRITE(PIPECONF(cpu_transcoder), val);
5000         POSTING_READ(PIPECONF(cpu_transcoder));
5001 }
5002
5003 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5004                                     struct drm_display_mode *adjusted_mode,
5005                                     intel_clock_t *clock,
5006                                     bool *has_reduced_clock,
5007                                     intel_clock_t *reduced_clock)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_encoder *intel_encoder;
5012         int refclk;
5013         const intel_limit_t *limit;
5014         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5015
5016         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5017                 switch (intel_encoder->type) {
5018                 case INTEL_OUTPUT_LVDS:
5019                         is_lvds = true;
5020                         break;
5021                 case INTEL_OUTPUT_SDVO:
5022                 case INTEL_OUTPUT_HDMI:
5023                         is_sdvo = true;
5024                         if (intel_encoder->needs_tv_clock)
5025                                 is_tv = true;
5026                         break;
5027                 case INTEL_OUTPUT_TVOUT:
5028                         is_tv = true;
5029                         break;
5030                 }
5031         }
5032
5033         refclk = ironlake_get_refclk(crtc);
5034
5035         /*
5036          * Returns a set of divisors for the desired target clock with the given
5037          * refclk, or FALSE.  The returned values represent the clock equation:
5038          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5039          */
5040         limit = intel_limit(crtc, refclk);
5041         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5042                               clock);
5043         if (!ret)
5044                 return false;
5045
5046         if (is_lvds && dev_priv->lvds_downclock_avail) {
5047                 /*
5048                  * Ensure we match the reduced clock's P to the target clock.
5049                  * If the clocks don't match, we can't switch the display clock
5050                  * by using the FP0/FP1. In such case we will disable the LVDS
5051                  * downclock feature.
5052                 */
5053                 *has_reduced_clock = limit->find_pll(limit, crtc,
5054                                                      dev_priv->lvds_downclock,
5055                                                      refclk,
5056                                                      clock,
5057                                                      reduced_clock);
5058         }
5059
5060         if (is_sdvo && is_tv)
5061                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5062
5063         return true;
5064 }
5065
5066 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5067 {
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069         uint32_t temp;
5070
5071         temp = I915_READ(SOUTH_CHICKEN1);
5072         if (temp & FDI_BC_BIFURCATION_SELECT)
5073                 return;
5074
5075         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5076         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5077
5078         temp |= FDI_BC_BIFURCATION_SELECT;
5079         DRM_DEBUG_KMS("enabling fdi C rx\n");
5080         I915_WRITE(SOUTH_CHICKEN1, temp);
5081         POSTING_READ(SOUTH_CHICKEN1);
5082 }
5083
5084 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5085 {
5086         struct drm_device *dev = intel_crtc->base.dev;
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct intel_crtc *pipe_B_crtc =
5089                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5090
5091         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5092                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5093         if (intel_crtc->fdi_lanes > 4) {
5094                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5095                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5096                 /* Clamp lanes to avoid programming the hw with bogus values. */
5097                 intel_crtc->fdi_lanes = 4;
5098
5099                 return false;
5100         }
5101
5102         if (dev_priv->num_pipe == 2)
5103                 return true;
5104
5105         switch (intel_crtc->pipe) {
5106         case PIPE_A:
5107                 return true;
5108         case PIPE_B:
5109                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5110                     intel_crtc->fdi_lanes > 2) {
5111                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5112                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5113                         /* Clamp lanes to avoid programming the hw with bogus values. */
5114                         intel_crtc->fdi_lanes = 2;
5115
5116                         return false;
5117                 }
5118
5119                 if (intel_crtc->fdi_lanes > 2)
5120                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5121                 else
5122                         cpt_enable_fdi_bc_bifurcation(dev);
5123
5124                 return true;
5125         case PIPE_C:
5126                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5127                         if (intel_crtc->fdi_lanes > 2) {
5128                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5129                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5130                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5131                                 intel_crtc->fdi_lanes = 2;
5132
5133                                 return false;
5134                         }
5135                 } else {
5136                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5137                         return false;
5138                 }
5139
5140                 cpt_enable_fdi_bc_bifurcation(dev);
5141
5142                 return true;
5143         default:
5144                 BUG();
5145         }
5146 }
5147
5148 static void ironlake_set_m_n(struct drm_crtc *crtc,
5149                              struct drm_display_mode *mode,
5150                              struct drm_display_mode *adjusted_mode)
5151 {
5152         struct drm_device *dev = crtc->dev;
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5155         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5156         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5157         struct fdi_m_n m_n = {0};
5158         int target_clock, pixel_multiplier, lane, link_bw;
5159         bool is_dp = false, is_cpu_edp = false;
5160
5161         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5162                 switch (intel_encoder->type) {
5163                 case INTEL_OUTPUT_DISPLAYPORT:
5164                         is_dp = true;
5165                         break;
5166                 case INTEL_OUTPUT_EDP:
5167                         is_dp = true;
5168                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5169                                 is_cpu_edp = true;
5170                         edp_encoder = intel_encoder;
5171                         break;
5172                 }
5173         }
5174
5175         /* FDI link */
5176         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5177         lane = 0;
5178         /* CPU eDP doesn't require FDI link, so just set DP M/N
5179            according to current link config */
5180         if (is_cpu_edp) {
5181                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5182         } else {
5183                 /* FDI is a binary signal running at ~2.7GHz, encoding
5184                  * each output octet as 10 bits. The actual frequency
5185                  * is stored as a divider into a 100MHz clock, and the
5186                  * mode pixel clock is stored in units of 1KHz.
5187                  * Hence the bw of each lane in terms of the mode signal
5188                  * is:
5189                  */
5190                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5191         }
5192
5193         /* [e]DP over FDI requires target mode clock instead of link clock. */
5194         if (edp_encoder)
5195                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5196         else if (is_dp)
5197                 target_clock = mode->clock;
5198         else
5199                 target_clock = adjusted_mode->clock;
5200
5201         if (!lane) {
5202                 /*
5203                  * Account for spread spectrum to avoid
5204                  * oversubscribing the link. Max center spread
5205                  * is 2.5%; use 5% for safety's sake.
5206                  */
5207                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5208                 lane = bps / (link_bw * 8) + 1;
5209         }
5210
5211         intel_crtc->fdi_lanes = lane;
5212
5213         if (pixel_multiplier > 1)
5214                 link_bw *= pixel_multiplier;
5215         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5216                              &m_n);
5217
5218         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5219         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5220         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5221         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5222 }
5223
5224 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5225                                       struct drm_display_mode *adjusted_mode,
5226                                       intel_clock_t *clock, u32 fp)
5227 {
5228         struct drm_crtc *crtc = &intel_crtc->base;
5229         struct drm_device *dev = crtc->dev;
5230         struct drm_i915_private *dev_priv = dev->dev_private;
5231         struct intel_encoder *intel_encoder;
5232         uint32_t dpll;
5233         int factor, pixel_multiplier, num_connectors = 0;
5234         bool is_lvds = false, is_sdvo = false, is_tv = false;
5235         bool is_dp = false, is_cpu_edp = false;
5236
5237         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5238                 switch (intel_encoder->type) {
5239                 case INTEL_OUTPUT_LVDS:
5240                         is_lvds = true;
5241                         break;
5242                 case INTEL_OUTPUT_SDVO:
5243                 case INTEL_OUTPUT_HDMI:
5244                         is_sdvo = true;
5245                         if (intel_encoder->needs_tv_clock)
5246                                 is_tv = true;
5247                         break;
5248                 case INTEL_OUTPUT_TVOUT:
5249                         is_tv = true;
5250                         break;
5251                 case INTEL_OUTPUT_DISPLAYPORT:
5252                         is_dp = true;
5253                         break;
5254                 case INTEL_OUTPUT_EDP:
5255                         is_dp = true;
5256                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5257                                 is_cpu_edp = true;
5258                         break;
5259                 }
5260
5261                 num_connectors++;
5262         }
5263
5264         /* Enable autotuning of the PLL clock (if permissible) */
5265         factor = 21;
5266         if (is_lvds) {
5267                 if ((intel_panel_use_ssc(dev_priv) &&
5268                      dev_priv->lvds_ssc_freq == 100) ||
5269                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5270                         factor = 25;
5271         } else if (is_sdvo && is_tv)
5272                 factor = 20;
5273
5274         if (clock->m < factor * clock->n)
5275                 fp |= FP_CB_TUNE;
5276
5277         dpll = 0;
5278
5279         if (is_lvds)
5280                 dpll |= DPLLB_MODE_LVDS;
5281         else
5282                 dpll |= DPLLB_MODE_DAC_SERIAL;
5283         if (is_sdvo) {
5284                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5285                 if (pixel_multiplier > 1) {
5286                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5287                 }
5288                 dpll |= DPLL_DVO_HIGH_SPEED;
5289         }
5290         if (is_dp && !is_cpu_edp)
5291                 dpll |= DPLL_DVO_HIGH_SPEED;
5292
5293         /* compute bitmask from p1 value */
5294         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5295         /* also FPA1 */
5296         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5297
5298         switch (clock->p2) {
5299         case 5:
5300                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5301                 break;
5302         case 7:
5303                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5304                 break;
5305         case 10:
5306                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5307                 break;
5308         case 14:
5309                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5310                 break;
5311         }
5312
5313         if (is_sdvo && is_tv)
5314                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5315         else if (is_tv)
5316                 /* XXX: just matching BIOS for now */
5317                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5318                 dpll |= 3;
5319         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5320                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5321         else
5322                 dpll |= PLL_REF_INPUT_DREFCLK;
5323
5324         return dpll;
5325 }
5326
5327 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5328                                   struct drm_display_mode *mode,
5329                                   struct drm_display_mode *adjusted_mode,
5330                                   int x, int y,
5331                                   struct drm_framebuffer *fb)
5332 {
5333         struct drm_device *dev = crtc->dev;
5334         struct drm_i915_private *dev_priv = dev->dev_private;
5335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5336         int pipe = intel_crtc->pipe;
5337         int plane = intel_crtc->plane;
5338         int num_connectors = 0;
5339         intel_clock_t clock, reduced_clock;
5340         u32 dpll, fp = 0, fp2 = 0;
5341         bool ok, has_reduced_clock = false;
5342         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5343         struct intel_encoder *encoder;
5344         u32 temp;
5345         int ret;
5346         bool dither, fdi_config_ok;
5347
5348         for_each_encoder_on_crtc(dev, crtc, encoder) {
5349                 switch (encoder->type) {
5350                 case INTEL_OUTPUT_LVDS:
5351                         is_lvds = true;
5352                         break;
5353                 case INTEL_OUTPUT_DISPLAYPORT:
5354                         is_dp = true;
5355                         break;
5356                 case INTEL_OUTPUT_EDP:
5357                         is_dp = true;
5358                         if (!intel_encoder_is_pch_edp(&encoder->base))
5359                                 is_cpu_edp = true;
5360                         break;
5361                 }
5362
5363                 num_connectors++;
5364         }
5365
5366         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5367              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5368
5369         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5370                                      &has_reduced_clock, &reduced_clock);
5371         if (!ok) {
5372                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5373                 return -EINVAL;
5374         }
5375
5376         /* Ensure that the cursor is valid for the new mode before changing... */
5377         intel_crtc_update_cursor(crtc, true);
5378
5379         /* determine panel color depth */
5380         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5381                                               adjusted_mode);
5382         if (is_lvds && dev_priv->lvds_dither)
5383                 dither = true;
5384
5385         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5386         if (has_reduced_clock)
5387                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5388                         reduced_clock.m2;
5389
5390         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5391
5392         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5393         drm_mode_debug_printmodeline(mode);
5394
5395         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5396         if (!is_cpu_edp) {
5397                 struct intel_pch_pll *pll;
5398
5399                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5400                 if (pll == NULL) {
5401                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5402                                          pipe);
5403                         return -EINVAL;
5404                 }
5405         } else
5406                 intel_put_pch_pll(intel_crtc);
5407
5408         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5409          * This is an exception to the general rule that mode_set doesn't turn
5410          * things on.
5411          */
5412         if (is_lvds) {
5413                 temp = I915_READ(PCH_LVDS);
5414                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5415                 if (HAS_PCH_CPT(dev)) {
5416                         temp &= ~PORT_TRANS_SEL_MASK;
5417                         temp |= PORT_TRANS_SEL_CPT(pipe);
5418                 } else {
5419                         if (pipe == 1)
5420                                 temp |= LVDS_PIPEB_SELECT;
5421                         else
5422                                 temp &= ~LVDS_PIPEB_SELECT;
5423                 }
5424
5425                 /* set the corresponsding LVDS_BORDER bit */
5426                 temp |= dev_priv->lvds_border_bits;
5427                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5428                  * set the DPLLs for dual-channel mode or not.
5429                  */
5430                 if (clock.p2 == 7)
5431                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5432                 else
5433                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5434
5435                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5436                  * appropriately here, but we need to look more thoroughly into how
5437                  * panels behave in the two modes.
5438                  */
5439                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5440                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5441                         temp |= LVDS_HSYNC_POLARITY;
5442                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5443                         temp |= LVDS_VSYNC_POLARITY;
5444                 I915_WRITE(PCH_LVDS, temp);
5445         }
5446
5447         if (is_dp && !is_cpu_edp) {
5448                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5449         } else {
5450                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5451                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5452                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5453                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5454                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5455         }
5456
5457         if (intel_crtc->pch_pll) {
5458                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5459
5460                 /* Wait for the clocks to stabilize. */
5461                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5462                 udelay(150);
5463
5464                 /* The pixel multiplier can only be updated once the
5465                  * DPLL is enabled and the clocks are stable.
5466                  *
5467                  * So write it again.
5468                  */
5469                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5470         }
5471
5472         intel_crtc->lowfreq_avail = false;
5473         if (intel_crtc->pch_pll) {
5474                 if (is_lvds && has_reduced_clock && i915_powersave) {
5475                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5476                         intel_crtc->lowfreq_avail = true;
5477                 } else {
5478                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5479                 }
5480         }
5481
5482         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5483
5484         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5485          * ironlake_check_fdi_lanes. */
5486         ironlake_set_m_n(crtc, mode, adjusted_mode);
5487
5488         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5489
5490         if (is_cpu_edp)
5491                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5492
5493         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5494
5495         intel_wait_for_vblank(dev, pipe);
5496
5497         /* Set up the display plane register */
5498         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5499         POSTING_READ(DSPCNTR(plane));
5500
5501         ret = intel_pipe_set_base(crtc, x, y, fb);
5502
5503         intel_update_watermarks(dev);
5504
5505         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5506
5507         return fdi_config_ok ? ret : -EINVAL;
5508 }
5509
5510 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5511                                  struct drm_display_mode *mode,
5512                                  struct drm_display_mode *adjusted_mode,
5513                                  int x, int y,
5514                                  struct drm_framebuffer *fb)
5515 {
5516         struct drm_device *dev = crtc->dev;
5517         struct drm_i915_private *dev_priv = dev->dev_private;
5518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5519         int pipe = intel_crtc->pipe;
5520         int plane = intel_crtc->plane;
5521         int num_connectors = 0;
5522         intel_clock_t clock, reduced_clock;
5523         u32 dpll = 0, fp = 0, fp2 = 0;
5524         bool ok, has_reduced_clock = false;
5525         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5526         struct intel_encoder *encoder;
5527         u32 temp;
5528         int ret;
5529         bool dither;
5530
5531         for_each_encoder_on_crtc(dev, crtc, encoder) {
5532                 switch (encoder->type) {
5533                 case INTEL_OUTPUT_LVDS:
5534                         is_lvds = true;
5535                         break;
5536                 case INTEL_OUTPUT_DISPLAYPORT:
5537                         is_dp = true;
5538                         break;
5539                 case INTEL_OUTPUT_EDP:
5540                         is_dp = true;
5541                         if (!intel_encoder_is_pch_edp(&encoder->base))
5542                                 is_cpu_edp = true;
5543                         break;
5544                 }
5545
5546                 num_connectors++;
5547         }
5548
5549         if (is_cpu_edp)
5550                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5551         else
5552                 intel_crtc->cpu_transcoder = pipe;
5553
5554         /* We are not sure yet this won't happen. */
5555         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5556              INTEL_PCH_TYPE(dev));
5557
5558         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5559              num_connectors, pipe_name(pipe));
5560
5561         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5562                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5563
5564         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5565
5566         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5567                 return -EINVAL;
5568
5569         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5570                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5571                                              &has_reduced_clock,
5572                                              &reduced_clock);
5573                 if (!ok) {
5574                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5575                         return -EINVAL;
5576                 }
5577         }
5578
5579         /* Ensure that the cursor is valid for the new mode before changing... */
5580         intel_crtc_update_cursor(crtc, true);
5581
5582         /* determine panel color depth */
5583         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5584                                               adjusted_mode);
5585         if (is_lvds && dev_priv->lvds_dither)
5586                 dither = true;
5587
5588         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5589         drm_mode_debug_printmodeline(mode);
5590
5591         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5592                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5593                 if (has_reduced_clock)
5594                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5595                               reduced_clock.m2;
5596
5597                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5598                                              fp);
5599
5600                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5601                  * own on pre-Haswell/LPT generation */
5602                 if (!is_cpu_edp) {
5603                         struct intel_pch_pll *pll;
5604
5605                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5606                         if (pll == NULL) {
5607                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5608                                                  pipe);
5609                                 return -EINVAL;
5610                         }
5611                 } else
5612                         intel_put_pch_pll(intel_crtc);
5613
5614                 /* The LVDS pin pair needs to be on before the DPLLs are
5615                  * enabled.  This is an exception to the general rule that
5616                  * mode_set doesn't turn things on.
5617                  */
5618                 if (is_lvds) {
5619                         temp = I915_READ(PCH_LVDS);
5620                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5621                         if (HAS_PCH_CPT(dev)) {
5622                                 temp &= ~PORT_TRANS_SEL_MASK;
5623                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5624                         } else {
5625                                 if (pipe == 1)
5626                                         temp |= LVDS_PIPEB_SELECT;
5627                                 else
5628                                         temp &= ~LVDS_PIPEB_SELECT;
5629                         }
5630
5631                         /* set the corresponsding LVDS_BORDER bit */
5632                         temp |= dev_priv->lvds_border_bits;
5633                         /* Set the B0-B3 data pairs corresponding to whether
5634                          * we're going to set the DPLLs for dual-channel mode or
5635                          * not.
5636                          */
5637                         if (clock.p2 == 7)
5638                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5639                         else
5640                                 temp &= ~(LVDS_B0B3_POWER_UP |
5641                                           LVDS_CLKB_POWER_UP);
5642
5643                         /* It would be nice to set 24 vs 18-bit mode
5644                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5645                          * look more thoroughly into how panels behave in the
5646                          * two modes.
5647                          */
5648                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5649                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5650                                 temp |= LVDS_HSYNC_POLARITY;
5651                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5652                                 temp |= LVDS_VSYNC_POLARITY;
5653                         I915_WRITE(PCH_LVDS, temp);
5654                 }
5655         }
5656
5657         if (is_dp && !is_cpu_edp) {
5658                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5659         } else {
5660                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5661                         /* For non-DP output, clear any trans DP clock recovery
5662                          * setting.*/
5663                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5664                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5665                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5666                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5667                 }
5668         }
5669
5670         intel_crtc->lowfreq_avail = false;
5671         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5672                 if (intel_crtc->pch_pll) {
5673                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5674
5675                         /* Wait for the clocks to stabilize. */
5676                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5677                         udelay(150);
5678
5679                         /* The pixel multiplier can only be updated once the
5680                          * DPLL is enabled and the clocks are stable.
5681                          *
5682                          * So write it again.
5683                          */
5684                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5685                 }
5686
5687                 if (intel_crtc->pch_pll) {
5688                         if (is_lvds && has_reduced_clock && i915_powersave) {
5689                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5690                                 intel_crtc->lowfreq_avail = true;
5691                         } else {
5692                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5693                         }
5694                 }
5695         }
5696
5697         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5698
5699         if (!is_dp || is_cpu_edp)
5700                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5701
5702         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5703                 if (is_cpu_edp)
5704                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5705
5706         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5707
5708         /* Set up the display plane register */
5709         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5710         POSTING_READ(DSPCNTR(plane));
5711
5712         ret = intel_pipe_set_base(crtc, x, y, fb);
5713
5714         intel_update_watermarks(dev);
5715
5716         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5717
5718         return ret;
5719 }
5720
5721 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5722                                struct drm_display_mode *mode,
5723                                struct drm_display_mode *adjusted_mode,
5724                                int x, int y,
5725                                struct drm_framebuffer *fb)
5726 {
5727         struct drm_device *dev = crtc->dev;
5728         struct drm_i915_private *dev_priv = dev->dev_private;
5729         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5730         int pipe = intel_crtc->pipe;
5731         int ret;
5732
5733         drm_vblank_pre_modeset(dev, pipe);
5734
5735         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5736                                               x, y, fb);
5737         drm_vblank_post_modeset(dev, pipe);
5738
5739         return ret;
5740 }
5741
5742 static bool intel_eld_uptodate(struct drm_connector *connector,
5743                                int reg_eldv, uint32_t bits_eldv,
5744                                int reg_elda, uint32_t bits_elda,
5745                                int reg_edid)
5746 {
5747         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5748         uint8_t *eld = connector->eld;
5749         uint32_t i;
5750
5751         i = I915_READ(reg_eldv);
5752         i &= bits_eldv;
5753
5754         if (!eld[0])
5755                 return !i;
5756
5757         if (!i)
5758                 return false;
5759
5760         i = I915_READ(reg_elda);
5761         i &= ~bits_elda;
5762         I915_WRITE(reg_elda, i);
5763
5764         for (i = 0; i < eld[2]; i++)
5765                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5766                         return false;
5767
5768         return true;
5769 }
5770
5771 static void g4x_write_eld(struct drm_connector *connector,
5772                           struct drm_crtc *crtc)
5773 {
5774         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5775         uint8_t *eld = connector->eld;
5776         uint32_t eldv;
5777         uint32_t len;
5778         uint32_t i;
5779
5780         i = I915_READ(G4X_AUD_VID_DID);
5781
5782         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5783                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5784         else
5785                 eldv = G4X_ELDV_DEVCTG;
5786
5787         if (intel_eld_uptodate(connector,
5788                                G4X_AUD_CNTL_ST, eldv,
5789                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5790                                G4X_HDMIW_HDMIEDID))
5791                 return;
5792
5793         i = I915_READ(G4X_AUD_CNTL_ST);
5794         i &= ~(eldv | G4X_ELD_ADDR);
5795         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5796         I915_WRITE(G4X_AUD_CNTL_ST, i);
5797
5798         if (!eld[0])
5799                 return;
5800
5801         len = min_t(uint8_t, eld[2], len);
5802         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5803         for (i = 0; i < len; i++)
5804                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5805
5806         i = I915_READ(G4X_AUD_CNTL_ST);
5807         i |= eldv;
5808         I915_WRITE(G4X_AUD_CNTL_ST, i);
5809 }
5810
5811 static void haswell_write_eld(struct drm_connector *connector,
5812                                      struct drm_crtc *crtc)
5813 {
5814         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5815         uint8_t *eld = connector->eld;
5816         struct drm_device *dev = crtc->dev;
5817         uint32_t eldv;
5818         uint32_t i;
5819         int len;
5820         int pipe = to_intel_crtc(crtc)->pipe;
5821         int tmp;
5822
5823         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5824         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5825         int aud_config = HSW_AUD_CFG(pipe);
5826         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5827
5828
5829         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5830
5831         /* Audio output enable */
5832         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5833         tmp = I915_READ(aud_cntrl_st2);
5834         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5835         I915_WRITE(aud_cntrl_st2, tmp);
5836
5837         /* Wait for 1 vertical blank */
5838         intel_wait_for_vblank(dev, pipe);
5839
5840         /* Set ELD valid state */
5841         tmp = I915_READ(aud_cntrl_st2);
5842         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5843         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5844         I915_WRITE(aud_cntrl_st2, tmp);
5845         tmp = I915_READ(aud_cntrl_st2);
5846         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5847
5848         /* Enable HDMI mode */
5849         tmp = I915_READ(aud_config);
5850         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5851         /* clear N_programing_enable and N_value_index */
5852         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5853         I915_WRITE(aud_config, tmp);
5854
5855         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5856
5857         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5858
5859         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5860                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5861                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5862                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5863         } else
5864                 I915_WRITE(aud_config, 0);
5865
5866         if (intel_eld_uptodate(connector,
5867                                aud_cntrl_st2, eldv,
5868                                aud_cntl_st, IBX_ELD_ADDRESS,
5869                                hdmiw_hdmiedid))
5870                 return;
5871
5872         i = I915_READ(aud_cntrl_st2);
5873         i &= ~eldv;
5874         I915_WRITE(aud_cntrl_st2, i);
5875
5876         if (!eld[0])
5877                 return;
5878
5879         i = I915_READ(aud_cntl_st);
5880         i &= ~IBX_ELD_ADDRESS;
5881         I915_WRITE(aud_cntl_st, i);
5882         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5883         DRM_DEBUG_DRIVER("port num:%d\n", i);
5884
5885         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5886         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5887         for (i = 0; i < len; i++)
5888                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5889
5890         i = I915_READ(aud_cntrl_st2);
5891         i |= eldv;
5892         I915_WRITE(aud_cntrl_st2, i);
5893
5894 }
5895
5896 static void ironlake_write_eld(struct drm_connector *connector,
5897                                      struct drm_crtc *crtc)
5898 {
5899         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900         uint8_t *eld = connector->eld;
5901         uint32_t eldv;
5902         uint32_t i;
5903         int len;
5904         int hdmiw_hdmiedid;
5905         int aud_config;
5906         int aud_cntl_st;
5907         int aud_cntrl_st2;
5908         int pipe = to_intel_crtc(crtc)->pipe;
5909
5910         if (HAS_PCH_IBX(connector->dev)) {
5911                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5912                 aud_config = IBX_AUD_CFG(pipe);
5913                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5914                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5915         } else {
5916                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5917                 aud_config = CPT_AUD_CFG(pipe);
5918                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5919                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5920         }
5921
5922         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5923
5924         i = I915_READ(aud_cntl_st);
5925         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5926         if (!i) {
5927                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5928                 /* operate blindly on all ports */
5929                 eldv = IBX_ELD_VALIDB;
5930                 eldv |= IBX_ELD_VALIDB << 4;
5931                 eldv |= IBX_ELD_VALIDB << 8;
5932         } else {
5933                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5934                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5935         }
5936
5937         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5938                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5939                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5940                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5941         } else
5942                 I915_WRITE(aud_config, 0);
5943
5944         if (intel_eld_uptodate(connector,
5945                                aud_cntrl_st2, eldv,
5946                                aud_cntl_st, IBX_ELD_ADDRESS,
5947                                hdmiw_hdmiedid))
5948                 return;
5949
5950         i = I915_READ(aud_cntrl_st2);
5951         i &= ~eldv;
5952         I915_WRITE(aud_cntrl_st2, i);
5953
5954         if (!eld[0])
5955                 return;
5956
5957         i = I915_READ(aud_cntl_st);
5958         i &= ~IBX_ELD_ADDRESS;
5959         I915_WRITE(aud_cntl_st, i);
5960
5961         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5962         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5963         for (i = 0; i < len; i++)
5964                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5965
5966         i = I915_READ(aud_cntrl_st2);
5967         i |= eldv;
5968         I915_WRITE(aud_cntrl_st2, i);
5969 }
5970
5971 void intel_write_eld(struct drm_encoder *encoder,
5972                      struct drm_display_mode *mode)
5973 {
5974         struct drm_crtc *crtc = encoder->crtc;
5975         struct drm_connector *connector;
5976         struct drm_device *dev = encoder->dev;
5977         struct drm_i915_private *dev_priv = dev->dev_private;
5978
5979         connector = drm_select_eld(encoder, mode);
5980         if (!connector)
5981                 return;
5982
5983         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5984                          connector->base.id,
5985                          drm_get_connector_name(connector),
5986                          connector->encoder->base.id,
5987                          drm_get_encoder_name(connector->encoder));
5988
5989         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5990
5991         if (dev_priv->display.write_eld)
5992                 dev_priv->display.write_eld(connector, crtc);
5993 }
5994
5995 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5996 void intel_crtc_load_lut(struct drm_crtc *crtc)
5997 {
5998         struct drm_device *dev = crtc->dev;
5999         struct drm_i915_private *dev_priv = dev->dev_private;
6000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001         int palreg = PALETTE(intel_crtc->pipe);
6002         int i;
6003
6004         /* The clocks have to be on to load the palette. */
6005         if (!crtc->enabled || !intel_crtc->active)
6006                 return;
6007
6008         /* use legacy palette for Ironlake */
6009         if (HAS_PCH_SPLIT(dev))
6010                 palreg = LGC_PALETTE(intel_crtc->pipe);
6011
6012         for (i = 0; i < 256; i++) {
6013                 I915_WRITE(palreg + 4 * i,
6014                            (intel_crtc->lut_r[i] << 16) |
6015                            (intel_crtc->lut_g[i] << 8) |
6016                            intel_crtc->lut_b[i]);
6017         }
6018 }
6019
6020 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6021 {
6022         struct drm_device *dev = crtc->dev;
6023         struct drm_i915_private *dev_priv = dev->dev_private;
6024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6025         bool visible = base != 0;
6026         u32 cntl;
6027
6028         if (intel_crtc->cursor_visible == visible)
6029                 return;
6030
6031         cntl = I915_READ(_CURACNTR);
6032         if (visible) {
6033                 /* On these chipsets we can only modify the base whilst
6034                  * the cursor is disabled.
6035                  */
6036                 I915_WRITE(_CURABASE, base);
6037
6038                 cntl &= ~(CURSOR_FORMAT_MASK);
6039                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6040                 cntl |= CURSOR_ENABLE |
6041                         CURSOR_GAMMA_ENABLE |
6042                         CURSOR_FORMAT_ARGB;
6043         } else
6044                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6045         I915_WRITE(_CURACNTR, cntl);
6046
6047         intel_crtc->cursor_visible = visible;
6048 }
6049
6050 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6051 {
6052         struct drm_device *dev = crtc->dev;
6053         struct drm_i915_private *dev_priv = dev->dev_private;
6054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6055         int pipe = intel_crtc->pipe;
6056         bool visible = base != 0;
6057
6058         if (intel_crtc->cursor_visible != visible) {
6059                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6060                 if (base) {
6061                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6062                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6063                         cntl |= pipe << 28; /* Connect to correct pipe */
6064                 } else {
6065                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6066                         cntl |= CURSOR_MODE_DISABLE;
6067                 }
6068                 I915_WRITE(CURCNTR(pipe), cntl);
6069
6070                 intel_crtc->cursor_visible = visible;
6071         }
6072         /* and commit changes on next vblank */
6073         I915_WRITE(CURBASE(pipe), base);
6074 }
6075
6076 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6077 {
6078         struct drm_device *dev = crtc->dev;
6079         struct drm_i915_private *dev_priv = dev->dev_private;
6080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6081         int pipe = intel_crtc->pipe;
6082         bool visible = base != 0;
6083
6084         if (intel_crtc->cursor_visible != visible) {
6085                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6086                 if (base) {
6087                         cntl &= ~CURSOR_MODE;
6088                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6089                 } else {
6090                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6091                         cntl |= CURSOR_MODE_DISABLE;
6092                 }
6093                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6094
6095                 intel_crtc->cursor_visible = visible;
6096         }
6097         /* and commit changes on next vblank */
6098         I915_WRITE(CURBASE_IVB(pipe), base);
6099 }
6100
6101 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6102 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6103                                      bool on)
6104 {
6105         struct drm_device *dev = crtc->dev;
6106         struct drm_i915_private *dev_priv = dev->dev_private;
6107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108         int pipe = intel_crtc->pipe;
6109         int x = intel_crtc->cursor_x;
6110         int y = intel_crtc->cursor_y;
6111         u32 base, pos;
6112         bool visible;
6113
6114         pos = 0;
6115
6116         if (on && crtc->enabled && crtc->fb) {
6117                 base = intel_crtc->cursor_addr;
6118                 if (x > (int) crtc->fb->width)
6119                         base = 0;
6120
6121                 if (y > (int) crtc->fb->height)
6122                         base = 0;
6123         } else
6124                 base = 0;
6125
6126         if (x < 0) {
6127                 if (x + intel_crtc->cursor_width < 0)
6128                         base = 0;
6129
6130                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6131                 x = -x;
6132         }
6133         pos |= x << CURSOR_X_SHIFT;
6134
6135         if (y < 0) {
6136                 if (y + intel_crtc->cursor_height < 0)
6137                         base = 0;
6138
6139                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6140                 y = -y;
6141         }
6142         pos |= y << CURSOR_Y_SHIFT;
6143
6144         visible = base != 0;
6145         if (!visible && !intel_crtc->cursor_visible)
6146                 return;
6147
6148         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6149                 I915_WRITE(CURPOS_IVB(pipe), pos);
6150                 ivb_update_cursor(crtc, base);
6151         } else {
6152                 I915_WRITE(CURPOS(pipe), pos);
6153                 if (IS_845G(dev) || IS_I865G(dev))
6154                         i845_update_cursor(crtc, base);
6155                 else
6156                         i9xx_update_cursor(crtc, base);
6157         }
6158 }
6159
6160 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6161                                  struct drm_file *file,
6162                                  uint32_t handle,
6163                                  uint32_t width, uint32_t height)
6164 {
6165         struct drm_device *dev = crtc->dev;
6166         struct drm_i915_private *dev_priv = dev->dev_private;
6167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6168         struct drm_i915_gem_object *obj;
6169         uint32_t addr;
6170         int ret;
6171
6172         /* if we want to turn off the cursor ignore width and height */
6173         if (!handle) {
6174                 DRM_DEBUG_KMS("cursor off\n");
6175                 addr = 0;
6176                 obj = NULL;
6177                 mutex_lock(&dev->struct_mutex);
6178                 goto finish;
6179         }
6180
6181         /* Currently we only support 64x64 cursors */
6182         if (width != 64 || height != 64) {
6183                 DRM_ERROR("we currently only support 64x64 cursors\n");
6184                 return -EINVAL;
6185         }
6186
6187         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6188         if (&obj->base == NULL)
6189                 return -ENOENT;
6190
6191         if (obj->base.size < width * height * 4) {
6192                 DRM_ERROR("buffer is to small\n");
6193                 ret = -ENOMEM;
6194                 goto fail;
6195         }
6196
6197         /* we only need to pin inside GTT if cursor is non-phy */
6198         mutex_lock(&dev->struct_mutex);
6199         if (!dev_priv->info->cursor_needs_physical) {
6200                 if (obj->tiling_mode) {
6201                         DRM_ERROR("cursor cannot be tiled\n");
6202                         ret = -EINVAL;
6203                         goto fail_locked;
6204                 }
6205
6206                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6207                 if (ret) {
6208                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6209                         goto fail_locked;
6210                 }
6211
6212                 ret = i915_gem_object_put_fence(obj);
6213                 if (ret) {
6214                         DRM_ERROR("failed to release fence for cursor");
6215                         goto fail_unpin;
6216                 }
6217
6218                 addr = obj->gtt_offset;
6219         } else {
6220                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6221                 ret = i915_gem_attach_phys_object(dev, obj,
6222                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6223                                                   align);
6224                 if (ret) {
6225                         DRM_ERROR("failed to attach phys object\n");
6226                         goto fail_locked;
6227                 }
6228                 addr = obj->phys_obj->handle->busaddr;
6229         }
6230
6231         if (IS_GEN2(dev))
6232                 I915_WRITE(CURSIZE, (height << 12) | width);
6233
6234  finish:
6235         if (intel_crtc->cursor_bo) {
6236                 if (dev_priv->info->cursor_needs_physical) {
6237                         if (intel_crtc->cursor_bo != obj)
6238                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6239                 } else
6240                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6241                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6242         }
6243
6244         mutex_unlock(&dev->struct_mutex);
6245
6246         intel_crtc->cursor_addr = addr;
6247         intel_crtc->cursor_bo = obj;
6248         intel_crtc->cursor_width = width;
6249         intel_crtc->cursor_height = height;
6250
6251         intel_crtc_update_cursor(crtc, true);
6252
6253         return 0;
6254 fail_unpin:
6255         i915_gem_object_unpin(obj);
6256 fail_locked:
6257         mutex_unlock(&dev->struct_mutex);
6258 fail:
6259         drm_gem_object_unreference_unlocked(&obj->base);
6260         return ret;
6261 }
6262
6263 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6264 {
6265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266
6267         intel_crtc->cursor_x = x;
6268         intel_crtc->cursor_y = y;
6269
6270         intel_crtc_update_cursor(crtc, true);
6271
6272         return 0;
6273 }
6274
6275 /** Sets the color ramps on behalf of RandR */
6276 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6277                                  u16 blue, int regno)
6278 {
6279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6280
6281         intel_crtc->lut_r[regno] = red >> 8;
6282         intel_crtc->lut_g[regno] = green >> 8;
6283         intel_crtc->lut_b[regno] = blue >> 8;
6284 }
6285
6286 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6287                              u16 *blue, int regno)
6288 {
6289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290
6291         *red = intel_crtc->lut_r[regno] << 8;
6292         *green = intel_crtc->lut_g[regno] << 8;
6293         *blue = intel_crtc->lut_b[regno] << 8;
6294 }
6295
6296 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6297                                  u16 *blue, uint32_t start, uint32_t size)
6298 {
6299         int end = (start + size > 256) ? 256 : start + size, i;
6300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6301
6302         for (i = start; i < end; i++) {
6303                 intel_crtc->lut_r[i] = red[i] >> 8;
6304                 intel_crtc->lut_g[i] = green[i] >> 8;
6305                 intel_crtc->lut_b[i] = blue[i] >> 8;
6306         }
6307
6308         intel_crtc_load_lut(crtc);
6309 }
6310
6311 /**
6312  * Get a pipe with a simple mode set on it for doing load-based monitor
6313  * detection.
6314  *
6315  * It will be up to the load-detect code to adjust the pipe as appropriate for
6316  * its requirements.  The pipe will be connected to no other encoders.
6317  *
6318  * Currently this code will only succeed if there is a pipe with no encoders
6319  * configured for it.  In the future, it could choose to temporarily disable
6320  * some outputs to free up a pipe for its use.
6321  *
6322  * \return crtc, or NULL if no pipes are available.
6323  */
6324
6325 /* VESA 640x480x72Hz mode to set on the pipe */
6326 static struct drm_display_mode load_detect_mode = {
6327         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6328                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6329 };
6330
6331 static struct drm_framebuffer *
6332 intel_framebuffer_create(struct drm_device *dev,
6333                          struct drm_mode_fb_cmd2 *mode_cmd,
6334                          struct drm_i915_gem_object *obj)
6335 {
6336         struct intel_framebuffer *intel_fb;
6337         int ret;
6338
6339         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6340         if (!intel_fb) {
6341                 drm_gem_object_unreference_unlocked(&obj->base);
6342                 return ERR_PTR(-ENOMEM);
6343         }
6344
6345         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6346         if (ret) {
6347                 drm_gem_object_unreference_unlocked(&obj->base);
6348                 kfree(intel_fb);
6349                 return ERR_PTR(ret);
6350         }
6351
6352         return &intel_fb->base;
6353 }
6354
6355 static u32
6356 intel_framebuffer_pitch_for_width(int width, int bpp)
6357 {
6358         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6359         return ALIGN(pitch, 64);
6360 }
6361
6362 static u32
6363 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6364 {
6365         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6366         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6367 }
6368
6369 static struct drm_framebuffer *
6370 intel_framebuffer_create_for_mode(struct drm_device *dev,
6371                                   struct drm_display_mode *mode,
6372                                   int depth, int bpp)
6373 {
6374         struct drm_i915_gem_object *obj;
6375         struct drm_mode_fb_cmd2 mode_cmd;
6376
6377         obj = i915_gem_alloc_object(dev,
6378                                     intel_framebuffer_size_for_mode(mode, bpp));
6379         if (obj == NULL)
6380                 return ERR_PTR(-ENOMEM);
6381
6382         mode_cmd.width = mode->hdisplay;
6383         mode_cmd.height = mode->vdisplay;
6384         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6385                                                                 bpp);
6386         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6387
6388         return intel_framebuffer_create(dev, &mode_cmd, obj);
6389 }
6390
6391 static struct drm_framebuffer *
6392 mode_fits_in_fbdev(struct drm_device *dev,
6393                    struct drm_display_mode *mode)
6394 {
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         struct drm_i915_gem_object *obj;
6397         struct drm_framebuffer *fb;
6398
6399         if (dev_priv->fbdev == NULL)
6400                 return NULL;
6401
6402         obj = dev_priv->fbdev->ifb.obj;
6403         if (obj == NULL)
6404                 return NULL;
6405
6406         fb = &dev_priv->fbdev->ifb.base;
6407         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6408                                                                fb->bits_per_pixel))
6409                 return NULL;
6410
6411         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6412                 return NULL;
6413
6414         return fb;
6415 }
6416
6417 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6418                                 struct drm_display_mode *mode,
6419                                 struct intel_load_detect_pipe *old)
6420 {
6421         struct intel_crtc *intel_crtc;
6422         struct intel_encoder *intel_encoder =
6423                 intel_attached_encoder(connector);
6424         struct drm_crtc *possible_crtc;
6425         struct drm_encoder *encoder = &intel_encoder->base;
6426         struct drm_crtc *crtc = NULL;
6427         struct drm_device *dev = encoder->dev;
6428         struct drm_framebuffer *fb;
6429         int i = -1;
6430
6431         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6432                       connector->base.id, drm_get_connector_name(connector),
6433                       encoder->base.id, drm_get_encoder_name(encoder));
6434
6435         /*
6436          * Algorithm gets a little messy:
6437          *
6438          *   - if the connector already has an assigned crtc, use it (but make
6439          *     sure it's on first)
6440          *
6441          *   - try to find the first unused crtc that can drive this connector,
6442          *     and use that if we find one
6443          */
6444
6445         /* See if we already have a CRTC for this connector */
6446         if (encoder->crtc) {
6447                 crtc = encoder->crtc;
6448
6449                 old->dpms_mode = connector->dpms;
6450                 old->load_detect_temp = false;
6451
6452                 /* Make sure the crtc and connector are running */
6453                 if (connector->dpms != DRM_MODE_DPMS_ON)
6454                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6455
6456                 return true;
6457         }
6458
6459         /* Find an unused one (if possible) */
6460         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6461                 i++;
6462                 if (!(encoder->possible_crtcs & (1 << i)))
6463                         continue;
6464                 if (!possible_crtc->enabled) {
6465                         crtc = possible_crtc;
6466                         break;
6467                 }
6468         }
6469
6470         /*
6471          * If we didn't find an unused CRTC, don't use any.
6472          */
6473         if (!crtc) {
6474                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6475                 return false;
6476         }
6477
6478         intel_encoder->new_crtc = to_intel_crtc(crtc);
6479         to_intel_connector(connector)->new_encoder = intel_encoder;
6480
6481         intel_crtc = to_intel_crtc(crtc);
6482         old->dpms_mode = connector->dpms;
6483         old->load_detect_temp = true;
6484         old->release_fb = NULL;
6485
6486         if (!mode)
6487                 mode = &load_detect_mode;
6488
6489         /* We need a framebuffer large enough to accommodate all accesses
6490          * that the plane may generate whilst we perform load detection.
6491          * We can not rely on the fbcon either being present (we get called
6492          * during its initialisation to detect all boot displays, or it may
6493          * not even exist) or that it is large enough to satisfy the
6494          * requested mode.
6495          */
6496         fb = mode_fits_in_fbdev(dev, mode);
6497         if (fb == NULL) {
6498                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6499                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6500                 old->release_fb = fb;
6501         } else
6502                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6503         if (IS_ERR(fb)) {
6504                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6505                 goto fail;
6506         }
6507
6508         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6509                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6510                 if (old->release_fb)
6511                         old->release_fb->funcs->destroy(old->release_fb);
6512                 goto fail;
6513         }
6514
6515         /* let the connector get through one full cycle before testing */
6516         intel_wait_for_vblank(dev, intel_crtc->pipe);
6517
6518         return true;
6519 fail:
6520         connector->encoder = NULL;
6521         encoder->crtc = NULL;
6522         return false;
6523 }
6524
6525 void intel_release_load_detect_pipe(struct drm_connector *connector,
6526                                     struct intel_load_detect_pipe *old)
6527 {
6528         struct intel_encoder *intel_encoder =
6529                 intel_attached_encoder(connector);
6530         struct drm_encoder *encoder = &intel_encoder->base;
6531
6532         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6533                       connector->base.id, drm_get_connector_name(connector),
6534                       encoder->base.id, drm_get_encoder_name(encoder));
6535
6536         if (old->load_detect_temp) {
6537                 struct drm_crtc *crtc = encoder->crtc;
6538
6539                 to_intel_connector(connector)->new_encoder = NULL;
6540                 intel_encoder->new_crtc = NULL;
6541                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6542
6543                 if (old->release_fb)
6544                         old->release_fb->funcs->destroy(old->release_fb);
6545
6546                 return;
6547         }
6548
6549         /* Switch crtc and encoder back off if necessary */
6550         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6551                 connector->funcs->dpms(connector, old->dpms_mode);
6552 }
6553
6554 /* Returns the clock of the currently programmed mode of the given pipe. */
6555 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6556 {
6557         struct drm_i915_private *dev_priv = dev->dev_private;
6558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559         int pipe = intel_crtc->pipe;
6560         u32 dpll = I915_READ(DPLL(pipe));
6561         u32 fp;
6562         intel_clock_t clock;
6563
6564         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6565                 fp = I915_READ(FP0(pipe));
6566         else
6567                 fp = I915_READ(FP1(pipe));
6568
6569         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6570         if (IS_PINEVIEW(dev)) {
6571                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6572                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6573         } else {
6574                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6575                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6576         }
6577
6578         if (!IS_GEN2(dev)) {
6579                 if (IS_PINEVIEW(dev))
6580                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6581                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6582                 else
6583                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6584                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6585
6586                 switch (dpll & DPLL_MODE_MASK) {
6587                 case DPLLB_MODE_DAC_SERIAL:
6588                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6589                                 5 : 10;
6590                         break;
6591                 case DPLLB_MODE_LVDS:
6592                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6593                                 7 : 14;
6594                         break;
6595                 default:
6596                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6597                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6598                         return 0;
6599                 }
6600
6601                 /* XXX: Handle the 100Mhz refclk */
6602                 intel_clock(dev, 96000, &clock);
6603         } else {
6604                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6605
6606                 if (is_lvds) {
6607                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6608                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6609                         clock.p2 = 14;
6610
6611                         if ((dpll & PLL_REF_INPUT_MASK) ==
6612                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6613                                 /* XXX: might not be 66MHz */
6614                                 intel_clock(dev, 66000, &clock);
6615                         } else
6616                                 intel_clock(dev, 48000, &clock);
6617                 } else {
6618                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6619                                 clock.p1 = 2;
6620                         else {
6621                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6622                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6623                         }
6624                         if (dpll & PLL_P2_DIVIDE_BY_4)
6625                                 clock.p2 = 4;
6626                         else
6627                                 clock.p2 = 2;
6628
6629                         intel_clock(dev, 48000, &clock);
6630                 }
6631         }
6632
6633         /* XXX: It would be nice to validate the clocks, but we can't reuse
6634          * i830PllIsValid() because it relies on the xf86_config connector
6635          * configuration being accurate, which it isn't necessarily.
6636          */
6637
6638         return clock.dot;
6639 }
6640
6641 /** Returns the currently programmed mode of the given pipe. */
6642 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6643                                              struct drm_crtc *crtc)
6644 {
6645         struct drm_i915_private *dev_priv = dev->dev_private;
6646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6647         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6648         struct drm_display_mode *mode;
6649         int htot = I915_READ(HTOTAL(cpu_transcoder));
6650         int hsync = I915_READ(HSYNC(cpu_transcoder));
6651         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6652         int vsync = I915_READ(VSYNC(cpu_transcoder));
6653
6654         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6655         if (!mode)
6656                 return NULL;
6657
6658         mode->clock = intel_crtc_clock_get(dev, crtc);
6659         mode->hdisplay = (htot & 0xffff) + 1;
6660         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6661         mode->hsync_start = (hsync & 0xffff) + 1;
6662         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6663         mode->vdisplay = (vtot & 0xffff) + 1;
6664         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6665         mode->vsync_start = (vsync & 0xffff) + 1;
6666         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6667
6668         drm_mode_set_name(mode);
6669
6670         return mode;
6671 }
6672
6673 static void intel_increase_pllclock(struct drm_crtc *crtc)
6674 {
6675         struct drm_device *dev = crtc->dev;
6676         drm_i915_private_t *dev_priv = dev->dev_private;
6677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6678         int pipe = intel_crtc->pipe;
6679         int dpll_reg = DPLL(pipe);
6680         int dpll;
6681
6682         if (HAS_PCH_SPLIT(dev))
6683                 return;
6684
6685         if (!dev_priv->lvds_downclock_avail)
6686                 return;
6687
6688         dpll = I915_READ(dpll_reg);
6689         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6690                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6691
6692                 assert_panel_unlocked(dev_priv, pipe);
6693
6694                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6695                 I915_WRITE(dpll_reg, dpll);
6696                 intel_wait_for_vblank(dev, pipe);
6697
6698                 dpll = I915_READ(dpll_reg);
6699                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6700                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6701         }
6702 }
6703
6704 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6705 {
6706         struct drm_device *dev = crtc->dev;
6707         drm_i915_private_t *dev_priv = dev->dev_private;
6708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6709
6710         if (HAS_PCH_SPLIT(dev))
6711                 return;
6712
6713         if (!dev_priv->lvds_downclock_avail)
6714                 return;
6715
6716         /*
6717          * Since this is called by a timer, we should never get here in
6718          * the manual case.
6719          */
6720         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6721                 int pipe = intel_crtc->pipe;
6722                 int dpll_reg = DPLL(pipe);
6723                 int dpll;
6724
6725                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6726
6727                 assert_panel_unlocked(dev_priv, pipe);
6728
6729                 dpll = I915_READ(dpll_reg);
6730                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6731                 I915_WRITE(dpll_reg, dpll);
6732                 intel_wait_for_vblank(dev, pipe);
6733                 dpll = I915_READ(dpll_reg);
6734                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6735                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6736         }
6737
6738 }
6739
6740 void intel_mark_busy(struct drm_device *dev)
6741 {
6742         i915_update_gfx_val(dev->dev_private);
6743 }
6744
6745 void intel_mark_idle(struct drm_device *dev)
6746 {
6747 }
6748
6749 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6750 {
6751         struct drm_device *dev = obj->base.dev;
6752         struct drm_crtc *crtc;
6753
6754         if (!i915_powersave)
6755                 return;
6756
6757         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6758                 if (!crtc->fb)
6759                         continue;
6760
6761                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6762                         intel_increase_pllclock(crtc);
6763         }
6764 }
6765
6766 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6767 {
6768         struct drm_device *dev = obj->base.dev;
6769         struct drm_crtc *crtc;
6770
6771         if (!i915_powersave)
6772                 return;
6773
6774         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6775                 if (!crtc->fb)
6776                         continue;
6777
6778                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6779                         intel_decrease_pllclock(crtc);
6780         }
6781 }
6782
6783 static void intel_crtc_destroy(struct drm_crtc *crtc)
6784 {
6785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6786         struct drm_device *dev = crtc->dev;
6787         struct intel_unpin_work *work;
6788         unsigned long flags;
6789
6790         spin_lock_irqsave(&dev->event_lock, flags);
6791         work = intel_crtc->unpin_work;
6792         intel_crtc->unpin_work = NULL;
6793         spin_unlock_irqrestore(&dev->event_lock, flags);
6794
6795         if (work) {
6796                 cancel_work_sync(&work->work);
6797                 kfree(work);
6798         }
6799
6800         drm_crtc_cleanup(crtc);
6801
6802         kfree(intel_crtc);
6803 }
6804
6805 static void intel_unpin_work_fn(struct work_struct *__work)
6806 {
6807         struct intel_unpin_work *work =
6808                 container_of(__work, struct intel_unpin_work, work);
6809
6810         mutex_lock(&work->dev->struct_mutex);
6811         intel_unpin_fb_obj(work->old_fb_obj);
6812         drm_gem_object_unreference(&work->pending_flip_obj->base);
6813         drm_gem_object_unreference(&work->old_fb_obj->base);
6814
6815         intel_update_fbc(work->dev);
6816         mutex_unlock(&work->dev->struct_mutex);
6817         kfree(work);
6818 }
6819
6820 static void do_intel_finish_page_flip(struct drm_device *dev,
6821                                       struct drm_crtc *crtc)
6822 {
6823         drm_i915_private_t *dev_priv = dev->dev_private;
6824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6825         struct intel_unpin_work *work;
6826         struct drm_i915_gem_object *obj;
6827         struct drm_pending_vblank_event *e;
6828         struct timeval tvbl;
6829         unsigned long flags;
6830
6831         /* Ignore early vblank irqs */
6832         if (intel_crtc == NULL)
6833                 return;
6834
6835         spin_lock_irqsave(&dev->event_lock, flags);
6836         work = intel_crtc->unpin_work;
6837         if (work == NULL || !work->pending) {
6838                 spin_unlock_irqrestore(&dev->event_lock, flags);
6839                 return;
6840         }
6841
6842         intel_crtc->unpin_work = NULL;
6843
6844         if (work->event) {
6845                 e = work->event;
6846                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6847
6848                 e->event.tv_sec = tvbl.tv_sec;
6849                 e->event.tv_usec = tvbl.tv_usec;
6850
6851                 list_add_tail(&e->base.link,
6852                               &e->base.file_priv->event_list);
6853                 wake_up_interruptible(&e->base.file_priv->event_wait);
6854         }
6855
6856         drm_vblank_put(dev, intel_crtc->pipe);
6857
6858         spin_unlock_irqrestore(&dev->event_lock, flags);
6859
6860         obj = work->old_fb_obj;
6861
6862         atomic_clear_mask(1 << intel_crtc->plane,
6863                           &obj->pending_flip.counter);
6864
6865         wake_up(&dev_priv->pending_flip_queue);
6866         schedule_work(&work->work);
6867
6868         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6869 }
6870
6871 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6872 {
6873         drm_i915_private_t *dev_priv = dev->dev_private;
6874         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6875
6876         do_intel_finish_page_flip(dev, crtc);
6877 }
6878
6879 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6880 {
6881         drm_i915_private_t *dev_priv = dev->dev_private;
6882         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6883
6884         do_intel_finish_page_flip(dev, crtc);
6885 }
6886
6887 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6888 {
6889         drm_i915_private_t *dev_priv = dev->dev_private;
6890         struct intel_crtc *intel_crtc =
6891                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6892         unsigned long flags;
6893
6894         spin_lock_irqsave(&dev->event_lock, flags);
6895         if (intel_crtc->unpin_work) {
6896                 if ((++intel_crtc->unpin_work->pending) > 1)
6897                         DRM_ERROR("Prepared flip multiple times\n");
6898         } else {
6899                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6900         }
6901         spin_unlock_irqrestore(&dev->event_lock, flags);
6902 }
6903
6904 static int intel_gen2_queue_flip(struct drm_device *dev,
6905                                  struct drm_crtc *crtc,
6906                                  struct drm_framebuffer *fb,
6907                                  struct drm_i915_gem_object *obj)
6908 {
6909         struct drm_i915_private *dev_priv = dev->dev_private;
6910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911         u32 flip_mask;
6912         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6913         int ret;
6914
6915         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6916         if (ret)
6917                 goto err;
6918
6919         ret = intel_ring_begin(ring, 6);
6920         if (ret)
6921                 goto err_unpin;
6922
6923         /* Can't queue multiple flips, so wait for the previous
6924          * one to finish before executing the next.
6925          */
6926         if (intel_crtc->plane)
6927                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6928         else
6929                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6930         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6931         intel_ring_emit(ring, MI_NOOP);
6932         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6933                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6934         intel_ring_emit(ring, fb->pitches[0]);
6935         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6936         intel_ring_emit(ring, 0); /* aux display base address, unused */
6937         intel_ring_advance(ring);
6938         return 0;
6939
6940 err_unpin:
6941         intel_unpin_fb_obj(obj);
6942 err:
6943         return ret;
6944 }
6945
6946 static int intel_gen3_queue_flip(struct drm_device *dev,
6947                                  struct drm_crtc *crtc,
6948                                  struct drm_framebuffer *fb,
6949                                  struct drm_i915_gem_object *obj)
6950 {
6951         struct drm_i915_private *dev_priv = dev->dev_private;
6952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6953         u32 flip_mask;
6954         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6955         int ret;
6956
6957         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6958         if (ret)
6959                 goto err;
6960
6961         ret = intel_ring_begin(ring, 6);
6962         if (ret)
6963                 goto err_unpin;
6964
6965         if (intel_crtc->plane)
6966                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6967         else
6968                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6969         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6970         intel_ring_emit(ring, MI_NOOP);
6971         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6972                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6973         intel_ring_emit(ring, fb->pitches[0]);
6974         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6975         intel_ring_emit(ring, MI_NOOP);
6976
6977         intel_ring_advance(ring);
6978         return 0;
6979
6980 err_unpin:
6981         intel_unpin_fb_obj(obj);
6982 err:
6983         return ret;
6984 }
6985
6986 static int intel_gen4_queue_flip(struct drm_device *dev,
6987                                  struct drm_crtc *crtc,
6988                                  struct drm_framebuffer *fb,
6989                                  struct drm_i915_gem_object *obj)
6990 {
6991         struct drm_i915_private *dev_priv = dev->dev_private;
6992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993         uint32_t pf, pipesrc;
6994         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6995         int ret;
6996
6997         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6998         if (ret)
6999                 goto err;
7000
7001         ret = intel_ring_begin(ring, 4);
7002         if (ret)
7003                 goto err_unpin;
7004
7005         /* i965+ uses the linear or tiled offsets from the
7006          * Display Registers (which do not change across a page-flip)
7007          * so we need only reprogram the base address.
7008          */
7009         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7010                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7011         intel_ring_emit(ring, fb->pitches[0]);
7012         intel_ring_emit(ring,
7013                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7014                         obj->tiling_mode);
7015
7016         /* XXX Enabling the panel-fitter across page-flip is so far
7017          * untested on non-native modes, so ignore it for now.
7018          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7019          */
7020         pf = 0;
7021         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7022         intel_ring_emit(ring, pf | pipesrc);
7023         intel_ring_advance(ring);
7024         return 0;
7025
7026 err_unpin:
7027         intel_unpin_fb_obj(obj);
7028 err:
7029         return ret;
7030 }
7031
7032 static int intel_gen6_queue_flip(struct drm_device *dev,
7033                                  struct drm_crtc *crtc,
7034                                  struct drm_framebuffer *fb,
7035                                  struct drm_i915_gem_object *obj)
7036 {
7037         struct drm_i915_private *dev_priv = dev->dev_private;
7038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7039         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7040         uint32_t pf, pipesrc;
7041         int ret;
7042
7043         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7044         if (ret)
7045                 goto err;
7046
7047         ret = intel_ring_begin(ring, 4);
7048         if (ret)
7049                 goto err_unpin;
7050
7051         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7052                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7053         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7054         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7055
7056         /* Contrary to the suggestions in the documentation,
7057          * "Enable Panel Fitter" does not seem to be required when page
7058          * flipping with a non-native mode, and worse causes a normal
7059          * modeset to fail.
7060          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7061          */
7062         pf = 0;
7063         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7064         intel_ring_emit(ring, pf | pipesrc);
7065         intel_ring_advance(ring);
7066         return 0;
7067
7068 err_unpin:
7069         intel_unpin_fb_obj(obj);
7070 err:
7071         return ret;
7072 }
7073
7074 /*
7075  * On gen7 we currently use the blit ring because (in early silicon at least)
7076  * the render ring doesn't give us interrpts for page flip completion, which
7077  * means clients will hang after the first flip is queued.  Fortunately the
7078  * blit ring generates interrupts properly, so use it instead.
7079  */
7080 static int intel_gen7_queue_flip(struct drm_device *dev,
7081                                  struct drm_crtc *crtc,
7082                                  struct drm_framebuffer *fb,
7083                                  struct drm_i915_gem_object *obj)
7084 {
7085         struct drm_i915_private *dev_priv = dev->dev_private;
7086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7087         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7088         uint32_t plane_bit = 0;
7089         int ret;
7090
7091         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7092         if (ret)
7093                 goto err;
7094
7095         switch(intel_crtc->plane) {
7096         case PLANE_A:
7097                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7098                 break;
7099         case PLANE_B:
7100                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7101                 break;
7102         case PLANE_C:
7103                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7104                 break;
7105         default:
7106                 WARN_ONCE(1, "unknown plane in flip command\n");
7107                 ret = -ENODEV;
7108                 goto err_unpin;
7109         }
7110
7111         ret = intel_ring_begin(ring, 4);
7112         if (ret)
7113                 goto err_unpin;
7114
7115         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7116         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7117         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7118         intel_ring_emit(ring, (MI_NOOP));
7119         intel_ring_advance(ring);
7120         return 0;
7121
7122 err_unpin:
7123         intel_unpin_fb_obj(obj);
7124 err:
7125         return ret;
7126 }
7127
7128 static int intel_default_queue_flip(struct drm_device *dev,
7129                                     struct drm_crtc *crtc,
7130                                     struct drm_framebuffer *fb,
7131                                     struct drm_i915_gem_object *obj)
7132 {
7133         return -ENODEV;
7134 }
7135
7136 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7137                                 struct drm_framebuffer *fb,
7138                                 struct drm_pending_vblank_event *event)
7139 {
7140         struct drm_device *dev = crtc->dev;
7141         struct drm_i915_private *dev_priv = dev->dev_private;
7142         struct intel_framebuffer *intel_fb;
7143         struct drm_i915_gem_object *obj;
7144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145         struct intel_unpin_work *work;
7146         unsigned long flags;
7147         int ret;
7148
7149         /* Can't change pixel format via MI display flips. */
7150         if (fb->pixel_format != crtc->fb->pixel_format)
7151                 return -EINVAL;
7152
7153         /*
7154          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7155          * Note that pitch changes could also affect these register.
7156          */
7157         if (INTEL_INFO(dev)->gen > 3 &&
7158             (fb->offsets[0] != crtc->fb->offsets[0] ||
7159              fb->pitches[0] != crtc->fb->pitches[0]))
7160                 return -EINVAL;
7161
7162         work = kzalloc(sizeof *work, GFP_KERNEL);
7163         if (work == NULL)
7164                 return -ENOMEM;
7165
7166         work->event = event;
7167         work->dev = crtc->dev;
7168         intel_fb = to_intel_framebuffer(crtc->fb);
7169         work->old_fb_obj = intel_fb->obj;
7170         INIT_WORK(&work->work, intel_unpin_work_fn);
7171
7172         ret = drm_vblank_get(dev, intel_crtc->pipe);
7173         if (ret)
7174                 goto free_work;
7175
7176         /* We borrow the event spin lock for protecting unpin_work */
7177         spin_lock_irqsave(&dev->event_lock, flags);
7178         if (intel_crtc->unpin_work) {
7179                 spin_unlock_irqrestore(&dev->event_lock, flags);
7180                 kfree(work);
7181                 drm_vblank_put(dev, intel_crtc->pipe);
7182
7183                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7184                 return -EBUSY;
7185         }
7186         intel_crtc->unpin_work = work;
7187         spin_unlock_irqrestore(&dev->event_lock, flags);
7188
7189         intel_fb = to_intel_framebuffer(fb);
7190         obj = intel_fb->obj;
7191
7192         ret = i915_mutex_lock_interruptible(dev);
7193         if (ret)
7194                 goto cleanup;
7195
7196         /* Reference the objects for the scheduled work. */
7197         drm_gem_object_reference(&work->old_fb_obj->base);
7198         drm_gem_object_reference(&obj->base);
7199
7200         crtc->fb = fb;
7201
7202         work->pending_flip_obj = obj;
7203
7204         work->enable_stall_check = true;
7205
7206         /* Block clients from rendering to the new back buffer until
7207          * the flip occurs and the object is no longer visible.
7208          */
7209         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7210
7211         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7212         if (ret)
7213                 goto cleanup_pending;
7214
7215         intel_disable_fbc(dev);
7216         intel_mark_fb_busy(obj);
7217         mutex_unlock(&dev->struct_mutex);
7218
7219         trace_i915_flip_request(intel_crtc->plane, obj);
7220
7221         return 0;
7222
7223 cleanup_pending:
7224         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7225         drm_gem_object_unreference(&work->old_fb_obj->base);
7226         drm_gem_object_unreference(&obj->base);
7227         mutex_unlock(&dev->struct_mutex);
7228
7229 cleanup:
7230         spin_lock_irqsave(&dev->event_lock, flags);
7231         intel_crtc->unpin_work = NULL;
7232         spin_unlock_irqrestore(&dev->event_lock, flags);
7233
7234         drm_vblank_put(dev, intel_crtc->pipe);
7235 free_work:
7236         kfree(work);
7237
7238         return ret;
7239 }
7240
7241 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7242         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7243         .load_lut = intel_crtc_load_lut,
7244         .disable = intel_crtc_noop,
7245 };
7246
7247 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7248 {
7249         struct intel_encoder *other_encoder;
7250         struct drm_crtc *crtc = &encoder->new_crtc->base;
7251
7252         if (WARN_ON(!crtc))
7253                 return false;
7254
7255         list_for_each_entry(other_encoder,
7256                             &crtc->dev->mode_config.encoder_list,
7257                             base.head) {
7258
7259                 if (&other_encoder->new_crtc->base != crtc ||
7260                     encoder == other_encoder)
7261                         continue;
7262                 else
7263                         return true;
7264         }
7265
7266         return false;
7267 }
7268
7269 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7270                                   struct drm_crtc *crtc)
7271 {
7272         struct drm_device *dev;
7273         struct drm_crtc *tmp;
7274         int crtc_mask = 1;
7275
7276         WARN(!crtc, "checking null crtc?\n");
7277
7278         dev = crtc->dev;
7279
7280         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7281                 if (tmp == crtc)
7282                         break;
7283                 crtc_mask <<= 1;
7284         }
7285
7286         if (encoder->possible_crtcs & crtc_mask)
7287                 return true;
7288         return false;
7289 }
7290
7291 /**
7292  * intel_modeset_update_staged_output_state
7293  *
7294  * Updates the staged output configuration state, e.g. after we've read out the
7295  * current hw state.
7296  */
7297 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7298 {
7299         struct intel_encoder *encoder;
7300         struct intel_connector *connector;
7301
7302         list_for_each_entry(connector, &dev->mode_config.connector_list,
7303                             base.head) {
7304                 connector->new_encoder =
7305                         to_intel_encoder(connector->base.encoder);
7306         }
7307
7308         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7309                             base.head) {
7310                 encoder->new_crtc =
7311                         to_intel_crtc(encoder->base.crtc);
7312         }
7313 }
7314
7315 /**
7316  * intel_modeset_commit_output_state
7317  *
7318  * This function copies the stage display pipe configuration to the real one.
7319  */
7320 static void intel_modeset_commit_output_state(struct drm_device *dev)
7321 {
7322         struct intel_encoder *encoder;
7323         struct intel_connector *connector;
7324
7325         list_for_each_entry(connector, &dev->mode_config.connector_list,
7326                             base.head) {
7327                 connector->base.encoder = &connector->new_encoder->base;
7328         }
7329
7330         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7331                             base.head) {
7332                 encoder->base.crtc = &encoder->new_crtc->base;
7333         }
7334 }
7335
7336 static struct drm_display_mode *
7337 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7338                             struct drm_display_mode *mode)
7339 {
7340         struct drm_device *dev = crtc->dev;
7341         struct drm_display_mode *adjusted_mode;
7342         struct drm_encoder_helper_funcs *encoder_funcs;
7343         struct intel_encoder *encoder;
7344
7345         adjusted_mode = drm_mode_duplicate(dev, mode);
7346         if (!adjusted_mode)
7347                 return ERR_PTR(-ENOMEM);
7348
7349         /* Pass our mode to the connectors and the CRTC to give them a chance to
7350          * adjust it according to limitations or connector properties, and also
7351          * a chance to reject the mode entirely.
7352          */
7353         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7354                             base.head) {
7355
7356                 if (&encoder->new_crtc->base != crtc)
7357                         continue;
7358                 encoder_funcs = encoder->base.helper_private;
7359                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7360                                                 adjusted_mode))) {
7361                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7362                         goto fail;
7363                 }
7364         }
7365
7366         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7367                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7368                 goto fail;
7369         }
7370         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7371
7372         return adjusted_mode;
7373 fail:
7374         drm_mode_destroy(dev, adjusted_mode);
7375         return ERR_PTR(-EINVAL);
7376 }
7377
7378 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7379  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7380 static void
7381 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7382                              unsigned *prepare_pipes, unsigned *disable_pipes)
7383 {
7384         struct intel_crtc *intel_crtc;
7385         struct drm_device *dev = crtc->dev;
7386         struct intel_encoder *encoder;
7387         struct intel_connector *connector;
7388         struct drm_crtc *tmp_crtc;
7389
7390         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7391
7392         /* Check which crtcs have changed outputs connected to them, these need
7393          * to be part of the prepare_pipes mask. We don't (yet) support global
7394          * modeset across multiple crtcs, so modeset_pipes will only have one
7395          * bit set at most. */
7396         list_for_each_entry(connector, &dev->mode_config.connector_list,
7397                             base.head) {
7398                 if (connector->base.encoder == &connector->new_encoder->base)
7399                         continue;
7400
7401                 if (connector->base.encoder) {
7402                         tmp_crtc = connector->base.encoder->crtc;
7403
7404                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7405                 }
7406
7407                 if (connector->new_encoder)
7408                         *prepare_pipes |=
7409                                 1 << connector->new_encoder->new_crtc->pipe;
7410         }
7411
7412         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7413                             base.head) {
7414                 if (encoder->base.crtc == &encoder->new_crtc->base)
7415                         continue;
7416
7417                 if (encoder->base.crtc) {
7418                         tmp_crtc = encoder->base.crtc;
7419
7420                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7421                 }
7422
7423                 if (encoder->new_crtc)
7424                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7425         }
7426
7427         /* Check for any pipes that will be fully disabled ... */
7428         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7429                             base.head) {
7430                 bool used = false;
7431
7432                 /* Don't try to disable disabled crtcs. */
7433                 if (!intel_crtc->base.enabled)
7434                         continue;
7435
7436                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7437                                     base.head) {
7438                         if (encoder->new_crtc == intel_crtc)
7439                                 used = true;
7440                 }
7441
7442                 if (!used)
7443                         *disable_pipes |= 1 << intel_crtc->pipe;
7444         }
7445
7446
7447         /* set_mode is also used to update properties on life display pipes. */
7448         intel_crtc = to_intel_crtc(crtc);
7449         if (crtc->enabled)
7450                 *prepare_pipes |= 1 << intel_crtc->pipe;
7451
7452         /* We only support modeset on one single crtc, hence we need to do that
7453          * only for the passed in crtc iff we change anything else than just
7454          * disable crtcs.
7455          *
7456          * This is actually not true, to be fully compatible with the old crtc
7457          * helper we automatically disable _any_ output (i.e. doesn't need to be
7458          * connected to the crtc we're modesetting on) if it's disconnected.
7459          * Which is a rather nutty api (since changed the output configuration
7460          * without userspace's explicit request can lead to confusion), but
7461          * alas. Hence we currently need to modeset on all pipes we prepare. */
7462         if (*prepare_pipes)
7463                 *modeset_pipes = *prepare_pipes;
7464
7465         /* ... and mask these out. */
7466         *modeset_pipes &= ~(*disable_pipes);
7467         *prepare_pipes &= ~(*disable_pipes);
7468 }
7469
7470 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7471 {
7472         struct drm_encoder *encoder;
7473         struct drm_device *dev = crtc->dev;
7474
7475         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7476                 if (encoder->crtc == crtc)
7477                         return true;
7478
7479         return false;
7480 }
7481
7482 static void
7483 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7484 {
7485         struct intel_encoder *intel_encoder;
7486         struct intel_crtc *intel_crtc;
7487         struct drm_connector *connector;
7488
7489         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7490                             base.head) {
7491                 if (!intel_encoder->base.crtc)
7492                         continue;
7493
7494                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7495
7496                 if (prepare_pipes & (1 << intel_crtc->pipe))
7497                         intel_encoder->connectors_active = false;
7498         }
7499
7500         intel_modeset_commit_output_state(dev);
7501
7502         /* Update computed state. */
7503         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7504                             base.head) {
7505                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7506         }
7507
7508         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7509                 if (!connector->encoder || !connector->encoder->crtc)
7510                         continue;
7511
7512                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7513
7514                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7515                         struct drm_property *dpms_property =
7516                                 dev->mode_config.dpms_property;
7517
7518                         connector->dpms = DRM_MODE_DPMS_ON;
7519                         drm_connector_property_set_value(connector,
7520                                                          dpms_property,
7521                                                          DRM_MODE_DPMS_ON);
7522
7523                         intel_encoder = to_intel_encoder(connector->encoder);
7524                         intel_encoder->connectors_active = true;
7525                 }
7526         }
7527
7528 }
7529
7530 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7531         list_for_each_entry((intel_crtc), \
7532                             &(dev)->mode_config.crtc_list, \
7533                             base.head) \
7534                 if (mask & (1 <<(intel_crtc)->pipe)) \
7535
7536 void
7537 intel_modeset_check_state(struct drm_device *dev)
7538 {
7539         struct intel_crtc *crtc;
7540         struct intel_encoder *encoder;
7541         struct intel_connector *connector;
7542
7543         list_for_each_entry(connector, &dev->mode_config.connector_list,
7544                             base.head) {
7545                 /* This also checks the encoder/connector hw state with the
7546                  * ->get_hw_state callbacks. */
7547                 intel_connector_check_state(connector);
7548
7549                 WARN(&connector->new_encoder->base != connector->base.encoder,
7550                      "connector's staged encoder doesn't match current encoder\n");
7551         }
7552
7553         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7554                             base.head) {
7555                 bool enabled = false;
7556                 bool active = false;
7557                 enum pipe pipe, tracked_pipe;
7558
7559                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7560                               encoder->base.base.id,
7561                               drm_get_encoder_name(&encoder->base));
7562
7563                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7564                      "encoder's stage crtc doesn't match current crtc\n");
7565                 WARN(encoder->connectors_active && !encoder->base.crtc,
7566                      "encoder's active_connectors set, but no crtc\n");
7567
7568                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7569                                     base.head) {
7570                         if (connector->base.encoder != &encoder->base)
7571                                 continue;
7572                         enabled = true;
7573                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7574                                 active = true;
7575                 }
7576                 WARN(!!encoder->base.crtc != enabled,
7577                      "encoder's enabled state mismatch "
7578                      "(expected %i, found %i)\n",
7579                      !!encoder->base.crtc, enabled);
7580                 WARN(active && !encoder->base.crtc,
7581                      "active encoder with no crtc\n");
7582
7583                 WARN(encoder->connectors_active != active,
7584                      "encoder's computed active state doesn't match tracked active state "
7585                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7586
7587                 active = encoder->get_hw_state(encoder, &pipe);
7588                 WARN(active != encoder->connectors_active,
7589                      "encoder's hw state doesn't match sw tracking "
7590                      "(expected %i, found %i)\n",
7591                      encoder->connectors_active, active);
7592
7593                 if (!encoder->base.crtc)
7594                         continue;
7595
7596                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7597                 WARN(active && pipe != tracked_pipe,
7598                      "active encoder's pipe doesn't match"
7599                      "(expected %i, found %i)\n",
7600                      tracked_pipe, pipe);
7601
7602         }
7603
7604         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7605                             base.head) {
7606                 bool enabled = false;
7607                 bool active = false;
7608
7609                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7610                               crtc->base.base.id);
7611
7612                 WARN(crtc->active && !crtc->base.enabled,
7613                      "active crtc, but not enabled in sw tracking\n");
7614
7615                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7616                                     base.head) {
7617                         if (encoder->base.crtc != &crtc->base)
7618                                 continue;
7619                         enabled = true;
7620                         if (encoder->connectors_active)
7621                                 active = true;
7622                 }
7623                 WARN(active != crtc->active,
7624                      "crtc's computed active state doesn't match tracked active state "
7625                      "(expected %i, found %i)\n", active, crtc->active);
7626                 WARN(enabled != crtc->base.enabled,
7627                      "crtc's computed enabled state doesn't match tracked enabled state "
7628                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7629
7630                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7631         }
7632 }
7633
7634 bool intel_set_mode(struct drm_crtc *crtc,
7635                     struct drm_display_mode *mode,
7636                     int x, int y, struct drm_framebuffer *fb)
7637 {
7638         struct drm_device *dev = crtc->dev;
7639         drm_i915_private_t *dev_priv = dev->dev_private;
7640         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7641         struct drm_encoder_helper_funcs *encoder_funcs;
7642         struct drm_encoder *encoder;
7643         struct intel_crtc *intel_crtc;
7644         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7645         bool ret = true;
7646
7647         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7648                                      &prepare_pipes, &disable_pipes);
7649
7650         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7651                       modeset_pipes, prepare_pipes, disable_pipes);
7652
7653         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7654                 intel_crtc_disable(&intel_crtc->base);
7655
7656         saved_hwmode = crtc->hwmode;
7657         saved_mode = crtc->mode;
7658
7659         /* Hack: Because we don't (yet) support global modeset on multiple
7660          * crtcs, we don't keep track of the new mode for more than one crtc.
7661          * Hence simply check whether any bit is set in modeset_pipes in all the
7662          * pieces of code that are not yet converted to deal with mutliple crtcs
7663          * changing their mode at the same time. */
7664         adjusted_mode = NULL;
7665         if (modeset_pipes) {
7666                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7667                 if (IS_ERR(adjusted_mode)) {
7668                         return false;
7669                 }
7670         }
7671
7672         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7673                 if (intel_crtc->base.enabled)
7674                         dev_priv->display.crtc_disable(&intel_crtc->base);
7675         }
7676
7677         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7678          * to set it here already despite that we pass it down the callchain.
7679          */
7680         if (modeset_pipes)
7681                 crtc->mode = *mode;
7682
7683         /* Only after disabling all output pipelines that will be changed can we
7684          * update the the output configuration. */
7685         intel_modeset_update_state(dev, prepare_pipes);
7686
7687         if (dev_priv->display.modeset_global_resources)
7688                 dev_priv->display.modeset_global_resources(dev);
7689
7690         /* Set up the DPLL and any encoders state that needs to adjust or depend
7691          * on the DPLL.
7692          */
7693         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7694                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7695                                            mode, adjusted_mode,
7696                                            x, y, fb);
7697                 if (!ret)
7698                     goto done;
7699
7700                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7701
7702                         if (encoder->crtc != &intel_crtc->base)
7703                                 continue;
7704
7705                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7706                                 encoder->base.id, drm_get_encoder_name(encoder),
7707                                 mode->base.id, mode->name);
7708                         encoder_funcs = encoder->helper_private;
7709                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7710                 }
7711         }
7712
7713         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7714         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7715                 dev_priv->display.crtc_enable(&intel_crtc->base);
7716
7717         if (modeset_pipes) {
7718                 /* Store real post-adjustment hardware mode. */
7719                 crtc->hwmode = *adjusted_mode;
7720
7721                 /* Calculate and store various constants which
7722                  * are later needed by vblank and swap-completion
7723                  * timestamping. They are derived from true hwmode.
7724                  */
7725                 drm_calc_timestamping_constants(crtc);
7726         }
7727
7728         /* FIXME: add subpixel order */
7729 done:
7730         drm_mode_destroy(dev, adjusted_mode);
7731         if (!ret && crtc->enabled) {
7732                 crtc->hwmode = saved_hwmode;
7733                 crtc->mode = saved_mode;
7734         } else {
7735                 intel_modeset_check_state(dev);
7736         }
7737
7738         return ret;
7739 }
7740
7741 #undef for_each_intel_crtc_masked
7742
7743 static void intel_set_config_free(struct intel_set_config *config)
7744 {
7745         if (!config)
7746                 return;
7747
7748         kfree(config->save_connector_encoders);
7749         kfree(config->save_encoder_crtcs);
7750         kfree(config);
7751 }
7752
7753 static int intel_set_config_save_state(struct drm_device *dev,
7754                                        struct intel_set_config *config)
7755 {
7756         struct drm_encoder *encoder;
7757         struct drm_connector *connector;
7758         int count;
7759
7760         config->save_encoder_crtcs =
7761                 kcalloc(dev->mode_config.num_encoder,
7762                         sizeof(struct drm_crtc *), GFP_KERNEL);
7763         if (!config->save_encoder_crtcs)
7764                 return -ENOMEM;
7765
7766         config->save_connector_encoders =
7767                 kcalloc(dev->mode_config.num_connector,
7768                         sizeof(struct drm_encoder *), GFP_KERNEL);
7769         if (!config->save_connector_encoders)
7770                 return -ENOMEM;
7771
7772         /* Copy data. Note that driver private data is not affected.
7773          * Should anything bad happen only the expected state is
7774          * restored, not the drivers personal bookkeeping.
7775          */
7776         count = 0;
7777         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7778                 config->save_encoder_crtcs[count++] = encoder->crtc;
7779         }
7780
7781         count = 0;
7782         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7783                 config->save_connector_encoders[count++] = connector->encoder;
7784         }
7785
7786         return 0;
7787 }
7788
7789 static void intel_set_config_restore_state(struct drm_device *dev,
7790                                            struct intel_set_config *config)
7791 {
7792         struct intel_encoder *encoder;
7793         struct intel_connector *connector;
7794         int count;
7795
7796         count = 0;
7797         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7798                 encoder->new_crtc =
7799                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7800         }
7801
7802         count = 0;
7803         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7804                 connector->new_encoder =
7805                         to_intel_encoder(config->save_connector_encoders[count++]);
7806         }
7807 }
7808
7809 static void
7810 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7811                                       struct intel_set_config *config)
7812 {
7813
7814         /* We should be able to check here if the fb has the same properties
7815          * and then just flip_or_move it */
7816         if (set->crtc->fb != set->fb) {
7817                 /* If we have no fb then treat it as a full mode set */
7818                 if (set->crtc->fb == NULL) {
7819                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7820                         config->mode_changed = true;
7821                 } else if (set->fb == NULL) {
7822                         config->mode_changed = true;
7823                 } else if (set->fb->depth != set->crtc->fb->depth) {
7824                         config->mode_changed = true;
7825                 } else if (set->fb->bits_per_pixel !=
7826                            set->crtc->fb->bits_per_pixel) {
7827                         config->mode_changed = true;
7828                 } else
7829                         config->fb_changed = true;
7830         }
7831
7832         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7833                 config->fb_changed = true;
7834
7835         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7836                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7837                 drm_mode_debug_printmodeline(&set->crtc->mode);
7838                 drm_mode_debug_printmodeline(set->mode);
7839                 config->mode_changed = true;
7840         }
7841 }
7842
7843 static int
7844 intel_modeset_stage_output_state(struct drm_device *dev,
7845                                  struct drm_mode_set *set,
7846                                  struct intel_set_config *config)
7847 {
7848         struct drm_crtc *new_crtc;
7849         struct intel_connector *connector;
7850         struct intel_encoder *encoder;
7851         int count, ro;
7852
7853         /* The upper layers ensure that we either disabl a crtc or have a list
7854          * of connectors. For paranoia, double-check this. */
7855         WARN_ON(!set->fb && (set->num_connectors != 0));
7856         WARN_ON(set->fb && (set->num_connectors == 0));
7857
7858         count = 0;
7859         list_for_each_entry(connector, &dev->mode_config.connector_list,
7860                             base.head) {
7861                 /* Otherwise traverse passed in connector list and get encoders
7862                  * for them. */
7863                 for (ro = 0; ro < set->num_connectors; ro++) {
7864                         if (set->connectors[ro] == &connector->base) {
7865                                 connector->new_encoder = connector->encoder;
7866                                 break;
7867                         }
7868                 }
7869
7870                 /* If we disable the crtc, disable all its connectors. Also, if
7871                  * the connector is on the changing crtc but not on the new
7872                  * connector list, disable it. */
7873                 if ((!set->fb || ro == set->num_connectors) &&
7874                     connector->base.encoder &&
7875                     connector->base.encoder->crtc == set->crtc) {
7876                         connector->new_encoder = NULL;
7877
7878                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7879                                 connector->base.base.id,
7880                                 drm_get_connector_name(&connector->base));
7881                 }
7882
7883
7884                 if (&connector->new_encoder->base != connector->base.encoder) {
7885                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7886                         config->mode_changed = true;
7887                 }
7888
7889                 /* Disable all disconnected encoders. */
7890                 if (connector->base.status == connector_status_disconnected)
7891                         connector->new_encoder = NULL;
7892         }
7893         /* connector->new_encoder is now updated for all connectors. */
7894
7895         /* Update crtc of enabled connectors. */
7896         count = 0;
7897         list_for_each_entry(connector, &dev->mode_config.connector_list,
7898                             base.head) {
7899                 if (!connector->new_encoder)
7900                         continue;
7901
7902                 new_crtc = connector->new_encoder->base.crtc;
7903
7904                 for (ro = 0; ro < set->num_connectors; ro++) {
7905                         if (set->connectors[ro] == &connector->base)
7906                                 new_crtc = set->crtc;
7907                 }
7908
7909                 /* Make sure the new CRTC will work with the encoder */
7910                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7911                                            new_crtc)) {
7912                         return -EINVAL;
7913                 }
7914                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7915
7916                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7917                         connector->base.base.id,
7918                         drm_get_connector_name(&connector->base),
7919                         new_crtc->base.id);
7920         }
7921
7922         /* Check for any encoders that needs to be disabled. */
7923         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7924                             base.head) {
7925                 list_for_each_entry(connector,
7926                                     &dev->mode_config.connector_list,
7927                                     base.head) {
7928                         if (connector->new_encoder == encoder) {
7929                                 WARN_ON(!connector->new_encoder->new_crtc);
7930
7931                                 goto next_encoder;
7932                         }
7933                 }
7934                 encoder->new_crtc = NULL;
7935 next_encoder:
7936                 /* Only now check for crtc changes so we don't miss encoders
7937                  * that will be disabled. */
7938                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7939                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7940                         config->mode_changed = true;
7941                 }
7942         }
7943         /* Now we've also updated encoder->new_crtc for all encoders. */
7944
7945         return 0;
7946 }
7947
7948 static int intel_crtc_set_config(struct drm_mode_set *set)
7949 {
7950         struct drm_device *dev;
7951         struct drm_mode_set save_set;
7952         struct intel_set_config *config;
7953         int ret;
7954
7955         BUG_ON(!set);
7956         BUG_ON(!set->crtc);
7957         BUG_ON(!set->crtc->helper_private);
7958
7959         if (!set->mode)
7960                 set->fb = NULL;
7961
7962         /* The fb helper likes to play gross jokes with ->mode_set_config.
7963          * Unfortunately the crtc helper doesn't do much at all for this case,
7964          * so we have to cope with this madness until the fb helper is fixed up. */
7965         if (set->fb && set->num_connectors == 0)
7966                 return 0;
7967
7968         if (set->fb) {
7969                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7970                                 set->crtc->base.id, set->fb->base.id,
7971                                 (int)set->num_connectors, set->x, set->y);
7972         } else {
7973                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7974         }
7975
7976         dev = set->crtc->dev;
7977
7978         ret = -ENOMEM;
7979         config = kzalloc(sizeof(*config), GFP_KERNEL);
7980         if (!config)
7981                 goto out_config;
7982
7983         ret = intel_set_config_save_state(dev, config);
7984         if (ret)
7985                 goto out_config;
7986
7987         save_set.crtc = set->crtc;
7988         save_set.mode = &set->crtc->mode;
7989         save_set.x = set->crtc->x;
7990         save_set.y = set->crtc->y;
7991         save_set.fb = set->crtc->fb;
7992
7993         /* Compute whether we need a full modeset, only an fb base update or no
7994          * change at all. In the future we might also check whether only the
7995          * mode changed, e.g. for LVDS where we only change the panel fitter in
7996          * such cases. */
7997         intel_set_config_compute_mode_changes(set, config);
7998
7999         ret = intel_modeset_stage_output_state(dev, set, config);
8000         if (ret)
8001                 goto fail;
8002
8003         if (config->mode_changed) {
8004                 if (set->mode) {
8005                         DRM_DEBUG_KMS("attempting to set mode from"
8006                                         " userspace\n");
8007                         drm_mode_debug_printmodeline(set->mode);
8008                 }
8009
8010                 if (!intel_set_mode(set->crtc, set->mode,
8011                                     set->x, set->y, set->fb)) {
8012                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8013                                   set->crtc->base.id);
8014                         ret = -EINVAL;
8015                         goto fail;
8016                 }
8017         } else if (config->fb_changed) {
8018                 ret = intel_pipe_set_base(set->crtc,
8019                                           set->x, set->y, set->fb);
8020         }
8021
8022         intel_set_config_free(config);
8023
8024         return 0;
8025
8026 fail:
8027         intel_set_config_restore_state(dev, config);
8028
8029         /* Try to restore the config */
8030         if (config->mode_changed &&
8031             !intel_set_mode(save_set.crtc, save_set.mode,
8032                             save_set.x, save_set.y, save_set.fb))
8033                 DRM_ERROR("failed to restore config after modeset failure\n");
8034
8035 out_config:
8036         intel_set_config_free(config);
8037         return ret;
8038 }
8039
8040 static const struct drm_crtc_funcs intel_crtc_funcs = {
8041         .cursor_set = intel_crtc_cursor_set,
8042         .cursor_move = intel_crtc_cursor_move,
8043         .gamma_set = intel_crtc_gamma_set,
8044         .set_config = intel_crtc_set_config,
8045         .destroy = intel_crtc_destroy,
8046         .page_flip = intel_crtc_page_flip,
8047 };
8048
8049 static void intel_cpu_pll_init(struct drm_device *dev)
8050 {
8051         if (IS_HASWELL(dev))
8052                 intel_ddi_pll_init(dev);
8053 }
8054
8055 static void intel_pch_pll_init(struct drm_device *dev)
8056 {
8057         drm_i915_private_t *dev_priv = dev->dev_private;
8058         int i;
8059
8060         if (dev_priv->num_pch_pll == 0) {
8061                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8062                 return;
8063         }
8064
8065         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8066                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8067                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8068                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8069         }
8070 }
8071
8072 static void intel_crtc_init(struct drm_device *dev, int pipe)
8073 {
8074         drm_i915_private_t *dev_priv = dev->dev_private;
8075         struct intel_crtc *intel_crtc;
8076         int i;
8077
8078         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8079         if (intel_crtc == NULL)
8080                 return;
8081
8082         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8083
8084         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8085         for (i = 0; i < 256; i++) {
8086                 intel_crtc->lut_r[i] = i;
8087                 intel_crtc->lut_g[i] = i;
8088                 intel_crtc->lut_b[i] = i;
8089         }
8090
8091         /* Swap pipes & planes for FBC on pre-965 */
8092         intel_crtc->pipe = pipe;
8093         intel_crtc->plane = pipe;
8094         intel_crtc->cpu_transcoder = pipe;
8095         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8096                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8097                 intel_crtc->plane = !pipe;
8098         }
8099
8100         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8101                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8102         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8103         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8104
8105         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8106
8107         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8108 }
8109
8110 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8111                                 struct drm_file *file)
8112 {
8113         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8114         struct drm_mode_object *drmmode_obj;
8115         struct intel_crtc *crtc;
8116
8117         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8118                 return -ENODEV;
8119
8120         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8121                         DRM_MODE_OBJECT_CRTC);
8122
8123         if (!drmmode_obj) {
8124                 DRM_ERROR("no such CRTC id\n");
8125                 return -EINVAL;
8126         }
8127
8128         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8129         pipe_from_crtc_id->pipe = crtc->pipe;
8130
8131         return 0;
8132 }
8133
8134 static int intel_encoder_clones(struct intel_encoder *encoder)
8135 {
8136         struct drm_device *dev = encoder->base.dev;
8137         struct intel_encoder *source_encoder;
8138         int index_mask = 0;
8139         int entry = 0;
8140
8141         list_for_each_entry(source_encoder,
8142                             &dev->mode_config.encoder_list, base.head) {
8143
8144                 if (encoder == source_encoder)
8145                         index_mask |= (1 << entry);
8146
8147                 /* Intel hw has only one MUX where enocoders could be cloned. */
8148                 if (encoder->cloneable && source_encoder->cloneable)
8149                         index_mask |= (1 << entry);
8150
8151                 entry++;
8152         }
8153
8154         return index_mask;
8155 }
8156
8157 static bool has_edp_a(struct drm_device *dev)
8158 {
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160
8161         if (!IS_MOBILE(dev))
8162                 return false;
8163
8164         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8165                 return false;
8166
8167         if (IS_GEN5(dev) &&
8168             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8169                 return false;
8170
8171         return true;
8172 }
8173
8174 static void intel_setup_outputs(struct drm_device *dev)
8175 {
8176         struct drm_i915_private *dev_priv = dev->dev_private;
8177         struct intel_encoder *encoder;
8178         bool dpd_is_edp = false;
8179         bool has_lvds;
8180
8181         has_lvds = intel_lvds_init(dev);
8182         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8183                 /* disable the panel fitter on everything but LVDS */
8184                 I915_WRITE(PFIT_CONTROL, 0);
8185         }
8186
8187         if (HAS_PCH_SPLIT(dev)) {
8188                 dpd_is_edp = intel_dpd_is_edp(dev);
8189
8190                 if (has_edp_a(dev))
8191                         intel_dp_init(dev, DP_A, PORT_A);
8192
8193                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8194                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8195         }
8196
8197         intel_crt_init(dev);
8198
8199         if (IS_HASWELL(dev)) {
8200                 int found;
8201
8202                 /* Haswell uses DDI functions to detect digital outputs */
8203                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8204                 /* DDI A only supports eDP */
8205                 if (found)
8206                         intel_ddi_init(dev, PORT_A);
8207
8208                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8209                  * register */
8210                 found = I915_READ(SFUSE_STRAP);
8211
8212                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8213                         intel_ddi_init(dev, PORT_B);
8214                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8215                         intel_ddi_init(dev, PORT_C);
8216                 if (found & SFUSE_STRAP_DDID_DETECTED)
8217                         intel_ddi_init(dev, PORT_D);
8218         } else if (HAS_PCH_SPLIT(dev)) {
8219                 int found;
8220
8221                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8222                         /* PCH SDVOB multiplex with HDMIB */
8223                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8224                         if (!found)
8225                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8226                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8227                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8228                 }
8229
8230                 if (I915_READ(HDMIC) & PORT_DETECTED)
8231                         intel_hdmi_init(dev, HDMIC, PORT_C);
8232
8233                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8234                         intel_hdmi_init(dev, HDMID, PORT_D);
8235
8236                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8237                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8238
8239                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8240                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8241         } else if (IS_VALLEYVIEW(dev)) {
8242                 int found;
8243
8244                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8245                 if (I915_READ(DP_C) & DP_DETECTED)
8246                         intel_dp_init(dev, DP_C, PORT_C);
8247
8248                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8249                         /* SDVOB multiplex with HDMIB */
8250                         found = intel_sdvo_init(dev, SDVOB, true);
8251                         if (!found)
8252                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8253                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8254                                 intel_dp_init(dev, DP_B, PORT_B);
8255                 }
8256
8257                 if (I915_READ(SDVOC) & PORT_DETECTED)
8258                         intel_hdmi_init(dev, SDVOC, PORT_C);
8259
8260         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8261                 bool found = false;
8262
8263                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8264                         DRM_DEBUG_KMS("probing SDVOB\n");
8265                         found = intel_sdvo_init(dev, SDVOB, true);
8266                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8267                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8268                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8269                         }
8270
8271                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8272                                 DRM_DEBUG_KMS("probing DP_B\n");
8273                                 intel_dp_init(dev, DP_B, PORT_B);
8274                         }
8275                 }
8276
8277                 /* Before G4X SDVOC doesn't have its own detect register */
8278
8279                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8280                         DRM_DEBUG_KMS("probing SDVOC\n");
8281                         found = intel_sdvo_init(dev, SDVOC, false);
8282                 }
8283
8284                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8285
8286                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8287                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8288                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8289                         }
8290                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8291                                 DRM_DEBUG_KMS("probing DP_C\n");
8292                                 intel_dp_init(dev, DP_C, PORT_C);
8293                         }
8294                 }
8295
8296                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8297                     (I915_READ(DP_D) & DP_DETECTED)) {
8298                         DRM_DEBUG_KMS("probing DP_D\n");
8299                         intel_dp_init(dev, DP_D, PORT_D);
8300                 }
8301         } else if (IS_GEN2(dev))
8302                 intel_dvo_init(dev);
8303
8304         if (SUPPORTS_TV(dev))
8305                 intel_tv_init(dev);
8306
8307         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8308                 encoder->base.possible_crtcs = encoder->crtc_mask;
8309                 encoder->base.possible_clones =
8310                         intel_encoder_clones(encoder);
8311         }
8312
8313         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8314                 ironlake_init_pch_refclk(dev);
8315 }
8316
8317 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8318 {
8319         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8320
8321         drm_framebuffer_cleanup(fb);
8322         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8323
8324         kfree(intel_fb);
8325 }
8326
8327 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8328                                                 struct drm_file *file,
8329                                                 unsigned int *handle)
8330 {
8331         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8332         struct drm_i915_gem_object *obj = intel_fb->obj;
8333
8334         return drm_gem_handle_create(file, &obj->base, handle);
8335 }
8336
8337 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8338         .destroy = intel_user_framebuffer_destroy,
8339         .create_handle = intel_user_framebuffer_create_handle,
8340 };
8341
8342 int intel_framebuffer_init(struct drm_device *dev,
8343                            struct intel_framebuffer *intel_fb,
8344                            struct drm_mode_fb_cmd2 *mode_cmd,
8345                            struct drm_i915_gem_object *obj)
8346 {
8347         int ret;
8348
8349         if (obj->tiling_mode == I915_TILING_Y)
8350                 return -EINVAL;
8351
8352         if (mode_cmd->pitches[0] & 63)
8353                 return -EINVAL;
8354
8355         /* FIXME <= Gen4 stride limits are bit unclear */
8356         if (mode_cmd->pitches[0] > 32768)
8357                 return -EINVAL;
8358
8359         if (obj->tiling_mode != I915_TILING_NONE &&
8360             mode_cmd->pitches[0] != obj->stride)
8361                 return -EINVAL;
8362
8363         /* Reject formats not supported by any plane early. */
8364         switch (mode_cmd->pixel_format) {
8365         case DRM_FORMAT_C8:
8366         case DRM_FORMAT_RGB565:
8367         case DRM_FORMAT_XRGB8888:
8368         case DRM_FORMAT_ARGB8888:
8369                 break;
8370         case DRM_FORMAT_XRGB1555:
8371         case DRM_FORMAT_ARGB1555:
8372                 if (INTEL_INFO(dev)->gen > 3)
8373                         return -EINVAL;
8374                 break;
8375         case DRM_FORMAT_XBGR8888:
8376         case DRM_FORMAT_ABGR8888:
8377         case DRM_FORMAT_XRGB2101010:
8378         case DRM_FORMAT_ARGB2101010:
8379         case DRM_FORMAT_XBGR2101010:
8380         case DRM_FORMAT_ABGR2101010:
8381                 if (INTEL_INFO(dev)->gen < 4)
8382                         return -EINVAL;
8383                 break;
8384         case DRM_FORMAT_YUYV:
8385         case DRM_FORMAT_UYVY:
8386         case DRM_FORMAT_YVYU:
8387         case DRM_FORMAT_VYUY:
8388                 if (INTEL_INFO(dev)->gen < 6)
8389                         return -EINVAL;
8390                 break;
8391         default:
8392                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8393                 return -EINVAL;
8394         }
8395
8396         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8397         if (mode_cmd->offsets[0] != 0)
8398                 return -EINVAL;
8399
8400         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8401         if (ret) {
8402                 DRM_ERROR("framebuffer init failed %d\n", ret);
8403                 return ret;
8404         }
8405
8406         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8407         intel_fb->obj = obj;
8408         return 0;
8409 }
8410
8411 static struct drm_framebuffer *
8412 intel_user_framebuffer_create(struct drm_device *dev,
8413                               struct drm_file *filp,
8414                               struct drm_mode_fb_cmd2 *mode_cmd)
8415 {
8416         struct drm_i915_gem_object *obj;
8417
8418         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8419                                                 mode_cmd->handles[0]));
8420         if (&obj->base == NULL)
8421                 return ERR_PTR(-ENOENT);
8422
8423         return intel_framebuffer_create(dev, mode_cmd, obj);
8424 }
8425
8426 static const struct drm_mode_config_funcs intel_mode_funcs = {
8427         .fb_create = intel_user_framebuffer_create,
8428         .output_poll_changed = intel_fb_output_poll_changed,
8429 };
8430
8431 /* Set up chip specific display functions */
8432 static void intel_init_display(struct drm_device *dev)
8433 {
8434         struct drm_i915_private *dev_priv = dev->dev_private;
8435
8436         /* We always want a DPMS function */
8437         if (IS_HASWELL(dev)) {
8438                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8439                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8440                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8441                 dev_priv->display.off = haswell_crtc_off;
8442                 dev_priv->display.update_plane = ironlake_update_plane;
8443         } else if (HAS_PCH_SPLIT(dev)) {
8444                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8445                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8446                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8447                 dev_priv->display.off = ironlake_crtc_off;
8448                 dev_priv->display.update_plane = ironlake_update_plane;
8449         } else {
8450                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8451                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8452                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8453                 dev_priv->display.off = i9xx_crtc_off;
8454                 dev_priv->display.update_plane = i9xx_update_plane;
8455         }
8456
8457         /* Returns the core display clock speed */
8458         if (IS_VALLEYVIEW(dev))
8459                 dev_priv->display.get_display_clock_speed =
8460                         valleyview_get_display_clock_speed;
8461         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8462                 dev_priv->display.get_display_clock_speed =
8463                         i945_get_display_clock_speed;
8464         else if (IS_I915G(dev))
8465                 dev_priv->display.get_display_clock_speed =
8466                         i915_get_display_clock_speed;
8467         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8468                 dev_priv->display.get_display_clock_speed =
8469                         i9xx_misc_get_display_clock_speed;
8470         else if (IS_I915GM(dev))
8471                 dev_priv->display.get_display_clock_speed =
8472                         i915gm_get_display_clock_speed;
8473         else if (IS_I865G(dev))
8474                 dev_priv->display.get_display_clock_speed =
8475                         i865_get_display_clock_speed;
8476         else if (IS_I85X(dev))
8477                 dev_priv->display.get_display_clock_speed =
8478                         i855_get_display_clock_speed;
8479         else /* 852, 830 */
8480                 dev_priv->display.get_display_clock_speed =
8481                         i830_get_display_clock_speed;
8482
8483         if (HAS_PCH_SPLIT(dev)) {
8484                 if (IS_GEN5(dev)) {
8485                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8486                         dev_priv->display.write_eld = ironlake_write_eld;
8487                 } else if (IS_GEN6(dev)) {
8488                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8489                         dev_priv->display.write_eld = ironlake_write_eld;
8490                 } else if (IS_IVYBRIDGE(dev)) {
8491                         /* FIXME: detect B0+ stepping and use auto training */
8492                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8493                         dev_priv->display.write_eld = ironlake_write_eld;
8494                         dev_priv->display.modeset_global_resources =
8495                                 ivb_modeset_global_resources;
8496                 } else if (IS_HASWELL(dev)) {
8497                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8498                         dev_priv->display.write_eld = haswell_write_eld;
8499                 } else
8500                         dev_priv->display.update_wm = NULL;
8501         } else if (IS_G4X(dev)) {
8502                 dev_priv->display.write_eld = g4x_write_eld;
8503         }
8504
8505         /* Default just returns -ENODEV to indicate unsupported */
8506         dev_priv->display.queue_flip = intel_default_queue_flip;
8507
8508         switch (INTEL_INFO(dev)->gen) {
8509         case 2:
8510                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8511                 break;
8512
8513         case 3:
8514                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8515                 break;
8516
8517         case 4:
8518         case 5:
8519                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8520                 break;
8521
8522         case 6:
8523                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8524                 break;
8525         case 7:
8526                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8527                 break;
8528         }
8529 }
8530
8531 /*
8532  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8533  * resume, or other times.  This quirk makes sure that's the case for
8534  * affected systems.
8535  */
8536 static void quirk_pipea_force(struct drm_device *dev)
8537 {
8538         struct drm_i915_private *dev_priv = dev->dev_private;
8539
8540         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8541         DRM_INFO("applying pipe a force quirk\n");
8542 }
8543
8544 /*
8545  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8546  */
8547 static void quirk_ssc_force_disable(struct drm_device *dev)
8548 {
8549         struct drm_i915_private *dev_priv = dev->dev_private;
8550         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8551         DRM_INFO("applying lvds SSC disable quirk\n");
8552 }
8553
8554 /*
8555  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8556  * brightness value
8557  */
8558 static void quirk_invert_brightness(struct drm_device *dev)
8559 {
8560         struct drm_i915_private *dev_priv = dev->dev_private;
8561         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8562         DRM_INFO("applying inverted panel brightness quirk\n");
8563 }
8564
8565 struct intel_quirk {
8566         int device;
8567         int subsystem_vendor;
8568         int subsystem_device;
8569         void (*hook)(struct drm_device *dev);
8570 };
8571
8572 static struct intel_quirk intel_quirks[] = {
8573         /* HP Mini needs pipe A force quirk (LP: #322104) */
8574         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8575
8576         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8577         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8578
8579         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8580         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8581
8582         /* 830/845 need to leave pipe A & dpll A up */
8583         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8584         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8585
8586         /* Lenovo U160 cannot use SSC on LVDS */
8587         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8588
8589         /* Sony Vaio Y cannot use SSC on LVDS */
8590         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8591
8592         /* Acer Aspire 5734Z must invert backlight brightness */
8593         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8594 };
8595
8596 static void intel_init_quirks(struct drm_device *dev)
8597 {
8598         struct pci_dev *d = dev->pdev;
8599         int i;
8600
8601         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8602                 struct intel_quirk *q = &intel_quirks[i];
8603
8604                 if (d->device == q->device &&
8605                     (d->subsystem_vendor == q->subsystem_vendor ||
8606                      q->subsystem_vendor == PCI_ANY_ID) &&
8607                     (d->subsystem_device == q->subsystem_device ||
8608                      q->subsystem_device == PCI_ANY_ID))
8609                         q->hook(dev);
8610         }
8611 }
8612
8613 /* Disable the VGA plane that we never use */
8614 static void i915_disable_vga(struct drm_device *dev)
8615 {
8616         struct drm_i915_private *dev_priv = dev->dev_private;
8617         u8 sr1;
8618         u32 vga_reg;
8619
8620         if (HAS_PCH_SPLIT(dev))
8621                 vga_reg = CPU_VGACNTRL;
8622         else
8623                 vga_reg = VGACNTRL;
8624
8625         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8626         outb(SR01, VGA_SR_INDEX);
8627         sr1 = inb(VGA_SR_DATA);
8628         outb(sr1 | 1<<5, VGA_SR_DATA);
8629         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8630         udelay(300);
8631
8632         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8633         POSTING_READ(vga_reg);
8634 }
8635
8636 void intel_modeset_init_hw(struct drm_device *dev)
8637 {
8638         /* We attempt to init the necessary power wells early in the initialization
8639          * time, so the subsystems that expect power to be enabled can work.
8640          */
8641         intel_init_power_wells(dev);
8642
8643         intel_prepare_ddi(dev);
8644
8645         intel_init_clock_gating(dev);
8646
8647         mutex_lock(&dev->struct_mutex);
8648         intel_enable_gt_powersave(dev);
8649         mutex_unlock(&dev->struct_mutex);
8650 }
8651
8652 void intel_modeset_init(struct drm_device *dev)
8653 {
8654         struct drm_i915_private *dev_priv = dev->dev_private;
8655         int i, ret;
8656
8657         drm_mode_config_init(dev);
8658
8659         dev->mode_config.min_width = 0;
8660         dev->mode_config.min_height = 0;
8661
8662         dev->mode_config.preferred_depth = 24;
8663         dev->mode_config.prefer_shadow = 1;
8664
8665         dev->mode_config.funcs = &intel_mode_funcs;
8666
8667         intel_init_quirks(dev);
8668
8669         intel_init_pm(dev);
8670
8671         intel_init_display(dev);
8672
8673         if (IS_GEN2(dev)) {
8674                 dev->mode_config.max_width = 2048;
8675                 dev->mode_config.max_height = 2048;
8676         } else if (IS_GEN3(dev)) {
8677                 dev->mode_config.max_width = 4096;
8678                 dev->mode_config.max_height = 4096;
8679         } else {
8680                 dev->mode_config.max_width = 8192;
8681                 dev->mode_config.max_height = 8192;
8682         }
8683         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8684
8685         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8686                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8687
8688         for (i = 0; i < dev_priv->num_pipe; i++) {
8689                 intel_crtc_init(dev, i);
8690                 ret = intel_plane_init(dev, i);
8691                 if (ret)
8692                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8693         }
8694
8695         intel_cpu_pll_init(dev);
8696         intel_pch_pll_init(dev);
8697
8698         /* Just disable it once at startup */
8699         i915_disable_vga(dev);
8700         intel_setup_outputs(dev);
8701 }
8702
8703 static void
8704 intel_connector_break_all_links(struct intel_connector *connector)
8705 {
8706         connector->base.dpms = DRM_MODE_DPMS_OFF;
8707         connector->base.encoder = NULL;
8708         connector->encoder->connectors_active = false;
8709         connector->encoder->base.crtc = NULL;
8710 }
8711
8712 static void intel_enable_pipe_a(struct drm_device *dev)
8713 {
8714         struct intel_connector *connector;
8715         struct drm_connector *crt = NULL;
8716         struct intel_load_detect_pipe load_detect_temp;
8717
8718         /* We can't just switch on the pipe A, we need to set things up with a
8719          * proper mode and output configuration. As a gross hack, enable pipe A
8720          * by enabling the load detect pipe once. */
8721         list_for_each_entry(connector,
8722                             &dev->mode_config.connector_list,
8723                             base.head) {
8724                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8725                         crt = &connector->base;
8726                         break;
8727                 }
8728         }
8729
8730         if (!crt)
8731                 return;
8732
8733         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8734                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8735
8736
8737 }
8738
8739 static bool
8740 intel_check_plane_mapping(struct intel_crtc *crtc)
8741 {
8742         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8743         u32 reg, val;
8744
8745         if (dev_priv->num_pipe == 1)
8746                 return true;
8747
8748         reg = DSPCNTR(!crtc->plane);
8749         val = I915_READ(reg);
8750
8751         if ((val & DISPLAY_PLANE_ENABLE) &&
8752             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8753                 return false;
8754
8755         return true;
8756 }
8757
8758 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8759 {
8760         struct drm_device *dev = crtc->base.dev;
8761         struct drm_i915_private *dev_priv = dev->dev_private;
8762         u32 reg;
8763
8764         /* Clear any frame start delays used for debugging left by the BIOS */
8765         reg = PIPECONF(crtc->cpu_transcoder);
8766         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8767
8768         /* We need to sanitize the plane -> pipe mapping first because this will
8769          * disable the crtc (and hence change the state) if it is wrong. Note
8770          * that gen4+ has a fixed plane -> pipe mapping.  */
8771         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8772                 struct intel_connector *connector;
8773                 bool plane;
8774
8775                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8776                               crtc->base.base.id);
8777
8778                 /* Pipe has the wrong plane attached and the plane is active.
8779                  * Temporarily change the plane mapping and disable everything
8780                  * ...  */
8781                 plane = crtc->plane;
8782                 crtc->plane = !plane;
8783                 dev_priv->display.crtc_disable(&crtc->base);
8784                 crtc->plane = plane;
8785
8786                 /* ... and break all links. */
8787                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8788                                     base.head) {
8789                         if (connector->encoder->base.crtc != &crtc->base)
8790                                 continue;
8791
8792                         intel_connector_break_all_links(connector);
8793                 }
8794
8795                 WARN_ON(crtc->active);
8796                 crtc->base.enabled = false;
8797         }
8798
8799         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8800             crtc->pipe == PIPE_A && !crtc->active) {
8801                 /* BIOS forgot to enable pipe A, this mostly happens after
8802                  * resume. Force-enable the pipe to fix this, the update_dpms
8803                  * call below we restore the pipe to the right state, but leave
8804                  * the required bits on. */
8805                 intel_enable_pipe_a(dev);
8806         }
8807
8808         /* Adjust the state of the output pipe according to whether we
8809          * have active connectors/encoders. */
8810         intel_crtc_update_dpms(&crtc->base);
8811
8812         if (crtc->active != crtc->base.enabled) {
8813                 struct intel_encoder *encoder;
8814
8815                 /* This can happen either due to bugs in the get_hw_state
8816                  * functions or because the pipe is force-enabled due to the
8817                  * pipe A quirk. */
8818                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8819                               crtc->base.base.id,
8820                               crtc->base.enabled ? "enabled" : "disabled",
8821                               crtc->active ? "enabled" : "disabled");
8822
8823                 crtc->base.enabled = crtc->active;
8824
8825                 /* Because we only establish the connector -> encoder ->
8826                  * crtc links if something is active, this means the
8827                  * crtc is now deactivated. Break the links. connector
8828                  * -> encoder links are only establish when things are
8829                  *  actually up, hence no need to break them. */
8830                 WARN_ON(crtc->active);
8831
8832                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8833                         WARN_ON(encoder->connectors_active);
8834                         encoder->base.crtc = NULL;
8835                 }
8836         }
8837 }
8838
8839 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8840 {
8841         struct intel_connector *connector;
8842         struct drm_device *dev = encoder->base.dev;
8843
8844         /* We need to check both for a crtc link (meaning that the
8845          * encoder is active and trying to read from a pipe) and the
8846          * pipe itself being active. */
8847         bool has_active_crtc = encoder->base.crtc &&
8848                 to_intel_crtc(encoder->base.crtc)->active;
8849
8850         if (encoder->connectors_active && !has_active_crtc) {
8851                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8852                               encoder->base.base.id,
8853                               drm_get_encoder_name(&encoder->base));
8854
8855                 /* Connector is active, but has no active pipe. This is
8856                  * fallout from our resume register restoring. Disable
8857                  * the encoder manually again. */
8858                 if (encoder->base.crtc) {
8859                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8860                                       encoder->base.base.id,
8861                                       drm_get_encoder_name(&encoder->base));
8862                         encoder->disable(encoder);
8863                 }
8864
8865                 /* Inconsistent output/port/pipe state happens presumably due to
8866                  * a bug in one of the get_hw_state functions. Or someplace else
8867                  * in our code, like the register restore mess on resume. Clamp
8868                  * things to off as a safer default. */
8869                 list_for_each_entry(connector,
8870                                     &dev->mode_config.connector_list,
8871                                     base.head) {
8872                         if (connector->encoder != encoder)
8873                                 continue;
8874
8875                         intel_connector_break_all_links(connector);
8876                 }
8877         }
8878         /* Enabled encoders without active connectors will be fixed in
8879          * the crtc fixup. */
8880 }
8881
8882 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8883  * and i915 state tracking structures. */
8884 void intel_modeset_setup_hw_state(struct drm_device *dev)
8885 {
8886         struct drm_i915_private *dev_priv = dev->dev_private;
8887         enum pipe pipe;
8888         u32 tmp;
8889         struct intel_crtc *crtc;
8890         struct intel_encoder *encoder;
8891         struct intel_connector *connector;
8892
8893         if (IS_HASWELL(dev)) {
8894                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8895
8896                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8897                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8898                         case TRANS_DDI_EDP_INPUT_A_ON:
8899                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8900                                 pipe = PIPE_A;
8901                                 break;
8902                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8903                                 pipe = PIPE_B;
8904                                 break;
8905                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8906                                 pipe = PIPE_C;
8907                                 break;
8908                         }
8909
8910                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8911                         crtc->cpu_transcoder = TRANSCODER_EDP;
8912
8913                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8914                                       pipe_name(pipe));
8915                 }
8916         }
8917
8918         for_each_pipe(pipe) {
8919                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8920
8921                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8922                 if (tmp & PIPECONF_ENABLE)
8923                         crtc->active = true;
8924                 else
8925                         crtc->active = false;
8926
8927                 crtc->base.enabled = crtc->active;
8928
8929                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8930                               crtc->base.base.id,
8931                               crtc->active ? "enabled" : "disabled");
8932         }
8933
8934         if (IS_HASWELL(dev))
8935                 intel_ddi_setup_hw_pll_state(dev);
8936
8937         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8938                             base.head) {
8939                 pipe = 0;
8940
8941                 if (encoder->get_hw_state(encoder, &pipe)) {
8942                         encoder->base.crtc =
8943                                 dev_priv->pipe_to_crtc_mapping[pipe];
8944                 } else {
8945                         encoder->base.crtc = NULL;
8946                 }
8947
8948                 encoder->connectors_active = false;
8949                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8950                               encoder->base.base.id,
8951                               drm_get_encoder_name(&encoder->base),
8952                               encoder->base.crtc ? "enabled" : "disabled",
8953                               pipe);
8954         }
8955
8956         list_for_each_entry(connector, &dev->mode_config.connector_list,
8957                             base.head) {
8958                 if (connector->get_hw_state(connector)) {
8959                         connector->base.dpms = DRM_MODE_DPMS_ON;
8960                         connector->encoder->connectors_active = true;
8961                         connector->base.encoder = &connector->encoder->base;
8962                 } else {
8963                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8964                         connector->base.encoder = NULL;
8965                 }
8966                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8967                               connector->base.base.id,
8968                               drm_get_connector_name(&connector->base),
8969                               connector->base.encoder ? "enabled" : "disabled");
8970         }
8971
8972         /* HW state is read out, now we need to sanitize this mess. */
8973         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8974                             base.head) {
8975                 intel_sanitize_encoder(encoder);
8976         }
8977
8978         for_each_pipe(pipe) {
8979                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8980                 intel_sanitize_crtc(crtc);
8981         }
8982
8983         intel_modeset_update_staged_output_state(dev);
8984
8985         intel_modeset_check_state(dev);
8986
8987         drm_mode_config_reset(dev);
8988 }
8989
8990 void intel_modeset_gem_init(struct drm_device *dev)
8991 {
8992         intel_modeset_init_hw(dev);
8993
8994         intel_setup_overlay(dev);
8995
8996         intel_modeset_setup_hw_state(dev);
8997 }
8998
8999 void intel_modeset_cleanup(struct drm_device *dev)
9000 {
9001         struct drm_i915_private *dev_priv = dev->dev_private;
9002         struct drm_crtc *crtc;
9003         struct intel_crtc *intel_crtc;
9004
9005         drm_kms_helper_poll_fini(dev);
9006         mutex_lock(&dev->struct_mutex);
9007
9008         intel_unregister_dsm_handler();
9009
9010
9011         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9012                 /* Skip inactive CRTCs */
9013                 if (!crtc->fb)
9014                         continue;
9015
9016                 intel_crtc = to_intel_crtc(crtc);
9017                 intel_increase_pllclock(crtc);
9018         }
9019
9020         intel_disable_fbc(dev);
9021
9022         intel_disable_gt_powersave(dev);
9023
9024         ironlake_teardown_rc6(dev);
9025
9026         if (IS_VALLEYVIEW(dev))
9027                 vlv_init_dpio(dev);
9028
9029         mutex_unlock(&dev->struct_mutex);
9030
9031         /* Disable the irq before mode object teardown, for the irq might
9032          * enqueue unpin/hotplug work. */
9033         drm_irq_uninstall(dev);
9034         cancel_work_sync(&dev_priv->hotplug_work);
9035         cancel_work_sync(&dev_priv->rps.work);
9036
9037         /* flush any delayed tasks or pending work */
9038         flush_scheduled_work();
9039
9040         drm_mode_config_cleanup(dev);
9041 }
9042
9043 /*
9044  * Return which encoder is currently attached for connector.
9045  */
9046 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9047 {
9048         return &intel_attached_encoder(connector)->base;
9049 }
9050
9051 void intel_connector_attach_encoder(struct intel_connector *connector,
9052                                     struct intel_encoder *encoder)
9053 {
9054         connector->encoder = encoder;
9055         drm_mode_connector_attach_encoder(&connector->base,
9056                                           &encoder->base);
9057 }
9058
9059 /*
9060  * set vga decode state - true == enable VGA decode
9061  */
9062 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9063 {
9064         struct drm_i915_private *dev_priv = dev->dev_private;
9065         u16 gmch_ctrl;
9066
9067         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9068         if (state)
9069                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9070         else
9071                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9072         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9073         return 0;
9074 }
9075
9076 #ifdef CONFIG_DEBUG_FS
9077 #include <linux/seq_file.h>
9078
9079 struct intel_display_error_state {
9080         struct intel_cursor_error_state {
9081                 u32 control;
9082                 u32 position;
9083                 u32 base;
9084                 u32 size;
9085         } cursor[I915_MAX_PIPES];
9086
9087         struct intel_pipe_error_state {
9088                 u32 conf;
9089                 u32 source;
9090
9091                 u32 htotal;
9092                 u32 hblank;
9093                 u32 hsync;
9094                 u32 vtotal;
9095                 u32 vblank;
9096                 u32 vsync;
9097         } pipe[I915_MAX_PIPES];
9098
9099         struct intel_plane_error_state {
9100                 u32 control;
9101                 u32 stride;
9102                 u32 size;
9103                 u32 pos;
9104                 u32 addr;
9105                 u32 surface;
9106                 u32 tile_offset;
9107         } plane[I915_MAX_PIPES];
9108 };
9109
9110 struct intel_display_error_state *
9111 intel_display_capture_error_state(struct drm_device *dev)
9112 {
9113         drm_i915_private_t *dev_priv = dev->dev_private;
9114         struct intel_display_error_state *error;
9115         enum transcoder cpu_transcoder;
9116         int i;
9117
9118         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9119         if (error == NULL)
9120                 return NULL;
9121
9122         for_each_pipe(i) {
9123                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9124
9125                 error->cursor[i].control = I915_READ(CURCNTR(i));
9126                 error->cursor[i].position = I915_READ(CURPOS(i));
9127                 error->cursor[i].base = I915_READ(CURBASE(i));
9128
9129                 error->plane[i].control = I915_READ(DSPCNTR(i));
9130                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9131                 error->plane[i].size = I915_READ(DSPSIZE(i));
9132                 error->plane[i].pos = I915_READ(DSPPOS(i));
9133                 error->plane[i].addr = I915_READ(DSPADDR(i));
9134                 if (INTEL_INFO(dev)->gen >= 4) {
9135                         error->plane[i].surface = I915_READ(DSPSURF(i));
9136                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9137                 }
9138
9139                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9140                 error->pipe[i].source = I915_READ(PIPESRC(i));
9141                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9142                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9143                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9144                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9145                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9146                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9147         }
9148
9149         return error;
9150 }
9151
9152 void
9153 intel_display_print_error_state(struct seq_file *m,
9154                                 struct drm_device *dev,
9155                                 struct intel_display_error_state *error)
9156 {
9157         drm_i915_private_t *dev_priv = dev->dev_private;
9158         int i;
9159
9160         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9161         for_each_pipe(i) {
9162                 seq_printf(m, "Pipe [%d]:\n", i);
9163                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9164                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9165                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9166                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9167                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9168                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9169                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9170                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9171
9172                 seq_printf(m, "Plane [%d]:\n", i);
9173                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9174                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9175                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9176                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9177                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9178                 if (INTEL_INFO(dev)->gen >= 4) {
9179                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9180                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9181                 }
9182
9183                 seq_printf(m, "Cursor [%d]:\n", i);
9184                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9185                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9186                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9187         }
9188 }
9189 #endif