Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum transcoder cpu_transcoder)
1722 {
1723         u32 val, pipeconf_val;
1724
1725         /* PCH only available on ILK+ */
1726         BUG_ON(dev_priv->info->gen < 5);
1727
1728         /* FDI must be feeding us bits for PCH ports */
1729         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1731
1732         /* Workaround: set timing override bit. */
1733         val = I915_READ(_TRANSA_CHICKEN2);
1734         val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
1735         I915_WRITE(_TRANSA_CHICKEN2, val);
1736
1737         val = TRANS_ENABLE;
1738         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1739
1740         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1741             PIPECONF_INTERLACED_ILK)
1742                 val |= TRANS_INTERLACED;
1743         else
1744                 val |= TRANS_PROGRESSIVE;
1745
1746         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1747         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1748                 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 }
1750
1751 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752                                             enum pipe pipe)
1753 {
1754         int reg;
1755         u32 val;
1756
1757         /* FDI relies on the transcoder */
1758         assert_fdi_tx_disabled(dev_priv, pipe);
1759         assert_fdi_rx_disabled(dev_priv, pipe);
1760
1761         /* Ports must be off as well */
1762         assert_pch_ports_disabled(dev_priv, pipe);
1763
1764         reg = TRANSCONF(pipe);
1765         val = I915_READ(reg);
1766         val &= ~TRANS_ENABLE;
1767         I915_WRITE(reg, val);
1768         /* wait for PCH transcoder off, transcoder state */
1769         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1770                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1771 }
1772
1773 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1774 {
1775         u32 val;
1776
1777         val = I915_READ(_TRANSACONF);
1778         val &= ~TRANS_ENABLE;
1779         I915_WRITE(_TRANSACONF, val);
1780         /* wait for PCH transcoder off, transcoder state */
1781         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1782                 DRM_ERROR("Failed to disable PCH transcoder\n");
1783
1784         /* Workaround: clear timing override bit. */
1785         val = I915_READ(_TRANSA_CHICKEN2);
1786         val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
1787         I915_WRITE(_TRANSA_CHICKEN2, val);
1788 }
1789
1790 /**
1791  * intel_enable_pipe - enable a pipe, asserting requirements
1792  * @dev_priv: i915 private structure
1793  * @pipe: pipe to enable
1794  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1795  *
1796  * Enable @pipe, making sure that various hardware specific requirements
1797  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1798  *
1799  * @pipe should be %PIPE_A or %PIPE_B.
1800  *
1801  * Will wait until the pipe is actually running (i.e. first vblank) before
1802  * returning.
1803  */
1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1805                               bool pch_port)
1806 {
1807         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1808                                                                       pipe);
1809         int reg;
1810         u32 val;
1811
1812         /*
1813          * A pipe without a PLL won't actually be able to drive bits from
1814          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1815          * need the check.
1816          */
1817         if (!HAS_PCH_SPLIT(dev_priv->dev))
1818                 assert_pll_enabled(dev_priv, pipe);
1819         else {
1820                 if (pch_port) {
1821                         /* if driving the PCH, we need FDI enabled */
1822                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1823                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1824                 }
1825                 /* FIXME: assert CPU port conditions for SNB+ */
1826         }
1827
1828         reg = PIPECONF(cpu_transcoder);
1829         val = I915_READ(reg);
1830         if (val & PIPECONF_ENABLE)
1831                 return;
1832
1833         I915_WRITE(reg, val | PIPECONF_ENABLE);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_pipe - disable a pipe, asserting requirements
1839  * @dev_priv: i915 private structure
1840  * @pipe: pipe to disable
1841  *
1842  * Disable @pipe, making sure that various hardware specific requirements
1843  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844  *
1845  * @pipe should be %PIPE_A or %PIPE_B.
1846  *
1847  * Will wait until the pipe has shut down before returning.
1848  */
1849 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850                                enum pipe pipe)
1851 {
1852         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853                                                                       pipe);
1854         int reg;
1855         u32 val;
1856
1857         /*
1858          * Make sure planes won't keep trying to pump pixels to us,
1859          * or we might hang the display.
1860          */
1861         assert_planes_disabled(dev_priv, pipe);
1862
1863         /* Don't disable pipe A or pipe A PLLs if needed */
1864         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865                 return;
1866
1867         reg = PIPECONF(cpu_transcoder);
1868         val = I915_READ(reg);
1869         if ((val & PIPECONF_ENABLE) == 0)
1870                 return;
1871
1872         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1873         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874 }
1875
1876 /*
1877  * Plane regs are double buffered, going from enabled->disabled needs a
1878  * trigger in order to latch.  The display address reg provides this.
1879  */
1880 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1881                                       enum plane plane)
1882 {
1883         if (dev_priv->info->gen >= 4)
1884                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885         else
1886                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1887 }
1888
1889 /**
1890  * intel_enable_plane - enable a display plane on a given pipe
1891  * @dev_priv: i915 private structure
1892  * @plane: plane to enable
1893  * @pipe: pipe being fed
1894  *
1895  * Enable @plane on @pipe, making sure that @pipe is running first.
1896  */
1897 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898                                enum plane plane, enum pipe pipe)
1899 {
1900         int reg;
1901         u32 val;
1902
1903         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904         assert_pipe_enabled(dev_priv, pipe);
1905
1906         reg = DSPCNTR(plane);
1907         val = I915_READ(reg);
1908         if (val & DISPLAY_PLANE_ENABLE)
1909                 return;
1910
1911         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1912         intel_flush_display_plane(dev_priv, plane);
1913         intel_wait_for_vblank(dev_priv->dev, pipe);
1914 }
1915
1916 /**
1917  * intel_disable_plane - disable a display plane
1918  * @dev_priv: i915 private structure
1919  * @plane: plane to disable
1920  * @pipe: pipe consuming the data
1921  *
1922  * Disable @plane; should be an independent operation.
1923  */
1924 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925                                 enum plane plane, enum pipe pipe)
1926 {
1927         int reg;
1928         u32 val;
1929
1930         reg = DSPCNTR(plane);
1931         val = I915_READ(reg);
1932         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933                 return;
1934
1935         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1936         intel_flush_display_plane(dev_priv, plane);
1937         intel_wait_for_vblank(dev_priv->dev, pipe);
1938 }
1939
1940 int
1941 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1942                            struct drm_i915_gem_object *obj,
1943                            struct intel_ring_buffer *pipelined)
1944 {
1945         struct drm_i915_private *dev_priv = dev->dev_private;
1946         u32 alignment;
1947         int ret;
1948
1949         switch (obj->tiling_mode) {
1950         case I915_TILING_NONE:
1951                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952                         alignment = 128 * 1024;
1953                 else if (INTEL_INFO(dev)->gen >= 4)
1954                         alignment = 4 * 1024;
1955                 else
1956                         alignment = 64 * 1024;
1957                 break;
1958         case I915_TILING_X:
1959                 /* pin() will align the object as required by fence */
1960                 alignment = 0;
1961                 break;
1962         case I915_TILING_Y:
1963                 /* FIXME: Is this true? */
1964                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965                 return -EINVAL;
1966         default:
1967                 BUG();
1968         }
1969
1970         dev_priv->mm.interruptible = false;
1971         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1972         if (ret)
1973                 goto err_interruptible;
1974
1975         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976          * fence, whereas 965+ only requires a fence if using
1977          * framebuffer compression.  For simplicity, we always install
1978          * a fence as the cost is not that onerous.
1979          */
1980         ret = i915_gem_object_get_fence(obj);
1981         if (ret)
1982                 goto err_unpin;
1983
1984         i915_gem_object_pin_fence(obj);
1985
1986         dev_priv->mm.interruptible = true;
1987         return 0;
1988
1989 err_unpin:
1990         i915_gem_object_unpin(obj);
1991 err_interruptible:
1992         dev_priv->mm.interruptible = true;
1993         return ret;
1994 }
1995
1996 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997 {
1998         i915_gem_object_unpin_fence(obj);
1999         i915_gem_object_unpin(obj);
2000 }
2001
2002 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003  * is assumed to be a power-of-two. */
2004 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005                                                unsigned int bpp,
2006                                                unsigned int pitch)
2007 {
2008         int tile_rows, tiles;
2009
2010         tile_rows = *y / 8;
2011         *y %= 8;
2012         tiles = *x / (512/bpp);
2013         *x %= 512/bpp;
2014
2015         return tile_rows * pitch * 8 + tiles * 4096;
2016 }
2017
2018 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019                              int x, int y)
2020 {
2021         struct drm_device *dev = crtc->dev;
2022         struct drm_i915_private *dev_priv = dev->dev_private;
2023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024         struct intel_framebuffer *intel_fb;
2025         struct drm_i915_gem_object *obj;
2026         int plane = intel_crtc->plane;
2027         unsigned long linear_offset;
2028         u32 dspcntr;
2029         u32 reg;
2030
2031         switch (plane) {
2032         case 0:
2033         case 1:
2034                 break;
2035         default:
2036                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037                 return -EINVAL;
2038         }
2039
2040         intel_fb = to_intel_framebuffer(fb);
2041         obj = intel_fb->obj;
2042
2043         reg = DSPCNTR(plane);
2044         dspcntr = I915_READ(reg);
2045         /* Mask out pixel format bits in case we change it */
2046         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2047         switch (fb->pixel_format) {
2048         case DRM_FORMAT_C8:
2049                 dspcntr |= DISPPLANE_8BPP;
2050                 break;
2051         case DRM_FORMAT_XRGB1555:
2052         case DRM_FORMAT_ARGB1555:
2053                 dspcntr |= DISPPLANE_BGRX555;
2054                 break;
2055         case DRM_FORMAT_RGB565:
2056                 dspcntr |= DISPPLANE_BGRX565;
2057                 break;
2058         case DRM_FORMAT_XRGB8888:
2059         case DRM_FORMAT_ARGB8888:
2060                 dspcntr |= DISPPLANE_BGRX888;
2061                 break;
2062         case DRM_FORMAT_XBGR8888:
2063         case DRM_FORMAT_ABGR8888:
2064                 dspcntr |= DISPPLANE_RGBX888;
2065                 break;
2066         case DRM_FORMAT_XRGB2101010:
2067         case DRM_FORMAT_ARGB2101010:
2068                 dspcntr |= DISPPLANE_BGRX101010;
2069                 break;
2070         case DRM_FORMAT_XBGR2101010:
2071         case DRM_FORMAT_ABGR2101010:
2072                 dspcntr |= DISPPLANE_RGBX101010;
2073                 break;
2074         default:
2075                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2076                 return -EINVAL;
2077         }
2078
2079         if (INTEL_INFO(dev)->gen >= 4) {
2080                 if (obj->tiling_mode != I915_TILING_NONE)
2081                         dspcntr |= DISPPLANE_TILED;
2082                 else
2083                         dspcntr &= ~DISPPLANE_TILED;
2084         }
2085
2086         I915_WRITE(reg, dspcntr);
2087
2088         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2089
2090         if (INTEL_INFO(dev)->gen >= 4) {
2091                 intel_crtc->dspaddr_offset =
2092                         intel_gen4_compute_offset_xtiled(&x, &y,
2093                                                          fb->bits_per_pixel / 8,
2094                                                          fb->pitches[0]);
2095                 linear_offset -= intel_crtc->dspaddr_offset;
2096         } else {
2097                 intel_crtc->dspaddr_offset = linear_offset;
2098         }
2099
2100         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2102         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2103         if (INTEL_INFO(dev)->gen >= 4) {
2104                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2106                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108         } else
2109                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2110         POSTING_READ(reg);
2111
2112         return 0;
2113 }
2114
2115 static int ironlake_update_plane(struct drm_crtc *crtc,
2116                                  struct drm_framebuffer *fb, int x, int y)
2117 {
2118         struct drm_device *dev = crtc->dev;
2119         struct drm_i915_private *dev_priv = dev->dev_private;
2120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121         struct intel_framebuffer *intel_fb;
2122         struct drm_i915_gem_object *obj;
2123         int plane = intel_crtc->plane;
2124         unsigned long linear_offset;
2125         u32 dspcntr;
2126         u32 reg;
2127
2128         switch (plane) {
2129         case 0:
2130         case 1:
2131         case 2:
2132                 break;
2133         default:
2134                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135                 return -EINVAL;
2136         }
2137
2138         intel_fb = to_intel_framebuffer(fb);
2139         obj = intel_fb->obj;
2140
2141         reg = DSPCNTR(plane);
2142         dspcntr = I915_READ(reg);
2143         /* Mask out pixel format bits in case we change it */
2144         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2145         switch (fb->pixel_format) {
2146         case DRM_FORMAT_C8:
2147                 dspcntr |= DISPPLANE_8BPP;
2148                 break;
2149         case DRM_FORMAT_RGB565:
2150                 dspcntr |= DISPPLANE_BGRX565;
2151                 break;
2152         case DRM_FORMAT_XRGB8888:
2153         case DRM_FORMAT_ARGB8888:
2154                 dspcntr |= DISPPLANE_BGRX888;
2155                 break;
2156         case DRM_FORMAT_XBGR8888:
2157         case DRM_FORMAT_ABGR8888:
2158                 dspcntr |= DISPPLANE_RGBX888;
2159                 break;
2160         case DRM_FORMAT_XRGB2101010:
2161         case DRM_FORMAT_ARGB2101010:
2162                 dspcntr |= DISPPLANE_BGRX101010;
2163                 break;
2164         case DRM_FORMAT_XBGR2101010:
2165         case DRM_FORMAT_ABGR2101010:
2166                 dspcntr |= DISPPLANE_RGBX101010;
2167                 break;
2168         default:
2169                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2170                 return -EINVAL;
2171         }
2172
2173         if (obj->tiling_mode != I915_TILING_NONE)
2174                 dspcntr |= DISPPLANE_TILED;
2175         else
2176                 dspcntr &= ~DISPPLANE_TILED;
2177
2178         /* must disable */
2179         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181         I915_WRITE(reg, dspcntr);
2182
2183         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2184         intel_crtc->dspaddr_offset =
2185                 intel_gen4_compute_offset_xtiled(&x, &y,
2186                                                  fb->bits_per_pixel / 8,
2187                                                  fb->pitches[0]);
2188         linear_offset -= intel_crtc->dspaddr_offset;
2189
2190         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2192         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2193         I915_MODIFY_DISPBASE(DSPSURF(plane),
2194                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2195         if (IS_HASWELL(dev)) {
2196                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197         } else {
2198                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200         }
2201         POSTING_READ(reg);
2202
2203         return 0;
2204 }
2205
2206 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2207 static int
2208 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209                            int x, int y, enum mode_set_atomic state)
2210 {
2211         struct drm_device *dev = crtc->dev;
2212         struct drm_i915_private *dev_priv = dev->dev_private;
2213
2214         if (dev_priv->display.disable_fbc)
2215                 dev_priv->display.disable_fbc(dev);
2216         intel_increase_pllclock(crtc);
2217
2218         return dev_priv->display.update_plane(crtc, fb, x, y);
2219 }
2220
2221 static int
2222 intel_finish_fb(struct drm_framebuffer *old_fb)
2223 {
2224         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226         bool was_interruptible = dev_priv->mm.interruptible;
2227         int ret;
2228
2229         wait_event(dev_priv->pending_flip_queue,
2230                    atomic_read(&dev_priv->mm.wedged) ||
2231                    atomic_read(&obj->pending_flip) == 0);
2232
2233         /* Big Hammer, we also need to ensure that any pending
2234          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2235          * current scanout is retired before unpinning the old
2236          * framebuffer.
2237          *
2238          * This should only fail upon a hung GPU, in which case we
2239          * can safely continue.
2240          */
2241         dev_priv->mm.interruptible = false;
2242         ret = i915_gem_object_finish_gpu(obj);
2243         dev_priv->mm.interruptible = was_interruptible;
2244
2245         return ret;
2246 }
2247
2248 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_master_private *master_priv;
2252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253
2254         if (!dev->primary->master)
2255                 return;
2256
2257         master_priv = dev->primary->master->driver_priv;
2258         if (!master_priv->sarea_priv)
2259                 return;
2260
2261         switch (intel_crtc->pipe) {
2262         case 0:
2263                 master_priv->sarea_priv->pipeA_x = x;
2264                 master_priv->sarea_priv->pipeA_y = y;
2265                 break;
2266         case 1:
2267                 master_priv->sarea_priv->pipeB_x = x;
2268                 master_priv->sarea_priv->pipeB_y = y;
2269                 break;
2270         default:
2271                 break;
2272         }
2273 }
2274
2275 static int
2276 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2277                     struct drm_framebuffer *fb)
2278 {
2279         struct drm_device *dev = crtc->dev;
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2282         struct drm_framebuffer *old_fb;
2283         int ret;
2284
2285         /* no fb bound */
2286         if (!fb) {
2287                 DRM_ERROR("No FB bound\n");
2288                 return 0;
2289         }
2290
2291         if(intel_crtc->plane > dev_priv->num_pipe) {
2292                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2293                                 intel_crtc->plane,
2294                                 dev_priv->num_pipe);
2295                 return -EINVAL;
2296         }
2297
2298         mutex_lock(&dev->struct_mutex);
2299         ret = intel_pin_and_fence_fb_obj(dev,
2300                                          to_intel_framebuffer(fb)->obj,
2301                                          NULL);
2302         if (ret != 0) {
2303                 mutex_unlock(&dev->struct_mutex);
2304                 DRM_ERROR("pin & fence failed\n");
2305                 return ret;
2306         }
2307
2308         if (crtc->fb)
2309                 intel_finish_fb(crtc->fb);
2310
2311         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2312         if (ret) {
2313                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2314                 mutex_unlock(&dev->struct_mutex);
2315                 DRM_ERROR("failed to update base address\n");
2316                 return ret;
2317         }
2318
2319         old_fb = crtc->fb;
2320         crtc->fb = fb;
2321         crtc->x = x;
2322         crtc->y = y;
2323
2324         if (old_fb) {
2325                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2326                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2327         }
2328
2329         intel_update_fbc(dev);
2330         mutex_unlock(&dev->struct_mutex);
2331
2332         intel_crtc_update_sarea_pos(crtc, x, y);
2333
2334         return 0;
2335 }
2336
2337 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2338 {
2339         struct drm_device *dev = crtc->dev;
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341         u32 dpa_ctl;
2342
2343         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2344         dpa_ctl = I915_READ(DP_A);
2345         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2346
2347         if (clock < 200000) {
2348                 u32 temp;
2349                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2350                 /* workaround for 160Mhz:
2351                    1) program 0x4600c bits 15:0 = 0x8124
2352                    2) program 0x46010 bit 0 = 1
2353                    3) program 0x46034 bit 24 = 1
2354                    4) program 0x64000 bit 14 = 1
2355                    */
2356                 temp = I915_READ(0x4600c);
2357                 temp &= 0xffff0000;
2358                 I915_WRITE(0x4600c, temp | 0x8124);
2359
2360                 temp = I915_READ(0x46010);
2361                 I915_WRITE(0x46010, temp | 1);
2362
2363                 temp = I915_READ(0x46034);
2364                 I915_WRITE(0x46034, temp | (1 << 24));
2365         } else {
2366                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2367         }
2368         I915_WRITE(DP_A, dpa_ctl);
2369
2370         POSTING_READ(DP_A);
2371         udelay(500);
2372 }
2373
2374 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2375 {
2376         struct drm_device *dev = crtc->dev;
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379         int pipe = intel_crtc->pipe;
2380         u32 reg, temp;
2381
2382         /* enable normal train */
2383         reg = FDI_TX_CTL(pipe);
2384         temp = I915_READ(reg);
2385         if (IS_IVYBRIDGE(dev)) {
2386                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2387                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2388         } else {
2389                 temp &= ~FDI_LINK_TRAIN_NONE;
2390                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2391         }
2392         I915_WRITE(reg, temp);
2393
2394         reg = FDI_RX_CTL(pipe);
2395         temp = I915_READ(reg);
2396         if (HAS_PCH_CPT(dev)) {
2397                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2398                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2399         } else {
2400                 temp &= ~FDI_LINK_TRAIN_NONE;
2401                 temp |= FDI_LINK_TRAIN_NONE;
2402         }
2403         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2404
2405         /* wait one idle pattern time */
2406         POSTING_READ(reg);
2407         udelay(1000);
2408
2409         /* IVB wants error correction enabled */
2410         if (IS_IVYBRIDGE(dev))
2411                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2412                            FDI_FE_ERRC_ENABLE);
2413 }
2414
2415 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2416 {
2417         struct drm_i915_private *dev_priv = dev->dev_private;
2418         u32 flags = I915_READ(SOUTH_CHICKEN1);
2419
2420         flags |= FDI_PHASE_SYNC_OVR(pipe);
2421         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2422         flags |= FDI_PHASE_SYNC_EN(pipe);
2423         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2424         POSTING_READ(SOUTH_CHICKEN1);
2425 }
2426
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         struct intel_crtc *pipe_B_crtc =
2431                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432         struct intel_crtc *pipe_C_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434         uint32_t temp;
2435
2436         /* When everything is off disable fdi C so that we could enable fdi B
2437          * with all lanes. XXX: This misses the case where a pipe is not using
2438          * any pch resources and so doesn't need any fdi lanes. */
2439         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2440                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2441                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2442
2443                 temp = I915_READ(SOUTH_CHICKEN1);
2444                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2445                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2446                 I915_WRITE(SOUTH_CHICKEN1, temp);
2447         }
2448 }
2449
2450 /* The FDI link training functions for ILK/Ibexpeak. */
2451 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453         struct drm_device *dev = crtc->dev;
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456         int pipe = intel_crtc->pipe;
2457         int plane = intel_crtc->plane;
2458         u32 reg, temp, tries;
2459
2460         /* FDI needs bits from pipe & plane first */
2461         assert_pipe_enabled(dev_priv, pipe);
2462         assert_plane_enabled(dev_priv, plane);
2463
2464         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2465            for train result */
2466         reg = FDI_RX_IMR(pipe);
2467         temp = I915_READ(reg);
2468         temp &= ~FDI_RX_SYMBOL_LOCK;
2469         temp &= ~FDI_RX_BIT_LOCK;
2470         I915_WRITE(reg, temp);
2471         I915_READ(reg);
2472         udelay(150);
2473
2474         /* enable CPU FDI TX and PCH FDI RX */
2475         reg = FDI_TX_CTL(pipe);
2476         temp = I915_READ(reg);
2477         temp &= ~(7 << 19);
2478         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2479         temp &= ~FDI_LINK_TRAIN_NONE;
2480         temp |= FDI_LINK_TRAIN_PATTERN_1;
2481         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2482
2483         reg = FDI_RX_CTL(pipe);
2484         temp = I915_READ(reg);
2485         temp &= ~FDI_LINK_TRAIN_NONE;
2486         temp |= FDI_LINK_TRAIN_PATTERN_1;
2487         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488
2489         POSTING_READ(reg);
2490         udelay(150);
2491
2492         /* Ironlake workaround, enable clock pointer after FDI enable*/
2493         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2494         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2495                    FDI_RX_PHASE_SYNC_POINTER_EN);
2496
2497         reg = FDI_RX_IIR(pipe);
2498         for (tries = 0; tries < 5; tries++) {
2499                 temp = I915_READ(reg);
2500                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2501
2502                 if ((temp & FDI_RX_BIT_LOCK)) {
2503                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2504                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2505                         break;
2506                 }
2507         }
2508         if (tries == 5)
2509                 DRM_ERROR("FDI train 1 fail!\n");
2510
2511         /* Train 2 */
2512         reg = FDI_TX_CTL(pipe);
2513         temp = I915_READ(reg);
2514         temp &= ~FDI_LINK_TRAIN_NONE;
2515         temp |= FDI_LINK_TRAIN_PATTERN_2;
2516         I915_WRITE(reg, temp);
2517
2518         reg = FDI_RX_CTL(pipe);
2519         temp = I915_READ(reg);
2520         temp &= ~FDI_LINK_TRAIN_NONE;
2521         temp |= FDI_LINK_TRAIN_PATTERN_2;
2522         I915_WRITE(reg, temp);
2523
2524         POSTING_READ(reg);
2525         udelay(150);
2526
2527         reg = FDI_RX_IIR(pipe);
2528         for (tries = 0; tries < 5; tries++) {
2529                 temp = I915_READ(reg);
2530                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2531
2532                 if (temp & FDI_RX_SYMBOL_LOCK) {
2533                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2534                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2535                         break;
2536                 }
2537         }
2538         if (tries == 5)
2539                 DRM_ERROR("FDI train 2 fail!\n");
2540
2541         DRM_DEBUG_KMS("FDI train done\n");
2542
2543 }
2544
2545 static const int snb_b_fdi_train_param[] = {
2546         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2547         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2548         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2549         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2550 };
2551
2552 /* The FDI link training functions for SNB/Cougarpoint. */
2553 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2554 {
2555         struct drm_device *dev = crtc->dev;
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558         int pipe = intel_crtc->pipe;
2559         u32 reg, temp, i, retry;
2560
2561         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562            for train result */
2563         reg = FDI_RX_IMR(pipe);
2564         temp = I915_READ(reg);
2565         temp &= ~FDI_RX_SYMBOL_LOCK;
2566         temp &= ~FDI_RX_BIT_LOCK;
2567         I915_WRITE(reg, temp);
2568
2569         POSTING_READ(reg);
2570         udelay(150);
2571
2572         /* enable CPU FDI TX and PCH FDI RX */
2573         reg = FDI_TX_CTL(pipe);
2574         temp = I915_READ(reg);
2575         temp &= ~(7 << 19);
2576         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2577         temp &= ~FDI_LINK_TRAIN_NONE;
2578         temp |= FDI_LINK_TRAIN_PATTERN_1;
2579         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580         /* SNB-B */
2581         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2583
2584         I915_WRITE(FDI_RX_MISC(pipe),
2585                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         if (HAS_PCH_CPT(dev)) {
2590                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592         } else {
2593                 temp &= ~FDI_LINK_TRAIN_NONE;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2595         }
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         cpt_phase_pointer_enable(dev, pipe);
2602
2603         for (i = 0; i < 4; i++) {
2604                 reg = FDI_TX_CTL(pipe);
2605                 temp = I915_READ(reg);
2606                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607                 temp |= snb_b_fdi_train_param[i];
2608                 I915_WRITE(reg, temp);
2609
2610                 POSTING_READ(reg);
2611                 udelay(500);
2612
2613                 for (retry = 0; retry < 5; retry++) {
2614                         reg = FDI_RX_IIR(pipe);
2615                         temp = I915_READ(reg);
2616                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617                         if (temp & FDI_RX_BIT_LOCK) {
2618                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620                                 break;
2621                         }
2622                         udelay(50);
2623                 }
2624                 if (retry < 5)
2625                         break;
2626         }
2627         if (i == 4)
2628                 DRM_ERROR("FDI train 1 fail!\n");
2629
2630         /* Train 2 */
2631         reg = FDI_TX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_NONE;
2634         temp |= FDI_LINK_TRAIN_PATTERN_2;
2635         if (IS_GEN6(dev)) {
2636                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637                 /* SNB-B */
2638                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639         }
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         if (HAS_PCH_CPT(dev)) {
2645                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647         } else {
2648                 temp &= ~FDI_LINK_TRAIN_NONE;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650         }
2651         I915_WRITE(reg, temp);
2652
2653         POSTING_READ(reg);
2654         udelay(150);
2655
2656         for (i = 0; i < 4; i++) {
2657                 reg = FDI_TX_CTL(pipe);
2658                 temp = I915_READ(reg);
2659                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660                 temp |= snb_b_fdi_train_param[i];
2661                 I915_WRITE(reg, temp);
2662
2663                 POSTING_READ(reg);
2664                 udelay(500);
2665
2666                 for (retry = 0; retry < 5; retry++) {
2667                         reg = FDI_RX_IIR(pipe);
2668                         temp = I915_READ(reg);
2669                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670                         if (temp & FDI_RX_SYMBOL_LOCK) {
2671                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673                                 break;
2674                         }
2675                         udelay(50);
2676                 }
2677                 if (retry < 5)
2678                         break;
2679         }
2680         if (i == 4)
2681                 DRM_ERROR("FDI train 2 fail!\n");
2682
2683         DRM_DEBUG_KMS("FDI train done.\n");
2684 }
2685
2686 /* Manual link training for Ivy Bridge A0 parts */
2687 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688 {
2689         struct drm_device *dev = crtc->dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp, i;
2694
2695         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696            for train result */
2697         reg = FDI_RX_IMR(pipe);
2698         temp = I915_READ(reg);
2699         temp &= ~FDI_RX_SYMBOL_LOCK;
2700         temp &= ~FDI_RX_BIT_LOCK;
2701         I915_WRITE(reg, temp);
2702
2703         POSTING_READ(reg);
2704         udelay(150);
2705
2706         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707                       I915_READ(FDI_RX_IIR(pipe)));
2708
2709         /* enable CPU FDI TX and PCH FDI RX */
2710         reg = FDI_TX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         temp &= ~(7 << 19);
2713         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2714         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2716         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2717         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2718         temp |= FDI_COMPOSITE_SYNC;
2719         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2720
2721         I915_WRITE(FDI_RX_MISC(pipe),
2722                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~FDI_LINK_TRAIN_AUTO;
2727         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2729         temp |= FDI_COMPOSITE_SYNC;
2730         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2731
2732         POSTING_READ(reg);
2733         udelay(150);
2734
2735         cpt_phase_pointer_enable(dev, pipe);
2736
2737         for (i = 0; i < 4; i++) {
2738                 reg = FDI_TX_CTL(pipe);
2739                 temp = I915_READ(reg);
2740                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741                 temp |= snb_b_fdi_train_param[i];
2742                 I915_WRITE(reg, temp);
2743
2744                 POSTING_READ(reg);
2745                 udelay(500);
2746
2747                 reg = FDI_RX_IIR(pipe);
2748                 temp = I915_READ(reg);
2749                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751                 if (temp & FDI_RX_BIT_LOCK ||
2752                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2754                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2755                         break;
2756                 }
2757         }
2758         if (i == 4)
2759                 DRM_ERROR("FDI train 1 fail!\n");
2760
2761         /* Train 2 */
2762         reg = FDI_TX_CTL(pipe);
2763         temp = I915_READ(reg);
2764         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774         I915_WRITE(reg, temp);
2775
2776         POSTING_READ(reg);
2777         udelay(150);
2778
2779         for (i = 0; i < 4; i++) {
2780                 reg = FDI_TX_CTL(pipe);
2781                 temp = I915_READ(reg);
2782                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783                 temp |= snb_b_fdi_train_param[i];
2784                 I915_WRITE(reg, temp);
2785
2786                 POSTING_READ(reg);
2787                 udelay(500);
2788
2789                 reg = FDI_RX_IIR(pipe);
2790                 temp = I915_READ(reg);
2791                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793                 if (temp & FDI_RX_SYMBOL_LOCK) {
2794                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2796                         break;
2797                 }
2798         }
2799         if (i == 4)
2800                 DRM_ERROR("FDI train 2 fail!\n");
2801
2802         DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* On Haswell, the PLL configuration for ports and pipes is handled
2832          * separately, as part of DDI setup */
2833         if (!IS_HASWELL(dev)) {
2834                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835                 reg = FDI_TX_CTL(pipe);
2836                 temp = I915_READ(reg);
2837                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                         POSTING_READ(reg);
2841                         udelay(100);
2842                 }
2843         }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848         struct drm_device *dev = intel_crtc->base.dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* Switch from PCDclk to Rawclk */
2854         reg = FDI_RX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858         /* Disable CPU FDI TX PLL */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870         /* Wait for the clocks to turn off. */
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2876 {
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         u32 flags = I915_READ(SOUTH_CHICKEN1);
2879
2880         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2881         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2882         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2883         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2884         POSTING_READ(SOUTH_CHICKEN1);
2885 }
2886 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2887 {
2888         struct drm_device *dev = crtc->dev;
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2891         int pipe = intel_crtc->pipe;
2892         u32 reg, temp;
2893
2894         /* disable CPU FDI tx and PCH FDI rx */
2895         reg = FDI_TX_CTL(pipe);
2896         temp = I915_READ(reg);
2897         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2898         POSTING_READ(reg);
2899
2900         reg = FDI_RX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         temp &= ~(0x7 << 16);
2903         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2904         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2905
2906         POSTING_READ(reg);
2907         udelay(100);
2908
2909         /* Ironlake workaround, disable clock pointer after downing FDI */
2910         if (HAS_PCH_IBX(dev)) {
2911                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2912                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2913                            I915_READ(FDI_RX_CHICKEN(pipe) &
2914                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2915         } else if (HAS_PCH_CPT(dev)) {
2916                 cpt_phase_pointer_disable(dev, pipe);
2917         }
2918
2919         /* still set train pattern 1 */
2920         reg = FDI_TX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         temp &= ~FDI_LINK_TRAIN_NONE;
2923         temp |= FDI_LINK_TRAIN_PATTERN_1;
2924         I915_WRITE(reg, temp);
2925
2926         reg = FDI_RX_CTL(pipe);
2927         temp = I915_READ(reg);
2928         if (HAS_PCH_CPT(dev)) {
2929                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2930                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2931         } else {
2932                 temp &= ~FDI_LINK_TRAIN_NONE;
2933                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2934         }
2935         /* BPC in FDI rx is consistent with that in PIPECONF */
2936         temp &= ~(0x07 << 16);
2937         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2938         I915_WRITE(reg, temp);
2939
2940         POSTING_READ(reg);
2941         udelay(100);
2942 }
2943
2944 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2945 {
2946         struct drm_device *dev = crtc->dev;
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948         unsigned long flags;
2949         bool pending;
2950
2951         if (atomic_read(&dev_priv->mm.wedged))
2952                 return false;
2953
2954         spin_lock_irqsave(&dev->event_lock, flags);
2955         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2956         spin_unlock_irqrestore(&dev->event_lock, flags);
2957
2958         return pending;
2959 }
2960
2961 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2962 {
2963         struct drm_device *dev = crtc->dev;
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965
2966         if (crtc->fb == NULL)
2967                 return;
2968
2969         wait_event(dev_priv->pending_flip_queue,
2970                    !intel_crtc_has_pending_flip(crtc));
2971
2972         mutex_lock(&dev->struct_mutex);
2973         intel_finish_fb(crtc->fb);
2974         mutex_unlock(&dev->struct_mutex);
2975 }
2976
2977 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct intel_encoder *intel_encoder;
2981
2982         /*
2983          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2984          * must be driven by its own crtc; no sharing is possible.
2985          */
2986         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2987                 switch (intel_encoder->type) {
2988                 case INTEL_OUTPUT_EDP:
2989                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2990                                 return false;
2991                         continue;
2992                 }
2993         }
2994
2995         return true;
2996 }
2997
2998 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999 {
3000         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009         u32 temp;
3010
3011         /* It is necessary to ungate the pixclk gate prior to programming
3012          * the divisors, and gate it back when it is done.
3013          */
3014         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3015
3016         /* Disable SSCCTL */
3017         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3018                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3019                                         SBI_SSCCTL_DISABLE);
3020
3021         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022         if (crtc->mode.clock == 20000) {
3023                 auxdiv = 1;
3024                 divsel = 0x41;
3025                 phaseinc = 0x20;
3026         } else {
3027                 /* The iCLK virtual clock root frequency is in MHz,
3028                  * but the crtc->mode.clock in in KHz. To get the divisors,
3029                  * it is necessary to divide one by another, so we
3030                  * convert the virtual clock precision to KHz here for higher
3031                  * precision.
3032                  */
3033                 u32 iclk_virtual_root_freq = 172800 * 1000;
3034                 u32 iclk_pi_range = 64;
3035                 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038                 msb_divisor_value = desired_divisor / iclk_pi_range;
3039                 pi_value = desired_divisor % iclk_pi_range;
3040
3041                 auxdiv = 0;
3042                 divsel = msb_divisor_value - 2;
3043                 phaseinc = pi_value;
3044         }
3045
3046         /* This should not happen with any sane values */
3047         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053                         crtc->mode.clock,
3054                         auxdiv,
3055                         divsel,
3056                         phasedir,
3057                         phaseinc);
3058
3059         /* Program SSCDIVINTPHASE6 */
3060         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3061         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067
3068         intel_sbi_write(dev_priv,
3069                         SBI_SSCDIVINTPHASE6,
3070                         temp);
3071
3072         /* Program SSCAUXDIV */
3073         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3074         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076         intel_sbi_write(dev_priv,
3077                         SBI_SSCAUXDIV6,
3078                         temp);
3079
3080
3081         /* Enable modulator and associated divider */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3083         temp &= ~SBI_SSCCTL_DISABLE;
3084         intel_sbi_write(dev_priv,
3085                         SBI_SSCCTL6,
3086                         temp);
3087
3088         /* Wait for initialization time */
3089         udelay(24);
3090
3091         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3092 }
3093
3094 /*
3095  * Enable PCH resources required for PCH ports:
3096  *   - PCH PLLs
3097  *   - FDI training & RX/TX
3098  *   - update transcoder timings
3099  *   - DP transcoding bits
3100  *   - transcoder
3101  */
3102 static void ironlake_pch_enable(struct drm_crtc *crtc)
3103 {
3104         struct drm_device *dev = crtc->dev;
3105         struct drm_i915_private *dev_priv = dev->dev_private;
3106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107         int pipe = intel_crtc->pipe;
3108         u32 reg, temp;
3109
3110         assert_transcoder_disabled(dev_priv, pipe);
3111
3112         /* Write the TU size bits before fdi link training, so that error
3113          * detection works. */
3114         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3115                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3116
3117         /* For PCH output, training FDI link */
3118         dev_priv->display.fdi_link_train(crtc);
3119
3120         /* XXX: pch pll's can be enabled any time before we enable the PCH
3121          * transcoder, and we actually should do this to not upset any PCH
3122          * transcoder that already use the clock when we share it.
3123          *
3124          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3125          * unconditionally resets the pll - we need that to have the right LVDS
3126          * enable sequence. */
3127         ironlake_enable_pch_pll(intel_crtc);
3128
3129         if (HAS_PCH_CPT(dev)) {
3130                 u32 sel;
3131
3132                 temp = I915_READ(PCH_DPLL_SEL);
3133                 switch (pipe) {
3134                 default:
3135                 case 0:
3136                         temp |= TRANSA_DPLL_ENABLE;
3137                         sel = TRANSA_DPLLB_SEL;
3138                         break;
3139                 case 1:
3140                         temp |= TRANSB_DPLL_ENABLE;
3141                         sel = TRANSB_DPLLB_SEL;
3142                         break;
3143                 case 2:
3144                         temp |= TRANSC_DPLL_ENABLE;
3145                         sel = TRANSC_DPLLB_SEL;
3146                         break;
3147                 }
3148                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3149                         temp |= sel;
3150                 else
3151                         temp &= ~sel;
3152                 I915_WRITE(PCH_DPLL_SEL, temp);
3153         }
3154
3155         /* set transcoder timing, panel must allow it */
3156         assert_panel_unlocked(dev_priv, pipe);
3157         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3158         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3159         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3160
3161         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3162         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3163         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3164         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3165
3166         intel_fdi_normal_train(crtc);
3167
3168         /* For PCH DP, enable TRANS_DP_CTL */
3169         if (HAS_PCH_CPT(dev) &&
3170             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3171              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3172                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3173                 reg = TRANS_DP_CTL(pipe);
3174                 temp = I915_READ(reg);
3175                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3176                           TRANS_DP_SYNC_MASK |
3177                           TRANS_DP_BPC_MASK);
3178                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3179                          TRANS_DP_ENH_FRAMING);
3180                 temp |= bpc << 9; /* same format but at 11:9 */
3181
3182                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3183                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3184                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3185                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3186
3187                 switch (intel_trans_dp_port_sel(crtc)) {
3188                 case PCH_DP_B:
3189                         temp |= TRANS_DP_PORT_SEL_B;
3190                         break;
3191                 case PCH_DP_C:
3192                         temp |= TRANS_DP_PORT_SEL_C;
3193                         break;
3194                 case PCH_DP_D:
3195                         temp |= TRANS_DP_PORT_SEL_D;
3196                         break;
3197                 default:
3198                         BUG();
3199                 }
3200
3201                 I915_WRITE(reg, temp);
3202         }
3203
3204         ironlake_enable_pch_transcoder(dev_priv, pipe);
3205 }
3206
3207 static void lpt_pch_enable(struct drm_crtc *crtc)
3208 {
3209         struct drm_device *dev = crtc->dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212         int pipe = intel_crtc->pipe;
3213         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3214
3215         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3216
3217         /* Write the TU size bits before fdi link training, so that error
3218          * detection works. */
3219         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3220                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3221
3222         /* For PCH output, training FDI link */
3223         dev_priv->display.fdi_link_train(crtc);
3224
3225         lpt_program_iclkip(crtc);
3226
3227         /* Set transcoder timing. */
3228         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3231
3232         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3236
3237         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3238 }
3239
3240 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241 {
3242         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244         if (pll == NULL)
3245                 return;
3246
3247         if (pll->refcount == 0) {
3248                 WARN(1, "bad PCH PLL refcount\n");
3249                 return;
3250         }
3251
3252         --pll->refcount;
3253         intel_crtc->pch_pll = NULL;
3254 }
3255
3256 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257 {
3258         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259         struct intel_pch_pll *pll;
3260         int i;
3261
3262         pll = intel_crtc->pch_pll;
3263         if (pll) {
3264                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265                               intel_crtc->base.base.id, pll->pll_reg);
3266                 goto prepare;
3267         }
3268
3269         if (HAS_PCH_IBX(dev_priv->dev)) {
3270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271                 i = intel_crtc->pipe;
3272                 pll = &dev_priv->pch_plls[i];
3273
3274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275                               intel_crtc->base.base.id, pll->pll_reg);
3276
3277                 goto found;
3278         }
3279
3280         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 /* Only want to check enabled timings first */
3284                 if (pll->refcount == 0)
3285                         continue;
3286
3287                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288                     fp == I915_READ(pll->fp0_reg)) {
3289                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290                                       intel_crtc->base.base.id,
3291                                       pll->pll_reg, pll->refcount, pll->active);
3292
3293                         goto found;
3294                 }
3295         }
3296
3297         /* Ok no matching timings, maybe there's a free one? */
3298         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299                 pll = &dev_priv->pch_plls[i];
3300                 if (pll->refcount == 0) {
3301                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302                                       intel_crtc->base.base.id, pll->pll_reg);
3303                         goto found;
3304                 }
3305         }
3306
3307         return NULL;
3308
3309 found:
3310         intel_crtc->pch_pll = pll;
3311         pll->refcount++;
3312         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313 prepare: /* separate function? */
3314         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3315
3316         /* Wait for the clocks to stabilize before rewriting the regs */
3317         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3318         POSTING_READ(pll->pll_reg);
3319         udelay(150);
3320
3321         I915_WRITE(pll->fp0_reg, fp);
3322         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3323         pll->on = false;
3324         return pll;
3325 }
3326
3327 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 /* Without this, mode sets may fail silently on FDI */
3337                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3338                 udelay(250);
3339                 I915_WRITE(tc2reg, 0);
3340                 if (wait_for(I915_READ(dslreg) != temp, 5))
3341                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3342         }
3343 }
3344
3345 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353         u32 temp;
3354         bool is_pch_port;
3355
3356         WARN_ON(!crtc->enabled);
3357
3358         if (intel_crtc->active)
3359                 return;
3360
3361         intel_crtc->active = true;
3362         intel_update_watermarks(dev);
3363
3364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3365                 temp = I915_READ(PCH_LVDS);
3366                 if ((temp & LVDS_PORT_EN) == 0)
3367                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3368         }
3369
3370         is_pch_port = ironlake_crtc_driving_pch(crtc);
3371
3372         if (is_pch_port) {
3373                 /* Note: FDI PLL enabling _must_ be done before we enable the
3374                  * cpu pipes, hence this is separate from all the other fdi/pch
3375                  * enabling. */
3376                 ironlake_fdi_pll_enable(intel_crtc);
3377         } else {
3378                 assert_fdi_tx_disabled(dev_priv, pipe);
3379                 assert_fdi_rx_disabled(dev_priv, pipe);
3380         }
3381
3382         for_each_encoder_on_crtc(dev, crtc, encoder)
3383                 if (encoder->pre_enable)
3384                         encoder->pre_enable(encoder);
3385
3386         /* Enable panel fitting for LVDS */
3387         if (dev_priv->pch_pf_size &&
3388             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3389                 /* Force use of hard-coded filter coefficients
3390                  * as some pre-programmed values are broken,
3391                  * e.g. x201.
3392                  */
3393                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3394                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3395                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3396         }
3397
3398         /*
3399          * On ILK+ LUT must be loaded before the pipe is running but with
3400          * clocks enabled
3401          */
3402         intel_crtc_load_lut(crtc);
3403
3404         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405         intel_enable_plane(dev_priv, plane, pipe);
3406
3407         if (is_pch_port)
3408                 ironlake_pch_enable(crtc);
3409
3410         mutex_lock(&dev->struct_mutex);
3411         intel_update_fbc(dev);
3412         mutex_unlock(&dev->struct_mutex);
3413
3414         intel_crtc_update_cursor(crtc, true);
3415
3416         for_each_encoder_on_crtc(dev, crtc, encoder)
3417                 encoder->enable(encoder);
3418
3419         if (HAS_PCH_CPT(dev))
3420                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3421
3422         /*
3423          * There seems to be a race in PCH platform hw (at least on some
3424          * outputs) where an enabled pipe still completes any pageflip right
3425          * away (as if the pipe is off) instead of waiting for vblank. As soon
3426          * as the first vblank happend, everything works as expected. Hence just
3427          * wait for one vblank before returning to avoid strange things
3428          * happening.
3429          */
3430         intel_wait_for_vblank(dev, intel_crtc->pipe);
3431 }
3432
3433 static void haswell_crtc_enable(struct drm_crtc *crtc)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438         struct intel_encoder *encoder;
3439         int pipe = intel_crtc->pipe;
3440         int plane = intel_crtc->plane;
3441         bool is_pch_port;
3442
3443         WARN_ON(!crtc->enabled);
3444
3445         if (intel_crtc->active)
3446                 return;
3447
3448         intel_crtc->active = true;
3449         intel_update_watermarks(dev);
3450
3451         is_pch_port = haswell_crtc_driving_pch(crtc);
3452
3453         if (is_pch_port)
3454                 ironlake_fdi_pll_enable(intel_crtc);
3455
3456         for_each_encoder_on_crtc(dev, crtc, encoder)
3457                 if (encoder->pre_enable)
3458                         encoder->pre_enable(encoder);
3459
3460         intel_ddi_enable_pipe_clock(intel_crtc);
3461
3462         /* Enable panel fitting for eDP */
3463         if (dev_priv->pch_pf_size && HAS_eDP) {
3464                 /* Force use of hard-coded filter coefficients
3465                  * as some pre-programmed values are broken,
3466                  * e.g. x201.
3467                  */
3468                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3469                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3471         }
3472
3473         /*
3474          * On ILK+ LUT must be loaded before the pipe is running but with
3475          * clocks enabled
3476          */
3477         intel_crtc_load_lut(crtc);
3478
3479         intel_ddi_set_pipe_settings(crtc);
3480         intel_ddi_enable_pipe_func(crtc);
3481
3482         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3483         intel_enable_plane(dev_priv, plane, pipe);
3484
3485         if (is_pch_port)
3486                 lpt_pch_enable(crtc);
3487
3488         mutex_lock(&dev->struct_mutex);
3489         intel_update_fbc(dev);
3490         mutex_unlock(&dev->struct_mutex);
3491
3492         intel_crtc_update_cursor(crtc, true);
3493
3494         for_each_encoder_on_crtc(dev, crtc, encoder)
3495                 encoder->enable(encoder);
3496
3497         /*
3498          * There seems to be a race in PCH platform hw (at least on some
3499          * outputs) where an enabled pipe still completes any pageflip right
3500          * away (as if the pipe is off) instead of waiting for vblank. As soon
3501          * as the first vblank happend, everything works as expected. Hence just
3502          * wait for one vblank before returning to avoid strange things
3503          * happening.
3504          */
3505         intel_wait_for_vblank(dev, intel_crtc->pipe);
3506 }
3507
3508 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         struct intel_encoder *encoder;
3514         int pipe = intel_crtc->pipe;
3515         int plane = intel_crtc->plane;
3516         u32 reg, temp;
3517
3518
3519         if (!intel_crtc->active)
3520                 return;
3521
3522         for_each_encoder_on_crtc(dev, crtc, encoder)
3523                 encoder->disable(encoder);
3524
3525         intel_crtc_wait_for_pending_flips(crtc);
3526         drm_vblank_off(dev, pipe);
3527         intel_crtc_update_cursor(crtc, false);
3528
3529         intel_disable_plane(dev_priv, plane, pipe);
3530
3531         if (dev_priv->cfb_plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         intel_disable_pipe(dev_priv, pipe);
3535
3536         /* Disable PF */
3537         I915_WRITE(PF_CTL(pipe), 0);
3538         I915_WRITE(PF_WIN_SZ(pipe), 0);
3539
3540         for_each_encoder_on_crtc(dev, crtc, encoder)
3541                 if (encoder->post_disable)
3542                         encoder->post_disable(encoder);
3543
3544         ironlake_fdi_disable(crtc);
3545
3546         ironlake_disable_pch_transcoder(dev_priv, pipe);
3547
3548         if (HAS_PCH_CPT(dev)) {
3549                 /* disable TRANS_DP_CTL */
3550                 reg = TRANS_DP_CTL(pipe);
3551                 temp = I915_READ(reg);
3552                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3553                 temp |= TRANS_DP_PORT_SEL_NONE;
3554                 I915_WRITE(reg, temp);
3555
3556                 /* disable DPLL_SEL */
3557                 temp = I915_READ(PCH_DPLL_SEL);
3558                 switch (pipe) {
3559                 case 0:
3560                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3561                         break;
3562                 case 1:
3563                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3564                         break;
3565                 case 2:
3566                         /* C shares PLL A or B */
3567                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3568                         break;
3569                 default:
3570                         BUG(); /* wtf */
3571                 }
3572                 I915_WRITE(PCH_DPLL_SEL, temp);
3573         }
3574
3575         /* disable PCH DPLL */
3576         intel_disable_pch_pll(intel_crtc);
3577
3578         ironlake_fdi_pll_disable(intel_crtc);
3579
3580         intel_crtc->active = false;
3581         intel_update_watermarks(dev);
3582
3583         mutex_lock(&dev->struct_mutex);
3584         intel_update_fbc(dev);
3585         mutex_unlock(&dev->struct_mutex);
3586 }
3587
3588 static void haswell_crtc_disable(struct drm_crtc *crtc)
3589 {
3590         struct drm_device *dev = crtc->dev;
3591         struct drm_i915_private *dev_priv = dev->dev_private;
3592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593         struct intel_encoder *encoder;
3594         int pipe = intel_crtc->pipe;
3595         int plane = intel_crtc->plane;
3596         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3597         bool is_pch_port;
3598
3599         if (!intel_crtc->active)
3600                 return;
3601
3602         is_pch_port = haswell_crtc_driving_pch(crtc);
3603
3604         for_each_encoder_on_crtc(dev, crtc, encoder)
3605                 encoder->disable(encoder);
3606
3607         intel_crtc_wait_for_pending_flips(crtc);
3608         drm_vblank_off(dev, pipe);
3609         intel_crtc_update_cursor(crtc, false);
3610
3611         intel_disable_plane(dev_priv, plane, pipe);
3612
3613         if (dev_priv->cfb_plane == plane)
3614                 intel_disable_fbc(dev);
3615
3616         intel_disable_pipe(dev_priv, pipe);
3617
3618         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3619
3620         /* Disable PF */
3621         I915_WRITE(PF_CTL(pipe), 0);
3622         I915_WRITE(PF_WIN_SZ(pipe), 0);
3623
3624         intel_ddi_disable_pipe_clock(intel_crtc);
3625
3626         for_each_encoder_on_crtc(dev, crtc, encoder)
3627                 if (encoder->post_disable)
3628                         encoder->post_disable(encoder);
3629
3630         if (is_pch_port) {
3631                 ironlake_fdi_disable(crtc);
3632                 lpt_disable_pch_transcoder(dev_priv);
3633                 ironlake_fdi_pll_disable(intel_crtc);
3634         }
3635
3636         intel_crtc->active = false;
3637         intel_update_watermarks(dev);
3638
3639         mutex_lock(&dev->struct_mutex);
3640         intel_update_fbc(dev);
3641         mutex_unlock(&dev->struct_mutex);
3642 }
3643
3644 static void ironlake_crtc_off(struct drm_crtc *crtc)
3645 {
3646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647         intel_put_pch_pll(intel_crtc);
3648 }
3649
3650 static void haswell_crtc_off(struct drm_crtc *crtc)
3651 {
3652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653
3654         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3655          * start using it. */
3656         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3657
3658         intel_ddi_put_crtc_pll(crtc);
3659 }
3660
3661 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3662 {
3663         if (!enable && intel_crtc->overlay) {
3664                 struct drm_device *dev = intel_crtc->base.dev;
3665                 struct drm_i915_private *dev_priv = dev->dev_private;
3666
3667                 mutex_lock(&dev->struct_mutex);
3668                 dev_priv->mm.interruptible = false;
3669                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3670                 dev_priv->mm.interruptible = true;
3671                 mutex_unlock(&dev->struct_mutex);
3672         }
3673
3674         /* Let userspace switch the overlay on again. In most cases userspace
3675          * has to recompute where to put it anyway.
3676          */
3677 }
3678
3679 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3680 {
3681         struct drm_device *dev = crtc->dev;
3682         struct drm_i915_private *dev_priv = dev->dev_private;
3683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684         struct intel_encoder *encoder;
3685         int pipe = intel_crtc->pipe;
3686         int plane = intel_crtc->plane;
3687
3688         WARN_ON(!crtc->enabled);
3689
3690         if (intel_crtc->active)
3691                 return;
3692
3693         intel_crtc->active = true;
3694         intel_update_watermarks(dev);
3695
3696         intel_enable_pll(dev_priv, pipe);
3697         intel_enable_pipe(dev_priv, pipe, false);
3698         intel_enable_plane(dev_priv, plane, pipe);
3699
3700         intel_crtc_load_lut(crtc);
3701         intel_update_fbc(dev);
3702
3703         /* Give the overlay scaler a chance to enable if it's on this pipe */
3704         intel_crtc_dpms_overlay(intel_crtc, true);
3705         intel_crtc_update_cursor(crtc, true);
3706
3707         for_each_encoder_on_crtc(dev, crtc, encoder)
3708                 encoder->enable(encoder);
3709 }
3710
3711 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712 {
3713         struct drm_device *dev = crtc->dev;
3714         struct drm_i915_private *dev_priv = dev->dev_private;
3715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716         struct intel_encoder *encoder;
3717         int pipe = intel_crtc->pipe;
3718         int plane = intel_crtc->plane;
3719
3720
3721         if (!intel_crtc->active)
3722                 return;
3723
3724         for_each_encoder_on_crtc(dev, crtc, encoder)
3725                 encoder->disable(encoder);
3726
3727         /* Give the overlay scaler a chance to disable if it's on this pipe */
3728         intel_crtc_wait_for_pending_flips(crtc);
3729         drm_vblank_off(dev, pipe);
3730         intel_crtc_dpms_overlay(intel_crtc, false);
3731         intel_crtc_update_cursor(crtc, false);
3732
3733         if (dev_priv->cfb_plane == plane)
3734                 intel_disable_fbc(dev);
3735
3736         intel_disable_plane(dev_priv, plane, pipe);
3737         intel_disable_pipe(dev_priv, pipe);
3738         intel_disable_pll(dev_priv, pipe);
3739
3740         intel_crtc->active = false;
3741         intel_update_fbc(dev);
3742         intel_update_watermarks(dev);
3743 }
3744
3745 static void i9xx_crtc_off(struct drm_crtc *crtc)
3746 {
3747 }
3748
3749 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3750                                     bool enabled)
3751 {
3752         struct drm_device *dev = crtc->dev;
3753         struct drm_i915_master_private *master_priv;
3754         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755         int pipe = intel_crtc->pipe;
3756
3757         if (!dev->primary->master)
3758                 return;
3759
3760         master_priv = dev->primary->master->driver_priv;
3761         if (!master_priv->sarea_priv)
3762                 return;
3763
3764         switch (pipe) {
3765         case 0:
3766                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3767                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3768                 break;
3769         case 1:
3770                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3771                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3772                 break;
3773         default:
3774                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3775                 break;
3776         }
3777 }
3778
3779 /**
3780  * Sets the power management mode of the pipe and plane.
3781  */
3782 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3783 {
3784         struct drm_device *dev = crtc->dev;
3785         struct drm_i915_private *dev_priv = dev->dev_private;
3786         struct intel_encoder *intel_encoder;
3787         bool enable = false;
3788
3789         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3790                 enable |= intel_encoder->connectors_active;
3791
3792         if (enable)
3793                 dev_priv->display.crtc_enable(crtc);
3794         else
3795                 dev_priv->display.crtc_disable(crtc);
3796
3797         intel_crtc_update_sarea(crtc, enable);
3798 }
3799
3800 static void intel_crtc_noop(struct drm_crtc *crtc)
3801 {
3802 }
3803
3804 static void intel_crtc_disable(struct drm_crtc *crtc)
3805 {
3806         struct drm_device *dev = crtc->dev;
3807         struct drm_connector *connector;
3808         struct drm_i915_private *dev_priv = dev->dev_private;
3809
3810         /* crtc should still be enabled when we disable it. */
3811         WARN_ON(!crtc->enabled);
3812
3813         dev_priv->display.crtc_disable(crtc);
3814         intel_crtc_update_sarea(crtc, false);
3815         dev_priv->display.off(crtc);
3816
3817         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3818         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3819
3820         if (crtc->fb) {
3821                 mutex_lock(&dev->struct_mutex);
3822                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3823                 mutex_unlock(&dev->struct_mutex);
3824                 crtc->fb = NULL;
3825         }
3826
3827         /* Update computed state. */
3828         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3829                 if (!connector->encoder || !connector->encoder->crtc)
3830                         continue;
3831
3832                 if (connector->encoder->crtc != crtc)
3833                         continue;
3834
3835                 connector->dpms = DRM_MODE_DPMS_OFF;
3836                 to_intel_encoder(connector->encoder)->connectors_active = false;
3837         }
3838 }
3839
3840 void intel_modeset_disable(struct drm_device *dev)
3841 {
3842         struct drm_crtc *crtc;
3843
3844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3845                 if (crtc->enabled)
3846                         intel_crtc_disable(crtc);
3847         }
3848 }
3849
3850 void intel_encoder_noop(struct drm_encoder *encoder)
3851 {
3852 }
3853
3854 void intel_encoder_destroy(struct drm_encoder *encoder)
3855 {
3856         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3857
3858         drm_encoder_cleanup(encoder);
3859         kfree(intel_encoder);
3860 }
3861
3862 /* Simple dpms helper for encodres with just one connector, no cloning and only
3863  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864  * state of the entire output pipe. */
3865 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3866 {
3867         if (mode == DRM_MODE_DPMS_ON) {
3868                 encoder->connectors_active = true;
3869
3870                 intel_crtc_update_dpms(encoder->base.crtc);
3871         } else {
3872                 encoder->connectors_active = false;
3873
3874                 intel_crtc_update_dpms(encoder->base.crtc);
3875         }
3876 }
3877
3878 /* Cross check the actual hw state with our own modeset state tracking (and it's
3879  * internal consistency). */
3880 static void intel_connector_check_state(struct intel_connector *connector)
3881 {
3882         if (connector->get_hw_state(connector)) {
3883                 struct intel_encoder *encoder = connector->encoder;
3884                 struct drm_crtc *crtc;
3885                 bool encoder_enabled;
3886                 enum pipe pipe;
3887
3888                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889                               connector->base.base.id,
3890                               drm_get_connector_name(&connector->base));
3891
3892                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893                      "wrong connector dpms state\n");
3894                 WARN(connector->base.encoder != &encoder->base,
3895                      "active connector not linked to encoder\n");
3896                 WARN(!encoder->connectors_active,
3897                      "encoder->connectors_active not set\n");
3898
3899                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900                 WARN(!encoder_enabled, "encoder not enabled\n");
3901                 if (WARN_ON(!encoder->base.crtc))
3902                         return;
3903
3904                 crtc = encoder->base.crtc;
3905
3906                 WARN(!crtc->enabled, "crtc not enabled\n");
3907                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909                      "encoder active on the wrong pipe\n");
3910         }
3911 }
3912
3913 /* Even simpler default implementation, if there's really no special case to
3914  * consider. */
3915 void intel_connector_dpms(struct drm_connector *connector, int mode)
3916 {
3917         struct intel_encoder *encoder = intel_attached_encoder(connector);
3918
3919         /* All the simple cases only support two dpms states. */
3920         if (mode != DRM_MODE_DPMS_ON)
3921                 mode = DRM_MODE_DPMS_OFF;
3922
3923         if (mode == connector->dpms)
3924                 return;
3925
3926         connector->dpms = mode;
3927
3928         /* Only need to change hw state when actually enabled */
3929         if (encoder->base.crtc)
3930                 intel_encoder_dpms(encoder, mode);
3931         else
3932                 WARN_ON(encoder->connectors_active != false);
3933
3934         intel_modeset_check_state(connector->dev);
3935 }
3936
3937 /* Simple connector->get_hw_state implementation for encoders that support only
3938  * one connector and no cloning and hence the encoder state determines the state
3939  * of the connector. */
3940 bool intel_connector_get_hw_state(struct intel_connector *connector)
3941 {
3942         enum pipe pipe = 0;
3943         struct intel_encoder *encoder = connector->encoder;
3944
3945         return encoder->get_hw_state(encoder, &pipe);
3946 }
3947
3948 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3949                                   const struct drm_display_mode *mode,
3950                                   struct drm_display_mode *adjusted_mode)
3951 {
3952         struct drm_device *dev = crtc->dev;
3953
3954         if (HAS_PCH_SPLIT(dev)) {
3955                 /* FDI link clock is fixed at 2.7G */
3956                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3957                         return false;
3958         }
3959
3960         /* All interlaced capable intel hw wants timings in frames. Note though
3961          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3962          * timings, so we need to be careful not to clobber these.*/
3963         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3964                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3965
3966         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3967          * with a hsync front porch of 0.
3968          */
3969         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3970                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3971                 return false;
3972
3973         return true;
3974 }
3975
3976 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3977 {
3978         return 400000; /* FIXME */
3979 }
3980
3981 static int i945_get_display_clock_speed(struct drm_device *dev)
3982 {
3983         return 400000;
3984 }
3985
3986 static int i915_get_display_clock_speed(struct drm_device *dev)
3987 {
3988         return 333000;
3989 }
3990
3991 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3992 {
3993         return 200000;
3994 }
3995
3996 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3997 {
3998         u16 gcfgc = 0;
3999
4000         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4001
4002         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4003                 return 133000;
4004         else {
4005                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4006                 case GC_DISPLAY_CLOCK_333_MHZ:
4007                         return 333000;
4008                 default:
4009                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4010                         return 190000;
4011                 }
4012         }
4013 }
4014
4015 static int i865_get_display_clock_speed(struct drm_device *dev)
4016 {
4017         return 266000;
4018 }
4019
4020 static int i855_get_display_clock_speed(struct drm_device *dev)
4021 {
4022         u16 hpllcc = 0;
4023         /* Assume that the hardware is in the high speed state.  This
4024          * should be the default.
4025          */
4026         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4027         case GC_CLOCK_133_200:
4028         case GC_CLOCK_100_200:
4029                 return 200000;
4030         case GC_CLOCK_166_250:
4031                 return 250000;
4032         case GC_CLOCK_100_133:
4033                 return 133000;
4034         }
4035
4036         /* Shouldn't happen */
4037         return 0;
4038 }
4039
4040 static int i830_get_display_clock_speed(struct drm_device *dev)
4041 {
4042         return 133000;
4043 }
4044
4045 struct fdi_m_n {
4046         u32        tu;
4047         u32        gmch_m;
4048         u32        gmch_n;
4049         u32        link_m;
4050         u32        link_n;
4051 };
4052
4053 static void
4054 fdi_reduce_ratio(u32 *num, u32 *den)
4055 {
4056         while (*num > 0xffffff || *den > 0xffffff) {
4057                 *num >>= 1;
4058                 *den >>= 1;
4059         }
4060 }
4061
4062 static void
4063 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4064                      int link_clock, struct fdi_m_n *m_n)
4065 {
4066         m_n->tu = 64; /* default size */
4067
4068         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4069         m_n->gmch_m = bits_per_pixel * pixel_clock;
4070         m_n->gmch_n = link_clock * nlanes * 8;
4071         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072
4073         m_n->link_m = pixel_clock;
4074         m_n->link_n = link_clock;
4075         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4076 }
4077
4078 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079 {
4080         if (i915_panel_use_ssc >= 0)
4081                 return i915_panel_use_ssc != 0;
4082         return dev_priv->lvds_use_ssc
4083                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4084 }
4085
4086 /**
4087  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4088  * @crtc: CRTC structure
4089  * @mode: requested mode
4090  *
4091  * A pipe may be connected to one or more outputs.  Based on the depth of the
4092  * attached framebuffer, choose a good color depth to use on the pipe.
4093  *
4094  * If possible, match the pipe depth to the fb depth.  In some cases, this
4095  * isn't ideal, because the connected output supports a lesser or restricted
4096  * set of depths.  Resolve that here:
4097  *    LVDS typically supports only 6bpc, so clamp down in that case
4098  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4099  *    Displays may support a restricted set as well, check EDID and clamp as
4100  *      appropriate.
4101  *    DP may want to dither down to 6bpc to fit larger modes
4102  *
4103  * RETURNS:
4104  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4105  * true if they don't match).
4106  */
4107 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4108                                          struct drm_framebuffer *fb,
4109                                          unsigned int *pipe_bpp,
4110                                          struct drm_display_mode *mode)
4111 {
4112         struct drm_device *dev = crtc->dev;
4113         struct drm_i915_private *dev_priv = dev->dev_private;
4114         struct drm_connector *connector;
4115         struct intel_encoder *intel_encoder;
4116         unsigned int display_bpc = UINT_MAX, bpc;
4117
4118         /* Walk the encoders & connectors on this crtc, get min bpc */
4119         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4120
4121                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4122                         unsigned int lvds_bpc;
4123
4124                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4125                             LVDS_A3_POWER_UP)
4126                                 lvds_bpc = 8;
4127                         else
4128                                 lvds_bpc = 6;
4129
4130                         if (lvds_bpc < display_bpc) {
4131                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4132                                 display_bpc = lvds_bpc;
4133                         }
4134                         continue;
4135                 }
4136
4137                 /* Not one of the known troublemakers, check the EDID */
4138                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4139                                     head) {
4140                         if (connector->encoder != &intel_encoder->base)
4141                                 continue;
4142
4143                         /* Don't use an invalid EDID bpc value */
4144                         if (connector->display_info.bpc &&
4145                             connector->display_info.bpc < display_bpc) {
4146                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4147                                 display_bpc = connector->display_info.bpc;
4148                         }
4149                 }
4150
4151                 /*
4152                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4153                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4154                  */
4155                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4156                         if (display_bpc > 8 && display_bpc < 12) {
4157                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4158                                 display_bpc = 12;
4159                         } else {
4160                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4161                                 display_bpc = 8;
4162                         }
4163                 }
4164         }
4165
4166         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4167                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4168                 display_bpc = 6;
4169         }
4170
4171         /*
4172          * We could just drive the pipe at the highest bpc all the time and
4173          * enable dithering as needed, but that costs bandwidth.  So choose
4174          * the minimum value that expresses the full color range of the fb but
4175          * also stays within the max display bpc discovered above.
4176          */
4177
4178         switch (fb->depth) {
4179         case 8:
4180                 bpc = 8; /* since we go through a colormap */
4181                 break;
4182         case 15:
4183         case 16:
4184                 bpc = 6; /* min is 18bpp */
4185                 break;
4186         case 24:
4187                 bpc = 8;
4188                 break;
4189         case 30:
4190                 bpc = 10;
4191                 break;
4192         case 48:
4193                 bpc = 12;
4194                 break;
4195         default:
4196                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4197                 bpc = min((unsigned int)8, display_bpc);
4198                 break;
4199         }
4200
4201         display_bpc = min(display_bpc, bpc);
4202
4203         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4204                       bpc, display_bpc);
4205
4206         *pipe_bpp = display_bpc * 3;
4207
4208         return display_bpc != bpc;
4209 }
4210
4211 static int vlv_get_refclk(struct drm_crtc *crtc)
4212 {
4213         struct drm_device *dev = crtc->dev;
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         int refclk = 27000; /* for DP & HDMI */
4216
4217         return 100000; /* only one validated so far */
4218
4219         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4220                 refclk = 96000;
4221         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4222                 if (intel_panel_use_ssc(dev_priv))
4223                         refclk = 100000;
4224                 else
4225                         refclk = 96000;
4226         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4227                 refclk = 100000;
4228         }
4229
4230         return refclk;
4231 }
4232
4233 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4234 {
4235         struct drm_device *dev = crtc->dev;
4236         struct drm_i915_private *dev_priv = dev->dev_private;
4237         int refclk;
4238
4239         if (IS_VALLEYVIEW(dev)) {
4240                 refclk = vlv_get_refclk(crtc);
4241         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4242             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4243                 refclk = dev_priv->lvds_ssc_freq * 1000;
4244                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4245                               refclk / 1000);
4246         } else if (!IS_GEN2(dev)) {
4247                 refclk = 96000;
4248         } else {
4249                 refclk = 48000;
4250         }
4251
4252         return refclk;
4253 }
4254
4255 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4256                                       intel_clock_t *clock)
4257 {
4258         /* SDVO TV has fixed PLL values depend on its clock range,
4259            this mirrors vbios setting. */
4260         if (adjusted_mode->clock >= 100000
4261             && adjusted_mode->clock < 140500) {
4262                 clock->p1 = 2;
4263                 clock->p2 = 10;
4264                 clock->n = 3;
4265                 clock->m1 = 16;
4266                 clock->m2 = 8;
4267         } else if (adjusted_mode->clock >= 140500
4268                    && adjusted_mode->clock <= 200000) {
4269                 clock->p1 = 1;
4270                 clock->p2 = 10;
4271                 clock->n = 6;
4272                 clock->m1 = 12;
4273                 clock->m2 = 8;
4274         }
4275 }
4276
4277 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4278                                      intel_clock_t *clock,
4279                                      intel_clock_t *reduced_clock)
4280 {
4281         struct drm_device *dev = crtc->dev;
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284         int pipe = intel_crtc->pipe;
4285         u32 fp, fp2 = 0;
4286
4287         if (IS_PINEVIEW(dev)) {
4288                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4289                 if (reduced_clock)
4290                         fp2 = (1 << reduced_clock->n) << 16 |
4291                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4292         } else {
4293                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4294                 if (reduced_clock)
4295                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4296                                 reduced_clock->m2;
4297         }
4298
4299         I915_WRITE(FP0(pipe), fp);
4300
4301         intel_crtc->lowfreq_avail = false;
4302         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4303             reduced_clock && i915_powersave) {
4304                 I915_WRITE(FP1(pipe), fp2);
4305                 intel_crtc->lowfreq_avail = true;
4306         } else {
4307                 I915_WRITE(FP1(pipe), fp);
4308         }
4309 }
4310
4311 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4312                               struct drm_display_mode *adjusted_mode)
4313 {
4314         struct drm_device *dev = crtc->dev;
4315         struct drm_i915_private *dev_priv = dev->dev_private;
4316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317         int pipe = intel_crtc->pipe;
4318         u32 temp;
4319
4320         temp = I915_READ(LVDS);
4321         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4322         if (pipe == 1) {
4323                 temp |= LVDS_PIPEB_SELECT;
4324         } else {
4325                 temp &= ~LVDS_PIPEB_SELECT;
4326         }
4327         /* set the corresponsding LVDS_BORDER bit */
4328         temp |= dev_priv->lvds_border_bits;
4329         /* Set the B0-B3 data pairs corresponding to whether we're going to
4330          * set the DPLLs for dual-channel mode or not.
4331          */
4332         if (clock->p2 == 7)
4333                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4334         else
4335                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4336
4337         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4338          * appropriately here, but we need to look more thoroughly into how
4339          * panels behave in the two modes.
4340          */
4341         /* set the dithering flag on LVDS as needed */
4342         if (INTEL_INFO(dev)->gen >= 4) {
4343                 if (dev_priv->lvds_dither)
4344                         temp |= LVDS_ENABLE_DITHER;
4345                 else
4346                         temp &= ~LVDS_ENABLE_DITHER;
4347         }
4348         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4349         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4350                 temp |= LVDS_HSYNC_POLARITY;
4351         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4352                 temp |= LVDS_VSYNC_POLARITY;
4353         I915_WRITE(LVDS, temp);
4354 }
4355
4356 static void vlv_update_pll(struct drm_crtc *crtc,
4357                            struct drm_display_mode *mode,
4358                            struct drm_display_mode *adjusted_mode,
4359                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4360                            int num_connectors)
4361 {
4362         struct drm_device *dev = crtc->dev;
4363         struct drm_i915_private *dev_priv = dev->dev_private;
4364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365         int pipe = intel_crtc->pipe;
4366         u32 dpll, mdiv, pdiv;
4367         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4368         bool is_sdvo;
4369         u32 temp;
4370
4371         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4372                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4373
4374         dpll = DPLL_VGA_MODE_DIS;
4375         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4378
4379         I915_WRITE(DPLL(pipe), dpll);
4380         POSTING_READ(DPLL(pipe));
4381
4382         bestn = clock->n;
4383         bestm1 = clock->m1;
4384         bestm2 = clock->m2;
4385         bestp1 = clock->p1;
4386         bestp2 = clock->p2;
4387
4388         /*
4389          * In Valleyview PLL and program lane counter registers are exposed
4390          * through DPIO interface
4391          */
4392         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394         mdiv |= ((bestn << DPIO_N_SHIFT));
4395         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4396         mdiv |= (1 << DPIO_K_SHIFT);
4397         mdiv |= DPIO_ENABLE_CALIBRATION;
4398         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4399
4400         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4401
4402         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4403                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4404                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4405                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4406         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4407
4408         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4409
4410         dpll |= DPLL_VCO_ENABLE;
4411         I915_WRITE(DPLL(pipe), dpll);
4412         POSTING_READ(DPLL(pipe));
4413         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4415
4416         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4417
4418         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4420
4421         I915_WRITE(DPLL(pipe), dpll);
4422
4423         /* Wait for the clocks to stabilize. */
4424         POSTING_READ(DPLL(pipe));
4425         udelay(150);
4426
4427         temp = 0;
4428         if (is_sdvo) {
4429                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4430                 if (temp > 1)
4431                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4432                 else
4433                         temp = 0;
4434         }
4435         I915_WRITE(DPLL_MD(pipe), temp);
4436         POSTING_READ(DPLL_MD(pipe));
4437
4438         /* Now program lane control registers */
4439         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4440                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4441         {
4442                 temp = 0x1000C4;
4443                 if(pipe == 1)
4444                         temp |= (1 << 21);
4445                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4446         }
4447         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4448         {
4449                 temp = 0x1000C4;
4450                 if(pipe == 1)
4451                         temp |= (1 << 21);
4452                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4453         }
4454 }
4455
4456 static void i9xx_update_pll(struct drm_crtc *crtc,
4457                             struct drm_display_mode *mode,
4458                             struct drm_display_mode *adjusted_mode,
4459                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4460                             int num_connectors)
4461 {
4462         struct drm_device *dev = crtc->dev;
4463         struct drm_i915_private *dev_priv = dev->dev_private;
4464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465         int pipe = intel_crtc->pipe;
4466         u32 dpll;
4467         bool is_sdvo;
4468
4469         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4470
4471         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4473
4474         dpll = DPLL_VGA_MODE_DIS;
4475
4476         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477                 dpll |= DPLLB_MODE_LVDS;
4478         else
4479                 dpll |= DPLLB_MODE_DAC_SERIAL;
4480         if (is_sdvo) {
4481                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482                 if (pixel_multiplier > 1) {
4483                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4485                 }
4486                 dpll |= DPLL_DVO_HIGH_SPEED;
4487         }
4488         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489                 dpll |= DPLL_DVO_HIGH_SPEED;
4490
4491         /* compute bitmask from p1 value */
4492         if (IS_PINEVIEW(dev))
4493                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4494         else {
4495                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496                 if (IS_G4X(dev) && reduced_clock)
4497                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4498         }
4499         switch (clock->p2) {
4500         case 5:
4501                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4502                 break;
4503         case 7:
4504                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4505                 break;
4506         case 10:
4507                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4508                 break;
4509         case 14:
4510                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4511                 break;
4512         }
4513         if (INTEL_INFO(dev)->gen >= 4)
4514                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4515
4516         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519                 /* XXX: just matching BIOS for now */
4520                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521                 dpll |= 3;
4522         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525         else
4526                 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528         dpll |= DPLL_VCO_ENABLE;
4529         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530         POSTING_READ(DPLL(pipe));
4531         udelay(150);
4532
4533         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4534          * This is an exception to the general rule that mode_set doesn't turn
4535          * things on.
4536          */
4537         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4538                 intel_update_lvds(crtc, clock, adjusted_mode);
4539
4540         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4541                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4542
4543         I915_WRITE(DPLL(pipe), dpll);
4544
4545         /* Wait for the clocks to stabilize. */
4546         POSTING_READ(DPLL(pipe));
4547         udelay(150);
4548
4549         if (INTEL_INFO(dev)->gen >= 4) {
4550                 u32 temp = 0;
4551                 if (is_sdvo) {
4552                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4553                         if (temp > 1)
4554                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4555                         else
4556                                 temp = 0;
4557                 }
4558                 I915_WRITE(DPLL_MD(pipe), temp);
4559         } else {
4560                 /* The pixel multiplier can only be updated once the
4561                  * DPLL is enabled and the clocks are stable.
4562                  *
4563                  * So write it again.
4564                  */
4565                 I915_WRITE(DPLL(pipe), dpll);
4566         }
4567 }
4568
4569 static void i8xx_update_pll(struct drm_crtc *crtc,
4570                             struct drm_display_mode *adjusted_mode,
4571                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4572                             int num_connectors)
4573 {
4574         struct drm_device *dev = crtc->dev;
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577         int pipe = intel_crtc->pipe;
4578         u32 dpll;
4579
4580         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4581
4582         dpll = DPLL_VGA_MODE_DIS;
4583
4584         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4585                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586         } else {
4587                 if (clock->p1 == 2)
4588                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4589                 else
4590                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591                 if (clock->p2 == 4)
4592                         dpll |= PLL_P2_DIVIDE_BY_4;
4593         }
4594
4595         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4596                 /* XXX: just matching BIOS for now */
4597                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4598                 dpll |= 3;
4599         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4600                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4601                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4602         else
4603                 dpll |= PLL_REF_INPUT_DREFCLK;
4604
4605         dpll |= DPLL_VCO_ENABLE;
4606         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607         POSTING_READ(DPLL(pipe));
4608         udelay(150);
4609
4610         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4611          * This is an exception to the general rule that mode_set doesn't turn
4612          * things on.
4613          */
4614         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4615                 intel_update_lvds(crtc, clock, adjusted_mode);
4616
4617         I915_WRITE(DPLL(pipe), dpll);
4618
4619         /* Wait for the clocks to stabilize. */
4620         POSTING_READ(DPLL(pipe));
4621         udelay(150);
4622
4623         /* The pixel multiplier can only be updated once the
4624          * DPLL is enabled and the clocks are stable.
4625          *
4626          * So write it again.
4627          */
4628         I915_WRITE(DPLL(pipe), dpll);
4629 }
4630
4631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4632                                    struct drm_display_mode *mode,
4633                                    struct drm_display_mode *adjusted_mode)
4634 {
4635         struct drm_device *dev = intel_crtc->base.dev;
4636         struct drm_i915_private *dev_priv = dev->dev_private;
4637         enum pipe pipe = intel_crtc->pipe;
4638         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4639         uint32_t vsyncshift;
4640
4641         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642                 /* the chip adds 2 halflines automatically */
4643                 adjusted_mode->crtc_vtotal -= 1;
4644                 adjusted_mode->crtc_vblank_end -= 1;
4645                 vsyncshift = adjusted_mode->crtc_hsync_start
4646                              - adjusted_mode->crtc_htotal / 2;
4647         } else {
4648                 vsyncshift = 0;
4649         }
4650
4651         if (INTEL_INFO(dev)->gen > 3)
4652                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4653
4654         I915_WRITE(HTOTAL(cpu_transcoder),
4655                    (adjusted_mode->crtc_hdisplay - 1) |
4656                    ((adjusted_mode->crtc_htotal - 1) << 16));
4657         I915_WRITE(HBLANK(cpu_transcoder),
4658                    (adjusted_mode->crtc_hblank_start - 1) |
4659                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4660         I915_WRITE(HSYNC(cpu_transcoder),
4661                    (adjusted_mode->crtc_hsync_start - 1) |
4662                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4663
4664         I915_WRITE(VTOTAL(cpu_transcoder),
4665                    (adjusted_mode->crtc_vdisplay - 1) |
4666                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4667         I915_WRITE(VBLANK(cpu_transcoder),
4668                    (adjusted_mode->crtc_vblank_start - 1) |
4669                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4670         I915_WRITE(VSYNC(cpu_transcoder),
4671                    (adjusted_mode->crtc_vsync_start - 1) |
4672                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4673
4674         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4675          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4676          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4677          * bits. */
4678         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4679             (pipe == PIPE_B || pipe == PIPE_C))
4680                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4681
4682         /* pipesrc controls the size that is scaled from, which should
4683          * always be the user's requested size.
4684          */
4685         I915_WRITE(PIPESRC(pipe),
4686                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4687 }
4688
4689 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4690                               struct drm_display_mode *mode,
4691                               struct drm_display_mode *adjusted_mode,
4692                               int x, int y,
4693                               struct drm_framebuffer *fb)
4694 {
4695         struct drm_device *dev = crtc->dev;
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698         int pipe = intel_crtc->pipe;
4699         int plane = intel_crtc->plane;
4700         int refclk, num_connectors = 0;
4701         intel_clock_t clock, reduced_clock;
4702         u32 dspcntr, pipeconf;
4703         bool ok, has_reduced_clock = false, is_sdvo = false;
4704         bool is_lvds = false, is_tv = false, is_dp = false;
4705         struct intel_encoder *encoder;
4706         const intel_limit_t *limit;
4707         int ret;
4708
4709         for_each_encoder_on_crtc(dev, crtc, encoder) {
4710                 switch (encoder->type) {
4711                 case INTEL_OUTPUT_LVDS:
4712                         is_lvds = true;
4713                         break;
4714                 case INTEL_OUTPUT_SDVO:
4715                 case INTEL_OUTPUT_HDMI:
4716                         is_sdvo = true;
4717                         if (encoder->needs_tv_clock)
4718                                 is_tv = true;
4719                         break;
4720                 case INTEL_OUTPUT_TVOUT:
4721                         is_tv = true;
4722                         break;
4723                 case INTEL_OUTPUT_DISPLAYPORT:
4724                         is_dp = true;
4725                         break;
4726                 }
4727
4728                 num_connectors++;
4729         }
4730
4731         refclk = i9xx_get_refclk(crtc, num_connectors);
4732
4733         /*
4734          * Returns a set of divisors for the desired target clock with the given
4735          * refclk, or FALSE.  The returned values represent the clock equation:
4736          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4737          */
4738         limit = intel_limit(crtc, refclk);
4739         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4740                              &clock);
4741         if (!ok) {
4742                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4743                 return -EINVAL;
4744         }
4745
4746         /* Ensure that the cursor is valid for the new mode before changing... */
4747         intel_crtc_update_cursor(crtc, true);
4748
4749         if (is_lvds && dev_priv->lvds_downclock_avail) {
4750                 /*
4751                  * Ensure we match the reduced clock's P to the target clock.
4752                  * If the clocks don't match, we can't switch the display clock
4753                  * by using the FP0/FP1. In such case we will disable the LVDS
4754                  * downclock feature.
4755                 */
4756                 has_reduced_clock = limit->find_pll(limit, crtc,
4757                                                     dev_priv->lvds_downclock,
4758                                                     refclk,
4759                                                     &clock,
4760                                                     &reduced_clock);
4761         }
4762
4763         if (is_sdvo && is_tv)
4764                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4765
4766         if (IS_GEN2(dev))
4767                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4768                                 has_reduced_clock ? &reduced_clock : NULL,
4769                                 num_connectors);
4770         else if (IS_VALLEYVIEW(dev))
4771                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4772                                 has_reduced_clock ? &reduced_clock : NULL,
4773                                 num_connectors);
4774         else
4775                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4776                                 has_reduced_clock ? &reduced_clock : NULL,
4777                                 num_connectors);
4778
4779         /* setup pipeconf */
4780         pipeconf = I915_READ(PIPECONF(pipe));
4781
4782         /* Set up the display plane register */
4783         dspcntr = DISPPLANE_GAMMA_ENABLE;
4784
4785         if (pipe == 0)
4786                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4787         else
4788                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4789
4790         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792                  * core speed.
4793                  *
4794                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795                  * pipe == 0 check?
4796                  */
4797                 if (mode->clock >
4798                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4800                 else
4801                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4802         }
4803
4804         /* default to 8bpc */
4805         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4806         if (is_dp) {
4807                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4808                         pipeconf |= PIPECONF_BPP_6 |
4809                                     PIPECONF_DITHER_EN |
4810                                     PIPECONF_DITHER_TYPE_SP;
4811                 }
4812         }
4813
4814         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4815                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4816                         pipeconf |= PIPECONF_BPP_6 |
4817                                         PIPECONF_ENABLE |
4818                                         I965_PIPECONF_ACTIVE;
4819                 }
4820         }
4821
4822         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4823         drm_mode_debug_printmodeline(mode);
4824
4825         if (HAS_PIPE_CXSR(dev)) {
4826                 if (intel_crtc->lowfreq_avail) {
4827                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4828                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4829                 } else {
4830                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4831                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4832                 }
4833         }
4834
4835         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4836         if (!IS_GEN2(dev) &&
4837             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4838                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4839         else
4840                 pipeconf |= PIPECONF_PROGRESSIVE;
4841
4842         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4843
4844         /* pipesrc and dspsize control the size that is scaled from,
4845          * which should always be the user's requested size.
4846          */
4847         I915_WRITE(DSPSIZE(plane),
4848                    ((mode->vdisplay - 1) << 16) |
4849                    (mode->hdisplay - 1));
4850         I915_WRITE(DSPPOS(plane), 0);
4851
4852         I915_WRITE(PIPECONF(pipe), pipeconf);
4853         POSTING_READ(PIPECONF(pipe));
4854         intel_enable_pipe(dev_priv, pipe, false);
4855
4856         intel_wait_for_vblank(dev, pipe);
4857
4858         I915_WRITE(DSPCNTR(plane), dspcntr);
4859         POSTING_READ(DSPCNTR(plane));
4860
4861         ret = intel_pipe_set_base(crtc, x, y, fb);
4862
4863         intel_update_watermarks(dev);
4864
4865         return ret;
4866 }
4867
4868 /*
4869  * Initialize reference clocks when the driver loads
4870  */
4871 void ironlake_init_pch_refclk(struct drm_device *dev)
4872 {
4873         struct drm_i915_private *dev_priv = dev->dev_private;
4874         struct drm_mode_config *mode_config = &dev->mode_config;
4875         struct intel_encoder *encoder;
4876         u32 temp;
4877         bool has_lvds = false;
4878         bool has_cpu_edp = false;
4879         bool has_pch_edp = false;
4880         bool has_panel = false;
4881         bool has_ck505 = false;
4882         bool can_ssc = false;
4883
4884         /* We need to take the global config into account */
4885         list_for_each_entry(encoder, &mode_config->encoder_list,
4886                             base.head) {
4887                 switch (encoder->type) {
4888                 case INTEL_OUTPUT_LVDS:
4889                         has_panel = true;
4890                         has_lvds = true;
4891                         break;
4892                 case INTEL_OUTPUT_EDP:
4893                         has_panel = true;
4894                         if (intel_encoder_is_pch_edp(&encoder->base))
4895                                 has_pch_edp = true;
4896                         else
4897                                 has_cpu_edp = true;
4898                         break;
4899                 }
4900         }
4901
4902         if (HAS_PCH_IBX(dev)) {
4903                 has_ck505 = dev_priv->display_clock_mode;
4904                 can_ssc = has_ck505;
4905         } else {
4906                 has_ck505 = false;
4907                 can_ssc = true;
4908         }
4909
4910         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4911                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4912                       has_ck505);
4913
4914         /* Ironlake: try to setup display ref clock before DPLL
4915          * enabling. This is only under driver's control after
4916          * PCH B stepping, previous chipset stepping should be
4917          * ignoring this setting.
4918          */
4919         temp = I915_READ(PCH_DREF_CONTROL);
4920         /* Always enable nonspread source */
4921         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4922
4923         if (has_ck505)
4924                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4925         else
4926                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4927
4928         if (has_panel) {
4929                 temp &= ~DREF_SSC_SOURCE_MASK;
4930                 temp |= DREF_SSC_SOURCE_ENABLE;
4931
4932                 /* SSC must be turned on before enabling the CPU output  */
4933                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4934                         DRM_DEBUG_KMS("Using SSC on panel\n");
4935                         temp |= DREF_SSC1_ENABLE;
4936                 } else
4937                         temp &= ~DREF_SSC1_ENABLE;
4938
4939                 /* Get SSC going before enabling the outputs */
4940                 I915_WRITE(PCH_DREF_CONTROL, temp);
4941                 POSTING_READ(PCH_DREF_CONTROL);
4942                 udelay(200);
4943
4944                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4945
4946                 /* Enable CPU source on CPU attached eDP */
4947                 if (has_cpu_edp) {
4948                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4949                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4950                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4951                         }
4952                         else
4953                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4954                 } else
4955                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4956
4957                 I915_WRITE(PCH_DREF_CONTROL, temp);
4958                 POSTING_READ(PCH_DREF_CONTROL);
4959                 udelay(200);
4960         } else {
4961                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4962
4963                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4964
4965                 /* Turn off CPU output */
4966                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4967
4968                 I915_WRITE(PCH_DREF_CONTROL, temp);
4969                 POSTING_READ(PCH_DREF_CONTROL);
4970                 udelay(200);
4971
4972                 /* Turn off the SSC source */
4973                 temp &= ~DREF_SSC_SOURCE_MASK;
4974                 temp |= DREF_SSC_SOURCE_DISABLE;
4975
4976                 /* Turn off SSC1 */
4977                 temp &= ~ DREF_SSC1_ENABLE;
4978
4979                 I915_WRITE(PCH_DREF_CONTROL, temp);
4980                 POSTING_READ(PCH_DREF_CONTROL);
4981                 udelay(200);
4982         }
4983 }
4984
4985 static int ironlake_get_refclk(struct drm_crtc *crtc)
4986 {
4987         struct drm_device *dev = crtc->dev;
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         struct intel_encoder *encoder;
4990         struct intel_encoder *edp_encoder = NULL;
4991         int num_connectors = 0;
4992         bool is_lvds = false;
4993
4994         for_each_encoder_on_crtc(dev, crtc, encoder) {
4995                 switch (encoder->type) {
4996                 case INTEL_OUTPUT_LVDS:
4997                         is_lvds = true;
4998                         break;
4999                 case INTEL_OUTPUT_EDP:
5000                         edp_encoder = encoder;
5001                         break;
5002                 }
5003                 num_connectors++;
5004         }
5005
5006         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5007                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008                               dev_priv->lvds_ssc_freq);
5009                 return dev_priv->lvds_ssc_freq * 1000;
5010         }
5011
5012         return 120000;
5013 }
5014
5015 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5016                                   struct drm_display_mode *adjusted_mode,
5017                                   bool dither)
5018 {
5019         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021         int pipe = intel_crtc->pipe;
5022         uint32_t val;
5023
5024         val = I915_READ(PIPECONF(pipe));
5025
5026         val &= ~PIPE_BPC_MASK;
5027         switch (intel_crtc->bpp) {
5028         case 18:
5029                 val |= PIPE_6BPC;
5030                 break;
5031         case 24:
5032                 val |= PIPE_8BPC;
5033                 break;
5034         case 30:
5035                 val |= PIPE_10BPC;
5036                 break;
5037         case 36:
5038                 val |= PIPE_12BPC;
5039                 break;
5040         default:
5041                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5042                 BUG();
5043         }
5044
5045         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5046         if (dither)
5047                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5048
5049         val &= ~PIPECONF_INTERLACE_MASK;
5050         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5051                 val |= PIPECONF_INTERLACED_ILK;
5052         else
5053                 val |= PIPECONF_PROGRESSIVE;
5054
5055         I915_WRITE(PIPECONF(pipe), val);
5056         POSTING_READ(PIPECONF(pipe));
5057 }
5058
5059 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5060                                  struct drm_display_mode *adjusted_mode,
5061                                  bool dither)
5062 {
5063         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5066         uint32_t val;
5067
5068         val = I915_READ(PIPECONF(cpu_transcoder));
5069
5070         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5071         if (dither)
5072                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5073
5074         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5075         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5076                 val |= PIPECONF_INTERLACED_ILK;
5077         else
5078                 val |= PIPECONF_PROGRESSIVE;
5079
5080         I915_WRITE(PIPECONF(cpu_transcoder), val);
5081         POSTING_READ(PIPECONF(cpu_transcoder));
5082 }
5083
5084 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5085                                     struct drm_display_mode *adjusted_mode,
5086                                     intel_clock_t *clock,
5087                                     bool *has_reduced_clock,
5088                                     intel_clock_t *reduced_clock)
5089 {
5090         struct drm_device *dev = crtc->dev;
5091         struct drm_i915_private *dev_priv = dev->dev_private;
5092         struct intel_encoder *intel_encoder;
5093         int refclk;
5094         const intel_limit_t *limit;
5095         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5096
5097         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5098                 switch (intel_encoder->type) {
5099                 case INTEL_OUTPUT_LVDS:
5100                         is_lvds = true;
5101                         break;
5102                 case INTEL_OUTPUT_SDVO:
5103                 case INTEL_OUTPUT_HDMI:
5104                         is_sdvo = true;
5105                         if (intel_encoder->needs_tv_clock)
5106                                 is_tv = true;
5107                         break;
5108                 case INTEL_OUTPUT_TVOUT:
5109                         is_tv = true;
5110                         break;
5111                 }
5112         }
5113
5114         refclk = ironlake_get_refclk(crtc);
5115
5116         /*
5117          * Returns a set of divisors for the desired target clock with the given
5118          * refclk, or FALSE.  The returned values represent the clock equation:
5119          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5120          */
5121         limit = intel_limit(crtc, refclk);
5122         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5123                               clock);
5124         if (!ret)
5125                 return false;
5126
5127         if (is_lvds && dev_priv->lvds_downclock_avail) {
5128                 /*
5129                  * Ensure we match the reduced clock's P to the target clock.
5130                  * If the clocks don't match, we can't switch the display clock
5131                  * by using the FP0/FP1. In such case we will disable the LVDS
5132                  * downclock feature.
5133                 */
5134                 *has_reduced_clock = limit->find_pll(limit, crtc,
5135                                                      dev_priv->lvds_downclock,
5136                                                      refclk,
5137                                                      clock,
5138                                                      reduced_clock);
5139         }
5140
5141         if (is_sdvo && is_tv)
5142                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5143
5144         return true;
5145 }
5146
5147 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5148 {
5149         struct drm_i915_private *dev_priv = dev->dev_private;
5150         uint32_t temp;
5151
5152         temp = I915_READ(SOUTH_CHICKEN1);
5153         if (temp & FDI_BC_BIFURCATION_SELECT)
5154                 return;
5155
5156         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5157         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5158
5159         temp |= FDI_BC_BIFURCATION_SELECT;
5160         DRM_DEBUG_KMS("enabling fdi C rx\n");
5161         I915_WRITE(SOUTH_CHICKEN1, temp);
5162         POSTING_READ(SOUTH_CHICKEN1);
5163 }
5164
5165 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5166 {
5167         struct drm_device *dev = intel_crtc->base.dev;
5168         struct drm_i915_private *dev_priv = dev->dev_private;
5169         struct intel_crtc *pipe_B_crtc =
5170                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5171
5172         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5173                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5174         if (intel_crtc->fdi_lanes > 4) {
5175                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5176                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5177                 /* Clamp lanes to avoid programming the hw with bogus values. */
5178                 intel_crtc->fdi_lanes = 4;
5179
5180                 return false;
5181         }
5182
5183         if (dev_priv->num_pipe == 2)
5184                 return true;
5185
5186         switch (intel_crtc->pipe) {
5187         case PIPE_A:
5188                 return true;
5189         case PIPE_B:
5190                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5191                     intel_crtc->fdi_lanes > 2) {
5192                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5193                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5194                         /* Clamp lanes to avoid programming the hw with bogus values. */
5195                         intel_crtc->fdi_lanes = 2;
5196
5197                         return false;
5198                 }
5199
5200                 if (intel_crtc->fdi_lanes > 2)
5201                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5202                 else
5203                         cpt_enable_fdi_bc_bifurcation(dev);
5204
5205                 return true;
5206         case PIPE_C:
5207                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5208                         if (intel_crtc->fdi_lanes > 2) {
5209                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5210                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5211                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5212                                 intel_crtc->fdi_lanes = 2;
5213
5214                                 return false;
5215                         }
5216                 } else {
5217                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5218                         return false;
5219                 }
5220
5221                 cpt_enable_fdi_bc_bifurcation(dev);
5222
5223                 return true;
5224         default:
5225                 BUG();
5226         }
5227 }
5228
5229 static void ironlake_set_m_n(struct drm_crtc *crtc,
5230                              struct drm_display_mode *mode,
5231                              struct drm_display_mode *adjusted_mode)
5232 {
5233         struct drm_device *dev = crtc->dev;
5234         struct drm_i915_private *dev_priv = dev->dev_private;
5235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5237         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5238         struct fdi_m_n m_n = {0};
5239         int target_clock, pixel_multiplier, lane, link_bw;
5240         bool is_dp = false, is_cpu_edp = false;
5241
5242         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5243                 switch (intel_encoder->type) {
5244                 case INTEL_OUTPUT_DISPLAYPORT:
5245                         is_dp = true;
5246                         break;
5247                 case INTEL_OUTPUT_EDP:
5248                         is_dp = true;
5249                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5250                                 is_cpu_edp = true;
5251                         edp_encoder = intel_encoder;
5252                         break;
5253                 }
5254         }
5255
5256         /* FDI link */
5257         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5258         lane = 0;
5259         /* CPU eDP doesn't require FDI link, so just set DP M/N
5260            according to current link config */
5261         if (is_cpu_edp) {
5262                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5263         } else {
5264                 /* FDI is a binary signal running at ~2.7GHz, encoding
5265                  * each output octet as 10 bits. The actual frequency
5266                  * is stored as a divider into a 100MHz clock, and the
5267                  * mode pixel clock is stored in units of 1KHz.
5268                  * Hence the bw of each lane in terms of the mode signal
5269                  * is:
5270                  */
5271                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5272         }
5273
5274         /* [e]DP over FDI requires target mode clock instead of link clock. */
5275         if (edp_encoder)
5276                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5277         else if (is_dp)
5278                 target_clock = mode->clock;
5279         else
5280                 target_clock = adjusted_mode->clock;
5281
5282         if (!lane) {
5283                 /*
5284                  * Account for spread spectrum to avoid
5285                  * oversubscribing the link. Max center spread
5286                  * is 2.5%; use 5% for safety's sake.
5287                  */
5288                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5289                 lane = bps / (link_bw * 8) + 1;
5290         }
5291
5292         intel_crtc->fdi_lanes = lane;
5293
5294         if (pixel_multiplier > 1)
5295                 link_bw *= pixel_multiplier;
5296         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5297                              &m_n);
5298
5299         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5300         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5301         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5302         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5303 }
5304
5305 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5306                                       struct drm_display_mode *adjusted_mode,
5307                                       intel_clock_t *clock, u32 fp)
5308 {
5309         struct drm_crtc *crtc = &intel_crtc->base;
5310         struct drm_device *dev = crtc->dev;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312         struct intel_encoder *intel_encoder;
5313         uint32_t dpll;
5314         int factor, pixel_multiplier, num_connectors = 0;
5315         bool is_lvds = false, is_sdvo = false, is_tv = false;
5316         bool is_dp = false, is_cpu_edp = false;
5317
5318         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5319                 switch (intel_encoder->type) {
5320                 case INTEL_OUTPUT_LVDS:
5321                         is_lvds = true;
5322                         break;
5323                 case INTEL_OUTPUT_SDVO:
5324                 case INTEL_OUTPUT_HDMI:
5325                         is_sdvo = true;
5326                         if (intel_encoder->needs_tv_clock)
5327                                 is_tv = true;
5328                         break;
5329                 case INTEL_OUTPUT_TVOUT:
5330                         is_tv = true;
5331                         break;
5332                 case INTEL_OUTPUT_DISPLAYPORT:
5333                         is_dp = true;
5334                         break;
5335                 case INTEL_OUTPUT_EDP:
5336                         is_dp = true;
5337                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5338                                 is_cpu_edp = true;
5339                         break;
5340                 }
5341
5342                 num_connectors++;
5343         }
5344
5345         /* Enable autotuning of the PLL clock (if permissible) */
5346         factor = 21;
5347         if (is_lvds) {
5348                 if ((intel_panel_use_ssc(dev_priv) &&
5349                      dev_priv->lvds_ssc_freq == 100) ||
5350                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5351                         factor = 25;
5352         } else if (is_sdvo && is_tv)
5353                 factor = 20;
5354
5355         if (clock->m < factor * clock->n)
5356                 fp |= FP_CB_TUNE;
5357
5358         dpll = 0;
5359
5360         if (is_lvds)
5361                 dpll |= DPLLB_MODE_LVDS;
5362         else
5363                 dpll |= DPLLB_MODE_DAC_SERIAL;
5364         if (is_sdvo) {
5365                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5366                 if (pixel_multiplier > 1) {
5367                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5368                 }
5369                 dpll |= DPLL_DVO_HIGH_SPEED;
5370         }
5371         if (is_dp && !is_cpu_edp)
5372                 dpll |= DPLL_DVO_HIGH_SPEED;
5373
5374         /* compute bitmask from p1 value */
5375         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5376         /* also FPA1 */
5377         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5378
5379         switch (clock->p2) {
5380         case 5:
5381                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5382                 break;
5383         case 7:
5384                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5385                 break;
5386         case 10:
5387                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5388                 break;
5389         case 14:
5390                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5391                 break;
5392         }
5393
5394         if (is_sdvo && is_tv)
5395                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5396         else if (is_tv)
5397                 /* XXX: just matching BIOS for now */
5398                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5399                 dpll |= 3;
5400         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5401                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5402         else
5403                 dpll |= PLL_REF_INPUT_DREFCLK;
5404
5405         return dpll;
5406 }
5407
5408 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5409                                   struct drm_display_mode *mode,
5410                                   struct drm_display_mode *adjusted_mode,
5411                                   int x, int y,
5412                                   struct drm_framebuffer *fb)
5413 {
5414         struct drm_device *dev = crtc->dev;
5415         struct drm_i915_private *dev_priv = dev->dev_private;
5416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417         int pipe = intel_crtc->pipe;
5418         int plane = intel_crtc->plane;
5419         int num_connectors = 0;
5420         intel_clock_t clock, reduced_clock;
5421         u32 dpll, fp = 0, fp2 = 0;
5422         bool ok, has_reduced_clock = false;
5423         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5424         struct intel_encoder *encoder;
5425         u32 temp;
5426         int ret;
5427         bool dither, fdi_config_ok;
5428
5429         for_each_encoder_on_crtc(dev, crtc, encoder) {
5430                 switch (encoder->type) {
5431                 case INTEL_OUTPUT_LVDS:
5432                         is_lvds = true;
5433                         break;
5434                 case INTEL_OUTPUT_DISPLAYPORT:
5435                         is_dp = true;
5436                         break;
5437                 case INTEL_OUTPUT_EDP:
5438                         is_dp = true;
5439                         if (!intel_encoder_is_pch_edp(&encoder->base))
5440                                 is_cpu_edp = true;
5441                         break;
5442                 }
5443
5444                 num_connectors++;
5445         }
5446
5447         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5448              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5449
5450         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5451                                      &has_reduced_clock, &reduced_clock);
5452         if (!ok) {
5453                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454                 return -EINVAL;
5455         }
5456
5457         /* Ensure that the cursor is valid for the new mode before changing... */
5458         intel_crtc_update_cursor(crtc, true);
5459
5460         /* determine panel color depth */
5461         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5462                                               adjusted_mode);
5463         if (is_lvds && dev_priv->lvds_dither)
5464                 dither = true;
5465
5466         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5467         if (has_reduced_clock)
5468                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5469                         reduced_clock.m2;
5470
5471         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5472
5473         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5474         drm_mode_debug_printmodeline(mode);
5475
5476         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5477         if (!is_cpu_edp) {
5478                 struct intel_pch_pll *pll;
5479
5480                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5481                 if (pll == NULL) {
5482                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5483                                          pipe);
5484                         return -EINVAL;
5485                 }
5486         } else
5487                 intel_put_pch_pll(intel_crtc);
5488
5489         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5490          * This is an exception to the general rule that mode_set doesn't turn
5491          * things on.
5492          */
5493         if (is_lvds) {
5494                 temp = I915_READ(PCH_LVDS);
5495                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5496                 if (HAS_PCH_CPT(dev)) {
5497                         temp &= ~PORT_TRANS_SEL_MASK;
5498                         temp |= PORT_TRANS_SEL_CPT(pipe);
5499                 } else {
5500                         if (pipe == 1)
5501                                 temp |= LVDS_PIPEB_SELECT;
5502                         else
5503                                 temp &= ~LVDS_PIPEB_SELECT;
5504                 }
5505
5506                 /* set the corresponsding LVDS_BORDER bit */
5507                 temp |= dev_priv->lvds_border_bits;
5508                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5509                  * set the DPLLs for dual-channel mode or not.
5510                  */
5511                 if (clock.p2 == 7)
5512                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5513                 else
5514                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5515
5516                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5517                  * appropriately here, but we need to look more thoroughly into how
5518                  * panels behave in the two modes.
5519                  */
5520                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5521                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5522                         temp |= LVDS_HSYNC_POLARITY;
5523                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5524                         temp |= LVDS_VSYNC_POLARITY;
5525                 I915_WRITE(PCH_LVDS, temp);
5526         }
5527
5528         if (is_dp && !is_cpu_edp) {
5529                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5530         } else {
5531                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5532                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5533                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5534                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5535                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5536         }
5537
5538         if (intel_crtc->pch_pll) {
5539                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5540
5541                 /* Wait for the clocks to stabilize. */
5542                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5543                 udelay(150);
5544
5545                 /* The pixel multiplier can only be updated once the
5546                  * DPLL is enabled and the clocks are stable.
5547                  *
5548                  * So write it again.
5549                  */
5550                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5551         }
5552
5553         intel_crtc->lowfreq_avail = false;
5554         if (intel_crtc->pch_pll) {
5555                 if (is_lvds && has_reduced_clock && i915_powersave) {
5556                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5557                         intel_crtc->lowfreq_avail = true;
5558                 } else {
5559                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5560                 }
5561         }
5562
5563         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5564
5565         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5566          * ironlake_check_fdi_lanes. */
5567         ironlake_set_m_n(crtc, mode, adjusted_mode);
5568
5569         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5570
5571         if (is_cpu_edp)
5572                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5573
5574         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5575
5576         intel_wait_for_vblank(dev, pipe);
5577
5578         /* Set up the display plane register */
5579         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5580         POSTING_READ(DSPCNTR(plane));
5581
5582         ret = intel_pipe_set_base(crtc, x, y, fb);
5583
5584         intel_update_watermarks(dev);
5585
5586         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5587
5588         return fdi_config_ok ? ret : -EINVAL;
5589 }
5590
5591 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5592                                  struct drm_display_mode *mode,
5593                                  struct drm_display_mode *adjusted_mode,
5594                                  int x, int y,
5595                                  struct drm_framebuffer *fb)
5596 {
5597         struct drm_device *dev = crtc->dev;
5598         struct drm_i915_private *dev_priv = dev->dev_private;
5599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600         int pipe = intel_crtc->pipe;
5601         int plane = intel_crtc->plane;
5602         int num_connectors = 0;
5603         intel_clock_t clock, reduced_clock;
5604         u32 dpll = 0, fp = 0, fp2 = 0;
5605         bool ok, has_reduced_clock = false;
5606         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5607         struct intel_encoder *encoder;
5608         u32 temp;
5609         int ret;
5610         bool dither;
5611
5612         for_each_encoder_on_crtc(dev, crtc, encoder) {
5613                 switch (encoder->type) {
5614                 case INTEL_OUTPUT_LVDS:
5615                         is_lvds = true;
5616                         break;
5617                 case INTEL_OUTPUT_DISPLAYPORT:
5618                         is_dp = true;
5619                         break;
5620                 case INTEL_OUTPUT_EDP:
5621                         is_dp = true;
5622                         if (!intel_encoder_is_pch_edp(&encoder->base))
5623                                 is_cpu_edp = true;
5624                         break;
5625                 }
5626
5627                 num_connectors++;
5628         }
5629
5630         if (is_cpu_edp)
5631                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5632         else
5633                 intel_crtc->cpu_transcoder = pipe;
5634
5635         /* We are not sure yet this won't happen. */
5636         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5637              INTEL_PCH_TYPE(dev));
5638
5639         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5640              num_connectors, pipe_name(pipe));
5641
5642         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5643                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5644
5645         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5646
5647         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5648                 return -EINVAL;
5649
5650         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5651                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5652                                              &has_reduced_clock,
5653                                              &reduced_clock);
5654                 if (!ok) {
5655                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5656                         return -EINVAL;
5657                 }
5658         }
5659
5660         /* Ensure that the cursor is valid for the new mode before changing... */
5661         intel_crtc_update_cursor(crtc, true);
5662
5663         /* determine panel color depth */
5664         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5665                                               adjusted_mode);
5666         if (is_lvds && dev_priv->lvds_dither)
5667                 dither = true;
5668
5669         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5670         drm_mode_debug_printmodeline(mode);
5671
5672         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5673                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5674                 if (has_reduced_clock)
5675                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5676                               reduced_clock.m2;
5677
5678                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5679                                              fp);
5680
5681                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5682                  * own on pre-Haswell/LPT generation */
5683                 if (!is_cpu_edp) {
5684                         struct intel_pch_pll *pll;
5685
5686                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5687                         if (pll == NULL) {
5688                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5689                                                  pipe);
5690                                 return -EINVAL;
5691                         }
5692                 } else
5693                         intel_put_pch_pll(intel_crtc);
5694
5695                 /* The LVDS pin pair needs to be on before the DPLLs are
5696                  * enabled.  This is an exception to the general rule that
5697                  * mode_set doesn't turn things on.
5698                  */
5699                 if (is_lvds) {
5700                         temp = I915_READ(PCH_LVDS);
5701                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5702                         if (HAS_PCH_CPT(dev)) {
5703                                 temp &= ~PORT_TRANS_SEL_MASK;
5704                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5705                         } else {
5706                                 if (pipe == 1)
5707                                         temp |= LVDS_PIPEB_SELECT;
5708                                 else
5709                                         temp &= ~LVDS_PIPEB_SELECT;
5710                         }
5711
5712                         /* set the corresponsding LVDS_BORDER bit */
5713                         temp |= dev_priv->lvds_border_bits;
5714                         /* Set the B0-B3 data pairs corresponding to whether
5715                          * we're going to set the DPLLs for dual-channel mode or
5716                          * not.
5717                          */
5718                         if (clock.p2 == 7)
5719                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5720                         else
5721                                 temp &= ~(LVDS_B0B3_POWER_UP |
5722                                           LVDS_CLKB_POWER_UP);
5723
5724                         /* It would be nice to set 24 vs 18-bit mode
5725                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5726                          * look more thoroughly into how panels behave in the
5727                          * two modes.
5728                          */
5729                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5730                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5731                                 temp |= LVDS_HSYNC_POLARITY;
5732                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5733                                 temp |= LVDS_VSYNC_POLARITY;
5734                         I915_WRITE(PCH_LVDS, temp);
5735                 }
5736         }
5737
5738         if (is_dp && !is_cpu_edp) {
5739                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5740         } else {
5741                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5742                         /* For non-DP output, clear any trans DP clock recovery
5743                          * setting.*/
5744                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5745                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5746                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5747                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5748                 }
5749         }
5750
5751         intel_crtc->lowfreq_avail = false;
5752         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5753                 if (intel_crtc->pch_pll) {
5754                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5755
5756                         /* Wait for the clocks to stabilize. */
5757                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5758                         udelay(150);
5759
5760                         /* The pixel multiplier can only be updated once the
5761                          * DPLL is enabled and the clocks are stable.
5762                          *
5763                          * So write it again.
5764                          */
5765                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5766                 }
5767
5768                 if (intel_crtc->pch_pll) {
5769                         if (is_lvds && has_reduced_clock && i915_powersave) {
5770                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5771                                 intel_crtc->lowfreq_avail = true;
5772                         } else {
5773                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5774                         }
5775                 }
5776         }
5777
5778         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5779
5780         if (!is_dp || is_cpu_edp)
5781                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5782
5783         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5784                 if (is_cpu_edp)
5785                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5786
5787         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5788
5789         /* Set up the display plane register */
5790         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5791         POSTING_READ(DSPCNTR(plane));
5792
5793         ret = intel_pipe_set_base(crtc, x, y, fb);
5794
5795         intel_update_watermarks(dev);
5796
5797         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5798
5799         return ret;
5800 }
5801
5802 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5803                                struct drm_display_mode *mode,
5804                                struct drm_display_mode *adjusted_mode,
5805                                int x, int y,
5806                                struct drm_framebuffer *fb)
5807 {
5808         struct drm_device *dev = crtc->dev;
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         struct drm_encoder_helper_funcs *encoder_funcs;
5811         struct intel_encoder *encoder;
5812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813         int pipe = intel_crtc->pipe;
5814         int ret;
5815
5816         drm_vblank_pre_modeset(dev, pipe);
5817
5818         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5819                                               x, y, fb);
5820         drm_vblank_post_modeset(dev, pipe);
5821
5822         if (ret != 0)
5823                 return ret;
5824
5825         for_each_encoder_on_crtc(dev, crtc, encoder) {
5826                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827                         encoder->base.base.id,
5828                         drm_get_encoder_name(&encoder->base),
5829                         mode->base.id, mode->name);
5830                 encoder_funcs = encoder->base.helper_private;
5831                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5832         }
5833
5834         return 0;
5835 }
5836
5837 static bool intel_eld_uptodate(struct drm_connector *connector,
5838                                int reg_eldv, uint32_t bits_eldv,
5839                                int reg_elda, uint32_t bits_elda,
5840                                int reg_edid)
5841 {
5842         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843         uint8_t *eld = connector->eld;
5844         uint32_t i;
5845
5846         i = I915_READ(reg_eldv);
5847         i &= bits_eldv;
5848
5849         if (!eld[0])
5850                 return !i;
5851
5852         if (!i)
5853                 return false;
5854
5855         i = I915_READ(reg_elda);
5856         i &= ~bits_elda;
5857         I915_WRITE(reg_elda, i);
5858
5859         for (i = 0; i < eld[2]; i++)
5860                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5861                         return false;
5862
5863         return true;
5864 }
5865
5866 static void g4x_write_eld(struct drm_connector *connector,
5867                           struct drm_crtc *crtc)
5868 {
5869         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870         uint8_t *eld = connector->eld;
5871         uint32_t eldv;
5872         uint32_t len;
5873         uint32_t i;
5874
5875         i = I915_READ(G4X_AUD_VID_DID);
5876
5877         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5879         else
5880                 eldv = G4X_ELDV_DEVCTG;
5881
5882         if (intel_eld_uptodate(connector,
5883                                G4X_AUD_CNTL_ST, eldv,
5884                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885                                G4X_HDMIW_HDMIEDID))
5886                 return;
5887
5888         i = I915_READ(G4X_AUD_CNTL_ST);
5889         i &= ~(eldv | G4X_ELD_ADDR);
5890         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5891         I915_WRITE(G4X_AUD_CNTL_ST, i);
5892
5893         if (!eld[0])
5894                 return;
5895
5896         len = min_t(uint8_t, eld[2], len);
5897         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898         for (i = 0; i < len; i++)
5899                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5900
5901         i = I915_READ(G4X_AUD_CNTL_ST);
5902         i |= eldv;
5903         I915_WRITE(G4X_AUD_CNTL_ST, i);
5904 }
5905
5906 static void haswell_write_eld(struct drm_connector *connector,
5907                                      struct drm_crtc *crtc)
5908 {
5909         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910         uint8_t *eld = connector->eld;
5911         struct drm_device *dev = crtc->dev;
5912         uint32_t eldv;
5913         uint32_t i;
5914         int len;
5915         int pipe = to_intel_crtc(crtc)->pipe;
5916         int tmp;
5917
5918         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5919         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5920         int aud_config = HSW_AUD_CFG(pipe);
5921         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5922
5923
5924         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5925
5926         /* Audio output enable */
5927         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5928         tmp = I915_READ(aud_cntrl_st2);
5929         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5930         I915_WRITE(aud_cntrl_st2, tmp);
5931
5932         /* Wait for 1 vertical blank */
5933         intel_wait_for_vblank(dev, pipe);
5934
5935         /* Set ELD valid state */
5936         tmp = I915_READ(aud_cntrl_st2);
5937         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5938         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5939         I915_WRITE(aud_cntrl_st2, tmp);
5940         tmp = I915_READ(aud_cntrl_st2);
5941         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5942
5943         /* Enable HDMI mode */
5944         tmp = I915_READ(aud_config);
5945         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5946         /* clear N_programing_enable and N_value_index */
5947         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5948         I915_WRITE(aud_config, tmp);
5949
5950         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5951
5952         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5953
5954         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5955                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5956                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5957                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5958         } else
5959                 I915_WRITE(aud_config, 0);
5960
5961         if (intel_eld_uptodate(connector,
5962                                aud_cntrl_st2, eldv,
5963                                aud_cntl_st, IBX_ELD_ADDRESS,
5964                                hdmiw_hdmiedid))
5965                 return;
5966
5967         i = I915_READ(aud_cntrl_st2);
5968         i &= ~eldv;
5969         I915_WRITE(aud_cntrl_st2, i);
5970
5971         if (!eld[0])
5972                 return;
5973
5974         i = I915_READ(aud_cntl_st);
5975         i &= ~IBX_ELD_ADDRESS;
5976         I915_WRITE(aud_cntl_st, i);
5977         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5978         DRM_DEBUG_DRIVER("port num:%d\n", i);
5979
5980         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5981         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5982         for (i = 0; i < len; i++)
5983                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5984
5985         i = I915_READ(aud_cntrl_st2);
5986         i |= eldv;
5987         I915_WRITE(aud_cntrl_st2, i);
5988
5989 }
5990
5991 static void ironlake_write_eld(struct drm_connector *connector,
5992                                      struct drm_crtc *crtc)
5993 {
5994         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5995         uint8_t *eld = connector->eld;
5996         uint32_t eldv;
5997         uint32_t i;
5998         int len;
5999         int hdmiw_hdmiedid;
6000         int aud_config;
6001         int aud_cntl_st;
6002         int aud_cntrl_st2;
6003         int pipe = to_intel_crtc(crtc)->pipe;
6004
6005         if (HAS_PCH_IBX(connector->dev)) {
6006                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6007                 aud_config = IBX_AUD_CFG(pipe);
6008                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6009                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6010         } else {
6011                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6012                 aud_config = CPT_AUD_CFG(pipe);
6013                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6014                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6015         }
6016
6017         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6018
6019         i = I915_READ(aud_cntl_st);
6020         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6021         if (!i) {
6022                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6023                 /* operate blindly on all ports */
6024                 eldv = IBX_ELD_VALIDB;
6025                 eldv |= IBX_ELD_VALIDB << 4;
6026                 eldv |= IBX_ELD_VALIDB << 8;
6027         } else {
6028                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6029                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6030         }
6031
6032         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6033                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6034                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6035                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6036         } else
6037                 I915_WRITE(aud_config, 0);
6038
6039         if (intel_eld_uptodate(connector,
6040                                aud_cntrl_st2, eldv,
6041                                aud_cntl_st, IBX_ELD_ADDRESS,
6042                                hdmiw_hdmiedid))
6043                 return;
6044
6045         i = I915_READ(aud_cntrl_st2);
6046         i &= ~eldv;
6047         I915_WRITE(aud_cntrl_st2, i);
6048
6049         if (!eld[0])
6050                 return;
6051
6052         i = I915_READ(aud_cntl_st);
6053         i &= ~IBX_ELD_ADDRESS;
6054         I915_WRITE(aud_cntl_st, i);
6055
6056         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6057         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6058         for (i = 0; i < len; i++)
6059                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6060
6061         i = I915_READ(aud_cntrl_st2);
6062         i |= eldv;
6063         I915_WRITE(aud_cntrl_st2, i);
6064 }
6065
6066 void intel_write_eld(struct drm_encoder *encoder,
6067                      struct drm_display_mode *mode)
6068 {
6069         struct drm_crtc *crtc = encoder->crtc;
6070         struct drm_connector *connector;
6071         struct drm_device *dev = encoder->dev;
6072         struct drm_i915_private *dev_priv = dev->dev_private;
6073
6074         connector = drm_select_eld(encoder, mode);
6075         if (!connector)
6076                 return;
6077
6078         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6079                          connector->base.id,
6080                          drm_get_connector_name(connector),
6081                          connector->encoder->base.id,
6082                          drm_get_encoder_name(connector->encoder));
6083
6084         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6085
6086         if (dev_priv->display.write_eld)
6087                 dev_priv->display.write_eld(connector, crtc);
6088 }
6089
6090 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6091 void intel_crtc_load_lut(struct drm_crtc *crtc)
6092 {
6093         struct drm_device *dev = crtc->dev;
6094         struct drm_i915_private *dev_priv = dev->dev_private;
6095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096         int palreg = PALETTE(intel_crtc->pipe);
6097         int i;
6098
6099         /* The clocks have to be on to load the palette. */
6100         if (!crtc->enabled || !intel_crtc->active)
6101                 return;
6102
6103         /* use legacy palette for Ironlake */
6104         if (HAS_PCH_SPLIT(dev))
6105                 palreg = LGC_PALETTE(intel_crtc->pipe);
6106
6107         for (i = 0; i < 256; i++) {
6108                 I915_WRITE(palreg + 4 * i,
6109                            (intel_crtc->lut_r[i] << 16) |
6110                            (intel_crtc->lut_g[i] << 8) |
6111                            intel_crtc->lut_b[i]);
6112         }
6113 }
6114
6115 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6116 {
6117         struct drm_device *dev = crtc->dev;
6118         struct drm_i915_private *dev_priv = dev->dev_private;
6119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120         bool visible = base != 0;
6121         u32 cntl;
6122
6123         if (intel_crtc->cursor_visible == visible)
6124                 return;
6125
6126         cntl = I915_READ(_CURACNTR);
6127         if (visible) {
6128                 /* On these chipsets we can only modify the base whilst
6129                  * the cursor is disabled.
6130                  */
6131                 I915_WRITE(_CURABASE, base);
6132
6133                 cntl &= ~(CURSOR_FORMAT_MASK);
6134                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6135                 cntl |= CURSOR_ENABLE |
6136                         CURSOR_GAMMA_ENABLE |
6137                         CURSOR_FORMAT_ARGB;
6138         } else
6139                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6140         I915_WRITE(_CURACNTR, cntl);
6141
6142         intel_crtc->cursor_visible = visible;
6143 }
6144
6145 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6146 {
6147         struct drm_device *dev = crtc->dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150         int pipe = intel_crtc->pipe;
6151         bool visible = base != 0;
6152
6153         if (intel_crtc->cursor_visible != visible) {
6154                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6155                 if (base) {
6156                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6157                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6158                         cntl |= pipe << 28; /* Connect to correct pipe */
6159                 } else {
6160                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6161                         cntl |= CURSOR_MODE_DISABLE;
6162                 }
6163                 I915_WRITE(CURCNTR(pipe), cntl);
6164
6165                 intel_crtc->cursor_visible = visible;
6166         }
6167         /* and commit changes on next vblank */
6168         I915_WRITE(CURBASE(pipe), base);
6169 }
6170
6171 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6172 {
6173         struct drm_device *dev = crtc->dev;
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6176         int pipe = intel_crtc->pipe;
6177         bool visible = base != 0;
6178
6179         if (intel_crtc->cursor_visible != visible) {
6180                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6181                 if (base) {
6182                         cntl &= ~CURSOR_MODE;
6183                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6184                 } else {
6185                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6186                         cntl |= CURSOR_MODE_DISABLE;
6187                 }
6188                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6189
6190                 intel_crtc->cursor_visible = visible;
6191         }
6192         /* and commit changes on next vblank */
6193         I915_WRITE(CURBASE_IVB(pipe), base);
6194 }
6195
6196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6197 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6198                                      bool on)
6199 {
6200         struct drm_device *dev = crtc->dev;
6201         struct drm_i915_private *dev_priv = dev->dev_private;
6202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203         int pipe = intel_crtc->pipe;
6204         int x = intel_crtc->cursor_x;
6205         int y = intel_crtc->cursor_y;
6206         u32 base, pos;
6207         bool visible;
6208
6209         pos = 0;
6210
6211         if (on && crtc->enabled && crtc->fb) {
6212                 base = intel_crtc->cursor_addr;
6213                 if (x > (int) crtc->fb->width)
6214                         base = 0;
6215
6216                 if (y > (int) crtc->fb->height)
6217                         base = 0;
6218         } else
6219                 base = 0;
6220
6221         if (x < 0) {
6222                 if (x + intel_crtc->cursor_width < 0)
6223                         base = 0;
6224
6225                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6226                 x = -x;
6227         }
6228         pos |= x << CURSOR_X_SHIFT;
6229
6230         if (y < 0) {
6231                 if (y + intel_crtc->cursor_height < 0)
6232                         base = 0;
6233
6234                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6235                 y = -y;
6236         }
6237         pos |= y << CURSOR_Y_SHIFT;
6238
6239         visible = base != 0;
6240         if (!visible && !intel_crtc->cursor_visible)
6241                 return;
6242
6243         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6244                 I915_WRITE(CURPOS_IVB(pipe), pos);
6245                 ivb_update_cursor(crtc, base);
6246         } else {
6247                 I915_WRITE(CURPOS(pipe), pos);
6248                 if (IS_845G(dev) || IS_I865G(dev))
6249                         i845_update_cursor(crtc, base);
6250                 else
6251                         i9xx_update_cursor(crtc, base);
6252         }
6253 }
6254
6255 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6256                                  struct drm_file *file,
6257                                  uint32_t handle,
6258                                  uint32_t width, uint32_t height)
6259 {
6260         struct drm_device *dev = crtc->dev;
6261         struct drm_i915_private *dev_priv = dev->dev_private;
6262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6263         struct drm_i915_gem_object *obj;
6264         uint32_t addr;
6265         int ret;
6266
6267         /* if we want to turn off the cursor ignore width and height */
6268         if (!handle) {
6269                 DRM_DEBUG_KMS("cursor off\n");
6270                 addr = 0;
6271                 obj = NULL;
6272                 mutex_lock(&dev->struct_mutex);
6273                 goto finish;
6274         }
6275
6276         /* Currently we only support 64x64 cursors */
6277         if (width != 64 || height != 64) {
6278                 DRM_ERROR("we currently only support 64x64 cursors\n");
6279                 return -EINVAL;
6280         }
6281
6282         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6283         if (&obj->base == NULL)
6284                 return -ENOENT;
6285
6286         if (obj->base.size < width * height * 4) {
6287                 DRM_ERROR("buffer is to small\n");
6288                 ret = -ENOMEM;
6289                 goto fail;
6290         }
6291
6292         /* we only need to pin inside GTT if cursor is non-phy */
6293         mutex_lock(&dev->struct_mutex);
6294         if (!dev_priv->info->cursor_needs_physical) {
6295                 if (obj->tiling_mode) {
6296                         DRM_ERROR("cursor cannot be tiled\n");
6297                         ret = -EINVAL;
6298                         goto fail_locked;
6299                 }
6300
6301                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6302                 if (ret) {
6303                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6304                         goto fail_locked;
6305                 }
6306
6307                 ret = i915_gem_object_put_fence(obj);
6308                 if (ret) {
6309                         DRM_ERROR("failed to release fence for cursor");
6310                         goto fail_unpin;
6311                 }
6312
6313                 addr = obj->gtt_offset;
6314         } else {
6315                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6316                 ret = i915_gem_attach_phys_object(dev, obj,
6317                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6318                                                   align);
6319                 if (ret) {
6320                         DRM_ERROR("failed to attach phys object\n");
6321                         goto fail_locked;
6322                 }
6323                 addr = obj->phys_obj->handle->busaddr;
6324         }
6325
6326         if (IS_GEN2(dev))
6327                 I915_WRITE(CURSIZE, (height << 12) | width);
6328
6329  finish:
6330         if (intel_crtc->cursor_bo) {
6331                 if (dev_priv->info->cursor_needs_physical) {
6332                         if (intel_crtc->cursor_bo != obj)
6333                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6334                 } else
6335                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6336                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6337         }
6338
6339         mutex_unlock(&dev->struct_mutex);
6340
6341         intel_crtc->cursor_addr = addr;
6342         intel_crtc->cursor_bo = obj;
6343         intel_crtc->cursor_width = width;
6344         intel_crtc->cursor_height = height;
6345
6346         intel_crtc_update_cursor(crtc, true);
6347
6348         return 0;
6349 fail_unpin:
6350         i915_gem_object_unpin(obj);
6351 fail_locked:
6352         mutex_unlock(&dev->struct_mutex);
6353 fail:
6354         drm_gem_object_unreference_unlocked(&obj->base);
6355         return ret;
6356 }
6357
6358 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6359 {
6360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361
6362         intel_crtc->cursor_x = x;
6363         intel_crtc->cursor_y = y;
6364
6365         intel_crtc_update_cursor(crtc, true);
6366
6367         return 0;
6368 }
6369
6370 /** Sets the color ramps on behalf of RandR */
6371 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6372                                  u16 blue, int regno)
6373 {
6374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375
6376         intel_crtc->lut_r[regno] = red >> 8;
6377         intel_crtc->lut_g[regno] = green >> 8;
6378         intel_crtc->lut_b[regno] = blue >> 8;
6379 }
6380
6381 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6382                              u16 *blue, int regno)
6383 {
6384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385
6386         *red = intel_crtc->lut_r[regno] << 8;
6387         *green = intel_crtc->lut_g[regno] << 8;
6388         *blue = intel_crtc->lut_b[regno] << 8;
6389 }
6390
6391 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6392                                  u16 *blue, uint32_t start, uint32_t size)
6393 {
6394         int end = (start + size > 256) ? 256 : start + size, i;
6395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396
6397         for (i = start; i < end; i++) {
6398                 intel_crtc->lut_r[i] = red[i] >> 8;
6399                 intel_crtc->lut_g[i] = green[i] >> 8;
6400                 intel_crtc->lut_b[i] = blue[i] >> 8;
6401         }
6402
6403         intel_crtc_load_lut(crtc);
6404 }
6405
6406 /**
6407  * Get a pipe with a simple mode set on it for doing load-based monitor
6408  * detection.
6409  *
6410  * It will be up to the load-detect code to adjust the pipe as appropriate for
6411  * its requirements.  The pipe will be connected to no other encoders.
6412  *
6413  * Currently this code will only succeed if there is a pipe with no encoders
6414  * configured for it.  In the future, it could choose to temporarily disable
6415  * some outputs to free up a pipe for its use.
6416  *
6417  * \return crtc, or NULL if no pipes are available.
6418  */
6419
6420 /* VESA 640x480x72Hz mode to set on the pipe */
6421 static struct drm_display_mode load_detect_mode = {
6422         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6423                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6424 };
6425
6426 static struct drm_framebuffer *
6427 intel_framebuffer_create(struct drm_device *dev,
6428                          struct drm_mode_fb_cmd2 *mode_cmd,
6429                          struct drm_i915_gem_object *obj)
6430 {
6431         struct intel_framebuffer *intel_fb;
6432         int ret;
6433
6434         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6435         if (!intel_fb) {
6436                 drm_gem_object_unreference_unlocked(&obj->base);
6437                 return ERR_PTR(-ENOMEM);
6438         }
6439
6440         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6441         if (ret) {
6442                 drm_gem_object_unreference_unlocked(&obj->base);
6443                 kfree(intel_fb);
6444                 return ERR_PTR(ret);
6445         }
6446
6447         return &intel_fb->base;
6448 }
6449
6450 static u32
6451 intel_framebuffer_pitch_for_width(int width, int bpp)
6452 {
6453         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6454         return ALIGN(pitch, 64);
6455 }
6456
6457 static u32
6458 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6459 {
6460         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6461         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6462 }
6463
6464 static struct drm_framebuffer *
6465 intel_framebuffer_create_for_mode(struct drm_device *dev,
6466                                   struct drm_display_mode *mode,
6467                                   int depth, int bpp)
6468 {
6469         struct drm_i915_gem_object *obj;
6470         struct drm_mode_fb_cmd2 mode_cmd;
6471
6472         obj = i915_gem_alloc_object(dev,
6473                                     intel_framebuffer_size_for_mode(mode, bpp));
6474         if (obj == NULL)
6475                 return ERR_PTR(-ENOMEM);
6476
6477         mode_cmd.width = mode->hdisplay;
6478         mode_cmd.height = mode->vdisplay;
6479         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6480                                                                 bpp);
6481         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6482
6483         return intel_framebuffer_create(dev, &mode_cmd, obj);
6484 }
6485
6486 static struct drm_framebuffer *
6487 mode_fits_in_fbdev(struct drm_device *dev,
6488                    struct drm_display_mode *mode)
6489 {
6490         struct drm_i915_private *dev_priv = dev->dev_private;
6491         struct drm_i915_gem_object *obj;
6492         struct drm_framebuffer *fb;
6493
6494         if (dev_priv->fbdev == NULL)
6495                 return NULL;
6496
6497         obj = dev_priv->fbdev->ifb.obj;
6498         if (obj == NULL)
6499                 return NULL;
6500
6501         fb = &dev_priv->fbdev->ifb.base;
6502         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6503                                                                fb->bits_per_pixel))
6504                 return NULL;
6505
6506         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6507                 return NULL;
6508
6509         return fb;
6510 }
6511
6512 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6513                                 struct drm_display_mode *mode,
6514                                 struct intel_load_detect_pipe *old)
6515 {
6516         struct intel_crtc *intel_crtc;
6517         struct intel_encoder *intel_encoder =
6518                 intel_attached_encoder(connector);
6519         struct drm_crtc *possible_crtc;
6520         struct drm_encoder *encoder = &intel_encoder->base;
6521         struct drm_crtc *crtc = NULL;
6522         struct drm_device *dev = encoder->dev;
6523         struct drm_framebuffer *fb;
6524         int i = -1;
6525
6526         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6527                       connector->base.id, drm_get_connector_name(connector),
6528                       encoder->base.id, drm_get_encoder_name(encoder));
6529
6530         /*
6531          * Algorithm gets a little messy:
6532          *
6533          *   - if the connector already has an assigned crtc, use it (but make
6534          *     sure it's on first)
6535          *
6536          *   - try to find the first unused crtc that can drive this connector,
6537          *     and use that if we find one
6538          */
6539
6540         /* See if we already have a CRTC for this connector */
6541         if (encoder->crtc) {
6542                 crtc = encoder->crtc;
6543
6544                 old->dpms_mode = connector->dpms;
6545                 old->load_detect_temp = false;
6546
6547                 /* Make sure the crtc and connector are running */
6548                 if (connector->dpms != DRM_MODE_DPMS_ON)
6549                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6550
6551                 return true;
6552         }
6553
6554         /* Find an unused one (if possible) */
6555         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6556                 i++;
6557                 if (!(encoder->possible_crtcs & (1 << i)))
6558                         continue;
6559                 if (!possible_crtc->enabled) {
6560                         crtc = possible_crtc;
6561                         break;
6562                 }
6563         }
6564
6565         /*
6566          * If we didn't find an unused CRTC, don't use any.
6567          */
6568         if (!crtc) {
6569                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6570                 return false;
6571         }
6572
6573         intel_encoder->new_crtc = to_intel_crtc(crtc);
6574         to_intel_connector(connector)->new_encoder = intel_encoder;
6575
6576         intel_crtc = to_intel_crtc(crtc);
6577         old->dpms_mode = connector->dpms;
6578         old->load_detect_temp = true;
6579         old->release_fb = NULL;
6580
6581         if (!mode)
6582                 mode = &load_detect_mode;
6583
6584         /* We need a framebuffer large enough to accommodate all accesses
6585          * that the plane may generate whilst we perform load detection.
6586          * We can not rely on the fbcon either being present (we get called
6587          * during its initialisation to detect all boot displays, or it may
6588          * not even exist) or that it is large enough to satisfy the
6589          * requested mode.
6590          */
6591         fb = mode_fits_in_fbdev(dev, mode);
6592         if (fb == NULL) {
6593                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6594                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6595                 old->release_fb = fb;
6596         } else
6597                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6598         if (IS_ERR(fb)) {
6599                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6600                 goto fail;
6601         }
6602
6603         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6604                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6605                 if (old->release_fb)
6606                         old->release_fb->funcs->destroy(old->release_fb);
6607                 goto fail;
6608         }
6609
6610         /* let the connector get through one full cycle before testing */
6611         intel_wait_for_vblank(dev, intel_crtc->pipe);
6612
6613         return true;
6614 fail:
6615         connector->encoder = NULL;
6616         encoder->crtc = NULL;
6617         return false;
6618 }
6619
6620 void intel_release_load_detect_pipe(struct drm_connector *connector,
6621                                     struct intel_load_detect_pipe *old)
6622 {
6623         struct intel_encoder *intel_encoder =
6624                 intel_attached_encoder(connector);
6625         struct drm_encoder *encoder = &intel_encoder->base;
6626
6627         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6628                       connector->base.id, drm_get_connector_name(connector),
6629                       encoder->base.id, drm_get_encoder_name(encoder));
6630
6631         if (old->load_detect_temp) {
6632                 struct drm_crtc *crtc = encoder->crtc;
6633
6634                 to_intel_connector(connector)->new_encoder = NULL;
6635                 intel_encoder->new_crtc = NULL;
6636                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6637
6638                 if (old->release_fb)
6639                         old->release_fb->funcs->destroy(old->release_fb);
6640
6641                 return;
6642         }
6643
6644         /* Switch crtc and encoder back off if necessary */
6645         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6646                 connector->funcs->dpms(connector, old->dpms_mode);
6647 }
6648
6649 /* Returns the clock of the currently programmed mode of the given pipe. */
6650 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6651 {
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654         int pipe = intel_crtc->pipe;
6655         u32 dpll = I915_READ(DPLL(pipe));
6656         u32 fp;
6657         intel_clock_t clock;
6658
6659         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6660                 fp = I915_READ(FP0(pipe));
6661         else
6662                 fp = I915_READ(FP1(pipe));
6663
6664         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6665         if (IS_PINEVIEW(dev)) {
6666                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6667                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6668         } else {
6669                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6670                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6671         }
6672
6673         if (!IS_GEN2(dev)) {
6674                 if (IS_PINEVIEW(dev))
6675                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6676                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6677                 else
6678                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6679                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6680
6681                 switch (dpll & DPLL_MODE_MASK) {
6682                 case DPLLB_MODE_DAC_SERIAL:
6683                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6684                                 5 : 10;
6685                         break;
6686                 case DPLLB_MODE_LVDS:
6687                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6688                                 7 : 14;
6689                         break;
6690                 default:
6691                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6692                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6693                         return 0;
6694                 }
6695
6696                 /* XXX: Handle the 100Mhz refclk */
6697                 intel_clock(dev, 96000, &clock);
6698         } else {
6699                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6700
6701                 if (is_lvds) {
6702                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6703                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6704                         clock.p2 = 14;
6705
6706                         if ((dpll & PLL_REF_INPUT_MASK) ==
6707                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6708                                 /* XXX: might not be 66MHz */
6709                                 intel_clock(dev, 66000, &clock);
6710                         } else
6711                                 intel_clock(dev, 48000, &clock);
6712                 } else {
6713                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6714                                 clock.p1 = 2;
6715                         else {
6716                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6717                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6718                         }
6719                         if (dpll & PLL_P2_DIVIDE_BY_4)
6720                                 clock.p2 = 4;
6721                         else
6722                                 clock.p2 = 2;
6723
6724                         intel_clock(dev, 48000, &clock);
6725                 }
6726         }
6727
6728         /* XXX: It would be nice to validate the clocks, but we can't reuse
6729          * i830PllIsValid() because it relies on the xf86_config connector
6730          * configuration being accurate, which it isn't necessarily.
6731          */
6732
6733         return clock.dot;
6734 }
6735
6736 /** Returns the currently programmed mode of the given pipe. */
6737 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6738                                              struct drm_crtc *crtc)
6739 {
6740         struct drm_i915_private *dev_priv = dev->dev_private;
6741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6742         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6743         struct drm_display_mode *mode;
6744         int htot = I915_READ(HTOTAL(cpu_transcoder));
6745         int hsync = I915_READ(HSYNC(cpu_transcoder));
6746         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6747         int vsync = I915_READ(VSYNC(cpu_transcoder));
6748
6749         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6750         if (!mode)
6751                 return NULL;
6752
6753         mode->clock = intel_crtc_clock_get(dev, crtc);
6754         mode->hdisplay = (htot & 0xffff) + 1;
6755         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6756         mode->hsync_start = (hsync & 0xffff) + 1;
6757         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6758         mode->vdisplay = (vtot & 0xffff) + 1;
6759         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6760         mode->vsync_start = (vsync & 0xffff) + 1;
6761         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6762
6763         drm_mode_set_name(mode);
6764
6765         return mode;
6766 }
6767
6768 static void intel_increase_pllclock(struct drm_crtc *crtc)
6769 {
6770         struct drm_device *dev = crtc->dev;
6771         drm_i915_private_t *dev_priv = dev->dev_private;
6772         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6773         int pipe = intel_crtc->pipe;
6774         int dpll_reg = DPLL(pipe);
6775         int dpll;
6776
6777         if (HAS_PCH_SPLIT(dev))
6778                 return;
6779
6780         if (!dev_priv->lvds_downclock_avail)
6781                 return;
6782
6783         dpll = I915_READ(dpll_reg);
6784         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6785                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6786
6787                 assert_panel_unlocked(dev_priv, pipe);
6788
6789                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6790                 I915_WRITE(dpll_reg, dpll);
6791                 intel_wait_for_vblank(dev, pipe);
6792
6793                 dpll = I915_READ(dpll_reg);
6794                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6795                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6796         }
6797 }
6798
6799 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6800 {
6801         struct drm_device *dev = crtc->dev;
6802         drm_i915_private_t *dev_priv = dev->dev_private;
6803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6804
6805         if (HAS_PCH_SPLIT(dev))
6806                 return;
6807
6808         if (!dev_priv->lvds_downclock_avail)
6809                 return;
6810
6811         /*
6812          * Since this is called by a timer, we should never get here in
6813          * the manual case.
6814          */
6815         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6816                 int pipe = intel_crtc->pipe;
6817                 int dpll_reg = DPLL(pipe);
6818                 int dpll;
6819
6820                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6821
6822                 assert_panel_unlocked(dev_priv, pipe);
6823
6824                 dpll = I915_READ(dpll_reg);
6825                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6826                 I915_WRITE(dpll_reg, dpll);
6827                 intel_wait_for_vblank(dev, pipe);
6828                 dpll = I915_READ(dpll_reg);
6829                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6830                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6831         }
6832
6833 }
6834
6835 void intel_mark_busy(struct drm_device *dev)
6836 {
6837         i915_update_gfx_val(dev->dev_private);
6838 }
6839
6840 void intel_mark_idle(struct drm_device *dev)
6841 {
6842 }
6843
6844 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6845 {
6846         struct drm_device *dev = obj->base.dev;
6847         struct drm_crtc *crtc;
6848
6849         if (!i915_powersave)
6850                 return;
6851
6852         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6853                 if (!crtc->fb)
6854                         continue;
6855
6856                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6857                         intel_increase_pllclock(crtc);
6858         }
6859 }
6860
6861 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6862 {
6863         struct drm_device *dev = obj->base.dev;
6864         struct drm_crtc *crtc;
6865
6866         if (!i915_powersave)
6867                 return;
6868
6869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6870                 if (!crtc->fb)
6871                         continue;
6872
6873                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6874                         intel_decrease_pllclock(crtc);
6875         }
6876 }
6877
6878 static void intel_crtc_destroy(struct drm_crtc *crtc)
6879 {
6880         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6881         struct drm_device *dev = crtc->dev;
6882         struct intel_unpin_work *work;
6883         unsigned long flags;
6884
6885         spin_lock_irqsave(&dev->event_lock, flags);
6886         work = intel_crtc->unpin_work;
6887         intel_crtc->unpin_work = NULL;
6888         spin_unlock_irqrestore(&dev->event_lock, flags);
6889
6890         if (work) {
6891                 cancel_work_sync(&work->work);
6892                 kfree(work);
6893         }
6894
6895         drm_crtc_cleanup(crtc);
6896
6897         kfree(intel_crtc);
6898 }
6899
6900 static void intel_unpin_work_fn(struct work_struct *__work)
6901 {
6902         struct intel_unpin_work *work =
6903                 container_of(__work, struct intel_unpin_work, work);
6904
6905         mutex_lock(&work->dev->struct_mutex);
6906         intel_unpin_fb_obj(work->old_fb_obj);
6907         drm_gem_object_unreference(&work->pending_flip_obj->base);
6908         drm_gem_object_unreference(&work->old_fb_obj->base);
6909
6910         intel_update_fbc(work->dev);
6911         mutex_unlock(&work->dev->struct_mutex);
6912         kfree(work);
6913 }
6914
6915 static void do_intel_finish_page_flip(struct drm_device *dev,
6916                                       struct drm_crtc *crtc)
6917 {
6918         drm_i915_private_t *dev_priv = dev->dev_private;
6919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920         struct intel_unpin_work *work;
6921         struct drm_i915_gem_object *obj;
6922         struct drm_pending_vblank_event *e;
6923         struct timeval tvbl;
6924         unsigned long flags;
6925
6926         /* Ignore early vblank irqs */
6927         if (intel_crtc == NULL)
6928                 return;
6929
6930         spin_lock_irqsave(&dev->event_lock, flags);
6931         work = intel_crtc->unpin_work;
6932         if (work == NULL || !work->pending) {
6933                 spin_unlock_irqrestore(&dev->event_lock, flags);
6934                 return;
6935         }
6936
6937         intel_crtc->unpin_work = NULL;
6938
6939         if (work->event) {
6940                 e = work->event;
6941                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6942
6943                 e->event.tv_sec = tvbl.tv_sec;
6944                 e->event.tv_usec = tvbl.tv_usec;
6945
6946                 list_add_tail(&e->base.link,
6947                               &e->base.file_priv->event_list);
6948                 wake_up_interruptible(&e->base.file_priv->event_wait);
6949         }
6950
6951         drm_vblank_put(dev, intel_crtc->pipe);
6952
6953         spin_unlock_irqrestore(&dev->event_lock, flags);
6954
6955         obj = work->old_fb_obj;
6956
6957         atomic_clear_mask(1 << intel_crtc->plane,
6958                           &obj->pending_flip.counter);
6959
6960         wake_up(&dev_priv->pending_flip_queue);
6961         schedule_work(&work->work);
6962
6963         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6964 }
6965
6966 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6967 {
6968         drm_i915_private_t *dev_priv = dev->dev_private;
6969         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6970
6971         do_intel_finish_page_flip(dev, crtc);
6972 }
6973
6974 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6975 {
6976         drm_i915_private_t *dev_priv = dev->dev_private;
6977         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6978
6979         do_intel_finish_page_flip(dev, crtc);
6980 }
6981
6982 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6983 {
6984         drm_i915_private_t *dev_priv = dev->dev_private;
6985         struct intel_crtc *intel_crtc =
6986                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6987         unsigned long flags;
6988
6989         spin_lock_irqsave(&dev->event_lock, flags);
6990         if (intel_crtc->unpin_work) {
6991                 if ((++intel_crtc->unpin_work->pending) > 1)
6992                         DRM_ERROR("Prepared flip multiple times\n");
6993         } else {
6994                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6995         }
6996         spin_unlock_irqrestore(&dev->event_lock, flags);
6997 }
6998
6999 static int intel_gen2_queue_flip(struct drm_device *dev,
7000                                  struct drm_crtc *crtc,
7001                                  struct drm_framebuffer *fb,
7002                                  struct drm_i915_gem_object *obj)
7003 {
7004         struct drm_i915_private *dev_priv = dev->dev_private;
7005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006         u32 flip_mask;
7007         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7008         int ret;
7009
7010         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7011         if (ret)
7012                 goto err;
7013
7014         ret = intel_ring_begin(ring, 6);
7015         if (ret)
7016                 goto err_unpin;
7017
7018         /* Can't queue multiple flips, so wait for the previous
7019          * one to finish before executing the next.
7020          */
7021         if (intel_crtc->plane)
7022                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7023         else
7024                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7025         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7026         intel_ring_emit(ring, MI_NOOP);
7027         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7028                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029         intel_ring_emit(ring, fb->pitches[0]);
7030         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7031         intel_ring_emit(ring, 0); /* aux display base address, unused */
7032         intel_ring_advance(ring);
7033         return 0;
7034
7035 err_unpin:
7036         intel_unpin_fb_obj(obj);
7037 err:
7038         return ret;
7039 }
7040
7041 static int intel_gen3_queue_flip(struct drm_device *dev,
7042                                  struct drm_crtc *crtc,
7043                                  struct drm_framebuffer *fb,
7044                                  struct drm_i915_gem_object *obj)
7045 {
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048         u32 flip_mask;
7049         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7050         int ret;
7051
7052         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7053         if (ret)
7054                 goto err;
7055
7056         ret = intel_ring_begin(ring, 6);
7057         if (ret)
7058                 goto err_unpin;
7059
7060         if (intel_crtc->plane)
7061                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7062         else
7063                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7064         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7065         intel_ring_emit(ring, MI_NOOP);
7066         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7067                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7068         intel_ring_emit(ring, fb->pitches[0]);
7069         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7070         intel_ring_emit(ring, MI_NOOP);
7071
7072         intel_ring_advance(ring);
7073         return 0;
7074
7075 err_unpin:
7076         intel_unpin_fb_obj(obj);
7077 err:
7078         return ret;
7079 }
7080
7081 static int intel_gen4_queue_flip(struct drm_device *dev,
7082                                  struct drm_crtc *crtc,
7083                                  struct drm_framebuffer *fb,
7084                                  struct drm_i915_gem_object *obj)
7085 {
7086         struct drm_i915_private *dev_priv = dev->dev_private;
7087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088         uint32_t pf, pipesrc;
7089         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7090         int ret;
7091
7092         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7093         if (ret)
7094                 goto err;
7095
7096         ret = intel_ring_begin(ring, 4);
7097         if (ret)
7098                 goto err_unpin;
7099
7100         /* i965+ uses the linear or tiled offsets from the
7101          * Display Registers (which do not change across a page-flip)
7102          * so we need only reprogram the base address.
7103          */
7104         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7105                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106         intel_ring_emit(ring, fb->pitches[0]);
7107         intel_ring_emit(ring,
7108                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7109                         obj->tiling_mode);
7110
7111         /* XXX Enabling the panel-fitter across page-flip is so far
7112          * untested on non-native modes, so ignore it for now.
7113          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7114          */
7115         pf = 0;
7116         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7117         intel_ring_emit(ring, pf | pipesrc);
7118         intel_ring_advance(ring);
7119         return 0;
7120
7121 err_unpin:
7122         intel_unpin_fb_obj(obj);
7123 err:
7124         return ret;
7125 }
7126
7127 static int intel_gen6_queue_flip(struct drm_device *dev,
7128                                  struct drm_crtc *crtc,
7129                                  struct drm_framebuffer *fb,
7130                                  struct drm_i915_gem_object *obj)
7131 {
7132         struct drm_i915_private *dev_priv = dev->dev_private;
7133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7135         uint32_t pf, pipesrc;
7136         int ret;
7137
7138         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7139         if (ret)
7140                 goto err;
7141
7142         ret = intel_ring_begin(ring, 4);
7143         if (ret)
7144                 goto err_unpin;
7145
7146         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7147                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7148         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7149         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7150
7151         /* Contrary to the suggestions in the documentation,
7152          * "Enable Panel Fitter" does not seem to be required when page
7153          * flipping with a non-native mode, and worse causes a normal
7154          * modeset to fail.
7155          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7156          */
7157         pf = 0;
7158         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7159         intel_ring_emit(ring, pf | pipesrc);
7160         intel_ring_advance(ring);
7161         return 0;
7162
7163 err_unpin:
7164         intel_unpin_fb_obj(obj);
7165 err:
7166         return ret;
7167 }
7168
7169 /*
7170  * On gen7 we currently use the blit ring because (in early silicon at least)
7171  * the render ring doesn't give us interrpts for page flip completion, which
7172  * means clients will hang after the first flip is queued.  Fortunately the
7173  * blit ring generates interrupts properly, so use it instead.
7174  */
7175 static int intel_gen7_queue_flip(struct drm_device *dev,
7176                                  struct drm_crtc *crtc,
7177                                  struct drm_framebuffer *fb,
7178                                  struct drm_i915_gem_object *obj)
7179 {
7180         struct drm_i915_private *dev_priv = dev->dev_private;
7181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7183         uint32_t plane_bit = 0;
7184         int ret;
7185
7186         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187         if (ret)
7188                 goto err;
7189
7190         switch(intel_crtc->plane) {
7191         case PLANE_A:
7192                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7193                 break;
7194         case PLANE_B:
7195                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7196                 break;
7197         case PLANE_C:
7198                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7199                 break;
7200         default:
7201                 WARN_ONCE(1, "unknown plane in flip command\n");
7202                 ret = -ENODEV;
7203                 goto err_unpin;
7204         }
7205
7206         ret = intel_ring_begin(ring, 4);
7207         if (ret)
7208                 goto err_unpin;
7209
7210         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7211         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7212         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7213         intel_ring_emit(ring, (MI_NOOP));
7214         intel_ring_advance(ring);
7215         return 0;
7216
7217 err_unpin:
7218         intel_unpin_fb_obj(obj);
7219 err:
7220         return ret;
7221 }
7222
7223 static int intel_default_queue_flip(struct drm_device *dev,
7224                                     struct drm_crtc *crtc,
7225                                     struct drm_framebuffer *fb,
7226                                     struct drm_i915_gem_object *obj)
7227 {
7228         return -ENODEV;
7229 }
7230
7231 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7232                                 struct drm_framebuffer *fb,
7233                                 struct drm_pending_vblank_event *event)
7234 {
7235         struct drm_device *dev = crtc->dev;
7236         struct drm_i915_private *dev_priv = dev->dev_private;
7237         struct intel_framebuffer *intel_fb;
7238         struct drm_i915_gem_object *obj;
7239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7240         struct intel_unpin_work *work;
7241         unsigned long flags;
7242         int ret;
7243
7244         /* Can't change pixel format via MI display flips. */
7245         if (fb->pixel_format != crtc->fb->pixel_format)
7246                 return -EINVAL;
7247
7248         /*
7249          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7250          * Note that pitch changes could also affect these register.
7251          */
7252         if (INTEL_INFO(dev)->gen > 3 &&
7253             (fb->offsets[0] != crtc->fb->offsets[0] ||
7254              fb->pitches[0] != crtc->fb->pitches[0]))
7255                 return -EINVAL;
7256
7257         work = kzalloc(sizeof *work, GFP_KERNEL);
7258         if (work == NULL)
7259                 return -ENOMEM;
7260
7261         work->event = event;
7262         work->dev = crtc->dev;
7263         intel_fb = to_intel_framebuffer(crtc->fb);
7264         work->old_fb_obj = intel_fb->obj;
7265         INIT_WORK(&work->work, intel_unpin_work_fn);
7266
7267         ret = drm_vblank_get(dev, intel_crtc->pipe);
7268         if (ret)
7269                 goto free_work;
7270
7271         /* We borrow the event spin lock for protecting unpin_work */
7272         spin_lock_irqsave(&dev->event_lock, flags);
7273         if (intel_crtc->unpin_work) {
7274                 spin_unlock_irqrestore(&dev->event_lock, flags);
7275                 kfree(work);
7276                 drm_vblank_put(dev, intel_crtc->pipe);
7277
7278                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7279                 return -EBUSY;
7280         }
7281         intel_crtc->unpin_work = work;
7282         spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284         intel_fb = to_intel_framebuffer(fb);
7285         obj = intel_fb->obj;
7286
7287         ret = i915_mutex_lock_interruptible(dev);
7288         if (ret)
7289                 goto cleanup;
7290
7291         /* Reference the objects for the scheduled work. */
7292         drm_gem_object_reference(&work->old_fb_obj->base);
7293         drm_gem_object_reference(&obj->base);
7294
7295         crtc->fb = fb;
7296
7297         work->pending_flip_obj = obj;
7298
7299         work->enable_stall_check = true;
7300
7301         /* Block clients from rendering to the new back buffer until
7302          * the flip occurs and the object is no longer visible.
7303          */
7304         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7305
7306         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7307         if (ret)
7308                 goto cleanup_pending;
7309
7310         intel_disable_fbc(dev);
7311         intel_mark_fb_busy(obj);
7312         mutex_unlock(&dev->struct_mutex);
7313
7314         trace_i915_flip_request(intel_crtc->plane, obj);
7315
7316         return 0;
7317
7318 cleanup_pending:
7319         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7320         drm_gem_object_unreference(&work->old_fb_obj->base);
7321         drm_gem_object_unreference(&obj->base);
7322         mutex_unlock(&dev->struct_mutex);
7323
7324 cleanup:
7325         spin_lock_irqsave(&dev->event_lock, flags);
7326         intel_crtc->unpin_work = NULL;
7327         spin_unlock_irqrestore(&dev->event_lock, flags);
7328
7329         drm_vblank_put(dev, intel_crtc->pipe);
7330 free_work:
7331         kfree(work);
7332
7333         return ret;
7334 }
7335
7336 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7337         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7338         .load_lut = intel_crtc_load_lut,
7339         .disable = intel_crtc_noop,
7340 };
7341
7342 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7343 {
7344         struct intel_encoder *other_encoder;
7345         struct drm_crtc *crtc = &encoder->new_crtc->base;
7346
7347         if (WARN_ON(!crtc))
7348                 return false;
7349
7350         list_for_each_entry(other_encoder,
7351                             &crtc->dev->mode_config.encoder_list,
7352                             base.head) {
7353
7354                 if (&other_encoder->new_crtc->base != crtc ||
7355                     encoder == other_encoder)
7356                         continue;
7357                 else
7358                         return true;
7359         }
7360
7361         return false;
7362 }
7363
7364 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7365                                   struct drm_crtc *crtc)
7366 {
7367         struct drm_device *dev;
7368         struct drm_crtc *tmp;
7369         int crtc_mask = 1;
7370
7371         WARN(!crtc, "checking null crtc?\n");
7372
7373         dev = crtc->dev;
7374
7375         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7376                 if (tmp == crtc)
7377                         break;
7378                 crtc_mask <<= 1;
7379         }
7380
7381         if (encoder->possible_crtcs & crtc_mask)
7382                 return true;
7383         return false;
7384 }
7385
7386 /**
7387  * intel_modeset_update_staged_output_state
7388  *
7389  * Updates the staged output configuration state, e.g. after we've read out the
7390  * current hw state.
7391  */
7392 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7393 {
7394         struct intel_encoder *encoder;
7395         struct intel_connector *connector;
7396
7397         list_for_each_entry(connector, &dev->mode_config.connector_list,
7398                             base.head) {
7399                 connector->new_encoder =
7400                         to_intel_encoder(connector->base.encoder);
7401         }
7402
7403         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7404                             base.head) {
7405                 encoder->new_crtc =
7406                         to_intel_crtc(encoder->base.crtc);
7407         }
7408 }
7409
7410 /**
7411  * intel_modeset_commit_output_state
7412  *
7413  * This function copies the stage display pipe configuration to the real one.
7414  */
7415 static void intel_modeset_commit_output_state(struct drm_device *dev)
7416 {
7417         struct intel_encoder *encoder;
7418         struct intel_connector *connector;
7419
7420         list_for_each_entry(connector, &dev->mode_config.connector_list,
7421                             base.head) {
7422                 connector->base.encoder = &connector->new_encoder->base;
7423         }
7424
7425         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426                             base.head) {
7427                 encoder->base.crtc = &encoder->new_crtc->base;
7428         }
7429 }
7430
7431 static struct drm_display_mode *
7432 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7433                             struct drm_display_mode *mode)
7434 {
7435         struct drm_device *dev = crtc->dev;
7436         struct drm_display_mode *adjusted_mode;
7437         struct drm_encoder_helper_funcs *encoder_funcs;
7438         struct intel_encoder *encoder;
7439
7440         adjusted_mode = drm_mode_duplicate(dev, mode);
7441         if (!adjusted_mode)
7442                 return ERR_PTR(-ENOMEM);
7443
7444         /* Pass our mode to the connectors and the CRTC to give them a chance to
7445          * adjust it according to limitations or connector properties, and also
7446          * a chance to reject the mode entirely.
7447          */
7448         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449                             base.head) {
7450
7451                 if (&encoder->new_crtc->base != crtc)
7452                         continue;
7453                 encoder_funcs = encoder->base.helper_private;
7454                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7455                                                 adjusted_mode))) {
7456                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7457                         goto fail;
7458                 }
7459         }
7460
7461         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7462                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7463                 goto fail;
7464         }
7465         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7466
7467         return adjusted_mode;
7468 fail:
7469         drm_mode_destroy(dev, adjusted_mode);
7470         return ERR_PTR(-EINVAL);
7471 }
7472
7473 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7474  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7475 static void
7476 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7477                              unsigned *prepare_pipes, unsigned *disable_pipes)
7478 {
7479         struct intel_crtc *intel_crtc;
7480         struct drm_device *dev = crtc->dev;
7481         struct intel_encoder *encoder;
7482         struct intel_connector *connector;
7483         struct drm_crtc *tmp_crtc;
7484
7485         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7486
7487         /* Check which crtcs have changed outputs connected to them, these need
7488          * to be part of the prepare_pipes mask. We don't (yet) support global
7489          * modeset across multiple crtcs, so modeset_pipes will only have one
7490          * bit set at most. */
7491         list_for_each_entry(connector, &dev->mode_config.connector_list,
7492                             base.head) {
7493                 if (connector->base.encoder == &connector->new_encoder->base)
7494                         continue;
7495
7496                 if (connector->base.encoder) {
7497                         tmp_crtc = connector->base.encoder->crtc;
7498
7499                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7500                 }
7501
7502                 if (connector->new_encoder)
7503                         *prepare_pipes |=
7504                                 1 << connector->new_encoder->new_crtc->pipe;
7505         }
7506
7507         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7508                             base.head) {
7509                 if (encoder->base.crtc == &encoder->new_crtc->base)
7510                         continue;
7511
7512                 if (encoder->base.crtc) {
7513                         tmp_crtc = encoder->base.crtc;
7514
7515                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7516                 }
7517
7518                 if (encoder->new_crtc)
7519                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7520         }
7521
7522         /* Check for any pipes that will be fully disabled ... */
7523         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7524                             base.head) {
7525                 bool used = false;
7526
7527                 /* Don't try to disable disabled crtcs. */
7528                 if (!intel_crtc->base.enabled)
7529                         continue;
7530
7531                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7532                                     base.head) {
7533                         if (encoder->new_crtc == intel_crtc)
7534                                 used = true;
7535                 }
7536
7537                 if (!used)
7538                         *disable_pipes |= 1 << intel_crtc->pipe;
7539         }
7540
7541
7542         /* set_mode is also used to update properties on life display pipes. */
7543         intel_crtc = to_intel_crtc(crtc);
7544         if (crtc->enabled)
7545                 *prepare_pipes |= 1 << intel_crtc->pipe;
7546
7547         /* We only support modeset on one single crtc, hence we need to do that
7548          * only for the passed in crtc iff we change anything else than just
7549          * disable crtcs.
7550          *
7551          * This is actually not true, to be fully compatible with the old crtc
7552          * helper we automatically disable _any_ output (i.e. doesn't need to be
7553          * connected to the crtc we're modesetting on) if it's disconnected.
7554          * Which is a rather nutty api (since changed the output configuration
7555          * without userspace's explicit request can lead to confusion), but
7556          * alas. Hence we currently need to modeset on all pipes we prepare. */
7557         if (*prepare_pipes)
7558                 *modeset_pipes = *prepare_pipes;
7559
7560         /* ... and mask these out. */
7561         *modeset_pipes &= ~(*disable_pipes);
7562         *prepare_pipes &= ~(*disable_pipes);
7563 }
7564
7565 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7566 {
7567         struct drm_encoder *encoder;
7568         struct drm_device *dev = crtc->dev;
7569
7570         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7571                 if (encoder->crtc == crtc)
7572                         return true;
7573
7574         return false;
7575 }
7576
7577 static void
7578 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7579 {
7580         struct intel_encoder *intel_encoder;
7581         struct intel_crtc *intel_crtc;
7582         struct drm_connector *connector;
7583
7584         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7585                             base.head) {
7586                 if (!intel_encoder->base.crtc)
7587                         continue;
7588
7589                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7590
7591                 if (prepare_pipes & (1 << intel_crtc->pipe))
7592                         intel_encoder->connectors_active = false;
7593         }
7594
7595         intel_modeset_commit_output_state(dev);
7596
7597         /* Update computed state. */
7598         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7599                             base.head) {
7600                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7601         }
7602
7603         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7604                 if (!connector->encoder || !connector->encoder->crtc)
7605                         continue;
7606
7607                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7608
7609                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7610                         struct drm_property *dpms_property =
7611                                 dev->mode_config.dpms_property;
7612
7613                         connector->dpms = DRM_MODE_DPMS_ON;
7614                         drm_connector_property_set_value(connector,
7615                                                          dpms_property,
7616                                                          DRM_MODE_DPMS_ON);
7617
7618                         intel_encoder = to_intel_encoder(connector->encoder);
7619                         intel_encoder->connectors_active = true;
7620                 }
7621         }
7622
7623 }
7624
7625 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7626         list_for_each_entry((intel_crtc), \
7627                             &(dev)->mode_config.crtc_list, \
7628                             base.head) \
7629                 if (mask & (1 <<(intel_crtc)->pipe)) \
7630
7631 void
7632 intel_modeset_check_state(struct drm_device *dev)
7633 {
7634         struct intel_crtc *crtc;
7635         struct intel_encoder *encoder;
7636         struct intel_connector *connector;
7637
7638         list_for_each_entry(connector, &dev->mode_config.connector_list,
7639                             base.head) {
7640                 /* This also checks the encoder/connector hw state with the
7641                  * ->get_hw_state callbacks. */
7642                 intel_connector_check_state(connector);
7643
7644                 WARN(&connector->new_encoder->base != connector->base.encoder,
7645                      "connector's staged encoder doesn't match current encoder\n");
7646         }
7647
7648         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649                             base.head) {
7650                 bool enabled = false;
7651                 bool active = false;
7652                 enum pipe pipe, tracked_pipe;
7653
7654                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7655                               encoder->base.base.id,
7656                               drm_get_encoder_name(&encoder->base));
7657
7658                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7659                      "encoder's stage crtc doesn't match current crtc\n");
7660                 WARN(encoder->connectors_active && !encoder->base.crtc,
7661                      "encoder's active_connectors set, but no crtc\n");
7662
7663                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7664                                     base.head) {
7665                         if (connector->base.encoder != &encoder->base)
7666                                 continue;
7667                         enabled = true;
7668                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7669                                 active = true;
7670                 }
7671                 WARN(!!encoder->base.crtc != enabled,
7672                      "encoder's enabled state mismatch "
7673                      "(expected %i, found %i)\n",
7674                      !!encoder->base.crtc, enabled);
7675                 WARN(active && !encoder->base.crtc,
7676                      "active encoder with no crtc\n");
7677
7678                 WARN(encoder->connectors_active != active,
7679                      "encoder's computed active state doesn't match tracked active state "
7680                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7681
7682                 active = encoder->get_hw_state(encoder, &pipe);
7683                 WARN(active != encoder->connectors_active,
7684                      "encoder's hw state doesn't match sw tracking "
7685                      "(expected %i, found %i)\n",
7686                      encoder->connectors_active, active);
7687
7688                 if (!encoder->base.crtc)
7689                         continue;
7690
7691                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7692                 WARN(active && pipe != tracked_pipe,
7693                      "active encoder's pipe doesn't match"
7694                      "(expected %i, found %i)\n",
7695                      tracked_pipe, pipe);
7696
7697         }
7698
7699         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7700                             base.head) {
7701                 bool enabled = false;
7702                 bool active = false;
7703
7704                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7705                               crtc->base.base.id);
7706
7707                 WARN(crtc->active && !crtc->base.enabled,
7708                      "active crtc, but not enabled in sw tracking\n");
7709
7710                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7711                                     base.head) {
7712                         if (encoder->base.crtc != &crtc->base)
7713                                 continue;
7714                         enabled = true;
7715                         if (encoder->connectors_active)
7716                                 active = true;
7717                 }
7718                 WARN(active != crtc->active,
7719                      "crtc's computed active state doesn't match tracked active state "
7720                      "(expected %i, found %i)\n", active, crtc->active);
7721                 WARN(enabled != crtc->base.enabled,
7722                      "crtc's computed enabled state doesn't match tracked enabled state "
7723                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7724
7725                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7726         }
7727 }
7728
7729 bool intel_set_mode(struct drm_crtc *crtc,
7730                     struct drm_display_mode *mode,
7731                     int x, int y, struct drm_framebuffer *fb)
7732 {
7733         struct drm_device *dev = crtc->dev;
7734         drm_i915_private_t *dev_priv = dev->dev_private;
7735         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7736         struct intel_crtc *intel_crtc;
7737         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7738         bool ret = true;
7739
7740         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7741                                      &prepare_pipes, &disable_pipes);
7742
7743         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7744                       modeset_pipes, prepare_pipes, disable_pipes);
7745
7746         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7747                 intel_crtc_disable(&intel_crtc->base);
7748
7749         saved_hwmode = crtc->hwmode;
7750         saved_mode = crtc->mode;
7751
7752         /* Hack: Because we don't (yet) support global modeset on multiple
7753          * crtcs, we don't keep track of the new mode for more than one crtc.
7754          * Hence simply check whether any bit is set in modeset_pipes in all the
7755          * pieces of code that are not yet converted to deal with mutliple crtcs
7756          * changing their mode at the same time. */
7757         adjusted_mode = NULL;
7758         if (modeset_pipes) {
7759                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7760                 if (IS_ERR(adjusted_mode)) {
7761                         return false;
7762                 }
7763         }
7764
7765         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7766                 if (intel_crtc->base.enabled)
7767                         dev_priv->display.crtc_disable(&intel_crtc->base);
7768         }
7769
7770         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7771          * to set it here already despite that we pass it down the callchain.
7772          */
7773         if (modeset_pipes)
7774                 crtc->mode = *mode;
7775
7776         /* Only after disabling all output pipelines that will be changed can we
7777          * update the the output configuration. */
7778         intel_modeset_update_state(dev, prepare_pipes);
7779
7780         if (dev_priv->display.modeset_global_resources)
7781                 dev_priv->display.modeset_global_resources(dev);
7782
7783         /* Set up the DPLL and any encoders state that needs to adjust or depend
7784          * on the DPLL.
7785          */
7786         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7787                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7788                                            mode, adjusted_mode,
7789                                            x, y, fb);
7790                 if (!ret)
7791                     goto done;
7792         }
7793
7794         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7795         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7796                 dev_priv->display.crtc_enable(&intel_crtc->base);
7797
7798         if (modeset_pipes) {
7799                 /* Store real post-adjustment hardware mode. */
7800                 crtc->hwmode = *adjusted_mode;
7801
7802                 /* Calculate and store various constants which
7803                  * are later needed by vblank and swap-completion
7804                  * timestamping. They are derived from true hwmode.
7805                  */
7806                 drm_calc_timestamping_constants(crtc);
7807         }
7808
7809         /* FIXME: add subpixel order */
7810 done:
7811         drm_mode_destroy(dev, adjusted_mode);
7812         if (!ret && crtc->enabled) {
7813                 crtc->hwmode = saved_hwmode;
7814                 crtc->mode = saved_mode;
7815         } else {
7816                 intel_modeset_check_state(dev);
7817         }
7818
7819         return ret;
7820 }
7821
7822 #undef for_each_intel_crtc_masked
7823
7824 static void intel_set_config_free(struct intel_set_config *config)
7825 {
7826         if (!config)
7827                 return;
7828
7829         kfree(config->save_connector_encoders);
7830         kfree(config->save_encoder_crtcs);
7831         kfree(config);
7832 }
7833
7834 static int intel_set_config_save_state(struct drm_device *dev,
7835                                        struct intel_set_config *config)
7836 {
7837         struct drm_encoder *encoder;
7838         struct drm_connector *connector;
7839         int count;
7840
7841         config->save_encoder_crtcs =
7842                 kcalloc(dev->mode_config.num_encoder,
7843                         sizeof(struct drm_crtc *), GFP_KERNEL);
7844         if (!config->save_encoder_crtcs)
7845                 return -ENOMEM;
7846
7847         config->save_connector_encoders =
7848                 kcalloc(dev->mode_config.num_connector,
7849                         sizeof(struct drm_encoder *), GFP_KERNEL);
7850         if (!config->save_connector_encoders)
7851                 return -ENOMEM;
7852
7853         /* Copy data. Note that driver private data is not affected.
7854          * Should anything bad happen only the expected state is
7855          * restored, not the drivers personal bookkeeping.
7856          */
7857         count = 0;
7858         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7859                 config->save_encoder_crtcs[count++] = encoder->crtc;
7860         }
7861
7862         count = 0;
7863         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7864                 config->save_connector_encoders[count++] = connector->encoder;
7865         }
7866
7867         return 0;
7868 }
7869
7870 static void intel_set_config_restore_state(struct drm_device *dev,
7871                                            struct intel_set_config *config)
7872 {
7873         struct intel_encoder *encoder;
7874         struct intel_connector *connector;
7875         int count;
7876
7877         count = 0;
7878         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7879                 encoder->new_crtc =
7880                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7881         }
7882
7883         count = 0;
7884         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7885                 connector->new_encoder =
7886                         to_intel_encoder(config->save_connector_encoders[count++]);
7887         }
7888 }
7889
7890 static void
7891 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7892                                       struct intel_set_config *config)
7893 {
7894
7895         /* We should be able to check here if the fb has the same properties
7896          * and then just flip_or_move it */
7897         if (set->crtc->fb != set->fb) {
7898                 /* If we have no fb then treat it as a full mode set */
7899                 if (set->crtc->fb == NULL) {
7900                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7901                         config->mode_changed = true;
7902                 } else if (set->fb == NULL) {
7903                         config->mode_changed = true;
7904                 } else if (set->fb->depth != set->crtc->fb->depth) {
7905                         config->mode_changed = true;
7906                 } else if (set->fb->bits_per_pixel !=
7907                            set->crtc->fb->bits_per_pixel) {
7908                         config->mode_changed = true;
7909                 } else
7910                         config->fb_changed = true;
7911         }
7912
7913         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7914                 config->fb_changed = true;
7915
7916         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7917                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7918                 drm_mode_debug_printmodeline(&set->crtc->mode);
7919                 drm_mode_debug_printmodeline(set->mode);
7920                 config->mode_changed = true;
7921         }
7922 }
7923
7924 static int
7925 intel_modeset_stage_output_state(struct drm_device *dev,
7926                                  struct drm_mode_set *set,
7927                                  struct intel_set_config *config)
7928 {
7929         struct drm_crtc *new_crtc;
7930         struct intel_connector *connector;
7931         struct intel_encoder *encoder;
7932         int count, ro;
7933
7934         /* The upper layers ensure that we either disabl a crtc or have a list
7935          * of connectors. For paranoia, double-check this. */
7936         WARN_ON(!set->fb && (set->num_connectors != 0));
7937         WARN_ON(set->fb && (set->num_connectors == 0));
7938
7939         count = 0;
7940         list_for_each_entry(connector, &dev->mode_config.connector_list,
7941                             base.head) {
7942                 /* Otherwise traverse passed in connector list and get encoders
7943                  * for them. */
7944                 for (ro = 0; ro < set->num_connectors; ro++) {
7945                         if (set->connectors[ro] == &connector->base) {
7946                                 connector->new_encoder = connector->encoder;
7947                                 break;
7948                         }
7949                 }
7950
7951                 /* If we disable the crtc, disable all its connectors. Also, if
7952                  * the connector is on the changing crtc but not on the new
7953                  * connector list, disable it. */
7954                 if ((!set->fb || ro == set->num_connectors) &&
7955                     connector->base.encoder &&
7956                     connector->base.encoder->crtc == set->crtc) {
7957                         connector->new_encoder = NULL;
7958
7959                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7960                                 connector->base.base.id,
7961                                 drm_get_connector_name(&connector->base));
7962                 }
7963
7964
7965                 if (&connector->new_encoder->base != connector->base.encoder) {
7966                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7967                         config->mode_changed = true;
7968                 }
7969
7970                 /* Disable all disconnected encoders. */
7971                 if (connector->base.status == connector_status_disconnected)
7972                         connector->new_encoder = NULL;
7973         }
7974         /* connector->new_encoder is now updated for all connectors. */
7975
7976         /* Update crtc of enabled connectors. */
7977         count = 0;
7978         list_for_each_entry(connector, &dev->mode_config.connector_list,
7979                             base.head) {
7980                 if (!connector->new_encoder)
7981                         continue;
7982
7983                 new_crtc = connector->new_encoder->base.crtc;
7984
7985                 for (ro = 0; ro < set->num_connectors; ro++) {
7986                         if (set->connectors[ro] == &connector->base)
7987                                 new_crtc = set->crtc;
7988                 }
7989
7990                 /* Make sure the new CRTC will work with the encoder */
7991                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7992                                            new_crtc)) {
7993                         return -EINVAL;
7994                 }
7995                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7996
7997                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7998                         connector->base.base.id,
7999                         drm_get_connector_name(&connector->base),
8000                         new_crtc->base.id);
8001         }
8002
8003         /* Check for any encoders that needs to be disabled. */
8004         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8005                             base.head) {
8006                 list_for_each_entry(connector,
8007                                     &dev->mode_config.connector_list,
8008                                     base.head) {
8009                         if (connector->new_encoder == encoder) {
8010                                 WARN_ON(!connector->new_encoder->new_crtc);
8011
8012                                 goto next_encoder;
8013                         }
8014                 }
8015                 encoder->new_crtc = NULL;
8016 next_encoder:
8017                 /* Only now check for crtc changes so we don't miss encoders
8018                  * that will be disabled. */
8019                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8020                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8021                         config->mode_changed = true;
8022                 }
8023         }
8024         /* Now we've also updated encoder->new_crtc for all encoders. */
8025
8026         return 0;
8027 }
8028
8029 static int intel_crtc_set_config(struct drm_mode_set *set)
8030 {
8031         struct drm_device *dev;
8032         struct drm_mode_set save_set;
8033         struct intel_set_config *config;
8034         int ret;
8035
8036         BUG_ON(!set);
8037         BUG_ON(!set->crtc);
8038         BUG_ON(!set->crtc->helper_private);
8039
8040         if (!set->mode)
8041                 set->fb = NULL;
8042
8043         /* The fb helper likes to play gross jokes with ->mode_set_config.
8044          * Unfortunately the crtc helper doesn't do much at all for this case,
8045          * so we have to cope with this madness until the fb helper is fixed up. */
8046         if (set->fb && set->num_connectors == 0)
8047                 return 0;
8048
8049         if (set->fb) {
8050                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8051                                 set->crtc->base.id, set->fb->base.id,
8052                                 (int)set->num_connectors, set->x, set->y);
8053         } else {
8054                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8055         }
8056
8057         dev = set->crtc->dev;
8058
8059         ret = -ENOMEM;
8060         config = kzalloc(sizeof(*config), GFP_KERNEL);
8061         if (!config)
8062                 goto out_config;
8063
8064         ret = intel_set_config_save_state(dev, config);
8065         if (ret)
8066                 goto out_config;
8067
8068         save_set.crtc = set->crtc;
8069         save_set.mode = &set->crtc->mode;
8070         save_set.x = set->crtc->x;
8071         save_set.y = set->crtc->y;
8072         save_set.fb = set->crtc->fb;
8073
8074         /* Compute whether we need a full modeset, only an fb base update or no
8075          * change at all. In the future we might also check whether only the
8076          * mode changed, e.g. for LVDS where we only change the panel fitter in
8077          * such cases. */
8078         intel_set_config_compute_mode_changes(set, config);
8079
8080         ret = intel_modeset_stage_output_state(dev, set, config);
8081         if (ret)
8082                 goto fail;
8083
8084         if (config->mode_changed) {
8085                 if (set->mode) {
8086                         DRM_DEBUG_KMS("attempting to set mode from"
8087                                         " userspace\n");
8088                         drm_mode_debug_printmodeline(set->mode);
8089                 }
8090
8091                 if (!intel_set_mode(set->crtc, set->mode,
8092                                     set->x, set->y, set->fb)) {
8093                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8094                                   set->crtc->base.id);
8095                         ret = -EINVAL;
8096                         goto fail;
8097                 }
8098         } else if (config->fb_changed) {
8099                 ret = intel_pipe_set_base(set->crtc,
8100                                           set->x, set->y, set->fb);
8101         }
8102
8103         intel_set_config_free(config);
8104
8105         return 0;
8106
8107 fail:
8108         intel_set_config_restore_state(dev, config);
8109
8110         /* Try to restore the config */
8111         if (config->mode_changed &&
8112             !intel_set_mode(save_set.crtc, save_set.mode,
8113                             save_set.x, save_set.y, save_set.fb))
8114                 DRM_ERROR("failed to restore config after modeset failure\n");
8115
8116 out_config:
8117         intel_set_config_free(config);
8118         return ret;
8119 }
8120
8121 static const struct drm_crtc_funcs intel_crtc_funcs = {
8122         .cursor_set = intel_crtc_cursor_set,
8123         .cursor_move = intel_crtc_cursor_move,
8124         .gamma_set = intel_crtc_gamma_set,
8125         .set_config = intel_crtc_set_config,
8126         .destroy = intel_crtc_destroy,
8127         .page_flip = intel_crtc_page_flip,
8128 };
8129
8130 static void intel_cpu_pll_init(struct drm_device *dev)
8131 {
8132         if (IS_HASWELL(dev))
8133                 intel_ddi_pll_init(dev);
8134 }
8135
8136 static void intel_pch_pll_init(struct drm_device *dev)
8137 {
8138         drm_i915_private_t *dev_priv = dev->dev_private;
8139         int i;
8140
8141         if (dev_priv->num_pch_pll == 0) {
8142                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8143                 return;
8144         }
8145
8146         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8147                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8148                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8149                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8150         }
8151 }
8152
8153 static void intel_crtc_init(struct drm_device *dev, int pipe)
8154 {
8155         drm_i915_private_t *dev_priv = dev->dev_private;
8156         struct intel_crtc *intel_crtc;
8157         int i;
8158
8159         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8160         if (intel_crtc == NULL)
8161                 return;
8162
8163         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8164
8165         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8166         for (i = 0; i < 256; i++) {
8167                 intel_crtc->lut_r[i] = i;
8168                 intel_crtc->lut_g[i] = i;
8169                 intel_crtc->lut_b[i] = i;
8170         }
8171
8172         /* Swap pipes & planes for FBC on pre-965 */
8173         intel_crtc->pipe = pipe;
8174         intel_crtc->plane = pipe;
8175         intel_crtc->cpu_transcoder = pipe;
8176         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8177                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8178                 intel_crtc->plane = !pipe;
8179         }
8180
8181         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8182                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8183         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8184         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8185
8186         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8187
8188         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8189 }
8190
8191 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8192                                 struct drm_file *file)
8193 {
8194         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8195         struct drm_mode_object *drmmode_obj;
8196         struct intel_crtc *crtc;
8197
8198         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8199                 return -ENODEV;
8200
8201         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8202                         DRM_MODE_OBJECT_CRTC);
8203
8204         if (!drmmode_obj) {
8205                 DRM_ERROR("no such CRTC id\n");
8206                 return -EINVAL;
8207         }
8208
8209         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8210         pipe_from_crtc_id->pipe = crtc->pipe;
8211
8212         return 0;
8213 }
8214
8215 static int intel_encoder_clones(struct intel_encoder *encoder)
8216 {
8217         struct drm_device *dev = encoder->base.dev;
8218         struct intel_encoder *source_encoder;
8219         int index_mask = 0;
8220         int entry = 0;
8221
8222         list_for_each_entry(source_encoder,
8223                             &dev->mode_config.encoder_list, base.head) {
8224
8225                 if (encoder == source_encoder)
8226                         index_mask |= (1 << entry);
8227
8228                 /* Intel hw has only one MUX where enocoders could be cloned. */
8229                 if (encoder->cloneable && source_encoder->cloneable)
8230                         index_mask |= (1 << entry);
8231
8232                 entry++;
8233         }
8234
8235         return index_mask;
8236 }
8237
8238 static bool has_edp_a(struct drm_device *dev)
8239 {
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241
8242         if (!IS_MOBILE(dev))
8243                 return false;
8244
8245         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8246                 return false;
8247
8248         if (IS_GEN5(dev) &&
8249             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8250                 return false;
8251
8252         return true;
8253 }
8254
8255 static void intel_setup_outputs(struct drm_device *dev)
8256 {
8257         struct drm_i915_private *dev_priv = dev->dev_private;
8258         struct intel_encoder *encoder;
8259         bool dpd_is_edp = false;
8260         bool has_lvds;
8261
8262         has_lvds = intel_lvds_init(dev);
8263         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8264                 /* disable the panel fitter on everything but LVDS */
8265                 I915_WRITE(PFIT_CONTROL, 0);
8266         }
8267
8268         intel_crt_init(dev);
8269
8270         if (IS_HASWELL(dev)) {
8271                 int found;
8272
8273                 /* Haswell uses DDI functions to detect digital outputs */
8274                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8275                 /* DDI A only supports eDP */
8276                 if (found)
8277                         intel_ddi_init(dev, PORT_A);
8278
8279                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8280                  * register */
8281                 found = I915_READ(SFUSE_STRAP);
8282
8283                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8284                         intel_ddi_init(dev, PORT_B);
8285                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8286                         intel_ddi_init(dev, PORT_C);
8287                 if (found & SFUSE_STRAP_DDID_DETECTED)
8288                         intel_ddi_init(dev, PORT_D);
8289         } else if (HAS_PCH_SPLIT(dev)) {
8290                 int found;
8291                 dpd_is_edp = intel_dpd_is_edp(dev);
8292
8293                 if (has_edp_a(dev))
8294                         intel_dp_init(dev, DP_A, PORT_A);
8295
8296                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8297                         /* PCH SDVOB multiplex with HDMIB */
8298                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8299                         if (!found)
8300                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8301                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8302                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8303                 }
8304
8305                 if (I915_READ(HDMIC) & PORT_DETECTED)
8306                         intel_hdmi_init(dev, HDMIC, PORT_C);
8307
8308                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8309                         intel_hdmi_init(dev, HDMID, PORT_D);
8310
8311                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8312                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8313
8314                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8315                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8316         } else if (IS_VALLEYVIEW(dev)) {
8317                 int found;
8318
8319                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8320                 if (I915_READ(DP_C) & DP_DETECTED)
8321                         intel_dp_init(dev, DP_C, PORT_C);
8322
8323                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8324                         /* SDVOB multiplex with HDMIB */
8325                         found = intel_sdvo_init(dev, SDVOB, true);
8326                         if (!found)
8327                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8328                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8329                                 intel_dp_init(dev, DP_B, PORT_B);
8330                 }
8331
8332                 if (I915_READ(SDVOC) & PORT_DETECTED)
8333                         intel_hdmi_init(dev, SDVOC, PORT_C);
8334
8335         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8336                 bool found = false;
8337
8338                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8339                         DRM_DEBUG_KMS("probing SDVOB\n");
8340                         found = intel_sdvo_init(dev, SDVOB, true);
8341                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8342                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8343                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8344                         }
8345
8346                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8347                                 DRM_DEBUG_KMS("probing DP_B\n");
8348                                 intel_dp_init(dev, DP_B, PORT_B);
8349                         }
8350                 }
8351
8352                 /* Before G4X SDVOC doesn't have its own detect register */
8353
8354                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8355                         DRM_DEBUG_KMS("probing SDVOC\n");
8356                         found = intel_sdvo_init(dev, SDVOC, false);
8357                 }
8358
8359                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8360
8361                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8362                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8363                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8364                         }
8365                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8366                                 DRM_DEBUG_KMS("probing DP_C\n");
8367                                 intel_dp_init(dev, DP_C, PORT_C);
8368                         }
8369                 }
8370
8371                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8372                     (I915_READ(DP_D) & DP_DETECTED)) {
8373                         DRM_DEBUG_KMS("probing DP_D\n");
8374                         intel_dp_init(dev, DP_D, PORT_D);
8375                 }
8376         } else if (IS_GEN2(dev))
8377                 intel_dvo_init(dev);
8378
8379         if (SUPPORTS_TV(dev))
8380                 intel_tv_init(dev);
8381
8382         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8383                 encoder->base.possible_crtcs = encoder->crtc_mask;
8384                 encoder->base.possible_clones =
8385                         intel_encoder_clones(encoder);
8386         }
8387
8388         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8389                 ironlake_init_pch_refclk(dev);
8390
8391         drm_helper_move_panel_connectors_to_head(dev);
8392 }
8393
8394 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8395 {
8396         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8397
8398         drm_framebuffer_cleanup(fb);
8399         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8400
8401         kfree(intel_fb);
8402 }
8403
8404 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8405                                                 struct drm_file *file,
8406                                                 unsigned int *handle)
8407 {
8408         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8409         struct drm_i915_gem_object *obj = intel_fb->obj;
8410
8411         return drm_gem_handle_create(file, &obj->base, handle);
8412 }
8413
8414 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8415         .destroy = intel_user_framebuffer_destroy,
8416         .create_handle = intel_user_framebuffer_create_handle,
8417 };
8418
8419 int intel_framebuffer_init(struct drm_device *dev,
8420                            struct intel_framebuffer *intel_fb,
8421                            struct drm_mode_fb_cmd2 *mode_cmd,
8422                            struct drm_i915_gem_object *obj)
8423 {
8424         int ret;
8425
8426         if (obj->tiling_mode == I915_TILING_Y)
8427                 return -EINVAL;
8428
8429         if (mode_cmd->pitches[0] & 63)
8430                 return -EINVAL;
8431
8432         /* FIXME <= Gen4 stride limits are bit unclear */
8433         if (mode_cmd->pitches[0] > 32768)
8434                 return -EINVAL;
8435
8436         if (obj->tiling_mode != I915_TILING_NONE &&
8437             mode_cmd->pitches[0] != obj->stride)
8438                 return -EINVAL;
8439
8440         /* Reject formats not supported by any plane early. */
8441         switch (mode_cmd->pixel_format) {
8442         case DRM_FORMAT_C8:
8443         case DRM_FORMAT_RGB565:
8444         case DRM_FORMAT_XRGB8888:
8445         case DRM_FORMAT_ARGB8888:
8446                 break;
8447         case DRM_FORMAT_XRGB1555:
8448         case DRM_FORMAT_ARGB1555:
8449                 if (INTEL_INFO(dev)->gen > 3)
8450                         return -EINVAL;
8451                 break;
8452         case DRM_FORMAT_XBGR8888:
8453         case DRM_FORMAT_ABGR8888:
8454         case DRM_FORMAT_XRGB2101010:
8455         case DRM_FORMAT_ARGB2101010:
8456         case DRM_FORMAT_XBGR2101010:
8457         case DRM_FORMAT_ABGR2101010:
8458                 if (INTEL_INFO(dev)->gen < 4)
8459                         return -EINVAL;
8460                 break;
8461         case DRM_FORMAT_YUYV:
8462         case DRM_FORMAT_UYVY:
8463         case DRM_FORMAT_YVYU:
8464         case DRM_FORMAT_VYUY:
8465                 if (INTEL_INFO(dev)->gen < 6)
8466                         return -EINVAL;
8467                 break;
8468         default:
8469                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8470                 return -EINVAL;
8471         }
8472
8473         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8474         if (mode_cmd->offsets[0] != 0)
8475                 return -EINVAL;
8476
8477         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8478         if (ret) {
8479                 DRM_ERROR("framebuffer init failed %d\n", ret);
8480                 return ret;
8481         }
8482
8483         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8484         intel_fb->obj = obj;
8485         return 0;
8486 }
8487
8488 static struct drm_framebuffer *
8489 intel_user_framebuffer_create(struct drm_device *dev,
8490                               struct drm_file *filp,
8491                               struct drm_mode_fb_cmd2 *mode_cmd)
8492 {
8493         struct drm_i915_gem_object *obj;
8494
8495         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8496                                                 mode_cmd->handles[0]));
8497         if (&obj->base == NULL)
8498                 return ERR_PTR(-ENOENT);
8499
8500         return intel_framebuffer_create(dev, mode_cmd, obj);
8501 }
8502
8503 static const struct drm_mode_config_funcs intel_mode_funcs = {
8504         .fb_create = intel_user_framebuffer_create,
8505         .output_poll_changed = intel_fb_output_poll_changed,
8506 };
8507
8508 /* Set up chip specific display functions */
8509 static void intel_init_display(struct drm_device *dev)
8510 {
8511         struct drm_i915_private *dev_priv = dev->dev_private;
8512
8513         /* We always want a DPMS function */
8514         if (IS_HASWELL(dev)) {
8515                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8516                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8517                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8518                 dev_priv->display.off = haswell_crtc_off;
8519                 dev_priv->display.update_plane = ironlake_update_plane;
8520         } else if (HAS_PCH_SPLIT(dev)) {
8521                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8522                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8523                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8524                 dev_priv->display.off = ironlake_crtc_off;
8525                 dev_priv->display.update_plane = ironlake_update_plane;
8526         } else {
8527                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8528                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8529                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8530                 dev_priv->display.off = i9xx_crtc_off;
8531                 dev_priv->display.update_plane = i9xx_update_plane;
8532         }
8533
8534         /* Returns the core display clock speed */
8535         if (IS_VALLEYVIEW(dev))
8536                 dev_priv->display.get_display_clock_speed =
8537                         valleyview_get_display_clock_speed;
8538         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8539                 dev_priv->display.get_display_clock_speed =
8540                         i945_get_display_clock_speed;
8541         else if (IS_I915G(dev))
8542                 dev_priv->display.get_display_clock_speed =
8543                         i915_get_display_clock_speed;
8544         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8545                 dev_priv->display.get_display_clock_speed =
8546                         i9xx_misc_get_display_clock_speed;
8547         else if (IS_I915GM(dev))
8548                 dev_priv->display.get_display_clock_speed =
8549                         i915gm_get_display_clock_speed;
8550         else if (IS_I865G(dev))
8551                 dev_priv->display.get_display_clock_speed =
8552                         i865_get_display_clock_speed;
8553         else if (IS_I85X(dev))
8554                 dev_priv->display.get_display_clock_speed =
8555                         i855_get_display_clock_speed;
8556         else /* 852, 830 */
8557                 dev_priv->display.get_display_clock_speed =
8558                         i830_get_display_clock_speed;
8559
8560         if (HAS_PCH_SPLIT(dev)) {
8561                 if (IS_GEN5(dev)) {
8562                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8563                         dev_priv->display.write_eld = ironlake_write_eld;
8564                 } else if (IS_GEN6(dev)) {
8565                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8566                         dev_priv->display.write_eld = ironlake_write_eld;
8567                 } else if (IS_IVYBRIDGE(dev)) {
8568                         /* FIXME: detect B0+ stepping and use auto training */
8569                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8570                         dev_priv->display.write_eld = ironlake_write_eld;
8571                         dev_priv->display.modeset_global_resources =
8572                                 ivb_modeset_global_resources;
8573                 } else if (IS_HASWELL(dev)) {
8574                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8575                         dev_priv->display.write_eld = haswell_write_eld;
8576                 } else
8577                         dev_priv->display.update_wm = NULL;
8578         } else if (IS_G4X(dev)) {
8579                 dev_priv->display.write_eld = g4x_write_eld;
8580         }
8581
8582         /* Default just returns -ENODEV to indicate unsupported */
8583         dev_priv->display.queue_flip = intel_default_queue_flip;
8584
8585         switch (INTEL_INFO(dev)->gen) {
8586         case 2:
8587                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8588                 break;
8589
8590         case 3:
8591                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8592                 break;
8593
8594         case 4:
8595         case 5:
8596                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8597                 break;
8598
8599         case 6:
8600                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8601                 break;
8602         case 7:
8603                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8604                 break;
8605         }
8606 }
8607
8608 /*
8609  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8610  * resume, or other times.  This quirk makes sure that's the case for
8611  * affected systems.
8612  */
8613 static void quirk_pipea_force(struct drm_device *dev)
8614 {
8615         struct drm_i915_private *dev_priv = dev->dev_private;
8616
8617         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8618         DRM_INFO("applying pipe a force quirk\n");
8619 }
8620
8621 /*
8622  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8623  */
8624 static void quirk_ssc_force_disable(struct drm_device *dev)
8625 {
8626         struct drm_i915_private *dev_priv = dev->dev_private;
8627         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8628         DRM_INFO("applying lvds SSC disable quirk\n");
8629 }
8630
8631 /*
8632  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8633  * brightness value
8634  */
8635 static void quirk_invert_brightness(struct drm_device *dev)
8636 {
8637         struct drm_i915_private *dev_priv = dev->dev_private;
8638         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8639         DRM_INFO("applying inverted panel brightness quirk\n");
8640 }
8641
8642 struct intel_quirk {
8643         int device;
8644         int subsystem_vendor;
8645         int subsystem_device;
8646         void (*hook)(struct drm_device *dev);
8647 };
8648
8649 static struct intel_quirk intel_quirks[] = {
8650         /* HP Mini needs pipe A force quirk (LP: #322104) */
8651         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8652
8653         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8654         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8655
8656         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8657         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8658
8659         /* 830/845 need to leave pipe A & dpll A up */
8660         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8661         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8662
8663         /* Lenovo U160 cannot use SSC on LVDS */
8664         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8665
8666         /* Sony Vaio Y cannot use SSC on LVDS */
8667         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8668
8669         /* Acer Aspire 5734Z must invert backlight brightness */
8670         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8671 };
8672
8673 static void intel_init_quirks(struct drm_device *dev)
8674 {
8675         struct pci_dev *d = dev->pdev;
8676         int i;
8677
8678         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8679                 struct intel_quirk *q = &intel_quirks[i];
8680
8681                 if (d->device == q->device &&
8682                     (d->subsystem_vendor == q->subsystem_vendor ||
8683                      q->subsystem_vendor == PCI_ANY_ID) &&
8684                     (d->subsystem_device == q->subsystem_device ||
8685                      q->subsystem_device == PCI_ANY_ID))
8686                         q->hook(dev);
8687         }
8688 }
8689
8690 /* Disable the VGA plane that we never use */
8691 static void i915_disable_vga(struct drm_device *dev)
8692 {
8693         struct drm_i915_private *dev_priv = dev->dev_private;
8694         u8 sr1;
8695         u32 vga_reg;
8696
8697         if (HAS_PCH_SPLIT(dev))
8698                 vga_reg = CPU_VGACNTRL;
8699         else
8700                 vga_reg = VGACNTRL;
8701
8702         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8703         outb(SR01, VGA_SR_INDEX);
8704         sr1 = inb(VGA_SR_DATA);
8705         outb(sr1 | 1<<5, VGA_SR_DATA);
8706         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8707         udelay(300);
8708
8709         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8710         POSTING_READ(vga_reg);
8711 }
8712
8713 void intel_modeset_init_hw(struct drm_device *dev)
8714 {
8715         /* We attempt to init the necessary power wells early in the initialization
8716          * time, so the subsystems that expect power to be enabled can work.
8717          */
8718         intel_init_power_wells(dev);
8719
8720         intel_prepare_ddi(dev);
8721
8722         intel_init_clock_gating(dev);
8723
8724         mutex_lock(&dev->struct_mutex);
8725         intel_enable_gt_powersave(dev);
8726         mutex_unlock(&dev->struct_mutex);
8727 }
8728
8729 void intel_modeset_init(struct drm_device *dev)
8730 {
8731         struct drm_i915_private *dev_priv = dev->dev_private;
8732         int i, ret;
8733
8734         drm_mode_config_init(dev);
8735
8736         dev->mode_config.min_width = 0;
8737         dev->mode_config.min_height = 0;
8738
8739         dev->mode_config.preferred_depth = 24;
8740         dev->mode_config.prefer_shadow = 1;
8741
8742         dev->mode_config.funcs = &intel_mode_funcs;
8743
8744         intel_init_quirks(dev);
8745
8746         intel_init_pm(dev);
8747
8748         intel_init_display(dev);
8749
8750         if (IS_GEN2(dev)) {
8751                 dev->mode_config.max_width = 2048;
8752                 dev->mode_config.max_height = 2048;
8753         } else if (IS_GEN3(dev)) {
8754                 dev->mode_config.max_width = 4096;
8755                 dev->mode_config.max_height = 4096;
8756         } else {
8757                 dev->mode_config.max_width = 8192;
8758                 dev->mode_config.max_height = 8192;
8759         }
8760         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8761
8762         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8763                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8764
8765         for (i = 0; i < dev_priv->num_pipe; i++) {
8766                 intel_crtc_init(dev, i);
8767                 ret = intel_plane_init(dev, i);
8768                 if (ret)
8769                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8770         }
8771
8772         intel_cpu_pll_init(dev);
8773         intel_pch_pll_init(dev);
8774
8775         /* Just disable it once at startup */
8776         i915_disable_vga(dev);
8777         intel_setup_outputs(dev);
8778 }
8779
8780 static void
8781 intel_connector_break_all_links(struct intel_connector *connector)
8782 {
8783         connector->base.dpms = DRM_MODE_DPMS_OFF;
8784         connector->base.encoder = NULL;
8785         connector->encoder->connectors_active = false;
8786         connector->encoder->base.crtc = NULL;
8787 }
8788
8789 static void intel_enable_pipe_a(struct drm_device *dev)
8790 {
8791         struct intel_connector *connector;
8792         struct drm_connector *crt = NULL;
8793         struct intel_load_detect_pipe load_detect_temp;
8794
8795         /* We can't just switch on the pipe A, we need to set things up with a
8796          * proper mode and output configuration. As a gross hack, enable pipe A
8797          * by enabling the load detect pipe once. */
8798         list_for_each_entry(connector,
8799                             &dev->mode_config.connector_list,
8800                             base.head) {
8801                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8802                         crt = &connector->base;
8803                         break;
8804                 }
8805         }
8806
8807         if (!crt)
8808                 return;
8809
8810         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8811                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8812
8813
8814 }
8815
8816 static bool
8817 intel_check_plane_mapping(struct intel_crtc *crtc)
8818 {
8819         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8820         u32 reg, val;
8821
8822         if (dev_priv->num_pipe == 1)
8823                 return true;
8824
8825         reg = DSPCNTR(!crtc->plane);
8826         val = I915_READ(reg);
8827
8828         if ((val & DISPLAY_PLANE_ENABLE) &&
8829             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8830                 return false;
8831
8832         return true;
8833 }
8834
8835 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8836 {
8837         struct drm_device *dev = crtc->base.dev;
8838         struct drm_i915_private *dev_priv = dev->dev_private;
8839         u32 reg;
8840
8841         /* Clear any frame start delays used for debugging left by the BIOS */
8842         reg = PIPECONF(crtc->cpu_transcoder);
8843         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8844
8845         /* We need to sanitize the plane -> pipe mapping first because this will
8846          * disable the crtc (and hence change the state) if it is wrong. Note
8847          * that gen4+ has a fixed plane -> pipe mapping.  */
8848         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8849                 struct intel_connector *connector;
8850                 bool plane;
8851
8852                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8853                               crtc->base.base.id);
8854
8855                 /* Pipe has the wrong plane attached and the plane is active.
8856                  * Temporarily change the plane mapping and disable everything
8857                  * ...  */
8858                 plane = crtc->plane;
8859                 crtc->plane = !plane;
8860                 dev_priv->display.crtc_disable(&crtc->base);
8861                 crtc->plane = plane;
8862
8863                 /* ... and break all links. */
8864                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8865                                     base.head) {
8866                         if (connector->encoder->base.crtc != &crtc->base)
8867                                 continue;
8868
8869                         intel_connector_break_all_links(connector);
8870                 }
8871
8872                 WARN_ON(crtc->active);
8873                 crtc->base.enabled = false;
8874         }
8875
8876         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8877             crtc->pipe == PIPE_A && !crtc->active) {
8878                 /* BIOS forgot to enable pipe A, this mostly happens after
8879                  * resume. Force-enable the pipe to fix this, the update_dpms
8880                  * call below we restore the pipe to the right state, but leave
8881                  * the required bits on. */
8882                 intel_enable_pipe_a(dev);
8883         }
8884
8885         /* Adjust the state of the output pipe according to whether we
8886          * have active connectors/encoders. */
8887         intel_crtc_update_dpms(&crtc->base);
8888
8889         if (crtc->active != crtc->base.enabled) {
8890                 struct intel_encoder *encoder;
8891
8892                 /* This can happen either due to bugs in the get_hw_state
8893                  * functions or because the pipe is force-enabled due to the
8894                  * pipe A quirk. */
8895                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8896                               crtc->base.base.id,
8897                               crtc->base.enabled ? "enabled" : "disabled",
8898                               crtc->active ? "enabled" : "disabled");
8899
8900                 crtc->base.enabled = crtc->active;
8901
8902                 /* Because we only establish the connector -> encoder ->
8903                  * crtc links if something is active, this means the
8904                  * crtc is now deactivated. Break the links. connector
8905                  * -> encoder links are only establish when things are
8906                  *  actually up, hence no need to break them. */
8907                 WARN_ON(crtc->active);
8908
8909                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8910                         WARN_ON(encoder->connectors_active);
8911                         encoder->base.crtc = NULL;
8912                 }
8913         }
8914 }
8915
8916 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8917 {
8918         struct intel_connector *connector;
8919         struct drm_device *dev = encoder->base.dev;
8920
8921         /* We need to check both for a crtc link (meaning that the
8922          * encoder is active and trying to read from a pipe) and the
8923          * pipe itself being active. */
8924         bool has_active_crtc = encoder->base.crtc &&
8925                 to_intel_crtc(encoder->base.crtc)->active;
8926
8927         if (encoder->connectors_active && !has_active_crtc) {
8928                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8929                               encoder->base.base.id,
8930                               drm_get_encoder_name(&encoder->base));
8931
8932                 /* Connector is active, but has no active pipe. This is
8933                  * fallout from our resume register restoring. Disable
8934                  * the encoder manually again. */
8935                 if (encoder->base.crtc) {
8936                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8937                                       encoder->base.base.id,
8938                                       drm_get_encoder_name(&encoder->base));
8939                         encoder->disable(encoder);
8940                 }
8941
8942                 /* Inconsistent output/port/pipe state happens presumably due to
8943                  * a bug in one of the get_hw_state functions. Or someplace else
8944                  * in our code, like the register restore mess on resume. Clamp
8945                  * things to off as a safer default. */
8946                 list_for_each_entry(connector,
8947                                     &dev->mode_config.connector_list,
8948                                     base.head) {
8949                         if (connector->encoder != encoder)
8950                                 continue;
8951
8952                         intel_connector_break_all_links(connector);
8953                 }
8954         }
8955         /* Enabled encoders without active connectors will be fixed in
8956          * the crtc fixup. */
8957 }
8958
8959 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8960  * and i915 state tracking structures. */
8961 void intel_modeset_setup_hw_state(struct drm_device *dev)
8962 {
8963         struct drm_i915_private *dev_priv = dev->dev_private;
8964         enum pipe pipe;
8965         u32 tmp;
8966         struct intel_crtc *crtc;
8967         struct intel_encoder *encoder;
8968         struct intel_connector *connector;
8969
8970         if (IS_HASWELL(dev)) {
8971                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8972
8973                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8974                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8975                         case TRANS_DDI_EDP_INPUT_A_ON:
8976                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8977                                 pipe = PIPE_A;
8978                                 break;
8979                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8980                                 pipe = PIPE_B;
8981                                 break;
8982                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8983                                 pipe = PIPE_C;
8984                                 break;
8985                         }
8986
8987                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8988                         crtc->cpu_transcoder = TRANSCODER_EDP;
8989
8990                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8991                                       pipe_name(pipe));
8992                 }
8993         }
8994
8995         for_each_pipe(pipe) {
8996                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8997
8998                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8999                 if (tmp & PIPECONF_ENABLE)
9000                         crtc->active = true;
9001                 else
9002                         crtc->active = false;
9003
9004                 crtc->base.enabled = crtc->active;
9005
9006                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9007                               crtc->base.base.id,
9008                               crtc->active ? "enabled" : "disabled");
9009         }
9010
9011         if (IS_HASWELL(dev))
9012                 intel_ddi_setup_hw_pll_state(dev);
9013
9014         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9015                             base.head) {
9016                 pipe = 0;
9017
9018                 if (encoder->get_hw_state(encoder, &pipe)) {
9019                         encoder->base.crtc =
9020                                 dev_priv->pipe_to_crtc_mapping[pipe];
9021                 } else {
9022                         encoder->base.crtc = NULL;
9023                 }
9024
9025                 encoder->connectors_active = false;
9026                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9027                               encoder->base.base.id,
9028                               drm_get_encoder_name(&encoder->base),
9029                               encoder->base.crtc ? "enabled" : "disabled",
9030                               pipe);
9031         }
9032
9033         list_for_each_entry(connector, &dev->mode_config.connector_list,
9034                             base.head) {
9035                 if (connector->get_hw_state(connector)) {
9036                         connector->base.dpms = DRM_MODE_DPMS_ON;
9037                         connector->encoder->connectors_active = true;
9038                         connector->base.encoder = &connector->encoder->base;
9039                 } else {
9040                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9041                         connector->base.encoder = NULL;
9042                 }
9043                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9044                               connector->base.base.id,
9045                               drm_get_connector_name(&connector->base),
9046                               connector->base.encoder ? "enabled" : "disabled");
9047         }
9048
9049         /* HW state is read out, now we need to sanitize this mess. */
9050         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9051                             base.head) {
9052                 intel_sanitize_encoder(encoder);
9053         }
9054
9055         for_each_pipe(pipe) {
9056                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9057                 intel_sanitize_crtc(crtc);
9058         }
9059
9060         intel_modeset_update_staged_output_state(dev);
9061
9062         intel_modeset_check_state(dev);
9063
9064         drm_mode_config_reset(dev);
9065 }
9066
9067 void intel_modeset_gem_init(struct drm_device *dev)
9068 {
9069         intel_modeset_init_hw(dev);
9070
9071         intel_setup_overlay(dev);
9072
9073         intel_modeset_setup_hw_state(dev);
9074 }
9075
9076 void intel_modeset_cleanup(struct drm_device *dev)
9077 {
9078         struct drm_i915_private *dev_priv = dev->dev_private;
9079         struct drm_crtc *crtc;
9080         struct intel_crtc *intel_crtc;
9081
9082         drm_kms_helper_poll_fini(dev);
9083         mutex_lock(&dev->struct_mutex);
9084
9085         intel_unregister_dsm_handler();
9086
9087
9088         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9089                 /* Skip inactive CRTCs */
9090                 if (!crtc->fb)
9091                         continue;
9092
9093                 intel_crtc = to_intel_crtc(crtc);
9094                 intel_increase_pllclock(crtc);
9095         }
9096
9097         intel_disable_fbc(dev);
9098
9099         intel_disable_gt_powersave(dev);
9100
9101         ironlake_teardown_rc6(dev);
9102
9103         if (IS_VALLEYVIEW(dev))
9104                 vlv_init_dpio(dev);
9105
9106         mutex_unlock(&dev->struct_mutex);
9107
9108         /* Disable the irq before mode object teardown, for the irq might
9109          * enqueue unpin/hotplug work. */
9110         drm_irq_uninstall(dev);
9111         cancel_work_sync(&dev_priv->hotplug_work);
9112         cancel_work_sync(&dev_priv->rps.work);
9113
9114         /* flush any delayed tasks or pending work */
9115         flush_scheduled_work();
9116
9117         drm_mode_config_cleanup(dev);
9118 }
9119
9120 /*
9121  * Return which encoder is currently attached for connector.
9122  */
9123 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9124 {
9125         return &intel_attached_encoder(connector)->base;
9126 }
9127
9128 void intel_connector_attach_encoder(struct intel_connector *connector,
9129                                     struct intel_encoder *encoder)
9130 {
9131         connector->encoder = encoder;
9132         drm_mode_connector_attach_encoder(&connector->base,
9133                                           &encoder->base);
9134 }
9135
9136 /*
9137  * set vga decode state - true == enable VGA decode
9138  */
9139 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9140 {
9141         struct drm_i915_private *dev_priv = dev->dev_private;
9142         u16 gmch_ctrl;
9143
9144         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9145         if (state)
9146                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9147         else
9148                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9149         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9150         return 0;
9151 }
9152
9153 #ifdef CONFIG_DEBUG_FS
9154 #include <linux/seq_file.h>
9155
9156 struct intel_display_error_state {
9157         struct intel_cursor_error_state {
9158                 u32 control;
9159                 u32 position;
9160                 u32 base;
9161                 u32 size;
9162         } cursor[I915_MAX_PIPES];
9163
9164         struct intel_pipe_error_state {
9165                 u32 conf;
9166                 u32 source;
9167
9168                 u32 htotal;
9169                 u32 hblank;
9170                 u32 hsync;
9171                 u32 vtotal;
9172                 u32 vblank;
9173                 u32 vsync;
9174         } pipe[I915_MAX_PIPES];
9175
9176         struct intel_plane_error_state {
9177                 u32 control;
9178                 u32 stride;
9179                 u32 size;
9180                 u32 pos;
9181                 u32 addr;
9182                 u32 surface;
9183                 u32 tile_offset;
9184         } plane[I915_MAX_PIPES];
9185 };
9186
9187 struct intel_display_error_state *
9188 intel_display_capture_error_state(struct drm_device *dev)
9189 {
9190         drm_i915_private_t *dev_priv = dev->dev_private;
9191         struct intel_display_error_state *error;
9192         enum transcoder cpu_transcoder;
9193         int i;
9194
9195         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9196         if (error == NULL)
9197                 return NULL;
9198
9199         for_each_pipe(i) {
9200                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9201
9202                 error->cursor[i].control = I915_READ(CURCNTR(i));
9203                 error->cursor[i].position = I915_READ(CURPOS(i));
9204                 error->cursor[i].base = I915_READ(CURBASE(i));
9205
9206                 error->plane[i].control = I915_READ(DSPCNTR(i));
9207                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9208                 error->plane[i].size = I915_READ(DSPSIZE(i));
9209                 error->plane[i].pos = I915_READ(DSPPOS(i));
9210                 error->plane[i].addr = I915_READ(DSPADDR(i));
9211                 if (INTEL_INFO(dev)->gen >= 4) {
9212                         error->plane[i].surface = I915_READ(DSPSURF(i));
9213                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9214                 }
9215
9216                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9217                 error->pipe[i].source = I915_READ(PIPESRC(i));
9218                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9219                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9220                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9221                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9222                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9223                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9224         }
9225
9226         return error;
9227 }
9228
9229 void
9230 intel_display_print_error_state(struct seq_file *m,
9231                                 struct drm_device *dev,
9232                                 struct intel_display_error_state *error)
9233 {
9234         drm_i915_private_t *dev_priv = dev->dev_private;
9235         int i;
9236
9237         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9238         for_each_pipe(i) {
9239                 seq_printf(m, "Pipe [%d]:\n", i);
9240                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9241                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9242                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9243                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9244                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9245                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9246                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9247                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9248
9249                 seq_printf(m, "Plane [%d]:\n", i);
9250                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9251                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9252                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9253                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9254                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9255                 if (INTEL_INFO(dev)->gen >= 4) {
9256                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9257                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9258                 }
9259
9260                 seq_printf(m, "Cursor [%d]:\n", i);
9261                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9262                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9263                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9264         }
9265 }
9266 #endif