2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
66 typedef struct intel_limit intel_limit_t;
68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
76 intel_pch_rawclk(struct drm_device *dev)
78 struct drm_i915_private *dev_priv = dev->dev_private;
80 WARN_ON(!HAS_PCH_SPLIT(dev));
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
85 static inline u32 /* units of 100MHz */
86 intel_fdi_link_freq(struct drm_device *dev)
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
95 static const intel_limit_t intel_limits_i8xx_dac = {
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
121 static const intel_limit_t intel_limits_i8xx_lvds = {
122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
134 static const intel_limit_t intel_limits_i9xx_sdvo = {
135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
147 static const intel_limit_t intel_limits_i9xx_lvds = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
161 static const intel_limit_t intel_limits_g4x_sdvo = {
162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
176 static const intel_limit_t intel_limits_g4x_hdmi = {
177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
217 static const intel_limit_t intel_limits_pineview_sdvo = {
218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
220 /* Pineview's Ncounter is a ring counter */
221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
223 /* Pineview only has one combined m divider, which we treat as m2. */
224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
232 static const intel_limit_t intel_limits_pineview_lvds = {
233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
245 /* Ironlake / Sandybridge
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
250 static const intel_limit_t intel_limits_ironlake_dac = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
289 /* LVDS 100mhz refclk limits. */
290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
298 .p1 = { .min = 2, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
311 .p1 = { .min = 2, .max = 6 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
316 static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
324 .p1 = { .min = 1, .max = 3 },
325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
329 static const intel_limit_t intel_limits_vlv_hdmi = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
342 static const intel_limit_t intel_limits_vlv_dp = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 },
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 struct drm_device *dev = crtc->dev;
359 const intel_limit_t *limit;
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
362 if (intel_is_dual_link_lvds(dev)) {
363 if (refclk == 100000)
364 limit = &intel_limits_ironlake_dual_lvds_100m;
366 limit = &intel_limits_ironlake_dual_lvds;
368 if (refclk == 100000)
369 limit = &intel_limits_ironlake_single_lvds_100m;
371 limit = &intel_limits_ironlake_single_lvds;
374 limit = &intel_limits_ironlake_dac;
379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
385 if (intel_is_dual_link_lvds(dev))
386 limit = &intel_limits_g4x_dual_channel_lvds;
388 limit = &intel_limits_g4x_single_channel_lvds;
389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
391 limit = &intel_limits_g4x_hdmi;
392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
393 limit = &intel_limits_g4x_sdvo;
394 } else /* The option is for other outputs */
395 limit = &intel_limits_i9xx_sdvo;
400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
405 if (HAS_PCH_SPLIT(dev))
406 limit = intel_ironlake_limit(crtc, refclk);
407 else if (IS_G4X(dev)) {
408 limit = intel_g4x_limit(crtc);
409 } else if (IS_PINEVIEW(dev)) {
410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
411 limit = &intel_limits_pineview_lvds;
413 limit = &intel_limits_pineview_sdvo;
414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
420 limit = &intel_limits_vlv_dp;
421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
425 limit = &intel_limits_i9xx_sdvo;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_i8xx_lvds;
429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
430 limit = &intel_limits_i8xx_dvo;
432 limit = &intel_limits_i8xx_dac;
437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
438 static void pineview_clock(int refclk, intel_clock_t *clock)
440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
451 static void i9xx_clock(int refclk, intel_clock_t *clock)
453 clock->m = i9xx_dpll_compute_m(clock);
454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
460 * Returns whether any output on the specified pipe is of the specified type
462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
464 struct drm_device *dev = crtc->dev;
465 struct intel_encoder *encoder;
467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
474 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
480 static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
485 INTELPllInvalid("p1 out of range\n");
486 if (clock->p < limit->p.min || limit->p.max < clock->p)
487 INTELPllInvalid("p out of range\n");
488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
489 INTELPllInvalid("m2 out of range\n");
490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
491 INTELPllInvalid("m1 out of range\n");
492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
493 INTELPllInvalid("m1 <= m2\n");
494 if (clock->m < limit->m.min || limit->m.max < clock->m)
495 INTELPllInvalid("m out of range\n");
496 if (clock->n < limit->n.min || limit->n.max < clock->n)
497 INTELPllInvalid("n out of range\n");
498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
499 INTELPllInvalid("vco out of range\n");
500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
504 INTELPllInvalid("dot out of range\n");
510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
514 struct drm_device *dev = crtc->dev;
518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
524 if (intel_is_dual_link_lvds(dev))
525 clock.p2 = limit->p2.p2_fast;
527 clock.p2 = limit->p2.p2_slow;
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
532 clock.p2 = limit->p2.p2_fast;
535 memset(best_clock, 0, sizeof(*best_clock));
537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
541 if (clock.m2 >= clock.m1)
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
554 clock.p != match_clock->p)
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
567 return (err != target);
571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
575 struct drm_device *dev = crtc->dev;
579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
585 if (intel_is_dual_link_lvds(dev))
586 clock.p2 = limit->p2.p2_fast;
588 clock.p2 = limit->p2.p2_slow;
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
593 clock.p2 = limit->p2.p2_fast;
596 memset(best_clock, 0, sizeof(*best_clock));
598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
608 pineview_clock(refclk, &clock);
609 if (!intel_PLL_is_valid(dev, limit,
613 clock.p != match_clock->p)
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
626 return (err != target);
630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
634 struct drm_device *dev = crtc->dev;
638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (intel_is_dual_link_lvds(dev))
644 clock.p2 = limit->p2.p2_fast;
646 clock.p2 = limit->p2.p2_slow;
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
651 clock.p2 = limit->p2.p2_fast;
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
656 /* based on hardware requirement, prefer smaller n to precision */
657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
658 /* based on hardware requirement, prefere larger m1,m2 */
659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
667 i9xx_clock(refclk, &clock);
668 if (!intel_PLL_is_valid(dev, limit,
672 this_err = abs(clock.dot - target);
673 if (this_err < err_most) {
687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
693 u32 updrate, minupdate, p;
694 unsigned long bestppm, ppm, absppm;
698 dotclk = target * 1000;
701 fastclk = dotclk / (2*100);
704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
728 if (absppm < bestppm - 10) {
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
760 return intel_crtc->config.cpu_transcoder;
763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
768 frame = I915_READ(frame_reg);
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
775 * intel_wait_for_vblank - wait for vblank on a given pipe
777 * @pipe: pipe to wait for
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 int pipestat_reg = PIPESTAT(pipe);
787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
808 /* Wait for vblank interrupt bit to set */
809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
812 DRM_DEBUG_KMS("vblank wait timed out\n");
816 * intel_wait_for_pipe_off - wait for pipe to turn off
818 * @pipe: pipe to wait for
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
825 * wait for the pipe register state bit to turn off
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
838 if (INTEL_INFO(dev)->gen >= 4) {
839 int reg = PIPECONF(cpu_transcoder);
841 /* Wait for the Pipe State to go off */
842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
844 WARN(1, "pipe_off wait timed out\n");
846 u32 last_line, line_mask;
847 int reg = PIPEDSL(pipe);
848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
851 line_mask = DSL_LINEMASK_GEN2;
853 line_mask = DSL_LINEMASK_GEN3;
855 /* Wait for the display line to settle */
857 last_line = I915_READ(reg) & line_mask;
859 } while (((I915_READ(reg) & line_mask) != last_line) &&
860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
862 WARN(1, "pipe_off wait timed out\n");
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
871 * Returns true if @port is connected, false otherwise.
873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
878 if (HAS_PCH_IBX(dev_priv->dev)) {
881 bit = SDE_PORTB_HOTPLUG;
884 bit = SDE_PORTC_HOTPLUG;
887 bit = SDE_PORTD_HOTPLUG;
895 bit = SDE_PORTB_HOTPLUG_CPT;
898 bit = SDE_PORTC_HOTPLUG_CPT;
901 bit = SDE_PORTD_HOTPLUG_CPT;
908 return I915_READ(SDEISR) & bit;
911 static const char *state_string(bool enabled)
913 return enabled ? "on" : "off";
916 /* Only for pre-ILK configs */
917 void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
932 struct intel_shared_dpll *
933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
937 if (crtc->config.shared_dpll < 0)
940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
949 struct intel_dpll_hw_state hw_state;
951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 "asserting DPLL %s with no DPLL\n", state_string(state)))
960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
961 WARN(cur_state != state,
962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
978 val = I915_READ(reg);
979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020 if (HAS_DDI(dev_priv->dev))
1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1046 int pp_reg, lvds_reg;
1048 enum pipe panel_pipe = PIPE_A;
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1055 pp_reg = PP_CONTROL;
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
1072 void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
1096 pipe_name(pipe), state_string(state), state_string(cur_state));
1099 static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
1114 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1117 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1120 struct drm_device *dev = dev_priv->dev;
1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1135 /* Need to check both planes against the pipe */
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
1147 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1150 struct drm_device *dev = dev_priv->dev;
1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1164 val = I915_READ(reg);
1165 WARN((val & SPRITE_ENABLE),
1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
1170 val = I915_READ(reg);
1171 WARN((val & DVS_ENABLE),
1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1173 plane_name(pipe), pipe_name(pipe));
1177 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1193 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1200 reg = PCH_TRANSCONF(pipe);
1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1208 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
1211 if ((val & DP_PORT_EN) == 0)
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1226 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1229 if ((val & SDVO_ENABLE) == 0)
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1242 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1245 if ((val & LVDS_PORT_EN) == 0)
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1258 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1273 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, int reg, u32 port_sel)
1276 u32 val = I915_READ(reg);
1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1279 reg, pipe_name(pipe));
1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
1283 "IBX PCH dp port still using transcoder B\n");
1286 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1289 u32 val = I915_READ(reg);
1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1292 reg, pipe_name(pipe));
1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1295 && (val & SDVO_PIPE_B_SELECT),
1296 "IBX PCH hdmi port still using transcoder B\n");
1299 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1310 val = I915_READ(reg);
1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
1316 val = I915_READ(reg);
1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1326 static void vlv_enable_pll(struct intel_crtc *crtc)
1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
1333 assert_pipe_disabled(dev_priv, crtc->pipe);
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1340 assert_panel_unlocked(dev_priv, crtc->pipe);
1342 I915_WRITE(reg, dpll);
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
1352 /* We do this three times for luck */
1353 I915_WRITE(reg, dpll);
1355 udelay(150); /* wait for warmup */
1356 I915_WRITE(reg, dpll);
1358 udelay(150); /* wait for warmup */
1359 I915_WRITE(reg, dpll);
1361 udelay(150); /* wait for warmup */
1364 static void i9xx_enable_pll(struct intel_crtc *crtc)
1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
1371 assert_pipe_disabled(dev_priv, crtc->pipe);
1373 /* No really, not for ILK+ */
1374 BUG_ON(dev_priv->info->gen >= 5);
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
1380 I915_WRITE(reg, dpll);
1382 /* Wait for the clocks to stabilize. */
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1393 * So write it again.
1395 I915_WRITE(reg, dpll);
1398 /* We do this three times for luck */
1399 I915_WRITE(reg, dpll);
1401 udelay(150); /* wait for warmup */
1402 I915_WRITE(reg, dpll);
1404 udelay(150); /* wait for warmup */
1405 I915_WRITE(reg, dpll);
1407 udelay(150); /* wait for warmup */
1411 * i9xx_disable_pll - disable a PLL
1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1417 * Note! This is for pre-ILK only.
1419 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
1432 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1439 port_mask = DPLL_PORTC_READY_MASK;
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1447 * ironlake_enable_shared_dpll - enable PCH PLL
1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1454 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1459 /* PCH PLLs only available on ILK, SNB and IVB */
1460 BUG_ON(dev_priv->info->gen < 5);
1461 if (WARN_ON(pll == NULL))
1464 if (WARN_ON(pll->refcount == 0))
1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
1469 crtc->base.base.id);
1471 if (pll->active++) {
1473 assert_shared_dpll_enabled(dev_priv, pll);
1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1479 pll->enable(dev_priv, pll);
1483 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
1490 if (WARN_ON(pll == NULL))
1493 if (WARN_ON(pll->refcount == 0))
1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
1498 crtc->base.base.id);
1500 if (WARN_ON(pll->active == 0)) {
1501 assert_shared_dpll_disabled(dev_priv, pll);
1505 assert_shared_dpll_enabled(dev_priv, pll);
1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1511 pll->disable(dev_priv, pll);
1515 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1518 struct drm_device *dev = dev_priv->dev;
1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1521 uint32_t reg, val, pipeconf_val;
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1526 /* Make sure PCH DPLL is enabled */
1527 assert_shared_dpll_enabled(dev_priv,
1528 intel_crtc_to_shared_dpll(intel_crtc));
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
1543 reg = PCH_TRANSCONF(pipe);
1544 val = I915_READ(reg);
1545 pipeconf_val = I915_READ(PIPECONF(pipe));
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1562 val |= TRANS_INTERLACED;
1564 val |= TRANS_PROGRESSIVE;
1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1571 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1572 enum transcoder cpu_transcoder)
1574 u32 val, pipeconf_val;
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1579 /* FDI must be feeding us bits for PCH ports */
1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
1593 val |= TRANS_INTERLACED;
1595 val |= TRANS_PROGRESSIVE;
1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1599 DRM_ERROR("Failed to enable PCH transcoder\n");
1602 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1605 struct drm_device *dev = dev_priv->dev;
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1615 reg = PCH_TRANSCONF(pipe);
1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1632 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1636 val = I915_READ(LPT_TRANSCONF);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(LPT_TRANSCONF, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1641 DRM_ERROR("Failed to disable PCH transcoder\n");
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1650 * intel_enable_pipe - enable a pipe, asserting requirements
1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1658 * @pipe should be %PIPE_A or %PIPE_B.
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1663 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1668 enum pipe pch_transcoder;
1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1675 if (HAS_PCH_LPT(dev_priv->dev))
1676 pch_transcoder = TRANSCODER_A;
1678 pch_transcoder = pipe;
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
1686 assert_pll_enabled(dev_priv, pipe);
1689 /* if driving the PCH, we need FDI enabled */
1690 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1691 assert_fdi_tx_pll_enabled(dev_priv,
1692 (enum pipe) cpu_transcoder);
1694 /* FIXME: assert CPU port conditions for SNB+ */
1697 reg = PIPECONF(cpu_transcoder);
1698 val = I915_READ(reg);
1699 if (val & PIPECONF_ENABLE)
1702 I915_WRITE(reg, val | PIPECONF_ENABLE);
1703 intel_wait_for_vblank(dev_priv->dev, pipe);
1707 * intel_disable_pipe - disable a pipe, asserting requirements
1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe to disable
1711 * Disable @pipe, making sure that various hardware specific requirements
1712 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1714 * @pipe should be %PIPE_A or %PIPE_B.
1716 * Will wait until the pipe has shut down before returning.
1718 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1721 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 * Make sure planes won't keep trying to pump pixels to us,
1728 * or we might hang the display.
1730 assert_planes_disabled(dev_priv, pipe);
1731 assert_sprites_disabled(dev_priv, pipe);
1733 /* Don't disable pipe A or pipe A PLLs if needed */
1734 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1737 reg = PIPECONF(cpu_transcoder);
1738 val = I915_READ(reg);
1739 if ((val & PIPECONF_ENABLE) == 0)
1742 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1743 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1747 * Plane regs are double buffered, going from enabled->disabled needs a
1748 * trigger in order to latch. The display address reg provides this.
1750 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1753 if (dev_priv->info->gen >= 4)
1754 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1756 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1760 * intel_enable_plane - enable a display plane on a given pipe
1761 * @dev_priv: i915 private structure
1762 * @plane: plane to enable
1763 * @pipe: pipe being fed
1765 * Enable @plane on @pipe, making sure that @pipe is running first.
1767 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768 enum plane plane, enum pipe pipe)
1773 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774 assert_pipe_enabled(dev_priv, pipe);
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
1778 if (val & DISPLAY_PLANE_ENABLE)
1781 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1787 * intel_disable_plane - disable a display plane
1788 * @dev_priv: i915 private structure
1789 * @plane: plane to disable
1790 * @pipe: pipe consuming the data
1792 * Disable @plane; should be an independent operation.
1794 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795 enum plane plane, enum pipe pipe)
1800 reg = DSPCNTR(plane);
1801 val = I915_READ(reg);
1802 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1805 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1806 intel_flush_display_plane(dev_priv, plane);
1807 intel_wait_for_vblank(dev_priv->dev, pipe);
1810 static bool need_vtd_wa(struct drm_device *dev)
1812 #ifdef CONFIG_INTEL_IOMMU
1813 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1820 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1821 struct drm_i915_gem_object *obj,
1822 struct intel_ring_buffer *pipelined)
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1828 switch (obj->tiling_mode) {
1829 case I915_TILING_NONE:
1830 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831 alignment = 128 * 1024;
1832 else if (INTEL_INFO(dev)->gen >= 4)
1833 alignment = 4 * 1024;
1835 alignment = 64 * 1024;
1838 /* pin() will align the object as required by fence */
1842 /* Despite that we check this in framebuffer_init userspace can
1843 * screw us over and change the tiling after the fact. Only
1844 * pinned buffers can't change their tiling. */
1845 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1851 /* Note that the w/a also requires 64 PTE of padding following the
1852 * bo. We currently fill all unused PTE with the shadow page and so
1853 * we should always have valid PTE following the scanout preventing
1856 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857 alignment = 256 * 1024;
1859 dev_priv->mm.interruptible = false;
1860 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1862 goto err_interruptible;
1864 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865 * fence, whereas 965+ only requires a fence if using
1866 * framebuffer compression. For simplicity, we always install
1867 * a fence as the cost is not that onerous.
1869 ret = i915_gem_object_get_fence(obj);
1873 i915_gem_object_pin_fence(obj);
1875 dev_priv->mm.interruptible = true;
1879 i915_gem_object_unpin_from_display_plane(obj);
1881 dev_priv->mm.interruptible = true;
1885 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1887 i915_gem_object_unpin_fence(obj);
1888 i915_gem_object_unpin_from_display_plane(obj);
1891 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892 * is assumed to be a power-of-two. */
1893 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894 unsigned int tiling_mode,
1898 if (tiling_mode != I915_TILING_NONE) {
1899 unsigned int tile_rows, tiles;
1904 tiles = *x / (512/cpp);
1907 return tile_rows * pitch * 8 + tiles * 4096;
1909 unsigned int offset;
1911 offset = *y * pitch + *x * cpp;
1913 *x = (offset & 4095) / cpp;
1914 return offset & -4096;
1918 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1921 struct drm_device *dev = crtc->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924 struct intel_framebuffer *intel_fb;
1925 struct drm_i915_gem_object *obj;
1926 int plane = intel_crtc->plane;
1927 unsigned long linear_offset;
1936 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1940 intel_fb = to_intel_framebuffer(fb);
1941 obj = intel_fb->obj;
1943 reg = DSPCNTR(plane);
1944 dspcntr = I915_READ(reg);
1945 /* Mask out pixel format bits in case we change it */
1946 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1947 switch (fb->pixel_format) {
1949 dspcntr |= DISPPLANE_8BPP;
1951 case DRM_FORMAT_XRGB1555:
1952 case DRM_FORMAT_ARGB1555:
1953 dspcntr |= DISPPLANE_BGRX555;
1955 case DRM_FORMAT_RGB565:
1956 dspcntr |= DISPPLANE_BGRX565;
1958 case DRM_FORMAT_XRGB8888:
1959 case DRM_FORMAT_ARGB8888:
1960 dspcntr |= DISPPLANE_BGRX888;
1962 case DRM_FORMAT_XBGR8888:
1963 case DRM_FORMAT_ABGR8888:
1964 dspcntr |= DISPPLANE_RGBX888;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 dspcntr |= DISPPLANE_BGRX101010;
1970 case DRM_FORMAT_XBGR2101010:
1971 case DRM_FORMAT_ABGR2101010:
1972 dspcntr |= DISPPLANE_RGBX101010;
1978 if (INTEL_INFO(dev)->gen >= 4) {
1979 if (obj->tiling_mode != I915_TILING_NONE)
1980 dspcntr |= DISPPLANE_TILED;
1982 dspcntr &= ~DISPPLANE_TILED;
1986 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1988 I915_WRITE(reg, dspcntr);
1990 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 intel_crtc->dspaddr_offset =
1994 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995 fb->bits_per_pixel / 8,
1997 linear_offset -= intel_crtc->dspaddr_offset;
1999 intel_crtc->dspaddr_offset = linear_offset;
2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2005 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2006 if (INTEL_INFO(dev)->gen >= 4) {
2007 I915_MODIFY_DISPBASE(DSPSURF(plane),
2008 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2009 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2010 I915_WRITE(DSPLINOFF(plane), linear_offset);
2012 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2018 static int ironlake_update_plane(struct drm_crtc *crtc,
2019 struct drm_framebuffer *fb, int x, int y)
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
2027 unsigned long linear_offset;
2037 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->pixel_format) {
2050 dspcntr |= DISPPLANE_8BPP;
2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2078 dspcntr &= ~DISPPLANE_TILED;
2081 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2083 I915_WRITE(reg, dspcntr);
2085 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2086 intel_crtc->dspaddr_offset =
2087 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2088 fb->bits_per_pixel / 8,
2090 linear_offset -= intel_crtc->dspaddr_offset;
2092 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2093 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2095 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2096 I915_MODIFY_DISPBASE(DSPSURF(plane),
2097 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2098 if (IS_HASWELL(dev)) {
2099 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2101 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102 I915_WRITE(DSPLINOFF(plane), linear_offset);
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112 int x, int y, enum mode_set_atomic state)
2114 struct drm_device *dev = crtc->dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2117 if (dev_priv->display.disable_fbc)
2118 dev_priv->display.disable_fbc(dev);
2119 intel_increase_pllclock(crtc);
2121 return dev_priv->display.update_plane(crtc, fb, x, y);
2124 void intel_display_handle_reset(struct drm_device *dev)
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 struct drm_crtc *crtc;
2130 * Flips in the rings have been nuked by the reset,
2131 * so complete all pending flips so that user space
2132 * will get its events and not get stuck.
2134 * Also update the base address of all primary
2135 * planes to the the last fb to make sure we're
2136 * showing the correct fb after a reset.
2138 * Need to make two loops over the crtcs so that we
2139 * don't try to grab a crtc mutex before the
2140 * pending_flip_queue really got woken up.
2143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145 enum plane plane = intel_crtc->plane;
2147 intel_prepare_page_flip(dev, plane);
2148 intel_finish_page_flip_plane(dev, plane);
2151 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154 mutex_lock(&crtc->mutex);
2155 if (intel_crtc->active)
2156 dev_priv->display.update_plane(crtc, crtc->fb,
2158 mutex_unlock(&crtc->mutex);
2163 intel_finish_fb(struct drm_framebuffer *old_fb)
2165 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2166 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2167 bool was_interruptible = dev_priv->mm.interruptible;
2170 /* Big Hammer, we also need to ensure that any pending
2171 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2172 * current scanout is retired before unpinning the old
2175 * This should only fail upon a hung GPU, in which case we
2176 * can safely continue.
2178 dev_priv->mm.interruptible = false;
2179 ret = i915_gem_object_finish_gpu(obj);
2180 dev_priv->mm.interruptible = was_interruptible;
2185 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_master_private *master_priv;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2191 if (!dev->primary->master)
2194 master_priv = dev->primary->master->driver_priv;
2195 if (!master_priv->sarea_priv)
2198 switch (intel_crtc->pipe) {
2200 master_priv->sarea_priv->pipeA_x = x;
2201 master_priv->sarea_priv->pipeA_y = y;
2204 master_priv->sarea_priv->pipeB_x = x;
2205 master_priv->sarea_priv->pipeB_y = y;
2213 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2214 struct drm_framebuffer *fb)
2216 struct drm_device *dev = crtc->dev;
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2219 struct drm_framebuffer *old_fb;
2224 DRM_ERROR("No FB bound\n");
2228 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2229 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2230 plane_name(intel_crtc->plane),
2231 INTEL_INFO(dev)->num_pipes);
2235 mutex_lock(&dev->struct_mutex);
2236 ret = intel_pin_and_fence_fb_obj(dev,
2237 to_intel_framebuffer(fb)->obj,
2240 mutex_unlock(&dev->struct_mutex);
2241 DRM_ERROR("pin & fence failed\n");
2245 /* Update pipe size and adjust fitter if needed */
2246 if (i915_fastboot) {
2247 I915_WRITE(PIPESRC(intel_crtc->pipe),
2248 ((crtc->mode.hdisplay - 1) << 16) |
2249 (crtc->mode.vdisplay - 1));
2250 if (!intel_crtc->config.pch_pfit.size &&
2251 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2252 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2253 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2254 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2255 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2259 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2261 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2262 mutex_unlock(&dev->struct_mutex);
2263 DRM_ERROR("failed to update base address\n");
2273 if (intel_crtc->active && old_fb != fb)
2274 intel_wait_for_vblank(dev, intel_crtc->pipe);
2275 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2278 intel_update_fbc(dev);
2279 intel_edp_psr_update(dev);
2280 mutex_unlock(&dev->struct_mutex);
2282 intel_crtc_update_sarea_pos(crtc, x, y);
2287 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2289 struct drm_device *dev = crtc->dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2292 int pipe = intel_crtc->pipe;
2295 /* enable normal train */
2296 reg = FDI_TX_CTL(pipe);
2297 temp = I915_READ(reg);
2298 if (IS_IVYBRIDGE(dev)) {
2299 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2300 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2302 temp &= ~FDI_LINK_TRAIN_NONE;
2303 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2305 I915_WRITE(reg, temp);
2307 reg = FDI_RX_CTL(pipe);
2308 temp = I915_READ(reg);
2309 if (HAS_PCH_CPT(dev)) {
2310 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2311 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2313 temp &= ~FDI_LINK_TRAIN_NONE;
2314 temp |= FDI_LINK_TRAIN_NONE;
2316 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2318 /* wait one idle pattern time */
2322 /* IVB wants error correction enabled */
2323 if (IS_IVYBRIDGE(dev))
2324 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2325 FDI_FE_ERRC_ENABLE);
2328 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2330 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2333 static void ivb_modeset_global_resources(struct drm_device *dev)
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *pipe_B_crtc =
2337 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2338 struct intel_crtc *pipe_C_crtc =
2339 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2343 * When everything is off disable fdi C so that we could enable fdi B
2344 * with all lanes. Note that we don't care about enabled pipes without
2345 * an enabled pch encoder.
2347 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2348 !pipe_has_enabled_pch(pipe_C_crtc)) {
2349 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2350 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2352 temp = I915_READ(SOUTH_CHICKEN1);
2353 temp &= ~FDI_BC_BIFURCATION_SELECT;
2354 DRM_DEBUG_KMS("disabling fdi C rx\n");
2355 I915_WRITE(SOUTH_CHICKEN1, temp);
2359 /* The FDI link training functions for ILK/Ibexpeak. */
2360 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362 struct drm_device *dev = crtc->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 int pipe = intel_crtc->pipe;
2366 int plane = intel_crtc->plane;
2367 u32 reg, temp, tries;
2369 /* FDI needs bits from pipe & plane first */
2370 assert_pipe_enabled(dev_priv, pipe);
2371 assert_plane_enabled(dev_priv, plane);
2373 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 reg = FDI_RX_IMR(pipe);
2376 temp = I915_READ(reg);
2377 temp &= ~FDI_RX_SYMBOL_LOCK;
2378 temp &= ~FDI_RX_BIT_LOCK;
2379 I915_WRITE(reg, temp);
2383 /* enable CPU FDI TX and PCH FDI RX */
2384 reg = FDI_TX_CTL(pipe);
2385 temp = I915_READ(reg);
2386 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2387 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_1;
2390 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2392 reg = FDI_RX_CTL(pipe);
2393 temp = I915_READ(reg);
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_PATTERN_1;
2396 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2401 /* Ironlake workaround, enable clock pointer after FDI enable*/
2402 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2403 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2404 FDI_RX_PHASE_SYNC_POINTER_EN);
2406 reg = FDI_RX_IIR(pipe);
2407 for (tries = 0; tries < 5; tries++) {
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2411 if ((temp & FDI_RX_BIT_LOCK)) {
2412 DRM_DEBUG_KMS("FDI train 1 done.\n");
2413 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2418 DRM_ERROR("FDI train 1 fail!\n");
2421 reg = FDI_TX_CTL(pipe);
2422 temp = I915_READ(reg);
2423 temp &= ~FDI_LINK_TRAIN_NONE;
2424 temp |= FDI_LINK_TRAIN_PATTERN_2;
2425 I915_WRITE(reg, temp);
2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_2;
2431 I915_WRITE(reg, temp);
2436 reg = FDI_RX_IIR(pipe);
2437 for (tries = 0; tries < 5; tries++) {
2438 temp = I915_READ(reg);
2439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2441 if (temp & FDI_RX_SYMBOL_LOCK) {
2442 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2443 DRM_DEBUG_KMS("FDI train 2 done.\n");
2448 DRM_ERROR("FDI train 2 fail!\n");
2450 DRM_DEBUG_KMS("FDI train done\n");
2454 static const int snb_b_fdi_train_param[] = {
2455 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2456 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2457 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2458 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2461 /* The FDI link training functions for SNB/Cougarpoint. */
2462 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2464 struct drm_device *dev = crtc->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467 int pipe = intel_crtc->pipe;
2468 u32 reg, temp, i, retry;
2470 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2472 reg = FDI_RX_IMR(pipe);
2473 temp = I915_READ(reg);
2474 temp &= ~FDI_RX_SYMBOL_LOCK;
2475 temp &= ~FDI_RX_BIT_LOCK;
2476 I915_WRITE(reg, temp);
2481 /* enable CPU FDI TX and PCH FDI RX */
2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2485 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2486 temp &= ~FDI_LINK_TRAIN_NONE;
2487 temp |= FDI_LINK_TRAIN_PATTERN_1;
2488 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2490 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2491 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2493 I915_WRITE(FDI_RX_MISC(pipe),
2494 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2510 for (i = 0; i < 4; i++) {
2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
2513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514 temp |= snb_b_fdi_train_param[i];
2515 I915_WRITE(reg, temp);
2520 for (retry = 0; retry < 5; retry++) {
2521 reg = FDI_RX_IIR(pipe);
2522 temp = I915_READ(reg);
2523 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2524 if (temp & FDI_RX_BIT_LOCK) {
2525 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2526 DRM_DEBUG_KMS("FDI train 1 done.\n");
2535 DRM_ERROR("FDI train 1 fail!\n");
2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_2;
2543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2547 I915_WRITE(reg, temp);
2549 reg = FDI_RX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 if (HAS_PCH_CPT(dev)) {
2552 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
2558 I915_WRITE(reg, temp);
2563 for (i = 0; i < 4; i++) {
2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
2566 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567 temp |= snb_b_fdi_train_param[i];
2568 I915_WRITE(reg, temp);
2573 for (retry = 0; retry < 5; retry++) {
2574 reg = FDI_RX_IIR(pipe);
2575 temp = I915_READ(reg);
2576 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2577 if (temp & FDI_RX_SYMBOL_LOCK) {
2578 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2579 DRM_DEBUG_KMS("FDI train 2 done.\n");
2588 DRM_ERROR("FDI train 2 fail!\n");
2590 DRM_DEBUG_KMS("FDI train done.\n");
2593 /* Manual link training for Ivy Bridge A0 parts */
2594 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
2608 I915_WRITE(reg, temp);
2613 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2614 I915_READ(FDI_RX_IIR(pipe)));
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg = FDI_TX_CTL(pipe);
2618 temp = I915_READ(reg);
2619 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2620 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2621 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2625 temp |= FDI_COMPOSITE_SYNC;
2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2628 I915_WRITE(FDI_RX_MISC(pipe),
2629 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2636 temp |= FDI_COMPOSITE_SYNC;
2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2642 for (i = 0; i < 4; i++) {
2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
2647 I915_WRITE(reg, temp);
2652 reg = FDI_RX_IIR(pipe);
2653 temp = I915_READ(reg);
2654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK ||
2657 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2658 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2659 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2664 DRM_ERROR("FDI train 1 fail!\n");
2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 I915_WRITE(reg, temp);
2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2679 I915_WRITE(reg, temp);
2684 for (i = 0; i < 4; i++) {
2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688 temp |= snb_b_fdi_train_param[i];
2689 I915_WRITE(reg, temp);
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698 if (temp & FDI_RX_SYMBOL_LOCK) {
2699 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2705 DRM_ERROR("FDI train 2 fail!\n");
2707 DRM_DEBUG_KMS("FDI train done.\n");
2710 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2712 struct drm_device *dev = intel_crtc->base.dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 int pipe = intel_crtc->pipe;
2718 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2722 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2723 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2724 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729 /* Switch from Rawclk to PCDclk */
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp | FDI_PCDCLK);
2736 /* Enable CPU FDI TX PLL, always on for Ironlake */
2737 reg = FDI_TX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2740 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2747 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2749 struct drm_device *dev = intel_crtc->base.dev;
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 int pipe = intel_crtc->pipe;
2754 /* Switch from PCDclk to Rawclk */
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2759 /* Disable CPU FDI TX PLL */
2760 reg = FDI_TX_CTL(pipe);
2761 temp = I915_READ(reg);
2762 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2767 reg = FDI_RX_CTL(pipe);
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2771 /* Wait for the clocks to turn off. */
2776 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2778 struct drm_device *dev = crtc->dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2781 int pipe = intel_crtc->pipe;
2784 /* disable CPU FDI tx and PCH FDI rx */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2790 reg = FDI_RX_CTL(pipe);
2791 temp = I915_READ(reg);
2792 temp &= ~(0x7 << 16);
2793 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2794 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2799 /* Ironlake workaround, disable clock pointer after downing FDI */
2800 if (HAS_PCH_IBX(dev)) {
2801 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2804 /* still set train pattern 1 */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 temp &= ~FDI_LINK_TRAIN_NONE;
2808 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809 I915_WRITE(reg, temp);
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 if (HAS_PCH_CPT(dev)) {
2814 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2815 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2817 temp &= ~FDI_LINK_TRAIN_NONE;
2818 temp |= FDI_LINK_TRAIN_PATTERN_1;
2820 /* BPC in FDI rx is consistent with that in PIPECONF */
2821 temp &= ~(0x07 << 16);
2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp);
2829 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2831 struct drm_device *dev = crtc->dev;
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2834 unsigned long flags;
2837 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2838 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2841 spin_lock_irqsave(&dev->event_lock, flags);
2842 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2843 spin_unlock_irqrestore(&dev->event_lock, flags);
2848 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2850 struct drm_device *dev = crtc->dev;
2851 struct drm_i915_private *dev_priv = dev->dev_private;
2853 if (crtc->fb == NULL)
2856 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2858 wait_event(dev_priv->pending_flip_queue,
2859 !intel_crtc_has_pending_flip(crtc));
2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
2866 /* Program iCLKIP clock to the desired frequency */
2867 static void lpt_program_iclkip(struct drm_crtc *crtc)
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2874 mutex_lock(&dev_priv->dpio_lock);
2876 /* It is necessary to ungate the pixclk gate prior to programming
2877 * the divisors, and gate it back when it is done.
2879 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2881 /* Disable SSCCTL */
2882 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2883 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2887 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2888 if (crtc->mode.clock == 20000) {
2893 /* The iCLK virtual clock root frequency is in MHz,
2894 * but the crtc->mode.clock in in KHz. To get the divisors,
2895 * it is necessary to divide one by another, so we
2896 * convert the virtual clock precision to KHz here for higher
2899 u32 iclk_virtual_root_freq = 172800 * 1000;
2900 u32 iclk_pi_range = 64;
2901 u32 desired_divisor, msb_divisor_value, pi_value;
2903 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2904 msb_divisor_value = desired_divisor / iclk_pi_range;
2905 pi_value = desired_divisor % iclk_pi_range;
2908 divsel = msb_divisor_value - 2;
2909 phaseinc = pi_value;
2912 /* This should not happen with any sane values */
2913 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2914 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2915 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2916 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2918 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2925 /* Program SSCDIVINTPHASE6 */
2926 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2927 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2928 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2929 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2930 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2931 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2932 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2933 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2935 /* Program SSCAUXDIV */
2936 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2937 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2938 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2939 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2941 /* Enable modulator and associated divider */
2942 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2943 temp &= ~SBI_SSCCTL_DISABLE;
2944 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2946 /* Wait for initialization time */
2949 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2951 mutex_unlock(&dev_priv->dpio_lock);
2954 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2955 enum pipe pch_transcoder)
2957 struct drm_device *dev = crtc->base.dev;
2958 struct drm_i915_private *dev_priv = dev->dev_private;
2959 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2961 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2962 I915_READ(HTOTAL(cpu_transcoder)));
2963 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2964 I915_READ(HBLANK(cpu_transcoder)));
2965 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2966 I915_READ(HSYNC(cpu_transcoder)));
2968 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2969 I915_READ(VTOTAL(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2971 I915_READ(VBLANK(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2973 I915_READ(VSYNC(cpu_transcoder)));
2974 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2975 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2979 * Enable PCH resources required for PCH ports:
2981 * - FDI training & RX/TX
2982 * - update transcoder timings
2983 * - DP transcoding bits
2986 static void ironlake_pch_enable(struct drm_crtc *crtc)
2988 struct drm_device *dev = crtc->dev;
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2991 int pipe = intel_crtc->pipe;
2994 assert_pch_transcoder_disabled(dev_priv, pipe);
2996 /* Write the TU size bits before fdi link training, so that error
2997 * detection works. */
2998 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2999 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3001 /* For PCH output, training FDI link */
3002 dev_priv->display.fdi_link_train(crtc);
3004 /* We need to program the right clock selection before writing the pixel
3005 * mutliplier into the DPLL. */
3006 if (HAS_PCH_CPT(dev)) {
3009 temp = I915_READ(PCH_DPLL_SEL);
3010 temp |= TRANS_DPLL_ENABLE(pipe);
3011 sel = TRANS_DPLLB_SEL(pipe);
3012 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3016 I915_WRITE(PCH_DPLL_SEL, temp);
3019 /* XXX: pch pll's can be enabled any time before we enable the PCH
3020 * transcoder, and we actually should do this to not upset any PCH
3021 * transcoder that already use the clock when we share it.
3023 * Note that enable_shared_dpll tries to do the right thing, but
3024 * get_shared_dpll unconditionally resets the pll - we need that to have
3025 * the right LVDS enable sequence. */
3026 ironlake_enable_shared_dpll(intel_crtc);
3028 /* set transcoder timing, panel must allow it */
3029 assert_panel_unlocked(dev_priv, pipe);
3030 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3032 intel_fdi_normal_train(crtc);
3034 /* For PCH DP, enable TRANS_DP_CTL */
3035 if (HAS_PCH_CPT(dev) &&
3036 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3037 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3039 reg = TRANS_DP_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3042 TRANS_DP_SYNC_MASK |
3044 temp |= (TRANS_DP_OUTPUT_ENABLE |
3045 TRANS_DP_ENH_FRAMING);
3046 temp |= bpc << 9; /* same format but at 11:9 */
3048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3053 switch (intel_trans_dp_port_sel(crtc)) {
3055 temp |= TRANS_DP_PORT_SEL_B;
3058 temp |= TRANS_DP_PORT_SEL_C;
3061 temp |= TRANS_DP_PORT_SEL_D;
3067 I915_WRITE(reg, temp);
3070 ironlake_enable_pch_transcoder(dev_priv, pipe);
3073 static void lpt_pch_enable(struct drm_crtc *crtc)
3075 struct drm_device *dev = crtc->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3078 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3080 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3082 lpt_program_iclkip(crtc);
3084 /* Set transcoder timing. */
3085 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3087 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3090 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3092 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3097 if (pll->refcount == 0) {
3098 WARN(1, "bad %s refcount\n", pll->name);
3102 if (--pll->refcount == 0) {
3104 WARN_ON(pll->active);
3107 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3110 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3112 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3113 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3114 enum intel_dpll_id i;
3117 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3118 crtc->base.base.id, pll->name);
3119 intel_put_shared_dpll(crtc);
3122 if (HAS_PCH_IBX(dev_priv->dev)) {
3123 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3124 i = (enum intel_dpll_id) crtc->pipe;
3125 pll = &dev_priv->shared_dplls[i];
3127 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3128 crtc->base.base.id, pll->name);
3133 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3134 pll = &dev_priv->shared_dplls[i];
3136 /* Only want to check enabled timings first */
3137 if (pll->refcount == 0)
3140 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3141 sizeof(pll->hw_state)) == 0) {
3142 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3144 pll->name, pll->refcount, pll->active);
3150 /* Ok no matching timings, maybe there's a free one? */
3151 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3152 pll = &dev_priv->shared_dplls[i];
3153 if (pll->refcount == 0) {
3154 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3155 crtc->base.base.id, pll->name);
3163 crtc->config.shared_dpll = i;
3164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3165 pipe_name(crtc->pipe));
3167 if (pll->active == 0) {
3168 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3169 sizeof(pll->hw_state));
3171 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3173 assert_shared_dpll_disabled(dev_priv, pll);
3175 pll->mode_set(dev_priv, pll);
3182 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 int dslreg = PIPEDSL(pipe);
3188 temp = I915_READ(dslreg);
3190 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3191 if (wait_for(I915_READ(dslreg) != temp, 5))
3192 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3196 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3198 struct drm_device *dev = crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int pipe = crtc->pipe;
3202 if (crtc->config.pch_pfit.size) {
3203 /* Force use of hard-coded filter coefficients
3204 * as some pre-programmed values are broken,
3207 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3208 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3209 PF_PIPE_SEL_IVB(pipe));
3211 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3212 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3213 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3217 static void intel_enable_planes(struct drm_crtc *crtc)
3219 struct drm_device *dev = crtc->dev;
3220 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3221 struct intel_plane *intel_plane;
3223 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3224 if (intel_plane->pipe == pipe)
3225 intel_plane_restore(&intel_plane->base);
3228 static void intel_disable_planes(struct drm_crtc *crtc)
3230 struct drm_device *dev = crtc->dev;
3231 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3232 struct intel_plane *intel_plane;
3234 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3235 if (intel_plane->pipe == pipe)
3236 intel_plane_disable(&intel_plane->base);
3239 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3241 struct drm_device *dev = crtc->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 struct intel_encoder *encoder;
3245 int pipe = intel_crtc->pipe;
3246 int plane = intel_crtc->plane;
3248 WARN_ON(!crtc->enabled);
3250 if (intel_crtc->active)
3253 intel_crtc->active = true;
3255 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3256 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3258 intel_update_watermarks(dev);
3260 for_each_encoder_on_crtc(dev, crtc, encoder)
3261 if (encoder->pre_enable)
3262 encoder->pre_enable(encoder);
3264 if (intel_crtc->config.has_pch_encoder) {
3265 /* Note: FDI PLL enabling _must_ be done before we enable the
3266 * cpu pipes, hence this is separate from all the other fdi/pch
3268 ironlake_fdi_pll_enable(intel_crtc);
3270 assert_fdi_tx_disabled(dev_priv, pipe);
3271 assert_fdi_rx_disabled(dev_priv, pipe);
3274 ironlake_pfit_enable(intel_crtc);
3277 * On ILK+ LUT must be loaded before the pipe is running but with
3280 intel_crtc_load_lut(crtc);
3282 intel_enable_pipe(dev_priv, pipe,
3283 intel_crtc->config.has_pch_encoder);
3284 intel_enable_plane(dev_priv, plane, pipe);
3285 intel_enable_planes(crtc);
3286 intel_crtc_update_cursor(crtc, true);
3288 if (intel_crtc->config.has_pch_encoder)
3289 ironlake_pch_enable(crtc);
3291 mutex_lock(&dev->struct_mutex);
3292 intel_update_fbc(dev);
3293 mutex_unlock(&dev->struct_mutex);
3295 for_each_encoder_on_crtc(dev, crtc, encoder)
3296 encoder->enable(encoder);
3298 if (HAS_PCH_CPT(dev))
3299 cpt_verify_modeset(dev, intel_crtc->pipe);
3302 * There seems to be a race in PCH platform hw (at least on some
3303 * outputs) where an enabled pipe still completes any pageflip right
3304 * away (as if the pipe is off) instead of waiting for vblank. As soon
3305 * as the first vblank happend, everything works as expected. Hence just
3306 * wait for one vblank before returning to avoid strange things
3309 intel_wait_for_vblank(dev, intel_crtc->pipe);
3312 /* IPS only exists on ULT machines and is tied to pipe A. */
3313 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3315 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3318 static void hsw_enable_ips(struct intel_crtc *crtc)
3320 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3322 if (!crtc->config.ips_enabled)
3325 /* We can only enable IPS after we enable a plane and wait for a vblank.
3326 * We guarantee that the plane is enabled by calling intel_enable_ips
3327 * only after intel_enable_plane. And intel_enable_plane already waits
3328 * for a vblank, so all we need to do here is to enable the IPS bit. */
3329 assert_plane_enabled(dev_priv, crtc->plane);
3330 I915_WRITE(IPS_CTL, IPS_ENABLE);
3333 static void hsw_disable_ips(struct intel_crtc *crtc)
3335 struct drm_device *dev = crtc->base.dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3338 if (!crtc->config.ips_enabled)
3341 assert_plane_enabled(dev_priv, crtc->plane);
3342 I915_WRITE(IPS_CTL, 0);
3344 /* We need to wait for a vblank before we can disable the plane. */
3345 intel_wait_for_vblank(dev, crtc->pipe);
3348 static void haswell_crtc_enable(struct drm_crtc *crtc)
3350 struct drm_device *dev = crtc->dev;
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353 struct intel_encoder *encoder;
3354 int pipe = intel_crtc->pipe;
3355 int plane = intel_crtc->plane;
3357 WARN_ON(!crtc->enabled);
3359 if (intel_crtc->active)
3362 intel_crtc->active = true;
3364 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3365 if (intel_crtc->config.has_pch_encoder)
3366 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3368 intel_update_watermarks(dev);
3370 if (intel_crtc->config.has_pch_encoder)
3371 dev_priv->display.fdi_link_train(crtc);
3373 for_each_encoder_on_crtc(dev, crtc, encoder)
3374 if (encoder->pre_enable)
3375 encoder->pre_enable(encoder);
3377 intel_ddi_enable_pipe_clock(intel_crtc);
3379 ironlake_pfit_enable(intel_crtc);
3382 * On ILK+ LUT must be loaded before the pipe is running but with
3385 intel_crtc_load_lut(crtc);
3387 intel_ddi_set_pipe_settings(crtc);
3388 intel_ddi_enable_transcoder_func(crtc);
3390 intel_enable_pipe(dev_priv, pipe,
3391 intel_crtc->config.has_pch_encoder);
3392 intel_enable_plane(dev_priv, plane, pipe);
3393 intel_enable_planes(crtc);
3394 intel_crtc_update_cursor(crtc, true);
3396 hsw_enable_ips(intel_crtc);
3398 if (intel_crtc->config.has_pch_encoder)
3399 lpt_pch_enable(crtc);
3401 mutex_lock(&dev->struct_mutex);
3402 intel_update_fbc(dev);
3403 mutex_unlock(&dev->struct_mutex);
3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->enable(encoder);
3409 * There seems to be a race in PCH platform hw (at least on some
3410 * outputs) where an enabled pipe still completes any pageflip right
3411 * away (as if the pipe is off) instead of waiting for vblank. As soon
3412 * as the first vblank happend, everything works as expected. Hence just
3413 * wait for one vblank before returning to avoid strange things
3416 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3421 struct drm_device *dev = crtc->base.dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 int pipe = crtc->pipe;
3425 /* To avoid upsetting the power well on haswell only disable the pfit if
3426 * it's in use. The hw state code will make sure we get this right. */
3427 if (crtc->config.pch_pfit.size) {
3428 I915_WRITE(PF_CTL(pipe), 0);
3429 I915_WRITE(PF_WIN_POS(pipe), 0);
3430 I915_WRITE(PF_WIN_SZ(pipe), 0);
3434 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3436 struct drm_device *dev = crtc->dev;
3437 struct drm_i915_private *dev_priv = dev->dev_private;
3438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439 struct intel_encoder *encoder;
3440 int pipe = intel_crtc->pipe;
3441 int plane = intel_crtc->plane;
3445 if (!intel_crtc->active)
3448 for_each_encoder_on_crtc(dev, crtc, encoder)
3449 encoder->disable(encoder);
3451 intel_crtc_wait_for_pending_flips(crtc);
3452 drm_vblank_off(dev, pipe);
3454 if (dev_priv->fbc.plane == plane)
3455 intel_disable_fbc(dev);
3457 intel_crtc_update_cursor(crtc, false);
3458 intel_disable_planes(crtc);
3459 intel_disable_plane(dev_priv, plane, pipe);
3461 if (intel_crtc->config.has_pch_encoder)
3462 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3464 intel_disable_pipe(dev_priv, pipe);
3466 ironlake_pfit_disable(intel_crtc);
3468 for_each_encoder_on_crtc(dev, crtc, encoder)
3469 if (encoder->post_disable)
3470 encoder->post_disable(encoder);
3472 if (intel_crtc->config.has_pch_encoder) {
3473 ironlake_fdi_disable(crtc);
3475 ironlake_disable_pch_transcoder(dev_priv, pipe);
3476 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3478 if (HAS_PCH_CPT(dev)) {
3479 /* disable TRANS_DP_CTL */
3480 reg = TRANS_DP_CTL(pipe);
3481 temp = I915_READ(reg);
3482 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3483 TRANS_DP_PORT_SEL_MASK);
3484 temp |= TRANS_DP_PORT_SEL_NONE;
3485 I915_WRITE(reg, temp);
3487 /* disable DPLL_SEL */
3488 temp = I915_READ(PCH_DPLL_SEL);
3489 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3490 I915_WRITE(PCH_DPLL_SEL, temp);
3493 /* disable PCH DPLL */
3494 intel_disable_shared_dpll(intel_crtc);
3496 ironlake_fdi_pll_disable(intel_crtc);
3499 intel_crtc->active = false;
3500 intel_update_watermarks(dev);
3502 mutex_lock(&dev->struct_mutex);
3503 intel_update_fbc(dev);
3504 mutex_unlock(&dev->struct_mutex);
3507 static void haswell_crtc_disable(struct drm_crtc *crtc)
3509 struct drm_device *dev = crtc->dev;
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3512 struct intel_encoder *encoder;
3513 int pipe = intel_crtc->pipe;
3514 int plane = intel_crtc->plane;
3515 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3517 if (!intel_crtc->active)
3520 for_each_encoder_on_crtc(dev, crtc, encoder)
3521 encoder->disable(encoder);
3523 intel_crtc_wait_for_pending_flips(crtc);
3524 drm_vblank_off(dev, pipe);
3526 /* FBC must be disabled before disabling the plane on HSW. */
3527 if (dev_priv->fbc.plane == plane)
3528 intel_disable_fbc(dev);
3530 hsw_disable_ips(intel_crtc);
3532 intel_crtc_update_cursor(crtc, false);
3533 intel_disable_planes(crtc);
3534 intel_disable_plane(dev_priv, plane, pipe);
3536 if (intel_crtc->config.has_pch_encoder)
3537 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3538 intel_disable_pipe(dev_priv, pipe);
3540 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3542 ironlake_pfit_disable(intel_crtc);
3544 intel_ddi_disable_pipe_clock(intel_crtc);
3546 for_each_encoder_on_crtc(dev, crtc, encoder)
3547 if (encoder->post_disable)
3548 encoder->post_disable(encoder);
3550 if (intel_crtc->config.has_pch_encoder) {
3551 lpt_disable_pch_transcoder(dev_priv);
3552 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3553 intel_ddi_fdi_disable(crtc);
3556 intel_crtc->active = false;
3557 intel_update_watermarks(dev);
3559 mutex_lock(&dev->struct_mutex);
3560 intel_update_fbc(dev);
3561 mutex_unlock(&dev->struct_mutex);
3564 static void ironlake_crtc_off(struct drm_crtc *crtc)
3566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567 intel_put_shared_dpll(intel_crtc);
3570 static void haswell_crtc_off(struct drm_crtc *crtc)
3572 intel_ddi_put_crtc_pll(crtc);
3575 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3577 if (!enable && intel_crtc->overlay) {
3578 struct drm_device *dev = intel_crtc->base.dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3581 mutex_lock(&dev->struct_mutex);
3582 dev_priv->mm.interruptible = false;
3583 (void) intel_overlay_switch_off(intel_crtc->overlay);
3584 dev_priv->mm.interruptible = true;
3585 mutex_unlock(&dev->struct_mutex);
3588 /* Let userspace switch the overlay on again. In most cases userspace
3589 * has to recompute where to put it anyway.
3594 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3595 * cursor plane briefly if not already running after enabling the display
3597 * This workaround avoids occasional blank screens when self refresh is
3601 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3603 u32 cntl = I915_READ(CURCNTR(pipe));
3605 if ((cntl & CURSOR_MODE) == 0) {
3606 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3608 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3609 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3610 intel_wait_for_vblank(dev_priv->dev, pipe);
3611 I915_WRITE(CURCNTR(pipe), cntl);
3612 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3613 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3617 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3619 struct drm_device *dev = crtc->base.dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc_config *pipe_config = &crtc->config;
3623 if (!crtc->config.gmch_pfit.control)
3627 * The panel fitter should only be adjusted whilst the pipe is disabled,
3628 * according to register description and PRM.
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3633 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3634 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3636 /* Border color in case we don't scale up to the full screen. Black by
3637 * default, change to something else for debugging. */
3638 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3641 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3643 struct drm_device *dev = crtc->dev;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_encoder *encoder;
3647 int pipe = intel_crtc->pipe;
3648 int plane = intel_crtc->plane;
3650 WARN_ON(!crtc->enabled);
3652 if (intel_crtc->active)
3655 intel_crtc->active = true;
3656 intel_update_watermarks(dev);
3658 for_each_encoder_on_crtc(dev, crtc, encoder)
3659 if (encoder->pre_pll_enable)
3660 encoder->pre_pll_enable(encoder);
3662 vlv_enable_pll(intel_crtc);
3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 if (encoder->pre_enable)
3666 encoder->pre_enable(encoder);
3668 i9xx_pfit_enable(intel_crtc);
3670 intel_crtc_load_lut(crtc);
3672 intel_enable_pipe(dev_priv, pipe, false);
3673 intel_enable_plane(dev_priv, plane, pipe);
3674 intel_enable_planes(crtc);
3675 intel_crtc_update_cursor(crtc, true);
3677 intel_update_fbc(dev);
3679 for_each_encoder_on_crtc(dev, crtc, encoder)
3680 encoder->enable(encoder);
3683 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3685 struct drm_device *dev = crtc->dev;
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688 struct intel_encoder *encoder;
3689 int pipe = intel_crtc->pipe;
3690 int plane = intel_crtc->plane;
3692 WARN_ON(!crtc->enabled);
3694 if (intel_crtc->active)
3697 intel_crtc->active = true;
3698 intel_update_watermarks(dev);
3700 for_each_encoder_on_crtc(dev, crtc, encoder)
3701 if (encoder->pre_enable)
3702 encoder->pre_enable(encoder);
3704 i9xx_enable_pll(intel_crtc);
3706 i9xx_pfit_enable(intel_crtc);
3708 intel_crtc_load_lut(crtc);
3710 intel_enable_pipe(dev_priv, pipe, false);
3711 intel_enable_plane(dev_priv, plane, pipe);
3712 intel_enable_planes(crtc);
3713 /* The fixup needs to happen before cursor is enabled */
3715 g4x_fixup_plane(dev_priv, pipe);
3716 intel_crtc_update_cursor(crtc, true);
3718 /* Give the overlay scaler a chance to enable if it's on this pipe */
3719 intel_crtc_dpms_overlay(intel_crtc, true);
3721 intel_update_fbc(dev);
3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->enable(encoder);
3727 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3732 if (!crtc->config.gmch_pfit.control)
3735 assert_pipe_disabled(dev_priv, crtc->pipe);
3737 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3738 I915_READ(PFIT_CONTROL));
3739 I915_WRITE(PFIT_CONTROL, 0);
3742 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3744 struct drm_device *dev = crtc->dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3747 struct intel_encoder *encoder;
3748 int pipe = intel_crtc->pipe;
3749 int plane = intel_crtc->plane;
3751 if (!intel_crtc->active)
3754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 encoder->disable(encoder);
3757 /* Give the overlay scaler a chance to disable if it's on this pipe */
3758 intel_crtc_wait_for_pending_flips(crtc);
3759 drm_vblank_off(dev, pipe);
3761 if (dev_priv->fbc.plane == plane)
3762 intel_disable_fbc(dev);
3764 intel_crtc_dpms_overlay(intel_crtc, false);
3765 intel_crtc_update_cursor(crtc, false);
3766 intel_disable_planes(crtc);
3767 intel_disable_plane(dev_priv, plane, pipe);
3769 intel_disable_pipe(dev_priv, pipe);
3771 i9xx_pfit_disable(intel_crtc);
3773 for_each_encoder_on_crtc(dev, crtc, encoder)
3774 if (encoder->post_disable)
3775 encoder->post_disable(encoder);
3777 i9xx_disable_pll(dev_priv, pipe);
3779 intel_crtc->active = false;
3780 intel_update_fbc(dev);
3781 intel_update_watermarks(dev);
3784 static void i9xx_crtc_off(struct drm_crtc *crtc)
3788 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_master_private *master_priv;
3793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3794 int pipe = intel_crtc->pipe;
3796 if (!dev->primary->master)
3799 master_priv = dev->primary->master->driver_priv;
3800 if (!master_priv->sarea_priv)
3805 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3806 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3809 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3813 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3819 * Sets the power management mode of the pipe and plane.
3821 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 struct intel_encoder *intel_encoder;
3826 bool enable = false;
3828 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3829 enable |= intel_encoder->connectors_active;
3832 dev_priv->display.crtc_enable(crtc);
3834 dev_priv->display.crtc_disable(crtc);
3836 intel_crtc_update_sarea(crtc, enable);
3839 static void intel_crtc_disable(struct drm_crtc *crtc)
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_connector *connector;
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846 /* crtc should still be enabled when we disable it. */
3847 WARN_ON(!crtc->enabled);
3849 dev_priv->display.crtc_disable(crtc);
3850 intel_crtc->eld_vld = false;
3851 intel_crtc_update_sarea(crtc, false);
3852 dev_priv->display.off(crtc);
3854 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3855 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3858 mutex_lock(&dev->struct_mutex);
3859 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3860 mutex_unlock(&dev->struct_mutex);
3864 /* Update computed state. */
3865 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3866 if (!connector->encoder || !connector->encoder->crtc)
3869 if (connector->encoder->crtc != crtc)
3872 connector->dpms = DRM_MODE_DPMS_OFF;
3873 to_intel_encoder(connector->encoder)->connectors_active = false;
3877 void intel_encoder_destroy(struct drm_encoder *encoder)
3879 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3881 drm_encoder_cleanup(encoder);
3882 kfree(intel_encoder);
3885 /* Simple dpms helper for encoders with just one connector, no cloning and only
3886 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3887 * state of the entire output pipe. */
3888 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3890 if (mode == DRM_MODE_DPMS_ON) {
3891 encoder->connectors_active = true;
3893 intel_crtc_update_dpms(encoder->base.crtc);
3895 encoder->connectors_active = false;
3897 intel_crtc_update_dpms(encoder->base.crtc);
3901 /* Cross check the actual hw state with our own modeset state tracking (and it's
3902 * internal consistency). */
3903 static void intel_connector_check_state(struct intel_connector *connector)
3905 if (connector->get_hw_state(connector)) {
3906 struct intel_encoder *encoder = connector->encoder;
3907 struct drm_crtc *crtc;
3908 bool encoder_enabled;
3911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3912 connector->base.base.id,
3913 drm_get_connector_name(&connector->base));
3915 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3916 "wrong connector dpms state\n");
3917 WARN(connector->base.encoder != &encoder->base,
3918 "active connector not linked to encoder\n");
3919 WARN(!encoder->connectors_active,
3920 "encoder->connectors_active not set\n");
3922 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3923 WARN(!encoder_enabled, "encoder not enabled\n");
3924 if (WARN_ON(!encoder->base.crtc))
3927 crtc = encoder->base.crtc;
3929 WARN(!crtc->enabled, "crtc not enabled\n");
3930 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3931 WARN(pipe != to_intel_crtc(crtc)->pipe,
3932 "encoder active on the wrong pipe\n");
3936 /* Even simpler default implementation, if there's really no special case to
3938 void intel_connector_dpms(struct drm_connector *connector, int mode)
3940 struct intel_encoder *encoder = intel_attached_encoder(connector);
3942 /* All the simple cases only support two dpms states. */
3943 if (mode != DRM_MODE_DPMS_ON)
3944 mode = DRM_MODE_DPMS_OFF;
3946 if (mode == connector->dpms)
3949 connector->dpms = mode;
3951 /* Only need to change hw state when actually enabled */
3952 if (encoder->base.crtc)
3953 intel_encoder_dpms(encoder, mode);
3955 WARN_ON(encoder->connectors_active != false);
3957 intel_modeset_check_state(connector->dev);
3960 /* Simple connector->get_hw_state implementation for encoders that support only
3961 * one connector and no cloning and hence the encoder state determines the state
3962 * of the connector. */
3963 bool intel_connector_get_hw_state(struct intel_connector *connector)
3966 struct intel_encoder *encoder = connector->encoder;
3968 return encoder->get_hw_state(encoder, &pipe);
3971 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3972 struct intel_crtc_config *pipe_config)
3974 struct drm_i915_private *dev_priv = dev->dev_private;
3975 struct intel_crtc *pipe_B_crtc =
3976 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3978 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3979 pipe_name(pipe), pipe_config->fdi_lanes);
3980 if (pipe_config->fdi_lanes > 4) {
3981 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3982 pipe_name(pipe), pipe_config->fdi_lanes);
3986 if (IS_HASWELL(dev)) {
3987 if (pipe_config->fdi_lanes > 2) {
3988 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3989 pipe_config->fdi_lanes);
3996 if (INTEL_INFO(dev)->num_pipes == 2)
3999 /* Ivybridge 3 pipe is really complicated */
4004 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4005 pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4012 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4013 pipe_B_crtc->config.fdi_lanes <= 2) {
4014 if (pipe_config->fdi_lanes > 2) {
4015 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4016 pipe_name(pipe), pipe_config->fdi_lanes);
4020 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4030 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4031 struct intel_crtc_config *pipe_config)
4033 struct drm_device *dev = intel_crtc->base.dev;
4034 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4035 int lane, link_bw, fdi_dotclock;
4036 bool setup_ok, needs_recompute = false;
4039 /* FDI is a binary signal running at ~2.7GHz, encoding
4040 * each output octet as 10 bits. The actual frequency
4041 * is stored as a divider into a 100MHz clock, and the
4042 * mode pixel clock is stored in units of 1KHz.
4043 * Hence the bw of each lane in terms of the mode signal
4046 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4048 fdi_dotclock = adjusted_mode->clock;
4049 fdi_dotclock /= pipe_config->pixel_multiplier;
4051 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4052 pipe_config->pipe_bpp);
4054 pipe_config->fdi_lanes = lane;
4056 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4057 link_bw, &pipe_config->fdi_m_n);
4059 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4060 intel_crtc->pipe, pipe_config);
4061 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4062 pipe_config->pipe_bpp -= 2*3;
4063 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4064 pipe_config->pipe_bpp);
4065 needs_recompute = true;
4066 pipe_config->bw_constrained = true;
4071 if (needs_recompute)
4074 return setup_ok ? 0 : -EINVAL;
4077 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4078 struct intel_crtc_config *pipe_config)
4080 pipe_config->ips_enabled = i915_enable_ips &&
4081 hsw_crtc_supports_ips(crtc) &&
4082 pipe_config->pipe_bpp <= 24;
4085 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4086 struct intel_crtc_config *pipe_config)
4088 struct drm_device *dev = crtc->base.dev;
4089 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4091 if (HAS_PCH_SPLIT(dev)) {
4092 /* FDI link clock is fixed at 2.7G */
4093 if (pipe_config->requested_mode.clock * 3
4094 > IRONLAKE_FDI_FREQ * 4)
4098 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4099 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4101 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4102 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4105 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4106 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4107 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4108 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4110 pipe_config->pipe_bpp = 8*3;
4114 hsw_compute_ips_config(crtc, pipe_config);
4116 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4117 * clock survives for now. */
4118 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4119 pipe_config->shared_dpll = crtc->config.shared_dpll;
4121 if (pipe_config->has_pch_encoder)
4122 return ironlake_fdi_compute_config(crtc, pipe_config);
4127 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4129 return 400000; /* FIXME */
4132 static int i945_get_display_clock_speed(struct drm_device *dev)
4137 static int i915_get_display_clock_speed(struct drm_device *dev)
4142 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4147 static int pnv_get_display_clock_speed(struct drm_device *dev)
4151 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4156 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4158 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4160 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4163 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4164 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4166 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4171 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4175 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4177 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4180 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4181 case GC_DISPLAY_CLOCK_333_MHZ:
4184 case GC_DISPLAY_CLOCK_190_200_MHZ:
4190 static int i865_get_display_clock_speed(struct drm_device *dev)
4195 static int i855_get_display_clock_speed(struct drm_device *dev)
4198 /* Assume that the hardware is in the high speed state. This
4199 * should be the default.
4201 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4202 case GC_CLOCK_133_200:
4203 case GC_CLOCK_100_200:
4205 case GC_CLOCK_166_250:
4207 case GC_CLOCK_100_133:
4211 /* Shouldn't happen */
4215 static int i830_get_display_clock_speed(struct drm_device *dev)
4221 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4223 while (*num > DATA_LINK_M_N_MASK ||
4224 *den > DATA_LINK_M_N_MASK) {
4230 static void compute_m_n(unsigned int m, unsigned int n,
4231 uint32_t *ret_m, uint32_t *ret_n)
4233 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4234 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4235 intel_reduce_m_n_ratio(ret_m, ret_n);
4239 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4240 int pixel_clock, int link_clock,
4241 struct intel_link_m_n *m_n)
4245 compute_m_n(bits_per_pixel * pixel_clock,
4246 link_clock * nlanes * 8,
4247 &m_n->gmch_m, &m_n->gmch_n);
4249 compute_m_n(pixel_clock, link_clock,
4250 &m_n->link_m, &m_n->link_n);
4253 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4255 if (i915_panel_use_ssc >= 0)
4256 return i915_panel_use_ssc != 0;
4257 return dev_priv->vbt.lvds_use_ssc
4258 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4261 static int vlv_get_refclk(struct drm_crtc *crtc)
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 int refclk = 27000; /* for DP & HDMI */
4267 return 100000; /* only one validated so far */
4269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4271 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4272 if (intel_panel_use_ssc(dev_priv))
4276 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4283 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4289 if (IS_VALLEYVIEW(dev)) {
4290 refclk = vlv_get_refclk(crtc);
4291 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4292 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4293 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4294 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4296 } else if (!IS_GEN2(dev)) {
4305 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4307 return (1 << dpll->n) << 16 | dpll->m2;
4310 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4312 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4315 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4316 intel_clock_t *reduced_clock)
4318 struct drm_device *dev = crtc->base.dev;
4319 struct drm_i915_private *dev_priv = dev->dev_private;
4320 int pipe = crtc->pipe;
4323 if (IS_PINEVIEW(dev)) {
4324 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4326 fp2 = pnv_dpll_compute_fp(reduced_clock);
4328 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4330 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4333 I915_WRITE(FP0(pipe), fp);
4334 crtc->config.dpll_hw_state.fp0 = fp;
4336 crtc->lowfreq_avail = false;
4337 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4338 reduced_clock && i915_powersave) {
4339 I915_WRITE(FP1(pipe), fp2);
4340 crtc->config.dpll_hw_state.fp1 = fp2;
4341 crtc->lowfreq_avail = true;
4343 I915_WRITE(FP1(pipe), fp);
4344 crtc->config.dpll_hw_state.fp1 = fp;
4348 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4353 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4354 * and set it to a reasonable value instead.
4356 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4357 reg_val &= 0xffffff00;
4358 reg_val |= 0x00000030;
4359 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4361 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4362 reg_val &= 0x8cffffff;
4363 reg_val = 0x8c000000;
4364 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4366 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4367 reg_val &= 0xffffff00;
4368 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4370 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4371 reg_val &= 0x00ffffff;
4372 reg_val |= 0xb0000000;
4373 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4376 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4377 struct intel_link_m_n *m_n)
4379 struct drm_device *dev = crtc->base.dev;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381 int pipe = crtc->pipe;
4383 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4385 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4386 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4389 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4390 struct intel_link_m_n *m_n)
4392 struct drm_device *dev = crtc->base.dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 int pipe = crtc->pipe;
4395 enum transcoder transcoder = crtc->config.cpu_transcoder;
4397 if (INTEL_INFO(dev)->gen >= 5) {
4398 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4399 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4400 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4401 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4403 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4404 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4405 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4406 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4410 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4412 if (crtc->config.has_pch_encoder)
4413 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4415 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4418 static void vlv_update_pll(struct intel_crtc *crtc)
4420 struct drm_device *dev = crtc->base.dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 int pipe = crtc->pipe;
4424 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4425 u32 coreclk, reg_val, dpll_md;
4427 mutex_lock(&dev_priv->dpio_lock);
4429 bestn = crtc->config.dpll.n;
4430 bestm1 = crtc->config.dpll.m1;
4431 bestm2 = crtc->config.dpll.m2;
4432 bestp1 = crtc->config.dpll.p1;
4433 bestp2 = crtc->config.dpll.p2;
4435 /* See eDP HDMI DPIO driver vbios notes doc */
4437 /* PLL B needs special handling */
4439 vlv_pllb_recal_opamp(dev_priv);
4441 /* Set up Tx target for periodic Rcomp update */
4442 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4444 /* Disable target IRef on PLL */
4445 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4446 reg_val &= 0x00ffffff;
4447 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4449 /* Disable fast lock */
4450 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4452 /* Set idtafcrecal before PLL is enabled */
4453 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4454 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4455 mdiv |= ((bestn << DPIO_N_SHIFT));
4456 mdiv |= (1 << DPIO_K_SHIFT);
4459 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4460 * but we don't support that).
4461 * Note: don't use the DAC post divider as it seems unstable.
4463 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4464 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4466 mdiv |= DPIO_ENABLE_CALIBRATION;
4467 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4469 /* Set HBR and RBR LPF coefficients */
4470 if (crtc->config.port_clock == 162000 ||
4471 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4472 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4473 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4476 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4479 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4481 /* Use SSC source */
4483 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4486 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488 } else { /* HDMI or VGA */
4489 /* Use bend source */
4491 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4494 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4498 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4499 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4500 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4501 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4502 coreclk |= 0x01000000;
4503 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4505 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4507 /* Enable DPIO clock input */
4508 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4509 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4511 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4513 dpll |= DPLL_VCO_ENABLE;
4514 crtc->config.dpll_hw_state.dpll = dpll;
4516 dpll_md = (crtc->config.pixel_multiplier - 1)
4517 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4518 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4520 if (crtc->config.has_dp_encoder)
4521 intel_dp_set_m_n(crtc);
4523 mutex_unlock(&dev_priv->dpio_lock);
4526 static void i9xx_update_pll(struct intel_crtc *crtc,
4527 intel_clock_t *reduced_clock,
4530 struct drm_device *dev = crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4534 struct dpll *clock = &crtc->config.dpll;
4536 i9xx_update_pll_dividers(crtc, reduced_clock);
4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4541 dpll = DPLL_VGA_MODE_DIS;
4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4544 dpll |= DPLLB_MODE_LVDS;
4546 dpll |= DPLLB_MODE_DAC_SERIAL;
4548 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4549 dpll |= (crtc->config.pixel_multiplier - 1)
4550 << SDVO_MULTIPLIER_SHIFT_HIRES;
4554 dpll |= DPLL_SDVO_HIGH_SPEED;
4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4557 dpll |= DPLL_SDVO_HIGH_SPEED;
4559 /* compute bitmask from p1 value */
4560 if (IS_PINEVIEW(dev))
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564 if (IS_G4X(dev) && reduced_clock)
4565 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4567 switch (clock->p2) {
4569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4581 if (INTEL_INFO(dev)->gen >= 4)
4582 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4584 if (crtc->config.sdvo_tv_clock)
4585 dpll |= PLL_REF_INPUT_TVCLKINBC;
4586 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4590 dpll |= PLL_REF_INPUT_DREFCLK;
4592 dpll |= DPLL_VCO_ENABLE;
4593 crtc->config.dpll_hw_state.dpll = dpll;
4595 if (INTEL_INFO(dev)->gen >= 4) {
4596 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4597 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4598 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4601 if (crtc->config.has_dp_encoder)
4602 intel_dp_set_m_n(crtc);
4605 static void i8xx_update_pll(struct intel_crtc *crtc,
4606 intel_clock_t *reduced_clock,
4609 struct drm_device *dev = crtc->base.dev;
4610 struct drm_i915_private *dev_priv = dev->dev_private;
4612 struct dpll *clock = &crtc->config.dpll;
4614 i9xx_update_pll_dividers(crtc, reduced_clock);
4616 dpll = DPLL_VGA_MODE_DIS;
4618 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4622 dpll |= PLL_P1_DIVIDE_BY_TWO;
4624 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4626 dpll |= PLL_P2_DIVIDE_BY_4;
4629 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4630 dpll |= DPLL_DVO_2X_MODE;
4632 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4633 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4634 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4636 dpll |= PLL_REF_INPUT_DREFCLK;
4638 dpll |= DPLL_VCO_ENABLE;
4639 crtc->config.dpll_hw_state.dpll = dpll;
4642 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4644 struct drm_device *dev = intel_crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 enum pipe pipe = intel_crtc->pipe;
4647 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4648 struct drm_display_mode *adjusted_mode =
4649 &intel_crtc->config.adjusted_mode;
4650 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4651 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4653 /* We need to be careful not to changed the adjusted mode, for otherwise
4654 * the hw state checker will get angry at the mismatch. */
4655 crtc_vtotal = adjusted_mode->crtc_vtotal;
4656 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4658 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4659 /* the chip adds 2 halflines automatically */
4661 crtc_vblank_end -= 1;
4662 vsyncshift = adjusted_mode->crtc_hsync_start
4663 - adjusted_mode->crtc_htotal / 2;
4668 if (INTEL_INFO(dev)->gen > 3)
4669 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4671 I915_WRITE(HTOTAL(cpu_transcoder),
4672 (adjusted_mode->crtc_hdisplay - 1) |
4673 ((adjusted_mode->crtc_htotal - 1) << 16));
4674 I915_WRITE(HBLANK(cpu_transcoder),
4675 (adjusted_mode->crtc_hblank_start - 1) |
4676 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4677 I915_WRITE(HSYNC(cpu_transcoder),
4678 (adjusted_mode->crtc_hsync_start - 1) |
4679 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4681 I915_WRITE(VTOTAL(cpu_transcoder),
4682 (adjusted_mode->crtc_vdisplay - 1) |
4683 ((crtc_vtotal - 1) << 16));
4684 I915_WRITE(VBLANK(cpu_transcoder),
4685 (adjusted_mode->crtc_vblank_start - 1) |
4686 ((crtc_vblank_end - 1) << 16));
4687 I915_WRITE(VSYNC(cpu_transcoder),
4688 (adjusted_mode->crtc_vsync_start - 1) |
4689 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4691 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4692 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4693 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4695 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4696 (pipe == PIPE_B || pipe == PIPE_C))
4697 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4699 /* pipesrc controls the size that is scaled from, which should
4700 * always be the user's requested size.
4702 I915_WRITE(PIPESRC(pipe),
4703 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4706 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4707 struct intel_crtc_config *pipe_config)
4709 struct drm_device *dev = crtc->base.dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4714 tmp = I915_READ(HTOTAL(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4717 tmp = I915_READ(HBLANK(cpu_transcoder));
4718 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4719 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4720 tmp = I915_READ(HSYNC(cpu_transcoder));
4721 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4722 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4724 tmp = I915_READ(VTOTAL(cpu_transcoder));
4725 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4726 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4727 tmp = I915_READ(VBLANK(cpu_transcoder));
4728 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4729 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4730 tmp = I915_READ(VSYNC(cpu_transcoder));
4731 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4732 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4734 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4735 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4736 pipe_config->adjusted_mode.crtc_vtotal += 1;
4737 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4740 tmp = I915_READ(PIPESRC(crtc->pipe));
4741 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4742 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4745 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4746 struct intel_crtc_config *pipe_config)
4748 struct drm_crtc *crtc = &intel_crtc->base;
4750 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4751 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4752 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4753 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4755 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4756 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4757 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4758 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4760 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4762 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4763 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4766 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4768 struct drm_device *dev = intel_crtc->base.dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4774 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4775 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4778 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4781 if (intel_crtc->config.requested_mode.clock >
4782 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4783 pipeconf |= PIPECONF_DOUBLE_WIDE;
4786 /* only g4x and later have fancy bpc/dither controls */
4787 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4788 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4789 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4790 pipeconf |= PIPECONF_DITHER_EN |
4791 PIPECONF_DITHER_TYPE_SP;
4793 switch (intel_crtc->config.pipe_bpp) {
4795 pipeconf |= PIPECONF_6BPC;
4798 pipeconf |= PIPECONF_8BPC;
4801 pipeconf |= PIPECONF_10BPC;
4804 /* Case prevented by intel_choose_pipe_bpp_dither. */
4809 if (HAS_PIPE_CXSR(dev)) {
4810 if (intel_crtc->lowfreq_avail) {
4811 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4812 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4814 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4818 if (!IS_GEN2(dev) &&
4819 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4820 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4822 pipeconf |= PIPECONF_PROGRESSIVE;
4824 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4825 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4827 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4828 POSTING_READ(PIPECONF(intel_crtc->pipe));
4831 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4833 struct drm_framebuffer *fb)
4835 struct drm_device *dev = crtc->dev;
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4838 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4839 int pipe = intel_crtc->pipe;
4840 int plane = intel_crtc->plane;
4841 int refclk, num_connectors = 0;
4842 intel_clock_t clock, reduced_clock;
4844 bool ok, has_reduced_clock = false;
4845 bool is_lvds = false;
4846 struct intel_encoder *encoder;
4847 const intel_limit_t *limit;
4850 for_each_encoder_on_crtc(dev, crtc, encoder) {
4851 switch (encoder->type) {
4852 case INTEL_OUTPUT_LVDS:
4860 refclk = i9xx_get_refclk(crtc, num_connectors);
4863 * Returns a set of divisors for the desired target clock with the given
4864 * refclk, or FALSE. The returned values represent the clock equation:
4865 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4867 limit = intel_limit(crtc, refclk);
4868 ok = dev_priv->display.find_dpll(limit, crtc,
4869 intel_crtc->config.port_clock,
4870 refclk, NULL, &clock);
4871 if (!ok && !intel_crtc->config.clock_set) {
4872 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4876 /* Ensure that the cursor is valid for the new mode before changing... */
4877 intel_crtc_update_cursor(crtc, true);
4879 if (is_lvds && dev_priv->lvds_downclock_avail) {
4881 * Ensure we match the reduced clock's P to the target clock.
4882 * If the clocks don't match, we can't switch the display clock
4883 * by using the FP0/FP1. In such case we will disable the LVDS
4884 * downclock feature.
4887 dev_priv->display.find_dpll(limit, crtc,
4888 dev_priv->lvds_downclock,
4892 /* Compat-code for transition, will disappear. */
4893 if (!intel_crtc->config.clock_set) {
4894 intel_crtc->config.dpll.n = clock.n;
4895 intel_crtc->config.dpll.m1 = clock.m1;
4896 intel_crtc->config.dpll.m2 = clock.m2;
4897 intel_crtc->config.dpll.p1 = clock.p1;
4898 intel_crtc->config.dpll.p2 = clock.p2;
4902 i8xx_update_pll(intel_crtc,
4903 has_reduced_clock ? &reduced_clock : NULL,
4905 else if (IS_VALLEYVIEW(dev))
4906 vlv_update_pll(intel_crtc);
4908 i9xx_update_pll(intel_crtc,
4909 has_reduced_clock ? &reduced_clock : NULL,
4912 /* Set up the display plane register */
4913 dspcntr = DISPPLANE_GAMMA_ENABLE;
4915 if (!IS_VALLEYVIEW(dev)) {
4917 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919 dspcntr |= DISPPLANE_SEL_PIPE_B;
4922 intel_set_pipe_timings(intel_crtc);
4924 /* pipesrc and dspsize control the size that is scaled from,
4925 * which should always be the user's requested size.
4927 I915_WRITE(DSPSIZE(plane),
4928 ((mode->vdisplay - 1) << 16) |
4929 (mode->hdisplay - 1));
4930 I915_WRITE(DSPPOS(plane), 0);
4932 i9xx_set_pipeconf(intel_crtc);
4934 I915_WRITE(DSPCNTR(plane), dspcntr);
4935 POSTING_READ(DSPCNTR(plane));
4937 ret = intel_pipe_set_base(crtc, x, y, fb);
4939 intel_update_watermarks(dev);
4944 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4945 struct intel_crtc_config *pipe_config)
4947 struct drm_device *dev = crtc->base.dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4951 tmp = I915_READ(PFIT_CONTROL);
4952 if (!(tmp & PFIT_ENABLE))
4955 /* Check whether the pfit is attached to our pipe. */
4956 if (INTEL_INFO(dev)->gen < 4) {
4957 if (crtc->pipe != PIPE_B)
4960 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4964 pipe_config->gmch_pfit.control = tmp;
4965 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4966 if (INTEL_INFO(dev)->gen < 5)
4967 pipe_config->gmch_pfit.lvds_border_bits =
4968 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4971 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4972 struct intel_crtc_config *pipe_config)
4974 struct drm_device *dev = crtc->base.dev;
4975 struct drm_i915_private *dev_priv = dev->dev_private;
4978 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4979 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4981 tmp = I915_READ(PIPECONF(crtc->pipe));
4982 if (!(tmp & PIPECONF_ENABLE))
4985 intel_get_pipe_timings(crtc, pipe_config);
4987 i9xx_get_pfit_config(crtc, pipe_config);
4989 if (INTEL_INFO(dev)->gen >= 4) {
4990 tmp = I915_READ(DPLL_MD(crtc->pipe));
4991 pipe_config->pixel_multiplier =
4992 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4993 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4994 pipe_config->dpll_hw_state.dpll_md = tmp;
4995 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4996 tmp = I915_READ(DPLL(crtc->pipe));
4997 pipe_config->pixel_multiplier =
4998 ((tmp & SDVO_MULTIPLIER_MASK)
4999 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5001 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5002 * port and will be fixed up in the encoder->get_config
5004 pipe_config->pixel_multiplier = 1;
5006 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5007 if (!IS_VALLEYVIEW(dev)) {
5008 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5009 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5011 /* Mask out read-only status bits. */
5012 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5013 DPLL_PORTC_READY_MASK |
5014 DPLL_PORTB_READY_MASK);
5020 static void ironlake_init_pch_refclk(struct drm_device *dev)
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023 struct drm_mode_config *mode_config = &dev->mode_config;
5024 struct intel_encoder *encoder;
5026 bool has_lvds = false;
5027 bool has_cpu_edp = false;
5028 bool has_panel = false;
5029 bool has_ck505 = false;
5030 bool can_ssc = false;
5032 /* We need to take the global config into account */
5033 list_for_each_entry(encoder, &mode_config->encoder_list,
5035 switch (encoder->type) {
5036 case INTEL_OUTPUT_LVDS:
5040 case INTEL_OUTPUT_EDP:
5042 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5048 if (HAS_PCH_IBX(dev)) {
5049 has_ck505 = dev_priv->vbt.display_clock_mode;
5050 can_ssc = has_ck505;
5056 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5057 has_panel, has_lvds, has_ck505);
5059 /* Ironlake: try to setup display ref clock before DPLL
5060 * enabling. This is only under driver's control after
5061 * PCH B stepping, previous chipset stepping should be
5062 * ignoring this setting.
5064 val = I915_READ(PCH_DREF_CONTROL);
5066 /* As we must carefully and slowly disable/enable each source in turn,
5067 * compute the final state we want first and check if we need to
5068 * make any changes at all.
5071 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5073 final |= DREF_NONSPREAD_CK505_ENABLE;
5075 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5077 final &= ~DREF_SSC_SOURCE_MASK;
5078 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5079 final &= ~DREF_SSC1_ENABLE;
5082 final |= DREF_SSC_SOURCE_ENABLE;
5084 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5085 final |= DREF_SSC1_ENABLE;
5088 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5093 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095 final |= DREF_SSC_SOURCE_DISABLE;
5096 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5102 /* Always enable nonspread source */
5103 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5106 val |= DREF_NONSPREAD_CK505_ENABLE;
5108 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5111 val &= ~DREF_SSC_SOURCE_MASK;
5112 val |= DREF_SSC_SOURCE_ENABLE;
5114 /* SSC must be turned on before enabling the CPU output */
5115 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5116 DRM_DEBUG_KMS("Using SSC on panel\n");
5117 val |= DREF_SSC1_ENABLE;
5119 val &= ~DREF_SSC1_ENABLE;
5121 /* Get SSC going before enabling the outputs */
5122 I915_WRITE(PCH_DREF_CONTROL, val);
5123 POSTING_READ(PCH_DREF_CONTROL);
5126 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5128 /* Enable CPU source on CPU attached eDP */
5130 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5131 DRM_DEBUG_KMS("Using SSC on eDP\n");
5132 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5135 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5137 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5139 I915_WRITE(PCH_DREF_CONTROL, val);
5140 POSTING_READ(PCH_DREF_CONTROL);
5143 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5145 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5147 /* Turn off CPU output */
5148 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5150 I915_WRITE(PCH_DREF_CONTROL, val);
5151 POSTING_READ(PCH_DREF_CONTROL);
5154 /* Turn off the SSC source */
5155 val &= ~DREF_SSC_SOURCE_MASK;
5156 val |= DREF_SSC_SOURCE_DISABLE;
5159 val &= ~DREF_SSC1_ENABLE;
5161 I915_WRITE(PCH_DREF_CONTROL, val);
5162 POSTING_READ(PCH_DREF_CONTROL);
5166 BUG_ON(val != final);
5169 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5173 tmp = I915_READ(SOUTH_CHICKEN2);
5174 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5175 I915_WRITE(SOUTH_CHICKEN2, tmp);
5177 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5178 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5179 DRM_ERROR("FDI mPHY reset assert timeout\n");
5181 tmp = I915_READ(SOUTH_CHICKEN2);
5182 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5183 I915_WRITE(SOUTH_CHICKEN2, tmp);
5185 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5186 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5187 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5190 /* WaMPhyProgramming:hsw */
5191 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5195 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5196 tmp &= ~(0xFF << 24);
5197 tmp |= (0x12 << 24);
5198 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5200 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5202 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5204 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5206 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5208 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5209 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5210 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5213 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5214 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5219 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5221 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5224 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5226 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5229 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5231 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5234 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5236 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5237 tmp &= ~(0xFF << 16);
5238 tmp |= (0x1C << 16);
5239 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5241 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5242 tmp &= ~(0xFF << 16);
5243 tmp |= (0x1C << 16);
5244 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5246 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5248 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5250 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5252 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5254 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5255 tmp &= ~(0xF << 28);
5257 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5259 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5260 tmp &= ~(0xF << 28);
5262 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5265 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5266 * Programming" based on the parameters passed:
5267 * - Sequence to enable CLKOUT_DP
5268 * - Sequence to enable CLKOUT_DP without spread
5269 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5271 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5277 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5279 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5280 with_fdi, "LP PCH doesn't have FDI\n"))
5283 mutex_lock(&dev_priv->dpio_lock);
5285 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5286 tmp &= ~SBI_SSCCTL_DISABLE;
5287 tmp |= SBI_SSCCTL_PATHALT;
5288 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5293 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5294 tmp &= ~SBI_SSCCTL_PATHALT;
5295 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5298 lpt_reset_fdi_mphy(dev_priv);
5299 lpt_program_fdi_mphy(dev_priv);
5303 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5304 SBI_GEN0 : SBI_DBUFF0;
5305 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5306 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5307 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5309 mutex_unlock(&dev_priv->dpio_lock);
5312 /* Sequence to disable CLKOUT_DP */
5313 static void lpt_disable_clkout_dp(struct drm_device *dev)
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5318 mutex_lock(&dev_priv->dpio_lock);
5320 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5321 SBI_GEN0 : SBI_DBUFF0;
5322 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5323 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5324 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5326 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5327 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5328 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5329 tmp |= SBI_SSCCTL_PATHALT;
5330 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5333 tmp |= SBI_SSCCTL_DISABLE;
5334 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5337 mutex_unlock(&dev_priv->dpio_lock);
5340 static void lpt_init_pch_refclk(struct drm_device *dev)
5342 struct drm_mode_config *mode_config = &dev->mode_config;
5343 struct intel_encoder *encoder;
5344 bool has_vga = false;
5346 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5347 switch (encoder->type) {
5348 case INTEL_OUTPUT_ANALOG:
5355 lpt_enable_clkout_dp(dev, true, true);
5357 lpt_disable_clkout_dp(dev);
5361 * Initialize reference clocks when the driver loads
5363 void intel_init_pch_refclk(struct drm_device *dev)
5365 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5366 ironlake_init_pch_refclk(dev);
5367 else if (HAS_PCH_LPT(dev))
5368 lpt_init_pch_refclk(dev);
5371 static int ironlake_get_refclk(struct drm_crtc *crtc)
5373 struct drm_device *dev = crtc->dev;
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct intel_encoder *encoder;
5376 int num_connectors = 0;
5377 bool is_lvds = false;
5379 for_each_encoder_on_crtc(dev, crtc, encoder) {
5380 switch (encoder->type) {
5381 case INTEL_OUTPUT_LVDS:
5388 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5389 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5390 dev_priv->vbt.lvds_ssc_freq);
5391 return dev_priv->vbt.lvds_ssc_freq * 1000;
5397 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5399 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401 int pipe = intel_crtc->pipe;
5406 switch (intel_crtc->config.pipe_bpp) {
5408 val |= PIPECONF_6BPC;
5411 val |= PIPECONF_8BPC;
5414 val |= PIPECONF_10BPC;
5417 val |= PIPECONF_12BPC;
5420 /* Case prevented by intel_choose_pipe_bpp_dither. */
5424 if (intel_crtc->config.dither)
5425 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5427 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5428 val |= PIPECONF_INTERLACED_ILK;
5430 val |= PIPECONF_PROGRESSIVE;
5432 if (intel_crtc->config.limited_color_range)
5433 val |= PIPECONF_COLOR_RANGE_SELECT;
5435 I915_WRITE(PIPECONF(pipe), val);
5436 POSTING_READ(PIPECONF(pipe));
5440 * Set up the pipe CSC unit.
5442 * Currently only full range RGB to limited range RGB conversion
5443 * is supported, but eventually this should handle various
5444 * RGB<->YCbCr scenarios as well.
5446 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5448 struct drm_device *dev = crtc->dev;
5449 struct drm_i915_private *dev_priv = dev->dev_private;
5450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5451 int pipe = intel_crtc->pipe;
5452 uint16_t coeff = 0x7800; /* 1.0 */
5455 * TODO: Check what kind of values actually come out of the pipe
5456 * with these coeff/postoff values and adjust to get the best
5457 * accuracy. Perhaps we even need to take the bpc value into
5461 if (intel_crtc->config.limited_color_range)
5462 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5465 * GY/GU and RY/RU should be the other way around according
5466 * to BSpec, but reality doesn't agree. Just set them up in
5467 * a way that results in the correct picture.
5469 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5470 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5472 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5473 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5475 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5476 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5478 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5479 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5480 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5482 if (INTEL_INFO(dev)->gen > 6) {
5483 uint16_t postoff = 0;
5485 if (intel_crtc->config.limited_color_range)
5486 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5488 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5489 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5490 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5492 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5494 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5496 if (intel_crtc->config.limited_color_range)
5497 mode |= CSC_BLACK_SCREEN_OFFSET;
5499 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5503 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5505 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5512 if (intel_crtc->config.dither)
5513 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5515 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5516 val |= PIPECONF_INTERLACED_ILK;
5518 val |= PIPECONF_PROGRESSIVE;
5520 I915_WRITE(PIPECONF(cpu_transcoder), val);
5521 POSTING_READ(PIPECONF(cpu_transcoder));
5523 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5524 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5527 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5528 intel_clock_t *clock,
5529 bool *has_reduced_clock,
5530 intel_clock_t *reduced_clock)
5532 struct drm_device *dev = crtc->dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 struct intel_encoder *intel_encoder;
5536 const intel_limit_t *limit;
5537 bool ret, is_lvds = false;
5539 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5540 switch (intel_encoder->type) {
5541 case INTEL_OUTPUT_LVDS:
5547 refclk = ironlake_get_refclk(crtc);
5550 * Returns a set of divisors for the desired target clock with the given
5551 * refclk, or FALSE. The returned values represent the clock equation:
5552 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5554 limit = intel_limit(crtc, refclk);
5555 ret = dev_priv->display.find_dpll(limit, crtc,
5556 to_intel_crtc(crtc)->config.port_clock,
5557 refclk, NULL, clock);
5561 if (is_lvds && dev_priv->lvds_downclock_avail) {
5563 * Ensure we match the reduced clock's P to the target clock.
5564 * If the clocks don't match, we can't switch the display clock
5565 * by using the FP0/FP1. In such case we will disable the LVDS
5566 * downclock feature.
5568 *has_reduced_clock =
5569 dev_priv->display.find_dpll(limit, crtc,
5570 dev_priv->lvds_downclock,
5578 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5583 temp = I915_READ(SOUTH_CHICKEN1);
5584 if (temp & FDI_BC_BIFURCATION_SELECT)
5587 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5588 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5590 temp |= FDI_BC_BIFURCATION_SELECT;
5591 DRM_DEBUG_KMS("enabling fdi C rx\n");
5592 I915_WRITE(SOUTH_CHICKEN1, temp);
5593 POSTING_READ(SOUTH_CHICKEN1);
5596 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5598 struct drm_device *dev = intel_crtc->base.dev;
5599 struct drm_i915_private *dev_priv = dev->dev_private;
5601 switch (intel_crtc->pipe) {
5605 if (intel_crtc->config.fdi_lanes > 2)
5606 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5608 cpt_enable_fdi_bc_bifurcation(dev);
5612 cpt_enable_fdi_bc_bifurcation(dev);
5620 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5623 * Account for spread spectrum to avoid
5624 * oversubscribing the link. Max center spread
5625 * is 2.5%; use 5% for safety's sake.
5627 u32 bps = target_clock * bpp * 21 / 20;
5628 return bps / (link_bw * 8) + 1;
5631 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5633 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5636 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5638 intel_clock_t *reduced_clock, u32 *fp2)
5640 struct drm_crtc *crtc = &intel_crtc->base;
5641 struct drm_device *dev = crtc->dev;
5642 struct drm_i915_private *dev_priv = dev->dev_private;
5643 struct intel_encoder *intel_encoder;
5645 int factor, num_connectors = 0;
5646 bool is_lvds = false, is_sdvo = false;
5648 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5649 switch (intel_encoder->type) {
5650 case INTEL_OUTPUT_LVDS:
5653 case INTEL_OUTPUT_SDVO:
5654 case INTEL_OUTPUT_HDMI:
5662 /* Enable autotuning of the PLL clock (if permissible) */
5665 if ((intel_panel_use_ssc(dev_priv) &&
5666 dev_priv->vbt.lvds_ssc_freq == 100) ||
5667 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5669 } else if (intel_crtc->config.sdvo_tv_clock)
5672 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5675 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5681 dpll |= DPLLB_MODE_LVDS;
5683 dpll |= DPLLB_MODE_DAC_SERIAL;
5685 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5686 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5689 dpll |= DPLL_SDVO_HIGH_SPEED;
5690 if (intel_crtc->config.has_dp_encoder)
5691 dpll |= DPLL_SDVO_HIGH_SPEED;
5693 /* compute bitmask from p1 value */
5694 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5696 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5698 switch (intel_crtc->config.dpll.p2) {
5700 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5703 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5706 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5709 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5713 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5714 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5716 dpll |= PLL_REF_INPUT_DREFCLK;
5718 return dpll | DPLL_VCO_ENABLE;
5721 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5723 struct drm_framebuffer *fb)
5725 struct drm_device *dev = crtc->dev;
5726 struct drm_i915_private *dev_priv = dev->dev_private;
5727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5728 int pipe = intel_crtc->pipe;
5729 int plane = intel_crtc->plane;
5730 int num_connectors = 0;
5731 intel_clock_t clock, reduced_clock;
5732 u32 dpll = 0, fp = 0, fp2 = 0;
5733 bool ok, has_reduced_clock = false;
5734 bool is_lvds = false;
5735 struct intel_encoder *encoder;
5736 struct intel_shared_dpll *pll;
5739 for_each_encoder_on_crtc(dev, crtc, encoder) {
5740 switch (encoder->type) {
5741 case INTEL_OUTPUT_LVDS:
5749 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5750 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5752 ok = ironlake_compute_clocks(crtc, &clock,
5753 &has_reduced_clock, &reduced_clock);
5754 if (!ok && !intel_crtc->config.clock_set) {
5755 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5758 /* Compat-code for transition, will disappear. */
5759 if (!intel_crtc->config.clock_set) {
5760 intel_crtc->config.dpll.n = clock.n;
5761 intel_crtc->config.dpll.m1 = clock.m1;
5762 intel_crtc->config.dpll.m2 = clock.m2;
5763 intel_crtc->config.dpll.p1 = clock.p1;
5764 intel_crtc->config.dpll.p2 = clock.p2;
5767 /* Ensure that the cursor is valid for the new mode before changing... */
5768 intel_crtc_update_cursor(crtc, true);
5770 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5771 if (intel_crtc->config.has_pch_encoder) {
5772 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5773 if (has_reduced_clock)
5774 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5776 dpll = ironlake_compute_dpll(intel_crtc,
5777 &fp, &reduced_clock,
5778 has_reduced_clock ? &fp2 : NULL);
5780 intel_crtc->config.dpll_hw_state.dpll = dpll;
5781 intel_crtc->config.dpll_hw_state.fp0 = fp;
5782 if (has_reduced_clock)
5783 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5785 intel_crtc->config.dpll_hw_state.fp1 = fp;
5787 pll = intel_get_shared_dpll(intel_crtc);
5789 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5794 intel_put_shared_dpll(intel_crtc);
5796 if (intel_crtc->config.has_dp_encoder)
5797 intel_dp_set_m_n(intel_crtc);
5799 if (is_lvds && has_reduced_clock && i915_powersave)
5800 intel_crtc->lowfreq_avail = true;
5802 intel_crtc->lowfreq_avail = false;
5804 if (intel_crtc->config.has_pch_encoder) {
5805 pll = intel_crtc_to_shared_dpll(intel_crtc);
5809 intel_set_pipe_timings(intel_crtc);
5811 if (intel_crtc->config.has_pch_encoder) {
5812 intel_cpu_transcoder_set_m_n(intel_crtc,
5813 &intel_crtc->config.fdi_m_n);
5816 if (IS_IVYBRIDGE(dev))
5817 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5819 ironlake_set_pipeconf(crtc);
5821 /* Set up the display plane register */
5822 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5823 POSTING_READ(DSPCNTR(plane));
5825 ret = intel_pipe_set_base(crtc, x, y, fb);
5827 intel_update_watermarks(dev);
5832 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5833 struct intel_crtc_config *pipe_config)
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 enum transcoder transcoder = pipe_config->cpu_transcoder;
5839 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5840 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5841 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5843 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5844 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5845 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5848 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5849 struct intel_crtc_config *pipe_config)
5851 struct drm_device *dev = crtc->base.dev;
5852 struct drm_i915_private *dev_priv = dev->dev_private;
5855 tmp = I915_READ(PF_CTL(crtc->pipe));
5857 if (tmp & PF_ENABLE) {
5858 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5859 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5861 /* We currently do not free assignements of panel fitters on
5862 * ivb/hsw (since we don't use the higher upscaling modes which
5863 * differentiates them) so just WARN about this case for now. */
5865 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5866 PF_PIPE_SEL_IVB(crtc->pipe));
5871 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5872 struct intel_crtc_config *pipe_config)
5874 struct drm_device *dev = crtc->base.dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5878 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5879 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5881 tmp = I915_READ(PIPECONF(crtc->pipe));
5882 if (!(tmp & PIPECONF_ENABLE))
5885 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5886 struct intel_shared_dpll *pll;
5888 pipe_config->has_pch_encoder = true;
5890 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5891 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5892 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5894 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5896 if (HAS_PCH_IBX(dev_priv->dev)) {
5897 pipe_config->shared_dpll =
5898 (enum intel_dpll_id) crtc->pipe;
5900 tmp = I915_READ(PCH_DPLL_SEL);
5901 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5902 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5907 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5909 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5910 &pipe_config->dpll_hw_state));
5912 tmp = pipe_config->dpll_hw_state.dpll;
5913 pipe_config->pixel_multiplier =
5914 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5915 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5917 pipe_config->pixel_multiplier = 1;
5920 intel_get_pipe_timings(crtc, pipe_config);
5922 ironlake_get_pfit_config(crtc, pipe_config);
5927 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5929 struct drm_device *dev = dev_priv->dev;
5930 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5931 struct intel_crtc *crtc;
5932 unsigned long irqflags;
5933 uint32_t val, pch_hpd_mask;
5935 pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5936 if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5937 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5939 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5940 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5941 pipe_name(crtc->pipe));
5943 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5944 WARN(plls->spll_refcount, "SPLL enabled\n");
5945 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5946 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5947 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5948 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5949 "CPU PWM1 enabled\n");
5950 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5951 "CPU PWM2 enabled\n");
5952 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5953 "PCH PWM1 enabled\n");
5954 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5955 "Utility pin enabled\n");
5956 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5958 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5959 val = I915_READ(DEIMR);
5960 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5961 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5962 val = I915_READ(SDEIMR);
5963 WARN((val & ~pch_hpd_mask) != val,
5964 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5965 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5969 * This function implements pieces of two sequences from BSpec:
5970 * - Sequence for display software to disable LCPLL
5971 * - Sequence for display software to allow package C8+
5972 * The steps implemented here are just the steps that actually touch the LCPLL
5973 * register. Callers should take care of disabling all the display engine
5974 * functions, doing the mode unset, fixing interrupts, etc.
5976 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5977 bool switch_to_fclk, bool allow_power_down)
5981 assert_can_disable_lcpll(dev_priv);
5983 val = I915_READ(LCPLL_CTL);
5985 if (switch_to_fclk) {
5986 val |= LCPLL_CD_SOURCE_FCLK;
5987 I915_WRITE(LCPLL_CTL, val);
5989 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5990 LCPLL_CD_SOURCE_FCLK_DONE, 1))
5991 DRM_ERROR("Switching to FCLK failed\n");
5993 val = I915_READ(LCPLL_CTL);
5996 val |= LCPLL_PLL_DISABLE;
5997 I915_WRITE(LCPLL_CTL, val);
5998 POSTING_READ(LCPLL_CTL);
6000 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6001 DRM_ERROR("LCPLL still locked\n");
6003 val = I915_READ(D_COMP);
6004 val |= D_COMP_COMP_DISABLE;
6005 I915_WRITE(D_COMP, val);
6006 POSTING_READ(D_COMP);
6009 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6010 DRM_ERROR("D_COMP RCOMP still in progress\n");
6012 if (allow_power_down) {
6013 val = I915_READ(LCPLL_CTL);
6014 val |= LCPLL_POWER_DOWN_ALLOW;
6015 I915_WRITE(LCPLL_CTL, val);
6016 POSTING_READ(LCPLL_CTL);
6021 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6024 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6028 val = I915_READ(LCPLL_CTL);
6030 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6031 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6034 if (val & LCPLL_POWER_DOWN_ALLOW) {
6035 val &= ~LCPLL_POWER_DOWN_ALLOW;
6036 I915_WRITE(LCPLL_CTL, val);
6039 val = I915_READ(D_COMP);
6040 val |= D_COMP_COMP_FORCE;
6041 val &= ~D_COMP_COMP_DISABLE;
6042 I915_WRITE(D_COMP, val);
6045 val = I915_READ(LCPLL_CTL);
6046 val &= ~LCPLL_PLL_DISABLE;
6047 I915_WRITE(LCPLL_CTL, val);
6049 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6050 DRM_ERROR("LCPLL not locked yet\n");
6052 if (val & LCPLL_CD_SOURCE_FCLK) {
6053 val = I915_READ(LCPLL_CTL);
6054 val &= ~LCPLL_CD_SOURCE_FCLK;
6055 I915_WRITE(LCPLL_CTL, val);
6057 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6058 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6059 DRM_ERROR("Switching back to LCPLL failed\n");
6063 static void haswell_modeset_global_resources(struct drm_device *dev)
6065 bool enable = false;
6066 struct intel_crtc *crtc;
6068 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6069 if (!crtc->base.enabled)
6072 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6073 crtc->config.cpu_transcoder != TRANSCODER_EDP)
6077 intel_set_power_well(dev, enable);
6080 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6082 struct drm_framebuffer *fb)
6084 struct drm_device *dev = crtc->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087 int plane = intel_crtc->plane;
6090 if (!intel_ddi_pll_mode_set(crtc))
6093 /* Ensure that the cursor is valid for the new mode before changing... */
6094 intel_crtc_update_cursor(crtc, true);
6096 if (intel_crtc->config.has_dp_encoder)
6097 intel_dp_set_m_n(intel_crtc);
6099 intel_crtc->lowfreq_avail = false;
6101 intel_set_pipe_timings(intel_crtc);
6103 if (intel_crtc->config.has_pch_encoder) {
6104 intel_cpu_transcoder_set_m_n(intel_crtc,
6105 &intel_crtc->config.fdi_m_n);
6108 haswell_set_pipeconf(crtc);
6110 intel_set_pipe_csc(crtc);
6112 /* Set up the display plane register */
6113 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6114 POSTING_READ(DSPCNTR(plane));
6116 ret = intel_pipe_set_base(crtc, x, y, fb);
6118 intel_update_watermarks(dev);
6123 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6124 struct intel_crtc_config *pipe_config)
6126 struct drm_device *dev = crtc->base.dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
6128 enum intel_display_power_domain pfit_domain;
6131 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6132 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6134 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6135 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6136 enum pipe trans_edp_pipe;
6137 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6139 WARN(1, "unknown pipe linked to edp transcoder\n");
6140 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6141 case TRANS_DDI_EDP_INPUT_A_ON:
6142 trans_edp_pipe = PIPE_A;
6144 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6145 trans_edp_pipe = PIPE_B;
6147 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6148 trans_edp_pipe = PIPE_C;
6152 if (trans_edp_pipe == crtc->pipe)
6153 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6156 if (!intel_display_power_enabled(dev,
6157 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6160 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6161 if (!(tmp & PIPECONF_ENABLE))
6165 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6166 * DDI E. So just check whether this pipe is wired to DDI E and whether
6167 * the PCH transcoder is on.
6169 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6170 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6171 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6172 pipe_config->has_pch_encoder = true;
6174 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6175 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6176 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6178 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6181 intel_get_pipe_timings(crtc, pipe_config);
6183 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6184 if (intel_display_power_enabled(dev, pfit_domain))
6185 ironlake_get_pfit_config(crtc, pipe_config);
6187 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6188 (I915_READ(IPS_CTL) & IPS_ENABLE);
6190 pipe_config->pixel_multiplier = 1;
6195 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6197 struct drm_framebuffer *fb)
6199 struct drm_device *dev = crtc->dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 struct intel_encoder *encoder;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6204 int pipe = intel_crtc->pipe;
6207 drm_vblank_pre_modeset(dev, pipe);
6209 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6211 drm_vblank_post_modeset(dev, pipe);
6216 for_each_encoder_on_crtc(dev, crtc, encoder) {
6217 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6218 encoder->base.base.id,
6219 drm_get_encoder_name(&encoder->base),
6220 mode->base.id, mode->name);
6221 encoder->mode_set(encoder);
6227 static bool intel_eld_uptodate(struct drm_connector *connector,
6228 int reg_eldv, uint32_t bits_eldv,
6229 int reg_elda, uint32_t bits_elda,
6232 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6233 uint8_t *eld = connector->eld;
6236 i = I915_READ(reg_eldv);
6245 i = I915_READ(reg_elda);
6247 I915_WRITE(reg_elda, i);
6249 for (i = 0; i < eld[2]; i++)
6250 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6256 static void g4x_write_eld(struct drm_connector *connector,
6257 struct drm_crtc *crtc)
6259 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6260 uint8_t *eld = connector->eld;
6265 i = I915_READ(G4X_AUD_VID_DID);
6267 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6268 eldv = G4X_ELDV_DEVCL_DEVBLC;
6270 eldv = G4X_ELDV_DEVCTG;
6272 if (intel_eld_uptodate(connector,
6273 G4X_AUD_CNTL_ST, eldv,
6274 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6275 G4X_HDMIW_HDMIEDID))
6278 i = I915_READ(G4X_AUD_CNTL_ST);
6279 i &= ~(eldv | G4X_ELD_ADDR);
6280 len = (i >> 9) & 0x1f; /* ELD buffer size */
6281 I915_WRITE(G4X_AUD_CNTL_ST, i);
6286 len = min_t(uint8_t, eld[2], len);
6287 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6288 for (i = 0; i < len; i++)
6289 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6291 i = I915_READ(G4X_AUD_CNTL_ST);
6293 I915_WRITE(G4X_AUD_CNTL_ST, i);
6296 static void haswell_write_eld(struct drm_connector *connector,
6297 struct drm_crtc *crtc)
6299 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6300 uint8_t *eld = connector->eld;
6301 struct drm_device *dev = crtc->dev;
6302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306 int pipe = to_intel_crtc(crtc)->pipe;
6309 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6310 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6311 int aud_config = HSW_AUD_CFG(pipe);
6312 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6315 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6317 /* Audio output enable */
6318 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6319 tmp = I915_READ(aud_cntrl_st2);
6320 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6321 I915_WRITE(aud_cntrl_st2, tmp);
6323 /* Wait for 1 vertical blank */
6324 intel_wait_for_vblank(dev, pipe);
6326 /* Set ELD valid state */
6327 tmp = I915_READ(aud_cntrl_st2);
6328 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6329 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6330 I915_WRITE(aud_cntrl_st2, tmp);
6331 tmp = I915_READ(aud_cntrl_st2);
6332 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6334 /* Enable HDMI mode */
6335 tmp = I915_READ(aud_config);
6336 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6337 /* clear N_programing_enable and N_value_index */
6338 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6339 I915_WRITE(aud_config, tmp);
6341 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6343 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6344 intel_crtc->eld_vld = true;
6346 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6347 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6348 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6349 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6351 I915_WRITE(aud_config, 0);
6353 if (intel_eld_uptodate(connector,
6354 aud_cntrl_st2, eldv,
6355 aud_cntl_st, IBX_ELD_ADDRESS,
6359 i = I915_READ(aud_cntrl_st2);
6361 I915_WRITE(aud_cntrl_st2, i);
6366 i = I915_READ(aud_cntl_st);
6367 i &= ~IBX_ELD_ADDRESS;
6368 I915_WRITE(aud_cntl_st, i);
6369 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6370 DRM_DEBUG_DRIVER("port num:%d\n", i);
6372 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6373 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6374 for (i = 0; i < len; i++)
6375 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6377 i = I915_READ(aud_cntrl_st2);
6379 I915_WRITE(aud_cntrl_st2, i);
6383 static void ironlake_write_eld(struct drm_connector *connector,
6384 struct drm_crtc *crtc)
6386 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6387 uint8_t *eld = connector->eld;
6395 int pipe = to_intel_crtc(crtc)->pipe;
6397 if (HAS_PCH_IBX(connector->dev)) {
6398 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6399 aud_config = IBX_AUD_CFG(pipe);
6400 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6401 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6403 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6404 aud_config = CPT_AUD_CFG(pipe);
6405 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6406 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6409 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6411 i = I915_READ(aud_cntl_st);
6412 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6414 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6415 /* operate blindly on all ports */
6416 eldv = IBX_ELD_VALIDB;
6417 eldv |= IBX_ELD_VALIDB << 4;
6418 eldv |= IBX_ELD_VALIDB << 8;
6420 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6421 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6425 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6426 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6427 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6429 I915_WRITE(aud_config, 0);
6431 if (intel_eld_uptodate(connector,
6432 aud_cntrl_st2, eldv,
6433 aud_cntl_st, IBX_ELD_ADDRESS,
6437 i = I915_READ(aud_cntrl_st2);
6439 I915_WRITE(aud_cntrl_st2, i);
6444 i = I915_READ(aud_cntl_st);
6445 i &= ~IBX_ELD_ADDRESS;
6446 I915_WRITE(aud_cntl_st, i);
6448 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6449 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6450 for (i = 0; i < len; i++)
6451 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6453 i = I915_READ(aud_cntrl_st2);
6455 I915_WRITE(aud_cntrl_st2, i);
6458 void intel_write_eld(struct drm_encoder *encoder,
6459 struct drm_display_mode *mode)
6461 struct drm_crtc *crtc = encoder->crtc;
6462 struct drm_connector *connector;
6463 struct drm_device *dev = encoder->dev;
6464 struct drm_i915_private *dev_priv = dev->dev_private;
6466 connector = drm_select_eld(encoder, mode);
6470 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6472 drm_get_connector_name(connector),
6473 connector->encoder->base.id,
6474 drm_get_encoder_name(connector->encoder));
6476 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6478 if (dev_priv->display.write_eld)
6479 dev_priv->display.write_eld(connector, crtc);
6482 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6483 void intel_crtc_load_lut(struct drm_crtc *crtc)
6485 struct drm_device *dev = crtc->dev;
6486 struct drm_i915_private *dev_priv = dev->dev_private;
6487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6488 enum pipe pipe = intel_crtc->pipe;
6489 int palreg = PALETTE(pipe);
6491 bool reenable_ips = false;
6493 /* The clocks have to be on to load the palette. */
6494 if (!crtc->enabled || !intel_crtc->active)
6497 if (!HAS_PCH_SPLIT(dev_priv->dev))
6498 assert_pll_enabled(dev_priv, pipe);
6500 /* use legacy palette for Ironlake */
6501 if (HAS_PCH_SPLIT(dev))
6502 palreg = LGC_PALETTE(pipe);
6504 /* Workaround : Do not read or write the pipe palette/gamma data while
6505 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6507 if (intel_crtc->config.ips_enabled &&
6508 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6509 GAMMA_MODE_MODE_SPLIT)) {
6510 hsw_disable_ips(intel_crtc);
6511 reenable_ips = true;
6514 for (i = 0; i < 256; i++) {
6515 I915_WRITE(palreg + 4 * i,
6516 (intel_crtc->lut_r[i] << 16) |
6517 (intel_crtc->lut_g[i] << 8) |
6518 intel_crtc->lut_b[i]);
6522 hsw_enable_ips(intel_crtc);
6525 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6527 struct drm_device *dev = crtc->dev;
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6530 bool visible = base != 0;
6533 if (intel_crtc->cursor_visible == visible)
6536 cntl = I915_READ(_CURACNTR);
6538 /* On these chipsets we can only modify the base whilst
6539 * the cursor is disabled.
6541 I915_WRITE(_CURABASE, base);
6543 cntl &= ~(CURSOR_FORMAT_MASK);
6544 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6545 cntl |= CURSOR_ENABLE |
6546 CURSOR_GAMMA_ENABLE |
6549 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6550 I915_WRITE(_CURACNTR, cntl);
6552 intel_crtc->cursor_visible = visible;
6555 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6557 struct drm_device *dev = crtc->dev;
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6560 int pipe = intel_crtc->pipe;
6561 bool visible = base != 0;
6563 if (intel_crtc->cursor_visible != visible) {
6564 uint32_t cntl = I915_READ(CURCNTR(pipe));
6566 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6567 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6568 cntl |= pipe << 28; /* Connect to correct pipe */
6570 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6571 cntl |= CURSOR_MODE_DISABLE;
6573 I915_WRITE(CURCNTR(pipe), cntl);
6575 intel_crtc->cursor_visible = visible;
6577 /* and commit changes on next vblank */
6578 I915_WRITE(CURBASE(pipe), base);
6581 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6583 struct drm_device *dev = crtc->dev;
6584 struct drm_i915_private *dev_priv = dev->dev_private;
6585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586 int pipe = intel_crtc->pipe;
6587 bool visible = base != 0;
6589 if (intel_crtc->cursor_visible != visible) {
6590 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6592 cntl &= ~CURSOR_MODE;
6593 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6595 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6596 cntl |= CURSOR_MODE_DISABLE;
6598 if (IS_HASWELL(dev))
6599 cntl |= CURSOR_PIPE_CSC_ENABLE;
6600 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6602 intel_crtc->cursor_visible = visible;
6604 /* and commit changes on next vblank */
6605 I915_WRITE(CURBASE_IVB(pipe), base);
6608 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6609 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6612 struct drm_device *dev = crtc->dev;
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615 int pipe = intel_crtc->pipe;
6616 int x = intel_crtc->cursor_x;
6617 int y = intel_crtc->cursor_y;
6623 if (on && crtc->enabled && crtc->fb) {
6624 base = intel_crtc->cursor_addr;
6625 if (x > (int) crtc->fb->width)
6628 if (y > (int) crtc->fb->height)
6634 if (x + intel_crtc->cursor_width < 0)
6637 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6640 pos |= x << CURSOR_X_SHIFT;
6643 if (y + intel_crtc->cursor_height < 0)
6646 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6649 pos |= y << CURSOR_Y_SHIFT;
6651 visible = base != 0;
6652 if (!visible && !intel_crtc->cursor_visible)
6655 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6656 I915_WRITE(CURPOS_IVB(pipe), pos);
6657 ivb_update_cursor(crtc, base);
6659 I915_WRITE(CURPOS(pipe), pos);
6660 if (IS_845G(dev) || IS_I865G(dev))
6661 i845_update_cursor(crtc, base);
6663 i9xx_update_cursor(crtc, base);
6667 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6668 struct drm_file *file,
6670 uint32_t width, uint32_t height)
6672 struct drm_device *dev = crtc->dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675 struct drm_i915_gem_object *obj;
6679 /* if we want to turn off the cursor ignore width and height */
6681 DRM_DEBUG_KMS("cursor off\n");
6684 mutex_lock(&dev->struct_mutex);
6688 /* Currently we only support 64x64 cursors */
6689 if (width != 64 || height != 64) {
6690 DRM_ERROR("we currently only support 64x64 cursors\n");
6694 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6695 if (&obj->base == NULL)
6698 if (obj->base.size < width * height * 4) {
6699 DRM_ERROR("buffer is to small\n");
6704 /* we only need to pin inside GTT if cursor is non-phy */
6705 mutex_lock(&dev->struct_mutex);
6706 if (!dev_priv->info->cursor_needs_physical) {
6709 if (obj->tiling_mode) {
6710 DRM_ERROR("cursor cannot be tiled\n");
6715 /* Note that the w/a also requires 2 PTE of padding following
6716 * the bo. We currently fill all unused PTE with the shadow
6717 * page and so we should always have valid PTE following the
6718 * cursor preventing the VT-d warning.
6721 if (need_vtd_wa(dev))
6722 alignment = 64*1024;
6724 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6726 DRM_ERROR("failed to move cursor bo into the GTT\n");
6730 ret = i915_gem_object_put_fence(obj);
6732 DRM_ERROR("failed to release fence for cursor");
6736 addr = i915_gem_obj_ggtt_offset(obj);
6738 int align = IS_I830(dev) ? 16 * 1024 : 256;
6739 ret = i915_gem_attach_phys_object(dev, obj,
6740 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6743 DRM_ERROR("failed to attach phys object\n");
6746 addr = obj->phys_obj->handle->busaddr;
6750 I915_WRITE(CURSIZE, (height << 12) | width);
6753 if (intel_crtc->cursor_bo) {
6754 if (dev_priv->info->cursor_needs_physical) {
6755 if (intel_crtc->cursor_bo != obj)
6756 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6758 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6759 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6762 mutex_unlock(&dev->struct_mutex);
6764 intel_crtc->cursor_addr = addr;
6765 intel_crtc->cursor_bo = obj;
6766 intel_crtc->cursor_width = width;
6767 intel_crtc->cursor_height = height;
6769 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6773 i915_gem_object_unpin_from_display_plane(obj);
6775 mutex_unlock(&dev->struct_mutex);
6777 drm_gem_object_unreference_unlocked(&obj->base);
6781 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6785 intel_crtc->cursor_x = x;
6786 intel_crtc->cursor_y = y;
6788 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6793 /** Sets the color ramps on behalf of RandR */
6794 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6795 u16 blue, int regno)
6797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799 intel_crtc->lut_r[regno] = red >> 8;
6800 intel_crtc->lut_g[regno] = green >> 8;
6801 intel_crtc->lut_b[regno] = blue >> 8;
6804 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6805 u16 *blue, int regno)
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6809 *red = intel_crtc->lut_r[regno] << 8;
6810 *green = intel_crtc->lut_g[regno] << 8;
6811 *blue = intel_crtc->lut_b[regno] << 8;
6814 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6815 u16 *blue, uint32_t start, uint32_t size)
6817 int end = (start + size > 256) ? 256 : start + size, i;
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6820 for (i = start; i < end; i++) {
6821 intel_crtc->lut_r[i] = red[i] >> 8;
6822 intel_crtc->lut_g[i] = green[i] >> 8;
6823 intel_crtc->lut_b[i] = blue[i] >> 8;
6826 intel_crtc_load_lut(crtc);
6829 /* VESA 640x480x72Hz mode to set on the pipe */
6830 static struct drm_display_mode load_detect_mode = {
6831 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6832 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6835 static struct drm_framebuffer *
6836 intel_framebuffer_create(struct drm_device *dev,
6837 struct drm_mode_fb_cmd2 *mode_cmd,
6838 struct drm_i915_gem_object *obj)
6840 struct intel_framebuffer *intel_fb;
6843 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6845 drm_gem_object_unreference_unlocked(&obj->base);
6846 return ERR_PTR(-ENOMEM);
6849 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6851 drm_gem_object_unreference_unlocked(&obj->base);
6853 return ERR_PTR(ret);
6856 return &intel_fb->base;
6860 intel_framebuffer_pitch_for_width(int width, int bpp)
6862 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6863 return ALIGN(pitch, 64);
6867 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6869 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6870 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6873 static struct drm_framebuffer *
6874 intel_framebuffer_create_for_mode(struct drm_device *dev,
6875 struct drm_display_mode *mode,
6878 struct drm_i915_gem_object *obj;
6879 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6881 obj = i915_gem_alloc_object(dev,
6882 intel_framebuffer_size_for_mode(mode, bpp));
6884 return ERR_PTR(-ENOMEM);
6886 mode_cmd.width = mode->hdisplay;
6887 mode_cmd.height = mode->vdisplay;
6888 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6890 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6892 return intel_framebuffer_create(dev, &mode_cmd, obj);
6895 static struct drm_framebuffer *
6896 mode_fits_in_fbdev(struct drm_device *dev,
6897 struct drm_display_mode *mode)
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct drm_i915_gem_object *obj;
6901 struct drm_framebuffer *fb;
6903 if (dev_priv->fbdev == NULL)
6906 obj = dev_priv->fbdev->ifb.obj;
6910 fb = &dev_priv->fbdev->ifb.base;
6911 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6912 fb->bits_per_pixel))
6915 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6921 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6922 struct drm_display_mode *mode,
6923 struct intel_load_detect_pipe *old)
6925 struct intel_crtc *intel_crtc;
6926 struct intel_encoder *intel_encoder =
6927 intel_attached_encoder(connector);
6928 struct drm_crtc *possible_crtc;
6929 struct drm_encoder *encoder = &intel_encoder->base;
6930 struct drm_crtc *crtc = NULL;
6931 struct drm_device *dev = encoder->dev;
6932 struct drm_framebuffer *fb;
6935 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6936 connector->base.id, drm_get_connector_name(connector),
6937 encoder->base.id, drm_get_encoder_name(encoder));
6940 * Algorithm gets a little messy:
6942 * - if the connector already has an assigned crtc, use it (but make
6943 * sure it's on first)
6945 * - try to find the first unused crtc that can drive this connector,
6946 * and use that if we find one
6949 /* See if we already have a CRTC for this connector */
6950 if (encoder->crtc) {
6951 crtc = encoder->crtc;
6953 mutex_lock(&crtc->mutex);
6955 old->dpms_mode = connector->dpms;
6956 old->load_detect_temp = false;
6958 /* Make sure the crtc and connector are running */
6959 if (connector->dpms != DRM_MODE_DPMS_ON)
6960 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6965 /* Find an unused one (if possible) */
6966 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6968 if (!(encoder->possible_crtcs & (1 << i)))
6970 if (!possible_crtc->enabled) {
6971 crtc = possible_crtc;
6977 * If we didn't find an unused CRTC, don't use any.
6980 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6984 mutex_lock(&crtc->mutex);
6985 intel_encoder->new_crtc = to_intel_crtc(crtc);
6986 to_intel_connector(connector)->new_encoder = intel_encoder;
6988 intel_crtc = to_intel_crtc(crtc);
6989 old->dpms_mode = connector->dpms;
6990 old->load_detect_temp = true;
6991 old->release_fb = NULL;
6994 mode = &load_detect_mode;
6996 /* We need a framebuffer large enough to accommodate all accesses
6997 * that the plane may generate whilst we perform load detection.
6998 * We can not rely on the fbcon either being present (we get called
6999 * during its initialisation to detect all boot displays, or it may
7000 * not even exist) or that it is large enough to satisfy the
7003 fb = mode_fits_in_fbdev(dev, mode);
7005 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7006 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7007 old->release_fb = fb;
7009 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7011 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7012 mutex_unlock(&crtc->mutex);
7016 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7017 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7018 if (old->release_fb)
7019 old->release_fb->funcs->destroy(old->release_fb);
7020 mutex_unlock(&crtc->mutex);
7024 /* let the connector get through one full cycle before testing */
7025 intel_wait_for_vblank(dev, intel_crtc->pipe);
7029 void intel_release_load_detect_pipe(struct drm_connector *connector,
7030 struct intel_load_detect_pipe *old)
7032 struct intel_encoder *intel_encoder =
7033 intel_attached_encoder(connector);
7034 struct drm_encoder *encoder = &intel_encoder->base;
7035 struct drm_crtc *crtc = encoder->crtc;
7037 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7038 connector->base.id, drm_get_connector_name(connector),
7039 encoder->base.id, drm_get_encoder_name(encoder));
7041 if (old->load_detect_temp) {
7042 to_intel_connector(connector)->new_encoder = NULL;
7043 intel_encoder->new_crtc = NULL;
7044 intel_set_mode(crtc, NULL, 0, 0, NULL);
7046 if (old->release_fb) {
7047 drm_framebuffer_unregister_private(old->release_fb);
7048 drm_framebuffer_unreference(old->release_fb);
7051 mutex_unlock(&crtc->mutex);
7055 /* Switch crtc and encoder back off if necessary */
7056 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7057 connector->funcs->dpms(connector, old->dpms_mode);
7059 mutex_unlock(&crtc->mutex);
7062 /* Returns the clock of the currently programmed mode of the given pipe. */
7063 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7064 struct intel_crtc_config *pipe_config)
7066 struct drm_device *dev = crtc->base.dev;
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068 int pipe = pipe_config->cpu_transcoder;
7069 u32 dpll = I915_READ(DPLL(pipe));
7071 intel_clock_t clock;
7073 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7074 fp = I915_READ(FP0(pipe));
7076 fp = I915_READ(FP1(pipe));
7078 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7079 if (IS_PINEVIEW(dev)) {
7080 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7081 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7083 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7084 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7087 if (!IS_GEN2(dev)) {
7088 if (IS_PINEVIEW(dev))
7089 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7090 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7092 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7093 DPLL_FPA01_P1_POST_DIV_SHIFT);
7095 switch (dpll & DPLL_MODE_MASK) {
7096 case DPLLB_MODE_DAC_SERIAL:
7097 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7100 case DPLLB_MODE_LVDS:
7101 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7105 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7106 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7107 pipe_config->adjusted_mode.clock = 0;
7111 if (IS_PINEVIEW(dev))
7112 pineview_clock(96000, &clock);
7114 i9xx_clock(96000, &clock);
7116 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7119 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7120 DPLL_FPA01_P1_POST_DIV_SHIFT);
7123 if ((dpll & PLL_REF_INPUT_MASK) ==
7124 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7125 /* XXX: might not be 66MHz */
7126 i9xx_clock(66000, &clock);
7128 i9xx_clock(48000, &clock);
7130 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7133 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7134 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7136 if (dpll & PLL_P2_DIVIDE_BY_4)
7141 i9xx_clock(48000, &clock);
7145 pipe_config->adjusted_mode.clock = clock.dot *
7146 pipe_config->pixel_multiplier;
7149 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7150 struct intel_crtc_config *pipe_config)
7152 struct drm_device *dev = crtc->base.dev;
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7155 int link_freq, repeat;
7159 repeat = pipe_config->pixel_multiplier;
7162 * The calculation for the data clock is:
7163 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7164 * But we want to avoid losing precison if possible, so:
7165 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7167 * and the link clock is simpler:
7168 * link_clock = (m * link_clock * repeat) / n
7172 * We need to get the FDI or DP link clock here to derive
7175 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7176 * For DP, it's either 1.62GHz or 2.7GHz.
7177 * We do our calculations in 10*MHz since we don't need much precison.
7179 if (pipe_config->has_pch_encoder)
7180 link_freq = intel_fdi_link_freq(dev) * 10000;
7182 link_freq = pipe_config->port_clock;
7184 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7185 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7187 if (!link_m || !link_n)
7190 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7191 do_div(clock, link_n);
7193 pipe_config->adjusted_mode.clock = clock;
7196 /** Returns the currently programmed mode of the given pipe. */
7197 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7198 struct drm_crtc *crtc)
7200 struct drm_i915_private *dev_priv = dev->dev_private;
7201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7202 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7203 struct drm_display_mode *mode;
7204 struct intel_crtc_config pipe_config;
7205 int htot = I915_READ(HTOTAL(cpu_transcoder));
7206 int hsync = I915_READ(HSYNC(cpu_transcoder));
7207 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7208 int vsync = I915_READ(VSYNC(cpu_transcoder));
7210 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7215 * Construct a pipe_config sufficient for getting the clock info
7216 * back out of crtc_clock_get.
7218 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7219 * to use a real value here instead.
7221 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7222 pipe_config.pixel_multiplier = 1;
7223 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7225 mode->clock = pipe_config.adjusted_mode.clock;
7226 mode->hdisplay = (htot & 0xffff) + 1;
7227 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7228 mode->hsync_start = (hsync & 0xffff) + 1;
7229 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7230 mode->vdisplay = (vtot & 0xffff) + 1;
7231 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7232 mode->vsync_start = (vsync & 0xffff) + 1;
7233 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7235 drm_mode_set_name(mode);
7240 static void intel_increase_pllclock(struct drm_crtc *crtc)
7242 struct drm_device *dev = crtc->dev;
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245 int pipe = intel_crtc->pipe;
7246 int dpll_reg = DPLL(pipe);
7249 if (HAS_PCH_SPLIT(dev))
7252 if (!dev_priv->lvds_downclock_avail)
7255 dpll = I915_READ(dpll_reg);
7256 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7257 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7259 assert_panel_unlocked(dev_priv, pipe);
7261 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7262 I915_WRITE(dpll_reg, dpll);
7263 intel_wait_for_vblank(dev, pipe);
7265 dpll = I915_READ(dpll_reg);
7266 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7267 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7271 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7273 struct drm_device *dev = crtc->dev;
7274 drm_i915_private_t *dev_priv = dev->dev_private;
7275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7277 if (HAS_PCH_SPLIT(dev))
7280 if (!dev_priv->lvds_downclock_avail)
7284 * Since this is called by a timer, we should never get here in
7287 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7288 int pipe = intel_crtc->pipe;
7289 int dpll_reg = DPLL(pipe);
7292 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7294 assert_panel_unlocked(dev_priv, pipe);
7296 dpll = I915_READ(dpll_reg);
7297 dpll |= DISPLAY_RATE_SELECT_FPA1;
7298 I915_WRITE(dpll_reg, dpll);
7299 intel_wait_for_vblank(dev, pipe);
7300 dpll = I915_READ(dpll_reg);
7301 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7302 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7307 void intel_mark_busy(struct drm_device *dev)
7309 i915_update_gfx_val(dev->dev_private);
7312 void intel_mark_idle(struct drm_device *dev)
7314 struct drm_crtc *crtc;
7316 if (!i915_powersave)
7319 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7323 intel_decrease_pllclock(crtc);
7327 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7328 struct intel_ring_buffer *ring)
7330 struct drm_device *dev = obj->base.dev;
7331 struct drm_crtc *crtc;
7333 if (!i915_powersave)
7336 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7340 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7343 intel_increase_pllclock(crtc);
7344 if (ring && intel_fbc_enabled(dev))
7345 ring->fbc_dirty = true;
7349 static void intel_crtc_destroy(struct drm_crtc *crtc)
7351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7352 struct drm_device *dev = crtc->dev;
7353 struct intel_unpin_work *work;
7354 unsigned long flags;
7356 spin_lock_irqsave(&dev->event_lock, flags);
7357 work = intel_crtc->unpin_work;
7358 intel_crtc->unpin_work = NULL;
7359 spin_unlock_irqrestore(&dev->event_lock, flags);
7362 cancel_work_sync(&work->work);
7366 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7368 drm_crtc_cleanup(crtc);
7373 static void intel_unpin_work_fn(struct work_struct *__work)
7375 struct intel_unpin_work *work =
7376 container_of(__work, struct intel_unpin_work, work);
7377 struct drm_device *dev = work->crtc->dev;
7379 mutex_lock(&dev->struct_mutex);
7380 intel_unpin_fb_obj(work->old_fb_obj);
7381 drm_gem_object_unreference(&work->pending_flip_obj->base);
7382 drm_gem_object_unreference(&work->old_fb_obj->base);
7384 intel_update_fbc(dev);
7385 mutex_unlock(&dev->struct_mutex);
7387 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7388 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7393 static void do_intel_finish_page_flip(struct drm_device *dev,
7394 struct drm_crtc *crtc)
7396 drm_i915_private_t *dev_priv = dev->dev_private;
7397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398 struct intel_unpin_work *work;
7399 unsigned long flags;
7401 /* Ignore early vblank irqs */
7402 if (intel_crtc == NULL)
7405 spin_lock_irqsave(&dev->event_lock, flags);
7406 work = intel_crtc->unpin_work;
7408 /* Ensure we don't miss a work->pending update ... */
7411 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7412 spin_unlock_irqrestore(&dev->event_lock, flags);
7416 /* and that the unpin work is consistent wrt ->pending. */
7419 intel_crtc->unpin_work = NULL;
7422 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7424 drm_vblank_put(dev, intel_crtc->pipe);
7426 spin_unlock_irqrestore(&dev->event_lock, flags);
7428 wake_up_all(&dev_priv->pending_flip_queue);
7430 queue_work(dev_priv->wq, &work->work);
7432 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7435 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7437 drm_i915_private_t *dev_priv = dev->dev_private;
7438 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7440 do_intel_finish_page_flip(dev, crtc);
7443 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7445 drm_i915_private_t *dev_priv = dev->dev_private;
7446 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7448 do_intel_finish_page_flip(dev, crtc);
7451 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7453 drm_i915_private_t *dev_priv = dev->dev_private;
7454 struct intel_crtc *intel_crtc =
7455 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7456 unsigned long flags;
7458 /* NB: An MMIO update of the plane base pointer will also
7459 * generate a page-flip completion irq, i.e. every modeset
7460 * is also accompanied by a spurious intel_prepare_page_flip().
7462 spin_lock_irqsave(&dev->event_lock, flags);
7463 if (intel_crtc->unpin_work)
7464 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7465 spin_unlock_irqrestore(&dev->event_lock, flags);
7468 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7470 /* Ensure that the work item is consistent when activating it ... */
7472 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7473 /* and that it is marked active as soon as the irq could fire. */
7477 static int intel_gen2_queue_flip(struct drm_device *dev,
7478 struct drm_crtc *crtc,
7479 struct drm_framebuffer *fb,
7480 struct drm_i915_gem_object *obj)
7482 struct drm_i915_private *dev_priv = dev->dev_private;
7483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7485 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7488 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7492 ret = intel_ring_begin(ring, 6);
7496 /* Can't queue multiple flips, so wait for the previous
7497 * one to finish before executing the next.
7499 if (intel_crtc->plane)
7500 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7502 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7503 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7504 intel_ring_emit(ring, MI_NOOP);
7505 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7506 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7507 intel_ring_emit(ring, fb->pitches[0]);
7508 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7509 intel_ring_emit(ring, 0); /* aux display base address, unused */
7511 intel_mark_page_flip_active(intel_crtc);
7512 intel_ring_advance(ring);
7516 intel_unpin_fb_obj(obj);
7521 static int intel_gen3_queue_flip(struct drm_device *dev,
7522 struct drm_crtc *crtc,
7523 struct drm_framebuffer *fb,
7524 struct drm_i915_gem_object *obj)
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7529 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7532 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7536 ret = intel_ring_begin(ring, 6);
7540 if (intel_crtc->plane)
7541 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7543 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7544 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7545 intel_ring_emit(ring, MI_NOOP);
7546 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7547 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7548 intel_ring_emit(ring, fb->pitches[0]);
7549 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7550 intel_ring_emit(ring, MI_NOOP);
7552 intel_mark_page_flip_active(intel_crtc);
7553 intel_ring_advance(ring);
7557 intel_unpin_fb_obj(obj);
7562 static int intel_gen4_queue_flip(struct drm_device *dev,
7563 struct drm_crtc *crtc,
7564 struct drm_framebuffer *fb,
7565 struct drm_i915_gem_object *obj)
7567 struct drm_i915_private *dev_priv = dev->dev_private;
7568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7569 uint32_t pf, pipesrc;
7570 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7573 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7577 ret = intel_ring_begin(ring, 4);
7581 /* i965+ uses the linear or tiled offsets from the
7582 * Display Registers (which do not change across a page-flip)
7583 * so we need only reprogram the base address.
7585 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7586 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7587 intel_ring_emit(ring, fb->pitches[0]);
7588 intel_ring_emit(ring,
7589 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7592 /* XXX Enabling the panel-fitter across page-flip is so far
7593 * untested on non-native modes, so ignore it for now.
7594 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7597 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7598 intel_ring_emit(ring, pf | pipesrc);
7600 intel_mark_page_flip_active(intel_crtc);
7601 intel_ring_advance(ring);
7605 intel_unpin_fb_obj(obj);
7610 static int intel_gen6_queue_flip(struct drm_device *dev,
7611 struct drm_crtc *crtc,
7612 struct drm_framebuffer *fb,
7613 struct drm_i915_gem_object *obj)
7615 struct drm_i915_private *dev_priv = dev->dev_private;
7616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7617 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7618 uint32_t pf, pipesrc;
7621 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7625 ret = intel_ring_begin(ring, 4);
7629 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7630 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7631 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7632 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7634 /* Contrary to the suggestions in the documentation,
7635 * "Enable Panel Fitter" does not seem to be required when page
7636 * flipping with a non-native mode, and worse causes a normal
7638 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7641 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7642 intel_ring_emit(ring, pf | pipesrc);
7644 intel_mark_page_flip_active(intel_crtc);
7645 intel_ring_advance(ring);
7649 intel_unpin_fb_obj(obj);
7655 * On gen7 we currently use the blit ring because (in early silicon at least)
7656 * the render ring doesn't give us interrpts for page flip completion, which
7657 * means clients will hang after the first flip is queued. Fortunately the
7658 * blit ring generates interrupts properly, so use it instead.
7660 static int intel_gen7_queue_flip(struct drm_device *dev,
7661 struct drm_crtc *crtc,
7662 struct drm_framebuffer *fb,
7663 struct drm_i915_gem_object *obj)
7665 struct drm_i915_private *dev_priv = dev->dev_private;
7666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7667 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7668 uint32_t plane_bit = 0;
7671 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7675 switch(intel_crtc->plane) {
7677 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7680 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7683 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7686 WARN_ONCE(1, "unknown plane in flip command\n");
7691 ret = intel_ring_begin(ring, 4);
7695 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7696 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7697 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7698 intel_ring_emit(ring, (MI_NOOP));
7700 intel_mark_page_flip_active(intel_crtc);
7701 intel_ring_advance(ring);
7705 intel_unpin_fb_obj(obj);
7710 static int intel_default_queue_flip(struct drm_device *dev,
7711 struct drm_crtc *crtc,
7712 struct drm_framebuffer *fb,
7713 struct drm_i915_gem_object *obj)
7718 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7719 struct drm_framebuffer *fb,
7720 struct drm_pending_vblank_event *event)
7722 struct drm_device *dev = crtc->dev;
7723 struct drm_i915_private *dev_priv = dev->dev_private;
7724 struct drm_framebuffer *old_fb = crtc->fb;
7725 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7727 struct intel_unpin_work *work;
7728 unsigned long flags;
7731 /* Can't change pixel format via MI display flips. */
7732 if (fb->pixel_format != crtc->fb->pixel_format)
7736 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7737 * Note that pitch changes could also affect these register.
7739 if (INTEL_INFO(dev)->gen > 3 &&
7740 (fb->offsets[0] != crtc->fb->offsets[0] ||
7741 fb->pitches[0] != crtc->fb->pitches[0]))
7744 work = kzalloc(sizeof *work, GFP_KERNEL);
7748 work->event = event;
7750 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7751 INIT_WORK(&work->work, intel_unpin_work_fn);
7753 ret = drm_vblank_get(dev, intel_crtc->pipe);
7757 /* We borrow the event spin lock for protecting unpin_work */
7758 spin_lock_irqsave(&dev->event_lock, flags);
7759 if (intel_crtc->unpin_work) {
7760 spin_unlock_irqrestore(&dev->event_lock, flags);
7762 drm_vblank_put(dev, intel_crtc->pipe);
7764 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7767 intel_crtc->unpin_work = work;
7768 spin_unlock_irqrestore(&dev->event_lock, flags);
7770 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7771 flush_workqueue(dev_priv->wq);
7773 ret = i915_mutex_lock_interruptible(dev);
7777 /* Reference the objects for the scheduled work. */
7778 drm_gem_object_reference(&work->old_fb_obj->base);
7779 drm_gem_object_reference(&obj->base);
7783 work->pending_flip_obj = obj;
7785 work->enable_stall_check = true;
7787 atomic_inc(&intel_crtc->unpin_work_count);
7788 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7790 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7792 goto cleanup_pending;
7794 intel_disable_fbc(dev);
7795 intel_mark_fb_busy(obj, NULL);
7796 mutex_unlock(&dev->struct_mutex);
7798 trace_i915_flip_request(intel_crtc->plane, obj);
7803 atomic_dec(&intel_crtc->unpin_work_count);
7805 drm_gem_object_unreference(&work->old_fb_obj->base);
7806 drm_gem_object_unreference(&obj->base);
7807 mutex_unlock(&dev->struct_mutex);
7810 spin_lock_irqsave(&dev->event_lock, flags);
7811 intel_crtc->unpin_work = NULL;
7812 spin_unlock_irqrestore(&dev->event_lock, flags);
7814 drm_vblank_put(dev, intel_crtc->pipe);
7821 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7822 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7823 .load_lut = intel_crtc_load_lut,
7826 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7827 struct drm_crtc *crtc)
7829 struct drm_device *dev;
7830 struct drm_crtc *tmp;
7833 WARN(!crtc, "checking null crtc?\n");
7837 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7843 if (encoder->possible_crtcs & crtc_mask)
7849 * intel_modeset_update_staged_output_state
7851 * Updates the staged output configuration state, e.g. after we've read out the
7854 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7856 struct intel_encoder *encoder;
7857 struct intel_connector *connector;
7859 list_for_each_entry(connector, &dev->mode_config.connector_list,
7861 connector->new_encoder =
7862 to_intel_encoder(connector->base.encoder);
7865 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7868 to_intel_crtc(encoder->base.crtc);
7873 * intel_modeset_commit_output_state
7875 * This function copies the stage display pipe configuration to the real one.
7877 static void intel_modeset_commit_output_state(struct drm_device *dev)
7879 struct intel_encoder *encoder;
7880 struct intel_connector *connector;
7882 list_for_each_entry(connector, &dev->mode_config.connector_list,
7884 connector->base.encoder = &connector->new_encoder->base;
7887 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7889 encoder->base.crtc = &encoder->new_crtc->base;
7894 connected_sink_compute_bpp(struct intel_connector * connector,
7895 struct intel_crtc_config *pipe_config)
7897 int bpp = pipe_config->pipe_bpp;
7899 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7900 connector->base.base.id,
7901 drm_get_connector_name(&connector->base));
7903 /* Don't use an invalid EDID bpc value */
7904 if (connector->base.display_info.bpc &&
7905 connector->base.display_info.bpc * 3 < bpp) {
7906 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7907 bpp, connector->base.display_info.bpc*3);
7908 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7911 /* Clamp bpp to 8 on screens without EDID 1.4 */
7912 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7913 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7915 pipe_config->pipe_bpp = 24;
7920 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7921 struct drm_framebuffer *fb,
7922 struct intel_crtc_config *pipe_config)
7924 struct drm_device *dev = crtc->base.dev;
7925 struct intel_connector *connector;
7928 switch (fb->pixel_format) {
7930 bpp = 8*3; /* since we go through a colormap */
7932 case DRM_FORMAT_XRGB1555:
7933 case DRM_FORMAT_ARGB1555:
7934 /* checked in intel_framebuffer_init already */
7935 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7937 case DRM_FORMAT_RGB565:
7938 bpp = 6*3; /* min is 18bpp */
7940 case DRM_FORMAT_XBGR8888:
7941 case DRM_FORMAT_ABGR8888:
7942 /* checked in intel_framebuffer_init already */
7943 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7945 case DRM_FORMAT_XRGB8888:
7946 case DRM_FORMAT_ARGB8888:
7949 case DRM_FORMAT_XRGB2101010:
7950 case DRM_FORMAT_ARGB2101010:
7951 case DRM_FORMAT_XBGR2101010:
7952 case DRM_FORMAT_ABGR2101010:
7953 /* checked in intel_framebuffer_init already */
7954 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7958 /* TODO: gen4+ supports 16 bpc floating point, too. */
7960 DRM_DEBUG_KMS("unsupported depth\n");
7964 pipe_config->pipe_bpp = bpp;
7966 /* Clamp display bpp to EDID value */
7967 list_for_each_entry(connector, &dev->mode_config.connector_list,
7969 if (!connector->new_encoder ||
7970 connector->new_encoder->new_crtc != crtc)
7973 connected_sink_compute_bpp(connector, pipe_config);
7979 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7980 struct intel_crtc_config *pipe_config,
7981 const char *context)
7983 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7984 context, pipe_name(crtc->pipe));
7986 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7987 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7988 pipe_config->pipe_bpp, pipe_config->dither);
7989 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7990 pipe_config->has_pch_encoder,
7991 pipe_config->fdi_lanes,
7992 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7993 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7994 pipe_config->fdi_m_n.tu);
7995 DRM_DEBUG_KMS("requested mode:\n");
7996 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7997 DRM_DEBUG_KMS("adjusted mode:\n");
7998 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7999 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8000 pipe_config->gmch_pfit.control,
8001 pipe_config->gmch_pfit.pgm_ratios,
8002 pipe_config->gmch_pfit.lvds_border_bits);
8003 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8004 pipe_config->pch_pfit.pos,
8005 pipe_config->pch_pfit.size);
8006 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8009 static bool check_encoder_cloning(struct drm_crtc *crtc)
8011 int num_encoders = 0;
8012 bool uncloneable_encoders = false;
8013 struct intel_encoder *encoder;
8015 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8017 if (&encoder->new_crtc->base != crtc)
8021 if (!encoder->cloneable)
8022 uncloneable_encoders = true;
8025 return !(num_encoders > 1 && uncloneable_encoders);
8028 static struct intel_crtc_config *
8029 intel_modeset_pipe_config(struct drm_crtc *crtc,
8030 struct drm_framebuffer *fb,
8031 struct drm_display_mode *mode)
8033 struct drm_device *dev = crtc->dev;
8034 struct intel_encoder *encoder;
8035 struct intel_crtc_config *pipe_config;
8036 int plane_bpp, ret = -EINVAL;
8039 if (!check_encoder_cloning(crtc)) {
8040 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8041 return ERR_PTR(-EINVAL);
8044 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8046 return ERR_PTR(-ENOMEM);
8048 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8049 drm_mode_copy(&pipe_config->requested_mode, mode);
8050 pipe_config->cpu_transcoder =
8051 (enum transcoder) to_intel_crtc(crtc)->pipe;
8052 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8055 * Sanitize sync polarity flags based on requested ones. If neither
8056 * positive or negative polarity is requested, treat this as meaning
8057 * negative polarity.
8059 if (!(pipe_config->adjusted_mode.flags &
8060 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8061 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8063 if (!(pipe_config->adjusted_mode.flags &
8064 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8065 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8067 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8068 * plane pixel format and any sink constraints into account. Returns the
8069 * source plane bpp so that dithering can be selected on mismatches
8070 * after encoders and crtc also have had their say. */
8071 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8077 /* Ensure the port clock defaults are reset when retrying. */
8078 pipe_config->port_clock = 0;
8079 pipe_config->pixel_multiplier = 1;
8081 /* Fill in default crtc timings, allow encoders to overwrite them. */
8082 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8084 /* Pass our mode to the connectors and the CRTC to give them a chance to
8085 * adjust it according to limitations or connector properties, and also
8086 * a chance to reject the mode entirely.
8088 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8091 if (&encoder->new_crtc->base != crtc)
8094 if (!(encoder->compute_config(encoder, pipe_config))) {
8095 DRM_DEBUG_KMS("Encoder config failure\n");
8100 /* Set default port clock if not overwritten by the encoder. Needs to be
8101 * done afterwards in case the encoder adjusts the mode. */
8102 if (!pipe_config->port_clock)
8103 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8105 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8107 DRM_DEBUG_KMS("CRTC fixup failed\n");
8112 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8117 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8122 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8123 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8124 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8129 return ERR_PTR(ret);
8132 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8133 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8135 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8136 unsigned *prepare_pipes, unsigned *disable_pipes)
8138 struct intel_crtc *intel_crtc;
8139 struct drm_device *dev = crtc->dev;
8140 struct intel_encoder *encoder;
8141 struct intel_connector *connector;
8142 struct drm_crtc *tmp_crtc;
8144 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8146 /* Check which crtcs have changed outputs connected to them, these need
8147 * to be part of the prepare_pipes mask. We don't (yet) support global
8148 * modeset across multiple crtcs, so modeset_pipes will only have one
8149 * bit set at most. */
8150 list_for_each_entry(connector, &dev->mode_config.connector_list,
8152 if (connector->base.encoder == &connector->new_encoder->base)
8155 if (connector->base.encoder) {
8156 tmp_crtc = connector->base.encoder->crtc;
8158 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8161 if (connector->new_encoder)
8163 1 << connector->new_encoder->new_crtc->pipe;
8166 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8168 if (encoder->base.crtc == &encoder->new_crtc->base)
8171 if (encoder->base.crtc) {
8172 tmp_crtc = encoder->base.crtc;
8174 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8177 if (encoder->new_crtc)
8178 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8181 /* Check for any pipes that will be fully disabled ... */
8182 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8186 /* Don't try to disable disabled crtcs. */
8187 if (!intel_crtc->base.enabled)
8190 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8192 if (encoder->new_crtc == intel_crtc)
8197 *disable_pipes |= 1 << intel_crtc->pipe;
8201 /* set_mode is also used to update properties on life display pipes. */
8202 intel_crtc = to_intel_crtc(crtc);
8204 *prepare_pipes |= 1 << intel_crtc->pipe;
8207 * For simplicity do a full modeset on any pipe where the output routing
8208 * changed. We could be more clever, but that would require us to be
8209 * more careful with calling the relevant encoder->mode_set functions.
8212 *modeset_pipes = *prepare_pipes;
8214 /* ... and mask these out. */
8215 *modeset_pipes &= ~(*disable_pipes);
8216 *prepare_pipes &= ~(*disable_pipes);
8219 * HACK: We don't (yet) fully support global modesets. intel_set_config
8220 * obies this rule, but the modeset restore mode of
8221 * intel_modeset_setup_hw_state does not.
8223 *modeset_pipes &= 1 << intel_crtc->pipe;
8224 *prepare_pipes &= 1 << intel_crtc->pipe;
8226 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8227 *modeset_pipes, *prepare_pipes, *disable_pipes);
8230 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8232 struct drm_encoder *encoder;
8233 struct drm_device *dev = crtc->dev;
8235 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8236 if (encoder->crtc == crtc)
8243 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8245 struct intel_encoder *intel_encoder;
8246 struct intel_crtc *intel_crtc;
8247 struct drm_connector *connector;
8249 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8251 if (!intel_encoder->base.crtc)
8254 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8256 if (prepare_pipes & (1 << intel_crtc->pipe))
8257 intel_encoder->connectors_active = false;
8260 intel_modeset_commit_output_state(dev);
8262 /* Update computed state. */
8263 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8265 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8269 if (!connector->encoder || !connector->encoder->crtc)
8272 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8274 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8275 struct drm_property *dpms_property =
8276 dev->mode_config.dpms_property;
8278 connector->dpms = DRM_MODE_DPMS_ON;
8279 drm_object_property_set_value(&connector->base,
8283 intel_encoder = to_intel_encoder(connector->encoder);
8284 intel_encoder->connectors_active = true;
8290 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8291 struct intel_crtc_config *new)
8293 int clock1, clock2, diff;
8295 clock1 = cur->adjusted_mode.clock;
8296 clock2 = new->adjusted_mode.clock;
8298 if (clock1 == clock2)
8301 if (!clock1 || !clock2)
8304 diff = abs(clock1 - clock2);
8306 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8312 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8313 list_for_each_entry((intel_crtc), \
8314 &(dev)->mode_config.crtc_list, \
8316 if (mask & (1 <<(intel_crtc)->pipe))
8319 intel_pipe_config_compare(struct drm_device *dev,
8320 struct intel_crtc_config *current_config,
8321 struct intel_crtc_config *pipe_config)
8323 #define PIPE_CONF_CHECK_X(name) \
8324 if (current_config->name != pipe_config->name) { \
8325 DRM_ERROR("mismatch in " #name " " \
8326 "(expected 0x%08x, found 0x%08x)\n", \
8327 current_config->name, \
8328 pipe_config->name); \
8332 #define PIPE_CONF_CHECK_I(name) \
8333 if (current_config->name != pipe_config->name) { \
8334 DRM_ERROR("mismatch in " #name " " \
8335 "(expected %i, found %i)\n", \
8336 current_config->name, \
8337 pipe_config->name); \
8341 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8342 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8343 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8344 "(expected %i, found %i)\n", \
8345 current_config->name & (mask), \
8346 pipe_config->name & (mask)); \
8350 #define PIPE_CONF_QUIRK(quirk) \
8351 ((current_config->quirks | pipe_config->quirks) & (quirk))
8353 PIPE_CONF_CHECK_I(cpu_transcoder);
8355 PIPE_CONF_CHECK_I(has_pch_encoder);
8356 PIPE_CONF_CHECK_I(fdi_lanes);
8357 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8358 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8359 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8360 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8361 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8363 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8364 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8365 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8366 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8367 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8368 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8370 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8371 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8372 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8373 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8374 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8375 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8377 PIPE_CONF_CHECK_I(pixel_multiplier);
8379 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8380 DRM_MODE_FLAG_INTERLACE);
8382 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8383 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8384 DRM_MODE_FLAG_PHSYNC);
8385 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8386 DRM_MODE_FLAG_NHSYNC);
8387 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8388 DRM_MODE_FLAG_PVSYNC);
8389 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390 DRM_MODE_FLAG_NVSYNC);
8393 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8394 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8396 PIPE_CONF_CHECK_I(gmch_pfit.control);
8397 /* pfit ratios are autocomputed by the hw on gen4+ */
8398 if (INTEL_INFO(dev)->gen < 4)
8399 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8400 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8401 PIPE_CONF_CHECK_I(pch_pfit.pos);
8402 PIPE_CONF_CHECK_I(pch_pfit.size);
8404 PIPE_CONF_CHECK_I(ips_enabled);
8406 PIPE_CONF_CHECK_I(shared_dpll);
8407 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8408 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8409 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8410 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8412 #undef PIPE_CONF_CHECK_X
8413 #undef PIPE_CONF_CHECK_I
8414 #undef PIPE_CONF_CHECK_FLAGS
8415 #undef PIPE_CONF_QUIRK
8417 if (!IS_HASWELL(dev)) {
8418 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8419 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8420 current_config->adjusted_mode.clock,
8421 pipe_config->adjusted_mode.clock);
8430 check_connector_state(struct drm_device *dev)
8432 struct intel_connector *connector;
8434 list_for_each_entry(connector, &dev->mode_config.connector_list,
8436 /* This also checks the encoder/connector hw state with the
8437 * ->get_hw_state callbacks. */
8438 intel_connector_check_state(connector);
8440 WARN(&connector->new_encoder->base != connector->base.encoder,
8441 "connector's staged encoder doesn't match current encoder\n");
8446 check_encoder_state(struct drm_device *dev)
8448 struct intel_encoder *encoder;
8449 struct intel_connector *connector;
8451 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8453 bool enabled = false;
8454 bool active = false;
8455 enum pipe pipe, tracked_pipe;
8457 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8458 encoder->base.base.id,
8459 drm_get_encoder_name(&encoder->base));
8461 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8462 "encoder's stage crtc doesn't match current crtc\n");
8463 WARN(encoder->connectors_active && !encoder->base.crtc,
8464 "encoder's active_connectors set, but no crtc\n");
8466 list_for_each_entry(connector, &dev->mode_config.connector_list,
8468 if (connector->base.encoder != &encoder->base)
8471 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8474 WARN(!!encoder->base.crtc != enabled,
8475 "encoder's enabled state mismatch "
8476 "(expected %i, found %i)\n",
8477 !!encoder->base.crtc, enabled);
8478 WARN(active && !encoder->base.crtc,
8479 "active encoder with no crtc\n");
8481 WARN(encoder->connectors_active != active,
8482 "encoder's computed active state doesn't match tracked active state "
8483 "(expected %i, found %i)\n", active, encoder->connectors_active);
8485 active = encoder->get_hw_state(encoder, &pipe);
8486 WARN(active != encoder->connectors_active,
8487 "encoder's hw state doesn't match sw tracking "
8488 "(expected %i, found %i)\n",
8489 encoder->connectors_active, active);
8491 if (!encoder->base.crtc)
8494 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8495 WARN(active && pipe != tracked_pipe,
8496 "active encoder's pipe doesn't match"
8497 "(expected %i, found %i)\n",
8498 tracked_pipe, pipe);
8504 check_crtc_state(struct drm_device *dev)
8506 drm_i915_private_t *dev_priv = dev->dev_private;
8507 struct intel_crtc *crtc;
8508 struct intel_encoder *encoder;
8509 struct intel_crtc_config pipe_config;
8511 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8513 bool enabled = false;
8514 bool active = false;
8516 memset(&pipe_config, 0, sizeof(pipe_config));
8518 DRM_DEBUG_KMS("[CRTC:%d]\n",
8519 crtc->base.base.id);
8521 WARN(crtc->active && !crtc->base.enabled,
8522 "active crtc, but not enabled in sw tracking\n");
8524 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8526 if (encoder->base.crtc != &crtc->base)
8529 if (encoder->connectors_active)
8533 WARN(active != crtc->active,
8534 "crtc's computed active state doesn't match tracked active state "
8535 "(expected %i, found %i)\n", active, crtc->active);
8536 WARN(enabled != crtc->base.enabled,
8537 "crtc's computed enabled state doesn't match tracked enabled state "
8538 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8540 active = dev_priv->display.get_pipe_config(crtc,
8543 /* hw state is inconsistent with the pipe A quirk */
8544 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8545 active = crtc->active;
8547 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8549 if (encoder->base.crtc != &crtc->base)
8551 if (encoder->get_config)
8552 encoder->get_config(encoder, &pipe_config);
8555 if (dev_priv->display.get_clock)
8556 dev_priv->display.get_clock(crtc, &pipe_config);
8558 WARN(crtc->active != active,
8559 "crtc active state doesn't match with hw state "
8560 "(expected %i, found %i)\n", crtc->active, active);
8563 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8564 WARN(1, "pipe state doesn't match!\n");
8565 intel_dump_pipe_config(crtc, &pipe_config,
8567 intel_dump_pipe_config(crtc, &crtc->config,
8574 check_shared_dpll_state(struct drm_device *dev)
8576 drm_i915_private_t *dev_priv = dev->dev_private;
8577 struct intel_crtc *crtc;
8578 struct intel_dpll_hw_state dpll_hw_state;
8581 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8582 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8583 int enabled_crtcs = 0, active_crtcs = 0;
8586 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8588 DRM_DEBUG_KMS("%s\n", pll->name);
8590 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8592 WARN(pll->active > pll->refcount,
8593 "more active pll users than references: %i vs %i\n",
8594 pll->active, pll->refcount);
8595 WARN(pll->active && !pll->on,
8596 "pll in active use but not on in sw tracking\n");
8597 WARN(pll->on && !pll->active,
8598 "pll in on but not on in use in sw tracking\n");
8599 WARN(pll->on != active,
8600 "pll on state mismatch (expected %i, found %i)\n",
8603 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8605 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8607 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8610 WARN(pll->active != active_crtcs,
8611 "pll active crtcs mismatch (expected %i, found %i)\n",
8612 pll->active, active_crtcs);
8613 WARN(pll->refcount != enabled_crtcs,
8614 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8615 pll->refcount, enabled_crtcs);
8617 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8618 sizeof(dpll_hw_state)),
8619 "pll hw state mismatch\n");
8624 intel_modeset_check_state(struct drm_device *dev)
8626 check_connector_state(dev);
8627 check_encoder_state(dev);
8628 check_crtc_state(dev);
8629 check_shared_dpll_state(dev);
8632 static int __intel_set_mode(struct drm_crtc *crtc,
8633 struct drm_display_mode *mode,
8634 int x, int y, struct drm_framebuffer *fb)
8636 struct drm_device *dev = crtc->dev;
8637 drm_i915_private_t *dev_priv = dev->dev_private;
8638 struct drm_display_mode *saved_mode, *saved_hwmode;
8639 struct intel_crtc_config *pipe_config = NULL;
8640 struct intel_crtc *intel_crtc;
8641 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8644 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8647 saved_hwmode = saved_mode + 1;
8649 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8650 &prepare_pipes, &disable_pipes);
8652 *saved_hwmode = crtc->hwmode;
8653 *saved_mode = crtc->mode;
8655 /* Hack: Because we don't (yet) support global modeset on multiple
8656 * crtcs, we don't keep track of the new mode for more than one crtc.
8657 * Hence simply check whether any bit is set in modeset_pipes in all the
8658 * pieces of code that are not yet converted to deal with mutliple crtcs
8659 * changing their mode at the same time. */
8660 if (modeset_pipes) {
8661 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8662 if (IS_ERR(pipe_config)) {
8663 ret = PTR_ERR(pipe_config);
8668 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8672 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8673 intel_crtc_disable(&intel_crtc->base);
8675 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8676 if (intel_crtc->base.enabled)
8677 dev_priv->display.crtc_disable(&intel_crtc->base);
8680 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8681 * to set it here already despite that we pass it down the callchain.
8683 if (modeset_pipes) {
8685 /* mode_set/enable/disable functions rely on a correct pipe
8687 to_intel_crtc(crtc)->config = *pipe_config;
8690 /* Only after disabling all output pipelines that will be changed can we
8691 * update the the output configuration. */
8692 intel_modeset_update_state(dev, prepare_pipes);
8694 if (dev_priv->display.modeset_global_resources)
8695 dev_priv->display.modeset_global_resources(dev);
8697 /* Set up the DPLL and any encoders state that needs to adjust or depend
8700 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8701 ret = intel_crtc_mode_set(&intel_crtc->base,
8707 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8708 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8709 dev_priv->display.crtc_enable(&intel_crtc->base);
8711 if (modeset_pipes) {
8712 /* Store real post-adjustment hardware mode. */
8713 crtc->hwmode = pipe_config->adjusted_mode;
8715 /* Calculate and store various constants which
8716 * are later needed by vblank and swap-completion
8717 * timestamping. They are derived from true hwmode.
8719 drm_calc_timestamping_constants(crtc);
8722 /* FIXME: add subpixel order */
8724 if (ret && crtc->enabled) {
8725 crtc->hwmode = *saved_hwmode;
8726 crtc->mode = *saved_mode;
8735 static int intel_set_mode(struct drm_crtc *crtc,
8736 struct drm_display_mode *mode,
8737 int x, int y, struct drm_framebuffer *fb)
8741 ret = __intel_set_mode(crtc, mode, x, y, fb);
8744 intel_modeset_check_state(crtc->dev);
8749 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8751 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8754 #undef for_each_intel_crtc_masked
8756 static void intel_set_config_free(struct intel_set_config *config)
8761 kfree(config->save_connector_encoders);
8762 kfree(config->save_encoder_crtcs);
8766 static int intel_set_config_save_state(struct drm_device *dev,
8767 struct intel_set_config *config)
8769 struct drm_encoder *encoder;
8770 struct drm_connector *connector;
8773 config->save_encoder_crtcs =
8774 kcalloc(dev->mode_config.num_encoder,
8775 sizeof(struct drm_crtc *), GFP_KERNEL);
8776 if (!config->save_encoder_crtcs)
8779 config->save_connector_encoders =
8780 kcalloc(dev->mode_config.num_connector,
8781 sizeof(struct drm_encoder *), GFP_KERNEL);
8782 if (!config->save_connector_encoders)
8785 /* Copy data. Note that driver private data is not affected.
8786 * Should anything bad happen only the expected state is
8787 * restored, not the drivers personal bookkeeping.
8790 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8791 config->save_encoder_crtcs[count++] = encoder->crtc;
8795 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8796 config->save_connector_encoders[count++] = connector->encoder;
8802 static void intel_set_config_restore_state(struct drm_device *dev,
8803 struct intel_set_config *config)
8805 struct intel_encoder *encoder;
8806 struct intel_connector *connector;
8810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8812 to_intel_crtc(config->save_encoder_crtcs[count++]);
8816 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8817 connector->new_encoder =
8818 to_intel_encoder(config->save_connector_encoders[count++]);
8823 is_crtc_connector_off(struct drm_mode_set *set)
8827 if (set->num_connectors == 0)
8830 if (WARN_ON(set->connectors == NULL))
8833 for (i = 0; i < set->num_connectors; i++)
8834 if (set->connectors[i]->encoder &&
8835 set->connectors[i]->encoder->crtc == set->crtc &&
8836 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8843 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8844 struct intel_set_config *config)
8847 /* We should be able to check here if the fb has the same properties
8848 * and then just flip_or_move it */
8849 if (is_crtc_connector_off(set)) {
8850 config->mode_changed = true;
8851 } else if (set->crtc->fb != set->fb) {
8852 /* If we have no fb then treat it as a full mode set */
8853 if (set->crtc->fb == NULL) {
8854 struct intel_crtc *intel_crtc =
8855 to_intel_crtc(set->crtc);
8857 if (intel_crtc->active && i915_fastboot) {
8858 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8859 config->fb_changed = true;
8861 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8862 config->mode_changed = true;
8864 } else if (set->fb == NULL) {
8865 config->mode_changed = true;
8866 } else if (set->fb->pixel_format !=
8867 set->crtc->fb->pixel_format) {
8868 config->mode_changed = true;
8870 config->fb_changed = true;
8874 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8875 config->fb_changed = true;
8877 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8878 DRM_DEBUG_KMS("modes are different, full mode set\n");
8879 drm_mode_debug_printmodeline(&set->crtc->mode);
8880 drm_mode_debug_printmodeline(set->mode);
8881 config->mode_changed = true;
8884 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
8885 set->crtc->base.id, config->mode_changed, config->fb_changed);
8889 intel_modeset_stage_output_state(struct drm_device *dev,
8890 struct drm_mode_set *set,
8891 struct intel_set_config *config)
8893 struct drm_crtc *new_crtc;
8894 struct intel_connector *connector;
8895 struct intel_encoder *encoder;
8898 /* The upper layers ensure that we either disable a crtc or have a list
8899 * of connectors. For paranoia, double-check this. */
8900 WARN_ON(!set->fb && (set->num_connectors != 0));
8901 WARN_ON(set->fb && (set->num_connectors == 0));
8903 list_for_each_entry(connector, &dev->mode_config.connector_list,
8905 /* Otherwise traverse passed in connector list and get encoders
8907 for (ro = 0; ro < set->num_connectors; ro++) {
8908 if (set->connectors[ro] == &connector->base) {
8909 connector->new_encoder = connector->encoder;
8914 /* If we disable the crtc, disable all its connectors. Also, if
8915 * the connector is on the changing crtc but not on the new
8916 * connector list, disable it. */
8917 if ((!set->fb || ro == set->num_connectors) &&
8918 connector->base.encoder &&
8919 connector->base.encoder->crtc == set->crtc) {
8920 connector->new_encoder = NULL;
8922 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8923 connector->base.base.id,
8924 drm_get_connector_name(&connector->base));
8928 if (&connector->new_encoder->base != connector->base.encoder) {
8929 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8930 config->mode_changed = true;
8933 /* connector->new_encoder is now updated for all connectors. */
8935 /* Update crtc of enabled connectors. */
8936 list_for_each_entry(connector, &dev->mode_config.connector_list,
8938 if (!connector->new_encoder)
8941 new_crtc = connector->new_encoder->base.crtc;
8943 for (ro = 0; ro < set->num_connectors; ro++) {
8944 if (set->connectors[ro] == &connector->base)
8945 new_crtc = set->crtc;
8948 /* Make sure the new CRTC will work with the encoder */
8949 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8953 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8956 connector->base.base.id,
8957 drm_get_connector_name(&connector->base),
8961 /* Check for any encoders that needs to be disabled. */
8962 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8964 list_for_each_entry(connector,
8965 &dev->mode_config.connector_list,
8967 if (connector->new_encoder == encoder) {
8968 WARN_ON(!connector->new_encoder->new_crtc);
8973 encoder->new_crtc = NULL;
8975 /* Only now check for crtc changes so we don't miss encoders
8976 * that will be disabled. */
8977 if (&encoder->new_crtc->base != encoder->base.crtc) {
8978 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8979 config->mode_changed = true;
8982 /* Now we've also updated encoder->new_crtc for all encoders. */
8987 static int intel_crtc_set_config(struct drm_mode_set *set)
8989 struct drm_device *dev;
8990 struct drm_mode_set save_set;
8991 struct intel_set_config *config;
8996 BUG_ON(!set->crtc->helper_private);
8998 /* Enforce sane interface api - has been abused by the fb helper. */
8999 BUG_ON(!set->mode && set->fb);
9000 BUG_ON(set->fb && set->num_connectors == 0);
9003 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9004 set->crtc->base.id, set->fb->base.id,
9005 (int)set->num_connectors, set->x, set->y);
9007 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9010 dev = set->crtc->dev;
9013 config = kzalloc(sizeof(*config), GFP_KERNEL);
9017 ret = intel_set_config_save_state(dev, config);
9021 save_set.crtc = set->crtc;
9022 save_set.mode = &set->crtc->mode;
9023 save_set.x = set->crtc->x;
9024 save_set.y = set->crtc->y;
9025 save_set.fb = set->crtc->fb;
9027 /* Compute whether we need a full modeset, only an fb base update or no
9028 * change at all. In the future we might also check whether only the
9029 * mode changed, e.g. for LVDS where we only change the panel fitter in
9031 intel_set_config_compute_mode_changes(set, config);
9033 ret = intel_modeset_stage_output_state(dev, set, config);
9037 if (config->mode_changed) {
9038 ret = intel_set_mode(set->crtc, set->mode,
9039 set->x, set->y, set->fb);
9040 } else if (config->fb_changed) {
9041 intel_crtc_wait_for_pending_flips(set->crtc);
9043 ret = intel_pipe_set_base(set->crtc,
9044 set->x, set->y, set->fb);
9048 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9049 set->crtc->base.id, ret);
9051 intel_set_config_restore_state(dev, config);
9053 /* Try to restore the config */
9054 if (config->mode_changed &&
9055 intel_set_mode(save_set.crtc, save_set.mode,
9056 save_set.x, save_set.y, save_set.fb))
9057 DRM_ERROR("failed to restore config after modeset failure\n");
9061 intel_set_config_free(config);
9065 static const struct drm_crtc_funcs intel_crtc_funcs = {
9066 .cursor_set = intel_crtc_cursor_set,
9067 .cursor_move = intel_crtc_cursor_move,
9068 .gamma_set = intel_crtc_gamma_set,
9069 .set_config = intel_crtc_set_config,
9070 .destroy = intel_crtc_destroy,
9071 .page_flip = intel_crtc_page_flip,
9074 static void intel_cpu_pll_init(struct drm_device *dev)
9077 intel_ddi_pll_init(dev);
9080 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9081 struct intel_shared_dpll *pll,
9082 struct intel_dpll_hw_state *hw_state)
9086 val = I915_READ(PCH_DPLL(pll->id));
9087 hw_state->dpll = val;
9088 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9089 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9091 return val & DPLL_VCO_ENABLE;
9094 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9095 struct intel_shared_dpll *pll)
9097 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9098 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9101 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9102 struct intel_shared_dpll *pll)
9104 /* PCH refclock must be enabled first */
9105 assert_pch_refclk_enabled(dev_priv);
9107 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9109 /* Wait for the clocks to stabilize. */
9110 POSTING_READ(PCH_DPLL(pll->id));
9113 /* The pixel multiplier can only be updated once the
9114 * DPLL is enabled and the clocks are stable.
9116 * So write it again.
9118 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9119 POSTING_READ(PCH_DPLL(pll->id));
9123 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9124 struct intel_shared_dpll *pll)
9126 struct drm_device *dev = dev_priv->dev;
9127 struct intel_crtc *crtc;
9129 /* Make sure no transcoder isn't still depending on us. */
9130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9131 if (intel_crtc_to_shared_dpll(crtc) == pll)
9132 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9135 I915_WRITE(PCH_DPLL(pll->id), 0);
9136 POSTING_READ(PCH_DPLL(pll->id));
9140 static char *ibx_pch_dpll_names[] = {
9145 static void ibx_pch_dpll_init(struct drm_device *dev)
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9150 dev_priv->num_shared_dpll = 2;
9152 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9153 dev_priv->shared_dplls[i].id = i;
9154 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9155 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9156 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9157 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9158 dev_priv->shared_dplls[i].get_hw_state =
9159 ibx_pch_dpll_get_hw_state;
9163 static void intel_shared_dpll_init(struct drm_device *dev)
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9167 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9168 ibx_pch_dpll_init(dev);
9170 dev_priv->num_shared_dpll = 0;
9172 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9173 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9174 dev_priv->num_shared_dpll);
9177 static void intel_crtc_init(struct drm_device *dev, int pipe)
9179 drm_i915_private_t *dev_priv = dev->dev_private;
9180 struct intel_crtc *intel_crtc;
9183 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9184 if (intel_crtc == NULL)
9187 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9189 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9190 for (i = 0; i < 256; i++) {
9191 intel_crtc->lut_r[i] = i;
9192 intel_crtc->lut_g[i] = i;
9193 intel_crtc->lut_b[i] = i;
9196 /* Swap pipes & planes for FBC on pre-965 */
9197 intel_crtc->pipe = pipe;
9198 intel_crtc->plane = pipe;
9199 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9200 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9201 intel_crtc->plane = !pipe;
9204 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9205 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9206 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9207 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9209 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9212 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9213 struct drm_file *file)
9215 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9216 struct drm_mode_object *drmmode_obj;
9217 struct intel_crtc *crtc;
9219 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9222 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9223 DRM_MODE_OBJECT_CRTC);
9226 DRM_ERROR("no such CRTC id\n");
9230 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9231 pipe_from_crtc_id->pipe = crtc->pipe;
9236 static int intel_encoder_clones(struct intel_encoder *encoder)
9238 struct drm_device *dev = encoder->base.dev;
9239 struct intel_encoder *source_encoder;
9243 list_for_each_entry(source_encoder,
9244 &dev->mode_config.encoder_list, base.head) {
9246 if (encoder == source_encoder)
9247 index_mask |= (1 << entry);
9249 /* Intel hw has only one MUX where enocoders could be cloned. */
9250 if (encoder->cloneable && source_encoder->cloneable)
9251 index_mask |= (1 << entry);
9259 static bool has_edp_a(struct drm_device *dev)
9261 struct drm_i915_private *dev_priv = dev->dev_private;
9263 if (!IS_MOBILE(dev))
9266 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9270 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9276 static void intel_setup_outputs(struct drm_device *dev)
9278 struct drm_i915_private *dev_priv = dev->dev_private;
9279 struct intel_encoder *encoder;
9280 bool dpd_is_edp = false;
9282 intel_lvds_init(dev);
9285 intel_crt_init(dev);
9290 /* Haswell uses DDI functions to detect digital outputs */
9291 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9292 /* DDI A only supports eDP */
9294 intel_ddi_init(dev, PORT_A);
9296 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9298 found = I915_READ(SFUSE_STRAP);
9300 if (found & SFUSE_STRAP_DDIB_DETECTED)
9301 intel_ddi_init(dev, PORT_B);
9302 if (found & SFUSE_STRAP_DDIC_DETECTED)
9303 intel_ddi_init(dev, PORT_C);
9304 if (found & SFUSE_STRAP_DDID_DETECTED)
9305 intel_ddi_init(dev, PORT_D);
9306 } else if (HAS_PCH_SPLIT(dev)) {
9308 dpd_is_edp = intel_dpd_is_edp(dev);
9311 intel_dp_init(dev, DP_A, PORT_A);
9313 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9314 /* PCH SDVOB multiplex with HDMIB */
9315 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9317 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9318 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9319 intel_dp_init(dev, PCH_DP_B, PORT_B);
9322 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9323 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9325 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9326 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9328 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9329 intel_dp_init(dev, PCH_DP_C, PORT_C);
9331 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9332 intel_dp_init(dev, PCH_DP_D, PORT_D);
9333 } else if (IS_VALLEYVIEW(dev)) {
9334 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9335 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9336 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9338 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9339 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9343 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9344 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9346 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9347 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9349 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9352 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9353 DRM_DEBUG_KMS("probing SDVOB\n");
9354 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9355 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9356 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9357 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9360 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9361 intel_dp_init(dev, DP_B, PORT_B);
9364 /* Before G4X SDVOC doesn't have its own detect register */
9366 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9367 DRM_DEBUG_KMS("probing SDVOC\n");
9368 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9371 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9373 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9374 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9375 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9377 if (SUPPORTS_INTEGRATED_DP(dev))
9378 intel_dp_init(dev, DP_C, PORT_C);
9381 if (SUPPORTS_INTEGRATED_DP(dev) &&
9382 (I915_READ(DP_D) & DP_DETECTED))
9383 intel_dp_init(dev, DP_D, PORT_D);
9384 } else if (IS_GEN2(dev))
9385 intel_dvo_init(dev);
9387 if (SUPPORTS_TV(dev))
9390 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9391 encoder->base.possible_crtcs = encoder->crtc_mask;
9392 encoder->base.possible_clones =
9393 intel_encoder_clones(encoder);
9396 intel_init_pch_refclk(dev);
9398 drm_helper_move_panel_connectors_to_head(dev);
9401 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9403 drm_framebuffer_cleanup(&fb->base);
9404 drm_gem_object_unreference_unlocked(&fb->obj->base);
9407 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9409 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9411 intel_framebuffer_fini(intel_fb);
9415 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9416 struct drm_file *file,
9417 unsigned int *handle)
9419 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9420 struct drm_i915_gem_object *obj = intel_fb->obj;
9422 return drm_gem_handle_create(file, &obj->base, handle);
9425 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9426 .destroy = intel_user_framebuffer_destroy,
9427 .create_handle = intel_user_framebuffer_create_handle,
9430 int intel_framebuffer_init(struct drm_device *dev,
9431 struct intel_framebuffer *intel_fb,
9432 struct drm_mode_fb_cmd2 *mode_cmd,
9433 struct drm_i915_gem_object *obj)
9438 if (obj->tiling_mode == I915_TILING_Y) {
9439 DRM_DEBUG("hardware does not support tiling Y\n");
9443 if (mode_cmd->pitches[0] & 63) {
9444 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9445 mode_cmd->pitches[0]);
9449 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9450 pitch_limit = 32*1024;
9451 } else if (INTEL_INFO(dev)->gen >= 4) {
9452 if (obj->tiling_mode)
9453 pitch_limit = 16*1024;
9455 pitch_limit = 32*1024;
9456 } else if (INTEL_INFO(dev)->gen >= 3) {
9457 if (obj->tiling_mode)
9458 pitch_limit = 8*1024;
9460 pitch_limit = 16*1024;
9462 /* XXX DSPC is limited to 4k tiled */
9463 pitch_limit = 8*1024;
9465 if (mode_cmd->pitches[0] > pitch_limit) {
9466 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9467 obj->tiling_mode ? "tiled" : "linear",
9468 mode_cmd->pitches[0], pitch_limit);
9472 if (obj->tiling_mode != I915_TILING_NONE &&
9473 mode_cmd->pitches[0] != obj->stride) {
9474 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9475 mode_cmd->pitches[0], obj->stride);
9479 /* Reject formats not supported by any plane early. */
9480 switch (mode_cmd->pixel_format) {
9482 case DRM_FORMAT_RGB565:
9483 case DRM_FORMAT_XRGB8888:
9484 case DRM_FORMAT_ARGB8888:
9486 case DRM_FORMAT_XRGB1555:
9487 case DRM_FORMAT_ARGB1555:
9488 if (INTEL_INFO(dev)->gen > 3) {
9489 DRM_DEBUG("unsupported pixel format: %s\n",
9490 drm_get_format_name(mode_cmd->pixel_format));
9494 case DRM_FORMAT_XBGR8888:
9495 case DRM_FORMAT_ABGR8888:
9496 case DRM_FORMAT_XRGB2101010:
9497 case DRM_FORMAT_ARGB2101010:
9498 case DRM_FORMAT_XBGR2101010:
9499 case DRM_FORMAT_ABGR2101010:
9500 if (INTEL_INFO(dev)->gen < 4) {
9501 DRM_DEBUG("unsupported pixel format: %s\n",
9502 drm_get_format_name(mode_cmd->pixel_format));
9506 case DRM_FORMAT_YUYV:
9507 case DRM_FORMAT_UYVY:
9508 case DRM_FORMAT_YVYU:
9509 case DRM_FORMAT_VYUY:
9510 if (INTEL_INFO(dev)->gen < 5) {
9511 DRM_DEBUG("unsupported pixel format: %s\n",
9512 drm_get_format_name(mode_cmd->pixel_format));
9517 DRM_DEBUG("unsupported pixel format: %s\n",
9518 drm_get_format_name(mode_cmd->pixel_format));
9522 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9523 if (mode_cmd->offsets[0] != 0)
9526 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9527 intel_fb->obj = obj;
9529 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9531 DRM_ERROR("framebuffer init failed %d\n", ret);
9538 static struct drm_framebuffer *
9539 intel_user_framebuffer_create(struct drm_device *dev,
9540 struct drm_file *filp,
9541 struct drm_mode_fb_cmd2 *mode_cmd)
9543 struct drm_i915_gem_object *obj;
9545 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9546 mode_cmd->handles[0]));
9547 if (&obj->base == NULL)
9548 return ERR_PTR(-ENOENT);
9550 return intel_framebuffer_create(dev, mode_cmd, obj);
9553 static const struct drm_mode_config_funcs intel_mode_funcs = {
9554 .fb_create = intel_user_framebuffer_create,
9555 .output_poll_changed = intel_fb_output_poll_changed,
9558 /* Set up chip specific display functions */
9559 static void intel_init_display(struct drm_device *dev)
9561 struct drm_i915_private *dev_priv = dev->dev_private;
9563 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9564 dev_priv->display.find_dpll = g4x_find_best_dpll;
9565 else if (IS_VALLEYVIEW(dev))
9566 dev_priv->display.find_dpll = vlv_find_best_dpll;
9567 else if (IS_PINEVIEW(dev))
9568 dev_priv->display.find_dpll = pnv_find_best_dpll;
9570 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9573 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9574 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9575 dev_priv->display.crtc_enable = haswell_crtc_enable;
9576 dev_priv->display.crtc_disable = haswell_crtc_disable;
9577 dev_priv->display.off = haswell_crtc_off;
9578 dev_priv->display.update_plane = ironlake_update_plane;
9579 } else if (HAS_PCH_SPLIT(dev)) {
9580 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9581 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9582 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9583 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9584 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9585 dev_priv->display.off = ironlake_crtc_off;
9586 dev_priv->display.update_plane = ironlake_update_plane;
9587 } else if (IS_VALLEYVIEW(dev)) {
9588 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9589 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9590 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9591 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9592 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9593 dev_priv->display.off = i9xx_crtc_off;
9594 dev_priv->display.update_plane = i9xx_update_plane;
9596 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9597 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9598 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9599 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9600 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9601 dev_priv->display.off = i9xx_crtc_off;
9602 dev_priv->display.update_plane = i9xx_update_plane;
9605 /* Returns the core display clock speed */
9606 if (IS_VALLEYVIEW(dev))
9607 dev_priv->display.get_display_clock_speed =
9608 valleyview_get_display_clock_speed;
9609 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9610 dev_priv->display.get_display_clock_speed =
9611 i945_get_display_clock_speed;
9612 else if (IS_I915G(dev))
9613 dev_priv->display.get_display_clock_speed =
9614 i915_get_display_clock_speed;
9615 else if (IS_I945GM(dev) || IS_845G(dev))
9616 dev_priv->display.get_display_clock_speed =
9617 i9xx_misc_get_display_clock_speed;
9618 else if (IS_PINEVIEW(dev))
9619 dev_priv->display.get_display_clock_speed =
9620 pnv_get_display_clock_speed;
9621 else if (IS_I915GM(dev))
9622 dev_priv->display.get_display_clock_speed =
9623 i915gm_get_display_clock_speed;
9624 else if (IS_I865G(dev))
9625 dev_priv->display.get_display_clock_speed =
9626 i865_get_display_clock_speed;
9627 else if (IS_I85X(dev))
9628 dev_priv->display.get_display_clock_speed =
9629 i855_get_display_clock_speed;
9631 dev_priv->display.get_display_clock_speed =
9632 i830_get_display_clock_speed;
9634 if (HAS_PCH_SPLIT(dev)) {
9636 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9637 dev_priv->display.write_eld = ironlake_write_eld;
9638 } else if (IS_GEN6(dev)) {
9639 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9640 dev_priv->display.write_eld = ironlake_write_eld;
9641 } else if (IS_IVYBRIDGE(dev)) {
9642 /* FIXME: detect B0+ stepping and use auto training */
9643 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9644 dev_priv->display.write_eld = ironlake_write_eld;
9645 dev_priv->display.modeset_global_resources =
9646 ivb_modeset_global_resources;
9647 } else if (IS_HASWELL(dev)) {
9648 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9649 dev_priv->display.write_eld = haswell_write_eld;
9650 dev_priv->display.modeset_global_resources =
9651 haswell_modeset_global_resources;
9653 } else if (IS_G4X(dev)) {
9654 dev_priv->display.write_eld = g4x_write_eld;
9657 /* Default just returns -ENODEV to indicate unsupported */
9658 dev_priv->display.queue_flip = intel_default_queue_flip;
9660 switch (INTEL_INFO(dev)->gen) {
9662 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9666 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9671 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9675 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9678 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9684 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9685 * resume, or other times. This quirk makes sure that's the case for
9688 static void quirk_pipea_force(struct drm_device *dev)
9690 struct drm_i915_private *dev_priv = dev->dev_private;
9692 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9693 DRM_INFO("applying pipe a force quirk\n");
9697 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9699 static void quirk_ssc_force_disable(struct drm_device *dev)
9701 struct drm_i915_private *dev_priv = dev->dev_private;
9702 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9703 DRM_INFO("applying lvds SSC disable quirk\n");
9707 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9710 static void quirk_invert_brightness(struct drm_device *dev)
9712 struct drm_i915_private *dev_priv = dev->dev_private;
9713 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9714 DRM_INFO("applying inverted panel brightness quirk\n");
9718 * Some machines (Dell XPS13) suffer broken backlight controls if
9719 * BLM_PCH_PWM_ENABLE is set.
9721 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9723 struct drm_i915_private *dev_priv = dev->dev_private;
9724 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9725 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9728 struct intel_quirk {
9730 int subsystem_vendor;
9731 int subsystem_device;
9732 void (*hook)(struct drm_device *dev);
9735 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9736 struct intel_dmi_quirk {
9737 void (*hook)(struct drm_device *dev);
9738 const struct dmi_system_id (*dmi_id_list)[];
9741 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9743 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9747 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9749 .dmi_id_list = &(const struct dmi_system_id[]) {
9751 .callback = intel_dmi_reverse_brightness,
9752 .ident = "NCR Corporation",
9753 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9754 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9757 { } /* terminating entry */
9759 .hook = quirk_invert_brightness,
9763 static struct intel_quirk intel_quirks[] = {
9764 /* HP Mini needs pipe A force quirk (LP: #322104) */
9765 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9767 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9768 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9770 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9771 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9773 /* 830/845 need to leave pipe A & dpll A up */
9774 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9775 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9777 /* Lenovo U160 cannot use SSC on LVDS */
9778 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9780 /* Sony Vaio Y cannot use SSC on LVDS */
9781 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9783 /* Acer Aspire 5734Z must invert backlight brightness */
9784 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9786 /* Acer/eMachines G725 */
9787 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9789 /* Acer/eMachines e725 */
9790 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9792 /* Acer/Packard Bell NCL20 */
9793 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9795 /* Acer Aspire 4736Z */
9796 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9798 /* Dell XPS13 HD Sandy Bridge */
9799 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9800 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9801 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9804 static void intel_init_quirks(struct drm_device *dev)
9806 struct pci_dev *d = dev->pdev;
9809 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9810 struct intel_quirk *q = &intel_quirks[i];
9812 if (d->device == q->device &&
9813 (d->subsystem_vendor == q->subsystem_vendor ||
9814 q->subsystem_vendor == PCI_ANY_ID) &&
9815 (d->subsystem_device == q->subsystem_device ||
9816 q->subsystem_device == PCI_ANY_ID))
9819 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9820 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9821 intel_dmi_quirks[i].hook(dev);
9825 /* Disable the VGA plane that we never use */
9826 static void i915_disable_vga(struct drm_device *dev)
9828 struct drm_i915_private *dev_priv = dev->dev_private;
9830 u32 vga_reg = i915_vgacntrl_reg(dev);
9832 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9833 outb(SR01, VGA_SR_INDEX);
9834 sr1 = inb(VGA_SR_DATA);
9835 outb(sr1 | 1<<5, VGA_SR_DATA);
9836 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9839 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9840 POSTING_READ(vga_reg);
9843 void intel_modeset_init_hw(struct drm_device *dev)
9845 intel_init_power_well(dev);
9847 intel_prepare_ddi(dev);
9849 intel_init_clock_gating(dev);
9851 mutex_lock(&dev->struct_mutex);
9852 intel_enable_gt_powersave(dev);
9853 mutex_unlock(&dev->struct_mutex);
9856 void intel_modeset_suspend_hw(struct drm_device *dev)
9858 intel_suspend_hw(dev);
9861 void intel_modeset_init(struct drm_device *dev)
9863 struct drm_i915_private *dev_priv = dev->dev_private;
9866 drm_mode_config_init(dev);
9868 dev->mode_config.min_width = 0;
9869 dev->mode_config.min_height = 0;
9871 dev->mode_config.preferred_depth = 24;
9872 dev->mode_config.prefer_shadow = 1;
9874 dev->mode_config.funcs = &intel_mode_funcs;
9876 intel_init_quirks(dev);
9880 if (INTEL_INFO(dev)->num_pipes == 0)
9883 intel_init_display(dev);
9886 dev->mode_config.max_width = 2048;
9887 dev->mode_config.max_height = 2048;
9888 } else if (IS_GEN3(dev)) {
9889 dev->mode_config.max_width = 4096;
9890 dev->mode_config.max_height = 4096;
9892 dev->mode_config.max_width = 8192;
9893 dev->mode_config.max_height = 8192;
9895 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9897 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9898 INTEL_INFO(dev)->num_pipes,
9899 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9902 intel_crtc_init(dev, i);
9903 for (j = 0; j < dev_priv->num_plane; j++) {
9904 ret = intel_plane_init(dev, i, j);
9906 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9907 pipe_name(i), sprite_name(i, j), ret);
9911 intel_cpu_pll_init(dev);
9912 intel_shared_dpll_init(dev);
9914 /* Just disable it once at startup */
9915 i915_disable_vga(dev);
9916 intel_setup_outputs(dev);
9918 /* Just in case the BIOS is doing something questionable. */
9919 intel_disable_fbc(dev);
9923 intel_connector_break_all_links(struct intel_connector *connector)
9925 connector->base.dpms = DRM_MODE_DPMS_OFF;
9926 connector->base.encoder = NULL;
9927 connector->encoder->connectors_active = false;
9928 connector->encoder->base.crtc = NULL;
9931 static void intel_enable_pipe_a(struct drm_device *dev)
9933 struct intel_connector *connector;
9934 struct drm_connector *crt = NULL;
9935 struct intel_load_detect_pipe load_detect_temp;
9937 /* We can't just switch on the pipe A, we need to set things up with a
9938 * proper mode and output configuration. As a gross hack, enable pipe A
9939 * by enabling the load detect pipe once. */
9940 list_for_each_entry(connector,
9941 &dev->mode_config.connector_list,
9943 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9944 crt = &connector->base;
9952 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9953 intel_release_load_detect_pipe(crt, &load_detect_temp);
9959 intel_check_plane_mapping(struct intel_crtc *crtc)
9961 struct drm_device *dev = crtc->base.dev;
9962 struct drm_i915_private *dev_priv = dev->dev_private;
9965 if (INTEL_INFO(dev)->num_pipes == 1)
9968 reg = DSPCNTR(!crtc->plane);
9969 val = I915_READ(reg);
9971 if ((val & DISPLAY_PLANE_ENABLE) &&
9972 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9978 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9980 struct drm_device *dev = crtc->base.dev;
9981 struct drm_i915_private *dev_priv = dev->dev_private;
9984 /* Clear any frame start delays used for debugging left by the BIOS */
9985 reg = PIPECONF(crtc->config.cpu_transcoder);
9986 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9988 /* We need to sanitize the plane -> pipe mapping first because this will
9989 * disable the crtc (and hence change the state) if it is wrong. Note
9990 * that gen4+ has a fixed plane -> pipe mapping. */
9991 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9992 struct intel_connector *connector;
9995 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9996 crtc->base.base.id);
9998 /* Pipe has the wrong plane attached and the plane is active.
9999 * Temporarily change the plane mapping and disable everything
10001 plane = crtc->plane;
10002 crtc->plane = !plane;
10003 dev_priv->display.crtc_disable(&crtc->base);
10004 crtc->plane = plane;
10006 /* ... and break all links. */
10007 list_for_each_entry(connector, &dev->mode_config.connector_list,
10009 if (connector->encoder->base.crtc != &crtc->base)
10012 intel_connector_break_all_links(connector);
10015 WARN_ON(crtc->active);
10016 crtc->base.enabled = false;
10019 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10020 crtc->pipe == PIPE_A && !crtc->active) {
10021 /* BIOS forgot to enable pipe A, this mostly happens after
10022 * resume. Force-enable the pipe to fix this, the update_dpms
10023 * call below we restore the pipe to the right state, but leave
10024 * the required bits on. */
10025 intel_enable_pipe_a(dev);
10028 /* Adjust the state of the output pipe according to whether we
10029 * have active connectors/encoders. */
10030 intel_crtc_update_dpms(&crtc->base);
10032 if (crtc->active != crtc->base.enabled) {
10033 struct intel_encoder *encoder;
10035 /* This can happen either due to bugs in the get_hw_state
10036 * functions or because the pipe is force-enabled due to the
10038 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10039 crtc->base.base.id,
10040 crtc->base.enabled ? "enabled" : "disabled",
10041 crtc->active ? "enabled" : "disabled");
10043 crtc->base.enabled = crtc->active;
10045 /* Because we only establish the connector -> encoder ->
10046 * crtc links if something is active, this means the
10047 * crtc is now deactivated. Break the links. connector
10048 * -> encoder links are only establish when things are
10049 * actually up, hence no need to break them. */
10050 WARN_ON(crtc->active);
10052 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10053 WARN_ON(encoder->connectors_active);
10054 encoder->base.crtc = NULL;
10059 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10061 struct intel_connector *connector;
10062 struct drm_device *dev = encoder->base.dev;
10064 /* We need to check both for a crtc link (meaning that the
10065 * encoder is active and trying to read from a pipe) and the
10066 * pipe itself being active. */
10067 bool has_active_crtc = encoder->base.crtc &&
10068 to_intel_crtc(encoder->base.crtc)->active;
10070 if (encoder->connectors_active && !has_active_crtc) {
10071 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10072 encoder->base.base.id,
10073 drm_get_encoder_name(&encoder->base));
10075 /* Connector is active, but has no active pipe. This is
10076 * fallout from our resume register restoring. Disable
10077 * the encoder manually again. */
10078 if (encoder->base.crtc) {
10079 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10080 encoder->base.base.id,
10081 drm_get_encoder_name(&encoder->base));
10082 encoder->disable(encoder);
10085 /* Inconsistent output/port/pipe state happens presumably due to
10086 * a bug in one of the get_hw_state functions. Or someplace else
10087 * in our code, like the register restore mess on resume. Clamp
10088 * things to off as a safer default. */
10089 list_for_each_entry(connector,
10090 &dev->mode_config.connector_list,
10092 if (connector->encoder != encoder)
10095 intel_connector_break_all_links(connector);
10098 /* Enabled encoders without active connectors will be fixed in
10099 * the crtc fixup. */
10102 void i915_redisable_vga(struct drm_device *dev)
10104 struct drm_i915_private *dev_priv = dev->dev_private;
10105 u32 vga_reg = i915_vgacntrl_reg(dev);
10107 /* This function can be called both from intel_modeset_setup_hw_state or
10108 * at a very early point in our resume sequence, where the power well
10109 * structures are not yet restored. Since this function is at a very
10110 * paranoid "someone might have enabled VGA while we were not looking"
10111 * level, just check if the power well is enabled instead of trying to
10112 * follow the "don't touch the power well if we don't need it" policy
10113 * the rest of the driver uses. */
10114 if (HAS_POWER_WELL(dev) &&
10115 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE) == 0)
10118 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10119 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10120 i915_disable_vga(dev);
10124 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10126 struct drm_i915_private *dev_priv = dev->dev_private;
10128 struct intel_crtc *crtc;
10129 struct intel_encoder *encoder;
10130 struct intel_connector *connector;
10133 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10135 memset(&crtc->config, 0, sizeof(crtc->config));
10137 crtc->active = dev_priv->display.get_pipe_config(crtc,
10140 crtc->base.enabled = crtc->active;
10142 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10143 crtc->base.base.id,
10144 crtc->active ? "enabled" : "disabled");
10147 /* FIXME: Smash this into the new shared dpll infrastructure. */
10149 intel_ddi_setup_hw_pll_state(dev);
10151 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10152 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10154 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10156 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10158 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10161 pll->refcount = pll->active;
10163 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10164 pll->name, pll->refcount, pll->on);
10167 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10171 if (encoder->get_hw_state(encoder, &pipe)) {
10172 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10173 encoder->base.crtc = &crtc->base;
10174 if (encoder->get_config)
10175 encoder->get_config(encoder, &crtc->config);
10177 encoder->base.crtc = NULL;
10180 encoder->connectors_active = false;
10181 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10182 encoder->base.base.id,
10183 drm_get_encoder_name(&encoder->base),
10184 encoder->base.crtc ? "enabled" : "disabled",
10188 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10192 if (dev_priv->display.get_clock)
10193 dev_priv->display.get_clock(crtc,
10197 list_for_each_entry(connector, &dev->mode_config.connector_list,
10199 if (connector->get_hw_state(connector)) {
10200 connector->base.dpms = DRM_MODE_DPMS_ON;
10201 connector->encoder->connectors_active = true;
10202 connector->base.encoder = &connector->encoder->base;
10204 connector->base.dpms = DRM_MODE_DPMS_OFF;
10205 connector->base.encoder = NULL;
10207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10208 connector->base.base.id,
10209 drm_get_connector_name(&connector->base),
10210 connector->base.encoder ? "enabled" : "disabled");
10214 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10215 * and i915 state tracking structures. */
10216 void intel_modeset_setup_hw_state(struct drm_device *dev,
10217 bool force_restore)
10219 struct drm_i915_private *dev_priv = dev->dev_private;
10221 struct drm_plane *plane;
10222 struct intel_crtc *crtc;
10223 struct intel_encoder *encoder;
10226 intel_modeset_readout_hw_state(dev);
10229 * Now that we have the config, copy it to each CRTC struct
10230 * Note that this could go away if we move to using crtc_config
10231 * checking everywhere.
10233 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10235 if (crtc->active && i915_fastboot) {
10236 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10238 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10239 crtc->base.base.id);
10240 drm_mode_debug_printmodeline(&crtc->base.mode);
10244 /* HW state is read out, now we need to sanitize this mess. */
10245 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10247 intel_sanitize_encoder(encoder);
10250 for_each_pipe(pipe) {
10251 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10252 intel_sanitize_crtc(crtc);
10253 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10256 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10257 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10259 if (!pll->on || pll->active)
10262 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10264 pll->disable(dev_priv, pll);
10268 if (force_restore) {
10270 * We need to use raw interfaces for restoring state to avoid
10271 * checking (bogus) intermediate states.
10273 for_each_pipe(pipe) {
10274 struct drm_crtc *crtc =
10275 dev_priv->pipe_to_crtc_mapping[pipe];
10277 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10280 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10281 intel_plane_restore(plane);
10283 i915_redisable_vga(dev);
10285 intel_modeset_update_staged_output_state(dev);
10288 intel_modeset_check_state(dev);
10290 drm_mode_config_reset(dev);
10293 void intel_modeset_gem_init(struct drm_device *dev)
10295 intel_modeset_init_hw(dev);
10297 intel_setup_overlay(dev);
10299 intel_modeset_setup_hw_state(dev, false);
10302 void intel_modeset_cleanup(struct drm_device *dev)
10304 struct drm_i915_private *dev_priv = dev->dev_private;
10305 struct drm_crtc *crtc;
10308 * Interrupts and polling as the first thing to avoid creating havoc.
10309 * Too much stuff here (turning of rps, connectors, ...) would
10310 * experience fancy races otherwise.
10312 drm_irq_uninstall(dev);
10313 cancel_work_sync(&dev_priv->hotplug_work);
10315 * Due to the hpd irq storm handling the hotplug work can re-arm the
10316 * poll handlers. Hence disable polling after hpd handling is shut down.
10318 drm_kms_helper_poll_fini(dev);
10320 mutex_lock(&dev->struct_mutex);
10322 intel_unregister_dsm_handler();
10324 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10325 /* Skip inactive CRTCs */
10329 intel_increase_pllclock(crtc);
10332 intel_disable_fbc(dev);
10334 intel_disable_gt_powersave(dev);
10336 ironlake_teardown_rc6(dev);
10338 mutex_unlock(&dev->struct_mutex);
10340 /* flush any delayed tasks or pending work */
10341 flush_scheduled_work();
10343 /* destroy backlight, if any, before the connectors */
10344 intel_panel_destroy_backlight(dev);
10346 drm_mode_config_cleanup(dev);
10348 intel_cleanup_overlay(dev);
10352 * Return which encoder is currently attached for connector.
10354 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10356 return &intel_attached_encoder(connector)->base;
10359 void intel_connector_attach_encoder(struct intel_connector *connector,
10360 struct intel_encoder *encoder)
10362 connector->encoder = encoder;
10363 drm_mode_connector_attach_encoder(&connector->base,
10368 * set vga decode state - true == enable VGA decode
10370 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10372 struct drm_i915_private *dev_priv = dev->dev_private;
10375 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10377 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10379 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10380 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10384 struct intel_display_error_state {
10386 u32 power_well_driver;
10388 struct intel_cursor_error_state {
10393 } cursor[I915_MAX_PIPES];
10395 struct intel_pipe_error_state {
10396 enum transcoder cpu_transcoder;
10406 } pipe[I915_MAX_PIPES];
10408 struct intel_plane_error_state {
10416 } plane[I915_MAX_PIPES];
10419 struct intel_display_error_state *
10420 intel_display_capture_error_state(struct drm_device *dev)
10422 drm_i915_private_t *dev_priv = dev->dev_private;
10423 struct intel_display_error_state *error;
10424 enum transcoder cpu_transcoder;
10427 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10431 if (HAS_POWER_WELL(dev))
10432 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10435 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10436 error->pipe[i].cpu_transcoder = cpu_transcoder;
10438 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10439 error->cursor[i].control = I915_READ(CURCNTR(i));
10440 error->cursor[i].position = I915_READ(CURPOS(i));
10441 error->cursor[i].base = I915_READ(CURBASE(i));
10443 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10444 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10445 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10448 error->plane[i].control = I915_READ(DSPCNTR(i));
10449 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10450 if (INTEL_INFO(dev)->gen <= 3) {
10451 error->plane[i].size = I915_READ(DSPSIZE(i));
10452 error->plane[i].pos = I915_READ(DSPPOS(i));
10454 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10455 error->plane[i].addr = I915_READ(DSPADDR(i));
10456 if (INTEL_INFO(dev)->gen >= 4) {
10457 error->plane[i].surface = I915_READ(DSPSURF(i));
10458 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10461 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10462 error->pipe[i].source = I915_READ(PIPESRC(i));
10463 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10464 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10465 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10466 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10467 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10468 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10471 /* In the code above we read the registers without checking if the power
10472 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10473 * prevent the next I915_WRITE from detecting it and printing an error
10475 intel_uncore_clear_errors(dev);
10480 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10483 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10484 struct drm_device *dev,
10485 struct intel_display_error_state *error)
10489 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10490 if (HAS_POWER_WELL(dev))
10491 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10492 error->power_well_driver);
10494 err_printf(m, "Pipe [%d]:\n", i);
10495 err_printf(m, " CPU transcoder: %c\n",
10496 transcoder_name(error->pipe[i].cpu_transcoder));
10497 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10498 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10499 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10500 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10501 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10502 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10503 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10504 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10506 err_printf(m, "Plane [%d]:\n", i);
10507 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10508 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10509 if (INTEL_INFO(dev)->gen <= 3) {
10510 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10511 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10513 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10514 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10515 if (INTEL_INFO(dev)->gen >= 4) {
10516 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10517 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10520 err_printf(m, "Cursor [%d]:\n", i);
10521 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10522 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10523 err_printf(m, " BASE: %08x\n", error->cursor[i].base);