2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
186 .find_pll = intel_g4x_find_best_PLL,
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
215 .find_pll = intel_g4x_find_best_PLL,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
230 .find_pll = intel_g4x_find_best_PLL,
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val = I915_READ(DPIO_DATA);
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
456 static void vlv_init_dpio(struct drm_device *dev)
458 struct drm_i915_private *dev_priv = dev->dev_private;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
494 if (dmi_check_system(intel_dual_link_lvds))
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
526 limit = &intel_limits_ironlake_dual_lvds;
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
531 limit = &intel_limits_ironlake_single_lvds;
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
535 limit = &intel_limits_ironlake_display_port;
537 limit = &intel_limits_ironlake_dac;
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
593 limit = &intel_limits_i9xx_sdvo;
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
598 limit = &intel_limits_i8xx_dvo;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
696 clock.p2 = limit->p2.p2_slow;
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
701 clock.p2 = limit->p2.p2_fast;
704 memset(best_clock, 0, sizeof(*best_clock));
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
724 clock.p != match_clock->p)
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
737 return (err != target);
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
757 if (HAS_PCH_SPLIT(dev))
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
763 clock.p2 = limit->p2.p2_fast;
765 clock.p2 = limit->p2.p2_slow;
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
770 clock.p2 = limit->p2.p2_fast;
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
791 clock.p != match_clock->p)
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
813 struct drm_device *dev = crtc->dev;
816 if (target < 200000) {
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
841 if (target < 200000) {
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
873 dotclk = target * 1000;
876 fastclk = dotclk / (2*100);
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
904 if (absppm < bestppm - 10) {
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
935 frame = I915_READ(frame_reg);
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 /* Wait for the display line to settle */
1022 last_line = I915_READ(reg) & line_mask;
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled)
1033 return enabled ? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1183 int pp_reg, lvds_reg;
1185 enum pipe panel_pipe = PIPE_A;
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1192 pp_reg = PP_CONTROL;
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1309 if ((val & DP_PORT_EN) == 0)
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1327 if ((val & PORT_ENABLE) == 0)
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1343 if ((val & LVDS_PORT_EN) == 0)
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1431 * Note! This is for pre-ILK only.
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1460 udelay(150); /* wait for warmup */
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1470 * Note! This is for pre-ILK only.
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1495 unsigned long flags;
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1504 I915_WRITE(SBI_ADDR,
1506 I915_WRITE(SBI_DATA,
1508 I915_WRITE(SBI_CTL_STAT,
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1525 unsigned long flags;
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1535 I915_WRITE(SBI_ADDR,
1537 I915_WRITE(SBI_CTL_STAT,
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1547 value = I915_READ(SBI_DATA);
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1575 if (WARN_ON(pll->refcount == 0))
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1614 if (WARN_ON(pll->refcount == 0))
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1688 val |= TRANS_INTERLACED;
1690 val |= TRANS_PROGRESSIVE;
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728 * @pipe should be %PIPE_A or %PIPE_B.
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1752 /* FIXME: assert CPU port conditions for SNB+ */
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 * @pipe should be %PIPE_A or %PIPE_B.
1774 * Will wait until the pipe has shut down before returning.
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1786 assert_planes_disabled(dev_priv, pipe);
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1845 * Disable @plane; should be an independent operation.
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1932 alignment = 64 * 1024;
1935 /* pin() will align the object as required by fence */
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1949 goto err_interruptible;
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1956 ret = i915_gem_object_get_fence(obj);
1960 i915_gem_object_pin_fence(obj);
1962 dev_priv->mm.interruptible = true;
1966 i915_gem_object_unpin(obj);
1968 dev_priv->mm.interruptible = true;
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1984 int tile_rows, tiles;
1988 tiles = *x / (512/bpp);
1991 return tile_rows * pitch * 8 + tiles * 4096;
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2025 dspcntr |= DISPPLANE_8BPP;
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2031 dspcntr |= DISPPLANE_16BPP;
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2045 dspcntr &= ~DISPPLANE_TILED;
2048 I915_WRITE(reg, dspcntr);
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2057 linear_offset -= intel_crtc->dspaddr_offset;
2059 intel_crtc->dspaddr_offset = linear_offset;
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2109 dspcntr |= DISPPLANE_8BPP;
2112 if (fb->depth != 16)
2115 dspcntr |= DISPPLANE_16BPP;
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2134 dspcntr &= ~DISPPLANE_TILED;
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2139 I915_WRITE(reg, dspcntr);
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2146 linear_offset -= intel_crtc->dspaddr_offset;
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *fb)
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 struct drm_framebuffer *old_fb;
2215 DRM_ERROR("No FB bound\n");
2219 if(intel_crtc->plane > dev_priv->num_pipe) {
2220 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2222 dev_priv->num_pipe);
2226 mutex_lock(&dev->struct_mutex);
2227 ret = intel_pin_and_fence_fb_obj(dev,
2228 to_intel_framebuffer(fb)->obj,
2231 mutex_unlock(&dev->struct_mutex);
2232 DRM_ERROR("pin & fence failed\n");
2237 intel_finish_fb(crtc->fb);
2239 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2241 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2242 mutex_unlock(&dev->struct_mutex);
2243 DRM_ERROR("failed to update base address\n");
2251 intel_wait_for_vblank(dev, intel_crtc->pipe);
2252 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2255 intel_update_fbc(dev);
2256 mutex_unlock(&dev->struct_mutex);
2258 if (!dev->primary->master)
2261 master_priv = dev->primary->master->driver_priv;
2262 if (!master_priv->sarea_priv)
2265 if (intel_crtc->pipe) {
2266 master_priv->sarea_priv->pipeB_x = x;
2267 master_priv->sarea_priv->pipeB_y = y;
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
2276 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2278 struct drm_device *dev = crtc->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2282 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2283 dpa_ctl = I915_READ(DP_A);
2284 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2286 if (clock < 200000) {
2288 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2289 /* workaround for 160Mhz:
2290 1) program 0x4600c bits 15:0 = 0x8124
2291 2) program 0x46010 bit 0 = 1
2292 3) program 0x46034 bit 24 = 1
2293 4) program 0x64000 bit 14 = 1
2295 temp = I915_READ(0x4600c);
2297 I915_WRITE(0x4600c, temp | 0x8124);
2299 temp = I915_READ(0x46010);
2300 I915_WRITE(0x46010, temp | 1);
2302 temp = I915_READ(0x46034);
2303 I915_WRITE(0x46034, temp | (1 << 24));
2305 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2307 I915_WRITE(DP_A, dpa_ctl);
2313 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2315 struct drm_device *dev = crtc->dev;
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318 int pipe = intel_crtc->pipe;
2321 /* enable normal train */
2322 reg = FDI_TX_CTL(pipe);
2323 temp = I915_READ(reg);
2324 if (IS_IVYBRIDGE(dev)) {
2325 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2326 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2328 temp &= ~FDI_LINK_TRAIN_NONE;
2329 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2331 I915_WRITE(reg, temp);
2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 if (HAS_PCH_CPT(dev)) {
2336 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2337 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2339 temp &= ~FDI_LINK_TRAIN_NONE;
2340 temp |= FDI_LINK_TRAIN_NONE;
2342 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2344 /* wait one idle pattern time */
2348 /* IVB wants error correction enabled */
2349 if (IS_IVYBRIDGE(dev))
2350 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2351 FDI_FE_ERRC_ENABLE);
2354 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 flags = I915_READ(SOUTH_CHICKEN1);
2359 flags |= FDI_PHASE_SYNC_OVR(pipe);
2360 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2361 flags |= FDI_PHASE_SYNC_EN(pipe);
2362 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2363 POSTING_READ(SOUTH_CHICKEN1);
2366 /* The FDI link training functions for ILK/Ibexpeak. */
2367 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2369 struct drm_device *dev = crtc->dev;
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372 int pipe = intel_crtc->pipe;
2373 int plane = intel_crtc->plane;
2374 u32 reg, temp, tries;
2376 /* FDI needs bits from pipe & plane first */
2377 assert_pipe_enabled(dev_priv, pipe);
2378 assert_plane_enabled(dev_priv, plane);
2380 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2382 reg = FDI_RX_IMR(pipe);
2383 temp = I915_READ(reg);
2384 temp &= ~FDI_RX_SYMBOL_LOCK;
2385 temp &= ~FDI_RX_BIT_LOCK;
2386 I915_WRITE(reg, temp);
2390 /* enable CPU FDI TX and PCH FDI RX */
2391 reg = FDI_TX_CTL(pipe);
2392 temp = I915_READ(reg);
2394 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
2397 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_1;
2403 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2408 /* Ironlake workaround, enable clock pointer after FDI enable*/
2409 if (HAS_PCH_IBX(dev)) {
2410 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2411 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2412 FDI_RX_PHASE_SYNC_POINTER_EN);
2415 reg = FDI_RX_IIR(pipe);
2416 for (tries = 0; tries < 5; tries++) {
2417 temp = I915_READ(reg);
2418 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2420 if ((temp & FDI_RX_BIT_LOCK)) {
2421 DRM_DEBUG_KMS("FDI train 1 done.\n");
2422 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2427 DRM_ERROR("FDI train 1 fail!\n");
2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
2434 I915_WRITE(reg, temp);
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_2;
2440 I915_WRITE(reg, temp);
2445 reg = FDI_RX_IIR(pipe);
2446 for (tries = 0; tries < 5; tries++) {
2447 temp = I915_READ(reg);
2448 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_SYMBOL_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2452 DRM_DEBUG_KMS("FDI train 2 done.\n");
2457 DRM_ERROR("FDI train 2 fail!\n");
2459 DRM_DEBUG_KMS("FDI train done\n");
2463 static const int snb_b_fdi_train_param[] = {
2464 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2465 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2466 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2467 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2470 /* The FDI link training functions for SNB/Cougarpoint. */
2471 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2473 struct drm_device *dev = crtc->dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476 int pipe = intel_crtc->pipe;
2477 u32 reg, temp, i, retry;
2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
2485 I915_WRITE(reg, temp);
2490 /* enable CPU FDI TX and PCH FDI RX */
2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
2494 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1;
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2499 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2500 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2511 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2516 if (HAS_PCH_CPT(dev))
2517 cpt_phase_pointer_enable(dev, pipe);
2519 for (i = 0; i < 4; i++) {
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523 temp |= snb_b_fdi_train_param[i];
2524 I915_WRITE(reg, temp);
2529 for (retry = 0; retry < 5; retry++) {
2530 reg = FDI_RX_IIR(pipe);
2531 temp = I915_READ(reg);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533 if (temp & FDI_RX_BIT_LOCK) {
2534 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2535 DRM_DEBUG_KMS("FDI train 1 done.\n");
2544 DRM_ERROR("FDI train 1 fail!\n");
2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
2549 temp &= ~FDI_LINK_TRAIN_NONE;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 I915_WRITE(reg, temp);
2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 if (HAS_PCH_CPT(dev)) {
2561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 I915_WRITE(reg, temp);
2572 for (i = 0; i < 4; i++) {
2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
2575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576 temp |= snb_b_fdi_train_param[i];
2577 I915_WRITE(reg, temp);
2582 for (retry = 0; retry < 5; retry++) {
2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586 if (temp & FDI_RX_SYMBOL_LOCK) {
2587 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2588 DRM_DEBUG_KMS("FDI train 2 done.\n");
2597 DRM_ERROR("FDI train 2 fail!\n");
2599 DRM_DEBUG_KMS("FDI train done.\n");
2602 /* Manual link training for Ivy Bridge A0 parts */
2603 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2605 struct drm_device *dev = crtc->dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 int pipe = intel_crtc->pipe;
2611 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2613 reg = FDI_RX_IMR(pipe);
2614 temp = I915_READ(reg);
2615 temp &= ~FDI_RX_SYMBOL_LOCK;
2616 temp &= ~FDI_RX_BIT_LOCK;
2617 I915_WRITE(reg, temp);
2622 /* enable CPU FDI TX and PCH FDI RX */
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2626 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2628 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2631 temp |= FDI_COMPOSITE_SYNC;
2632 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_AUTO;
2637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2639 temp |= FDI_COMPOSITE_SYNC;
2640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2645 if (HAS_PCH_CPT(dev))
2646 cpt_phase_pointer_enable(dev, pipe);
2648 for (i = 0; i < 4; i++) {
2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
2653 I915_WRITE(reg, temp);
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2662 if (temp & FDI_RX_BIT_LOCK ||
2663 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done.\n");
2670 DRM_ERROR("FDI train 1 fail!\n");
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2679 I915_WRITE(reg, temp);
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685 I915_WRITE(reg, temp);
2690 for (i = 0; i < 4; i++) {
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2704 if (temp & FDI_RX_SYMBOL_LOCK) {
2705 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2706 DRM_DEBUG_KMS("FDI train 2 done.\n");
2711 DRM_ERROR("FDI train 2 fail!\n");
2713 DRM_DEBUG_KMS("FDI train done.\n");
2716 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2718 struct drm_device *dev = intel_crtc->base.dev;
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720 int pipe = intel_crtc->pipe;
2723 /* Write the TU size bits so error detection works */
2724 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2725 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2727 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~((0x7 << 19) | (0x7 << 16));
2731 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2732 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2733 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2738 /* Switch from Rawclk to PCDclk */
2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp | FDI_PCDCLK);
2745 /* On Haswell, the PLL configuration for ports and pipes is handled
2746 * separately, as part of DDI setup */
2747 if (!IS_HASWELL(dev)) {
2748 /* Enable CPU FDI TX PLL, always on for Ironlake */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2760 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2762 struct drm_device *dev = intel_crtc->base.dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 int pipe = intel_crtc->pipe;
2767 /* Switch from PCDclk to Rawclk */
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2772 /* Disable CPU FDI TX PLL */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2784 /* Wait for the clocks to turn off. */
2789 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 u32 flags = I915_READ(SOUTH_CHICKEN1);
2794 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2796 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2797 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2798 POSTING_READ(SOUTH_CHICKEN1);
2800 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 int pipe = intel_crtc->pipe;
2808 /* disable CPU FDI tx and PCH FDI rx */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~(0x7 << 16);
2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2823 /* Ironlake workaround, disable clock pointer after downing FDI */
2824 if (HAS_PCH_IBX(dev)) {
2825 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2826 I915_WRITE(FDI_RX_CHICKEN(pipe),
2827 I915_READ(FDI_RX_CHICKEN(pipe) &
2828 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2829 } else if (HAS_PCH_CPT(dev)) {
2830 cpt_phase_pointer_disable(dev, pipe);
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2852 I915_WRITE(reg, temp);
2858 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2860 struct drm_device *dev = crtc->dev;
2862 if (crtc->fb == NULL)
2865 mutex_lock(&dev->struct_mutex);
2866 intel_finish_fb(crtc->fb);
2867 mutex_unlock(&dev->struct_mutex);
2870 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2872 struct drm_device *dev = crtc->dev;
2873 struct intel_encoder *intel_encoder;
2876 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2877 * must be driven by its own crtc; no sharing is possible.
2879 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2881 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2882 * CPU handles all others */
2883 if (IS_HASWELL(dev)) {
2884 /* It is still unclear how this will work on PPT, so throw up a warning */
2885 WARN_ON(!HAS_PCH_LPT(dev));
2887 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2888 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2891 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2892 intel_encoder->type);
2897 switch (intel_encoder->type) {
2898 case INTEL_OUTPUT_EDP:
2899 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2908 /* Program iCLKIP clock to the desired frequency */
2909 static void lpt_program_iclkip(struct drm_crtc *crtc)
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 /* It is necessary to ungate the pixclk gate prior to programming
2917 * the divisors, and gate it back when it is done.
2919 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2921 /* Disable SSCCTL */
2922 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2923 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2924 SBI_SSCCTL_DISABLE);
2926 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927 if (crtc->mode.clock == 20000) {
2932 /* The iCLK virtual clock root frequency is in MHz,
2933 * but the crtc->mode.clock in in KHz. To get the divisors,
2934 * it is necessary to divide one by another, so we
2935 * convert the virtual clock precision to KHz here for higher
2938 u32 iclk_virtual_root_freq = 172800 * 1000;
2939 u32 iclk_pi_range = 64;
2940 u32 desired_divisor, msb_divisor_value, pi_value;
2942 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943 msb_divisor_value = desired_divisor / iclk_pi_range;
2944 pi_value = desired_divisor % iclk_pi_range;
2947 divsel = msb_divisor_value - 2;
2948 phaseinc = pi_value;
2951 /* This should not happen with any sane values */
2952 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2957 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2964 /* Program SSCDIVINTPHASE6 */
2965 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2966 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2973 intel_sbi_write(dev_priv,
2974 SBI_SSCDIVINTPHASE6,
2977 /* Program SSCAUXDIV */
2978 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2979 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2980 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2981 intel_sbi_write(dev_priv,
2986 /* Enable modulator and associated divider */
2987 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2988 temp &= ~SBI_SSCCTL_DISABLE;
2989 intel_sbi_write(dev_priv,
2993 /* Wait for initialization time */
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3000 * Enable PCH resources required for PCH ports:
3002 * - FDI training & RX/TX
3003 * - update transcoder timings
3004 * - DP transcoding bits
3007 static void ironlake_pch_enable(struct drm_crtc *crtc)
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012 int pipe = intel_crtc->pipe;
3015 assert_transcoder_disabled(dev_priv, pipe);
3017 /* For PCH output, training FDI link */
3018 dev_priv->display.fdi_link_train(crtc);
3020 intel_enable_pch_pll(intel_crtc);
3022 if (HAS_PCH_LPT(dev)) {
3023 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3024 lpt_program_iclkip(crtc);
3025 } else if (HAS_PCH_CPT(dev)) {
3028 temp = I915_READ(PCH_DPLL_SEL);
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3048 I915_WRITE(PCH_DPLL_SEL, temp);
3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3062 if (!IS_HASWELL(dev))
3063 intel_fdi_normal_train(crtc);
3065 /* For PCH DP, enable TRANS_DP_CTL */
3066 if (HAS_PCH_CPT(dev) &&
3067 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3068 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3069 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3070 reg = TRANS_DP_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3073 TRANS_DP_SYNC_MASK |
3075 temp |= (TRANS_DP_OUTPUT_ENABLE |
3076 TRANS_DP_ENH_FRAMING);
3077 temp |= bpc << 9; /* same format but at 11:9 */
3079 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3080 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3081 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3082 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3084 switch (intel_trans_dp_port_sel(crtc)) {
3086 temp |= TRANS_DP_PORT_SEL_B;
3089 temp |= TRANS_DP_PORT_SEL_C;
3092 temp |= TRANS_DP_PORT_SEL_D;
3095 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3096 temp |= TRANS_DP_PORT_SEL_B;
3100 I915_WRITE(reg, temp);
3103 intel_enable_transcoder(dev_priv, pipe);
3106 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3108 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3113 if (pll->refcount == 0) {
3114 WARN(1, "bad PCH PLL refcount\n");
3119 intel_crtc->pch_pll = NULL;
3122 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3124 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3125 struct intel_pch_pll *pll;
3128 pll = intel_crtc->pch_pll;
3130 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3131 intel_crtc->base.base.id, pll->pll_reg);
3135 if (HAS_PCH_IBX(dev_priv->dev)) {
3136 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3137 i = intel_crtc->pipe;
3138 pll = &dev_priv->pch_plls[i];
3140 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3141 intel_crtc->base.base.id, pll->pll_reg);
3146 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147 pll = &dev_priv->pch_plls[i];
3149 /* Only want to check enabled timings first */
3150 if (pll->refcount == 0)
3153 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3154 fp == I915_READ(pll->fp0_reg)) {
3155 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3156 intel_crtc->base.base.id,
3157 pll->pll_reg, pll->refcount, pll->active);
3163 /* Ok no matching timings, maybe there's a free one? */
3164 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3165 pll = &dev_priv->pch_plls[i];
3166 if (pll->refcount == 0) {
3167 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3168 intel_crtc->base.base.id, pll->pll_reg);
3176 intel_crtc->pch_pll = pll;
3178 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3179 prepare: /* separate function? */
3180 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3182 /* Wait for the clocks to stabilize before rewriting the regs */
3183 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3184 POSTING_READ(pll->pll_reg);
3187 I915_WRITE(pll->fp0_reg, fp);
3188 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3193 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3199 temp = I915_READ(dslreg);
3201 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3202 /* Without this, mode sets may fail silently on FDI */
3203 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3205 I915_WRITE(tc2reg, 0);
3206 if (wait_for(I915_READ(dslreg) != temp, 5))
3207 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3211 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216 struct intel_encoder *encoder;
3217 int pipe = intel_crtc->pipe;
3218 int plane = intel_crtc->plane;
3222 WARN_ON(!crtc->enabled);
3224 /* XXX: For compatability with the crtc helper code, call the encoder's
3225 * enable function unconditionally for now. */
3226 if (intel_crtc->active)
3229 intel_crtc->active = true;
3230 intel_update_watermarks(dev);
3232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233 temp = I915_READ(PCH_LVDS);
3234 if ((temp & LVDS_PORT_EN) == 0)
3235 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3238 is_pch_port = intel_crtc_driving_pch(crtc);
3241 ironlake_fdi_pll_enable(intel_crtc);
3243 ironlake_fdi_disable(crtc);
3245 /* Enable panel fitting for LVDS */
3246 if (dev_priv->pch_pf_size &&
3247 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3248 /* Force use of hard-coded filter coefficients
3249 * as some pre-programmed values are broken,
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3258 * On ILK+ LUT must be loaded before the pipe is running but with
3261 intel_crtc_load_lut(crtc);
3263 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3264 intel_enable_plane(dev_priv, plane, pipe);
3267 ironlake_pch_enable(crtc);
3269 mutex_lock(&dev->struct_mutex);
3270 intel_update_fbc(dev);
3271 mutex_unlock(&dev->struct_mutex);
3273 intel_crtc_update_cursor(crtc, true);
3276 for_each_encoder_on_crtc(dev, crtc, encoder)
3277 encoder->enable(encoder);
3279 if (HAS_PCH_CPT(dev))
3280 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3283 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288 struct intel_encoder *encoder;
3289 int pipe = intel_crtc->pipe;
3290 int plane = intel_crtc->plane;
3293 /* XXX: For compatability with the crtc helper code, call the encoder's
3294 * disable function unconditionally for now. */
3295 for_each_encoder_on_crtc(dev, crtc, encoder)
3296 encoder->disable(encoder);
3298 if (!intel_crtc->active)
3301 intel_crtc_wait_for_pending_flips(crtc);
3302 drm_vblank_off(dev, pipe);
3303 intel_crtc_update_cursor(crtc, false);
3305 intel_disable_plane(dev_priv, plane, pipe);
3307 if (dev_priv->cfb_plane == plane)
3308 intel_disable_fbc(dev);
3310 intel_disable_pipe(dev_priv, pipe);
3313 I915_WRITE(PF_CTL(pipe), 0);
3314 I915_WRITE(PF_WIN_SZ(pipe), 0);
3316 ironlake_fdi_disable(crtc);
3318 /* This is a horrible layering violation; we should be doing this in
3319 * the connector/encoder ->prepare instead, but we don't always have
3320 * enough information there about the config to know whether it will
3321 * actually be necessary or just cause undesired flicker.
3323 intel_disable_pch_ports(dev_priv, pipe);
3325 intel_disable_transcoder(dev_priv, pipe);
3327 if (HAS_PCH_CPT(dev)) {
3328 /* disable TRANS_DP_CTL */
3329 reg = TRANS_DP_CTL(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3332 temp |= TRANS_DP_PORT_SEL_NONE;
3333 I915_WRITE(reg, temp);
3335 /* disable DPLL_SEL */
3336 temp = I915_READ(PCH_DPLL_SEL);
3339 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3342 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3345 /* C shares PLL A or B */
3346 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3351 I915_WRITE(PCH_DPLL_SEL, temp);
3354 /* disable PCH DPLL */
3355 intel_disable_pch_pll(intel_crtc);
3357 ironlake_fdi_pll_disable(intel_crtc);
3359 intel_crtc->active = false;
3360 intel_update_watermarks(dev);
3362 mutex_lock(&dev->struct_mutex);
3363 intel_update_fbc(dev);
3364 mutex_unlock(&dev->struct_mutex);
3367 static void ironlake_crtc_off(struct drm_crtc *crtc)
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370 intel_put_pch_pll(intel_crtc);
3373 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3375 if (!enable && intel_crtc->overlay) {
3376 struct drm_device *dev = intel_crtc->base.dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3379 mutex_lock(&dev->struct_mutex);
3380 dev_priv->mm.interruptible = false;
3381 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382 dev_priv->mm.interruptible = true;
3383 mutex_unlock(&dev->struct_mutex);
3386 /* Let userspace switch the overlay on again. In most cases userspace
3387 * has to recompute where to put it anyway.
3391 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 struct intel_encoder *encoder;
3397 int pipe = intel_crtc->pipe;
3398 int plane = intel_crtc->plane;
3400 WARN_ON(!crtc->enabled);
3402 /* XXX: For compatability with the crtc helper code, call the encoder's
3403 * enable function unconditionally for now. */
3404 if (intel_crtc->active)
3407 intel_crtc->active = true;
3408 intel_update_watermarks(dev);
3410 intel_enable_pll(dev_priv, pipe);
3411 intel_enable_pipe(dev_priv, pipe, false);
3412 intel_enable_plane(dev_priv, plane, pipe);
3414 intel_crtc_load_lut(crtc);
3415 intel_update_fbc(dev);
3417 /* Give the overlay scaler a chance to enable if it's on this pipe */
3418 intel_crtc_dpms_overlay(intel_crtc, true);
3419 intel_crtc_update_cursor(crtc, true);
3422 for_each_encoder_on_crtc(dev, crtc, encoder)
3423 encoder->enable(encoder);
3426 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3428 struct drm_device *dev = crtc->dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431 struct intel_encoder *encoder;
3432 int pipe = intel_crtc->pipe;
3433 int plane = intel_crtc->plane;
3435 /* XXX: For compatability with the crtc helper code, call the encoder's
3436 * disable function unconditionally for now. */
3437 for_each_encoder_on_crtc(dev, crtc, encoder)
3438 encoder->disable(encoder);
3440 if (!intel_crtc->active)
3443 /* Give the overlay scaler a chance to disable if it's on this pipe */
3444 intel_crtc_wait_for_pending_flips(crtc);
3445 drm_vblank_off(dev, pipe);
3446 intel_crtc_dpms_overlay(intel_crtc, false);
3447 intel_crtc_update_cursor(crtc, false);
3449 if (dev_priv->cfb_plane == plane)
3450 intel_disable_fbc(dev);
3452 intel_disable_plane(dev_priv, plane, pipe);
3453 intel_disable_pipe(dev_priv, pipe);
3454 intel_disable_pll(dev_priv, pipe);
3456 intel_crtc->active = false;
3457 intel_update_fbc(dev);
3458 intel_update_watermarks(dev);
3461 static void i9xx_crtc_off(struct drm_crtc *crtc)
3466 * Sets the power management mode of the pipe and plane.
3468 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3470 struct drm_device *dev = crtc->dev;
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472 struct drm_i915_master_private *master_priv;
3473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3474 struct intel_encoder *intel_encoder;
3475 int pipe = intel_crtc->pipe;
3476 bool enabled, enable = false;
3478 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3479 enable |= intel_encoder->connectors_active;
3482 dev_priv->display.crtc_enable(crtc);
3484 dev_priv->display.crtc_disable(crtc);
3486 if (!dev->primary->master)
3489 master_priv = dev->primary->master->driver_priv;
3490 if (!master_priv->sarea_priv)
3493 enabled = crtc->enabled && enable;
3497 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3501 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3505 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3510 static void intel_crtc_disable(struct drm_crtc *crtc)
3512 struct drm_device *dev = crtc->dev;
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3515 /* crtc->disable is only called when we have no encoders, hence this
3516 * will disable the pipe. */
3517 intel_crtc_update_dpms(crtc);
3518 dev_priv->display.off(crtc);
3520 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3524 mutex_lock(&dev->struct_mutex);
3525 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3526 mutex_unlock(&dev->struct_mutex);
3530 void intel_encoder_disable(struct drm_encoder *encoder)
3532 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3534 intel_encoder->disable(intel_encoder);
3537 void intel_encoder_destroy(struct drm_encoder *encoder)
3539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3541 drm_encoder_cleanup(encoder);
3542 kfree(intel_encoder);
3545 /* Simple dpms helper for encodres with just one connector, no cloning and only
3546 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547 * state of the entire output pipe. */
3548 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3550 if (mode == DRM_MODE_DPMS_ON) {
3551 encoder->connectors_active = true;
3553 intel_crtc_update_dpms(encoder->base.crtc);
3555 encoder->connectors_active = false;
3557 intel_crtc_update_dpms(encoder->base.crtc);
3561 /* Cross check the actual hw state with our own modeset state tracking (and it's
3562 * internal consistency). */
3563 void intel_connector_check_state(struct intel_connector *connector)
3565 if (connector->get_hw_state(connector)) {
3566 struct intel_encoder *encoder = connector->encoder;
3567 struct drm_crtc *crtc;
3568 bool encoder_enabled;
3571 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3572 connector->base.base.id,
3573 drm_get_connector_name(&connector->base));
3575 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3576 "wrong connector dpms state\n");
3577 WARN(connector->base.encoder != &encoder->base,
3578 "active connector not linked to encoder\n");
3579 WARN(!encoder->connectors_active,
3580 "encoder->connectors_active not set\n");
3582 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3583 WARN(!encoder_enabled, "encoder not enabled\n");
3584 if (WARN_ON(!encoder->base.crtc))
3587 crtc = encoder->base.crtc;
3589 WARN(!crtc->enabled, "crtc not enabled\n");
3590 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3591 WARN(pipe != to_intel_crtc(crtc)->pipe,
3592 "encoder active on the wrong pipe\n");
3596 /* Even simpler default implementation, if there's really no special case to
3598 void intel_connector_dpms(struct drm_connector *connector, int mode)
3600 struct intel_encoder *encoder = intel_attached_encoder(connector);
3602 /* All the simple cases only support two dpms states. */
3603 if (mode != DRM_MODE_DPMS_ON)
3604 mode = DRM_MODE_DPMS_OFF;
3606 if (mode == connector->dpms)
3609 connector->dpms = mode;
3611 /* Only need to change hw state when actually enabled */
3612 if (encoder->base.crtc)
3613 intel_encoder_dpms(encoder, mode);
3615 encoder->connectors_active = false;
3617 intel_connector_check_state(to_intel_connector(connector));
3620 /* Simple connector->get_hw_state implementation for encoders that support only
3621 * one connector and no cloning and hence the encoder state determines the state
3622 * of the connector. */
3623 bool intel_connector_get_hw_state(struct intel_connector *connector)
3626 struct intel_encoder *encoder = connector->encoder;
3628 return encoder->get_hw_state(encoder, &pipe);
3631 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3632 const struct drm_display_mode *mode,
3633 struct drm_display_mode *adjusted_mode)
3635 struct drm_device *dev = crtc->dev;
3637 if (HAS_PCH_SPLIT(dev)) {
3638 /* FDI link clock is fixed at 2.7G */
3639 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3643 /* All interlaced capable intel hw wants timings in frames. Note though
3644 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3645 * timings, so we need to be careful not to clobber these.*/
3646 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3647 drm_mode_set_crtcinfo(adjusted_mode, 0);
3652 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3654 return 400000; /* FIXME */
3657 static int i945_get_display_clock_speed(struct drm_device *dev)
3662 static int i915_get_display_clock_speed(struct drm_device *dev)
3667 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3672 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3676 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3678 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3681 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3682 case GC_DISPLAY_CLOCK_333_MHZ:
3685 case GC_DISPLAY_CLOCK_190_200_MHZ:
3691 static int i865_get_display_clock_speed(struct drm_device *dev)
3696 static int i855_get_display_clock_speed(struct drm_device *dev)
3699 /* Assume that the hardware is in the high speed state. This
3700 * should be the default.
3702 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3703 case GC_CLOCK_133_200:
3704 case GC_CLOCK_100_200:
3706 case GC_CLOCK_166_250:
3708 case GC_CLOCK_100_133:
3712 /* Shouldn't happen */
3716 static int i830_get_display_clock_speed(struct drm_device *dev)
3730 fdi_reduce_ratio(u32 *num, u32 *den)
3732 while (*num > 0xffffff || *den > 0xffffff) {
3739 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3740 int link_clock, struct fdi_m_n *m_n)
3742 m_n->tu = 64; /* default size */
3744 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3745 m_n->gmch_m = bits_per_pixel * pixel_clock;
3746 m_n->gmch_n = link_clock * nlanes * 8;
3747 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3749 m_n->link_m = pixel_clock;
3750 m_n->link_n = link_clock;
3751 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3754 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3756 if (i915_panel_use_ssc >= 0)
3757 return i915_panel_use_ssc != 0;
3758 return dev_priv->lvds_use_ssc
3759 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3763 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3764 * @crtc: CRTC structure
3765 * @mode: requested mode
3767 * A pipe may be connected to one or more outputs. Based on the depth of the
3768 * attached framebuffer, choose a good color depth to use on the pipe.
3770 * If possible, match the pipe depth to the fb depth. In some cases, this
3771 * isn't ideal, because the connected output supports a lesser or restricted
3772 * set of depths. Resolve that here:
3773 * LVDS typically supports only 6bpc, so clamp down in that case
3774 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3775 * Displays may support a restricted set as well, check EDID and clamp as
3777 * DP may want to dither down to 6bpc to fit larger modes
3780 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3781 * true if they don't match).
3783 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3784 struct drm_framebuffer *fb,
3785 unsigned int *pipe_bpp,
3786 struct drm_display_mode *mode)
3788 struct drm_device *dev = crtc->dev;
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct drm_connector *connector;
3791 struct intel_encoder *intel_encoder;
3792 unsigned int display_bpc = UINT_MAX, bpc;
3794 /* Walk the encoders & connectors on this crtc, get min bpc */
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3797 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3798 unsigned int lvds_bpc;
3800 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3806 if (lvds_bpc < display_bpc) {
3807 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3808 display_bpc = lvds_bpc;
3813 /* Not one of the known troublemakers, check the EDID */
3814 list_for_each_entry(connector, &dev->mode_config.connector_list,
3816 if (connector->encoder != &intel_encoder->base)
3819 /* Don't use an invalid EDID bpc value */
3820 if (connector->display_info.bpc &&
3821 connector->display_info.bpc < display_bpc) {
3822 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3823 display_bpc = connector->display_info.bpc;
3828 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3829 * through, clamp it down. (Note: >12bpc will be caught below.)
3831 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3832 if (display_bpc > 8 && display_bpc < 12) {
3833 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3836 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3842 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3843 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3848 * We could just drive the pipe at the highest bpc all the time and
3849 * enable dithering as needed, but that costs bandwidth. So choose
3850 * the minimum value that expresses the full color range of the fb but
3851 * also stays within the max display bpc discovered above.
3854 switch (fb->depth) {
3856 bpc = 8; /* since we go through a colormap */
3860 bpc = 6; /* min is 18bpp */
3872 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3873 bpc = min((unsigned int)8, display_bpc);
3877 display_bpc = min(display_bpc, bpc);
3879 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3882 *pipe_bpp = display_bpc * 3;
3884 return display_bpc != bpc;
3887 static int vlv_get_refclk(struct drm_crtc *crtc)
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 int refclk = 27000; /* for DP & HDMI */
3893 return 100000; /* only one validated so far */
3895 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3897 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3898 if (intel_panel_use_ssc(dev_priv))
3902 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3909 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3915 if (IS_VALLEYVIEW(dev)) {
3916 refclk = vlv_get_refclk(crtc);
3917 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3918 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3919 refclk = dev_priv->lvds_ssc_freq * 1000;
3920 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3922 } else if (!IS_GEN2(dev)) {
3931 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3932 intel_clock_t *clock)
3934 /* SDVO TV has fixed PLL values depend on its clock range,
3935 this mirrors vbios setting. */
3936 if (adjusted_mode->clock >= 100000
3937 && adjusted_mode->clock < 140500) {
3943 } else if (adjusted_mode->clock >= 140500
3944 && adjusted_mode->clock <= 200000) {
3953 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3954 intel_clock_t *clock,
3955 intel_clock_t *reduced_clock)
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 int pipe = intel_crtc->pipe;
3963 if (IS_PINEVIEW(dev)) {
3964 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3966 fp2 = (1 << reduced_clock->n) << 16 |
3967 reduced_clock->m1 << 8 | reduced_clock->m2;
3969 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3971 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3975 I915_WRITE(FP0(pipe), fp);
3977 intel_crtc->lowfreq_avail = false;
3978 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3979 reduced_clock && i915_powersave) {
3980 I915_WRITE(FP1(pipe), fp2);
3981 intel_crtc->lowfreq_avail = true;
3983 I915_WRITE(FP1(pipe), fp);
3987 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3988 struct drm_display_mode *adjusted_mode)
3990 struct drm_device *dev = crtc->dev;
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993 int pipe = intel_crtc->pipe;
3996 temp = I915_READ(LVDS);
3997 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3999 temp |= LVDS_PIPEB_SELECT;
4001 temp &= ~LVDS_PIPEB_SELECT;
4003 /* set the corresponsding LVDS_BORDER bit */
4004 temp |= dev_priv->lvds_border_bits;
4005 /* Set the B0-B3 data pairs corresponding to whether we're going to
4006 * set the DPLLs for dual-channel mode or not.
4009 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4011 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4013 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4014 * appropriately here, but we need to look more thoroughly into how
4015 * panels behave in the two modes.
4017 /* set the dithering flag on LVDS as needed */
4018 if (INTEL_INFO(dev)->gen >= 4) {
4019 if (dev_priv->lvds_dither)
4020 temp |= LVDS_ENABLE_DITHER;
4022 temp &= ~LVDS_ENABLE_DITHER;
4024 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4025 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4026 temp |= LVDS_HSYNC_POLARITY;
4027 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4028 temp |= LVDS_VSYNC_POLARITY;
4029 I915_WRITE(LVDS, temp);
4032 static void vlv_update_pll(struct drm_crtc *crtc,
4033 struct drm_display_mode *mode,
4034 struct drm_display_mode *adjusted_mode,
4035 intel_clock_t *clock, intel_clock_t *reduced_clock,
4036 int refclk, int num_connectors)
4038 struct drm_device *dev = crtc->dev;
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4041 int pipe = intel_crtc->pipe;
4042 u32 dpll, mdiv, pdiv;
4043 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4046 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4054 /* Enable DPIO clock input */
4055 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4056 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4057 I915_WRITE(DPLL(pipe), dpll);
4058 POSTING_READ(DPLL(pipe));
4060 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4061 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4062 mdiv |= ((bestn << DPIO_N_SHIFT));
4063 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4064 mdiv |= (1 << DPIO_K_SHIFT);
4065 mdiv |= DPIO_ENABLE_CALIBRATION;
4066 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4068 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4070 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4071 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4072 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4073 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4075 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4077 dpll |= DPLL_VCO_ENABLE;
4078 I915_WRITE(DPLL(pipe), dpll);
4079 POSTING_READ(DPLL(pipe));
4080 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4081 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4084 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4087 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4091 I915_WRITE(DPLL_MD(pipe), temp);
4092 POSTING_READ(DPLL_MD(pipe));
4095 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4098 static void i9xx_update_pll(struct drm_crtc *crtc,
4099 struct drm_display_mode *mode,
4100 struct drm_display_mode *adjusted_mode,
4101 intel_clock_t *clock, intel_clock_t *reduced_clock,
4104 struct drm_device *dev = crtc->dev;
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107 int pipe = intel_crtc->pipe;
4111 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4112 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4114 dpll = DPLL_VGA_MODE_DIS;
4116 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4117 dpll |= DPLLB_MODE_LVDS;
4119 dpll |= DPLLB_MODE_DAC_SERIAL;
4121 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4122 if (pixel_multiplier > 1) {
4123 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4124 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4126 dpll |= DPLL_DVO_HIGH_SPEED;
4128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4129 dpll |= DPLL_DVO_HIGH_SPEED;
4131 /* compute bitmask from p1 value */
4132 if (IS_PINEVIEW(dev))
4133 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4135 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4136 if (IS_G4X(dev) && reduced_clock)
4137 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4139 switch (clock->p2) {
4141 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4144 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4147 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4150 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4153 if (INTEL_INFO(dev)->gen >= 4)
4154 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4156 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4157 dpll |= PLL_REF_INPUT_TVCLKINBC;
4158 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4159 /* XXX: just matching BIOS for now */
4160 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4162 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4163 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4164 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4166 dpll |= PLL_REF_INPUT_DREFCLK;
4168 dpll |= DPLL_VCO_ENABLE;
4169 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4170 POSTING_READ(DPLL(pipe));
4173 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4174 * This is an exception to the general rule that mode_set doesn't turn
4177 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4178 intel_update_lvds(crtc, clock, adjusted_mode);
4180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4181 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4183 I915_WRITE(DPLL(pipe), dpll);
4185 /* Wait for the clocks to stabilize. */
4186 POSTING_READ(DPLL(pipe));
4189 if (INTEL_INFO(dev)->gen >= 4) {
4192 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4194 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4198 I915_WRITE(DPLL_MD(pipe), temp);
4200 /* The pixel multiplier can only be updated once the
4201 * DPLL is enabled and the clocks are stable.
4203 * So write it again.
4205 I915_WRITE(DPLL(pipe), dpll);
4209 static void i8xx_update_pll(struct drm_crtc *crtc,
4210 struct drm_display_mode *adjusted_mode,
4211 intel_clock_t *clock,
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 int pipe = intel_crtc->pipe;
4220 dpll = DPLL_VGA_MODE_DIS;
4222 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4223 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4226 dpll |= PLL_P1_DIVIDE_BY_TWO;
4228 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4230 dpll |= PLL_P2_DIVIDE_BY_4;
4233 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4234 /* XXX: just matching BIOS for now */
4235 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4237 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4238 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4239 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4241 dpll |= PLL_REF_INPUT_DREFCLK;
4243 dpll |= DPLL_VCO_ENABLE;
4244 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4245 POSTING_READ(DPLL(pipe));
4248 I915_WRITE(DPLL(pipe), dpll);
4250 /* Wait for the clocks to stabilize. */
4251 POSTING_READ(DPLL(pipe));
4254 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4255 * This is an exception to the general rule that mode_set doesn't turn
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4259 intel_update_lvds(crtc, clock, adjusted_mode);
4261 /* The pixel multiplier can only be updated once the
4262 * DPLL is enabled and the clocks are stable.
4264 * So write it again.
4266 I915_WRITE(DPLL(pipe), dpll);
4269 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4270 struct drm_display_mode *mode,
4271 struct drm_display_mode *adjusted_mode,
4273 struct drm_framebuffer *fb)
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278 int pipe = intel_crtc->pipe;
4279 int plane = intel_crtc->plane;
4280 int refclk, num_connectors = 0;
4281 intel_clock_t clock, reduced_clock;
4282 u32 dspcntr, pipeconf, vsyncshift;
4283 bool ok, has_reduced_clock = false, is_sdvo = false;
4284 bool is_lvds = false, is_tv = false, is_dp = false;
4285 struct intel_encoder *encoder;
4286 const intel_limit_t *limit;
4289 for_each_encoder_on_crtc(dev, crtc, encoder) {
4290 switch (encoder->type) {
4291 case INTEL_OUTPUT_LVDS:
4294 case INTEL_OUTPUT_SDVO:
4295 case INTEL_OUTPUT_HDMI:
4297 if (encoder->needs_tv_clock)
4300 case INTEL_OUTPUT_TVOUT:
4303 case INTEL_OUTPUT_DISPLAYPORT:
4311 refclk = i9xx_get_refclk(crtc, num_connectors);
4314 * Returns a set of divisors for the desired target clock with the given
4315 * refclk, or FALSE. The returned values represent the clock equation:
4316 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4318 limit = intel_limit(crtc, refclk);
4319 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4322 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4326 /* Ensure that the cursor is valid for the new mode before changing... */
4327 intel_crtc_update_cursor(crtc, true);
4329 if (is_lvds && dev_priv->lvds_downclock_avail) {
4331 * Ensure we match the reduced clock's P to the target clock.
4332 * If the clocks don't match, we can't switch the display clock
4333 * by using the FP0/FP1. In such case we will disable the LVDS
4334 * downclock feature.
4336 has_reduced_clock = limit->find_pll(limit, crtc,
4337 dev_priv->lvds_downclock,
4343 if (is_sdvo && is_tv)
4344 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4346 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4347 &reduced_clock : NULL);
4350 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4351 else if (IS_VALLEYVIEW(dev))
4352 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4353 refclk, num_connectors);
4355 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4356 has_reduced_clock ? &reduced_clock : NULL,
4359 /* setup pipeconf */
4360 pipeconf = I915_READ(PIPECONF(pipe));
4362 /* Set up the display plane register */
4363 dspcntr = DISPPLANE_GAMMA_ENABLE;
4366 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4368 dspcntr |= DISPPLANE_SEL_PIPE_B;
4370 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4371 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4374 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4378 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4379 pipeconf |= PIPECONF_DOUBLE_WIDE;
4381 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4384 /* default to 8bpc */
4385 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4387 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4388 pipeconf |= PIPECONF_BPP_6 |
4389 PIPECONF_DITHER_EN |
4390 PIPECONF_DITHER_TYPE_SP;
4394 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4395 drm_mode_debug_printmodeline(mode);
4397 if (HAS_PIPE_CXSR(dev)) {
4398 if (intel_crtc->lowfreq_avail) {
4399 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4400 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4402 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4403 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4407 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4408 if (!IS_GEN2(dev) &&
4409 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4410 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4411 /* the chip adds 2 halflines automatically */
4412 adjusted_mode->crtc_vtotal -= 1;
4413 adjusted_mode->crtc_vblank_end -= 1;
4414 vsyncshift = adjusted_mode->crtc_hsync_start
4415 - adjusted_mode->crtc_htotal/2;
4417 pipeconf |= PIPECONF_PROGRESSIVE;
4422 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4424 I915_WRITE(HTOTAL(pipe),
4425 (adjusted_mode->crtc_hdisplay - 1) |
4426 ((adjusted_mode->crtc_htotal - 1) << 16));
4427 I915_WRITE(HBLANK(pipe),
4428 (adjusted_mode->crtc_hblank_start - 1) |
4429 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4430 I915_WRITE(HSYNC(pipe),
4431 (adjusted_mode->crtc_hsync_start - 1) |
4432 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4434 I915_WRITE(VTOTAL(pipe),
4435 (adjusted_mode->crtc_vdisplay - 1) |
4436 ((adjusted_mode->crtc_vtotal - 1) << 16));
4437 I915_WRITE(VBLANK(pipe),
4438 (adjusted_mode->crtc_vblank_start - 1) |
4439 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4440 I915_WRITE(VSYNC(pipe),
4441 (adjusted_mode->crtc_vsync_start - 1) |
4442 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4444 /* pipesrc and dspsize control the size that is scaled from,
4445 * which should always be the user's requested size.
4447 I915_WRITE(DSPSIZE(plane),
4448 ((mode->vdisplay - 1) << 16) |
4449 (mode->hdisplay - 1));
4450 I915_WRITE(DSPPOS(plane), 0);
4451 I915_WRITE(PIPESRC(pipe),
4452 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4454 I915_WRITE(PIPECONF(pipe), pipeconf);
4455 POSTING_READ(PIPECONF(pipe));
4456 intel_enable_pipe(dev_priv, pipe, false);
4458 intel_wait_for_vblank(dev, pipe);
4460 I915_WRITE(DSPCNTR(plane), dspcntr);
4461 POSTING_READ(DSPCNTR(plane));
4463 ret = intel_pipe_set_base(crtc, x, y, fb);
4465 intel_update_watermarks(dev);
4471 * Initialize reference clocks when the driver loads
4473 void ironlake_init_pch_refclk(struct drm_device *dev)
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct drm_mode_config *mode_config = &dev->mode_config;
4477 struct intel_encoder *encoder;
4479 bool has_lvds = false;
4480 bool has_cpu_edp = false;
4481 bool has_pch_edp = false;
4482 bool has_panel = false;
4483 bool has_ck505 = false;
4484 bool can_ssc = false;
4486 /* We need to take the global config into account */
4487 list_for_each_entry(encoder, &mode_config->encoder_list,
4489 switch (encoder->type) {
4490 case INTEL_OUTPUT_LVDS:
4494 case INTEL_OUTPUT_EDP:
4496 if (intel_encoder_is_pch_edp(&encoder->base))
4504 if (HAS_PCH_IBX(dev)) {
4505 has_ck505 = dev_priv->display_clock_mode;
4506 can_ssc = has_ck505;
4512 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4513 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4516 /* Ironlake: try to setup display ref clock before DPLL
4517 * enabling. This is only under driver's control after
4518 * PCH B stepping, previous chipset stepping should be
4519 * ignoring this setting.
4521 temp = I915_READ(PCH_DREF_CONTROL);
4522 /* Always enable nonspread source */
4523 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4526 temp |= DREF_NONSPREAD_CK505_ENABLE;
4528 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4531 temp &= ~DREF_SSC_SOURCE_MASK;
4532 temp |= DREF_SSC_SOURCE_ENABLE;
4534 /* SSC must be turned on before enabling the CPU output */
4535 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4536 DRM_DEBUG_KMS("Using SSC on panel\n");
4537 temp |= DREF_SSC1_ENABLE;
4539 temp &= ~DREF_SSC1_ENABLE;
4541 /* Get SSC going before enabling the outputs */
4542 I915_WRITE(PCH_DREF_CONTROL, temp);
4543 POSTING_READ(PCH_DREF_CONTROL);
4546 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4548 /* Enable CPU source on CPU attached eDP */
4550 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4551 DRM_DEBUG_KMS("Using SSC on eDP\n");
4552 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4555 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4557 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4559 I915_WRITE(PCH_DREF_CONTROL, temp);
4560 POSTING_READ(PCH_DREF_CONTROL);
4563 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4565 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4567 /* Turn off CPU output */
4568 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4570 I915_WRITE(PCH_DREF_CONTROL, temp);
4571 POSTING_READ(PCH_DREF_CONTROL);
4574 /* Turn off the SSC source */
4575 temp &= ~DREF_SSC_SOURCE_MASK;
4576 temp |= DREF_SSC_SOURCE_DISABLE;
4579 temp &= ~ DREF_SSC1_ENABLE;
4581 I915_WRITE(PCH_DREF_CONTROL, temp);
4582 POSTING_READ(PCH_DREF_CONTROL);
4587 static int ironlake_get_refclk(struct drm_crtc *crtc)
4589 struct drm_device *dev = crtc->dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_encoder *encoder;
4592 struct intel_encoder *edp_encoder = NULL;
4593 int num_connectors = 0;
4594 bool is_lvds = false;
4596 for_each_encoder_on_crtc(dev, crtc, encoder) {
4597 switch (encoder->type) {
4598 case INTEL_OUTPUT_LVDS:
4601 case INTEL_OUTPUT_EDP:
4602 edp_encoder = encoder;
4608 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4609 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4610 dev_priv->lvds_ssc_freq);
4611 return dev_priv->lvds_ssc_freq * 1000;
4617 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4618 struct drm_display_mode *mode,
4619 struct drm_display_mode *adjusted_mode,
4621 struct drm_framebuffer *fb)
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 int pipe = intel_crtc->pipe;
4627 int plane = intel_crtc->plane;
4628 int refclk, num_connectors = 0;
4629 intel_clock_t clock, reduced_clock;
4630 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4631 bool ok, has_reduced_clock = false, is_sdvo = false;
4632 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4633 struct intel_encoder *encoder, *edp_encoder = NULL;
4634 const intel_limit_t *limit;
4636 struct fdi_m_n m_n = {0};
4638 int target_clock, pixel_multiplier, lane, link_bw, factor;
4639 unsigned int pipe_bpp;
4641 bool is_cpu_edp = false, is_pch_edp = false;
4643 for_each_encoder_on_crtc(dev, crtc, encoder) {
4644 switch (encoder->type) {
4645 case INTEL_OUTPUT_LVDS:
4648 case INTEL_OUTPUT_SDVO:
4649 case INTEL_OUTPUT_HDMI:
4651 if (encoder->needs_tv_clock)
4654 case INTEL_OUTPUT_TVOUT:
4657 case INTEL_OUTPUT_ANALOG:
4660 case INTEL_OUTPUT_DISPLAYPORT:
4663 case INTEL_OUTPUT_EDP:
4665 if (intel_encoder_is_pch_edp(&encoder->base))
4669 edp_encoder = encoder;
4676 refclk = ironlake_get_refclk(crtc);
4679 * Returns a set of divisors for the desired target clock with the given
4680 * refclk, or FALSE. The returned values represent the clock equation:
4681 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4683 limit = intel_limit(crtc, refclk);
4684 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4687 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4691 /* Ensure that the cursor is valid for the new mode before changing... */
4692 intel_crtc_update_cursor(crtc, true);
4694 if (is_lvds && dev_priv->lvds_downclock_avail) {
4696 * Ensure we match the reduced clock's P to the target clock.
4697 * If the clocks don't match, we can't switch the display clock
4698 * by using the FP0/FP1. In such case we will disable the LVDS
4699 * downclock feature.
4701 has_reduced_clock = limit->find_pll(limit, crtc,
4702 dev_priv->lvds_downclock,
4708 if (is_sdvo && is_tv)
4709 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4713 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4715 /* CPU eDP doesn't require FDI link, so just set DP M/N
4716 according to current link config */
4718 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4720 /* FDI is a binary signal running at ~2.7GHz, encoding
4721 * each output octet as 10 bits. The actual frequency
4722 * is stored as a divider into a 100MHz clock, and the
4723 * mode pixel clock is stored in units of 1KHz.
4724 * Hence the bw of each lane in terms of the mode signal
4727 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4730 /* [e]DP over FDI requires target mode clock instead of link clock. */
4732 target_clock = intel_edp_target_clock(edp_encoder, mode);
4734 target_clock = mode->clock;
4736 target_clock = adjusted_mode->clock;
4738 /* determine panel color depth */
4739 temp = I915_READ(PIPECONF(pipe));
4740 temp &= ~PIPE_BPC_MASK;
4741 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
4756 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4763 intel_crtc->bpp = pipe_bpp;
4764 I915_WRITE(PIPECONF(pipe), temp);
4768 * Account for spread spectrum to avoid
4769 * oversubscribing the link. Max center spread
4770 * is 2.5%; use 5% for safety's sake.
4772 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4773 lane = bps / (link_bw * 8) + 1;
4776 intel_crtc->fdi_lanes = lane;
4778 if (pixel_multiplier > 1)
4779 link_bw *= pixel_multiplier;
4780 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4784 if (has_reduced_clock)
4785 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4788 /* Enable autotuning of the PLL clock (if permissible) */
4791 if ((intel_panel_use_ssc(dev_priv) &&
4792 dev_priv->lvds_ssc_freq == 100) ||
4793 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4795 } else if (is_sdvo && is_tv)
4798 if (clock.m < factor * clock.n)
4804 dpll |= DPLLB_MODE_LVDS;
4806 dpll |= DPLLB_MODE_DAC_SERIAL;
4808 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4809 if (pixel_multiplier > 1) {
4810 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4812 dpll |= DPLL_DVO_HIGH_SPEED;
4814 if (is_dp && !is_cpu_edp)
4815 dpll |= DPLL_DVO_HIGH_SPEED;
4817 /* compute bitmask from p1 value */
4818 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4820 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4824 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4827 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4830 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4833 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4837 if (is_sdvo && is_tv)
4838 dpll |= PLL_REF_INPUT_TVCLKINBC;
4840 /* XXX: just matching BIOS for now */
4841 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4843 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4844 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4846 dpll |= PLL_REF_INPUT_DREFCLK;
4848 /* setup pipeconf */
4849 pipeconf = I915_READ(PIPECONF(pipe));
4851 /* Set up the display plane register */
4852 dspcntr = DISPPLANE_GAMMA_ENABLE;
4854 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4855 drm_mode_debug_printmodeline(mode);
4857 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4858 * pre-Haswell/LPT generation */
4859 if (HAS_PCH_LPT(dev)) {
4860 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4862 } else if (!is_cpu_edp) {
4863 struct intel_pch_pll *pll;
4865 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4867 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4872 intel_put_pch_pll(intel_crtc);
4874 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4875 * This is an exception to the general rule that mode_set doesn't turn
4879 temp = I915_READ(PCH_LVDS);
4880 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4881 if (HAS_PCH_CPT(dev)) {
4882 temp &= ~PORT_TRANS_SEL_MASK;
4883 temp |= PORT_TRANS_SEL_CPT(pipe);
4886 temp |= LVDS_PIPEB_SELECT;
4888 temp &= ~LVDS_PIPEB_SELECT;
4891 /* set the corresponsding LVDS_BORDER bit */
4892 temp |= dev_priv->lvds_border_bits;
4893 /* Set the B0-B3 data pairs corresponding to whether we're going to
4894 * set the DPLLs for dual-channel mode or not.
4897 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4899 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4901 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4902 * appropriately here, but we need to look more thoroughly into how
4903 * panels behave in the two modes.
4905 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4906 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4907 temp |= LVDS_HSYNC_POLARITY;
4908 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4909 temp |= LVDS_VSYNC_POLARITY;
4910 I915_WRITE(PCH_LVDS, temp);
4913 pipeconf &= ~PIPECONF_DITHER_EN;
4914 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4915 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4916 pipeconf |= PIPECONF_DITHER_EN;
4917 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4919 if (is_dp && !is_cpu_edp) {
4920 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4922 /* For non-DP output, clear any trans DP clock recovery setting.*/
4923 I915_WRITE(TRANSDATA_M1(pipe), 0);
4924 I915_WRITE(TRANSDATA_N1(pipe), 0);
4925 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4926 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4929 if (intel_crtc->pch_pll) {
4930 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4932 /* Wait for the clocks to stabilize. */
4933 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4936 /* The pixel multiplier can only be updated once the
4937 * DPLL is enabled and the clocks are stable.
4939 * So write it again.
4941 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4944 intel_crtc->lowfreq_avail = false;
4945 if (intel_crtc->pch_pll) {
4946 if (is_lvds && has_reduced_clock && i915_powersave) {
4947 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4948 intel_crtc->lowfreq_avail = true;
4950 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4954 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4955 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4956 pipeconf |= PIPECONF_INTERLACED_ILK;
4957 /* the chip adds 2 halflines automatically */
4958 adjusted_mode->crtc_vtotal -= 1;
4959 adjusted_mode->crtc_vblank_end -= 1;
4960 I915_WRITE(VSYNCSHIFT(pipe),
4961 adjusted_mode->crtc_hsync_start
4962 - adjusted_mode->crtc_htotal/2);
4964 pipeconf |= PIPECONF_PROGRESSIVE;
4965 I915_WRITE(VSYNCSHIFT(pipe), 0);
4968 I915_WRITE(HTOTAL(pipe),
4969 (adjusted_mode->crtc_hdisplay - 1) |
4970 ((adjusted_mode->crtc_htotal - 1) << 16));
4971 I915_WRITE(HBLANK(pipe),
4972 (adjusted_mode->crtc_hblank_start - 1) |
4973 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4974 I915_WRITE(HSYNC(pipe),
4975 (adjusted_mode->crtc_hsync_start - 1) |
4976 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4978 I915_WRITE(VTOTAL(pipe),
4979 (adjusted_mode->crtc_vdisplay - 1) |
4980 ((adjusted_mode->crtc_vtotal - 1) << 16));
4981 I915_WRITE(VBLANK(pipe),
4982 (adjusted_mode->crtc_vblank_start - 1) |
4983 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4984 I915_WRITE(VSYNC(pipe),
4985 (adjusted_mode->crtc_vsync_start - 1) |
4986 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4988 /* pipesrc controls the size that is scaled from, which should
4989 * always be the user's requested size.
4991 I915_WRITE(PIPESRC(pipe),
4992 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4994 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4995 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4996 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4997 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5000 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5002 I915_WRITE(PIPECONF(pipe), pipeconf);
5003 POSTING_READ(PIPECONF(pipe));
5005 intel_wait_for_vblank(dev, pipe);
5007 I915_WRITE(DSPCNTR(plane), dspcntr);
5008 POSTING_READ(DSPCNTR(plane));
5010 ret = intel_pipe_set_base(crtc, x, y, fb);
5012 intel_update_watermarks(dev);
5014 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5019 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5020 struct drm_display_mode *mode,
5021 struct drm_display_mode *adjusted_mode,
5023 struct drm_framebuffer *fb)
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 int pipe = intel_crtc->pipe;
5031 drm_vblank_pre_modeset(dev, pipe);
5033 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5035 drm_vblank_post_modeset(dev, pipe);
5040 static bool intel_eld_uptodate(struct drm_connector *connector,
5041 int reg_eldv, uint32_t bits_eldv,
5042 int reg_elda, uint32_t bits_elda,
5045 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5046 uint8_t *eld = connector->eld;
5049 i = I915_READ(reg_eldv);
5058 i = I915_READ(reg_elda);
5060 I915_WRITE(reg_elda, i);
5062 for (i = 0; i < eld[2]; i++)
5063 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5069 static void g4x_write_eld(struct drm_connector *connector,
5070 struct drm_crtc *crtc)
5072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073 uint8_t *eld = connector->eld;
5078 i = I915_READ(G4X_AUD_VID_DID);
5080 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5081 eldv = G4X_ELDV_DEVCL_DEVBLC;
5083 eldv = G4X_ELDV_DEVCTG;
5085 if (intel_eld_uptodate(connector,
5086 G4X_AUD_CNTL_ST, eldv,
5087 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5088 G4X_HDMIW_HDMIEDID))
5091 i = I915_READ(G4X_AUD_CNTL_ST);
5092 i &= ~(eldv | G4X_ELD_ADDR);
5093 len = (i >> 9) & 0x1f; /* ELD buffer size */
5094 I915_WRITE(G4X_AUD_CNTL_ST, i);
5099 len = min_t(uint8_t, eld[2], len);
5100 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5101 for (i = 0; i < len; i++)
5102 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5104 i = I915_READ(G4X_AUD_CNTL_ST);
5106 I915_WRITE(G4X_AUD_CNTL_ST, i);
5109 static void haswell_write_eld(struct drm_connector *connector,
5110 struct drm_crtc *crtc)
5112 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5113 uint8_t *eld = connector->eld;
5114 struct drm_device *dev = crtc->dev;
5118 int pipe = to_intel_crtc(crtc)->pipe;
5121 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5122 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5123 int aud_config = HSW_AUD_CFG(pipe);
5124 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5127 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5129 /* Audio output enable */
5130 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5131 tmp = I915_READ(aud_cntrl_st2);
5132 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5133 I915_WRITE(aud_cntrl_st2, tmp);
5135 /* Wait for 1 vertical blank */
5136 intel_wait_for_vblank(dev, pipe);
5138 /* Set ELD valid state */
5139 tmp = I915_READ(aud_cntrl_st2);
5140 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5141 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5142 I915_WRITE(aud_cntrl_st2, tmp);
5143 tmp = I915_READ(aud_cntrl_st2);
5144 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5146 /* Enable HDMI mode */
5147 tmp = I915_READ(aud_config);
5148 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5149 /* clear N_programing_enable and N_value_index */
5150 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5151 I915_WRITE(aud_config, tmp);
5153 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5155 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5158 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5159 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5160 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5162 I915_WRITE(aud_config, 0);
5164 if (intel_eld_uptodate(connector,
5165 aud_cntrl_st2, eldv,
5166 aud_cntl_st, IBX_ELD_ADDRESS,
5170 i = I915_READ(aud_cntrl_st2);
5172 I915_WRITE(aud_cntrl_st2, i);
5177 i = I915_READ(aud_cntl_st);
5178 i &= ~IBX_ELD_ADDRESS;
5179 I915_WRITE(aud_cntl_st, i);
5180 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5181 DRM_DEBUG_DRIVER("port num:%d\n", i);
5183 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5184 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5185 for (i = 0; i < len; i++)
5186 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5188 i = I915_READ(aud_cntrl_st2);
5190 I915_WRITE(aud_cntrl_st2, i);
5194 static void ironlake_write_eld(struct drm_connector *connector,
5195 struct drm_crtc *crtc)
5197 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5198 uint8_t *eld = connector->eld;
5206 int pipe = to_intel_crtc(crtc)->pipe;
5208 if (HAS_PCH_IBX(connector->dev)) {
5209 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5210 aud_config = IBX_AUD_CFG(pipe);
5211 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5212 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5214 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5215 aud_config = CPT_AUD_CFG(pipe);
5216 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5217 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5220 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5222 i = I915_READ(aud_cntl_st);
5223 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5225 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5226 /* operate blindly on all ports */
5227 eldv = IBX_ELD_VALIDB;
5228 eldv |= IBX_ELD_VALIDB << 4;
5229 eldv |= IBX_ELD_VALIDB << 8;
5231 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5232 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5235 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5236 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5237 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5238 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5240 I915_WRITE(aud_config, 0);
5242 if (intel_eld_uptodate(connector,
5243 aud_cntrl_st2, eldv,
5244 aud_cntl_st, IBX_ELD_ADDRESS,
5248 i = I915_READ(aud_cntrl_st2);
5250 I915_WRITE(aud_cntrl_st2, i);
5255 i = I915_READ(aud_cntl_st);
5256 i &= ~IBX_ELD_ADDRESS;
5257 I915_WRITE(aud_cntl_st, i);
5259 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5260 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5261 for (i = 0; i < len; i++)
5262 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5264 i = I915_READ(aud_cntrl_st2);
5266 I915_WRITE(aud_cntrl_st2, i);
5269 void intel_write_eld(struct drm_encoder *encoder,
5270 struct drm_display_mode *mode)
5272 struct drm_crtc *crtc = encoder->crtc;
5273 struct drm_connector *connector;
5274 struct drm_device *dev = encoder->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5277 connector = drm_select_eld(encoder, mode);
5281 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5283 drm_get_connector_name(connector),
5284 connector->encoder->base.id,
5285 drm_get_encoder_name(connector->encoder));
5287 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5289 if (dev_priv->display.write_eld)
5290 dev_priv->display.write_eld(connector, crtc);
5293 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5294 void intel_crtc_load_lut(struct drm_crtc *crtc)
5296 struct drm_device *dev = crtc->dev;
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5299 int palreg = PALETTE(intel_crtc->pipe);
5302 /* The clocks have to be on to load the palette. */
5303 if (!crtc->enabled || !intel_crtc->active)
5306 /* use legacy palette for Ironlake */
5307 if (HAS_PCH_SPLIT(dev))
5308 palreg = LGC_PALETTE(intel_crtc->pipe);
5310 for (i = 0; i < 256; i++) {
5311 I915_WRITE(palreg + 4 * i,
5312 (intel_crtc->lut_r[i] << 16) |
5313 (intel_crtc->lut_g[i] << 8) |
5314 intel_crtc->lut_b[i]);
5318 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5320 struct drm_device *dev = crtc->dev;
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323 bool visible = base != 0;
5326 if (intel_crtc->cursor_visible == visible)
5329 cntl = I915_READ(_CURACNTR);
5331 /* On these chipsets we can only modify the base whilst
5332 * the cursor is disabled.
5334 I915_WRITE(_CURABASE, base);
5336 cntl &= ~(CURSOR_FORMAT_MASK);
5337 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5338 cntl |= CURSOR_ENABLE |
5339 CURSOR_GAMMA_ENABLE |
5342 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5343 I915_WRITE(_CURACNTR, cntl);
5345 intel_crtc->cursor_visible = visible;
5348 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5350 struct drm_device *dev = crtc->dev;
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353 int pipe = intel_crtc->pipe;
5354 bool visible = base != 0;
5356 if (intel_crtc->cursor_visible != visible) {
5357 uint32_t cntl = I915_READ(CURCNTR(pipe));
5359 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5360 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5361 cntl |= pipe << 28; /* Connect to correct pipe */
5363 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5364 cntl |= CURSOR_MODE_DISABLE;
5366 I915_WRITE(CURCNTR(pipe), cntl);
5368 intel_crtc->cursor_visible = visible;
5370 /* and commit changes on next vblank */
5371 I915_WRITE(CURBASE(pipe), base);
5374 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5376 struct drm_device *dev = crtc->dev;
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379 int pipe = intel_crtc->pipe;
5380 bool visible = base != 0;
5382 if (intel_crtc->cursor_visible != visible) {
5383 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5385 cntl &= ~CURSOR_MODE;
5386 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5389 cntl |= CURSOR_MODE_DISABLE;
5391 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5393 intel_crtc->cursor_visible = visible;
5395 /* and commit changes on next vblank */
5396 I915_WRITE(CURBASE_IVB(pipe), base);
5399 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5400 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5403 struct drm_device *dev = crtc->dev;
5404 struct drm_i915_private *dev_priv = dev->dev_private;
5405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406 int pipe = intel_crtc->pipe;
5407 int x = intel_crtc->cursor_x;
5408 int y = intel_crtc->cursor_y;
5414 if (on && crtc->enabled && crtc->fb) {
5415 base = intel_crtc->cursor_addr;
5416 if (x > (int) crtc->fb->width)
5419 if (y > (int) crtc->fb->height)
5425 if (x + intel_crtc->cursor_width < 0)
5428 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5431 pos |= x << CURSOR_X_SHIFT;
5434 if (y + intel_crtc->cursor_height < 0)
5437 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5440 pos |= y << CURSOR_Y_SHIFT;
5442 visible = base != 0;
5443 if (!visible && !intel_crtc->cursor_visible)
5446 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5447 I915_WRITE(CURPOS_IVB(pipe), pos);
5448 ivb_update_cursor(crtc, base);
5450 I915_WRITE(CURPOS(pipe), pos);
5451 if (IS_845G(dev) || IS_I865G(dev))
5452 i845_update_cursor(crtc, base);
5454 i9xx_update_cursor(crtc, base);
5458 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5459 struct drm_file *file,
5461 uint32_t width, uint32_t height)
5463 struct drm_device *dev = crtc->dev;
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5466 struct drm_i915_gem_object *obj;
5470 /* if we want to turn off the cursor ignore width and height */
5472 DRM_DEBUG_KMS("cursor off\n");
5475 mutex_lock(&dev->struct_mutex);
5479 /* Currently we only support 64x64 cursors */
5480 if (width != 64 || height != 64) {
5481 DRM_ERROR("we currently only support 64x64 cursors\n");
5485 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5486 if (&obj->base == NULL)
5489 if (obj->base.size < width * height * 4) {
5490 DRM_ERROR("buffer is to small\n");
5495 /* we only need to pin inside GTT if cursor is non-phy */
5496 mutex_lock(&dev->struct_mutex);
5497 if (!dev_priv->info->cursor_needs_physical) {
5498 if (obj->tiling_mode) {
5499 DRM_ERROR("cursor cannot be tiled\n");
5504 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5506 DRM_ERROR("failed to move cursor bo into the GTT\n");
5510 ret = i915_gem_object_put_fence(obj);
5512 DRM_ERROR("failed to release fence for cursor");
5516 addr = obj->gtt_offset;
5518 int align = IS_I830(dev) ? 16 * 1024 : 256;
5519 ret = i915_gem_attach_phys_object(dev, obj,
5520 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5523 DRM_ERROR("failed to attach phys object\n");
5526 addr = obj->phys_obj->handle->busaddr;
5530 I915_WRITE(CURSIZE, (height << 12) | width);
5533 if (intel_crtc->cursor_bo) {
5534 if (dev_priv->info->cursor_needs_physical) {
5535 if (intel_crtc->cursor_bo != obj)
5536 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5538 i915_gem_object_unpin(intel_crtc->cursor_bo);
5539 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5542 mutex_unlock(&dev->struct_mutex);
5544 intel_crtc->cursor_addr = addr;
5545 intel_crtc->cursor_bo = obj;
5546 intel_crtc->cursor_width = width;
5547 intel_crtc->cursor_height = height;
5549 intel_crtc_update_cursor(crtc, true);
5553 i915_gem_object_unpin(obj);
5555 mutex_unlock(&dev->struct_mutex);
5557 drm_gem_object_unreference_unlocked(&obj->base);
5561 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5565 intel_crtc->cursor_x = x;
5566 intel_crtc->cursor_y = y;
5568 intel_crtc_update_cursor(crtc, true);
5573 /** Sets the color ramps on behalf of RandR */
5574 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5575 u16 blue, int regno)
5577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5579 intel_crtc->lut_r[regno] = red >> 8;
5580 intel_crtc->lut_g[regno] = green >> 8;
5581 intel_crtc->lut_b[regno] = blue >> 8;
5584 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5585 u16 *blue, int regno)
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589 *red = intel_crtc->lut_r[regno] << 8;
5590 *green = intel_crtc->lut_g[regno] << 8;
5591 *blue = intel_crtc->lut_b[regno] << 8;
5594 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5595 u16 *blue, uint32_t start, uint32_t size)
5597 int end = (start + size > 256) ? 256 : start + size, i;
5598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 for (i = start; i < end; i++) {
5601 intel_crtc->lut_r[i] = red[i] >> 8;
5602 intel_crtc->lut_g[i] = green[i] >> 8;
5603 intel_crtc->lut_b[i] = blue[i] >> 8;
5606 intel_crtc_load_lut(crtc);
5610 * Get a pipe with a simple mode set on it for doing load-based monitor
5613 * It will be up to the load-detect code to adjust the pipe as appropriate for
5614 * its requirements. The pipe will be connected to no other encoders.
5616 * Currently this code will only succeed if there is a pipe with no encoders
5617 * configured for it. In the future, it could choose to temporarily disable
5618 * some outputs to free up a pipe for its use.
5620 * \return crtc, or NULL if no pipes are available.
5623 /* VESA 640x480x72Hz mode to set on the pipe */
5624 static struct drm_display_mode load_detect_mode = {
5625 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5626 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5629 static struct drm_framebuffer *
5630 intel_framebuffer_create(struct drm_device *dev,
5631 struct drm_mode_fb_cmd2 *mode_cmd,
5632 struct drm_i915_gem_object *obj)
5634 struct intel_framebuffer *intel_fb;
5637 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5639 drm_gem_object_unreference_unlocked(&obj->base);
5640 return ERR_PTR(-ENOMEM);
5643 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5645 drm_gem_object_unreference_unlocked(&obj->base);
5647 return ERR_PTR(ret);
5650 return &intel_fb->base;
5654 intel_framebuffer_pitch_for_width(int width, int bpp)
5656 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5657 return ALIGN(pitch, 64);
5661 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5663 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5664 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5667 static struct drm_framebuffer *
5668 intel_framebuffer_create_for_mode(struct drm_device *dev,
5669 struct drm_display_mode *mode,
5672 struct drm_i915_gem_object *obj;
5673 struct drm_mode_fb_cmd2 mode_cmd;
5675 obj = i915_gem_alloc_object(dev,
5676 intel_framebuffer_size_for_mode(mode, bpp));
5678 return ERR_PTR(-ENOMEM);
5680 mode_cmd.width = mode->hdisplay;
5681 mode_cmd.height = mode->vdisplay;
5682 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5684 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5686 return intel_framebuffer_create(dev, &mode_cmd, obj);
5689 static struct drm_framebuffer *
5690 mode_fits_in_fbdev(struct drm_device *dev,
5691 struct drm_display_mode *mode)
5693 struct drm_i915_private *dev_priv = dev->dev_private;
5694 struct drm_i915_gem_object *obj;
5695 struct drm_framebuffer *fb;
5697 if (dev_priv->fbdev == NULL)
5700 obj = dev_priv->fbdev->ifb.obj;
5704 fb = &dev_priv->fbdev->ifb.base;
5705 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5706 fb->bits_per_pixel))
5709 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5715 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5716 struct drm_display_mode *mode,
5717 struct intel_load_detect_pipe *old)
5719 struct intel_crtc *intel_crtc;
5720 struct intel_encoder *intel_encoder =
5721 intel_attached_encoder(connector);
5722 struct drm_crtc *possible_crtc;
5723 struct drm_encoder *encoder = &intel_encoder->base;
5724 struct drm_crtc *crtc = NULL;
5725 struct drm_device *dev = encoder->dev;
5726 struct drm_framebuffer *fb;
5729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5730 connector->base.id, drm_get_connector_name(connector),
5731 encoder->base.id, drm_get_encoder_name(encoder));
5734 * Algorithm gets a little messy:
5736 * - if the connector already has an assigned crtc, use it (but make
5737 * sure it's on first)
5739 * - try to find the first unused crtc that can drive this connector,
5740 * and use that if we find one
5743 /* See if we already have a CRTC for this connector */
5744 if (encoder->crtc) {
5745 crtc = encoder->crtc;
5747 old->dpms_mode = connector->dpms;
5748 old->load_detect_temp = false;
5750 /* Make sure the crtc and connector are running */
5751 if (connector->dpms != DRM_MODE_DPMS_ON)
5752 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5757 /* Find an unused one (if possible) */
5758 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5760 if (!(encoder->possible_crtcs & (1 << i)))
5762 if (!possible_crtc->enabled) {
5763 crtc = possible_crtc;
5769 * If we didn't find an unused CRTC, don't use any.
5772 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5776 encoder->crtc = crtc;
5777 connector->encoder = encoder;
5779 intel_crtc = to_intel_crtc(crtc);
5780 old->dpms_mode = connector->dpms;
5781 old->load_detect_temp = true;
5782 old->release_fb = NULL;
5785 mode = &load_detect_mode;
5787 /* We need a framebuffer large enough to accommodate all accesses
5788 * that the plane may generate whilst we perform load detection.
5789 * We can not rely on the fbcon either being present (we get called
5790 * during its initialisation to detect all boot displays, or it may
5791 * not even exist) or that it is large enough to satisfy the
5794 fb = mode_fits_in_fbdev(dev, mode);
5796 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5797 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5798 old->release_fb = fb;
5800 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5802 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5806 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5807 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5808 if (old->release_fb)
5809 old->release_fb->funcs->destroy(old->release_fb);
5813 /* let the connector get through one full cycle before testing */
5814 intel_wait_for_vblank(dev, intel_crtc->pipe);
5818 connector->encoder = NULL;
5819 encoder->crtc = NULL;
5823 void intel_release_load_detect_pipe(struct drm_connector *connector,
5824 struct intel_load_detect_pipe *old)
5826 struct intel_encoder *intel_encoder =
5827 intel_attached_encoder(connector);
5828 struct drm_encoder *encoder = &intel_encoder->base;
5829 struct drm_device *dev = encoder->dev;
5831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5832 connector->base.id, drm_get_connector_name(connector),
5833 encoder->base.id, drm_get_encoder_name(encoder));
5835 if (old->load_detect_temp) {
5836 connector->encoder = NULL;
5837 encoder->crtc = NULL;
5838 drm_helper_disable_unused_functions(dev);
5840 if (old->release_fb)
5841 old->release_fb->funcs->destroy(old->release_fb);
5846 /* Switch crtc and encoder back off if necessary */
5847 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5848 connector->funcs->dpms(connector, old->dpms_mode);
5851 /* Returns the clock of the currently programmed mode of the given pipe. */
5852 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856 int pipe = intel_crtc->pipe;
5857 u32 dpll = I915_READ(DPLL(pipe));
5859 intel_clock_t clock;
5861 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5862 fp = I915_READ(FP0(pipe));
5864 fp = I915_READ(FP1(pipe));
5866 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5867 if (IS_PINEVIEW(dev)) {
5868 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5869 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5871 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5872 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5875 if (!IS_GEN2(dev)) {
5876 if (IS_PINEVIEW(dev))
5877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5878 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5881 DPLL_FPA01_P1_POST_DIV_SHIFT);
5883 switch (dpll & DPLL_MODE_MASK) {
5884 case DPLLB_MODE_DAC_SERIAL:
5885 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5888 case DPLLB_MODE_LVDS:
5889 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5893 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5894 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5898 /* XXX: Handle the 100Mhz refclk */
5899 intel_clock(dev, 96000, &clock);
5901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5905 DPLL_FPA01_P1_POST_DIV_SHIFT);
5908 if ((dpll & PLL_REF_INPUT_MASK) ==
5909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5910 /* XXX: might not be 66MHz */
5911 intel_clock(dev, 66000, &clock);
5913 intel_clock(dev, 48000, &clock);
5915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5921 if (dpll & PLL_P2_DIVIDE_BY_4)
5926 intel_clock(dev, 48000, &clock);
5930 /* XXX: It would be nice to validate the clocks, but we can't reuse
5931 * i830PllIsValid() because it relies on the xf86_config connector
5932 * configuration being accurate, which it isn't necessarily.
5938 /** Returns the currently programmed mode of the given pipe. */
5939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5940 struct drm_crtc *crtc)
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944 int pipe = intel_crtc->pipe;
5945 struct drm_display_mode *mode;
5946 int htot = I915_READ(HTOTAL(pipe));
5947 int hsync = I915_READ(HSYNC(pipe));
5948 int vtot = I915_READ(VTOTAL(pipe));
5949 int vsync = I915_READ(VSYNC(pipe));
5951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5955 mode->clock = intel_crtc_clock_get(dev, crtc);
5956 mode->hdisplay = (htot & 0xffff) + 1;
5957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5958 mode->hsync_start = (hsync & 0xffff) + 1;
5959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5960 mode->vdisplay = (vtot & 0xffff) + 1;
5961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5962 mode->vsync_start = (vsync & 0xffff) + 1;
5963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5965 drm_mode_set_name(mode);
5970 static void intel_increase_pllclock(struct drm_crtc *crtc)
5972 struct drm_device *dev = crtc->dev;
5973 drm_i915_private_t *dev_priv = dev->dev_private;
5974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5975 int pipe = intel_crtc->pipe;
5976 int dpll_reg = DPLL(pipe);
5979 if (HAS_PCH_SPLIT(dev))
5982 if (!dev_priv->lvds_downclock_avail)
5985 dpll = I915_READ(dpll_reg);
5986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5989 assert_panel_unlocked(dev_priv, pipe);
5991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5992 I915_WRITE(dpll_reg, dpll);
5993 intel_wait_for_vblank(dev, pipe);
5995 dpll = I915_READ(dpll_reg);
5996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6001 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6003 struct drm_device *dev = crtc->dev;
6004 drm_i915_private_t *dev_priv = dev->dev_private;
6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6007 if (HAS_PCH_SPLIT(dev))
6010 if (!dev_priv->lvds_downclock_avail)
6014 * Since this is called by a timer, we should never get here in
6017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6018 int pipe = intel_crtc->pipe;
6019 int dpll_reg = DPLL(pipe);
6022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6024 assert_panel_unlocked(dev_priv, pipe);
6026 dpll = I915_READ(dpll_reg);
6027 dpll |= DISPLAY_RATE_SELECT_FPA1;
6028 I915_WRITE(dpll_reg, dpll);
6029 intel_wait_for_vblank(dev, pipe);
6030 dpll = I915_READ(dpll_reg);
6031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6037 void intel_mark_busy(struct drm_device *dev)
6039 i915_update_gfx_val(dev->dev_private);
6042 void intel_mark_idle(struct drm_device *dev)
6046 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6048 struct drm_device *dev = obj->base.dev;
6049 struct drm_crtc *crtc;
6051 if (!i915_powersave)
6054 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6058 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6059 intel_increase_pllclock(crtc);
6063 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6065 struct drm_device *dev = obj->base.dev;
6066 struct drm_crtc *crtc;
6068 if (!i915_powersave)
6071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6075 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6076 intel_decrease_pllclock(crtc);
6080 static void intel_crtc_destroy(struct drm_crtc *crtc)
6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083 struct drm_device *dev = crtc->dev;
6084 struct intel_unpin_work *work;
6085 unsigned long flags;
6087 spin_lock_irqsave(&dev->event_lock, flags);
6088 work = intel_crtc->unpin_work;
6089 intel_crtc->unpin_work = NULL;
6090 spin_unlock_irqrestore(&dev->event_lock, flags);
6093 cancel_work_sync(&work->work);
6097 drm_crtc_cleanup(crtc);
6102 static void intel_unpin_work_fn(struct work_struct *__work)
6104 struct intel_unpin_work *work =
6105 container_of(__work, struct intel_unpin_work, work);
6107 mutex_lock(&work->dev->struct_mutex);
6108 intel_unpin_fb_obj(work->old_fb_obj);
6109 drm_gem_object_unreference(&work->pending_flip_obj->base);
6110 drm_gem_object_unreference(&work->old_fb_obj->base);
6112 intel_update_fbc(work->dev);
6113 mutex_unlock(&work->dev->struct_mutex);
6117 static void do_intel_finish_page_flip(struct drm_device *dev,
6118 struct drm_crtc *crtc)
6120 drm_i915_private_t *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 struct intel_unpin_work *work;
6123 struct drm_i915_gem_object *obj;
6124 struct drm_pending_vblank_event *e;
6125 struct timeval tnow, tvbl;
6126 unsigned long flags;
6128 /* Ignore early vblank irqs */
6129 if (intel_crtc == NULL)
6132 do_gettimeofday(&tnow);
6134 spin_lock_irqsave(&dev->event_lock, flags);
6135 work = intel_crtc->unpin_work;
6136 if (work == NULL || !work->pending) {
6137 spin_unlock_irqrestore(&dev->event_lock, flags);
6141 intel_crtc->unpin_work = NULL;
6145 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6147 /* Called before vblank count and timestamps have
6148 * been updated for the vblank interval of flip
6149 * completion? Need to increment vblank count and
6150 * add one videorefresh duration to returned timestamp
6151 * to account for this. We assume this happened if we
6152 * get called over 0.9 frame durations after the last
6153 * timestamped vblank.
6155 * This calculation can not be used with vrefresh rates
6156 * below 5Hz (10Hz to be on the safe side) without
6157 * promoting to 64 integers.
6159 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6160 9 * crtc->framedur_ns) {
6161 e->event.sequence++;
6162 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6166 e->event.tv_sec = tvbl.tv_sec;
6167 e->event.tv_usec = tvbl.tv_usec;
6169 list_add_tail(&e->base.link,
6170 &e->base.file_priv->event_list);
6171 wake_up_interruptible(&e->base.file_priv->event_wait);
6174 drm_vblank_put(dev, intel_crtc->pipe);
6176 spin_unlock_irqrestore(&dev->event_lock, flags);
6178 obj = work->old_fb_obj;
6180 atomic_clear_mask(1 << intel_crtc->plane,
6181 &obj->pending_flip.counter);
6182 if (atomic_read(&obj->pending_flip) == 0)
6183 wake_up(&dev_priv->pending_flip_queue);
6185 schedule_work(&work->work);
6187 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6190 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6193 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6195 do_intel_finish_page_flip(dev, crtc);
6198 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6200 drm_i915_private_t *dev_priv = dev->dev_private;
6201 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6203 do_intel_finish_page_flip(dev, crtc);
6206 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6208 drm_i915_private_t *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc =
6210 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6211 unsigned long flags;
6213 spin_lock_irqsave(&dev->event_lock, flags);
6214 if (intel_crtc->unpin_work) {
6215 if ((++intel_crtc->unpin_work->pending) > 1)
6216 DRM_ERROR("Prepared flip multiple times\n");
6218 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6220 spin_unlock_irqrestore(&dev->event_lock, flags);
6223 static int intel_gen2_queue_flip(struct drm_device *dev,
6224 struct drm_crtc *crtc,
6225 struct drm_framebuffer *fb,
6226 struct drm_i915_gem_object *obj)
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6231 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6234 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6238 ret = intel_ring_begin(ring, 6);
6242 /* Can't queue multiple flips, so wait for the previous
6243 * one to finish before executing the next.
6245 if (intel_crtc->plane)
6246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250 intel_ring_emit(ring, MI_NOOP);
6251 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253 intel_ring_emit(ring, fb->pitches[0]);
6254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6255 intel_ring_emit(ring, 0); /* aux display base address, unused */
6256 intel_ring_advance(ring);
6260 intel_unpin_fb_obj(obj);
6265 static int intel_gen3_queue_flip(struct drm_device *dev,
6266 struct drm_crtc *crtc,
6267 struct drm_framebuffer *fb,
6268 struct drm_i915_gem_object *obj)
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6276 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6280 ret = intel_ring_begin(ring, 6);
6284 if (intel_crtc->plane)
6285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6289 intel_ring_emit(ring, MI_NOOP);
6290 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292 intel_ring_emit(ring, fb->pitches[0]);
6293 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6294 intel_ring_emit(ring, MI_NOOP);
6296 intel_ring_advance(ring);
6300 intel_unpin_fb_obj(obj);
6305 static int intel_gen4_queue_flip(struct drm_device *dev,
6306 struct drm_crtc *crtc,
6307 struct drm_framebuffer *fb,
6308 struct drm_i915_gem_object *obj)
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 uint32_t pf, pipesrc;
6313 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6316 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6320 ret = intel_ring_begin(ring, 4);
6324 /* i965+ uses the linear or tiled offsets from the
6325 * Display Registers (which do not change across a page-flip)
6326 * so we need only reprogram the base address.
6328 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6330 intel_ring_emit(ring, fb->pitches[0]);
6331 intel_ring_emit(ring,
6332 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6335 /* XXX Enabling the panel-fitter across page-flip is so far
6336 * untested on non-native modes, so ignore it for now.
6337 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6340 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6341 intel_ring_emit(ring, pf | pipesrc);
6342 intel_ring_advance(ring);
6346 intel_unpin_fb_obj(obj);
6351 static int intel_gen6_queue_flip(struct drm_device *dev,
6352 struct drm_crtc *crtc,
6353 struct drm_framebuffer *fb,
6354 struct drm_i915_gem_object *obj)
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6359 uint32_t pf, pipesrc;
6362 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6366 ret = intel_ring_begin(ring, 4);
6370 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6371 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6372 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6373 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6375 /* Contrary to the suggestions in the documentation,
6376 * "Enable Panel Fitter" does not seem to be required when page
6377 * flipping with a non-native mode, and worse causes a normal
6379 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6382 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6383 intel_ring_emit(ring, pf | pipesrc);
6384 intel_ring_advance(ring);
6388 intel_unpin_fb_obj(obj);
6394 * On gen7 we currently use the blit ring because (in early silicon at least)
6395 * the render ring doesn't give us interrpts for page flip completion, which
6396 * means clients will hang after the first flip is queued. Fortunately the
6397 * blit ring generates interrupts properly, so use it instead.
6399 static int intel_gen7_queue_flip(struct drm_device *dev,
6400 struct drm_crtc *crtc,
6401 struct drm_framebuffer *fb,
6402 struct drm_i915_gem_object *obj)
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6407 uint32_t plane_bit = 0;
6410 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6414 switch(intel_crtc->plane) {
6416 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6419 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6425 WARN_ONCE(1, "unknown plane in flip command\n");
6430 ret = intel_ring_begin(ring, 4);
6434 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6435 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6436 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6437 intel_ring_emit(ring, (MI_NOOP));
6438 intel_ring_advance(ring);
6442 intel_unpin_fb_obj(obj);
6447 static int intel_default_queue_flip(struct drm_device *dev,
6448 struct drm_crtc *crtc,
6449 struct drm_framebuffer *fb,
6450 struct drm_i915_gem_object *obj)
6455 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6456 struct drm_framebuffer *fb,
6457 struct drm_pending_vblank_event *event)
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_framebuffer *intel_fb;
6462 struct drm_i915_gem_object *obj;
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 struct intel_unpin_work *work;
6465 unsigned long flags;
6468 /* Can't change pixel format via MI display flips. */
6469 if (fb->pixel_format != crtc->fb->pixel_format)
6473 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6474 * Note that pitch changes could also affect these register.
6476 if (INTEL_INFO(dev)->gen > 3 &&
6477 (fb->offsets[0] != crtc->fb->offsets[0] ||
6478 fb->pitches[0] != crtc->fb->pitches[0]))
6481 work = kzalloc(sizeof *work, GFP_KERNEL);
6485 work->event = event;
6486 work->dev = crtc->dev;
6487 intel_fb = to_intel_framebuffer(crtc->fb);
6488 work->old_fb_obj = intel_fb->obj;
6489 INIT_WORK(&work->work, intel_unpin_work_fn);
6491 ret = drm_vblank_get(dev, intel_crtc->pipe);
6495 /* We borrow the event spin lock for protecting unpin_work */
6496 spin_lock_irqsave(&dev->event_lock, flags);
6497 if (intel_crtc->unpin_work) {
6498 spin_unlock_irqrestore(&dev->event_lock, flags);
6500 drm_vblank_put(dev, intel_crtc->pipe);
6502 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6505 intel_crtc->unpin_work = work;
6506 spin_unlock_irqrestore(&dev->event_lock, flags);
6508 intel_fb = to_intel_framebuffer(fb);
6509 obj = intel_fb->obj;
6511 ret = i915_mutex_lock_interruptible(dev);
6515 /* Reference the objects for the scheduled work. */
6516 drm_gem_object_reference(&work->old_fb_obj->base);
6517 drm_gem_object_reference(&obj->base);
6521 work->pending_flip_obj = obj;
6523 work->enable_stall_check = true;
6525 /* Block clients from rendering to the new back buffer until
6526 * the flip occurs and the object is no longer visible.
6528 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6532 goto cleanup_pending;
6534 intel_disable_fbc(dev);
6535 intel_mark_fb_busy(obj);
6536 mutex_unlock(&dev->struct_mutex);
6538 trace_i915_flip_request(intel_crtc->plane, obj);
6543 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6544 drm_gem_object_unreference(&work->old_fb_obj->base);
6545 drm_gem_object_unreference(&obj->base);
6546 mutex_unlock(&dev->struct_mutex);
6549 spin_lock_irqsave(&dev->event_lock, flags);
6550 intel_crtc->unpin_work = NULL;
6551 spin_unlock_irqrestore(&dev->event_lock, flags);
6553 drm_vblank_put(dev, intel_crtc->pipe);
6560 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6561 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6562 .load_lut = intel_crtc_load_lut,
6563 .disable = intel_crtc_disable,
6566 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6567 struct drm_crtc *crtc)
6569 struct drm_device *dev;
6570 struct drm_crtc *tmp;
6573 WARN(!crtc, "checking null crtc?\n");
6577 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6583 if (encoder->possible_crtcs & crtc_mask)
6589 intel_crtc_prepare_encoders(struct drm_device *dev)
6591 struct intel_encoder *encoder;
6593 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6594 /* Disable unused encoders */
6595 if (encoder->base.crtc == NULL)
6596 encoder->disable(encoder);
6601 * intel_modeset_update_staged_output_state
6603 * Updates the staged output configuration state, e.g. after we've read out the
6606 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6608 struct intel_encoder *encoder;
6609 struct intel_connector *connector;
6611 list_for_each_entry(connector, &dev->mode_config.connector_list,
6613 connector->new_encoder =
6614 to_intel_encoder(connector->base.encoder);
6617 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6620 to_intel_crtc(encoder->base.crtc);
6625 * intel_modeset_commit_output_state
6627 * This function copies the stage display pipe configuration to the real one.
6629 static void intel_modeset_commit_output_state(struct drm_device *dev)
6631 struct intel_encoder *encoder;
6632 struct intel_connector *connector;
6634 list_for_each_entry(connector, &dev->mode_config.connector_list,
6636 connector->base.encoder = &connector->new_encoder->base;
6639 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6641 encoder->base.crtc = &encoder->new_crtc->base;
6645 bool intel_set_mode(struct drm_crtc *crtc,
6646 struct drm_display_mode *mode,
6647 int x, int y, struct drm_framebuffer *fb)
6649 struct drm_device *dev = crtc->dev;
6650 drm_i915_private_t *dev_priv = dev->dev_private;
6651 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6652 struct drm_encoder_helper_funcs *encoder_funcs;
6653 struct drm_encoder *encoder;
6656 intel_modeset_commit_output_state(dev);
6658 crtc->enabled = drm_helper_crtc_in_use(crtc);
6659 if (!crtc->enabled) {
6660 drm_helper_disable_unused_functions(dev);
6664 adjusted_mode = drm_mode_duplicate(dev, mode);
6668 saved_hwmode = crtc->hwmode;
6669 saved_mode = crtc->mode;
6671 /* Update crtc values up front so the driver can rely on them for mode
6676 /* Pass our mode to the connectors and the CRTC to give them a chance to
6677 * adjust it according to limitations or connector properties, and also
6678 * a chance to reject the mode entirely.
6680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6682 if (encoder->crtc != crtc)
6684 encoder_funcs = encoder->helper_private;
6685 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6687 DRM_DEBUG_KMS("Encoder fixup failed\n");
6692 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6693 DRM_DEBUG_KMS("CRTC fixup failed\n");
6696 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6698 intel_crtc_prepare_encoders(dev);
6700 dev_priv->display.crtc_disable(crtc);
6702 /* Set up the DPLL and any encoders state that needs to adjust or depend
6705 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, fb);
6709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6711 if (encoder->crtc != crtc)
6714 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6715 encoder->base.id, drm_get_encoder_name(encoder),
6716 mode->base.id, mode->name);
6717 encoder_funcs = encoder->helper_private;
6718 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6724 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6725 dev_priv->display.crtc_enable(crtc);
6727 /* Store real post-adjustment hardware mode. */
6728 crtc->hwmode = *adjusted_mode;
6730 /* Calculate and store various constants which
6731 * are later needed by vblank and swap-completion
6732 * timestamping. They are derived from true hwmode.
6734 drm_calc_timestamping_constants(crtc);
6736 /* FIXME: add subpixel order */
6738 drm_mode_destroy(dev, adjusted_mode);
6740 crtc->hwmode = saved_hwmode;
6741 crtc->mode = saved_mode;
6747 static void intel_set_config_free(struct intel_set_config *config)
6752 kfree(config->save_connector_encoders);
6753 kfree(config->save_encoder_crtcs);
6757 static int intel_set_config_save_state(struct drm_device *dev,
6758 struct intel_set_config *config)
6760 struct drm_encoder *encoder;
6761 struct drm_connector *connector;
6764 config->save_encoder_crtcs =
6765 kcalloc(dev->mode_config.num_encoder,
6766 sizeof(struct drm_crtc *), GFP_KERNEL);
6767 if (!config->save_encoder_crtcs)
6770 config->save_connector_encoders =
6771 kcalloc(dev->mode_config.num_connector,
6772 sizeof(struct drm_encoder *), GFP_KERNEL);
6773 if (!config->save_connector_encoders)
6776 /* Copy data. Note that driver private data is not affected.
6777 * Should anything bad happen only the expected state is
6778 * restored, not the drivers personal bookkeeping.
6781 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6782 config->save_encoder_crtcs[count++] = encoder->crtc;
6786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6787 config->save_connector_encoders[count++] = connector->encoder;
6793 static void intel_set_config_restore_state(struct drm_device *dev,
6794 struct intel_set_config *config)
6796 struct intel_encoder *encoder;
6797 struct intel_connector *connector;
6801 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6803 to_intel_crtc(config->save_encoder_crtcs[count++]);
6807 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
6808 connector->new_encoder =
6809 to_intel_encoder(config->save_connector_encoders[count++]);
6814 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
6815 struct intel_set_config *config)
6818 /* We should be able to check here if the fb has the same properties
6819 * and then just flip_or_move it */
6820 if (set->crtc->fb != set->fb) {
6821 /* If we have no fb then treat it as a full mode set */
6822 if (set->crtc->fb == NULL) {
6823 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6824 config->mode_changed = true;
6825 } else if (set->fb == NULL) {
6826 config->mode_changed = true;
6827 } else if (set->fb->depth != set->crtc->fb->depth) {
6828 config->mode_changed = true;
6829 } else if (set->fb->bits_per_pixel !=
6830 set->crtc->fb->bits_per_pixel) {
6831 config->mode_changed = true;
6833 config->fb_changed = true;
6836 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
6837 config->fb_changed = true;
6839 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6840 DRM_DEBUG_KMS("modes are different, full mode set\n");
6841 drm_mode_debug_printmodeline(&set->crtc->mode);
6842 drm_mode_debug_printmodeline(set->mode);
6843 config->mode_changed = true;
6848 intel_modeset_stage_output_state(struct drm_device *dev,
6849 struct drm_mode_set *set,
6850 struct intel_set_config *config)
6852 struct drm_crtc *new_crtc;
6853 struct intel_connector *connector;
6854 struct intel_encoder *encoder;
6857 /* The upper layers ensure that we either disabl a crtc or have a list
6858 * of connectors. For paranoia, double-check this. */
6859 WARN_ON(!set->fb && (set->num_connectors != 0));
6860 WARN_ON(set->fb && (set->num_connectors == 0));
6863 list_for_each_entry(connector, &dev->mode_config.connector_list,
6865 /* Otherwise traverse passed in connector list and get encoders
6867 for (ro = 0; ro < set->num_connectors; ro++) {
6868 if (set->connectors[ro] == &connector->base) {
6869 connector->new_encoder = connector->encoder;
6874 /* If we disable the crtc, disable all its connectors. Also, if
6875 * the connector is on the changing crtc but not on the new
6876 * connector list, disable it. */
6877 if ((!set->fb || ro == set->num_connectors) &&
6878 connector->base.encoder &&
6879 connector->base.encoder->crtc == set->crtc) {
6880 connector->new_encoder = NULL;
6882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6883 connector->base.base.id,
6884 drm_get_connector_name(&connector->base));
6888 if (&connector->new_encoder->base != connector->base.encoder) {
6889 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6890 config->mode_changed = true;
6893 /* Disable all disconnected encoders. */
6894 if (connector->base.status == connector_status_disconnected)
6895 connector->new_encoder = NULL;
6897 /* connector->new_encoder is now updated for all connectors. */
6899 /* Update crtc of enabled connectors. */
6901 list_for_each_entry(connector, &dev->mode_config.connector_list,
6903 if (!connector->new_encoder)
6906 new_crtc = connector->new_encoder->base.crtc;
6908 for (ro = 0; ro < set->num_connectors; ro++) {
6909 if (set->connectors[ro] == &connector->base)
6910 new_crtc = set->crtc;
6913 /* Make sure the new CRTC will work with the encoder */
6914 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
6918 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
6920 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6921 connector->base.base.id,
6922 drm_get_connector_name(&connector->base),
6926 /* Check for any encoders that needs to be disabled. */
6927 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6929 list_for_each_entry(connector,
6930 &dev->mode_config.connector_list,
6932 if (connector->new_encoder == encoder) {
6933 WARN_ON(!connector->new_encoder->new_crtc);
6938 encoder->new_crtc = NULL;
6940 /* Only now check for crtc changes so we don't miss encoders
6941 * that will be disabled. */
6942 if (&encoder->new_crtc->base != encoder->base.crtc) {
6943 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6944 config->mode_changed = true;
6947 /* Now we've also updated encoder->new_crtc for all encoders. */
6952 static int intel_crtc_set_config(struct drm_mode_set *set)
6954 struct drm_device *dev;
6955 struct drm_mode_set save_set;
6956 struct intel_set_config *config;
6962 BUG_ON(!set->crtc->helper_private);
6967 /* The fb helper likes to play gross jokes with ->mode_set_config.
6968 * Unfortunately the crtc helper doesn't do much at all for this case,
6969 * so we have to cope with this madness until the fb helper is fixed up. */
6970 if (set->fb && set->num_connectors == 0)
6974 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6975 set->crtc->base.id, set->fb->base.id,
6976 (int)set->num_connectors, set->x, set->y);
6978 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6981 dev = set->crtc->dev;
6984 config = kzalloc(sizeof(*config), GFP_KERNEL);
6988 ret = intel_set_config_save_state(dev, config);
6992 save_set.crtc = set->crtc;
6993 save_set.mode = &set->crtc->mode;
6994 save_set.x = set->crtc->x;
6995 save_set.y = set->crtc->y;
6996 save_set.fb = set->crtc->fb;
6998 /* Compute whether we need a full modeset, only an fb base update or no
6999 * change at all. In the future we might also check whether only the
7000 * mode changed, e.g. for LVDS where we only change the panel fitter in
7002 intel_set_config_compute_mode_changes(set, config);
7004 ret = intel_modeset_stage_output_state(dev, set, config);
7008 if (config->mode_changed) {
7010 DRM_DEBUG_KMS("attempting to set mode from"
7012 drm_mode_debug_printmodeline(set->mode);
7015 if (!intel_set_mode(set->crtc, set->mode,
7016 set->x, set->y, set->fb)) {
7017 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7018 set->crtc->base.id);
7023 if (set->crtc->enabled) {
7024 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7025 for (i = 0; i < set->num_connectors; i++) {
7026 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7027 drm_get_connector_name(set->connectors[i]));
7028 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7031 } else if (config->fb_changed) {
7032 ret = intel_pipe_set_base(set->crtc,
7033 set->x, set->y, set->fb);
7036 intel_set_config_free(config);
7041 intel_set_config_restore_state(dev, config);
7043 /* Try to restore the config */
7044 if (config->mode_changed &&
7045 !intel_set_mode(save_set.crtc, save_set.mode,
7046 save_set.x, save_set.y, save_set.fb))
7047 DRM_ERROR("failed to restore config after modeset failure\n");
7050 intel_set_config_free(config);
7054 static const struct drm_crtc_funcs intel_crtc_funcs = {
7055 .cursor_set = intel_crtc_cursor_set,
7056 .cursor_move = intel_crtc_cursor_move,
7057 .gamma_set = intel_crtc_gamma_set,
7058 .set_config = intel_crtc_set_config,
7059 .destroy = intel_crtc_destroy,
7060 .page_flip = intel_crtc_page_flip,
7063 static void intel_pch_pll_init(struct drm_device *dev)
7065 drm_i915_private_t *dev_priv = dev->dev_private;
7068 if (dev_priv->num_pch_pll == 0) {
7069 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7073 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7074 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7075 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7076 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7080 static void intel_crtc_init(struct drm_device *dev, int pipe)
7082 drm_i915_private_t *dev_priv = dev->dev_private;
7083 struct intel_crtc *intel_crtc;
7086 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7087 if (intel_crtc == NULL)
7090 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7092 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7093 for (i = 0; i < 256; i++) {
7094 intel_crtc->lut_r[i] = i;
7095 intel_crtc->lut_g[i] = i;
7096 intel_crtc->lut_b[i] = i;
7099 /* Swap pipes & planes for FBC on pre-965 */
7100 intel_crtc->pipe = pipe;
7101 intel_crtc->plane = pipe;
7102 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7103 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7104 intel_crtc->plane = !pipe;
7107 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7108 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7109 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7110 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7112 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7114 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7117 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7118 struct drm_file *file)
7120 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7121 struct drm_mode_object *drmmode_obj;
7122 struct intel_crtc *crtc;
7124 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7127 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7128 DRM_MODE_OBJECT_CRTC);
7131 DRM_ERROR("no such CRTC id\n");
7135 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7136 pipe_from_crtc_id->pipe = crtc->pipe;
7141 static int intel_encoder_clones(struct intel_encoder *encoder)
7143 struct drm_device *dev = encoder->base.dev;
7144 struct intel_encoder *source_encoder;
7148 list_for_each_entry(source_encoder,
7149 &dev->mode_config.encoder_list, base.head) {
7151 if (encoder == source_encoder)
7152 index_mask |= (1 << entry);
7154 /* Intel hw has only one MUX where enocoders could be cloned. */
7155 if (encoder->cloneable && source_encoder->cloneable)
7156 index_mask |= (1 << entry);
7164 static bool has_edp_a(struct drm_device *dev)
7166 struct drm_i915_private *dev_priv = dev->dev_private;
7168 if (!IS_MOBILE(dev))
7171 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7175 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7181 static void intel_setup_outputs(struct drm_device *dev)
7183 struct drm_i915_private *dev_priv = dev->dev_private;
7184 struct intel_encoder *encoder;
7185 bool dpd_is_edp = false;
7188 has_lvds = intel_lvds_init(dev);
7189 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7190 /* disable the panel fitter on everything but LVDS */
7191 I915_WRITE(PFIT_CONTROL, 0);
7194 if (HAS_PCH_SPLIT(dev)) {
7195 dpd_is_edp = intel_dpd_is_edp(dev);
7198 intel_dp_init(dev, DP_A, PORT_A);
7200 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7201 intel_dp_init(dev, PCH_DP_D, PORT_D);
7204 intel_crt_init(dev);
7206 if (IS_HASWELL(dev)) {
7209 /* Haswell uses DDI functions to detect digital outputs */
7210 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7211 /* DDI A only supports eDP */
7213 intel_ddi_init(dev, PORT_A);
7215 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7217 found = I915_READ(SFUSE_STRAP);
7219 if (found & SFUSE_STRAP_DDIB_DETECTED)
7220 intel_ddi_init(dev, PORT_B);
7221 if (found & SFUSE_STRAP_DDIC_DETECTED)
7222 intel_ddi_init(dev, PORT_C);
7223 if (found & SFUSE_STRAP_DDID_DETECTED)
7224 intel_ddi_init(dev, PORT_D);
7225 } else if (HAS_PCH_SPLIT(dev)) {
7228 if (I915_READ(HDMIB) & PORT_DETECTED) {
7229 /* PCH SDVOB multiplex with HDMIB */
7230 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7232 intel_hdmi_init(dev, HDMIB, PORT_B);
7233 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7234 intel_dp_init(dev, PCH_DP_B, PORT_B);
7237 if (I915_READ(HDMIC) & PORT_DETECTED)
7238 intel_hdmi_init(dev, HDMIC, PORT_C);
7240 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7241 intel_hdmi_init(dev, HDMID, PORT_D);
7243 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7244 intel_dp_init(dev, PCH_DP_C, PORT_C);
7246 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7247 intel_dp_init(dev, PCH_DP_D, PORT_D);
7248 } else if (IS_VALLEYVIEW(dev)) {
7251 if (I915_READ(SDVOB) & PORT_DETECTED) {
7252 /* SDVOB multiplex with HDMIB */
7253 found = intel_sdvo_init(dev, SDVOB, true);
7255 intel_hdmi_init(dev, SDVOB, PORT_B);
7256 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7257 intel_dp_init(dev, DP_B, PORT_B);
7260 if (I915_READ(SDVOC) & PORT_DETECTED)
7261 intel_hdmi_init(dev, SDVOC, PORT_C);
7263 /* Shares lanes with HDMI on SDVOC */
7264 if (I915_READ(DP_C) & DP_DETECTED)
7265 intel_dp_init(dev, DP_C, PORT_C);
7266 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7269 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7270 DRM_DEBUG_KMS("probing SDVOB\n");
7271 found = intel_sdvo_init(dev, SDVOB, true);
7272 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7273 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7274 intel_hdmi_init(dev, SDVOB, PORT_B);
7277 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7278 DRM_DEBUG_KMS("probing DP_B\n");
7279 intel_dp_init(dev, DP_B, PORT_B);
7283 /* Before G4X SDVOC doesn't have its own detect register */
7285 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7286 DRM_DEBUG_KMS("probing SDVOC\n");
7287 found = intel_sdvo_init(dev, SDVOC, false);
7290 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7292 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7293 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7294 intel_hdmi_init(dev, SDVOC, PORT_C);
7296 if (SUPPORTS_INTEGRATED_DP(dev)) {
7297 DRM_DEBUG_KMS("probing DP_C\n");
7298 intel_dp_init(dev, DP_C, PORT_C);
7302 if (SUPPORTS_INTEGRATED_DP(dev) &&
7303 (I915_READ(DP_D) & DP_DETECTED)) {
7304 DRM_DEBUG_KMS("probing DP_D\n");
7305 intel_dp_init(dev, DP_D, PORT_D);
7307 } else if (IS_GEN2(dev))
7308 intel_dvo_init(dev);
7310 if (SUPPORTS_TV(dev))
7313 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7314 encoder->base.possible_crtcs = encoder->crtc_mask;
7315 encoder->base.possible_clones =
7316 intel_encoder_clones(encoder);
7319 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7320 ironlake_init_pch_refclk(dev);
7323 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7325 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7327 drm_framebuffer_cleanup(fb);
7328 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7333 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7334 struct drm_file *file,
7335 unsigned int *handle)
7337 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7338 struct drm_i915_gem_object *obj = intel_fb->obj;
7340 return drm_gem_handle_create(file, &obj->base, handle);
7343 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7344 .destroy = intel_user_framebuffer_destroy,
7345 .create_handle = intel_user_framebuffer_create_handle,
7348 int intel_framebuffer_init(struct drm_device *dev,
7349 struct intel_framebuffer *intel_fb,
7350 struct drm_mode_fb_cmd2 *mode_cmd,
7351 struct drm_i915_gem_object *obj)
7355 if (obj->tiling_mode == I915_TILING_Y)
7358 if (mode_cmd->pitches[0] & 63)
7361 switch (mode_cmd->pixel_format) {
7362 case DRM_FORMAT_RGB332:
7363 case DRM_FORMAT_RGB565:
7364 case DRM_FORMAT_XRGB8888:
7365 case DRM_FORMAT_XBGR8888:
7366 case DRM_FORMAT_ARGB8888:
7367 case DRM_FORMAT_XRGB2101010:
7368 case DRM_FORMAT_ARGB2101010:
7369 /* RGB formats are common across chipsets */
7371 case DRM_FORMAT_YUYV:
7372 case DRM_FORMAT_UYVY:
7373 case DRM_FORMAT_YVYU:
7374 case DRM_FORMAT_VYUY:
7377 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7378 mode_cmd->pixel_format);
7382 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7384 DRM_ERROR("framebuffer init failed %d\n", ret);
7388 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7389 intel_fb->obj = obj;
7393 static struct drm_framebuffer *
7394 intel_user_framebuffer_create(struct drm_device *dev,
7395 struct drm_file *filp,
7396 struct drm_mode_fb_cmd2 *mode_cmd)
7398 struct drm_i915_gem_object *obj;
7400 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7401 mode_cmd->handles[0]));
7402 if (&obj->base == NULL)
7403 return ERR_PTR(-ENOENT);
7405 return intel_framebuffer_create(dev, mode_cmd, obj);
7408 static const struct drm_mode_config_funcs intel_mode_funcs = {
7409 .fb_create = intel_user_framebuffer_create,
7410 .output_poll_changed = intel_fb_output_poll_changed,
7413 /* Set up chip specific display functions */
7414 static void intel_init_display(struct drm_device *dev)
7416 struct drm_i915_private *dev_priv = dev->dev_private;
7418 /* We always want a DPMS function */
7419 if (HAS_PCH_SPLIT(dev)) {
7420 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7421 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7422 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7423 dev_priv->display.off = ironlake_crtc_off;
7424 dev_priv->display.update_plane = ironlake_update_plane;
7426 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7427 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7428 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7429 dev_priv->display.off = i9xx_crtc_off;
7430 dev_priv->display.update_plane = i9xx_update_plane;
7433 /* Returns the core display clock speed */
7434 if (IS_VALLEYVIEW(dev))
7435 dev_priv->display.get_display_clock_speed =
7436 valleyview_get_display_clock_speed;
7437 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7438 dev_priv->display.get_display_clock_speed =
7439 i945_get_display_clock_speed;
7440 else if (IS_I915G(dev))
7441 dev_priv->display.get_display_clock_speed =
7442 i915_get_display_clock_speed;
7443 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7444 dev_priv->display.get_display_clock_speed =
7445 i9xx_misc_get_display_clock_speed;
7446 else if (IS_I915GM(dev))
7447 dev_priv->display.get_display_clock_speed =
7448 i915gm_get_display_clock_speed;
7449 else if (IS_I865G(dev))
7450 dev_priv->display.get_display_clock_speed =
7451 i865_get_display_clock_speed;
7452 else if (IS_I85X(dev))
7453 dev_priv->display.get_display_clock_speed =
7454 i855_get_display_clock_speed;
7456 dev_priv->display.get_display_clock_speed =
7457 i830_get_display_clock_speed;
7459 if (HAS_PCH_SPLIT(dev)) {
7461 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7462 dev_priv->display.write_eld = ironlake_write_eld;
7463 } else if (IS_GEN6(dev)) {
7464 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7465 dev_priv->display.write_eld = ironlake_write_eld;
7466 } else if (IS_IVYBRIDGE(dev)) {
7467 /* FIXME: detect B0+ stepping and use auto training */
7468 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7469 dev_priv->display.write_eld = ironlake_write_eld;
7470 } else if (IS_HASWELL(dev)) {
7471 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7472 dev_priv->display.write_eld = haswell_write_eld;
7474 dev_priv->display.update_wm = NULL;
7475 } else if (IS_G4X(dev)) {
7476 dev_priv->display.write_eld = g4x_write_eld;
7479 /* Default just returns -ENODEV to indicate unsupported */
7480 dev_priv->display.queue_flip = intel_default_queue_flip;
7482 switch (INTEL_INFO(dev)->gen) {
7484 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7488 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7493 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7497 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7500 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7506 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7507 * resume, or other times. This quirk makes sure that's the case for
7510 static void quirk_pipea_force(struct drm_device *dev)
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7514 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7515 DRM_INFO("applying pipe a force quirk\n");
7519 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7521 static void quirk_ssc_force_disable(struct drm_device *dev)
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7524 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7525 DRM_INFO("applying lvds SSC disable quirk\n");
7529 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7532 static void quirk_invert_brightness(struct drm_device *dev)
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7536 DRM_INFO("applying inverted panel brightness quirk\n");
7539 struct intel_quirk {
7541 int subsystem_vendor;
7542 int subsystem_device;
7543 void (*hook)(struct drm_device *dev);
7546 static struct intel_quirk intel_quirks[] = {
7547 /* HP Mini needs pipe A force quirk (LP: #322104) */
7548 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7550 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7551 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7553 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7554 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7556 /* 855 & before need to leave pipe A & dpll A up */
7557 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7558 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7559 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7561 /* Lenovo U160 cannot use SSC on LVDS */
7562 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7564 /* Sony Vaio Y cannot use SSC on LVDS */
7565 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7567 /* Acer Aspire 5734Z must invert backlight brightness */
7568 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7571 static void intel_init_quirks(struct drm_device *dev)
7573 struct pci_dev *d = dev->pdev;
7576 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7577 struct intel_quirk *q = &intel_quirks[i];
7579 if (d->device == q->device &&
7580 (d->subsystem_vendor == q->subsystem_vendor ||
7581 q->subsystem_vendor == PCI_ANY_ID) &&
7582 (d->subsystem_device == q->subsystem_device ||
7583 q->subsystem_device == PCI_ANY_ID))
7588 /* Disable the VGA plane that we never use */
7589 static void i915_disable_vga(struct drm_device *dev)
7591 struct drm_i915_private *dev_priv = dev->dev_private;
7595 if (HAS_PCH_SPLIT(dev))
7596 vga_reg = CPU_VGACNTRL;
7600 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7601 outb(SR01, VGA_SR_INDEX);
7602 sr1 = inb(VGA_SR_DATA);
7603 outb(sr1 | 1<<5, VGA_SR_DATA);
7604 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7607 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7608 POSTING_READ(vga_reg);
7611 void intel_modeset_init_hw(struct drm_device *dev)
7613 /* We attempt to init the necessary power wells early in the initialization
7614 * time, so the subsystems that expect power to be enabled can work.
7616 intel_init_power_wells(dev);
7618 intel_prepare_ddi(dev);
7620 intel_init_clock_gating(dev);
7622 mutex_lock(&dev->struct_mutex);
7623 intel_enable_gt_powersave(dev);
7624 mutex_unlock(&dev->struct_mutex);
7627 void intel_modeset_init(struct drm_device *dev)
7629 struct drm_i915_private *dev_priv = dev->dev_private;
7632 drm_mode_config_init(dev);
7634 dev->mode_config.min_width = 0;
7635 dev->mode_config.min_height = 0;
7637 dev->mode_config.preferred_depth = 24;
7638 dev->mode_config.prefer_shadow = 1;
7640 dev->mode_config.funcs = &intel_mode_funcs;
7642 intel_init_quirks(dev);
7646 intel_init_display(dev);
7649 dev->mode_config.max_width = 2048;
7650 dev->mode_config.max_height = 2048;
7651 } else if (IS_GEN3(dev)) {
7652 dev->mode_config.max_width = 4096;
7653 dev->mode_config.max_height = 4096;
7655 dev->mode_config.max_width = 8192;
7656 dev->mode_config.max_height = 8192;
7658 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7660 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7661 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7663 for (i = 0; i < dev_priv->num_pipe; i++) {
7664 intel_crtc_init(dev, i);
7665 ret = intel_plane_init(dev, i);
7667 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7670 intel_pch_pll_init(dev);
7672 /* Just disable it once at startup */
7673 i915_disable_vga(dev);
7674 intel_setup_outputs(dev);
7678 intel_connector_break_all_links(struct intel_connector *connector)
7680 connector->base.dpms = DRM_MODE_DPMS_OFF;
7681 connector->base.encoder = NULL;
7682 connector->encoder->connectors_active = false;
7683 connector->encoder->base.crtc = NULL;
7686 static void intel_enable_pipe_a(struct drm_device *dev)
7688 struct intel_connector *connector;
7689 struct drm_connector *crt = NULL;
7690 struct intel_load_detect_pipe load_detect_temp;
7692 /* We can't just switch on the pipe A, we need to set things up with a
7693 * proper mode and output configuration. As a gross hack, enable pipe A
7694 * by enabling the load detect pipe once. */
7695 list_for_each_entry(connector,
7696 &dev->mode_config.connector_list,
7698 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7699 crt = &connector->base;
7707 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7708 intel_release_load_detect_pipe(crt, &load_detect_temp);
7713 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7719 /* Clear any frame start delays used for debugging left by the BIOS */
7720 reg = PIPECONF(crtc->pipe);
7721 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7723 /* We need to sanitize the plane -> pipe mapping first because this will
7724 * disable the crtc (and hence change the state) if it is wrong. */
7725 if (!HAS_PCH_SPLIT(dev)) {
7726 struct intel_connector *connector;
7729 reg = DSPCNTR(crtc->plane);
7730 val = I915_READ(reg);
7732 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7733 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7736 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7737 crtc->base.base.id);
7739 /* Pipe has the wrong plane attached and the plane is active.
7740 * Temporarily change the plane mapping and disable everything
7742 plane = crtc->plane;
7743 crtc->plane = !plane;
7744 dev_priv->display.crtc_disable(&crtc->base);
7745 crtc->plane = plane;
7747 /* ... and break all links. */
7748 list_for_each_entry(connector, &dev->mode_config.connector_list,
7750 if (connector->encoder->base.crtc != &crtc->base)
7753 intel_connector_break_all_links(connector);
7756 WARN_ON(crtc->active);
7757 crtc->base.enabled = false;
7761 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7762 crtc->pipe == PIPE_A && !crtc->active) {
7763 /* BIOS forgot to enable pipe A, this mostly happens after
7764 * resume. Force-enable the pipe to fix this, the update_dpms
7765 * call below we restore the pipe to the right state, but leave
7766 * the required bits on. */
7767 intel_enable_pipe_a(dev);
7770 /* Adjust the state of the output pipe according to whether we
7771 * have active connectors/encoders. */
7772 intel_crtc_update_dpms(&crtc->base);
7774 if (crtc->active != crtc->base.enabled) {
7775 struct intel_encoder *encoder;
7777 /* This can happen either due to bugs in the get_hw_state
7778 * functions or because the pipe is force-enabled due to the
7780 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7782 crtc->base.enabled ? "enabled" : "disabled",
7783 crtc->active ? "enabled" : "disabled");
7785 crtc->base.enabled = crtc->active;
7787 /* Because we only establish the connector -> encoder ->
7788 * crtc links if something is active, this means the
7789 * crtc is now deactivated. Break the links. connector
7790 * -> encoder links are only establish when things are
7791 * actually up, hence no need to break them. */
7792 WARN_ON(crtc->active);
7794 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7795 WARN_ON(encoder->connectors_active);
7796 encoder->base.crtc = NULL;
7801 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7803 struct intel_connector *connector;
7804 struct drm_device *dev = encoder->base.dev;
7806 /* We need to check both for a crtc link (meaning that the
7807 * encoder is active and trying to read from a pipe) and the
7808 * pipe itself being active. */
7809 bool has_active_crtc = encoder->base.crtc &&
7810 to_intel_crtc(encoder->base.crtc)->active;
7812 if (encoder->connectors_active && !has_active_crtc) {
7813 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7814 encoder->base.base.id,
7815 drm_get_encoder_name(&encoder->base));
7817 /* Connector is active, but has no active pipe. This is
7818 * fallout from our resume register restoring. Disable
7819 * the encoder manually again. */
7820 if (encoder->base.crtc) {
7821 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7822 encoder->base.base.id,
7823 drm_get_encoder_name(&encoder->base));
7824 encoder->disable(encoder);
7827 /* Inconsistent output/port/pipe state happens presumably due to
7828 * a bug in one of the get_hw_state functions. Or someplace else
7829 * in our code, like the register restore mess on resume. Clamp
7830 * things to off as a safer default. */
7831 list_for_each_entry(connector,
7832 &dev->mode_config.connector_list,
7834 if (connector->encoder != encoder)
7837 intel_connector_break_all_links(connector);
7840 /* Enabled encoders without active connectors will be fixed in
7841 * the crtc fixup. */
7844 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7845 * and i915 state tracking structures. */
7846 void intel_modeset_setup_hw_state(struct drm_device *dev)
7848 struct drm_i915_private *dev_priv = dev->dev_private;
7851 struct intel_crtc *crtc;
7852 struct intel_encoder *encoder;
7853 struct intel_connector *connector;
7855 for_each_pipe(pipe) {
7856 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7858 tmp = I915_READ(PIPECONF(pipe));
7859 if (tmp & PIPECONF_ENABLE)
7860 crtc->active = true;
7862 crtc->active = false;
7864 crtc->base.enabled = crtc->active;
7866 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7868 crtc->active ? "enabled" : "disabled");
7871 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7875 if (encoder->get_hw_state(encoder, &pipe)) {
7876 encoder->base.crtc =
7877 dev_priv->pipe_to_crtc_mapping[pipe];
7879 encoder->base.crtc = NULL;
7882 encoder->connectors_active = false;
7883 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7884 encoder->base.base.id,
7885 drm_get_encoder_name(&encoder->base),
7886 encoder->base.crtc ? "enabled" : "disabled",
7890 list_for_each_entry(connector, &dev->mode_config.connector_list,
7892 if (connector->get_hw_state(connector)) {
7893 connector->base.dpms = DRM_MODE_DPMS_ON;
7894 connector->encoder->connectors_active = true;
7895 connector->base.encoder = &connector->encoder->base;
7897 connector->base.dpms = DRM_MODE_DPMS_OFF;
7898 connector->base.encoder = NULL;
7900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7901 connector->base.base.id,
7902 drm_get_connector_name(&connector->base),
7903 connector->base.encoder ? "enabled" : "disabled");
7906 /* HW state is read out, now we need to sanitize this mess. */
7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7909 intel_sanitize_encoder(encoder);
7912 for_each_pipe(pipe) {
7913 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7914 intel_sanitize_crtc(crtc);
7917 intel_modeset_update_staged_output_state(dev);
7920 void intel_modeset_gem_init(struct drm_device *dev)
7922 intel_modeset_init_hw(dev);
7924 intel_setup_overlay(dev);
7926 intel_modeset_setup_hw_state(dev);
7929 void intel_modeset_cleanup(struct drm_device *dev)
7931 struct drm_i915_private *dev_priv = dev->dev_private;
7932 struct drm_crtc *crtc;
7933 struct intel_crtc *intel_crtc;
7935 drm_kms_helper_poll_fini(dev);
7936 mutex_lock(&dev->struct_mutex);
7938 intel_unregister_dsm_handler();
7941 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7942 /* Skip inactive CRTCs */
7946 intel_crtc = to_intel_crtc(crtc);
7947 intel_increase_pllclock(crtc);
7950 intel_disable_fbc(dev);
7952 intel_disable_gt_powersave(dev);
7954 ironlake_teardown_rc6(dev);
7956 if (IS_VALLEYVIEW(dev))
7959 mutex_unlock(&dev->struct_mutex);
7961 /* Disable the irq before mode object teardown, for the irq might
7962 * enqueue unpin/hotplug work. */
7963 drm_irq_uninstall(dev);
7964 cancel_work_sync(&dev_priv->hotplug_work);
7965 cancel_work_sync(&dev_priv->rps.work);
7967 /* flush any delayed tasks or pending work */
7968 flush_scheduled_work();
7970 drm_mode_config_cleanup(dev);
7974 * Return which encoder is currently attached for connector.
7976 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7978 return &intel_attached_encoder(connector)->base;
7981 void intel_connector_attach_encoder(struct intel_connector *connector,
7982 struct intel_encoder *encoder)
7984 connector->encoder = encoder;
7985 drm_mode_connector_attach_encoder(&connector->base,
7990 * set vga decode state - true == enable VGA decode
7992 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7994 struct drm_i915_private *dev_priv = dev->dev_private;
7997 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7999 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8001 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8002 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8006 #ifdef CONFIG_DEBUG_FS
8007 #include <linux/seq_file.h>
8009 struct intel_display_error_state {
8010 struct intel_cursor_error_state {
8015 } cursor[I915_MAX_PIPES];
8017 struct intel_pipe_error_state {
8027 } pipe[I915_MAX_PIPES];
8029 struct intel_plane_error_state {
8037 } plane[I915_MAX_PIPES];
8040 struct intel_display_error_state *
8041 intel_display_capture_error_state(struct drm_device *dev)
8043 drm_i915_private_t *dev_priv = dev->dev_private;
8044 struct intel_display_error_state *error;
8047 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8052 error->cursor[i].control = I915_READ(CURCNTR(i));
8053 error->cursor[i].position = I915_READ(CURPOS(i));
8054 error->cursor[i].base = I915_READ(CURBASE(i));
8056 error->plane[i].control = I915_READ(DSPCNTR(i));
8057 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8058 error->plane[i].size = I915_READ(DSPSIZE(i));
8059 error->plane[i].pos = I915_READ(DSPPOS(i));
8060 error->plane[i].addr = I915_READ(DSPADDR(i));
8061 if (INTEL_INFO(dev)->gen >= 4) {
8062 error->plane[i].surface = I915_READ(DSPSURF(i));
8063 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8066 error->pipe[i].conf = I915_READ(PIPECONF(i));
8067 error->pipe[i].source = I915_READ(PIPESRC(i));
8068 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8069 error->pipe[i].hblank = I915_READ(HBLANK(i));
8070 error->pipe[i].hsync = I915_READ(HSYNC(i));
8071 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8072 error->pipe[i].vblank = I915_READ(VBLANK(i));
8073 error->pipe[i].vsync = I915_READ(VSYNC(i));
8080 intel_display_print_error_state(struct seq_file *m,
8081 struct drm_device *dev,
8082 struct intel_display_error_state *error)
8084 drm_i915_private_t *dev_priv = dev->dev_private;
8087 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8089 seq_printf(m, "Pipe [%d]:\n", i);
8090 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8091 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8092 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8093 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8094 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8095 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8096 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8097 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8099 seq_printf(m, "Plane [%d]:\n", i);
8100 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8101 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8102 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8103 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8104 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8105 if (INTEL_INFO(dev)->gen >= 4) {
8106 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8107 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8110 seq_printf(m, "Cursor [%d]:\n", i);
8111 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8112 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8113 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);