Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 941 {
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         u32 frame, frame_reg = PIPEFRAME(pipe);
 944
 945         frame = I915_READ(frame_reg);
 946
 947         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 948                 DRM_DEBUG_KMS("vblank wait timed out\n");
 949 }
 950
 951 /**
 952  * intel_wait_for_vblank - wait for vblank on a given pipe
 953  * @dev: drm device
 954  * @pipe: pipe to wait for
 955  *
 956  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 957  * mode setting code.
 958  */
 959 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 960 {
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         int pipestat_reg = PIPESTAT(pipe);
 963
 964         if (INTEL_INFO(dev)->gen >= 5) {
 965                 ironlake_wait_for_vblank(dev, pipe);
 966                 return;
 967         }
 968
 969         /* Clear existing vblank status. Note this will clear any other
 970          * sticky status fields as well.
 971          *
 972          * This races with i915_driver_irq_handler() with the result
 973          * that either function could miss a vblank event.  Here it is not
 974          * fatal, as we will either wait upon the next vblank interrupt or
 975          * timeout.  Generally speaking intel_wait_for_vblank() is only
 976          * called during modeset at which time the GPU should be idle and
 977          * should *not* be performing page flips and thus not waiting on
 978          * vblanks...
 979          * Currently, the result of us stealing a vblank from the irq
 980          * handler is that a single frame will be skipped during swapbuffers.
 981          */
 982         I915_WRITE(pipestat_reg,
 983                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 984
 985         /* Wait for vblank interrupt bit to set */
 986         if (wait_for(I915_READ(pipestat_reg) &
 987                      PIPE_VBLANK_INTERRUPT_STATUS,
 988                      50))
 989                 DRM_DEBUG_KMS("vblank wait timed out\n");
 990 }
 991
 992 /*
 993  * intel_wait_for_pipe_off - wait for pipe to turn off
 994  * @dev: drm device
 995  * @pipe: pipe to wait for
 996  *
 997  * After disabling a pipe, we can't wait for vblank in the usual way,
 998  * spinning on the vblank interrupt status bit, since we won't actually
 999  * see an interrupt when the pipe is disabled.
1000  *
1001  * On Gen4 and above:
1002  *   wait for the pipe register state bit to turn off
1003  *
1004  * Otherwise:
1005  *   wait for the display line value to settle (it usually
1006  *   ends up stopping at the start of the next frame).
1007  *
1008  */
1009 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013         if (INTEL_INFO(dev)->gen >= 4) {
1014                 int reg = PIPECONF(pipe);
1015
1016                 /* Wait for the Pipe State to go off */
1017                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1018                              100))
1019                         WARN(1, "pipe_off wait timed out\n");
1020         } else {
1021                 u32 last_line, line_mask;
1022                 int reg = PIPEDSL(pipe);
1023                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1024
1025                 if (IS_GEN2(dev))
1026                         line_mask = DSL_LINEMASK_GEN2;
1027                 else
1028                         line_mask = DSL_LINEMASK_GEN3;
1029
1030                 /* Wait for the display line to settle */
1031                 do {
1032                         last_line = I915_READ(reg) & line_mask;
1033                         mdelay(5);
1034                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1035                          time_after(timeout, jiffies));
1036                 if (time_after(jiffies, timeout))
1037                         WARN(1, "pipe_off wait timed out\n");
1038         }
1039 }
1040
1041 static const char *state_string(bool enabled)
1042 {
1043         return enabled ? "on" : "off";
1044 }
1045
1046 /* Only for pre-ILK configs */
1047 static void assert_pll(struct drm_i915_private *dev_priv,
1048                        enum pipe pipe, bool state)
1049 {
1050         int reg;
1051         u32 val;
1052         bool cur_state;
1053
1054         reg = DPLL(pipe);
1055         val = I915_READ(reg);
1056         cur_state = !!(val & DPLL_VCO_ENABLE);
1057         WARN(cur_state != state,
1058              "PLL state assertion failure (expected %s, current %s)\n",
1059              state_string(state), state_string(cur_state));
1060 }
1061 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1062 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1063
1064 /* For ILK+ */
1065 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1066                            struct intel_pch_pll *pll,
1067                            struct intel_crtc *crtc,
1068                            bool state)
1069 {
1070         u32 val;
1071         bool cur_state;
1072
1073         if (HAS_PCH_LPT(dev_priv->dev)) {
1074                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1075                 return;
1076         }
1077
1078         if (WARN (!pll,
1079                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1080                 return;
1081
1082         val = I915_READ(pll->pll_reg);
1083         cur_state = !!(val & DPLL_VCO_ENABLE);
1084         WARN(cur_state != state,
1085              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1086              pll->pll_reg, state_string(state), state_string(cur_state), val);
1087
1088         /* Make sure the selected PLL is correctly attached to the transcoder */
1089         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1090                 u32 pch_dpll;
1091
1092                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1093                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1094                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1095                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1096                           cur_state, crtc->pipe, pch_dpll)) {
1097                         cur_state = !!(val >> (4*crtc->pipe + 3));
1098                         WARN(cur_state != state,
1099                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1100                              pll->pll_reg == _PCH_DPLL_B,
1101                              state_string(state),
1102                              crtc->pipe,
1103                              val);
1104                 }
1105         }
1106 }
1107 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1108 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1109
1110 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         int reg;
1114         u32 val;
1115         bool cur_state;
1116
1117         if (IS_HASWELL(dev_priv->dev)) {
1118                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1119                 reg = DDI_FUNC_CTL(pipe);
1120                 val = I915_READ(reg);
1121                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1122         } else {
1123                 reg = FDI_TX_CTL(pipe);
1124                 val = I915_READ(reg);
1125                 cur_state = !!(val & FDI_TX_ENABLE);
1126         }
1127         WARN(cur_state != state,
1128              "FDI TX state assertion failure (expected %s, current %s)\n",
1129              state_string(state), state_string(cur_state));
1130 }
1131 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1132 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1133
1134 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1135                           enum pipe pipe, bool state)
1136 {
1137         int reg;
1138         u32 val;
1139         bool cur_state;
1140
1141         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1142                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1143                         return;
1144         } else {
1145                 reg = FDI_RX_CTL(pipe);
1146                 val = I915_READ(reg);
1147                 cur_state = !!(val & FDI_RX_ENABLE);
1148         }
1149         WARN(cur_state != state,
1150              "FDI RX state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1154 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1155
1156 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1157                                       enum pipe pipe)
1158 {
1159         int reg;
1160         u32 val;
1161
1162         /* ILK FDI PLL is always enabled */
1163         if (dev_priv->info->gen == 5)
1164                 return;
1165
1166         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1167         if (IS_HASWELL(dev_priv->dev))
1168                 return;
1169
1170         reg = FDI_TX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1176                                       enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1182                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1183                 return;
1184         }
1185         reg = FDI_RX_CTL(pipe);
1186         val = I915_READ(reg);
1187         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                                   enum pipe pipe)
1192 {
1193         int pp_reg, lvds_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1199                 pp_reg = PCH_PP_CONTROL;
1200                 lvds_reg = PCH_LVDS;
1201         } else {
1202                 pp_reg = PP_CONTROL;
1203                 lvds_reg = LVDS;
1204         }
1205
1206         val = I915_READ(pp_reg);
1207         if (!(val & PANEL_POWER_ON) ||
1208             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1209                 locked = false;
1210
1211         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1212                 panel_pipe = PIPE_B;
1213
1214         WARN(panel_pipe == pipe && locked,
1215              "panel assertion failure, pipe %c regs locked\n",
1216              pipe_name(pipe));
1217 }
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         reg = PIPECONF(pipe);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & PIPECONF_ENABLE);
1233         WARN(cur_state != state,
1234              "pipe %c assertion failure (expected %s, current %s)\n",
1235              pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237
1238 static void assert_plane(struct drm_i915_private *dev_priv,
1239                          enum plane plane, bool state)
1240 {
1241         int reg;
1242         u32 val;
1243         bool cur_state;
1244
1245         reg = DSPCNTR(plane);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1248         WARN(cur_state != state,
1249              "plane %c assertion failure (expected %s, current %s)\n",
1250              plane_name(plane), state_string(state), state_string(cur_state));
1251 }
1252
1253 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1254 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1255
1256 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1257                                    enum pipe pipe)
1258 {
1259         int reg, i;
1260         u32 val;
1261         int cur_pipe;
1262
1263         /* Planes are fixed to pipes on ILK+ */
1264         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1265                 reg = DSPCNTR(pipe);
1266                 val = I915_READ(reg);
1267                 WARN((val & DISPLAY_PLANE_ENABLE),
1268                      "plane %c assertion failure, should be disabled but not\n",
1269                      plane_name(pipe));
1270                 return;
1271         }
1272
1273         /* Need to check both planes against the pipe */
1274         for (i = 0; i < 2; i++) {
1275                 reg = DSPCNTR(i);
1276                 val = I915_READ(reg);
1277                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1278                         DISPPLANE_SEL_PIPE_SHIFT;
1279                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1280                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1281                      plane_name(i), pipe_name(pipe));
1282         }
1283 }
1284
1285 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1286 {
1287         u32 val;
1288         bool enabled;
1289
1290         if (HAS_PCH_LPT(dev_priv->dev)) {
1291                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1292                 return;
1293         }
1294
1295         val = I915_READ(PCH_DREF_CONTROL);
1296         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1297                             DREF_SUPERSPREAD_SOURCE_MASK));
1298         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1299 }
1300
1301 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1302                                        enum pipe pipe)
1303 {
1304         int reg;
1305         u32 val;
1306         bool enabled;
1307
1308         reg = TRANSCONF(pipe);
1309         val = I915_READ(reg);
1310         enabled = !!(val & TRANS_ENABLE);
1311         WARN(enabled,
1312              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313              pipe_name(pipe));
1314 }
1315
1316 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1317                             enum pipe pipe, u32 port_sel, u32 val)
1318 {
1319         if ((val & DP_PORT_EN) == 0)
1320                 return false;
1321
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1324                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1325                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1326                         return false;
1327         } else {
1328                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1329                         return false;
1330         }
1331         return true;
1332 }
1333
1334 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1335                               enum pipe pipe, u32 val)
1336 {
1337         if ((val & PORT_ENABLE) == 0)
1338                 return false;
1339
1340         if (HAS_PCH_CPT(dev_priv->dev)) {
1341                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & LVDS_PORT_EN) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1358                         return false;
1359         } else {
1360                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1361                         return false;
1362         }
1363         return true;
1364 }
1365
1366 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1367                               enum pipe pipe, u32 val)
1368 {
1369         if ((val & ADPA_DAC_ENABLE) == 0)
1370                 return false;
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1382                                    enum pipe pipe, int reg, u32 port_sel)
1383 {
1384         u32 val = I915_READ(reg);
1385         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1386              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1387              reg, pipe_name(pipe));
1388
1389         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1390              && (val & DP_PIPEB_SELECT),
1391              "IBX PCH dp port still using transcoder B\n");
1392 }
1393
1394 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1395                                      enum pipe pipe, int reg)
1396 {
1397         u32 val = I915_READ(reg);
1398         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1399              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1400              reg, pipe_name(pipe));
1401
1402         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1403              && (val & SDVO_PIPE_B_SELECT),
1404              "IBX PCH hdmi port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1408                                       enum pipe pipe)
1409 {
1410         int reg;
1411         u32 val;
1412
1413         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1414         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1415         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1416
1417         reg = PCH_ADPA;
1418         val = I915_READ(reg);
1419         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1420              "PCH VGA enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         reg = PCH_LVDS;
1424         val = I915_READ(reg);
1425         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1426              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1427              pipe_name(pipe));
1428
1429         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1430         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1431         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1432 }
1433
1434 /**
1435  * intel_enable_pll - enable a PLL
1436  * @dev_priv: i915 private structure
1437  * @pipe: pipe PLL to enable
1438  *
1439  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1440  * make sure the PLL reg is writable first though, since the panel write
1441  * protect mechanism may be enabled.
1442  *
1443  * Note!  This is for pre-ILK only.
1444  *
1445  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1446  */
1447 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451
1452         /* No really, not for ILK+ */
1453         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1454
1455         /* PLL is protected by panel, make sure we can write it */
1456         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1457                 assert_panel_unlocked(dev_priv, pipe);
1458
1459         reg = DPLL(pipe);
1460         val = I915_READ(reg);
1461         val |= DPLL_VCO_ENABLE;
1462
1463         /* We do this three times for luck */
1464         I915_WRITE(reg, val);
1465         POSTING_READ(reg);
1466         udelay(150); /* wait for warmup */
1467         I915_WRITE(reg, val);
1468         POSTING_READ(reg);
1469         udelay(150); /* wait for warmup */
1470         I915_WRITE(reg, val);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473 }
1474
1475 /**
1476  * intel_disable_pll - disable a PLL
1477  * @dev_priv: i915 private structure
1478  * @pipe: pipe PLL to disable
1479  *
1480  * Disable the PLL for @pipe, making sure the pipe is off first.
1481  *
1482  * Note!  This is for pre-ILK only.
1483  */
1484 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1485 {
1486         int reg;
1487         u32 val;
1488
1489         /* Don't disable pipe A or pipe A PLLs if needed */
1490         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1491                 return;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         reg = DPLL(pipe);
1497         val = I915_READ(reg);
1498         val &= ~DPLL_VCO_ENABLE;
1499         I915_WRITE(reg, val);
1500         POSTING_READ(reg);
1501 }
1502
1503 /* SBI access */
1504 static void
1505 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1506 {
1507         unsigned long flags;
1508
1509         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1510         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1511                                 100)) {
1512                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1513                 goto out_unlock;
1514         }
1515
1516         I915_WRITE(SBI_ADDR,
1517                         (reg << 16));
1518         I915_WRITE(SBI_DATA,
1519                         value);
1520         I915_WRITE(SBI_CTL_STAT,
1521                         SBI_BUSY |
1522                         SBI_CTL_OP_CRWR);
1523
1524         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1525                                 100)) {
1526                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1527                 goto out_unlock;
1528         }
1529
1530 out_unlock:
1531         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1532 }
1533
1534 static u32
1535 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1536 {
1537         unsigned long flags;
1538         u32 value = 0;
1539
1540         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1544                 goto out_unlock;
1545         }
1546
1547         I915_WRITE(SBI_ADDR,
1548                         (reg << 16));
1549         I915_WRITE(SBI_CTL_STAT,
1550                         SBI_BUSY |
1551                         SBI_CTL_OP_CRRD);
1552
1553         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1554                                 100)) {
1555                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1556                 goto out_unlock;
1557         }
1558
1559         value = I915_READ(SBI_DATA);
1560
1561 out_unlock:
1562         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1563         return value;
1564 }
1565
1566 /**
1567  * intel_enable_pch_pll - enable PCH PLL
1568  * @dev_priv: i915 private structure
1569  * @pipe: pipe PLL to enable
1570  *
1571  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1572  * drives the transcoder clock.
1573  */
1574 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1575 {
1576         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1577         struct intel_pch_pll *pll;
1578         int reg;
1579         u32 val;
1580
1581         /* PCH PLLs only available on ILK, SNB and IVB */
1582         BUG_ON(dev_priv->info->gen < 5);
1583         pll = intel_crtc->pch_pll;
1584         if (pll == NULL)
1585                 return;
1586
1587         if (WARN_ON(pll->refcount == 0))
1588                 return;
1589
1590         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1591                       pll->pll_reg, pll->active, pll->on,
1592                       intel_crtc->base.base.id);
1593
1594         /* PCH refclock must be enabled first */
1595         assert_pch_refclk_enabled(dev_priv);
1596
1597         if (pll->active++ && pll->on) {
1598                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1599                 return;
1600         }
1601
1602         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1603
1604         reg = pll->pll_reg;
1605         val = I915_READ(reg);
1606         val |= DPLL_VCO_ENABLE;
1607         I915_WRITE(reg, val);
1608         POSTING_READ(reg);
1609         udelay(200);
1610
1611         pll->on = true;
1612 }
1613
1614 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1615 {
1616         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1617         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1618         int reg;
1619         u32 val;
1620
1621         /* PCH only available on ILK+ */
1622         BUG_ON(dev_priv->info->gen < 5);
1623         if (pll == NULL)
1624                return;
1625
1626         if (WARN_ON(pll->refcount == 0))
1627                 return;
1628
1629         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1630                       pll->pll_reg, pll->active, pll->on,
1631                       intel_crtc->base.base.id);
1632
1633         if (WARN_ON(pll->active == 0)) {
1634                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1635                 return;
1636         }
1637
1638         if (--pll->active) {
1639                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1640                 return;
1641         }
1642
1643         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1644
1645         /* Make sure transcoder isn't still depending on us */
1646         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1647
1648         reg = pll->pll_reg;
1649         val = I915_READ(reg);
1650         val &= ~DPLL_VCO_ENABLE;
1651         I915_WRITE(reg, val);
1652         POSTING_READ(reg);
1653         udelay(200);
1654
1655         pll->on = false;
1656 }
1657
1658 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1659                                     enum pipe pipe)
1660 {
1661         int reg;
1662         u32 val, pipeconf_val;
1663         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1664
1665         /* PCH only available on ILK+ */
1666         BUG_ON(dev_priv->info->gen < 5);
1667
1668         /* Make sure PCH DPLL is enabled */
1669         assert_pch_pll_enabled(dev_priv,
1670                                to_intel_crtc(crtc)->pch_pll,
1671                                to_intel_crtc(crtc));
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, pipe);
1675         assert_fdi_rx_enabled(dev_priv, pipe);
1676
1677         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1678                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1679                 return;
1680         }
1681         reg = TRANSCONF(pipe);
1682         val = I915_READ(reg);
1683         pipeconf_val = I915_READ(PIPECONF(pipe));
1684
1685         if (HAS_PCH_IBX(dev_priv->dev)) {
1686                 /*
1687                  * make the BPC in transcoder be consistent with
1688                  * that in pipeconf reg.
1689                  */
1690                 val &= ~PIPE_BPC_MASK;
1691                 val |= pipeconf_val & PIPE_BPC_MASK;
1692         }
1693
1694         val &= ~TRANS_INTERLACE_MASK;
1695         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1696                 if (HAS_PCH_IBX(dev_priv->dev) &&
1697                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1698                         val |= TRANS_LEGACY_INTERLACED_ILK;
1699                 else
1700                         val |= TRANS_INTERLACED;
1701         else
1702                 val |= TRANS_PROGRESSIVE;
1703
1704         I915_WRITE(reg, val | TRANS_ENABLE);
1705         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1706                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1707 }
1708
1709 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1710                                      enum pipe pipe)
1711 {
1712         int reg;
1713         u32 val;
1714
1715         /* FDI relies on the transcoder */
1716         assert_fdi_tx_disabled(dev_priv, pipe);
1717         assert_fdi_rx_disabled(dev_priv, pipe);
1718
1719         /* Ports must be off as well */
1720         assert_pch_ports_disabled(dev_priv, pipe);
1721
1722         reg = TRANSCONF(pipe);
1723         val = I915_READ(reg);
1724         val &= ~TRANS_ENABLE;
1725         I915_WRITE(reg, val);
1726         /* wait for PCH transcoder off, transcoder state */
1727         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1728                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1729 }
1730
1731 /**
1732  * intel_enable_pipe - enable a pipe, asserting requirements
1733  * @dev_priv: i915 private structure
1734  * @pipe: pipe to enable
1735  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1736  *
1737  * Enable @pipe, making sure that various hardware specific requirements
1738  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1739  *
1740  * @pipe should be %PIPE_A or %PIPE_B.
1741  *
1742  * Will wait until the pipe is actually running (i.e. first vblank) before
1743  * returning.
1744  */
1745 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1746                               bool pch_port)
1747 {
1748         int reg;
1749         u32 val;
1750
1751         /*
1752          * A pipe without a PLL won't actually be able to drive bits from
1753          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1754          * need the check.
1755          */
1756         if (!HAS_PCH_SPLIT(dev_priv->dev))
1757                 assert_pll_enabled(dev_priv, pipe);
1758         else {
1759                 if (pch_port) {
1760                         /* if driving the PCH, we need FDI enabled */
1761                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1762                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1763                 }
1764                 /* FIXME: assert CPU port conditions for SNB+ */
1765         }
1766
1767         reg = PIPECONF(pipe);
1768         val = I915_READ(reg);
1769         if (val & PIPECONF_ENABLE)
1770                 return;
1771
1772         I915_WRITE(reg, val | PIPECONF_ENABLE);
1773         intel_wait_for_vblank(dev_priv->dev, pipe);
1774 }
1775
1776 /**
1777  * intel_disable_pipe - disable a pipe, asserting requirements
1778  * @dev_priv: i915 private structure
1779  * @pipe: pipe to disable
1780  *
1781  * Disable @pipe, making sure that various hardware specific requirements
1782  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1783  *
1784  * @pipe should be %PIPE_A or %PIPE_B.
1785  *
1786  * Will wait until the pipe has shut down before returning.
1787  */
1788 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1789                                enum pipe pipe)
1790 {
1791         int reg;
1792         u32 val;
1793
1794         /*
1795          * Make sure planes won't keep trying to pump pixels to us,
1796          * or we might hang the display.
1797          */
1798         assert_planes_disabled(dev_priv, pipe);
1799
1800         /* Don't disable pipe A or pipe A PLLs if needed */
1801         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802                 return;
1803
1804         reg = PIPECONF(pipe);
1805         val = I915_READ(reg);
1806         if ((val & PIPECONF_ENABLE) == 0)
1807                 return;
1808
1809         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1810         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1811 }
1812
1813 /*
1814  * Plane regs are double buffered, going from enabled->disabled needs a
1815  * trigger in order to latch.  The display address reg provides this.
1816  */
1817 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1818                                       enum plane plane)
1819 {
1820         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1821         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 int
1876 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1877                            struct drm_i915_gem_object *obj,
1878                            struct intel_ring_buffer *pipelined)
1879 {
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         u32 alignment;
1882         int ret;
1883
1884         switch (obj->tiling_mode) {
1885         case I915_TILING_NONE:
1886                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887                         alignment = 128 * 1024;
1888                 else if (INTEL_INFO(dev)->gen >= 4)
1889                         alignment = 4 * 1024;
1890                 else
1891                         alignment = 64 * 1024;
1892                 break;
1893         case I915_TILING_X:
1894                 /* pin() will align the object as required by fence */
1895                 alignment = 0;
1896                 break;
1897         case I915_TILING_Y:
1898                 /* FIXME: Is this true? */
1899                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1900                 return -EINVAL;
1901         default:
1902                 BUG();
1903         }
1904
1905         dev_priv->mm.interruptible = false;
1906         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1907         if (ret)
1908                 goto err_interruptible;
1909
1910         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1911          * fence, whereas 965+ only requires a fence if using
1912          * framebuffer compression.  For simplicity, we always install
1913          * a fence as the cost is not that onerous.
1914          */
1915         ret = i915_gem_object_get_fence(obj);
1916         if (ret)
1917                 goto err_unpin;
1918
1919         i915_gem_object_pin_fence(obj);
1920
1921         dev_priv->mm.interruptible = true;
1922         return 0;
1923
1924 err_unpin:
1925         i915_gem_object_unpin(obj);
1926 err_interruptible:
1927         dev_priv->mm.interruptible = true;
1928         return ret;
1929 }
1930
1931 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1932 {
1933         i915_gem_object_unpin_fence(obj);
1934         i915_gem_object_unpin(obj);
1935 }
1936
1937 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1938  * is assumed to be a power-of-two. */
1939 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1940                                                         unsigned int bpp,
1941                                                         unsigned int pitch)
1942 {
1943         int tile_rows, tiles;
1944
1945         tile_rows = *y / 8;
1946         *y %= 8;
1947         tiles = *x / (512/bpp);
1948         *x %= 512/bpp;
1949
1950         return tile_rows * pitch * 8 + tiles * 4096;
1951 }
1952
1953 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1954                              int x, int y)
1955 {
1956         struct drm_device *dev = crtc->dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1959         struct intel_framebuffer *intel_fb;
1960         struct drm_i915_gem_object *obj;
1961         int plane = intel_crtc->plane;
1962         unsigned long linear_offset;
1963         u32 dspcntr;
1964         u32 reg;
1965
1966         switch (plane) {
1967         case 0:
1968         case 1:
1969                 break;
1970         default:
1971                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1972                 return -EINVAL;
1973         }
1974
1975         intel_fb = to_intel_framebuffer(fb);
1976         obj = intel_fb->obj;
1977
1978         reg = DSPCNTR(plane);
1979         dspcntr = I915_READ(reg);
1980         /* Mask out pixel format bits in case we change it */
1981         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1982         switch (fb->bits_per_pixel) {
1983         case 8:
1984                 dspcntr |= DISPPLANE_8BPP;
1985                 break;
1986         case 16:
1987                 if (fb->depth == 15)
1988                         dspcntr |= DISPPLANE_15_16BPP;
1989                 else
1990                         dspcntr |= DISPPLANE_16BPP;
1991                 break;
1992         case 24:
1993         case 32:
1994                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1995                 break;
1996         default:
1997                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1998                 return -EINVAL;
1999         }
2000         if (INTEL_INFO(dev)->gen >= 4) {
2001                 if (obj->tiling_mode != I915_TILING_NONE)
2002                         dspcntr |= DISPPLANE_TILED;
2003                 else
2004                         dspcntr &= ~DISPPLANE_TILED;
2005         }
2006
2007         I915_WRITE(reg, dspcntr);
2008
2009         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2010
2011         if (INTEL_INFO(dev)->gen >= 4) {
2012                 intel_crtc->dspaddr_offset =
2013                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2014                                                            fb->bits_per_pixel / 8,
2015                                                            fb->pitches[0]);
2016                 linear_offset -= intel_crtc->dspaddr_offset;
2017         } else {
2018                 intel_crtc->dspaddr_offset = linear_offset;
2019         }
2020
2021         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2022                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2023         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2024         if (INTEL_INFO(dev)->gen >= 4) {
2025                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2026                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2027                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2028                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2029         } else
2030                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2031         POSTING_READ(reg);
2032
2033         return 0;
2034 }
2035
2036 static int ironlake_update_plane(struct drm_crtc *crtc,
2037                                  struct drm_framebuffer *fb, int x, int y)
2038 {
2039         struct drm_device *dev = crtc->dev;
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042         struct intel_framebuffer *intel_fb;
2043         struct drm_i915_gem_object *obj;
2044         int plane = intel_crtc->plane;
2045         unsigned long linear_offset;
2046         u32 dspcntr;
2047         u32 reg;
2048
2049         switch (plane) {
2050         case 0:
2051         case 1:
2052         case 2:
2053                 break;
2054         default:
2055                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056                 return -EINVAL;
2057         }
2058
2059         intel_fb = to_intel_framebuffer(fb);
2060         obj = intel_fb->obj;
2061
2062         reg = DSPCNTR(plane);
2063         dspcntr = I915_READ(reg);
2064         /* Mask out pixel format bits in case we change it */
2065         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066         switch (fb->bits_per_pixel) {
2067         case 8:
2068                 dspcntr |= DISPPLANE_8BPP;
2069                 break;
2070         case 16:
2071                 if (fb->depth != 16)
2072                         return -EINVAL;
2073
2074                 dspcntr |= DISPPLANE_16BPP;
2075                 break;
2076         case 24:
2077         case 32:
2078                 if (fb->depth == 24)
2079                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2080                 else if (fb->depth == 30)
2081                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2082                 else
2083                         return -EINVAL;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2087                 return -EINVAL;
2088         }
2089
2090         if (obj->tiling_mode != I915_TILING_NONE)
2091                 dspcntr |= DISPPLANE_TILED;
2092         else
2093                 dspcntr &= ~DISPPLANE_TILED;
2094
2095         /* must disable */
2096         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101         intel_crtc->dspaddr_offset =
2102                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2103                                                    fb->bits_per_pixel / 8,
2104                                                    fb->pitches[0]);
2105         linear_offset -= intel_crtc->dspaddr_offset;
2106
2107         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2108                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2109         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2110         I915_MODIFY_DISPBASE(DSPSURF(plane),
2111                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2112         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2113         I915_WRITE(DSPLINOFF(plane), linear_offset);
2114         POSTING_READ(reg);
2115
2116         return 0;
2117 }
2118
2119 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2120 static int
2121 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2122                            int x, int y, enum mode_set_atomic state)
2123 {
2124         struct drm_device *dev = crtc->dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126
2127         if (dev_priv->display.disable_fbc)
2128                 dev_priv->display.disable_fbc(dev);
2129         intel_increase_pllclock(crtc);
2130
2131         return dev_priv->display.update_plane(crtc, fb, x, y);
2132 }
2133
2134 static int
2135 intel_finish_fb(struct drm_framebuffer *old_fb)
2136 {
2137         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2138         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2139         bool was_interruptible = dev_priv->mm.interruptible;
2140         int ret;
2141
2142         wait_event(dev_priv->pending_flip_queue,
2143                    atomic_read(&dev_priv->mm.wedged) ||
2144                    atomic_read(&obj->pending_flip) == 0);
2145
2146         /* Big Hammer, we also need to ensure that any pending
2147          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2148          * current scanout is retired before unpinning the old
2149          * framebuffer.
2150          *
2151          * This should only fail upon a hung GPU, in which case we
2152          * can safely continue.
2153          */
2154         dev_priv->mm.interruptible = false;
2155         ret = i915_gem_object_finish_gpu(obj);
2156         dev_priv->mm.interruptible = was_interruptible;
2157
2158         return ret;
2159 }
2160
2161 static int
2162 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2163                     struct drm_framebuffer *fb)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         struct drm_i915_master_private *master_priv;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169         struct drm_framebuffer *old_fb;
2170         int ret;
2171
2172         /* no fb bound */
2173         if (!fb) {
2174                 DRM_ERROR("No FB bound\n");
2175                 return 0;
2176         }
2177
2178         if(intel_crtc->plane > dev_priv->num_pipe) {
2179                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2180                                 intel_crtc->plane,
2181                                 dev_priv->num_pipe);
2182                 return -EINVAL;
2183         }
2184
2185         mutex_lock(&dev->struct_mutex);
2186         ret = intel_pin_and_fence_fb_obj(dev,
2187                                          to_intel_framebuffer(fb)->obj,
2188                                          NULL);
2189         if (ret != 0) {
2190                 mutex_unlock(&dev->struct_mutex);
2191                 DRM_ERROR("pin & fence failed\n");
2192                 return ret;
2193         }
2194
2195         if (crtc->fb)
2196                 intel_finish_fb(crtc->fb);
2197
2198         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2199         if (ret) {
2200                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2201                 mutex_unlock(&dev->struct_mutex);
2202                 DRM_ERROR("failed to update base address\n");
2203                 return ret;
2204         }
2205
2206         old_fb = crtc->fb;
2207         crtc->fb = fb;
2208         crtc->x = x;
2209         crtc->y = y;
2210
2211         if (old_fb) {
2212                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2213                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2214         }
2215
2216         intel_update_fbc(dev);
2217         mutex_unlock(&dev->struct_mutex);
2218
2219         if (!dev->primary->master)
2220                 return 0;
2221
2222         master_priv = dev->primary->master->driver_priv;
2223         if (!master_priv->sarea_priv)
2224                 return 0;
2225
2226         if (intel_crtc->pipe) {
2227                 master_priv->sarea_priv->pipeB_x = x;
2228                 master_priv->sarea_priv->pipeB_y = y;
2229         } else {
2230                 master_priv->sarea_priv->pipeA_x = x;
2231                 master_priv->sarea_priv->pipeA_y = y;
2232         }
2233
2234         return 0;
2235 }
2236
2237 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         u32 dpa_ctl;
2242
2243         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2244         dpa_ctl = I915_READ(DP_A);
2245         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2246
2247         if (clock < 200000) {
2248                 u32 temp;
2249                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2250                 /* workaround for 160Mhz:
2251                    1) program 0x4600c bits 15:0 = 0x8124
2252                    2) program 0x46010 bit 0 = 1
2253                    3) program 0x46034 bit 24 = 1
2254                    4) program 0x64000 bit 14 = 1
2255                    */
2256                 temp = I915_READ(0x4600c);
2257                 temp &= 0xffff0000;
2258                 I915_WRITE(0x4600c, temp | 0x8124);
2259
2260                 temp = I915_READ(0x46010);
2261                 I915_WRITE(0x46010, temp | 1);
2262
2263                 temp = I915_READ(0x46034);
2264                 I915_WRITE(0x46034, temp | (1 << 24));
2265         } else {
2266                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2267         }
2268         I915_WRITE(DP_A, dpa_ctl);
2269
2270         POSTING_READ(DP_A);
2271         udelay(500);
2272 }
2273
2274 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         int pipe = intel_crtc->pipe;
2280         u32 reg, temp;
2281
2282         /* enable normal train */
2283         reg = FDI_TX_CTL(pipe);
2284         temp = I915_READ(reg);
2285         if (IS_IVYBRIDGE(dev)) {
2286                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2287                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2288         } else {
2289                 temp &= ~FDI_LINK_TRAIN_NONE;
2290                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2291         }
2292         I915_WRITE(reg, temp);
2293
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (HAS_PCH_CPT(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2298                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE;
2302         }
2303         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2304
2305         /* wait one idle pattern time */
2306         POSTING_READ(reg);
2307         udelay(1000);
2308
2309         /* IVB wants error correction enabled */
2310         if (IS_IVYBRIDGE(dev))
2311                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2312                            FDI_FE_ERRC_ENABLE);
2313 }
2314
2315 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         u32 flags = I915_READ(SOUTH_CHICKEN1);
2319
2320         flags |= FDI_PHASE_SYNC_OVR(pipe);
2321         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2322         flags |= FDI_PHASE_SYNC_EN(pipe);
2323         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2324         POSTING_READ(SOUTH_CHICKEN1);
2325 }
2326
2327 /* The FDI link training functions for ILK/Ibexpeak. */
2328 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2329 {
2330         struct drm_device *dev = crtc->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         int pipe = intel_crtc->pipe;
2334         int plane = intel_crtc->plane;
2335         u32 reg, temp, tries;
2336
2337         /* FDI needs bits from pipe & plane first */
2338         assert_pipe_enabled(dev_priv, pipe);
2339         assert_plane_enabled(dev_priv, plane);
2340
2341         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2342            for train result */
2343         reg = FDI_RX_IMR(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_RX_SYMBOL_LOCK;
2346         temp &= ~FDI_RX_BIT_LOCK;
2347         I915_WRITE(reg, temp);
2348         I915_READ(reg);
2349         udelay(150);
2350
2351         /* enable CPU FDI TX and PCH FDI RX */
2352         reg = FDI_TX_CTL(pipe);
2353         temp = I915_READ(reg);
2354         temp &= ~(7 << 19);
2355         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2356         temp &= ~FDI_LINK_TRAIN_NONE;
2357         temp |= FDI_LINK_TRAIN_PATTERN_1;
2358         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         temp &= ~FDI_LINK_TRAIN_NONE;
2363         temp |= FDI_LINK_TRAIN_PATTERN_1;
2364         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2365
2366         POSTING_READ(reg);
2367         udelay(150);
2368
2369         /* Ironlake workaround, enable clock pointer after FDI enable*/
2370         if (HAS_PCH_IBX(dev)) {
2371                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2372                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2373                            FDI_RX_PHASE_SYNC_POINTER_EN);
2374         }
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if ((temp & FDI_RX_BIT_LOCK)) {
2382                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2383                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 1 fail!\n");
2389
2390         /* Train 2 */
2391         reg = FDI_TX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         temp &= ~FDI_LINK_TRAIN_NONE;
2394         temp |= FDI_LINK_TRAIN_PATTERN_2;
2395         I915_WRITE(reg, temp);
2396
2397         reg = FDI_RX_CTL(pipe);
2398         temp = I915_READ(reg);
2399         temp &= ~FDI_LINK_TRAIN_NONE;
2400         temp |= FDI_LINK_TRAIN_PATTERN_2;
2401         I915_WRITE(reg, temp);
2402
2403         POSTING_READ(reg);
2404         udelay(150);
2405
2406         reg = FDI_RX_IIR(pipe);
2407         for (tries = 0; tries < 5; tries++) {
2408                 temp = I915_READ(reg);
2409                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411                 if (temp & FDI_RX_SYMBOL_LOCK) {
2412                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2414                         break;
2415                 }
2416         }
2417         if (tries == 5)
2418                 DRM_ERROR("FDI train 2 fail!\n");
2419
2420         DRM_DEBUG_KMS("FDI train done\n");
2421
2422 }
2423
2424 static const int snb_b_fdi_train_param[] = {
2425         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2426         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2427         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2428         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2429 };
2430
2431 /* The FDI link training functions for SNB/Cougarpoint. */
2432 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2433 {
2434         struct drm_device *dev = crtc->dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437         int pipe = intel_crtc->pipe;
2438         u32 reg, temp, i, retry;
2439
2440         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2441            for train result */
2442         reg = FDI_RX_IMR(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_RX_SYMBOL_LOCK;
2445         temp &= ~FDI_RX_BIT_LOCK;
2446         I915_WRITE(reg, temp);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         /* enable CPU FDI TX and PCH FDI RX */
2452         reg = FDI_TX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         temp &= ~(7 << 19);
2455         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2456         temp &= ~FDI_LINK_TRAIN_NONE;
2457         temp |= FDI_LINK_TRAIN_PATTERN_1;
2458         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2459         /* SNB-B */
2460         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2461         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2462
2463         reg = FDI_RX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         if (HAS_PCH_CPT(dev)) {
2466                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2467                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2468         } else {
2469                 temp &= ~FDI_LINK_TRAIN_NONE;
2470                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2471         }
2472         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2473
2474         POSTING_READ(reg);
2475         udelay(150);
2476
2477         if (HAS_PCH_CPT(dev))
2478                 cpt_phase_pointer_enable(dev, pipe);
2479
2480         for (i = 0; i < 4; i++) {
2481                 reg = FDI_TX_CTL(pipe);
2482                 temp = I915_READ(reg);
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 temp |= snb_b_fdi_train_param[i];
2485                 I915_WRITE(reg, temp);
2486
2487                 POSTING_READ(reg);
2488                 udelay(500);
2489
2490                 for (retry = 0; retry < 5; retry++) {
2491                         reg = FDI_RX_IIR(pipe);
2492                         temp = I915_READ(reg);
2493                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2494                         if (temp & FDI_RX_BIT_LOCK) {
2495                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2497                                 break;
2498                         }
2499                         udelay(50);
2500                 }
2501                 if (retry < 5)
2502                         break;
2503         }
2504         if (i == 4)
2505                 DRM_ERROR("FDI train 1 fail!\n");
2506
2507         /* Train 2 */
2508         reg = FDI_TX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_2;
2512         if (IS_GEN6(dev)) {
2513                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514                 /* SNB-B */
2515                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2516         }
2517         I915_WRITE(reg, temp);
2518
2519         reg = FDI_RX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         if (HAS_PCH_CPT(dev)) {
2522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2524         } else {
2525                 temp &= ~FDI_LINK_TRAIN_NONE;
2526                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         }
2528         I915_WRITE(reg, temp);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         for (i = 0; i < 4; i++) {
2534                 reg = FDI_TX_CTL(pipe);
2535                 temp = I915_READ(reg);
2536                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537                 temp |= snb_b_fdi_train_param[i];
2538                 I915_WRITE(reg, temp);
2539
2540                 POSTING_READ(reg);
2541                 udelay(500);
2542
2543                 for (retry = 0; retry < 5; retry++) {
2544                         reg = FDI_RX_IIR(pipe);
2545                         temp = I915_READ(reg);
2546                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547                         if (temp & FDI_RX_SYMBOL_LOCK) {
2548                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2550                                 break;
2551                         }
2552                         udelay(50);
2553                 }
2554                 if (retry < 5)
2555                         break;
2556         }
2557         if (i == 4)
2558                 DRM_ERROR("FDI train 2 fail!\n");
2559
2560         DRM_DEBUG_KMS("FDI train done.\n");
2561 }
2562
2563 /* Manual link training for Ivy Bridge A0 parts */
2564 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2565 {
2566         struct drm_device *dev = crtc->dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2569         int pipe = intel_crtc->pipe;
2570         u32 reg, temp, i;
2571
2572         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2573            for train result */
2574         reg = FDI_RX_IMR(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_RX_SYMBOL_LOCK;
2577         temp &= ~FDI_RX_BIT_LOCK;
2578         I915_WRITE(reg, temp);
2579
2580         POSTING_READ(reg);
2581         udelay(150);
2582
2583         /* enable CPU FDI TX and PCH FDI RX */
2584         reg = FDI_TX_CTL(pipe);
2585         temp = I915_READ(reg);
2586         temp &= ~(7 << 19);
2587         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2588         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2590         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2591         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2592         temp |= FDI_COMPOSITE_SYNC;
2593         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_LINK_TRAIN_AUTO;
2598         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600         temp |= FDI_COMPOSITE_SYNC;
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         if (HAS_PCH_CPT(dev))
2607                 cpt_phase_pointer_enable(dev, pipe);
2608
2609         for (i = 0; i < 4; i++) {
2610                 reg = FDI_TX_CTL(pipe);
2611                 temp = I915_READ(reg);
2612                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613                 temp |= snb_b_fdi_train_param[i];
2614                 I915_WRITE(reg, temp);
2615
2616                 POSTING_READ(reg);
2617                 udelay(500);
2618
2619                 reg = FDI_RX_IIR(pipe);
2620                 temp = I915_READ(reg);
2621                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2622
2623                 if (temp & FDI_RX_BIT_LOCK ||
2624                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2625                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2626                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2627                         break;
2628                 }
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2638         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2646         I915_WRITE(reg, temp);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         for (i = 0; i < 4; i++) {
2652                 reg = FDI_TX_CTL(pipe);
2653                 temp = I915_READ(reg);
2654                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655                 temp |= snb_b_fdi_train_param[i];
2656                 I915_WRITE(reg, temp);
2657
2658                 POSTING_READ(reg);
2659                 udelay(500);
2660
2661                 reg = FDI_RX_IIR(pipe);
2662                 temp = I915_READ(reg);
2663                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2664
2665                 if (temp & FDI_RX_SYMBOL_LOCK) {
2666                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2667                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2668                         break;
2669                 }
2670         }
2671         if (i == 4)
2672                 DRM_ERROR("FDI train 2 fail!\n");
2673
2674         DRM_DEBUG_KMS("FDI train done.\n");
2675 }
2676
2677 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2678 {
2679         struct drm_device *dev = intel_crtc->base.dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         int pipe = intel_crtc->pipe;
2682         u32 reg, temp;
2683
2684         /* Write the TU size bits so error detection works */
2685         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2686                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2687
2688         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2689         reg = FDI_RX_CTL(pipe);
2690         temp = I915_READ(reg);
2691         temp &= ~((0x7 << 19) | (0x7 << 16));
2692         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2693         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2694         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2695
2696         POSTING_READ(reg);
2697         udelay(200);
2698
2699         /* Switch from Rawclk to PCDclk */
2700         temp = I915_READ(reg);
2701         I915_WRITE(reg, temp | FDI_PCDCLK);
2702
2703         POSTING_READ(reg);
2704         udelay(200);
2705
2706         /* On Haswell, the PLL configuration for ports and pipes is handled
2707          * separately, as part of DDI setup */
2708         if (!IS_HASWELL(dev)) {
2709                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2710                 reg = FDI_TX_CTL(pipe);
2711                 temp = I915_READ(reg);
2712                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2713                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2714
2715                         POSTING_READ(reg);
2716                         udelay(100);
2717                 }
2718         }
2719 }
2720
2721 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2722 {
2723         struct drm_device *dev = intel_crtc->base.dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* Switch from PCDclk to Rawclk */
2729         reg = FDI_RX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2732
2733         /* Disable CPU FDI TX PLL */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2737
2738         POSTING_READ(reg);
2739         udelay(100);
2740
2741         reg = FDI_RX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2744
2745         /* Wait for the clocks to turn off. */
2746         POSTING_READ(reg);
2747         udelay(100);
2748 }
2749
2750 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2751 {
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         u32 flags = I915_READ(SOUTH_CHICKEN1);
2754
2755         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2756         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2757         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2758         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2759         POSTING_READ(SOUTH_CHICKEN1);
2760 }
2761 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2762 {
2763         struct drm_device *dev = crtc->dev;
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2766         int pipe = intel_crtc->pipe;
2767         u32 reg, temp;
2768
2769         /* disable CPU FDI tx and PCH FDI rx */
2770         reg = FDI_TX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2773         POSTING_READ(reg);
2774
2775         reg = FDI_RX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         temp &= ~(0x7 << 16);
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(100);
2783
2784         /* Ironlake workaround, disable clock pointer after downing FDI */
2785         if (HAS_PCH_IBX(dev)) {
2786                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2787                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2788                            I915_READ(FDI_RX_CHICKEN(pipe) &
2789                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2790         } else if (HAS_PCH_CPT(dev)) {
2791                 cpt_phase_pointer_disable(dev, pipe);
2792         }
2793
2794         /* still set train pattern 1 */
2795         reg = FDI_TX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         temp &= ~FDI_LINK_TRAIN_NONE;
2798         temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         I915_WRITE(reg, temp);
2800
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         if (HAS_PCH_CPT(dev)) {
2804                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2805                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2806         } else {
2807                 temp &= ~FDI_LINK_TRAIN_NONE;
2808                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809         }
2810         /* BPC in FDI rx is consistent with that in PIPECONF */
2811         temp &= ~(0x07 << 16);
2812         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2813         I915_WRITE(reg, temp);
2814
2815         POSTING_READ(reg);
2816         udelay(100);
2817 }
2818
2819 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2820 {
2821         struct drm_device *dev = crtc->dev;
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         unsigned long flags;
2824         bool pending;
2825
2826         if (atomic_read(&dev_priv->mm.wedged))
2827                 return false;
2828
2829         spin_lock_irqsave(&dev->event_lock, flags);
2830         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2831         spin_unlock_irqrestore(&dev->event_lock, flags);
2832
2833         return pending;
2834 }
2835
2836 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840
2841         if (crtc->fb == NULL)
2842                 return;
2843
2844         wait_event(dev_priv->pending_flip_queue,
2845                    !intel_crtc_has_pending_flip(crtc));
2846
2847         mutex_lock(&dev->struct_mutex);
2848         intel_finish_fb(crtc->fb);
2849         mutex_unlock(&dev->struct_mutex);
2850 }
2851
2852 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct intel_encoder *intel_encoder;
2856
2857         /*
2858          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2859          * must be driven by its own crtc; no sharing is possible.
2860          */
2861         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2862                 switch (intel_encoder->type) {
2863                 case INTEL_OUTPUT_EDP:
2864                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2865                                 return false;
2866                         continue;
2867                 }
2868         }
2869
2870         return true;
2871 }
2872
2873 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2874 {
2875         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2876 }
2877
2878 /* Program iCLKIP clock to the desired frequency */
2879 static void lpt_program_iclkip(struct drm_crtc *crtc)
2880 {
2881         struct drm_device *dev = crtc->dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2884         u32 temp;
2885
2886         /* It is necessary to ungate the pixclk gate prior to programming
2887          * the divisors, and gate it back when it is done.
2888          */
2889         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2890
2891         /* Disable SSCCTL */
2892         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2893                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2894                                         SBI_SSCCTL_DISABLE);
2895
2896         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2897         if (crtc->mode.clock == 20000) {
2898                 auxdiv = 1;
2899                 divsel = 0x41;
2900                 phaseinc = 0x20;
2901         } else {
2902                 /* The iCLK virtual clock root frequency is in MHz,
2903                  * but the crtc->mode.clock in in KHz. To get the divisors,
2904                  * it is necessary to divide one by another, so we
2905                  * convert the virtual clock precision to KHz here for higher
2906                  * precision.
2907                  */
2908                 u32 iclk_virtual_root_freq = 172800 * 1000;
2909                 u32 iclk_pi_range = 64;
2910                 u32 desired_divisor, msb_divisor_value, pi_value;
2911
2912                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2913                 msb_divisor_value = desired_divisor / iclk_pi_range;
2914                 pi_value = desired_divisor % iclk_pi_range;
2915
2916                 auxdiv = 0;
2917                 divsel = msb_divisor_value - 2;
2918                 phaseinc = pi_value;
2919         }
2920
2921         /* This should not happen with any sane values */
2922         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2923                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2924         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2925                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2926
2927         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2928                         crtc->mode.clock,
2929                         auxdiv,
2930                         divsel,
2931                         phasedir,
2932                         phaseinc);
2933
2934         /* Program SSCDIVINTPHASE6 */
2935         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2936         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2937         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2938         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2939         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2940         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2941         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2942
2943         intel_sbi_write(dev_priv,
2944                         SBI_SSCDIVINTPHASE6,
2945                         temp);
2946
2947         /* Program SSCAUXDIV */
2948         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2949         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2950         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2951         intel_sbi_write(dev_priv,
2952                         SBI_SSCAUXDIV6,
2953                         temp);
2954
2955
2956         /* Enable modulator and associated divider */
2957         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2958         temp &= ~SBI_SSCCTL_DISABLE;
2959         intel_sbi_write(dev_priv,
2960                         SBI_SSCCTL6,
2961                         temp);
2962
2963         /* Wait for initialization time */
2964         udelay(24);
2965
2966         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2967 }
2968
2969 /*
2970  * Enable PCH resources required for PCH ports:
2971  *   - PCH PLLs
2972  *   - FDI training & RX/TX
2973  *   - update transcoder timings
2974  *   - DP transcoding bits
2975  *   - transcoder
2976  */
2977 static void ironlake_pch_enable(struct drm_crtc *crtc)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2982         int pipe = intel_crtc->pipe;
2983         u32 reg, temp;
2984
2985         assert_transcoder_disabled(dev_priv, pipe);
2986
2987         /* For PCH output, training FDI link */
2988         dev_priv->display.fdi_link_train(crtc);
2989
2990         intel_enable_pch_pll(intel_crtc);
2991
2992         if (HAS_PCH_LPT(dev)) {
2993                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2994                 lpt_program_iclkip(crtc);
2995         } else if (HAS_PCH_CPT(dev)) {
2996                 u32 sel;
2997
2998                 temp = I915_READ(PCH_DPLL_SEL);
2999                 switch (pipe) {
3000                 default:
3001                 case 0:
3002                         temp |= TRANSA_DPLL_ENABLE;
3003                         sel = TRANSA_DPLLB_SEL;
3004                         break;
3005                 case 1:
3006                         temp |= TRANSB_DPLL_ENABLE;
3007                         sel = TRANSB_DPLLB_SEL;
3008                         break;
3009                 case 2:
3010                         temp |= TRANSC_DPLL_ENABLE;
3011                         sel = TRANSC_DPLLB_SEL;
3012                         break;
3013                 }
3014                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3015                         temp |= sel;
3016                 else
3017                         temp &= ~sel;
3018                 I915_WRITE(PCH_DPLL_SEL, temp);
3019         }
3020
3021         /* set transcoder timing, panel must allow it */
3022         assert_panel_unlocked(dev_priv, pipe);
3023         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3024         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3025         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3026
3027         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3028         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3029         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3030         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3031
3032         if (!IS_HASWELL(dev))
3033                 intel_fdi_normal_train(crtc);
3034
3035         /* For PCH DP, enable TRANS_DP_CTL */
3036         if (HAS_PCH_CPT(dev) &&
3037             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3038              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3039                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3040                 reg = TRANS_DP_CTL(pipe);
3041                 temp = I915_READ(reg);
3042                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3043                           TRANS_DP_SYNC_MASK |
3044                           TRANS_DP_BPC_MASK);
3045                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3046                          TRANS_DP_ENH_FRAMING);
3047                 temp |= bpc << 9; /* same format but at 11:9 */
3048
3049                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3050                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3051                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3052                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3053
3054                 switch (intel_trans_dp_port_sel(crtc)) {
3055                 case PCH_DP_B:
3056                         temp |= TRANS_DP_PORT_SEL_B;
3057                         break;
3058                 case PCH_DP_C:
3059                         temp |= TRANS_DP_PORT_SEL_C;
3060                         break;
3061                 case PCH_DP_D:
3062                         temp |= TRANS_DP_PORT_SEL_D;
3063                         break;
3064                 default:
3065                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3066                         temp |= TRANS_DP_PORT_SEL_B;
3067                         break;
3068                 }
3069
3070                 I915_WRITE(reg, temp);
3071         }
3072
3073         intel_enable_transcoder(dev_priv, pipe);
3074 }
3075
3076 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3077 {
3078         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3079
3080         if (pll == NULL)
3081                 return;
3082
3083         if (pll->refcount == 0) {
3084                 WARN(1, "bad PCH PLL refcount\n");
3085                 return;
3086         }
3087
3088         --pll->refcount;
3089         intel_crtc->pch_pll = NULL;
3090 }
3091
3092 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3093 {
3094         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3095         struct intel_pch_pll *pll;
3096         int i;
3097
3098         pll = intel_crtc->pch_pll;
3099         if (pll) {
3100                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3101                               intel_crtc->base.base.id, pll->pll_reg);
3102                 goto prepare;
3103         }
3104
3105         if (HAS_PCH_IBX(dev_priv->dev)) {
3106                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3107                 i = intel_crtc->pipe;
3108                 pll = &dev_priv->pch_plls[i];
3109
3110                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3111                               intel_crtc->base.base.id, pll->pll_reg);
3112
3113                 goto found;
3114         }
3115
3116         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3117                 pll = &dev_priv->pch_plls[i];
3118
3119                 /* Only want to check enabled timings first */
3120                 if (pll->refcount == 0)
3121                         continue;
3122
3123                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3124                     fp == I915_READ(pll->fp0_reg)) {
3125                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3126                                       intel_crtc->base.base.id,
3127                                       pll->pll_reg, pll->refcount, pll->active);
3128
3129                         goto found;
3130                 }
3131         }
3132
3133         /* Ok no matching timings, maybe there's a free one? */
3134         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3135                 pll = &dev_priv->pch_plls[i];
3136                 if (pll->refcount == 0) {
3137                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3138                                       intel_crtc->base.base.id, pll->pll_reg);
3139                         goto found;
3140                 }
3141         }
3142
3143         return NULL;
3144
3145 found:
3146         intel_crtc->pch_pll = pll;
3147         pll->refcount++;
3148         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3149 prepare: /* separate function? */
3150         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3151
3152         /* Wait for the clocks to stabilize before rewriting the regs */
3153         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3154         POSTING_READ(pll->pll_reg);
3155         udelay(150);
3156
3157         I915_WRITE(pll->fp0_reg, fp);
3158         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3159         pll->on = false;
3160         return pll;
3161 }
3162
3163 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3164 {
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3167         u32 temp;
3168
3169         temp = I915_READ(dslreg);
3170         udelay(500);
3171         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3172                 /* Without this, mode sets may fail silently on FDI */
3173                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3174                 udelay(250);
3175                 I915_WRITE(tc2reg, 0);
3176                 if (wait_for(I915_READ(dslreg) != temp, 5))
3177                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3178         }
3179 }
3180
3181 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3182 {
3183         struct drm_device *dev = crtc->dev;
3184         struct drm_i915_private *dev_priv = dev->dev_private;
3185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3186         struct intel_encoder *encoder;
3187         int pipe = intel_crtc->pipe;
3188         int plane = intel_crtc->plane;
3189         u32 temp;
3190         bool is_pch_port;
3191
3192         WARN_ON(!crtc->enabled);
3193
3194         if (intel_crtc->active)
3195                 return;
3196
3197         intel_crtc->active = true;
3198         intel_update_watermarks(dev);
3199
3200         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3201                 temp = I915_READ(PCH_LVDS);
3202                 if ((temp & LVDS_PORT_EN) == 0)
3203                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3204         }
3205
3206         is_pch_port = ironlake_crtc_driving_pch(crtc);
3207
3208         if (is_pch_port) {
3209                 ironlake_fdi_pll_enable(intel_crtc);
3210         } else {
3211                 assert_fdi_tx_disabled(dev_priv, pipe);
3212                 assert_fdi_rx_disabled(dev_priv, pipe);
3213         }
3214
3215         for_each_encoder_on_crtc(dev, crtc, encoder)
3216                 if (encoder->pre_enable)
3217                         encoder->pre_enable(encoder);
3218
3219         /* Enable panel fitting for LVDS */
3220         if (dev_priv->pch_pf_size &&
3221             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3222                 /* Force use of hard-coded filter coefficients
3223                  * as some pre-programmed values are broken,
3224                  * e.g. x201.
3225                  */
3226                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3227                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3228                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3229         }
3230
3231         /*
3232          * On ILK+ LUT must be loaded before the pipe is running but with
3233          * clocks enabled
3234          */
3235         intel_crtc_load_lut(crtc);
3236
3237         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3238         intel_enable_plane(dev_priv, plane, pipe);
3239
3240         if (is_pch_port)
3241                 ironlake_pch_enable(crtc);
3242
3243         mutex_lock(&dev->struct_mutex);
3244         intel_update_fbc(dev);
3245         mutex_unlock(&dev->struct_mutex);
3246
3247         intel_crtc_update_cursor(crtc, true);
3248
3249         for_each_encoder_on_crtc(dev, crtc, encoder)
3250                 encoder->enable(encoder);
3251
3252         if (HAS_PCH_CPT(dev))
3253                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3254
3255         /*
3256          * There seems to be a race in PCH platform hw (at least on some
3257          * outputs) where an enabled pipe still completes any pageflip right
3258          * away (as if the pipe is off) instead of waiting for vblank. As soon
3259          * as the first vblank happend, everything works as expected. Hence just
3260          * wait for one vblank before returning to avoid strange things
3261          * happening.
3262          */
3263         intel_wait_for_vblank(dev, intel_crtc->pipe);
3264 }
3265
3266 static void haswell_crtc_enable(struct drm_crtc *crtc)
3267 {
3268         struct drm_device *dev = crtc->dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271         struct intel_encoder *encoder;
3272         int pipe = intel_crtc->pipe;
3273         int plane = intel_crtc->plane;
3274         bool is_pch_port;
3275
3276         WARN_ON(!crtc->enabled);
3277
3278         if (intel_crtc->active)
3279                 return;
3280
3281         intel_crtc->active = true;
3282         intel_update_watermarks(dev);
3283
3284         is_pch_port = haswell_crtc_driving_pch(crtc);
3285
3286         if (is_pch_port)
3287                 ironlake_fdi_pll_enable(intel_crtc);
3288
3289         for_each_encoder_on_crtc(dev, crtc, encoder)
3290                 if (encoder->pre_enable)
3291                         encoder->pre_enable(encoder);
3292
3293         intel_ddi_enable_pipe_clock(intel_crtc);
3294
3295         /* Enable panel fitting for eDP */
3296         if (dev_priv->pch_pf_size && HAS_eDP) {
3297                 /* Force use of hard-coded filter coefficients
3298                  * as some pre-programmed values are broken,
3299                  * e.g. x201.
3300                  */
3301                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3302                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3303                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3304         }
3305
3306         /*
3307          * On ILK+ LUT must be loaded before the pipe is running but with
3308          * clocks enabled
3309          */
3310         intel_crtc_load_lut(crtc);
3311
3312         intel_ddi_set_pipe_settings(crtc);
3313         intel_ddi_enable_pipe_func(crtc);
3314
3315         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3316         intel_enable_plane(dev_priv, plane, pipe);
3317
3318         if (is_pch_port)
3319                 ironlake_pch_enable(crtc);
3320
3321         mutex_lock(&dev->struct_mutex);
3322         intel_update_fbc(dev);
3323         mutex_unlock(&dev->struct_mutex);
3324
3325         intel_crtc_update_cursor(crtc, true);
3326
3327         for_each_encoder_on_crtc(dev, crtc, encoder)
3328                 encoder->enable(encoder);
3329
3330         /*
3331          * There seems to be a race in PCH platform hw (at least on some
3332          * outputs) where an enabled pipe still completes any pageflip right
3333          * away (as if the pipe is off) instead of waiting for vblank. As soon
3334          * as the first vblank happend, everything works as expected. Hence just
3335          * wait for one vblank before returning to avoid strange things
3336          * happening.
3337          */
3338         intel_wait_for_vblank(dev, intel_crtc->pipe);
3339 }
3340
3341 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         struct intel_encoder *encoder;
3347         int pipe = intel_crtc->pipe;
3348         int plane = intel_crtc->plane;
3349         u32 reg, temp;
3350
3351
3352         if (!intel_crtc->active)
3353                 return;
3354
3355         for_each_encoder_on_crtc(dev, crtc, encoder)
3356                 encoder->disable(encoder);
3357
3358         intel_crtc_wait_for_pending_flips(crtc);
3359         drm_vblank_off(dev, pipe);
3360         intel_crtc_update_cursor(crtc, false);
3361
3362         intel_disable_plane(dev_priv, plane, pipe);
3363
3364         if (dev_priv->cfb_plane == plane)
3365                 intel_disable_fbc(dev);
3366
3367         intel_disable_pipe(dev_priv, pipe);
3368
3369         /* Disable PF */
3370         I915_WRITE(PF_CTL(pipe), 0);
3371         I915_WRITE(PF_WIN_SZ(pipe), 0);
3372
3373         for_each_encoder_on_crtc(dev, crtc, encoder)
3374                 if (encoder->post_disable)
3375                         encoder->post_disable(encoder);
3376
3377         ironlake_fdi_disable(crtc);
3378
3379         intel_disable_transcoder(dev_priv, pipe);
3380
3381         if (HAS_PCH_CPT(dev)) {
3382                 /* disable TRANS_DP_CTL */
3383                 reg = TRANS_DP_CTL(pipe);
3384                 temp = I915_READ(reg);
3385                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3386                 temp |= TRANS_DP_PORT_SEL_NONE;
3387                 I915_WRITE(reg, temp);
3388
3389                 /* disable DPLL_SEL */
3390                 temp = I915_READ(PCH_DPLL_SEL);
3391                 switch (pipe) {
3392                 case 0:
3393                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3394                         break;
3395                 case 1:
3396                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3397                         break;
3398                 case 2:
3399                         /* C shares PLL A or B */
3400                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3401                         break;
3402                 default:
3403                         BUG(); /* wtf */
3404                 }
3405                 I915_WRITE(PCH_DPLL_SEL, temp);
3406         }
3407
3408         /* disable PCH DPLL */
3409         intel_disable_pch_pll(intel_crtc);
3410
3411         ironlake_fdi_pll_disable(intel_crtc);
3412
3413         intel_crtc->active = false;
3414         intel_update_watermarks(dev);
3415
3416         mutex_lock(&dev->struct_mutex);
3417         intel_update_fbc(dev);
3418         mutex_unlock(&dev->struct_mutex);
3419 }
3420
3421 static void haswell_crtc_disable(struct drm_crtc *crtc)
3422 {
3423         struct drm_device *dev = crtc->dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426         struct intel_encoder *encoder;
3427         int pipe = intel_crtc->pipe;
3428         int plane = intel_crtc->plane;
3429         bool is_pch_port;
3430
3431         if (!intel_crtc->active)
3432                 return;
3433
3434         is_pch_port = haswell_crtc_driving_pch(crtc);
3435
3436         for_each_encoder_on_crtc(dev, crtc, encoder)
3437                 encoder->disable(encoder);
3438
3439         intel_crtc_wait_for_pending_flips(crtc);
3440         drm_vblank_off(dev, pipe);
3441         intel_crtc_update_cursor(crtc, false);
3442
3443         intel_disable_plane(dev_priv, plane, pipe);
3444
3445         if (dev_priv->cfb_plane == plane)
3446                 intel_disable_fbc(dev);
3447
3448         intel_disable_pipe(dev_priv, pipe);
3449
3450         intel_ddi_disable_pipe_func(dev_priv, pipe);
3451
3452         /* Disable PF */
3453         I915_WRITE(PF_CTL(pipe), 0);
3454         I915_WRITE(PF_WIN_SZ(pipe), 0);
3455
3456         intel_ddi_disable_pipe_clock(intel_crtc);
3457
3458         for_each_encoder_on_crtc(dev, crtc, encoder)
3459                 if (encoder->post_disable)
3460                         encoder->post_disable(encoder);
3461
3462         if (is_pch_port) {
3463                 ironlake_fdi_disable(crtc);
3464                 intel_disable_transcoder(dev_priv, pipe);
3465                 intel_disable_pch_pll(intel_crtc);
3466                 ironlake_fdi_pll_disable(intel_crtc);
3467         }
3468
3469         intel_crtc->active = false;
3470         intel_update_watermarks(dev);
3471
3472         mutex_lock(&dev->struct_mutex);
3473         intel_update_fbc(dev);
3474         mutex_unlock(&dev->struct_mutex);
3475 }
3476
3477 static void ironlake_crtc_off(struct drm_crtc *crtc)
3478 {
3479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480         intel_put_pch_pll(intel_crtc);
3481 }
3482
3483 static void haswell_crtc_off(struct drm_crtc *crtc)
3484 {
3485         intel_ddi_put_crtc_pll(crtc);
3486 }
3487
3488 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3489 {
3490         if (!enable && intel_crtc->overlay) {
3491                 struct drm_device *dev = intel_crtc->base.dev;
3492                 struct drm_i915_private *dev_priv = dev->dev_private;
3493
3494                 mutex_lock(&dev->struct_mutex);
3495                 dev_priv->mm.interruptible = false;
3496                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3497                 dev_priv->mm.interruptible = true;
3498                 mutex_unlock(&dev->struct_mutex);
3499         }
3500
3501         /* Let userspace switch the overlay on again. In most cases userspace
3502          * has to recompute where to put it anyway.
3503          */
3504 }
3505
3506 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3507 {
3508         struct drm_device *dev = crtc->dev;
3509         struct drm_i915_private *dev_priv = dev->dev_private;
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         struct intel_encoder *encoder;
3512         int pipe = intel_crtc->pipe;
3513         int plane = intel_crtc->plane;
3514
3515         WARN_ON(!crtc->enabled);
3516
3517         if (intel_crtc->active)
3518                 return;
3519
3520         intel_crtc->active = true;
3521         intel_update_watermarks(dev);
3522
3523         intel_enable_pll(dev_priv, pipe);
3524         intel_enable_pipe(dev_priv, pipe, false);
3525         intel_enable_plane(dev_priv, plane, pipe);
3526
3527         intel_crtc_load_lut(crtc);
3528         intel_update_fbc(dev);
3529
3530         /* Give the overlay scaler a chance to enable if it's on this pipe */
3531         intel_crtc_dpms_overlay(intel_crtc, true);
3532         intel_crtc_update_cursor(crtc, true);
3533
3534         for_each_encoder_on_crtc(dev, crtc, encoder)
3535                 encoder->enable(encoder);
3536 }
3537
3538 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543         struct intel_encoder *encoder;
3544         int pipe = intel_crtc->pipe;
3545         int plane = intel_crtc->plane;
3546
3547
3548         if (!intel_crtc->active)
3549                 return;
3550
3551         for_each_encoder_on_crtc(dev, crtc, encoder)
3552                 encoder->disable(encoder);
3553
3554         /* Give the overlay scaler a chance to disable if it's on this pipe */
3555         intel_crtc_wait_for_pending_flips(crtc);
3556         drm_vblank_off(dev, pipe);
3557         intel_crtc_dpms_overlay(intel_crtc, false);
3558         intel_crtc_update_cursor(crtc, false);
3559
3560         if (dev_priv->cfb_plane == plane)
3561                 intel_disable_fbc(dev);
3562
3563         intel_disable_plane(dev_priv, plane, pipe);
3564         intel_disable_pipe(dev_priv, pipe);
3565         intel_disable_pll(dev_priv, pipe);
3566
3567         intel_crtc->active = false;
3568         intel_update_fbc(dev);
3569         intel_update_watermarks(dev);
3570 }
3571
3572 static void i9xx_crtc_off(struct drm_crtc *crtc)
3573 {
3574 }
3575
3576 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3577                                     bool enabled)
3578 {
3579         struct drm_device *dev = crtc->dev;
3580         struct drm_i915_master_private *master_priv;
3581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3582         int pipe = intel_crtc->pipe;
3583
3584         if (!dev->primary->master)
3585                 return;
3586
3587         master_priv = dev->primary->master->driver_priv;
3588         if (!master_priv->sarea_priv)
3589                 return;
3590
3591         switch (pipe) {
3592         case 0:
3593                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3594                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3595                 break;
3596         case 1:
3597                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3598                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3599                 break;
3600         default:
3601                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3602                 break;
3603         }
3604 }
3605
3606 /**
3607  * Sets the power management mode of the pipe and plane.
3608  */
3609 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3610 {
3611         struct drm_device *dev = crtc->dev;
3612         struct drm_i915_private *dev_priv = dev->dev_private;
3613         struct intel_encoder *intel_encoder;
3614         bool enable = false;
3615
3616         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3617                 enable |= intel_encoder->connectors_active;
3618
3619         if (enable)
3620                 dev_priv->display.crtc_enable(crtc);
3621         else
3622                 dev_priv->display.crtc_disable(crtc);
3623
3624         intel_crtc_update_sarea(crtc, enable);
3625 }
3626
3627 static void intel_crtc_noop(struct drm_crtc *crtc)
3628 {
3629 }
3630
3631 static void intel_crtc_disable(struct drm_crtc *crtc)
3632 {
3633         struct drm_device *dev = crtc->dev;
3634         struct drm_connector *connector;
3635         struct drm_i915_private *dev_priv = dev->dev_private;
3636
3637         /* crtc should still be enabled when we disable it. */
3638         WARN_ON(!crtc->enabled);
3639
3640         dev_priv->display.crtc_disable(crtc);
3641         intel_crtc_update_sarea(crtc, false);
3642         dev_priv->display.off(crtc);
3643
3644         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3645         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3646
3647         if (crtc->fb) {
3648                 mutex_lock(&dev->struct_mutex);
3649                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3650                 mutex_unlock(&dev->struct_mutex);
3651                 crtc->fb = NULL;
3652         }
3653
3654         /* Update computed state. */
3655         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3656                 if (!connector->encoder || !connector->encoder->crtc)
3657                         continue;
3658
3659                 if (connector->encoder->crtc != crtc)
3660                         continue;
3661
3662                 connector->dpms = DRM_MODE_DPMS_OFF;
3663                 to_intel_encoder(connector->encoder)->connectors_active = false;
3664         }
3665 }
3666
3667 void intel_modeset_disable(struct drm_device *dev)
3668 {
3669         struct drm_crtc *crtc;
3670
3671         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3672                 if (crtc->enabled)
3673                         intel_crtc_disable(crtc);
3674         }
3675 }
3676
3677 void intel_encoder_noop(struct drm_encoder *encoder)
3678 {
3679 }
3680
3681 void intel_encoder_destroy(struct drm_encoder *encoder)
3682 {
3683         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3684
3685         drm_encoder_cleanup(encoder);
3686         kfree(intel_encoder);
3687 }
3688
3689 /* Simple dpms helper for encodres with just one connector, no cloning and only
3690  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3691  * state of the entire output pipe. */
3692 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3693 {
3694         if (mode == DRM_MODE_DPMS_ON) {
3695                 encoder->connectors_active = true;
3696
3697                 intel_crtc_update_dpms(encoder->base.crtc);
3698         } else {
3699                 encoder->connectors_active = false;
3700
3701                 intel_crtc_update_dpms(encoder->base.crtc);
3702         }
3703 }
3704
3705 /* Cross check the actual hw state with our own modeset state tracking (and it's
3706  * internal consistency). */
3707 static void intel_connector_check_state(struct intel_connector *connector)
3708 {
3709         if (connector->get_hw_state(connector)) {
3710                 struct intel_encoder *encoder = connector->encoder;
3711                 struct drm_crtc *crtc;
3712                 bool encoder_enabled;
3713                 enum pipe pipe;
3714
3715                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3716                               connector->base.base.id,
3717                               drm_get_connector_name(&connector->base));
3718
3719                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3720                      "wrong connector dpms state\n");
3721                 WARN(connector->base.encoder != &encoder->base,
3722                      "active connector not linked to encoder\n");
3723                 WARN(!encoder->connectors_active,
3724                      "encoder->connectors_active not set\n");
3725
3726                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3727                 WARN(!encoder_enabled, "encoder not enabled\n");
3728                 if (WARN_ON(!encoder->base.crtc))
3729                         return;
3730
3731                 crtc = encoder->base.crtc;
3732
3733                 WARN(!crtc->enabled, "crtc not enabled\n");
3734                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3735                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3736                      "encoder active on the wrong pipe\n");
3737         }
3738 }
3739
3740 /* Even simpler default implementation, if there's really no special case to
3741  * consider. */
3742 void intel_connector_dpms(struct drm_connector *connector, int mode)
3743 {
3744         struct intel_encoder *encoder = intel_attached_encoder(connector);
3745
3746         /* All the simple cases only support two dpms states. */
3747         if (mode != DRM_MODE_DPMS_ON)
3748                 mode = DRM_MODE_DPMS_OFF;
3749
3750         if (mode == connector->dpms)
3751                 return;
3752
3753         connector->dpms = mode;
3754
3755         /* Only need to change hw state when actually enabled */
3756         if (encoder->base.crtc)
3757                 intel_encoder_dpms(encoder, mode);
3758         else
3759                 WARN_ON(encoder->connectors_active != false);
3760
3761         intel_modeset_check_state(connector->dev);
3762 }
3763
3764 /* Simple connector->get_hw_state implementation for encoders that support only
3765  * one connector and no cloning and hence the encoder state determines the state
3766  * of the connector. */
3767 bool intel_connector_get_hw_state(struct intel_connector *connector)
3768 {
3769         enum pipe pipe = 0;
3770         struct intel_encoder *encoder = connector->encoder;
3771
3772         return encoder->get_hw_state(encoder, &pipe);
3773 }
3774
3775 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3776                                   const struct drm_display_mode *mode,
3777                                   struct drm_display_mode *adjusted_mode)
3778 {
3779         struct drm_device *dev = crtc->dev;
3780
3781         if (HAS_PCH_SPLIT(dev)) {
3782                 /* FDI link clock is fixed at 2.7G */
3783                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3784                         return false;
3785         }
3786
3787         /* All interlaced capable intel hw wants timings in frames. Note though
3788          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3789          * timings, so we need to be careful not to clobber these.*/
3790         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3791                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3792
3793         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3794          * with a hsync front porch of 0.
3795          */
3796         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3797                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3798                 return false;
3799
3800         return true;
3801 }
3802
3803 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3804 {
3805         return 400000; /* FIXME */
3806 }
3807
3808 static int i945_get_display_clock_speed(struct drm_device *dev)
3809 {
3810         return 400000;
3811 }
3812
3813 static int i915_get_display_clock_speed(struct drm_device *dev)
3814 {
3815         return 333000;
3816 }
3817
3818 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3819 {
3820         return 200000;
3821 }
3822
3823 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3824 {
3825         u16 gcfgc = 0;
3826
3827         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3828
3829         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3830                 return 133000;
3831         else {
3832                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3833                 case GC_DISPLAY_CLOCK_333_MHZ:
3834                         return 333000;
3835                 default:
3836                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3837                         return 190000;
3838                 }
3839         }
3840 }
3841
3842 static int i865_get_display_clock_speed(struct drm_device *dev)
3843 {
3844         return 266000;
3845 }
3846
3847 static int i855_get_display_clock_speed(struct drm_device *dev)
3848 {
3849         u16 hpllcc = 0;
3850         /* Assume that the hardware is in the high speed state.  This
3851          * should be the default.
3852          */
3853         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3854         case GC_CLOCK_133_200:
3855         case GC_CLOCK_100_200:
3856                 return 200000;
3857         case GC_CLOCK_166_250:
3858                 return 250000;
3859         case GC_CLOCK_100_133:
3860                 return 133000;
3861         }
3862
3863         /* Shouldn't happen */
3864         return 0;
3865 }
3866
3867 static int i830_get_display_clock_speed(struct drm_device *dev)
3868 {
3869         return 133000;
3870 }
3871
3872 struct fdi_m_n {
3873         u32        tu;
3874         u32        gmch_m;
3875         u32        gmch_n;
3876         u32        link_m;
3877         u32        link_n;
3878 };
3879
3880 static void
3881 fdi_reduce_ratio(u32 *num, u32 *den)
3882 {
3883         while (*num > 0xffffff || *den > 0xffffff) {
3884                 *num >>= 1;
3885                 *den >>= 1;
3886         }
3887 }
3888
3889 static void
3890 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3891                      int link_clock, struct fdi_m_n *m_n)
3892 {
3893         m_n->tu = 64; /* default size */
3894
3895         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3896         m_n->gmch_m = bits_per_pixel * pixel_clock;
3897         m_n->gmch_n = link_clock * nlanes * 8;
3898         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3899
3900         m_n->link_m = pixel_clock;
3901         m_n->link_n = link_clock;
3902         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3903 }
3904
3905 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3906 {
3907         if (i915_panel_use_ssc >= 0)
3908                 return i915_panel_use_ssc != 0;
3909         return dev_priv->lvds_use_ssc
3910                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3911 }
3912
3913 /**
3914  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3915  * @crtc: CRTC structure
3916  * @mode: requested mode
3917  *
3918  * A pipe may be connected to one or more outputs.  Based on the depth of the
3919  * attached framebuffer, choose a good color depth to use on the pipe.
3920  *
3921  * If possible, match the pipe depth to the fb depth.  In some cases, this
3922  * isn't ideal, because the connected output supports a lesser or restricted
3923  * set of depths.  Resolve that here:
3924  *    LVDS typically supports only 6bpc, so clamp down in that case
3925  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3926  *    Displays may support a restricted set as well, check EDID and clamp as
3927  *      appropriate.
3928  *    DP may want to dither down to 6bpc to fit larger modes
3929  *
3930  * RETURNS:
3931  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3932  * true if they don't match).
3933  */
3934 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3935                                          struct drm_framebuffer *fb,
3936                                          unsigned int *pipe_bpp,
3937                                          struct drm_display_mode *mode)
3938 {
3939         struct drm_device *dev = crtc->dev;
3940         struct drm_i915_private *dev_priv = dev->dev_private;
3941         struct drm_connector *connector;
3942         struct intel_encoder *intel_encoder;
3943         unsigned int display_bpc = UINT_MAX, bpc;
3944
3945         /* Walk the encoders & connectors on this crtc, get min bpc */
3946         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3947
3948                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3949                         unsigned int lvds_bpc;
3950
3951                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3952                             LVDS_A3_POWER_UP)
3953                                 lvds_bpc = 8;
3954                         else
3955                                 lvds_bpc = 6;
3956
3957                         if (lvds_bpc < display_bpc) {
3958                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3959                                 display_bpc = lvds_bpc;
3960                         }
3961                         continue;
3962                 }
3963
3964                 /* Not one of the known troublemakers, check the EDID */
3965                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3966                                     head) {
3967                         if (connector->encoder != &intel_encoder->base)
3968                                 continue;
3969
3970                         /* Don't use an invalid EDID bpc value */
3971                         if (connector->display_info.bpc &&
3972                             connector->display_info.bpc < display_bpc) {
3973                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3974                                 display_bpc = connector->display_info.bpc;
3975                         }
3976                 }
3977
3978                 /*
3979                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3980                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3981                  */
3982                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3983                         if (display_bpc > 8 && display_bpc < 12) {
3984                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3985                                 display_bpc = 12;
3986                         } else {
3987                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3988                                 display_bpc = 8;
3989                         }
3990                 }
3991         }
3992
3993         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3994                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3995                 display_bpc = 6;
3996         }
3997
3998         /*
3999          * We could just drive the pipe at the highest bpc all the time and
4000          * enable dithering as needed, but that costs bandwidth.  So choose
4001          * the minimum value that expresses the full color range of the fb but
4002          * also stays within the max display bpc discovered above.
4003          */
4004
4005         switch (fb->depth) {
4006         case 8:
4007                 bpc = 8; /* since we go through a colormap */
4008                 break;
4009         case 15:
4010         case 16:
4011                 bpc = 6; /* min is 18bpp */
4012                 break;
4013         case 24:
4014                 bpc = 8;
4015                 break;
4016         case 30:
4017                 bpc = 10;
4018                 break;
4019         case 48:
4020                 bpc = 12;
4021                 break;
4022         default:
4023                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4024                 bpc = min((unsigned int)8, display_bpc);
4025                 break;
4026         }
4027
4028         display_bpc = min(display_bpc, bpc);
4029
4030         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4031                       bpc, display_bpc);
4032
4033         *pipe_bpp = display_bpc * 3;
4034
4035         return display_bpc != bpc;
4036 }
4037
4038 static int vlv_get_refclk(struct drm_crtc *crtc)
4039 {
4040         struct drm_device *dev = crtc->dev;
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         int refclk = 27000; /* for DP & HDMI */
4043
4044         return 100000; /* only one validated so far */
4045
4046         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4047                 refclk = 96000;
4048         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4049                 if (intel_panel_use_ssc(dev_priv))
4050                         refclk = 100000;
4051                 else
4052                         refclk = 96000;
4053         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4054                 refclk = 100000;
4055         }
4056
4057         return refclk;
4058 }
4059
4060 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4061 {
4062         struct drm_device *dev = crtc->dev;
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         int refclk;
4065
4066         if (IS_VALLEYVIEW(dev)) {
4067                 refclk = vlv_get_refclk(crtc);
4068         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4069             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4070                 refclk = dev_priv->lvds_ssc_freq * 1000;
4071                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4072                               refclk / 1000);
4073         } else if (!IS_GEN2(dev)) {
4074                 refclk = 96000;
4075         } else {
4076                 refclk = 48000;
4077         }
4078
4079         return refclk;
4080 }
4081
4082 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4083                                       intel_clock_t *clock)
4084 {
4085         /* SDVO TV has fixed PLL values depend on its clock range,
4086            this mirrors vbios setting. */
4087         if (adjusted_mode->clock >= 100000
4088             && adjusted_mode->clock < 140500) {
4089                 clock->p1 = 2;
4090                 clock->p2 = 10;
4091                 clock->n = 3;
4092                 clock->m1 = 16;
4093                 clock->m2 = 8;
4094         } else if (adjusted_mode->clock >= 140500
4095                    && adjusted_mode->clock <= 200000) {
4096                 clock->p1 = 1;
4097                 clock->p2 = 10;
4098                 clock->n = 6;
4099                 clock->m1 = 12;
4100                 clock->m2 = 8;
4101         }
4102 }
4103
4104 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4105                                      intel_clock_t *clock,
4106                                      intel_clock_t *reduced_clock)
4107 {
4108         struct drm_device *dev = crtc->dev;
4109         struct drm_i915_private *dev_priv = dev->dev_private;
4110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4111         int pipe = intel_crtc->pipe;
4112         u32 fp, fp2 = 0;
4113
4114         if (IS_PINEVIEW(dev)) {
4115                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4116                 if (reduced_clock)
4117                         fp2 = (1 << reduced_clock->n) << 16 |
4118                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4119         } else {
4120                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4121                 if (reduced_clock)
4122                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4123                                 reduced_clock->m2;
4124         }
4125
4126         I915_WRITE(FP0(pipe), fp);
4127
4128         intel_crtc->lowfreq_avail = false;
4129         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4130             reduced_clock && i915_powersave) {
4131                 I915_WRITE(FP1(pipe), fp2);
4132                 intel_crtc->lowfreq_avail = true;
4133         } else {
4134                 I915_WRITE(FP1(pipe), fp);
4135         }
4136 }
4137
4138 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4139                               struct drm_display_mode *adjusted_mode)
4140 {
4141         struct drm_device *dev = crtc->dev;
4142         struct drm_i915_private *dev_priv = dev->dev_private;
4143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4144         int pipe = intel_crtc->pipe;
4145         u32 temp;
4146
4147         temp = I915_READ(LVDS);
4148         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4149         if (pipe == 1) {
4150                 temp |= LVDS_PIPEB_SELECT;
4151         } else {
4152                 temp &= ~LVDS_PIPEB_SELECT;
4153         }
4154         /* set the corresponsding LVDS_BORDER bit */
4155         temp |= dev_priv->lvds_border_bits;
4156         /* Set the B0-B3 data pairs corresponding to whether we're going to
4157          * set the DPLLs for dual-channel mode or not.
4158          */
4159         if (clock->p2 == 7)
4160                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4161         else
4162                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4163
4164         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4165          * appropriately here, but we need to look more thoroughly into how
4166          * panels behave in the two modes.
4167          */
4168         /* set the dithering flag on LVDS as needed */
4169         if (INTEL_INFO(dev)->gen >= 4) {
4170                 if (dev_priv->lvds_dither)
4171                         temp |= LVDS_ENABLE_DITHER;
4172                 else
4173                         temp &= ~LVDS_ENABLE_DITHER;
4174         }
4175         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4176         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4177                 temp |= LVDS_HSYNC_POLARITY;
4178         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4179                 temp |= LVDS_VSYNC_POLARITY;
4180         I915_WRITE(LVDS, temp);
4181 }
4182
4183 static void vlv_update_pll(struct drm_crtc *crtc,
4184                            struct drm_display_mode *mode,
4185                            struct drm_display_mode *adjusted_mode,
4186                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4187                            int num_connectors)
4188 {
4189         struct drm_device *dev = crtc->dev;
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192         int pipe = intel_crtc->pipe;
4193         u32 dpll, mdiv, pdiv;
4194         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4195         bool is_sdvo;
4196         u32 temp;
4197
4198         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4199                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4200
4201         dpll = DPLL_VGA_MODE_DIS;
4202         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4203         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4204         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4205
4206         I915_WRITE(DPLL(pipe), dpll);
4207         POSTING_READ(DPLL(pipe));
4208
4209         bestn = clock->n;
4210         bestm1 = clock->m1;
4211         bestm2 = clock->m2;
4212         bestp1 = clock->p1;
4213         bestp2 = clock->p2;
4214
4215         /*
4216          * In Valleyview PLL and program lane counter registers are exposed
4217          * through DPIO interface
4218          */
4219         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4220         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4221         mdiv |= ((bestn << DPIO_N_SHIFT));
4222         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4223         mdiv |= (1 << DPIO_K_SHIFT);
4224         mdiv |= DPIO_ENABLE_CALIBRATION;
4225         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4226
4227         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4228
4229         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4230                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4231                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4232                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4233         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4234
4235         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4236
4237         dpll |= DPLL_VCO_ENABLE;
4238         I915_WRITE(DPLL(pipe), dpll);
4239         POSTING_READ(DPLL(pipe));
4240         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4241                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4242
4243         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4244
4245         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4246                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4247
4248         I915_WRITE(DPLL(pipe), dpll);
4249
4250         /* Wait for the clocks to stabilize. */
4251         POSTING_READ(DPLL(pipe));
4252         udelay(150);
4253
4254         temp = 0;
4255         if (is_sdvo) {
4256                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4257                 if (temp > 1)
4258                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4259                 else
4260                         temp = 0;
4261         }
4262         I915_WRITE(DPLL_MD(pipe), temp);
4263         POSTING_READ(DPLL_MD(pipe));
4264
4265         /* Now program lane control registers */
4266         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4267                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4268         {
4269                 temp = 0x1000C4;
4270                 if(pipe == 1)
4271                         temp |= (1 << 21);
4272                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4273         }
4274         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4275         {
4276                 temp = 0x1000C4;
4277                 if(pipe == 1)
4278                         temp |= (1 << 21);
4279                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4280         }
4281 }
4282
4283 static void i9xx_update_pll(struct drm_crtc *crtc,
4284                             struct drm_display_mode *mode,
4285                             struct drm_display_mode *adjusted_mode,
4286                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4287                             int num_connectors)
4288 {
4289         struct drm_device *dev = crtc->dev;
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4292         int pipe = intel_crtc->pipe;
4293         u32 dpll;
4294         bool is_sdvo;
4295
4296         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4297
4298         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4299                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4300
4301         dpll = DPLL_VGA_MODE_DIS;
4302
4303         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4304                 dpll |= DPLLB_MODE_LVDS;
4305         else
4306                 dpll |= DPLLB_MODE_DAC_SERIAL;
4307         if (is_sdvo) {
4308                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4309                 if (pixel_multiplier > 1) {
4310                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4311                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4312                 }
4313                 dpll |= DPLL_DVO_HIGH_SPEED;
4314         }
4315         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4316                 dpll |= DPLL_DVO_HIGH_SPEED;
4317
4318         /* compute bitmask from p1 value */
4319         if (IS_PINEVIEW(dev))
4320                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4321         else {
4322                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4323                 if (IS_G4X(dev) && reduced_clock)
4324                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4325         }
4326         switch (clock->p2) {
4327         case 5:
4328                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4329                 break;
4330         case 7:
4331                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4332                 break;
4333         case 10:
4334                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4335                 break;
4336         case 14:
4337                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4338                 break;
4339         }
4340         if (INTEL_INFO(dev)->gen >= 4)
4341                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4342
4343         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4344                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4345         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4346                 /* XXX: just matching BIOS for now */
4347                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4348                 dpll |= 3;
4349         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4350                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4351                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4352         else
4353                 dpll |= PLL_REF_INPUT_DREFCLK;
4354
4355         dpll |= DPLL_VCO_ENABLE;
4356         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4357         POSTING_READ(DPLL(pipe));
4358         udelay(150);
4359
4360         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4361          * This is an exception to the general rule that mode_set doesn't turn
4362          * things on.
4363          */
4364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4365                 intel_update_lvds(crtc, clock, adjusted_mode);
4366
4367         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4368                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4369
4370         I915_WRITE(DPLL(pipe), dpll);
4371
4372         /* Wait for the clocks to stabilize. */
4373         POSTING_READ(DPLL(pipe));
4374         udelay(150);
4375
4376         if (INTEL_INFO(dev)->gen >= 4) {
4377                 u32 temp = 0;
4378                 if (is_sdvo) {
4379                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4380                         if (temp > 1)
4381                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4382                         else
4383                                 temp = 0;
4384                 }
4385                 I915_WRITE(DPLL_MD(pipe), temp);
4386         } else {
4387                 /* The pixel multiplier can only be updated once the
4388                  * DPLL is enabled and the clocks are stable.
4389                  *
4390                  * So write it again.
4391                  */
4392                 I915_WRITE(DPLL(pipe), dpll);
4393         }
4394 }
4395
4396 static void i8xx_update_pll(struct drm_crtc *crtc,
4397                             struct drm_display_mode *adjusted_mode,
4398                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4399                             int num_connectors)
4400 {
4401         struct drm_device *dev = crtc->dev;
4402         struct drm_i915_private *dev_priv = dev->dev_private;
4403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4404         int pipe = intel_crtc->pipe;
4405         u32 dpll;
4406
4407         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4408
4409         dpll = DPLL_VGA_MODE_DIS;
4410
4411         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4412                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4413         } else {
4414                 if (clock->p1 == 2)
4415                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4416                 else
4417                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4418                 if (clock->p2 == 4)
4419                         dpll |= PLL_P2_DIVIDE_BY_4;
4420         }
4421
4422         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4423                 /* XXX: just matching BIOS for now */
4424                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4425                 dpll |= 3;
4426         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4427                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4428                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4429         else
4430                 dpll |= PLL_REF_INPUT_DREFCLK;
4431
4432         dpll |= DPLL_VCO_ENABLE;
4433         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4434         POSTING_READ(DPLL(pipe));
4435         udelay(150);
4436
4437         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4438          * This is an exception to the general rule that mode_set doesn't turn
4439          * things on.
4440          */
4441         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4442                 intel_update_lvds(crtc, clock, adjusted_mode);
4443
4444         I915_WRITE(DPLL(pipe), dpll);
4445
4446         /* Wait for the clocks to stabilize. */
4447         POSTING_READ(DPLL(pipe));
4448         udelay(150);
4449
4450         /* The pixel multiplier can only be updated once the
4451          * DPLL is enabled and the clocks are stable.
4452          *
4453          * So write it again.
4454          */
4455         I915_WRITE(DPLL(pipe), dpll);
4456 }
4457
4458 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4459                                    struct drm_display_mode *mode,
4460                                    struct drm_display_mode *adjusted_mode)
4461 {
4462         struct drm_device *dev = intel_crtc->base.dev;
4463         struct drm_i915_private *dev_priv = dev->dev_private;
4464         enum pipe pipe = intel_crtc->pipe;
4465         uint32_t vsyncshift;
4466
4467         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4468                 /* the chip adds 2 halflines automatically */
4469                 adjusted_mode->crtc_vtotal -= 1;
4470                 adjusted_mode->crtc_vblank_end -= 1;
4471                 vsyncshift = adjusted_mode->crtc_hsync_start
4472                              - adjusted_mode->crtc_htotal / 2;
4473         } else {
4474                 vsyncshift = 0;
4475         }
4476
4477         if (INTEL_INFO(dev)->gen > 3)
4478                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4479
4480         I915_WRITE(HTOTAL(pipe),
4481                    (adjusted_mode->crtc_hdisplay - 1) |
4482                    ((adjusted_mode->crtc_htotal - 1) << 16));
4483         I915_WRITE(HBLANK(pipe),
4484                    (adjusted_mode->crtc_hblank_start - 1) |
4485                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4486         I915_WRITE(HSYNC(pipe),
4487                    (adjusted_mode->crtc_hsync_start - 1) |
4488                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4489
4490         I915_WRITE(VTOTAL(pipe),
4491                    (adjusted_mode->crtc_vdisplay - 1) |
4492                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4493         I915_WRITE(VBLANK(pipe),
4494                    (adjusted_mode->crtc_vblank_start - 1) |
4495                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4496         I915_WRITE(VSYNC(pipe),
4497                    (adjusted_mode->crtc_vsync_start - 1) |
4498                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4499
4500         /* pipesrc controls the size that is scaled from, which should
4501          * always be the user's requested size.
4502          */
4503         I915_WRITE(PIPESRC(pipe),
4504                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4505 }
4506
4507 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4508                               struct drm_display_mode *mode,
4509                               struct drm_display_mode *adjusted_mode,
4510                               int x, int y,
4511                               struct drm_framebuffer *fb)
4512 {
4513         struct drm_device *dev = crtc->dev;
4514         struct drm_i915_private *dev_priv = dev->dev_private;
4515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516         int pipe = intel_crtc->pipe;
4517         int plane = intel_crtc->plane;
4518         int refclk, num_connectors = 0;
4519         intel_clock_t clock, reduced_clock;
4520         u32 dspcntr, pipeconf;
4521         bool ok, has_reduced_clock = false, is_sdvo = false;
4522         bool is_lvds = false, is_tv = false, is_dp = false;
4523         struct intel_encoder *encoder;
4524         const intel_limit_t *limit;
4525         int ret;
4526
4527         for_each_encoder_on_crtc(dev, crtc, encoder) {
4528                 switch (encoder->type) {
4529                 case INTEL_OUTPUT_LVDS:
4530                         is_lvds = true;
4531                         break;
4532                 case INTEL_OUTPUT_SDVO:
4533                 case INTEL_OUTPUT_HDMI:
4534                         is_sdvo = true;
4535                         if (encoder->needs_tv_clock)
4536                                 is_tv = true;
4537                         break;
4538                 case INTEL_OUTPUT_TVOUT:
4539                         is_tv = true;
4540                         break;
4541                 case INTEL_OUTPUT_DISPLAYPORT:
4542                         is_dp = true;
4543                         break;
4544                 }
4545
4546                 num_connectors++;
4547         }
4548
4549         refclk = i9xx_get_refclk(crtc, num_connectors);
4550
4551         /*
4552          * Returns a set of divisors for the desired target clock with the given
4553          * refclk, or FALSE.  The returned values represent the clock equation:
4554          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4555          */
4556         limit = intel_limit(crtc, refclk);
4557         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4558                              &clock);
4559         if (!ok) {
4560                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4561                 return -EINVAL;
4562         }
4563
4564         /* Ensure that the cursor is valid for the new mode before changing... */
4565         intel_crtc_update_cursor(crtc, true);
4566
4567         if (is_lvds && dev_priv->lvds_downclock_avail) {
4568                 /*
4569                  * Ensure we match the reduced clock's P to the target clock.
4570                  * If the clocks don't match, we can't switch the display clock
4571                  * by using the FP0/FP1. In such case we will disable the LVDS
4572                  * downclock feature.
4573                 */
4574                 has_reduced_clock = limit->find_pll(limit, crtc,
4575                                                     dev_priv->lvds_downclock,
4576                                                     refclk,
4577                                                     &clock,
4578                                                     &reduced_clock);
4579         }
4580
4581         if (is_sdvo && is_tv)
4582                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4583
4584         if (IS_GEN2(dev))
4585                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4586                                 has_reduced_clock ? &reduced_clock : NULL,
4587                                 num_connectors);
4588         else if (IS_VALLEYVIEW(dev))
4589                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4590                                 has_reduced_clock ? &reduced_clock : NULL,
4591                                 num_connectors);
4592         else
4593                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4594                                 has_reduced_clock ? &reduced_clock : NULL,
4595                                 num_connectors);
4596
4597         /* setup pipeconf */
4598         pipeconf = I915_READ(PIPECONF(pipe));
4599
4600         /* Set up the display plane register */
4601         dspcntr = DISPPLANE_GAMMA_ENABLE;
4602
4603         if (pipe == 0)
4604                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4605         else
4606                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4607
4608         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4609                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4610                  * core speed.
4611                  *
4612                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4613                  * pipe == 0 check?
4614                  */
4615                 if (mode->clock >
4616                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4617                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4618                 else
4619                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4620         }
4621
4622         /* default to 8bpc */
4623         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4624         if (is_dp) {
4625                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4626                         pipeconf |= PIPECONF_BPP_6 |
4627                                     PIPECONF_DITHER_EN |
4628                                     PIPECONF_DITHER_TYPE_SP;
4629                 }
4630         }
4631
4632         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4633                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4634                         pipeconf |= PIPECONF_BPP_6 |
4635                                         PIPECONF_ENABLE |
4636                                         I965_PIPECONF_ACTIVE;
4637                 }
4638         }
4639
4640         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4641         drm_mode_debug_printmodeline(mode);
4642
4643         if (HAS_PIPE_CXSR(dev)) {
4644                 if (intel_crtc->lowfreq_avail) {
4645                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4646                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4647                 } else {
4648                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4649                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4650                 }
4651         }
4652
4653         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4654         if (!IS_GEN2(dev) &&
4655             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4656                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4657         else
4658                 pipeconf |= PIPECONF_PROGRESSIVE;
4659
4660         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4661
4662         /* pipesrc and dspsize control the size that is scaled from,
4663          * which should always be the user's requested size.
4664          */
4665         I915_WRITE(DSPSIZE(plane),
4666                    ((mode->vdisplay - 1) << 16) |
4667                    (mode->hdisplay - 1));
4668         I915_WRITE(DSPPOS(plane), 0);
4669
4670         I915_WRITE(PIPECONF(pipe), pipeconf);
4671         POSTING_READ(PIPECONF(pipe));
4672         intel_enable_pipe(dev_priv, pipe, false);
4673
4674         intel_wait_for_vblank(dev, pipe);
4675
4676         I915_WRITE(DSPCNTR(plane), dspcntr);
4677         POSTING_READ(DSPCNTR(plane));
4678
4679         ret = intel_pipe_set_base(crtc, x, y, fb);
4680
4681         intel_update_watermarks(dev);
4682
4683         return ret;
4684 }
4685
4686 /*
4687  * Initialize reference clocks when the driver loads
4688  */
4689 void ironlake_init_pch_refclk(struct drm_device *dev)
4690 {
4691         struct drm_i915_private *dev_priv = dev->dev_private;
4692         struct drm_mode_config *mode_config = &dev->mode_config;
4693         struct intel_encoder *encoder;
4694         u32 temp;
4695         bool has_lvds = false;
4696         bool has_cpu_edp = false;
4697         bool has_pch_edp = false;
4698         bool has_panel = false;
4699         bool has_ck505 = false;
4700         bool can_ssc = false;
4701
4702         /* We need to take the global config into account */
4703         list_for_each_entry(encoder, &mode_config->encoder_list,
4704                             base.head) {
4705                 switch (encoder->type) {
4706                 case INTEL_OUTPUT_LVDS:
4707                         has_panel = true;
4708                         has_lvds = true;
4709                         break;
4710                 case INTEL_OUTPUT_EDP:
4711                         has_panel = true;
4712                         if (intel_encoder_is_pch_edp(&encoder->base))
4713                                 has_pch_edp = true;
4714                         else
4715                                 has_cpu_edp = true;
4716                         break;
4717                 }
4718         }
4719
4720         if (HAS_PCH_IBX(dev)) {
4721                 has_ck505 = dev_priv->display_clock_mode;
4722                 can_ssc = has_ck505;
4723         } else {
4724                 has_ck505 = false;
4725                 can_ssc = true;
4726         }
4727
4728         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4729                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4730                       has_ck505);
4731
4732         /* Ironlake: try to setup display ref clock before DPLL
4733          * enabling. This is only under driver's control after
4734          * PCH B stepping, previous chipset stepping should be
4735          * ignoring this setting.
4736          */
4737         temp = I915_READ(PCH_DREF_CONTROL);
4738         /* Always enable nonspread source */
4739         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4740
4741         if (has_ck505)
4742                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4743         else
4744                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4745
4746         if (has_panel) {
4747                 temp &= ~DREF_SSC_SOURCE_MASK;
4748                 temp |= DREF_SSC_SOURCE_ENABLE;
4749
4750                 /* SSC must be turned on before enabling the CPU output  */
4751                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4752                         DRM_DEBUG_KMS("Using SSC on panel\n");
4753                         temp |= DREF_SSC1_ENABLE;
4754                 } else
4755                         temp &= ~DREF_SSC1_ENABLE;
4756
4757                 /* Get SSC going before enabling the outputs */
4758                 I915_WRITE(PCH_DREF_CONTROL, temp);
4759                 POSTING_READ(PCH_DREF_CONTROL);
4760                 udelay(200);
4761
4762                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4763
4764                 /* Enable CPU source on CPU attached eDP */
4765                 if (has_cpu_edp) {
4766                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4767                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4768                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4769                         }
4770                         else
4771                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4772                 } else
4773                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4774
4775                 I915_WRITE(PCH_DREF_CONTROL, temp);
4776                 POSTING_READ(PCH_DREF_CONTROL);
4777                 udelay(200);
4778         } else {
4779                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4780
4781                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4782
4783                 /* Turn off CPU output */
4784                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4785
4786                 I915_WRITE(PCH_DREF_CONTROL, temp);
4787                 POSTING_READ(PCH_DREF_CONTROL);
4788                 udelay(200);
4789
4790                 /* Turn off the SSC source */
4791                 temp &= ~DREF_SSC_SOURCE_MASK;
4792                 temp |= DREF_SSC_SOURCE_DISABLE;
4793
4794                 /* Turn off SSC1 */
4795                 temp &= ~ DREF_SSC1_ENABLE;
4796
4797                 I915_WRITE(PCH_DREF_CONTROL, temp);
4798                 POSTING_READ(PCH_DREF_CONTROL);
4799                 udelay(200);
4800         }
4801 }
4802
4803 static int ironlake_get_refclk(struct drm_crtc *crtc)
4804 {
4805         struct drm_device *dev = crtc->dev;
4806         struct drm_i915_private *dev_priv = dev->dev_private;
4807         struct intel_encoder *encoder;
4808         struct intel_encoder *edp_encoder = NULL;
4809         int num_connectors = 0;
4810         bool is_lvds = false;
4811
4812         for_each_encoder_on_crtc(dev, crtc, encoder) {
4813                 switch (encoder->type) {
4814                 case INTEL_OUTPUT_LVDS:
4815                         is_lvds = true;
4816                         break;
4817                 case INTEL_OUTPUT_EDP:
4818                         edp_encoder = encoder;
4819                         break;
4820                 }
4821                 num_connectors++;
4822         }
4823
4824         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4825                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4826                               dev_priv->lvds_ssc_freq);
4827                 return dev_priv->lvds_ssc_freq * 1000;
4828         }
4829
4830         return 120000;
4831 }
4832
4833 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4834                                   struct drm_display_mode *adjusted_mode,
4835                                   bool dither)
4836 {
4837         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839         int pipe = intel_crtc->pipe;
4840         uint32_t val;
4841
4842         val = I915_READ(PIPECONF(pipe));
4843
4844         val &= ~PIPE_BPC_MASK;
4845         switch (intel_crtc->bpp) {
4846         case 18:
4847                 val |= PIPE_6BPC;
4848                 break;
4849         case 24:
4850                 val |= PIPE_8BPC;
4851                 break;
4852         case 30:
4853                 val |= PIPE_10BPC;
4854                 break;
4855         case 36:
4856                 val |= PIPE_12BPC;
4857                 break;
4858         default:
4859                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4860                 BUG();
4861         }
4862
4863         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4864         if (dither)
4865                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4866
4867         val &= ~PIPECONF_INTERLACE_MASK;
4868         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4869                 val |= PIPECONF_INTERLACED_ILK;
4870         else
4871                 val |= PIPECONF_PROGRESSIVE;
4872
4873         I915_WRITE(PIPECONF(pipe), val);
4874         POSTING_READ(PIPECONF(pipe));
4875 }
4876
4877 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4878                                  struct drm_display_mode *adjusted_mode,
4879                                  bool dither)
4880 {
4881         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883         int pipe = intel_crtc->pipe;
4884         uint32_t val;
4885
4886         val = I915_READ(PIPECONF(pipe));
4887
4888         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4889         if (dither)
4890                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4891
4892         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4893         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4894                 val |= PIPECONF_INTERLACED_ILK;
4895         else
4896                 val |= PIPECONF_PROGRESSIVE;
4897
4898         I915_WRITE(PIPECONF(pipe), val);
4899         POSTING_READ(PIPECONF(pipe));
4900 }
4901
4902 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4903                                     struct drm_display_mode *adjusted_mode,
4904                                     intel_clock_t *clock,
4905                                     bool *has_reduced_clock,
4906                                     intel_clock_t *reduced_clock)
4907 {
4908         struct drm_device *dev = crtc->dev;
4909         struct drm_i915_private *dev_priv = dev->dev_private;
4910         struct intel_encoder *intel_encoder;
4911         int refclk;
4912         const intel_limit_t *limit;
4913         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4914
4915         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4916                 switch (intel_encoder->type) {
4917                 case INTEL_OUTPUT_LVDS:
4918                         is_lvds = true;
4919                         break;
4920                 case INTEL_OUTPUT_SDVO:
4921                 case INTEL_OUTPUT_HDMI:
4922                         is_sdvo = true;
4923                         if (intel_encoder->needs_tv_clock)
4924                                 is_tv = true;
4925                         break;
4926                 case INTEL_OUTPUT_TVOUT:
4927                         is_tv = true;
4928                         break;
4929                 }
4930         }
4931
4932         refclk = ironlake_get_refclk(crtc);
4933
4934         /*
4935          * Returns a set of divisors for the desired target clock with the given
4936          * refclk, or FALSE.  The returned values represent the clock equation:
4937          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4938          */
4939         limit = intel_limit(crtc, refclk);
4940         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4941                               clock);
4942         if (!ret)
4943                 return false;
4944
4945         if (is_lvds && dev_priv->lvds_downclock_avail) {
4946                 /*
4947                  * Ensure we match the reduced clock's P to the target clock.
4948                  * If the clocks don't match, we can't switch the display clock
4949                  * by using the FP0/FP1. In such case we will disable the LVDS
4950                  * downclock feature.
4951                 */
4952                 *has_reduced_clock = limit->find_pll(limit, crtc,
4953                                                      dev_priv->lvds_downclock,
4954                                                      refclk,
4955                                                      clock,
4956                                                      reduced_clock);
4957         }
4958
4959         if (is_sdvo && is_tv)
4960                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4961
4962         return true;
4963 }
4964
4965 static void ironlake_set_m_n(struct drm_crtc *crtc,
4966                              struct drm_display_mode *mode,
4967                              struct drm_display_mode *adjusted_mode)
4968 {
4969         struct drm_device *dev = crtc->dev;
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972         enum pipe pipe = intel_crtc->pipe;
4973         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4974         struct fdi_m_n m_n = {0};
4975         int target_clock, pixel_multiplier, lane, link_bw;
4976         bool is_dp = false, is_cpu_edp = false;
4977
4978         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4979                 switch (intel_encoder->type) {
4980                 case INTEL_OUTPUT_DISPLAYPORT:
4981                         is_dp = true;
4982                         break;
4983                 case INTEL_OUTPUT_EDP:
4984                         is_dp = true;
4985                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4986                                 is_cpu_edp = true;
4987                         edp_encoder = intel_encoder;
4988                         break;
4989                 }
4990         }
4991
4992         /* FDI link */
4993         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4994         lane = 0;
4995         /* CPU eDP doesn't require FDI link, so just set DP M/N
4996            according to current link config */
4997         if (is_cpu_edp) {
4998                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4999         } else {
5000                 /* FDI is a binary signal running at ~2.7GHz, encoding
5001                  * each output octet as 10 bits. The actual frequency
5002                  * is stored as a divider into a 100MHz clock, and the
5003                  * mode pixel clock is stored in units of 1KHz.
5004                  * Hence the bw of each lane in terms of the mode signal
5005                  * is:
5006                  */
5007                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5008         }
5009
5010         /* [e]DP over FDI requires target mode clock instead of link clock. */
5011         if (edp_encoder)
5012                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5013         else if (is_dp)
5014                 target_clock = mode->clock;
5015         else
5016                 target_clock = adjusted_mode->clock;
5017
5018         if (!lane) {
5019                 /*
5020                  * Account for spread spectrum to avoid
5021                  * oversubscribing the link. Max center spread
5022                  * is 2.5%; use 5% for safety's sake.
5023                  */
5024                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5025                 lane = bps / (link_bw * 8) + 1;
5026         }
5027
5028         intel_crtc->fdi_lanes = lane;
5029
5030         if (pixel_multiplier > 1)
5031                 link_bw *= pixel_multiplier;
5032         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5033                              &m_n);
5034
5035         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5036         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5037         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5038         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5039 }
5040
5041 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5042                                       struct drm_display_mode *adjusted_mode,
5043                                       intel_clock_t *clock, u32 fp)
5044 {
5045         struct drm_crtc *crtc = &intel_crtc->base;
5046         struct drm_device *dev = crtc->dev;
5047         struct drm_i915_private *dev_priv = dev->dev_private;
5048         struct intel_encoder *intel_encoder;
5049         uint32_t dpll;
5050         int factor, pixel_multiplier, num_connectors = 0;
5051         bool is_lvds = false, is_sdvo = false, is_tv = false;
5052         bool is_dp = false, is_cpu_edp = false;
5053
5054         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5055                 switch (intel_encoder->type) {
5056                 case INTEL_OUTPUT_LVDS:
5057                         is_lvds = true;
5058                         break;
5059                 case INTEL_OUTPUT_SDVO:
5060                 case INTEL_OUTPUT_HDMI:
5061                         is_sdvo = true;
5062                         if (intel_encoder->needs_tv_clock)
5063                                 is_tv = true;
5064                         break;
5065                 case INTEL_OUTPUT_TVOUT:
5066                         is_tv = true;
5067                         break;
5068                 case INTEL_OUTPUT_DISPLAYPORT:
5069                         is_dp = true;
5070                         break;
5071                 case INTEL_OUTPUT_EDP:
5072                         is_dp = true;
5073                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5074                                 is_cpu_edp = true;
5075                         break;
5076                 }
5077
5078                 num_connectors++;
5079         }
5080
5081         /* Enable autotuning of the PLL clock (if permissible) */
5082         factor = 21;
5083         if (is_lvds) {
5084                 if ((intel_panel_use_ssc(dev_priv) &&
5085                      dev_priv->lvds_ssc_freq == 100) ||
5086                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5087                         factor = 25;
5088         } else if (is_sdvo && is_tv)
5089                 factor = 20;
5090
5091         if (clock->m < factor * clock->n)
5092                 fp |= FP_CB_TUNE;
5093
5094         dpll = 0;
5095
5096         if (is_lvds)
5097                 dpll |= DPLLB_MODE_LVDS;
5098         else
5099                 dpll |= DPLLB_MODE_DAC_SERIAL;
5100         if (is_sdvo) {
5101                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5102                 if (pixel_multiplier > 1) {
5103                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5104                 }
5105                 dpll |= DPLL_DVO_HIGH_SPEED;
5106         }
5107         if (is_dp && !is_cpu_edp)
5108                 dpll |= DPLL_DVO_HIGH_SPEED;
5109
5110         /* compute bitmask from p1 value */
5111         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5112         /* also FPA1 */
5113         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5114
5115         switch (clock->p2) {
5116         case 5:
5117                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5118                 break;
5119         case 7:
5120                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5121                 break;
5122         case 10:
5123                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5124                 break;
5125         case 14:
5126                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5127                 break;
5128         }
5129
5130         if (is_sdvo && is_tv)
5131                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5132         else if (is_tv)
5133                 /* XXX: just matching BIOS for now */
5134                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5135                 dpll |= 3;
5136         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5137                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5138         else
5139                 dpll |= PLL_REF_INPUT_DREFCLK;
5140
5141         return dpll;
5142 }
5143
5144 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5145                                   struct drm_display_mode *mode,
5146                                   struct drm_display_mode *adjusted_mode,
5147                                   int x, int y,
5148                                   struct drm_framebuffer *fb)
5149 {
5150         struct drm_device *dev = crtc->dev;
5151         struct drm_i915_private *dev_priv = dev->dev_private;
5152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5153         int pipe = intel_crtc->pipe;
5154         int plane = intel_crtc->plane;
5155         int num_connectors = 0;
5156         intel_clock_t clock, reduced_clock;
5157         u32 dpll, fp = 0, fp2 = 0;
5158         bool ok, has_reduced_clock = false;
5159         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5160         struct intel_encoder *encoder;
5161         u32 temp;
5162         int ret;
5163         bool dither;
5164
5165         for_each_encoder_on_crtc(dev, crtc, encoder) {
5166                 switch (encoder->type) {
5167                 case INTEL_OUTPUT_LVDS:
5168                         is_lvds = true;
5169                         break;
5170                 case INTEL_OUTPUT_DISPLAYPORT:
5171                         is_dp = true;
5172                         break;
5173                 case INTEL_OUTPUT_EDP:
5174                         is_dp = true;
5175                         if (!intel_encoder_is_pch_edp(&encoder->base))
5176                                 is_cpu_edp = true;
5177                         break;
5178                 }
5179
5180                 num_connectors++;
5181         }
5182
5183         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5184              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5185
5186         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5187                                      &has_reduced_clock, &reduced_clock);
5188         if (!ok) {
5189                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5190                 return -EINVAL;
5191         }
5192
5193         /* Ensure that the cursor is valid for the new mode before changing... */
5194         intel_crtc_update_cursor(crtc, true);
5195
5196         /* determine panel color depth */
5197         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5198         if (is_lvds && dev_priv->lvds_dither)
5199                 dither = true;
5200
5201         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5202         if (has_reduced_clock)
5203                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5204                         reduced_clock.m2;
5205
5206         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5207
5208         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5209         drm_mode_debug_printmodeline(mode);
5210
5211         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5212         if (!is_cpu_edp) {
5213                 struct intel_pch_pll *pll;
5214
5215                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5216                 if (pll == NULL) {
5217                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5218                                          pipe);
5219                         return -EINVAL;
5220                 }
5221         } else
5222                 intel_put_pch_pll(intel_crtc);
5223
5224         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5225          * This is an exception to the general rule that mode_set doesn't turn
5226          * things on.
5227          */
5228         if (is_lvds) {
5229                 temp = I915_READ(PCH_LVDS);
5230                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5231                 if (HAS_PCH_CPT(dev)) {
5232                         temp &= ~PORT_TRANS_SEL_MASK;
5233                         temp |= PORT_TRANS_SEL_CPT(pipe);
5234                 } else {
5235                         if (pipe == 1)
5236                                 temp |= LVDS_PIPEB_SELECT;
5237                         else
5238                                 temp &= ~LVDS_PIPEB_SELECT;
5239                 }
5240
5241                 /* set the corresponsding LVDS_BORDER bit */
5242                 temp |= dev_priv->lvds_border_bits;
5243                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5244                  * set the DPLLs for dual-channel mode or not.
5245                  */
5246                 if (clock.p2 == 7)
5247                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5248                 else
5249                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5250
5251                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5252                  * appropriately here, but we need to look more thoroughly into how
5253                  * panels behave in the two modes.
5254                  */
5255                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5256                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5257                         temp |= LVDS_HSYNC_POLARITY;
5258                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5259                         temp |= LVDS_VSYNC_POLARITY;
5260                 I915_WRITE(PCH_LVDS, temp);
5261         }
5262
5263         if (is_dp && !is_cpu_edp) {
5264                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5265         } else {
5266                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5267                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5268                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5269                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5270                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5271         }
5272
5273         if (intel_crtc->pch_pll) {
5274                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5275
5276                 /* Wait for the clocks to stabilize. */
5277                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5278                 udelay(150);
5279
5280                 /* The pixel multiplier can only be updated once the
5281                  * DPLL is enabled and the clocks are stable.
5282                  *
5283                  * So write it again.
5284                  */
5285                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5286         }
5287
5288         intel_crtc->lowfreq_avail = false;
5289         if (intel_crtc->pch_pll) {
5290                 if (is_lvds && has_reduced_clock && i915_powersave) {
5291                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5292                         intel_crtc->lowfreq_avail = true;
5293                 } else {
5294                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5295                 }
5296         }
5297
5298         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5299
5300         ironlake_set_m_n(crtc, mode, adjusted_mode);
5301
5302         if (is_cpu_edp)
5303                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5304
5305         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5306
5307         intel_wait_for_vblank(dev, pipe);
5308
5309         /* Set up the display plane register */
5310         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5311         POSTING_READ(DSPCNTR(plane));
5312
5313         ret = intel_pipe_set_base(crtc, x, y, fb);
5314
5315         intel_update_watermarks(dev);
5316
5317         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5318
5319         return ret;
5320 }
5321
5322 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5323                                  struct drm_display_mode *mode,
5324                                  struct drm_display_mode *adjusted_mode,
5325                                  int x, int y,
5326                                  struct drm_framebuffer *fb)
5327 {
5328         struct drm_device *dev = crtc->dev;
5329         struct drm_i915_private *dev_priv = dev->dev_private;
5330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331         int pipe = intel_crtc->pipe;
5332         int plane = intel_crtc->plane;
5333         int num_connectors = 0;
5334         intel_clock_t clock, reduced_clock;
5335         u32 dpll = 0, fp = 0, fp2 = 0;
5336         bool ok, has_reduced_clock = false;
5337         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5338         struct intel_encoder *encoder;
5339         u32 temp;
5340         int ret;
5341         bool dither;
5342
5343         for_each_encoder_on_crtc(dev, crtc, encoder) {
5344                 switch (encoder->type) {
5345                 case INTEL_OUTPUT_LVDS:
5346                         is_lvds = true;
5347                         break;
5348                 case INTEL_OUTPUT_DISPLAYPORT:
5349                         is_dp = true;
5350                         break;
5351                 case INTEL_OUTPUT_EDP:
5352                         is_dp = true;
5353                         if (!intel_encoder_is_pch_edp(&encoder->base))
5354                                 is_cpu_edp = true;
5355                         break;
5356                 }
5357
5358                 num_connectors++;
5359         }
5360
5361         /* We are not sure yet this won't happen. */
5362         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5363              INTEL_PCH_TYPE(dev));
5364
5365         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5366              num_connectors, pipe_name(pipe));
5367
5368         WARN_ON(I915_READ(PIPECONF(pipe)) &
5369                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5370
5371         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5372
5373         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5374                 return -EINVAL;
5375
5376         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5377                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5378                                              &has_reduced_clock,
5379                                              &reduced_clock);
5380                 if (!ok) {
5381                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5382                         return -EINVAL;
5383                 }
5384         }
5385
5386         /* Ensure that the cursor is valid for the new mode before changing... */
5387         intel_crtc_update_cursor(crtc, true);
5388
5389         /* determine panel color depth */
5390         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5391         if (is_lvds && dev_priv->lvds_dither)
5392                 dither = true;
5393
5394         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5395         drm_mode_debug_printmodeline(mode);
5396
5397         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5398                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5399                 if (has_reduced_clock)
5400                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5401                               reduced_clock.m2;
5402
5403                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5404                                              fp);
5405
5406                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5407                  * own on pre-Haswell/LPT generation */
5408                 if (!is_cpu_edp) {
5409                         struct intel_pch_pll *pll;
5410
5411                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5412                         if (pll == NULL) {
5413                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5414                                                  pipe);
5415                                 return -EINVAL;
5416                         }
5417                 } else
5418                         intel_put_pch_pll(intel_crtc);
5419
5420                 /* The LVDS pin pair needs to be on before the DPLLs are
5421                  * enabled.  This is an exception to the general rule that
5422                  * mode_set doesn't turn things on.
5423                  */
5424                 if (is_lvds) {
5425                         temp = I915_READ(PCH_LVDS);
5426                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5427                         if (HAS_PCH_CPT(dev)) {
5428                                 temp &= ~PORT_TRANS_SEL_MASK;
5429                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5430                         } else {
5431                                 if (pipe == 1)
5432                                         temp |= LVDS_PIPEB_SELECT;
5433                                 else
5434                                         temp &= ~LVDS_PIPEB_SELECT;
5435                         }
5436
5437                         /* set the corresponsding LVDS_BORDER bit */
5438                         temp |= dev_priv->lvds_border_bits;
5439                         /* Set the B0-B3 data pairs corresponding to whether
5440                          * we're going to set the DPLLs for dual-channel mode or
5441                          * not.
5442                          */
5443                         if (clock.p2 == 7)
5444                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5445                         else
5446                                 temp &= ~(LVDS_B0B3_POWER_UP |
5447                                           LVDS_CLKB_POWER_UP);
5448
5449                         /* It would be nice to set 24 vs 18-bit mode
5450                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5451                          * look more thoroughly into how panels behave in the
5452                          * two modes.
5453                          */
5454                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5455                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5456                                 temp |= LVDS_HSYNC_POLARITY;
5457                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5458                                 temp |= LVDS_VSYNC_POLARITY;
5459                         I915_WRITE(PCH_LVDS, temp);
5460                 }
5461         }
5462
5463         if (is_dp && !is_cpu_edp) {
5464                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5465         } else {
5466                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5467                         /* For non-DP output, clear any trans DP clock recovery
5468                          * setting.*/
5469                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5470                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5471                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5472                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5473                 }
5474         }
5475
5476         intel_crtc->lowfreq_avail = false;
5477         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5478                 if (intel_crtc->pch_pll) {
5479                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5480
5481                         /* Wait for the clocks to stabilize. */
5482                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5483                         udelay(150);
5484
5485                         /* The pixel multiplier can only be updated once the
5486                          * DPLL is enabled and the clocks are stable.
5487                          *
5488                          * So write it again.
5489                          */
5490                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5491                 }
5492
5493                 if (intel_crtc->pch_pll) {
5494                         if (is_lvds && has_reduced_clock && i915_powersave) {
5495                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5496                                 intel_crtc->lowfreq_avail = true;
5497                         } else {
5498                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5499                         }
5500                 }
5501         }
5502
5503         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5504
5505         if (!is_dp || is_cpu_edp)
5506                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5507
5508         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5509                 if (is_cpu_edp)
5510                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5511
5512         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5513
5514         /* Set up the display plane register */
5515         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5516         POSTING_READ(DSPCNTR(plane));
5517
5518         ret = intel_pipe_set_base(crtc, x, y, fb);
5519
5520         intel_update_watermarks(dev);
5521
5522         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5523
5524         return ret;
5525 }
5526
5527 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5528                                struct drm_display_mode *mode,
5529                                struct drm_display_mode *adjusted_mode,
5530                                int x, int y,
5531                                struct drm_framebuffer *fb)
5532 {
5533         struct drm_device *dev = crtc->dev;
5534         struct drm_i915_private *dev_priv = dev->dev_private;
5535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536         int pipe = intel_crtc->pipe;
5537         int ret;
5538
5539         drm_vblank_pre_modeset(dev, pipe);
5540
5541         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5542                                               x, y, fb);
5543         drm_vblank_post_modeset(dev, pipe);
5544
5545         return ret;
5546 }
5547
5548 static bool intel_eld_uptodate(struct drm_connector *connector,
5549                                int reg_eldv, uint32_t bits_eldv,
5550                                int reg_elda, uint32_t bits_elda,
5551                                int reg_edid)
5552 {
5553         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5554         uint8_t *eld = connector->eld;
5555         uint32_t i;
5556
5557         i = I915_READ(reg_eldv);
5558         i &= bits_eldv;
5559
5560         if (!eld[0])
5561                 return !i;
5562
5563         if (!i)
5564                 return false;
5565
5566         i = I915_READ(reg_elda);
5567         i &= ~bits_elda;
5568         I915_WRITE(reg_elda, i);
5569
5570         for (i = 0; i < eld[2]; i++)
5571                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5572                         return false;
5573
5574         return true;
5575 }
5576
5577 static void g4x_write_eld(struct drm_connector *connector,
5578                           struct drm_crtc *crtc)
5579 {
5580         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5581         uint8_t *eld = connector->eld;
5582         uint32_t eldv;
5583         uint32_t len;
5584         uint32_t i;
5585
5586         i = I915_READ(G4X_AUD_VID_DID);
5587
5588         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5589                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5590         else
5591                 eldv = G4X_ELDV_DEVCTG;
5592
5593         if (intel_eld_uptodate(connector,
5594                                G4X_AUD_CNTL_ST, eldv,
5595                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5596                                G4X_HDMIW_HDMIEDID))
5597                 return;
5598
5599         i = I915_READ(G4X_AUD_CNTL_ST);
5600         i &= ~(eldv | G4X_ELD_ADDR);
5601         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5602         I915_WRITE(G4X_AUD_CNTL_ST, i);
5603
5604         if (!eld[0])
5605                 return;
5606
5607         len = min_t(uint8_t, eld[2], len);
5608         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5609         for (i = 0; i < len; i++)
5610                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5611
5612         i = I915_READ(G4X_AUD_CNTL_ST);
5613         i |= eldv;
5614         I915_WRITE(G4X_AUD_CNTL_ST, i);
5615 }
5616
5617 static void haswell_write_eld(struct drm_connector *connector,
5618                                      struct drm_crtc *crtc)
5619 {
5620         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5621         uint8_t *eld = connector->eld;
5622         struct drm_device *dev = crtc->dev;
5623         uint32_t eldv;
5624         uint32_t i;
5625         int len;
5626         int pipe = to_intel_crtc(crtc)->pipe;
5627         int tmp;
5628
5629         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5630         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5631         int aud_config = HSW_AUD_CFG(pipe);
5632         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5633
5634
5635         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5636
5637         /* Audio output enable */
5638         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5639         tmp = I915_READ(aud_cntrl_st2);
5640         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5641         I915_WRITE(aud_cntrl_st2, tmp);
5642
5643         /* Wait for 1 vertical blank */
5644         intel_wait_for_vblank(dev, pipe);
5645
5646         /* Set ELD valid state */
5647         tmp = I915_READ(aud_cntrl_st2);
5648         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5649         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5650         I915_WRITE(aud_cntrl_st2, tmp);
5651         tmp = I915_READ(aud_cntrl_st2);
5652         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5653
5654         /* Enable HDMI mode */
5655         tmp = I915_READ(aud_config);
5656         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5657         /* clear N_programing_enable and N_value_index */
5658         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5659         I915_WRITE(aud_config, tmp);
5660
5661         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5662
5663         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5664
5665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5666                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5667                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5668                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5669         } else
5670                 I915_WRITE(aud_config, 0);
5671
5672         if (intel_eld_uptodate(connector,
5673                                aud_cntrl_st2, eldv,
5674                                aud_cntl_st, IBX_ELD_ADDRESS,
5675                                hdmiw_hdmiedid))
5676                 return;
5677
5678         i = I915_READ(aud_cntrl_st2);
5679         i &= ~eldv;
5680         I915_WRITE(aud_cntrl_st2, i);
5681
5682         if (!eld[0])
5683                 return;
5684
5685         i = I915_READ(aud_cntl_st);
5686         i &= ~IBX_ELD_ADDRESS;
5687         I915_WRITE(aud_cntl_st, i);
5688         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5689         DRM_DEBUG_DRIVER("port num:%d\n", i);
5690
5691         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5692         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5693         for (i = 0; i < len; i++)
5694                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5695
5696         i = I915_READ(aud_cntrl_st2);
5697         i |= eldv;
5698         I915_WRITE(aud_cntrl_st2, i);
5699
5700 }
5701
5702 static void ironlake_write_eld(struct drm_connector *connector,
5703                                      struct drm_crtc *crtc)
5704 {
5705         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5706         uint8_t *eld = connector->eld;
5707         uint32_t eldv;
5708         uint32_t i;
5709         int len;
5710         int hdmiw_hdmiedid;
5711         int aud_config;
5712         int aud_cntl_st;
5713         int aud_cntrl_st2;
5714         int pipe = to_intel_crtc(crtc)->pipe;
5715
5716         if (HAS_PCH_IBX(connector->dev)) {
5717                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5718                 aud_config = IBX_AUD_CFG(pipe);
5719                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5720                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5721         } else {
5722                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5723                 aud_config = CPT_AUD_CFG(pipe);
5724                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5725                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5726         }
5727
5728         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5729
5730         i = I915_READ(aud_cntl_st);
5731         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5732         if (!i) {
5733                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5734                 /* operate blindly on all ports */
5735                 eldv = IBX_ELD_VALIDB;
5736                 eldv |= IBX_ELD_VALIDB << 4;
5737                 eldv |= IBX_ELD_VALIDB << 8;
5738         } else {
5739                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5740                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5741         }
5742
5743         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5744                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5745                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5746                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5747         } else
5748                 I915_WRITE(aud_config, 0);
5749
5750         if (intel_eld_uptodate(connector,
5751                                aud_cntrl_st2, eldv,
5752                                aud_cntl_st, IBX_ELD_ADDRESS,
5753                                hdmiw_hdmiedid))
5754                 return;
5755
5756         i = I915_READ(aud_cntrl_st2);
5757         i &= ~eldv;
5758         I915_WRITE(aud_cntrl_st2, i);
5759
5760         if (!eld[0])
5761                 return;
5762
5763         i = I915_READ(aud_cntl_st);
5764         i &= ~IBX_ELD_ADDRESS;
5765         I915_WRITE(aud_cntl_st, i);
5766
5767         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5768         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5769         for (i = 0; i < len; i++)
5770                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5771
5772         i = I915_READ(aud_cntrl_st2);
5773         i |= eldv;
5774         I915_WRITE(aud_cntrl_st2, i);
5775 }
5776
5777 void intel_write_eld(struct drm_encoder *encoder,
5778                      struct drm_display_mode *mode)
5779 {
5780         struct drm_crtc *crtc = encoder->crtc;
5781         struct drm_connector *connector;
5782         struct drm_device *dev = encoder->dev;
5783         struct drm_i915_private *dev_priv = dev->dev_private;
5784
5785         connector = drm_select_eld(encoder, mode);
5786         if (!connector)
5787                 return;
5788
5789         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5790                          connector->base.id,
5791                          drm_get_connector_name(connector),
5792                          connector->encoder->base.id,
5793                          drm_get_encoder_name(connector->encoder));
5794
5795         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5796
5797         if (dev_priv->display.write_eld)
5798                 dev_priv->display.write_eld(connector, crtc);
5799 }
5800
5801 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5802 void intel_crtc_load_lut(struct drm_crtc *crtc)
5803 {
5804         struct drm_device *dev = crtc->dev;
5805         struct drm_i915_private *dev_priv = dev->dev_private;
5806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5807         int palreg = PALETTE(intel_crtc->pipe);
5808         int i;
5809
5810         /* The clocks have to be on to load the palette. */
5811         if (!crtc->enabled || !intel_crtc->active)
5812                 return;
5813
5814         /* use legacy palette for Ironlake */
5815         if (HAS_PCH_SPLIT(dev))
5816                 palreg = LGC_PALETTE(intel_crtc->pipe);
5817
5818         for (i = 0; i < 256; i++) {
5819                 I915_WRITE(palreg + 4 * i,
5820                            (intel_crtc->lut_r[i] << 16) |
5821                            (intel_crtc->lut_g[i] << 8) |
5822                            intel_crtc->lut_b[i]);
5823         }
5824 }
5825
5826 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5827 {
5828         struct drm_device *dev = crtc->dev;
5829         struct drm_i915_private *dev_priv = dev->dev_private;
5830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5831         bool visible = base != 0;
5832         u32 cntl;
5833
5834         if (intel_crtc->cursor_visible == visible)
5835                 return;
5836
5837         cntl = I915_READ(_CURACNTR);
5838         if (visible) {
5839                 /* On these chipsets we can only modify the base whilst
5840                  * the cursor is disabled.
5841                  */
5842                 I915_WRITE(_CURABASE, base);
5843
5844                 cntl &= ~(CURSOR_FORMAT_MASK);
5845                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5846                 cntl |= CURSOR_ENABLE |
5847                         CURSOR_GAMMA_ENABLE |
5848                         CURSOR_FORMAT_ARGB;
5849         } else
5850                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5851         I915_WRITE(_CURACNTR, cntl);
5852
5853         intel_crtc->cursor_visible = visible;
5854 }
5855
5856 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5857 {
5858         struct drm_device *dev = crtc->dev;
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5861         int pipe = intel_crtc->pipe;
5862         bool visible = base != 0;
5863
5864         if (intel_crtc->cursor_visible != visible) {
5865                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5866                 if (base) {
5867                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5868                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5869                         cntl |= pipe << 28; /* Connect to correct pipe */
5870                 } else {
5871                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5872                         cntl |= CURSOR_MODE_DISABLE;
5873                 }
5874                 I915_WRITE(CURCNTR(pipe), cntl);
5875
5876                 intel_crtc->cursor_visible = visible;
5877         }
5878         /* and commit changes on next vblank */
5879         I915_WRITE(CURBASE(pipe), base);
5880 }
5881
5882 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5883 {
5884         struct drm_device *dev = crtc->dev;
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5887         int pipe = intel_crtc->pipe;
5888         bool visible = base != 0;
5889
5890         if (intel_crtc->cursor_visible != visible) {
5891                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5892                 if (base) {
5893                         cntl &= ~CURSOR_MODE;
5894                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5895                 } else {
5896                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5897                         cntl |= CURSOR_MODE_DISABLE;
5898                 }
5899                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5900
5901                 intel_crtc->cursor_visible = visible;
5902         }
5903         /* and commit changes on next vblank */
5904         I915_WRITE(CURBASE_IVB(pipe), base);
5905 }
5906
5907 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5908 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5909                                      bool on)
5910 {
5911         struct drm_device *dev = crtc->dev;
5912         struct drm_i915_private *dev_priv = dev->dev_private;
5913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5914         int pipe = intel_crtc->pipe;
5915         int x = intel_crtc->cursor_x;
5916         int y = intel_crtc->cursor_y;
5917         u32 base, pos;
5918         bool visible;
5919
5920         pos = 0;
5921
5922         if (on && crtc->enabled && crtc->fb) {
5923                 base = intel_crtc->cursor_addr;
5924                 if (x > (int) crtc->fb->width)
5925                         base = 0;
5926
5927                 if (y > (int) crtc->fb->height)
5928                         base = 0;
5929         } else
5930                 base = 0;
5931
5932         if (x < 0) {
5933                 if (x + intel_crtc->cursor_width < 0)
5934                         base = 0;
5935
5936                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5937                 x = -x;
5938         }
5939         pos |= x << CURSOR_X_SHIFT;
5940
5941         if (y < 0) {
5942                 if (y + intel_crtc->cursor_height < 0)
5943                         base = 0;
5944
5945                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5946                 y = -y;
5947         }
5948         pos |= y << CURSOR_Y_SHIFT;
5949
5950         visible = base != 0;
5951         if (!visible && !intel_crtc->cursor_visible)
5952                 return;
5953
5954         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5955                 I915_WRITE(CURPOS_IVB(pipe), pos);
5956                 ivb_update_cursor(crtc, base);
5957         } else {
5958                 I915_WRITE(CURPOS(pipe), pos);
5959                 if (IS_845G(dev) || IS_I865G(dev))
5960                         i845_update_cursor(crtc, base);
5961                 else
5962                         i9xx_update_cursor(crtc, base);
5963         }
5964 }
5965
5966 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5967                                  struct drm_file *file,
5968                                  uint32_t handle,
5969                                  uint32_t width, uint32_t height)
5970 {
5971         struct drm_device *dev = crtc->dev;
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5974         struct drm_i915_gem_object *obj;
5975         uint32_t addr;
5976         int ret;
5977
5978         /* if we want to turn off the cursor ignore width and height */
5979         if (!handle) {
5980                 DRM_DEBUG_KMS("cursor off\n");
5981                 addr = 0;
5982                 obj = NULL;
5983                 mutex_lock(&dev->struct_mutex);
5984                 goto finish;
5985         }
5986
5987         /* Currently we only support 64x64 cursors */
5988         if (width != 64 || height != 64) {
5989                 DRM_ERROR("we currently only support 64x64 cursors\n");
5990                 return -EINVAL;
5991         }
5992
5993         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5994         if (&obj->base == NULL)
5995                 return -ENOENT;
5996
5997         if (obj->base.size < width * height * 4) {
5998                 DRM_ERROR("buffer is to small\n");
5999                 ret = -ENOMEM;
6000                 goto fail;
6001         }
6002
6003         /* we only need to pin inside GTT if cursor is non-phy */
6004         mutex_lock(&dev->struct_mutex);
6005         if (!dev_priv->info->cursor_needs_physical) {
6006                 if (obj->tiling_mode) {
6007                         DRM_ERROR("cursor cannot be tiled\n");
6008                         ret = -EINVAL;
6009                         goto fail_locked;
6010                 }
6011
6012                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6013                 if (ret) {
6014                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6015                         goto fail_locked;
6016                 }
6017
6018                 ret = i915_gem_object_put_fence(obj);
6019                 if (ret) {
6020                         DRM_ERROR("failed to release fence for cursor");
6021                         goto fail_unpin;
6022                 }
6023
6024                 addr = obj->gtt_offset;
6025         } else {
6026                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6027                 ret = i915_gem_attach_phys_object(dev, obj,
6028                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6029                                                   align);
6030                 if (ret) {
6031                         DRM_ERROR("failed to attach phys object\n");
6032                         goto fail_locked;
6033                 }
6034                 addr = obj->phys_obj->handle->busaddr;
6035         }
6036
6037         if (IS_GEN2(dev))
6038                 I915_WRITE(CURSIZE, (height << 12) | width);
6039
6040  finish:
6041         if (intel_crtc->cursor_bo) {
6042                 if (dev_priv->info->cursor_needs_physical) {
6043                         if (intel_crtc->cursor_bo != obj)
6044                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6045                 } else
6046                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6047                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6048         }
6049
6050         mutex_unlock(&dev->struct_mutex);
6051
6052         intel_crtc->cursor_addr = addr;
6053         intel_crtc->cursor_bo = obj;
6054         intel_crtc->cursor_width = width;
6055         intel_crtc->cursor_height = height;
6056
6057         intel_crtc_update_cursor(crtc, true);
6058
6059         return 0;
6060 fail_unpin:
6061         i915_gem_object_unpin(obj);
6062 fail_locked:
6063         mutex_unlock(&dev->struct_mutex);
6064 fail:
6065         drm_gem_object_unreference_unlocked(&obj->base);
6066         return ret;
6067 }
6068
6069 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6070 {
6071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072
6073         intel_crtc->cursor_x = x;
6074         intel_crtc->cursor_y = y;
6075
6076         intel_crtc_update_cursor(crtc, true);
6077
6078         return 0;
6079 }
6080
6081 /** Sets the color ramps on behalf of RandR */
6082 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6083                                  u16 blue, int regno)
6084 {
6085         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6086
6087         intel_crtc->lut_r[regno] = red >> 8;
6088         intel_crtc->lut_g[regno] = green >> 8;
6089         intel_crtc->lut_b[regno] = blue >> 8;
6090 }
6091
6092 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6093                              u16 *blue, int regno)
6094 {
6095         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096
6097         *red = intel_crtc->lut_r[regno] << 8;
6098         *green = intel_crtc->lut_g[regno] << 8;
6099         *blue = intel_crtc->lut_b[regno] << 8;
6100 }
6101
6102 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6103                                  u16 *blue, uint32_t start, uint32_t size)
6104 {
6105         int end = (start + size > 256) ? 256 : start + size, i;
6106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6107
6108         for (i = start; i < end; i++) {
6109                 intel_crtc->lut_r[i] = red[i] >> 8;
6110                 intel_crtc->lut_g[i] = green[i] >> 8;
6111                 intel_crtc->lut_b[i] = blue[i] >> 8;
6112         }
6113
6114         intel_crtc_load_lut(crtc);
6115 }
6116
6117 /**
6118  * Get a pipe with a simple mode set on it for doing load-based monitor
6119  * detection.
6120  *
6121  * It will be up to the load-detect code to adjust the pipe as appropriate for
6122  * its requirements.  The pipe will be connected to no other encoders.
6123  *
6124  * Currently this code will only succeed if there is a pipe with no encoders
6125  * configured for it.  In the future, it could choose to temporarily disable
6126  * some outputs to free up a pipe for its use.
6127  *
6128  * \return crtc, or NULL if no pipes are available.
6129  */
6130
6131 /* VESA 640x480x72Hz mode to set on the pipe */
6132 static struct drm_display_mode load_detect_mode = {
6133         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6134                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6135 };
6136
6137 static struct drm_framebuffer *
6138 intel_framebuffer_create(struct drm_device *dev,
6139                          struct drm_mode_fb_cmd2 *mode_cmd,
6140                          struct drm_i915_gem_object *obj)
6141 {
6142         struct intel_framebuffer *intel_fb;
6143         int ret;
6144
6145         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6146         if (!intel_fb) {
6147                 drm_gem_object_unreference_unlocked(&obj->base);
6148                 return ERR_PTR(-ENOMEM);
6149         }
6150
6151         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6152         if (ret) {
6153                 drm_gem_object_unreference_unlocked(&obj->base);
6154                 kfree(intel_fb);
6155                 return ERR_PTR(ret);
6156         }
6157
6158         return &intel_fb->base;
6159 }
6160
6161 static u32
6162 intel_framebuffer_pitch_for_width(int width, int bpp)
6163 {
6164         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6165         return ALIGN(pitch, 64);
6166 }
6167
6168 static u32
6169 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6170 {
6171         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6172         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6173 }
6174
6175 static struct drm_framebuffer *
6176 intel_framebuffer_create_for_mode(struct drm_device *dev,
6177                                   struct drm_display_mode *mode,
6178                                   int depth, int bpp)
6179 {
6180         struct drm_i915_gem_object *obj;
6181         struct drm_mode_fb_cmd2 mode_cmd;
6182
6183         obj = i915_gem_alloc_object(dev,
6184                                     intel_framebuffer_size_for_mode(mode, bpp));
6185         if (obj == NULL)
6186                 return ERR_PTR(-ENOMEM);
6187
6188         mode_cmd.width = mode->hdisplay;
6189         mode_cmd.height = mode->vdisplay;
6190         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6191                                                                 bpp);
6192         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6193
6194         return intel_framebuffer_create(dev, &mode_cmd, obj);
6195 }
6196
6197 static struct drm_framebuffer *
6198 mode_fits_in_fbdev(struct drm_device *dev,
6199                    struct drm_display_mode *mode)
6200 {
6201         struct drm_i915_private *dev_priv = dev->dev_private;
6202         struct drm_i915_gem_object *obj;
6203         struct drm_framebuffer *fb;
6204
6205         if (dev_priv->fbdev == NULL)
6206                 return NULL;
6207
6208         obj = dev_priv->fbdev->ifb.obj;
6209         if (obj == NULL)
6210                 return NULL;
6211
6212         fb = &dev_priv->fbdev->ifb.base;
6213         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6214                                                                fb->bits_per_pixel))
6215                 return NULL;
6216
6217         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6218                 return NULL;
6219
6220         return fb;
6221 }
6222
6223 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6224                                 struct drm_display_mode *mode,
6225                                 struct intel_load_detect_pipe *old)
6226 {
6227         struct intel_crtc *intel_crtc;
6228         struct intel_encoder *intel_encoder =
6229                 intel_attached_encoder(connector);
6230         struct drm_crtc *possible_crtc;
6231         struct drm_encoder *encoder = &intel_encoder->base;
6232         struct drm_crtc *crtc = NULL;
6233         struct drm_device *dev = encoder->dev;
6234         struct drm_framebuffer *fb;
6235         int i = -1;
6236
6237         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6238                       connector->base.id, drm_get_connector_name(connector),
6239                       encoder->base.id, drm_get_encoder_name(encoder));
6240
6241         /*
6242          * Algorithm gets a little messy:
6243          *
6244          *   - if the connector already has an assigned crtc, use it (but make
6245          *     sure it's on first)
6246          *
6247          *   - try to find the first unused crtc that can drive this connector,
6248          *     and use that if we find one
6249          */
6250
6251         /* See if we already have a CRTC for this connector */
6252         if (encoder->crtc) {
6253                 crtc = encoder->crtc;
6254
6255                 old->dpms_mode = connector->dpms;
6256                 old->load_detect_temp = false;
6257
6258                 /* Make sure the crtc and connector are running */
6259                 if (connector->dpms != DRM_MODE_DPMS_ON)
6260                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6261
6262                 return true;
6263         }
6264
6265         /* Find an unused one (if possible) */
6266         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6267                 i++;
6268                 if (!(encoder->possible_crtcs & (1 << i)))
6269                         continue;
6270                 if (!possible_crtc->enabled) {
6271                         crtc = possible_crtc;
6272                         break;
6273                 }
6274         }
6275
6276         /*
6277          * If we didn't find an unused CRTC, don't use any.
6278          */
6279         if (!crtc) {
6280                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6281                 return false;
6282         }
6283
6284         intel_encoder->new_crtc = to_intel_crtc(crtc);
6285         to_intel_connector(connector)->new_encoder = intel_encoder;
6286
6287         intel_crtc = to_intel_crtc(crtc);
6288         old->dpms_mode = connector->dpms;
6289         old->load_detect_temp = true;
6290         old->release_fb = NULL;
6291
6292         if (!mode)
6293                 mode = &load_detect_mode;
6294
6295         /* We need a framebuffer large enough to accommodate all accesses
6296          * that the plane may generate whilst we perform load detection.
6297          * We can not rely on the fbcon either being present (we get called
6298          * during its initialisation to detect all boot displays, or it may
6299          * not even exist) or that it is large enough to satisfy the
6300          * requested mode.
6301          */
6302         fb = mode_fits_in_fbdev(dev, mode);
6303         if (fb == NULL) {
6304                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6305                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6306                 old->release_fb = fb;
6307         } else
6308                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6309         if (IS_ERR(fb)) {
6310                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6311                 goto fail;
6312         }
6313
6314         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6315                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6316                 if (old->release_fb)
6317                         old->release_fb->funcs->destroy(old->release_fb);
6318                 goto fail;
6319         }
6320
6321         /* let the connector get through one full cycle before testing */
6322         intel_wait_for_vblank(dev, intel_crtc->pipe);
6323
6324         return true;
6325 fail:
6326         connector->encoder = NULL;
6327         encoder->crtc = NULL;
6328         return false;
6329 }
6330
6331 void intel_release_load_detect_pipe(struct drm_connector *connector,
6332                                     struct intel_load_detect_pipe *old)
6333 {
6334         struct intel_encoder *intel_encoder =
6335                 intel_attached_encoder(connector);
6336         struct drm_encoder *encoder = &intel_encoder->base;
6337
6338         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6339                       connector->base.id, drm_get_connector_name(connector),
6340                       encoder->base.id, drm_get_encoder_name(encoder));
6341
6342         if (old->load_detect_temp) {
6343                 struct drm_crtc *crtc = encoder->crtc;
6344
6345                 to_intel_connector(connector)->new_encoder = NULL;
6346                 intel_encoder->new_crtc = NULL;
6347                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6348
6349                 if (old->release_fb)
6350                         old->release_fb->funcs->destroy(old->release_fb);
6351
6352                 return;
6353         }
6354
6355         /* Switch crtc and encoder back off if necessary */
6356         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6357                 connector->funcs->dpms(connector, old->dpms_mode);
6358 }
6359
6360 /* Returns the clock of the currently programmed mode of the given pipe. */
6361 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6362 {
6363         struct drm_i915_private *dev_priv = dev->dev_private;
6364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365         int pipe = intel_crtc->pipe;
6366         u32 dpll = I915_READ(DPLL(pipe));
6367         u32 fp;
6368         intel_clock_t clock;
6369
6370         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6371                 fp = I915_READ(FP0(pipe));
6372         else
6373                 fp = I915_READ(FP1(pipe));
6374
6375         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6376         if (IS_PINEVIEW(dev)) {
6377                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6378                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6379         } else {
6380                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6381                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6382         }
6383
6384         if (!IS_GEN2(dev)) {
6385                 if (IS_PINEVIEW(dev))
6386                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6387                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6388                 else
6389                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6390                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6391
6392                 switch (dpll & DPLL_MODE_MASK) {
6393                 case DPLLB_MODE_DAC_SERIAL:
6394                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6395                                 5 : 10;
6396                         break;
6397                 case DPLLB_MODE_LVDS:
6398                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6399                                 7 : 14;
6400                         break;
6401                 default:
6402                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6403                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6404                         return 0;
6405                 }
6406
6407                 /* XXX: Handle the 100Mhz refclk */
6408                 intel_clock(dev, 96000, &clock);
6409         } else {
6410                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6411
6412                 if (is_lvds) {
6413                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6414                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6415                         clock.p2 = 14;
6416
6417                         if ((dpll & PLL_REF_INPUT_MASK) ==
6418                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6419                                 /* XXX: might not be 66MHz */
6420                                 intel_clock(dev, 66000, &clock);
6421                         } else
6422                                 intel_clock(dev, 48000, &clock);
6423                 } else {
6424                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6425                                 clock.p1 = 2;
6426                         else {
6427                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6428                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6429                         }
6430                         if (dpll & PLL_P2_DIVIDE_BY_4)
6431                                 clock.p2 = 4;
6432                         else
6433                                 clock.p2 = 2;
6434
6435                         intel_clock(dev, 48000, &clock);
6436                 }
6437         }
6438
6439         /* XXX: It would be nice to validate the clocks, but we can't reuse
6440          * i830PllIsValid() because it relies on the xf86_config connector
6441          * configuration being accurate, which it isn't necessarily.
6442          */
6443
6444         return clock.dot;
6445 }
6446
6447 /** Returns the currently programmed mode of the given pipe. */
6448 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6449                                              struct drm_crtc *crtc)
6450 {
6451         struct drm_i915_private *dev_priv = dev->dev_private;
6452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6453         int pipe = intel_crtc->pipe;
6454         struct drm_display_mode *mode;
6455         int htot = I915_READ(HTOTAL(pipe));
6456         int hsync = I915_READ(HSYNC(pipe));
6457         int vtot = I915_READ(VTOTAL(pipe));
6458         int vsync = I915_READ(VSYNC(pipe));
6459
6460         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6461         if (!mode)
6462                 return NULL;
6463
6464         mode->clock = intel_crtc_clock_get(dev, crtc);
6465         mode->hdisplay = (htot & 0xffff) + 1;
6466         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6467         mode->hsync_start = (hsync & 0xffff) + 1;
6468         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6469         mode->vdisplay = (vtot & 0xffff) + 1;
6470         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6471         mode->vsync_start = (vsync & 0xffff) + 1;
6472         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6473
6474         drm_mode_set_name(mode);
6475
6476         return mode;
6477 }
6478
6479 static void intel_increase_pllclock(struct drm_crtc *crtc)
6480 {
6481         struct drm_device *dev = crtc->dev;
6482         drm_i915_private_t *dev_priv = dev->dev_private;
6483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6484         int pipe = intel_crtc->pipe;
6485         int dpll_reg = DPLL(pipe);
6486         int dpll;
6487
6488         if (HAS_PCH_SPLIT(dev))
6489                 return;
6490
6491         if (!dev_priv->lvds_downclock_avail)
6492                 return;
6493
6494         dpll = I915_READ(dpll_reg);
6495         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6496                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6497
6498                 assert_panel_unlocked(dev_priv, pipe);
6499
6500                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6501                 I915_WRITE(dpll_reg, dpll);
6502                 intel_wait_for_vblank(dev, pipe);
6503
6504                 dpll = I915_READ(dpll_reg);
6505                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6506                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6507         }
6508 }
6509
6510 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6511 {
6512         struct drm_device *dev = crtc->dev;
6513         drm_i915_private_t *dev_priv = dev->dev_private;
6514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6515
6516         if (HAS_PCH_SPLIT(dev))
6517                 return;
6518
6519         if (!dev_priv->lvds_downclock_avail)
6520                 return;
6521
6522         /*
6523          * Since this is called by a timer, we should never get here in
6524          * the manual case.
6525          */
6526         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6527                 int pipe = intel_crtc->pipe;
6528                 int dpll_reg = DPLL(pipe);
6529                 int dpll;
6530
6531                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6532
6533                 assert_panel_unlocked(dev_priv, pipe);
6534
6535                 dpll = I915_READ(dpll_reg);
6536                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6537                 I915_WRITE(dpll_reg, dpll);
6538                 intel_wait_for_vblank(dev, pipe);
6539                 dpll = I915_READ(dpll_reg);
6540                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6541                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6542         }
6543
6544 }
6545
6546 void intel_mark_busy(struct drm_device *dev)
6547 {
6548         i915_update_gfx_val(dev->dev_private);
6549 }
6550
6551 void intel_mark_idle(struct drm_device *dev)
6552 {
6553 }
6554
6555 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6556 {
6557         struct drm_device *dev = obj->base.dev;
6558         struct drm_crtc *crtc;
6559
6560         if (!i915_powersave)
6561                 return;
6562
6563         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6564                 if (!crtc->fb)
6565                         continue;
6566
6567                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6568                         intel_increase_pllclock(crtc);
6569         }
6570 }
6571
6572 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6573 {
6574         struct drm_device *dev = obj->base.dev;
6575         struct drm_crtc *crtc;
6576
6577         if (!i915_powersave)
6578                 return;
6579
6580         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6581                 if (!crtc->fb)
6582                         continue;
6583
6584                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6585                         intel_decrease_pllclock(crtc);
6586         }
6587 }
6588
6589 static void intel_crtc_destroy(struct drm_crtc *crtc)
6590 {
6591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6592         struct drm_device *dev = crtc->dev;
6593         struct intel_unpin_work *work;
6594         unsigned long flags;
6595
6596         spin_lock_irqsave(&dev->event_lock, flags);
6597         work = intel_crtc->unpin_work;
6598         intel_crtc->unpin_work = NULL;
6599         spin_unlock_irqrestore(&dev->event_lock, flags);
6600
6601         if (work) {
6602                 cancel_work_sync(&work->work);
6603                 kfree(work);
6604         }
6605
6606         drm_crtc_cleanup(crtc);
6607
6608         kfree(intel_crtc);
6609 }
6610
6611 static void intel_unpin_work_fn(struct work_struct *__work)
6612 {
6613         struct intel_unpin_work *work =
6614                 container_of(__work, struct intel_unpin_work, work);
6615
6616         mutex_lock(&work->dev->struct_mutex);
6617         intel_unpin_fb_obj(work->old_fb_obj);
6618         drm_gem_object_unreference(&work->pending_flip_obj->base);
6619         drm_gem_object_unreference(&work->old_fb_obj->base);
6620
6621         intel_update_fbc(work->dev);
6622         mutex_unlock(&work->dev->struct_mutex);
6623         kfree(work);
6624 }
6625
6626 static void do_intel_finish_page_flip(struct drm_device *dev,
6627                                       struct drm_crtc *crtc)
6628 {
6629         drm_i915_private_t *dev_priv = dev->dev_private;
6630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6631         struct intel_unpin_work *work;
6632         struct drm_i915_gem_object *obj;
6633         struct drm_pending_vblank_event *e;
6634         struct timeval tvbl;
6635         unsigned long flags;
6636
6637         /* Ignore early vblank irqs */
6638         if (intel_crtc == NULL)
6639                 return;
6640
6641         spin_lock_irqsave(&dev->event_lock, flags);
6642         work = intel_crtc->unpin_work;
6643         if (work == NULL || !work->pending) {
6644                 spin_unlock_irqrestore(&dev->event_lock, flags);
6645                 return;
6646         }
6647
6648         intel_crtc->unpin_work = NULL;
6649
6650         if (work->event) {
6651                 e = work->event;
6652                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6653
6654                 e->event.tv_sec = tvbl.tv_sec;
6655                 e->event.tv_usec = tvbl.tv_usec;
6656
6657                 list_add_tail(&e->base.link,
6658                               &e->base.file_priv->event_list);
6659                 wake_up_interruptible(&e->base.file_priv->event_wait);
6660         }
6661
6662         drm_vblank_put(dev, intel_crtc->pipe);
6663
6664         spin_unlock_irqrestore(&dev->event_lock, flags);
6665
6666         obj = work->old_fb_obj;
6667
6668         atomic_clear_mask(1 << intel_crtc->plane,
6669                           &obj->pending_flip.counter);
6670
6671         wake_up(&dev_priv->pending_flip_queue);
6672         schedule_work(&work->work);
6673
6674         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6675 }
6676
6677 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6678 {
6679         drm_i915_private_t *dev_priv = dev->dev_private;
6680         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6681
6682         do_intel_finish_page_flip(dev, crtc);
6683 }
6684
6685 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6686 {
6687         drm_i915_private_t *dev_priv = dev->dev_private;
6688         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6689
6690         do_intel_finish_page_flip(dev, crtc);
6691 }
6692
6693 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6694 {
6695         drm_i915_private_t *dev_priv = dev->dev_private;
6696         struct intel_crtc *intel_crtc =
6697                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6698         unsigned long flags;
6699
6700         spin_lock_irqsave(&dev->event_lock, flags);
6701         if (intel_crtc->unpin_work) {
6702                 if ((++intel_crtc->unpin_work->pending) > 1)
6703                         DRM_ERROR("Prepared flip multiple times\n");
6704         } else {
6705                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6706         }
6707         spin_unlock_irqrestore(&dev->event_lock, flags);
6708 }
6709
6710 static int intel_gen2_queue_flip(struct drm_device *dev,
6711                                  struct drm_crtc *crtc,
6712                                  struct drm_framebuffer *fb,
6713                                  struct drm_i915_gem_object *obj)
6714 {
6715         struct drm_i915_private *dev_priv = dev->dev_private;
6716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6717         u32 flip_mask;
6718         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6719         int ret;
6720
6721         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6722         if (ret)
6723                 goto err;
6724
6725         ret = intel_ring_begin(ring, 6);
6726         if (ret)
6727                 goto err_unpin;
6728
6729         /* Can't queue multiple flips, so wait for the previous
6730          * one to finish before executing the next.
6731          */
6732         if (intel_crtc->plane)
6733                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6734         else
6735                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6736         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6737         intel_ring_emit(ring, MI_NOOP);
6738         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6739                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6740         intel_ring_emit(ring, fb->pitches[0]);
6741         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6742         intel_ring_emit(ring, 0); /* aux display base address, unused */
6743         intel_ring_advance(ring);
6744         return 0;
6745
6746 err_unpin:
6747         intel_unpin_fb_obj(obj);
6748 err:
6749         return ret;
6750 }
6751
6752 static int intel_gen3_queue_flip(struct drm_device *dev,
6753                                  struct drm_crtc *crtc,
6754                                  struct drm_framebuffer *fb,
6755                                  struct drm_i915_gem_object *obj)
6756 {
6757         struct drm_i915_private *dev_priv = dev->dev_private;
6758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759         u32 flip_mask;
6760         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6761         int ret;
6762
6763         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6764         if (ret)
6765                 goto err;
6766
6767         ret = intel_ring_begin(ring, 6);
6768         if (ret)
6769                 goto err_unpin;
6770
6771         if (intel_crtc->plane)
6772                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6773         else
6774                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6775         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6776         intel_ring_emit(ring, MI_NOOP);
6777         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6778                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6779         intel_ring_emit(ring, fb->pitches[0]);
6780         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6781         intel_ring_emit(ring, MI_NOOP);
6782
6783         intel_ring_advance(ring);
6784         return 0;
6785
6786 err_unpin:
6787         intel_unpin_fb_obj(obj);
6788 err:
6789         return ret;
6790 }
6791
6792 static int intel_gen4_queue_flip(struct drm_device *dev,
6793                                  struct drm_crtc *crtc,
6794                                  struct drm_framebuffer *fb,
6795                                  struct drm_i915_gem_object *obj)
6796 {
6797         struct drm_i915_private *dev_priv = dev->dev_private;
6798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799         uint32_t pf, pipesrc;
6800         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6801         int ret;
6802
6803         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6804         if (ret)
6805                 goto err;
6806
6807         ret = intel_ring_begin(ring, 4);
6808         if (ret)
6809                 goto err_unpin;
6810
6811         /* i965+ uses the linear or tiled offsets from the
6812          * Display Registers (which do not change across a page-flip)
6813          * so we need only reprogram the base address.
6814          */
6815         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6816                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6817         intel_ring_emit(ring, fb->pitches[0]);
6818         intel_ring_emit(ring,
6819                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6820                         obj->tiling_mode);
6821
6822         /* XXX Enabling the panel-fitter across page-flip is so far
6823          * untested on non-native modes, so ignore it for now.
6824          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6825          */
6826         pf = 0;
6827         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6828         intel_ring_emit(ring, pf | pipesrc);
6829         intel_ring_advance(ring);
6830         return 0;
6831
6832 err_unpin:
6833         intel_unpin_fb_obj(obj);
6834 err:
6835         return ret;
6836 }
6837
6838 static int intel_gen6_queue_flip(struct drm_device *dev,
6839                                  struct drm_crtc *crtc,
6840                                  struct drm_framebuffer *fb,
6841                                  struct drm_i915_gem_object *obj)
6842 {
6843         struct drm_i915_private *dev_priv = dev->dev_private;
6844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6845         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6846         uint32_t pf, pipesrc;
6847         int ret;
6848
6849         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6850         if (ret)
6851                 goto err;
6852
6853         ret = intel_ring_begin(ring, 4);
6854         if (ret)
6855                 goto err_unpin;
6856
6857         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6858                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6859         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6860         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6861
6862         /* Contrary to the suggestions in the documentation,
6863          * "Enable Panel Fitter" does not seem to be required when page
6864          * flipping with a non-native mode, and worse causes a normal
6865          * modeset to fail.
6866          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6867          */
6868         pf = 0;
6869         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6870         intel_ring_emit(ring, pf | pipesrc);
6871         intel_ring_advance(ring);
6872         return 0;
6873
6874 err_unpin:
6875         intel_unpin_fb_obj(obj);
6876 err:
6877         return ret;
6878 }
6879
6880 /*
6881  * On gen7 we currently use the blit ring because (in early silicon at least)
6882  * the render ring doesn't give us interrpts for page flip completion, which
6883  * means clients will hang after the first flip is queued.  Fortunately the
6884  * blit ring generates interrupts properly, so use it instead.
6885  */
6886 static int intel_gen7_queue_flip(struct drm_device *dev,
6887                                  struct drm_crtc *crtc,
6888                                  struct drm_framebuffer *fb,
6889                                  struct drm_i915_gem_object *obj)
6890 {
6891         struct drm_i915_private *dev_priv = dev->dev_private;
6892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6893         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6894         uint32_t plane_bit = 0;
6895         int ret;
6896
6897         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6898         if (ret)
6899                 goto err;
6900
6901         switch(intel_crtc->plane) {
6902         case PLANE_A:
6903                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6904                 break;
6905         case PLANE_B:
6906                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6907                 break;
6908         case PLANE_C:
6909                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6910                 break;
6911         default:
6912                 WARN_ONCE(1, "unknown plane in flip command\n");
6913                 ret = -ENODEV;
6914                 goto err_unpin;
6915         }
6916
6917         ret = intel_ring_begin(ring, 4);
6918         if (ret)
6919                 goto err_unpin;
6920
6921         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6922         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6923         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6924         intel_ring_emit(ring, (MI_NOOP));
6925         intel_ring_advance(ring);
6926         return 0;
6927
6928 err_unpin:
6929         intel_unpin_fb_obj(obj);
6930 err:
6931         return ret;
6932 }
6933
6934 static int intel_default_queue_flip(struct drm_device *dev,
6935                                     struct drm_crtc *crtc,
6936                                     struct drm_framebuffer *fb,
6937                                     struct drm_i915_gem_object *obj)
6938 {
6939         return -ENODEV;
6940 }
6941
6942 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6943                                 struct drm_framebuffer *fb,
6944                                 struct drm_pending_vblank_event *event)
6945 {
6946         struct drm_device *dev = crtc->dev;
6947         struct drm_i915_private *dev_priv = dev->dev_private;
6948         struct intel_framebuffer *intel_fb;
6949         struct drm_i915_gem_object *obj;
6950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951         struct intel_unpin_work *work;
6952         unsigned long flags;
6953         int ret;
6954
6955         /* Can't change pixel format via MI display flips. */
6956         if (fb->pixel_format != crtc->fb->pixel_format)
6957                 return -EINVAL;
6958
6959         /*
6960          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6961          * Note that pitch changes could also affect these register.
6962          */
6963         if (INTEL_INFO(dev)->gen > 3 &&
6964             (fb->offsets[0] != crtc->fb->offsets[0] ||
6965              fb->pitches[0] != crtc->fb->pitches[0]))
6966                 return -EINVAL;
6967
6968         work = kzalloc(sizeof *work, GFP_KERNEL);
6969         if (work == NULL)
6970                 return -ENOMEM;
6971
6972         work->event = event;
6973         work->dev = crtc->dev;
6974         intel_fb = to_intel_framebuffer(crtc->fb);
6975         work->old_fb_obj = intel_fb->obj;
6976         INIT_WORK(&work->work, intel_unpin_work_fn);
6977
6978         ret = drm_vblank_get(dev, intel_crtc->pipe);
6979         if (ret)
6980                 goto free_work;
6981
6982         /* We borrow the event spin lock for protecting unpin_work */
6983         spin_lock_irqsave(&dev->event_lock, flags);
6984         if (intel_crtc->unpin_work) {
6985                 spin_unlock_irqrestore(&dev->event_lock, flags);
6986                 kfree(work);
6987                 drm_vblank_put(dev, intel_crtc->pipe);
6988
6989                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6990                 return -EBUSY;
6991         }
6992         intel_crtc->unpin_work = work;
6993         spin_unlock_irqrestore(&dev->event_lock, flags);
6994
6995         intel_fb = to_intel_framebuffer(fb);
6996         obj = intel_fb->obj;
6997
6998         ret = i915_mutex_lock_interruptible(dev);
6999         if (ret)
7000                 goto cleanup;
7001
7002         /* Reference the objects for the scheduled work. */
7003         drm_gem_object_reference(&work->old_fb_obj->base);
7004         drm_gem_object_reference(&obj->base);
7005
7006         crtc->fb = fb;
7007
7008         work->pending_flip_obj = obj;
7009
7010         work->enable_stall_check = true;
7011
7012         /* Block clients from rendering to the new back buffer until
7013          * the flip occurs and the object is no longer visible.
7014          */
7015         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7016
7017         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7018         if (ret)
7019                 goto cleanup_pending;
7020
7021         intel_disable_fbc(dev);
7022         intel_mark_fb_busy(obj);
7023         mutex_unlock(&dev->struct_mutex);
7024
7025         trace_i915_flip_request(intel_crtc->plane, obj);
7026
7027         return 0;
7028
7029 cleanup_pending:
7030         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7031         drm_gem_object_unreference(&work->old_fb_obj->base);
7032         drm_gem_object_unreference(&obj->base);
7033         mutex_unlock(&dev->struct_mutex);
7034
7035 cleanup:
7036         spin_lock_irqsave(&dev->event_lock, flags);
7037         intel_crtc->unpin_work = NULL;
7038         spin_unlock_irqrestore(&dev->event_lock, flags);
7039
7040         drm_vblank_put(dev, intel_crtc->pipe);
7041 free_work:
7042         kfree(work);
7043
7044         return ret;
7045 }
7046
7047 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7048         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7049         .load_lut = intel_crtc_load_lut,
7050         .disable = intel_crtc_noop,
7051 };
7052
7053 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7054 {
7055         struct intel_encoder *other_encoder;
7056         struct drm_crtc *crtc = &encoder->new_crtc->base;
7057
7058         if (WARN_ON(!crtc))
7059                 return false;
7060
7061         list_for_each_entry(other_encoder,
7062                             &crtc->dev->mode_config.encoder_list,
7063                             base.head) {
7064
7065                 if (&other_encoder->new_crtc->base != crtc ||
7066                     encoder == other_encoder)
7067                         continue;
7068                 else
7069                         return true;
7070         }
7071
7072         return false;
7073 }
7074
7075 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7076                                   struct drm_crtc *crtc)
7077 {
7078         struct drm_device *dev;
7079         struct drm_crtc *tmp;
7080         int crtc_mask = 1;
7081
7082         WARN(!crtc, "checking null crtc?\n");
7083
7084         dev = crtc->dev;
7085
7086         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7087                 if (tmp == crtc)
7088                         break;
7089                 crtc_mask <<= 1;
7090         }
7091
7092         if (encoder->possible_crtcs & crtc_mask)
7093                 return true;
7094         return false;
7095 }
7096
7097 /**
7098  * intel_modeset_update_staged_output_state
7099  *
7100  * Updates the staged output configuration state, e.g. after we've read out the
7101  * current hw state.
7102  */
7103 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7104 {
7105         struct intel_encoder *encoder;
7106         struct intel_connector *connector;
7107
7108         list_for_each_entry(connector, &dev->mode_config.connector_list,
7109                             base.head) {
7110                 connector->new_encoder =
7111                         to_intel_encoder(connector->base.encoder);
7112         }
7113
7114         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7115                             base.head) {
7116                 encoder->new_crtc =
7117                         to_intel_crtc(encoder->base.crtc);
7118         }
7119 }
7120
7121 /**
7122  * intel_modeset_commit_output_state
7123  *
7124  * This function copies the stage display pipe configuration to the real one.
7125  */
7126 static void intel_modeset_commit_output_state(struct drm_device *dev)
7127 {
7128         struct intel_encoder *encoder;
7129         struct intel_connector *connector;
7130
7131         list_for_each_entry(connector, &dev->mode_config.connector_list,
7132                             base.head) {
7133                 connector->base.encoder = &connector->new_encoder->base;
7134         }
7135
7136         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7137                             base.head) {
7138                 encoder->base.crtc = &encoder->new_crtc->base;
7139         }
7140 }
7141
7142 static struct drm_display_mode *
7143 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7144                             struct drm_display_mode *mode)
7145 {
7146         struct drm_device *dev = crtc->dev;
7147         struct drm_display_mode *adjusted_mode;
7148         struct drm_encoder_helper_funcs *encoder_funcs;
7149         struct intel_encoder *encoder;
7150
7151         adjusted_mode = drm_mode_duplicate(dev, mode);
7152         if (!adjusted_mode)
7153                 return ERR_PTR(-ENOMEM);
7154
7155         /* Pass our mode to the connectors and the CRTC to give them a chance to
7156          * adjust it according to limitations or connector properties, and also
7157          * a chance to reject the mode entirely.
7158          */
7159         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7160                             base.head) {
7161
7162                 if (&encoder->new_crtc->base != crtc)
7163                         continue;
7164                 encoder_funcs = encoder->base.helper_private;
7165                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7166                                                 adjusted_mode))) {
7167                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7168                         goto fail;
7169                 }
7170         }
7171
7172         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7173                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7174                 goto fail;
7175         }
7176         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7177
7178         return adjusted_mode;
7179 fail:
7180         drm_mode_destroy(dev, adjusted_mode);
7181         return ERR_PTR(-EINVAL);
7182 }
7183
7184 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7185  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7186 static void
7187 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7188                              unsigned *prepare_pipes, unsigned *disable_pipes)
7189 {
7190         struct intel_crtc *intel_crtc;
7191         struct drm_device *dev = crtc->dev;
7192         struct intel_encoder *encoder;
7193         struct intel_connector *connector;
7194         struct drm_crtc *tmp_crtc;
7195
7196         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7197
7198         /* Check which crtcs have changed outputs connected to them, these need
7199          * to be part of the prepare_pipes mask. We don't (yet) support global
7200          * modeset across multiple crtcs, so modeset_pipes will only have one
7201          * bit set at most. */
7202         list_for_each_entry(connector, &dev->mode_config.connector_list,
7203                             base.head) {
7204                 if (connector->base.encoder == &connector->new_encoder->base)
7205                         continue;
7206
7207                 if (connector->base.encoder) {
7208                         tmp_crtc = connector->base.encoder->crtc;
7209
7210                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7211                 }
7212
7213                 if (connector->new_encoder)
7214                         *prepare_pipes |=
7215                                 1 << connector->new_encoder->new_crtc->pipe;
7216         }
7217
7218         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7219                             base.head) {
7220                 if (encoder->base.crtc == &encoder->new_crtc->base)
7221                         continue;
7222
7223                 if (encoder->base.crtc) {
7224                         tmp_crtc = encoder->base.crtc;
7225
7226                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7227                 }
7228
7229                 if (encoder->new_crtc)
7230                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7231         }
7232
7233         /* Check for any pipes that will be fully disabled ... */
7234         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7235                             base.head) {
7236                 bool used = false;
7237
7238                 /* Don't try to disable disabled crtcs. */
7239                 if (!intel_crtc->base.enabled)
7240                         continue;
7241
7242                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7243                                     base.head) {
7244                         if (encoder->new_crtc == intel_crtc)
7245                                 used = true;
7246                 }
7247
7248                 if (!used)
7249                         *disable_pipes |= 1 << intel_crtc->pipe;
7250         }
7251
7252
7253         /* set_mode is also used to update properties on life display pipes. */
7254         intel_crtc = to_intel_crtc(crtc);
7255         if (crtc->enabled)
7256                 *prepare_pipes |= 1 << intel_crtc->pipe;
7257
7258         /* We only support modeset on one single crtc, hence we need to do that
7259          * only for the passed in crtc iff we change anything else than just
7260          * disable crtcs.
7261          *
7262          * This is actually not true, to be fully compatible with the old crtc
7263          * helper we automatically disable _any_ output (i.e. doesn't need to be
7264          * connected to the crtc we're modesetting on) if it's disconnected.
7265          * Which is a rather nutty api (since changed the output configuration
7266          * without userspace's explicit request can lead to confusion), but
7267          * alas. Hence we currently need to modeset on all pipes we prepare. */
7268         if (*prepare_pipes)
7269                 *modeset_pipes = *prepare_pipes;
7270
7271         /* ... and mask these out. */
7272         *modeset_pipes &= ~(*disable_pipes);
7273         *prepare_pipes &= ~(*disable_pipes);
7274 }
7275
7276 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7277 {
7278         struct drm_encoder *encoder;
7279         struct drm_device *dev = crtc->dev;
7280
7281         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7282                 if (encoder->crtc == crtc)
7283                         return true;
7284
7285         return false;
7286 }
7287
7288 static void
7289 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7290 {
7291         struct intel_encoder *intel_encoder;
7292         struct intel_crtc *intel_crtc;
7293         struct drm_connector *connector;
7294
7295         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7296                             base.head) {
7297                 if (!intel_encoder->base.crtc)
7298                         continue;
7299
7300                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7301
7302                 if (prepare_pipes & (1 << intel_crtc->pipe))
7303                         intel_encoder->connectors_active = false;
7304         }
7305
7306         intel_modeset_commit_output_state(dev);
7307
7308         /* Update computed state. */
7309         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7310                             base.head) {
7311                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7312         }
7313
7314         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7315                 if (!connector->encoder || !connector->encoder->crtc)
7316                         continue;
7317
7318                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7319
7320                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7321                         struct drm_property *dpms_property =
7322                                 dev->mode_config.dpms_property;
7323
7324                         connector->dpms = DRM_MODE_DPMS_ON;
7325                         drm_connector_property_set_value(connector,
7326                                                          dpms_property,
7327                                                          DRM_MODE_DPMS_ON);
7328
7329                         intel_encoder = to_intel_encoder(connector->encoder);
7330                         intel_encoder->connectors_active = true;
7331                 }
7332         }
7333
7334 }
7335
7336 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7337         list_for_each_entry((intel_crtc), \
7338                             &(dev)->mode_config.crtc_list, \
7339                             base.head) \
7340                 if (mask & (1 <<(intel_crtc)->pipe)) \
7341
7342 void
7343 intel_modeset_check_state(struct drm_device *dev)
7344 {
7345         struct intel_crtc *crtc;
7346         struct intel_encoder *encoder;
7347         struct intel_connector *connector;
7348
7349         list_for_each_entry(connector, &dev->mode_config.connector_list,
7350                             base.head) {
7351                 /* This also checks the encoder/connector hw state with the
7352                  * ->get_hw_state callbacks. */
7353                 intel_connector_check_state(connector);
7354
7355                 WARN(&connector->new_encoder->base != connector->base.encoder,
7356                      "connector's staged encoder doesn't match current encoder\n");
7357         }
7358
7359         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7360                             base.head) {
7361                 bool enabled = false;
7362                 bool active = false;
7363                 enum pipe pipe, tracked_pipe;
7364
7365                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7366                               encoder->base.base.id,
7367                               drm_get_encoder_name(&encoder->base));
7368
7369                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7370                      "encoder's stage crtc doesn't match current crtc\n");
7371                 WARN(encoder->connectors_active && !encoder->base.crtc,
7372                      "encoder's active_connectors set, but no crtc\n");
7373
7374                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7375                                     base.head) {
7376                         if (connector->base.encoder != &encoder->base)
7377                                 continue;
7378                         enabled = true;
7379                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7380                                 active = true;
7381                 }
7382                 WARN(!!encoder->base.crtc != enabled,
7383                      "encoder's enabled state mismatch "
7384                      "(expected %i, found %i)\n",
7385                      !!encoder->base.crtc, enabled);
7386                 WARN(active && !encoder->base.crtc,
7387                      "active encoder with no crtc\n");
7388
7389                 WARN(encoder->connectors_active != active,
7390                      "encoder's computed active state doesn't match tracked active state "
7391                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7392
7393                 active = encoder->get_hw_state(encoder, &pipe);
7394                 WARN(active != encoder->connectors_active,
7395                      "encoder's hw state doesn't match sw tracking "
7396                      "(expected %i, found %i)\n",
7397                      encoder->connectors_active, active);
7398
7399                 if (!encoder->base.crtc)
7400                         continue;
7401
7402                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7403                 WARN(active && pipe != tracked_pipe,
7404                      "active encoder's pipe doesn't match"
7405                      "(expected %i, found %i)\n",
7406                      tracked_pipe, pipe);
7407
7408         }
7409
7410         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7411                             base.head) {
7412                 bool enabled = false;
7413                 bool active = false;
7414
7415                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7416                               crtc->base.base.id);
7417
7418                 WARN(crtc->active && !crtc->base.enabled,
7419                      "active crtc, but not enabled in sw tracking\n");
7420
7421                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7422                                     base.head) {
7423                         if (encoder->base.crtc != &crtc->base)
7424                                 continue;
7425                         enabled = true;
7426                         if (encoder->connectors_active)
7427                                 active = true;
7428                 }
7429                 WARN(active != crtc->active,
7430                      "crtc's computed active state doesn't match tracked active state "
7431                      "(expected %i, found %i)\n", active, crtc->active);
7432                 WARN(enabled != crtc->base.enabled,
7433                      "crtc's computed enabled state doesn't match tracked enabled state "
7434                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7435
7436                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7437         }
7438 }
7439
7440 bool intel_set_mode(struct drm_crtc *crtc,
7441                     struct drm_display_mode *mode,
7442                     int x, int y, struct drm_framebuffer *fb)
7443 {
7444         struct drm_device *dev = crtc->dev;
7445         drm_i915_private_t *dev_priv = dev->dev_private;
7446         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7447         struct drm_encoder_helper_funcs *encoder_funcs;
7448         struct drm_encoder *encoder;
7449         struct intel_crtc *intel_crtc;
7450         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7451         bool ret = true;
7452
7453         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7454                                      &prepare_pipes, &disable_pipes);
7455
7456         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7457                       modeset_pipes, prepare_pipes, disable_pipes);
7458
7459         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7460                 intel_crtc_disable(&intel_crtc->base);
7461
7462         saved_hwmode = crtc->hwmode;
7463         saved_mode = crtc->mode;
7464
7465         /* Hack: Because we don't (yet) support global modeset on multiple
7466          * crtcs, we don't keep track of the new mode for more than one crtc.
7467          * Hence simply check whether any bit is set in modeset_pipes in all the
7468          * pieces of code that are not yet converted to deal with mutliple crtcs
7469          * changing their mode at the same time. */
7470         adjusted_mode = NULL;
7471         if (modeset_pipes) {
7472                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7473                 if (IS_ERR(adjusted_mode)) {
7474                         return false;
7475                 }
7476         }
7477
7478         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7479                 if (intel_crtc->base.enabled)
7480                         dev_priv->display.crtc_disable(&intel_crtc->base);
7481         }
7482
7483         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7484          * to set it here already despite that we pass it down the callchain.
7485          */
7486         if (modeset_pipes)
7487                 crtc->mode = *mode;
7488
7489         /* Only after disabling all output pipelines that will be changed can we
7490          * update the the output configuration. */
7491         intel_modeset_update_state(dev, prepare_pipes);
7492
7493         /* Set up the DPLL and any encoders state that needs to adjust or depend
7494          * on the DPLL.
7495          */
7496         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7497                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7498                                            mode, adjusted_mode,
7499                                            x, y, fb);
7500                 if (!ret)
7501                     goto done;
7502
7503                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7504
7505                         if (encoder->crtc != &intel_crtc->base)
7506                                 continue;
7507
7508                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7509                                 encoder->base.id, drm_get_encoder_name(encoder),
7510                                 mode->base.id, mode->name);
7511                         encoder_funcs = encoder->helper_private;
7512                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7513                 }
7514         }
7515
7516         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7517         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7518                 dev_priv->display.crtc_enable(&intel_crtc->base);
7519
7520         if (modeset_pipes) {
7521                 /* Store real post-adjustment hardware mode. */
7522                 crtc->hwmode = *adjusted_mode;
7523
7524                 /* Calculate and store various constants which
7525                  * are later needed by vblank and swap-completion
7526                  * timestamping. They are derived from true hwmode.
7527                  */
7528                 drm_calc_timestamping_constants(crtc);
7529         }
7530
7531         /* FIXME: add subpixel order */
7532 done:
7533         drm_mode_destroy(dev, adjusted_mode);
7534         if (!ret && crtc->enabled) {
7535                 crtc->hwmode = saved_hwmode;
7536                 crtc->mode = saved_mode;
7537         } else {
7538                 intel_modeset_check_state(dev);
7539         }
7540
7541         return ret;
7542 }
7543
7544 #undef for_each_intel_crtc_masked
7545
7546 static void intel_set_config_free(struct intel_set_config *config)
7547 {
7548         if (!config)
7549                 return;
7550
7551         kfree(config->save_connector_encoders);
7552         kfree(config->save_encoder_crtcs);
7553         kfree(config);
7554 }
7555
7556 static int intel_set_config_save_state(struct drm_device *dev,
7557                                        struct intel_set_config *config)
7558 {
7559         struct drm_encoder *encoder;
7560         struct drm_connector *connector;
7561         int count;
7562
7563         config->save_encoder_crtcs =
7564                 kcalloc(dev->mode_config.num_encoder,
7565                         sizeof(struct drm_crtc *), GFP_KERNEL);
7566         if (!config->save_encoder_crtcs)
7567                 return -ENOMEM;
7568
7569         config->save_connector_encoders =
7570                 kcalloc(dev->mode_config.num_connector,
7571                         sizeof(struct drm_encoder *), GFP_KERNEL);
7572         if (!config->save_connector_encoders)
7573                 return -ENOMEM;
7574
7575         /* Copy data. Note that driver private data is not affected.
7576          * Should anything bad happen only the expected state is
7577          * restored, not the drivers personal bookkeeping.
7578          */
7579         count = 0;
7580         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7581                 config->save_encoder_crtcs[count++] = encoder->crtc;
7582         }
7583
7584         count = 0;
7585         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7586                 config->save_connector_encoders[count++] = connector->encoder;
7587         }
7588
7589         return 0;
7590 }
7591
7592 static void intel_set_config_restore_state(struct drm_device *dev,
7593                                            struct intel_set_config *config)
7594 {
7595         struct intel_encoder *encoder;
7596         struct intel_connector *connector;
7597         int count;
7598
7599         count = 0;
7600         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7601                 encoder->new_crtc =
7602                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7603         }
7604
7605         count = 0;
7606         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7607                 connector->new_encoder =
7608                         to_intel_encoder(config->save_connector_encoders[count++]);
7609         }
7610 }
7611
7612 static void
7613 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7614                                       struct intel_set_config *config)
7615 {
7616
7617         /* We should be able to check here if the fb has the same properties
7618          * and then just flip_or_move it */
7619         if (set->crtc->fb != set->fb) {
7620                 /* If we have no fb then treat it as a full mode set */
7621                 if (set->crtc->fb == NULL) {
7622                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7623                         config->mode_changed = true;
7624                 } else if (set->fb == NULL) {
7625                         config->mode_changed = true;
7626                 } else if (set->fb->depth != set->crtc->fb->depth) {
7627                         config->mode_changed = true;
7628                 } else if (set->fb->bits_per_pixel !=
7629                            set->crtc->fb->bits_per_pixel) {
7630                         config->mode_changed = true;
7631                 } else
7632                         config->fb_changed = true;
7633         }
7634
7635         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7636                 config->fb_changed = true;
7637
7638         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7639                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7640                 drm_mode_debug_printmodeline(&set->crtc->mode);
7641                 drm_mode_debug_printmodeline(set->mode);
7642                 config->mode_changed = true;
7643         }
7644 }
7645
7646 static int
7647 intel_modeset_stage_output_state(struct drm_device *dev,
7648                                  struct drm_mode_set *set,
7649                                  struct intel_set_config *config)
7650 {
7651         struct drm_crtc *new_crtc;
7652         struct intel_connector *connector;
7653         struct intel_encoder *encoder;
7654         int count, ro;
7655
7656         /* The upper layers ensure that we either disabl a crtc or have a list
7657          * of connectors. For paranoia, double-check this. */
7658         WARN_ON(!set->fb && (set->num_connectors != 0));
7659         WARN_ON(set->fb && (set->num_connectors == 0));
7660
7661         count = 0;
7662         list_for_each_entry(connector, &dev->mode_config.connector_list,
7663                             base.head) {
7664                 /* Otherwise traverse passed in connector list and get encoders
7665                  * for them. */
7666                 for (ro = 0; ro < set->num_connectors; ro++) {
7667                         if (set->connectors[ro] == &connector->base) {
7668                                 connector->new_encoder = connector->encoder;
7669                                 break;
7670                         }
7671                 }
7672
7673                 /* If we disable the crtc, disable all its connectors. Also, if
7674                  * the connector is on the changing crtc but not on the new
7675                  * connector list, disable it. */
7676                 if ((!set->fb || ro == set->num_connectors) &&
7677                     connector->base.encoder &&
7678                     connector->base.encoder->crtc == set->crtc) {
7679                         connector->new_encoder = NULL;
7680
7681                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7682                                 connector->base.base.id,
7683                                 drm_get_connector_name(&connector->base));
7684                 }
7685
7686
7687                 if (&connector->new_encoder->base != connector->base.encoder) {
7688                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7689                         config->mode_changed = true;
7690                 }
7691
7692                 /* Disable all disconnected encoders. */
7693                 if (connector->base.status == connector_status_disconnected)
7694                         connector->new_encoder = NULL;
7695         }
7696         /* connector->new_encoder is now updated for all connectors. */
7697
7698         /* Update crtc of enabled connectors. */
7699         count = 0;
7700         list_for_each_entry(connector, &dev->mode_config.connector_list,
7701                             base.head) {
7702                 if (!connector->new_encoder)
7703                         continue;
7704
7705                 new_crtc = connector->new_encoder->base.crtc;
7706
7707                 for (ro = 0; ro < set->num_connectors; ro++) {
7708                         if (set->connectors[ro] == &connector->base)
7709                                 new_crtc = set->crtc;
7710                 }
7711
7712                 /* Make sure the new CRTC will work with the encoder */
7713                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7714                                            new_crtc)) {
7715                         return -EINVAL;
7716                 }
7717                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7718
7719                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7720                         connector->base.base.id,
7721                         drm_get_connector_name(&connector->base),
7722                         new_crtc->base.id);
7723         }
7724
7725         /* Check for any encoders that needs to be disabled. */
7726         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7727                             base.head) {
7728                 list_for_each_entry(connector,
7729                                     &dev->mode_config.connector_list,
7730                                     base.head) {
7731                         if (connector->new_encoder == encoder) {
7732                                 WARN_ON(!connector->new_encoder->new_crtc);
7733
7734                                 goto next_encoder;
7735                         }
7736                 }
7737                 encoder->new_crtc = NULL;
7738 next_encoder:
7739                 /* Only now check for crtc changes so we don't miss encoders
7740                  * that will be disabled. */
7741                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7742                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7743                         config->mode_changed = true;
7744                 }
7745         }
7746         /* Now we've also updated encoder->new_crtc for all encoders. */
7747
7748         return 0;
7749 }
7750
7751 static int intel_crtc_set_config(struct drm_mode_set *set)
7752 {
7753         struct drm_device *dev;
7754         struct drm_mode_set save_set;
7755         struct intel_set_config *config;
7756         int ret;
7757
7758         BUG_ON(!set);
7759         BUG_ON(!set->crtc);
7760         BUG_ON(!set->crtc->helper_private);
7761
7762         if (!set->mode)
7763                 set->fb = NULL;
7764
7765         /* The fb helper likes to play gross jokes with ->mode_set_config.
7766          * Unfortunately the crtc helper doesn't do much at all for this case,
7767          * so we have to cope with this madness until the fb helper is fixed up. */
7768         if (set->fb && set->num_connectors == 0)
7769                 return 0;
7770
7771         if (set->fb) {
7772                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7773                                 set->crtc->base.id, set->fb->base.id,
7774                                 (int)set->num_connectors, set->x, set->y);
7775         } else {
7776                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7777         }
7778
7779         dev = set->crtc->dev;
7780
7781         ret = -ENOMEM;
7782         config = kzalloc(sizeof(*config), GFP_KERNEL);
7783         if (!config)
7784                 goto out_config;
7785
7786         ret = intel_set_config_save_state(dev, config);
7787         if (ret)
7788                 goto out_config;
7789
7790         save_set.crtc = set->crtc;
7791         save_set.mode = &set->crtc->mode;
7792         save_set.x = set->crtc->x;
7793         save_set.y = set->crtc->y;
7794         save_set.fb = set->crtc->fb;
7795
7796         /* Compute whether we need a full modeset, only an fb base update or no
7797          * change at all. In the future we might also check whether only the
7798          * mode changed, e.g. for LVDS where we only change the panel fitter in
7799          * such cases. */
7800         intel_set_config_compute_mode_changes(set, config);
7801
7802         ret = intel_modeset_stage_output_state(dev, set, config);
7803         if (ret)
7804                 goto fail;
7805
7806         if (config->mode_changed) {
7807                 if (set->mode) {
7808                         DRM_DEBUG_KMS("attempting to set mode from"
7809                                         " userspace\n");
7810                         drm_mode_debug_printmodeline(set->mode);
7811                 }
7812
7813                 if (!intel_set_mode(set->crtc, set->mode,
7814                                     set->x, set->y, set->fb)) {
7815                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7816                                   set->crtc->base.id);
7817                         ret = -EINVAL;
7818                         goto fail;
7819                 }
7820         } else if (config->fb_changed) {
7821                 ret = intel_pipe_set_base(set->crtc,
7822                                           set->x, set->y, set->fb);
7823         }
7824
7825         intel_set_config_free(config);
7826
7827         return 0;
7828
7829 fail:
7830         intel_set_config_restore_state(dev, config);
7831
7832         /* Try to restore the config */
7833         if (config->mode_changed &&
7834             !intel_set_mode(save_set.crtc, save_set.mode,
7835                             save_set.x, save_set.y, save_set.fb))
7836                 DRM_ERROR("failed to restore config after modeset failure\n");
7837
7838 out_config:
7839         intel_set_config_free(config);
7840         return ret;
7841 }
7842
7843 static const struct drm_crtc_funcs intel_crtc_funcs = {
7844         .cursor_set = intel_crtc_cursor_set,
7845         .cursor_move = intel_crtc_cursor_move,
7846         .gamma_set = intel_crtc_gamma_set,
7847         .set_config = intel_crtc_set_config,
7848         .destroy = intel_crtc_destroy,
7849         .page_flip = intel_crtc_page_flip,
7850 };
7851
7852 static void intel_cpu_pll_init(struct drm_device *dev)
7853 {
7854         if (IS_HASWELL(dev))
7855                 intel_ddi_pll_init(dev);
7856 }
7857
7858 static void intel_pch_pll_init(struct drm_device *dev)
7859 {
7860         drm_i915_private_t *dev_priv = dev->dev_private;
7861         int i;
7862
7863         if (dev_priv->num_pch_pll == 0) {
7864                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7865                 return;
7866         }
7867
7868         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7869                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7870                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7871                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7872         }
7873 }
7874
7875 static void intel_crtc_init(struct drm_device *dev, int pipe)
7876 {
7877         drm_i915_private_t *dev_priv = dev->dev_private;
7878         struct intel_crtc *intel_crtc;
7879         int i;
7880
7881         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7882         if (intel_crtc == NULL)
7883                 return;
7884
7885         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7886
7887         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7888         for (i = 0; i < 256; i++) {
7889                 intel_crtc->lut_r[i] = i;
7890                 intel_crtc->lut_g[i] = i;
7891                 intel_crtc->lut_b[i] = i;
7892         }
7893
7894         /* Swap pipes & planes for FBC on pre-965 */
7895         intel_crtc->pipe = pipe;
7896         intel_crtc->plane = pipe;
7897         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7898                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7899                 intel_crtc->plane = !pipe;
7900         }
7901
7902         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7903                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7904         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7905         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7906
7907         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7908
7909         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7910 }
7911
7912 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7913                                 struct drm_file *file)
7914 {
7915         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7916         struct drm_mode_object *drmmode_obj;
7917         struct intel_crtc *crtc;
7918
7919         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7920                 return -ENODEV;
7921
7922         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7923                         DRM_MODE_OBJECT_CRTC);
7924
7925         if (!drmmode_obj) {
7926                 DRM_ERROR("no such CRTC id\n");
7927                 return -EINVAL;
7928         }
7929
7930         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7931         pipe_from_crtc_id->pipe = crtc->pipe;
7932
7933         return 0;
7934 }
7935
7936 static int intel_encoder_clones(struct intel_encoder *encoder)
7937 {
7938         struct drm_device *dev = encoder->base.dev;
7939         struct intel_encoder *source_encoder;
7940         int index_mask = 0;
7941         int entry = 0;
7942
7943         list_for_each_entry(source_encoder,
7944                             &dev->mode_config.encoder_list, base.head) {
7945
7946                 if (encoder == source_encoder)
7947                         index_mask |= (1 << entry);
7948
7949                 /* Intel hw has only one MUX where enocoders could be cloned. */
7950                 if (encoder->cloneable && source_encoder->cloneable)
7951                         index_mask |= (1 << entry);
7952
7953                 entry++;
7954         }
7955
7956         return index_mask;
7957 }
7958
7959 static bool has_edp_a(struct drm_device *dev)
7960 {
7961         struct drm_i915_private *dev_priv = dev->dev_private;
7962
7963         if (!IS_MOBILE(dev))
7964                 return false;
7965
7966         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7967                 return false;
7968
7969         if (IS_GEN5(dev) &&
7970             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7971                 return false;
7972
7973         return true;
7974 }
7975
7976 static void intel_setup_outputs(struct drm_device *dev)
7977 {
7978         struct drm_i915_private *dev_priv = dev->dev_private;
7979         struct intel_encoder *encoder;
7980         bool dpd_is_edp = false;
7981         bool has_lvds;
7982
7983         has_lvds = intel_lvds_init(dev);
7984         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7985                 /* disable the panel fitter on everything but LVDS */
7986                 I915_WRITE(PFIT_CONTROL, 0);
7987         }
7988
7989         if (HAS_PCH_SPLIT(dev)) {
7990                 dpd_is_edp = intel_dpd_is_edp(dev);
7991
7992                 if (has_edp_a(dev))
7993                         intel_dp_init(dev, DP_A, PORT_A);
7994
7995                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7996                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7997         }
7998
7999         intel_crt_init(dev);
8000
8001         if (IS_HASWELL(dev)) {
8002                 int found;
8003
8004                 /* Haswell uses DDI functions to detect digital outputs */
8005                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8006                 /* DDI A only supports eDP */
8007                 if (found)
8008                         intel_ddi_init(dev, PORT_A);
8009
8010                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8011                  * register */
8012                 found = I915_READ(SFUSE_STRAP);
8013
8014                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8015                         intel_ddi_init(dev, PORT_B);
8016                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8017                         intel_ddi_init(dev, PORT_C);
8018                 if (found & SFUSE_STRAP_DDID_DETECTED)
8019                         intel_ddi_init(dev, PORT_D);
8020         } else if (HAS_PCH_SPLIT(dev)) {
8021                 int found;
8022
8023                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8024                         /* PCH SDVOB multiplex with HDMIB */
8025                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8026                         if (!found)
8027                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8028                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8029                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8030                 }
8031
8032                 if (I915_READ(HDMIC) & PORT_DETECTED)
8033                         intel_hdmi_init(dev, HDMIC, PORT_C);
8034
8035                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8036                         intel_hdmi_init(dev, HDMID, PORT_D);
8037
8038                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8039                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8040
8041                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8042                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8043         } else if (IS_VALLEYVIEW(dev)) {
8044                 int found;
8045
8046                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8047                 if (I915_READ(DP_C) & DP_DETECTED)
8048                         intel_dp_init(dev, DP_C, PORT_C);
8049
8050                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8051                         /* SDVOB multiplex with HDMIB */
8052                         found = intel_sdvo_init(dev, SDVOB, true);
8053                         if (!found)
8054                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8055                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8056                                 intel_dp_init(dev, DP_B, PORT_B);
8057                 }
8058
8059                 if (I915_READ(SDVOC) & PORT_DETECTED)
8060                         intel_hdmi_init(dev, SDVOC, PORT_C);
8061
8062         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8063                 bool found = false;
8064
8065                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8066                         DRM_DEBUG_KMS("probing SDVOB\n");
8067                         found = intel_sdvo_init(dev, SDVOB, true);
8068                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8069                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8070                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8071                         }
8072
8073                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8074                                 DRM_DEBUG_KMS("probing DP_B\n");
8075                                 intel_dp_init(dev, DP_B, PORT_B);
8076                         }
8077                 }
8078
8079                 /* Before G4X SDVOC doesn't have its own detect register */
8080
8081                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8082                         DRM_DEBUG_KMS("probing SDVOC\n");
8083                         found = intel_sdvo_init(dev, SDVOC, false);
8084                 }
8085
8086                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8087
8088                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8089                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8090                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8091                         }
8092                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8093                                 DRM_DEBUG_KMS("probing DP_C\n");
8094                                 intel_dp_init(dev, DP_C, PORT_C);
8095                         }
8096                 }
8097
8098                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8099                     (I915_READ(DP_D) & DP_DETECTED)) {
8100                         DRM_DEBUG_KMS("probing DP_D\n");
8101                         intel_dp_init(dev, DP_D, PORT_D);
8102                 }
8103         } else if (IS_GEN2(dev))
8104                 intel_dvo_init(dev);
8105
8106         if (SUPPORTS_TV(dev))
8107                 intel_tv_init(dev);
8108
8109         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8110                 encoder->base.possible_crtcs = encoder->crtc_mask;
8111                 encoder->base.possible_clones =
8112                         intel_encoder_clones(encoder);
8113         }
8114
8115         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8116                 ironlake_init_pch_refclk(dev);
8117 }
8118
8119 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8120 {
8121         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8122
8123         drm_framebuffer_cleanup(fb);
8124         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8125
8126         kfree(intel_fb);
8127 }
8128
8129 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8130                                                 struct drm_file *file,
8131                                                 unsigned int *handle)
8132 {
8133         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8134         struct drm_i915_gem_object *obj = intel_fb->obj;
8135
8136         return drm_gem_handle_create(file, &obj->base, handle);
8137 }
8138
8139 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8140         .destroy = intel_user_framebuffer_destroy,
8141         .create_handle = intel_user_framebuffer_create_handle,
8142 };
8143
8144 int intel_framebuffer_init(struct drm_device *dev,
8145                            struct intel_framebuffer *intel_fb,
8146                            struct drm_mode_fb_cmd2 *mode_cmd,
8147                            struct drm_i915_gem_object *obj)
8148 {
8149         int ret;
8150
8151         if (obj->tiling_mode == I915_TILING_Y)
8152                 return -EINVAL;
8153
8154         if (mode_cmd->pitches[0] & 63)
8155                 return -EINVAL;
8156
8157         switch (mode_cmd->pixel_format) {
8158         case DRM_FORMAT_RGB332:
8159         case DRM_FORMAT_RGB565:
8160         case DRM_FORMAT_XRGB8888:
8161         case DRM_FORMAT_XBGR8888:
8162         case DRM_FORMAT_ARGB8888:
8163         case DRM_FORMAT_XRGB2101010:
8164         case DRM_FORMAT_ARGB2101010:
8165                 /* RGB formats are common across chipsets */
8166                 break;
8167         case DRM_FORMAT_YUYV:
8168         case DRM_FORMAT_UYVY:
8169         case DRM_FORMAT_YVYU:
8170         case DRM_FORMAT_VYUY:
8171                 break;
8172         default:
8173                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8174                                 mode_cmd->pixel_format);
8175                 return -EINVAL;
8176         }
8177
8178         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8179         if (ret) {
8180                 DRM_ERROR("framebuffer init failed %d\n", ret);
8181                 return ret;
8182         }
8183
8184         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8185         intel_fb->obj = obj;
8186         return 0;
8187 }
8188
8189 static struct drm_framebuffer *
8190 intel_user_framebuffer_create(struct drm_device *dev,
8191                               struct drm_file *filp,
8192                               struct drm_mode_fb_cmd2 *mode_cmd)
8193 {
8194         struct drm_i915_gem_object *obj;
8195
8196         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8197                                                 mode_cmd->handles[0]));
8198         if (&obj->base == NULL)
8199                 return ERR_PTR(-ENOENT);
8200
8201         return intel_framebuffer_create(dev, mode_cmd, obj);
8202 }
8203
8204 static const struct drm_mode_config_funcs intel_mode_funcs = {
8205         .fb_create = intel_user_framebuffer_create,
8206         .output_poll_changed = intel_fb_output_poll_changed,
8207 };
8208
8209 /* Set up chip specific display functions */
8210 static void intel_init_display(struct drm_device *dev)
8211 {
8212         struct drm_i915_private *dev_priv = dev->dev_private;
8213
8214         /* We always want a DPMS function */
8215         if (IS_HASWELL(dev)) {
8216                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8217                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8218                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8219                 dev_priv->display.off = haswell_crtc_off;
8220                 dev_priv->display.update_plane = ironlake_update_plane;
8221         } else if (HAS_PCH_SPLIT(dev)) {
8222                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8223                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8224                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8225                 dev_priv->display.off = ironlake_crtc_off;
8226                 dev_priv->display.update_plane = ironlake_update_plane;
8227         } else {
8228                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8229                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8230                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8231                 dev_priv->display.off = i9xx_crtc_off;
8232                 dev_priv->display.update_plane = i9xx_update_plane;
8233         }
8234
8235         /* Returns the core display clock speed */
8236         if (IS_VALLEYVIEW(dev))
8237                 dev_priv->display.get_display_clock_speed =
8238                         valleyview_get_display_clock_speed;
8239         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8240                 dev_priv->display.get_display_clock_speed =
8241                         i945_get_display_clock_speed;
8242         else if (IS_I915G(dev))
8243                 dev_priv->display.get_display_clock_speed =
8244                         i915_get_display_clock_speed;
8245         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8246                 dev_priv->display.get_display_clock_speed =
8247                         i9xx_misc_get_display_clock_speed;
8248         else if (IS_I915GM(dev))
8249                 dev_priv->display.get_display_clock_speed =
8250                         i915gm_get_display_clock_speed;
8251         else if (IS_I865G(dev))
8252                 dev_priv->display.get_display_clock_speed =
8253                         i865_get_display_clock_speed;
8254         else if (IS_I85X(dev))
8255                 dev_priv->display.get_display_clock_speed =
8256                         i855_get_display_clock_speed;
8257         else /* 852, 830 */
8258                 dev_priv->display.get_display_clock_speed =
8259                         i830_get_display_clock_speed;
8260
8261         if (HAS_PCH_SPLIT(dev)) {
8262                 if (IS_GEN5(dev)) {
8263                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8264                         dev_priv->display.write_eld = ironlake_write_eld;
8265                 } else if (IS_GEN6(dev)) {
8266                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8267                         dev_priv->display.write_eld = ironlake_write_eld;
8268                 } else if (IS_IVYBRIDGE(dev)) {
8269                         /* FIXME: detect B0+ stepping and use auto training */
8270                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8271                         dev_priv->display.write_eld = ironlake_write_eld;
8272                 } else if (IS_HASWELL(dev)) {
8273                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8274                         dev_priv->display.write_eld = haswell_write_eld;
8275                 } else
8276                         dev_priv->display.update_wm = NULL;
8277         } else if (IS_G4X(dev)) {
8278                 dev_priv->display.write_eld = g4x_write_eld;
8279         }
8280
8281         /* Default just returns -ENODEV to indicate unsupported */
8282         dev_priv->display.queue_flip = intel_default_queue_flip;
8283
8284         switch (INTEL_INFO(dev)->gen) {
8285         case 2:
8286                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8287                 break;
8288
8289         case 3:
8290                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8291                 break;
8292
8293         case 4:
8294         case 5:
8295                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8296                 break;
8297
8298         case 6:
8299                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8300                 break;
8301         case 7:
8302                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8303                 break;
8304         }
8305 }
8306
8307 /*
8308  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8309  * resume, or other times.  This quirk makes sure that's the case for
8310  * affected systems.
8311  */
8312 static void quirk_pipea_force(struct drm_device *dev)
8313 {
8314         struct drm_i915_private *dev_priv = dev->dev_private;
8315
8316         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8317         DRM_INFO("applying pipe a force quirk\n");
8318 }
8319
8320 /*
8321  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8322  */
8323 static void quirk_ssc_force_disable(struct drm_device *dev)
8324 {
8325         struct drm_i915_private *dev_priv = dev->dev_private;
8326         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8327         DRM_INFO("applying lvds SSC disable quirk\n");
8328 }
8329
8330 /*
8331  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8332  * brightness value
8333  */
8334 static void quirk_invert_brightness(struct drm_device *dev)
8335 {
8336         struct drm_i915_private *dev_priv = dev->dev_private;
8337         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8338         DRM_INFO("applying inverted panel brightness quirk\n");
8339 }
8340
8341 struct intel_quirk {
8342         int device;
8343         int subsystem_vendor;
8344         int subsystem_device;
8345         void (*hook)(struct drm_device *dev);
8346 };
8347
8348 static struct intel_quirk intel_quirks[] = {
8349         /* HP Mini needs pipe A force quirk (LP: #322104) */
8350         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8351
8352         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8353         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8354
8355         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8356         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8357
8358         /* 830/845 need to leave pipe A & dpll A up */
8359         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8360         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8361
8362         /* Lenovo U160 cannot use SSC on LVDS */
8363         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8364
8365         /* Sony Vaio Y cannot use SSC on LVDS */
8366         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8367
8368         /* Acer Aspire 5734Z must invert backlight brightness */
8369         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8370 };
8371
8372 static void intel_init_quirks(struct drm_device *dev)
8373 {
8374         struct pci_dev *d = dev->pdev;
8375         int i;
8376
8377         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8378                 struct intel_quirk *q = &intel_quirks[i];
8379
8380                 if (d->device == q->device &&
8381                     (d->subsystem_vendor == q->subsystem_vendor ||
8382                      q->subsystem_vendor == PCI_ANY_ID) &&
8383                     (d->subsystem_device == q->subsystem_device ||
8384                      q->subsystem_device == PCI_ANY_ID))
8385                         q->hook(dev);
8386         }
8387 }
8388
8389 /* Disable the VGA plane that we never use */
8390 static void i915_disable_vga(struct drm_device *dev)
8391 {
8392         struct drm_i915_private *dev_priv = dev->dev_private;
8393         u8 sr1;
8394         u32 vga_reg;
8395
8396         if (HAS_PCH_SPLIT(dev))
8397                 vga_reg = CPU_VGACNTRL;
8398         else
8399                 vga_reg = VGACNTRL;
8400
8401         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8402         outb(SR01, VGA_SR_INDEX);
8403         sr1 = inb(VGA_SR_DATA);
8404         outb(sr1 | 1<<5, VGA_SR_DATA);
8405         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8406         udelay(300);
8407
8408         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8409         POSTING_READ(vga_reg);
8410 }
8411
8412 void intel_modeset_init_hw(struct drm_device *dev)
8413 {
8414         /* We attempt to init the necessary power wells early in the initialization
8415          * time, so the subsystems that expect power to be enabled can work.
8416          */
8417         intel_init_power_wells(dev);
8418
8419         intel_prepare_ddi(dev);
8420
8421         intel_init_clock_gating(dev);
8422
8423         mutex_lock(&dev->struct_mutex);
8424         intel_enable_gt_powersave(dev);
8425         mutex_unlock(&dev->struct_mutex);
8426 }
8427
8428 void intel_modeset_init(struct drm_device *dev)
8429 {
8430         struct drm_i915_private *dev_priv = dev->dev_private;
8431         int i, ret;
8432
8433         drm_mode_config_init(dev);
8434
8435         dev->mode_config.min_width = 0;
8436         dev->mode_config.min_height = 0;
8437
8438         dev->mode_config.preferred_depth = 24;
8439         dev->mode_config.prefer_shadow = 1;
8440
8441         dev->mode_config.funcs = &intel_mode_funcs;
8442
8443         intel_init_quirks(dev);
8444
8445         intel_init_pm(dev);
8446
8447         intel_init_display(dev);
8448
8449         if (IS_GEN2(dev)) {
8450                 dev->mode_config.max_width = 2048;
8451                 dev->mode_config.max_height = 2048;
8452         } else if (IS_GEN3(dev)) {
8453                 dev->mode_config.max_width = 4096;
8454                 dev->mode_config.max_height = 4096;
8455         } else {
8456                 dev->mode_config.max_width = 8192;
8457                 dev->mode_config.max_height = 8192;
8458         }
8459         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8460
8461         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8462                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8463
8464         for (i = 0; i < dev_priv->num_pipe; i++) {
8465                 intel_crtc_init(dev, i);
8466                 ret = intel_plane_init(dev, i);
8467                 if (ret)
8468                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8469         }
8470
8471         intel_cpu_pll_init(dev);
8472         intel_pch_pll_init(dev);
8473
8474         /* Just disable it once at startup */
8475         i915_disable_vga(dev);
8476         intel_setup_outputs(dev);
8477 }
8478
8479 static void
8480 intel_connector_break_all_links(struct intel_connector *connector)
8481 {
8482         connector->base.dpms = DRM_MODE_DPMS_OFF;
8483         connector->base.encoder = NULL;
8484         connector->encoder->connectors_active = false;
8485         connector->encoder->base.crtc = NULL;
8486 }
8487
8488 static void intel_enable_pipe_a(struct drm_device *dev)
8489 {
8490         struct intel_connector *connector;
8491         struct drm_connector *crt = NULL;
8492         struct intel_load_detect_pipe load_detect_temp;
8493
8494         /* We can't just switch on the pipe A, we need to set things up with a
8495          * proper mode and output configuration. As a gross hack, enable pipe A
8496          * by enabling the load detect pipe once. */
8497         list_for_each_entry(connector,
8498                             &dev->mode_config.connector_list,
8499                             base.head) {
8500                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8501                         crt = &connector->base;
8502                         break;
8503                 }
8504         }
8505
8506         if (!crt)
8507                 return;
8508
8509         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8510                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8511
8512
8513 }
8514
8515 static bool
8516 intel_check_plane_mapping(struct intel_crtc *crtc)
8517 {
8518         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8519         u32 reg, val;
8520
8521         if (dev_priv->num_pipe == 1)
8522                 return true;
8523
8524         reg = DSPCNTR(!crtc->plane);
8525         val = I915_READ(reg);
8526
8527         if ((val & DISPLAY_PLANE_ENABLE) &&
8528             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8529                 return false;
8530
8531         return true;
8532 }
8533
8534 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8535 {
8536         struct drm_device *dev = crtc->base.dev;
8537         struct drm_i915_private *dev_priv = dev->dev_private;
8538         u32 reg;
8539
8540         /* Clear any frame start delays used for debugging left by the BIOS */
8541         reg = PIPECONF(crtc->pipe);
8542         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8543
8544         /* We need to sanitize the plane -> pipe mapping first because this will
8545          * disable the crtc (and hence change the state) if it is wrong. Note
8546          * that gen4+ has a fixed plane -> pipe mapping.  */
8547         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8548                 struct intel_connector *connector;
8549                 bool plane;
8550
8551                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8552                               crtc->base.base.id);
8553
8554                 /* Pipe has the wrong plane attached and the plane is active.
8555                  * Temporarily change the plane mapping and disable everything
8556                  * ...  */
8557                 plane = crtc->plane;
8558                 crtc->plane = !plane;
8559                 dev_priv->display.crtc_disable(&crtc->base);
8560                 crtc->plane = plane;
8561
8562                 /* ... and break all links. */
8563                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8564                                     base.head) {
8565                         if (connector->encoder->base.crtc != &crtc->base)
8566                                 continue;
8567
8568                         intel_connector_break_all_links(connector);
8569                 }
8570
8571                 WARN_ON(crtc->active);
8572                 crtc->base.enabled = false;
8573         }
8574
8575         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8576             crtc->pipe == PIPE_A && !crtc->active) {
8577                 /* BIOS forgot to enable pipe A, this mostly happens after
8578                  * resume. Force-enable the pipe to fix this, the update_dpms
8579                  * call below we restore the pipe to the right state, but leave
8580                  * the required bits on. */
8581                 intel_enable_pipe_a(dev);
8582         }
8583
8584         /* Adjust the state of the output pipe according to whether we
8585          * have active connectors/encoders. */
8586         intel_crtc_update_dpms(&crtc->base);
8587
8588         if (crtc->active != crtc->base.enabled) {
8589                 struct intel_encoder *encoder;
8590
8591                 /* This can happen either due to bugs in the get_hw_state
8592                  * functions or because the pipe is force-enabled due to the
8593                  * pipe A quirk. */
8594                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8595                               crtc->base.base.id,
8596                               crtc->base.enabled ? "enabled" : "disabled",
8597                               crtc->active ? "enabled" : "disabled");
8598
8599                 crtc->base.enabled = crtc->active;
8600
8601                 /* Because we only establish the connector -> encoder ->
8602                  * crtc links if something is active, this means the
8603                  * crtc is now deactivated. Break the links. connector
8604                  * -> encoder links are only establish when things are
8605                  *  actually up, hence no need to break them. */
8606                 WARN_ON(crtc->active);
8607
8608                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8609                         WARN_ON(encoder->connectors_active);
8610                         encoder->base.crtc = NULL;
8611                 }
8612         }
8613 }
8614
8615 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8616 {
8617         struct intel_connector *connector;
8618         struct drm_device *dev = encoder->base.dev;
8619
8620         /* We need to check both for a crtc link (meaning that the
8621          * encoder is active and trying to read from a pipe) and the
8622          * pipe itself being active. */
8623         bool has_active_crtc = encoder->base.crtc &&
8624                 to_intel_crtc(encoder->base.crtc)->active;
8625
8626         if (encoder->connectors_active && !has_active_crtc) {
8627                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8628                               encoder->base.base.id,
8629                               drm_get_encoder_name(&encoder->base));
8630
8631                 /* Connector is active, but has no active pipe. This is
8632                  * fallout from our resume register restoring. Disable
8633                  * the encoder manually again. */
8634                 if (encoder->base.crtc) {
8635                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8636                                       encoder->base.base.id,
8637                                       drm_get_encoder_name(&encoder->base));
8638                         encoder->disable(encoder);
8639                 }
8640
8641                 /* Inconsistent output/port/pipe state happens presumably due to
8642                  * a bug in one of the get_hw_state functions. Or someplace else
8643                  * in our code, like the register restore mess on resume. Clamp
8644                  * things to off as a safer default. */
8645                 list_for_each_entry(connector,
8646                                     &dev->mode_config.connector_list,
8647                                     base.head) {
8648                         if (connector->encoder != encoder)
8649                                 continue;
8650
8651                         intel_connector_break_all_links(connector);
8652                 }
8653         }
8654         /* Enabled encoders without active connectors will be fixed in
8655          * the crtc fixup. */
8656 }
8657
8658 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8659  * and i915 state tracking structures. */
8660 void intel_modeset_setup_hw_state(struct drm_device *dev)
8661 {
8662         struct drm_i915_private *dev_priv = dev->dev_private;
8663         enum pipe pipe;
8664         u32 tmp;
8665         struct intel_crtc *crtc;
8666         struct intel_encoder *encoder;
8667         struct intel_connector *connector;
8668
8669         for_each_pipe(pipe) {
8670                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8671
8672                 tmp = I915_READ(PIPECONF(pipe));
8673                 if (tmp & PIPECONF_ENABLE)
8674                         crtc->active = true;
8675                 else
8676                         crtc->active = false;
8677
8678                 crtc->base.enabled = crtc->active;
8679
8680                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8681                               crtc->base.base.id,
8682                               crtc->active ? "enabled" : "disabled");
8683         }
8684
8685         if (IS_HASWELL(dev))
8686                 intel_ddi_setup_hw_pll_state(dev);
8687
8688         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8689                             base.head) {
8690                 pipe = 0;
8691
8692                 if (encoder->get_hw_state(encoder, &pipe)) {
8693                         encoder->base.crtc =
8694                                 dev_priv->pipe_to_crtc_mapping[pipe];
8695                 } else {
8696                         encoder->base.crtc = NULL;
8697                 }
8698
8699                 encoder->connectors_active = false;
8700                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8701                               encoder->base.base.id,
8702                               drm_get_encoder_name(&encoder->base),
8703                               encoder->base.crtc ? "enabled" : "disabled",
8704                               pipe);
8705         }
8706
8707         list_for_each_entry(connector, &dev->mode_config.connector_list,
8708                             base.head) {
8709                 if (connector->get_hw_state(connector)) {
8710                         connector->base.dpms = DRM_MODE_DPMS_ON;
8711                         connector->encoder->connectors_active = true;
8712                         connector->base.encoder = &connector->encoder->base;
8713                 } else {
8714                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8715                         connector->base.encoder = NULL;
8716                 }
8717                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8718                               connector->base.base.id,
8719                               drm_get_connector_name(&connector->base),
8720                               connector->base.encoder ? "enabled" : "disabled");
8721         }
8722
8723         /* HW state is read out, now we need to sanitize this mess. */
8724         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8725                             base.head) {
8726                 intel_sanitize_encoder(encoder);
8727         }
8728
8729         for_each_pipe(pipe) {
8730                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8731                 intel_sanitize_crtc(crtc);
8732         }
8733
8734         intel_modeset_update_staged_output_state(dev);
8735
8736         intel_modeset_check_state(dev);
8737
8738         drm_mode_config_reset(dev);
8739 }
8740
8741 void intel_modeset_gem_init(struct drm_device *dev)
8742 {
8743         intel_modeset_init_hw(dev);
8744
8745         intel_setup_overlay(dev);
8746
8747         intel_modeset_setup_hw_state(dev);
8748 }
8749
8750 void intel_modeset_cleanup(struct drm_device *dev)
8751 {
8752         struct drm_i915_private *dev_priv = dev->dev_private;
8753         struct drm_crtc *crtc;
8754         struct intel_crtc *intel_crtc;
8755
8756         drm_kms_helper_poll_fini(dev);
8757         mutex_lock(&dev->struct_mutex);
8758
8759         intel_unregister_dsm_handler();
8760
8761
8762         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8763                 /* Skip inactive CRTCs */
8764                 if (!crtc->fb)
8765                         continue;
8766
8767                 intel_crtc = to_intel_crtc(crtc);
8768                 intel_increase_pllclock(crtc);
8769         }
8770
8771         intel_disable_fbc(dev);
8772
8773         intel_disable_gt_powersave(dev);
8774
8775         ironlake_teardown_rc6(dev);
8776
8777         if (IS_VALLEYVIEW(dev))
8778                 vlv_init_dpio(dev);
8779
8780         mutex_unlock(&dev->struct_mutex);
8781
8782         /* Disable the irq before mode object teardown, for the irq might
8783          * enqueue unpin/hotplug work. */
8784         drm_irq_uninstall(dev);
8785         cancel_work_sync(&dev_priv->hotplug_work);
8786         cancel_work_sync(&dev_priv->rps.work);
8787
8788         /* flush any delayed tasks or pending work */
8789         flush_scheduled_work();
8790
8791         drm_mode_config_cleanup(dev);
8792 }
8793
8794 /*
8795  * Return which encoder is currently attached for connector.
8796  */
8797 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8798 {
8799         return &intel_attached_encoder(connector)->base;
8800 }
8801
8802 void intel_connector_attach_encoder(struct intel_connector *connector,
8803                                     struct intel_encoder *encoder)
8804 {
8805         connector->encoder = encoder;
8806         drm_mode_connector_attach_encoder(&connector->base,
8807                                           &encoder->base);
8808 }
8809
8810 /*
8811  * set vga decode state - true == enable VGA decode
8812  */
8813 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8814 {
8815         struct drm_i915_private *dev_priv = dev->dev_private;
8816         u16 gmch_ctrl;
8817
8818         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8819         if (state)
8820                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8821         else
8822                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8823         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8824         return 0;
8825 }
8826
8827 #ifdef CONFIG_DEBUG_FS
8828 #include <linux/seq_file.h>
8829
8830 struct intel_display_error_state {
8831         struct intel_cursor_error_state {
8832                 u32 control;
8833                 u32 position;
8834                 u32 base;
8835                 u32 size;
8836         } cursor[I915_MAX_PIPES];
8837
8838         struct intel_pipe_error_state {
8839                 u32 conf;
8840                 u32 source;
8841
8842                 u32 htotal;
8843                 u32 hblank;
8844                 u32 hsync;
8845                 u32 vtotal;
8846                 u32 vblank;
8847                 u32 vsync;
8848         } pipe[I915_MAX_PIPES];
8849
8850         struct intel_plane_error_state {
8851                 u32 control;
8852                 u32 stride;
8853                 u32 size;
8854                 u32 pos;
8855                 u32 addr;
8856                 u32 surface;
8857                 u32 tile_offset;
8858         } plane[I915_MAX_PIPES];
8859 };
8860
8861 struct intel_display_error_state *
8862 intel_display_capture_error_state(struct drm_device *dev)
8863 {
8864         drm_i915_private_t *dev_priv = dev->dev_private;
8865         struct intel_display_error_state *error;
8866         int i;
8867
8868         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8869         if (error == NULL)
8870                 return NULL;
8871
8872         for_each_pipe(i) {
8873                 error->cursor[i].control = I915_READ(CURCNTR(i));
8874                 error->cursor[i].position = I915_READ(CURPOS(i));
8875                 error->cursor[i].base = I915_READ(CURBASE(i));
8876
8877                 error->plane[i].control = I915_READ(DSPCNTR(i));
8878                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8879                 error->plane[i].size = I915_READ(DSPSIZE(i));
8880                 error->plane[i].pos = I915_READ(DSPPOS(i));
8881                 error->plane[i].addr = I915_READ(DSPADDR(i));
8882                 if (INTEL_INFO(dev)->gen >= 4) {
8883                         error->plane[i].surface = I915_READ(DSPSURF(i));
8884                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8885                 }
8886
8887                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8888                 error->pipe[i].source = I915_READ(PIPESRC(i));
8889                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8890                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8891                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8892                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8893                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8894                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8895         }
8896
8897         return error;
8898 }
8899
8900 void
8901 intel_display_print_error_state(struct seq_file *m,
8902                                 struct drm_device *dev,
8903                                 struct intel_display_error_state *error)
8904 {
8905         drm_i915_private_t *dev_priv = dev->dev_private;
8906         int i;
8907
8908         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8909         for_each_pipe(i) {
8910                 seq_printf(m, "Pipe [%d]:\n", i);
8911                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8912                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8913                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8914                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8915                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8916                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8917                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8918                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8919
8920                 seq_printf(m, "Plane [%d]:\n", i);
8921                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8922                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8923                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8924                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8925                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8926                 if (INTEL_INFO(dev)->gen >= 4) {
8927                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8928                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8929                 }
8930
8931                 seq_printf(m, "Cursor [%d]:\n", i);
8932                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8933                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8934                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8935         }
8936 }
8937 #endif