Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum transcoder cpu_transcoder)
1722 {
1723         u32 val, pipeconf_val;
1724
1725         /* PCH only available on ILK+ */
1726         BUG_ON(dev_priv->info->gen < 5);
1727
1728         /* FDI must be feeding us bits for PCH ports */
1729         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1731
1732         val = TRANS_ENABLE;
1733         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1734
1735         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1736                 val |= TRANS_INTERLACED;
1737         else
1738                 val |= TRANS_PROGRESSIVE;
1739
1740         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1741         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1742                 DRM_ERROR("Failed to enable PCH transcoder\n");
1743 }
1744
1745 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1746                                             enum pipe pipe)
1747 {
1748         int reg;
1749         u32 val;
1750
1751         /* FDI relies on the transcoder */
1752         assert_fdi_tx_disabled(dev_priv, pipe);
1753         assert_fdi_rx_disabled(dev_priv, pipe);
1754
1755         /* Ports must be off as well */
1756         assert_pch_ports_disabled(dev_priv, pipe);
1757
1758         reg = TRANSCONF(pipe);
1759         val = I915_READ(reg);
1760         val &= ~TRANS_ENABLE;
1761         I915_WRITE(reg, val);
1762         /* wait for PCH transcoder off, transcoder state */
1763         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1764                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1765 }
1766
1767 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1768                                        enum pipe pipe)
1769 {
1770         int reg;
1771         u32 val;
1772
1773         /* FDI relies on the transcoder */
1774         assert_fdi_tx_disabled(dev_priv, pipe);
1775         assert_fdi_rx_disabled(dev_priv, pipe);
1776
1777         reg = TRANSCONF(pipe);
1778         val = I915_READ(reg);
1779         val &= ~TRANS_ENABLE;
1780         I915_WRITE(reg, val);
1781         /* wait for PCH transcoder off, transcoder state */
1782         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1783                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1784 }
1785
1786 /**
1787  * intel_enable_pipe - enable a pipe, asserting requirements
1788  * @dev_priv: i915 private structure
1789  * @pipe: pipe to enable
1790  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1791  *
1792  * Enable @pipe, making sure that various hardware specific requirements
1793  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1794  *
1795  * @pipe should be %PIPE_A or %PIPE_B.
1796  *
1797  * Will wait until the pipe is actually running (i.e. first vblank) before
1798  * returning.
1799  */
1800 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1801                               bool pch_port)
1802 {
1803         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1804                                                                       pipe);
1805         int reg;
1806         u32 val;
1807
1808         /*
1809          * A pipe without a PLL won't actually be able to drive bits from
1810          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1811          * need the check.
1812          */
1813         if (!HAS_PCH_SPLIT(dev_priv->dev))
1814                 assert_pll_enabled(dev_priv, pipe);
1815         else {
1816                 if (pch_port) {
1817                         /* if driving the PCH, we need FDI enabled */
1818                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1819                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1820                 }
1821                 /* FIXME: assert CPU port conditions for SNB+ */
1822         }
1823
1824         reg = PIPECONF(cpu_transcoder);
1825         val = I915_READ(reg);
1826         if (val & PIPECONF_ENABLE)
1827                 return;
1828
1829         I915_WRITE(reg, val | PIPECONF_ENABLE);
1830         intel_wait_for_vblank(dev_priv->dev, pipe);
1831 }
1832
1833 /**
1834  * intel_disable_pipe - disable a pipe, asserting requirements
1835  * @dev_priv: i915 private structure
1836  * @pipe: pipe to disable
1837  *
1838  * Disable @pipe, making sure that various hardware specific requirements
1839  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1840  *
1841  * @pipe should be %PIPE_A or %PIPE_B.
1842  *
1843  * Will wait until the pipe has shut down before returning.
1844  */
1845 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1846                                enum pipe pipe)
1847 {
1848         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1849                                                                       pipe);
1850         int reg;
1851         u32 val;
1852
1853         /*
1854          * Make sure planes won't keep trying to pump pixels to us,
1855          * or we might hang the display.
1856          */
1857         assert_planes_disabled(dev_priv, pipe);
1858
1859         /* Don't disable pipe A or pipe A PLLs if needed */
1860         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1861                 return;
1862
1863         reg = PIPECONF(cpu_transcoder);
1864         val = I915_READ(reg);
1865         if ((val & PIPECONF_ENABLE) == 0)
1866                 return;
1867
1868         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1869         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1870 }
1871
1872 /*
1873  * Plane regs are double buffered, going from enabled->disabled needs a
1874  * trigger in order to latch.  The display address reg provides this.
1875  */
1876 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1877                                       enum plane plane)
1878 {
1879         if (dev_priv->info->gen >= 4)
1880                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1881         else
1882                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1883 }
1884
1885 /**
1886  * intel_enable_plane - enable a display plane on a given pipe
1887  * @dev_priv: i915 private structure
1888  * @plane: plane to enable
1889  * @pipe: pipe being fed
1890  *
1891  * Enable @plane on @pipe, making sure that @pipe is running first.
1892  */
1893 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1894                                enum plane plane, enum pipe pipe)
1895 {
1896         int reg;
1897         u32 val;
1898
1899         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1900         assert_pipe_enabled(dev_priv, pipe);
1901
1902         reg = DSPCNTR(plane);
1903         val = I915_READ(reg);
1904         if (val & DISPLAY_PLANE_ENABLE)
1905                 return;
1906
1907         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1908         intel_flush_display_plane(dev_priv, plane);
1909         intel_wait_for_vblank(dev_priv->dev, pipe);
1910 }
1911
1912 /**
1913  * intel_disable_plane - disable a display plane
1914  * @dev_priv: i915 private structure
1915  * @plane: plane to disable
1916  * @pipe: pipe consuming the data
1917  *
1918  * Disable @plane; should be an independent operation.
1919  */
1920 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1921                                 enum plane plane, enum pipe pipe)
1922 {
1923         int reg;
1924         u32 val;
1925
1926         reg = DSPCNTR(plane);
1927         val = I915_READ(reg);
1928         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1929                 return;
1930
1931         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1932         intel_flush_display_plane(dev_priv, plane);
1933         intel_wait_for_vblank(dev_priv->dev, pipe);
1934 }
1935
1936 int
1937 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1938                            struct drm_i915_gem_object *obj,
1939                            struct intel_ring_buffer *pipelined)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942         u32 alignment;
1943         int ret;
1944
1945         switch (obj->tiling_mode) {
1946         case I915_TILING_NONE:
1947                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1948                         alignment = 128 * 1024;
1949                 else if (INTEL_INFO(dev)->gen >= 4)
1950                         alignment = 4 * 1024;
1951                 else
1952                         alignment = 64 * 1024;
1953                 break;
1954         case I915_TILING_X:
1955                 /* pin() will align the object as required by fence */
1956                 alignment = 0;
1957                 break;
1958         case I915_TILING_Y:
1959                 /* FIXME: Is this true? */
1960                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1961                 return -EINVAL;
1962         default:
1963                 BUG();
1964         }
1965
1966         dev_priv->mm.interruptible = false;
1967         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1968         if (ret)
1969                 goto err_interruptible;
1970
1971         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1972          * fence, whereas 965+ only requires a fence if using
1973          * framebuffer compression.  For simplicity, we always install
1974          * a fence as the cost is not that onerous.
1975          */
1976         ret = i915_gem_object_get_fence(obj);
1977         if (ret)
1978                 goto err_unpin;
1979
1980         i915_gem_object_pin_fence(obj);
1981
1982         dev_priv->mm.interruptible = true;
1983         return 0;
1984
1985 err_unpin:
1986         i915_gem_object_unpin(obj);
1987 err_interruptible:
1988         dev_priv->mm.interruptible = true;
1989         return ret;
1990 }
1991
1992 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1993 {
1994         i915_gem_object_unpin_fence(obj);
1995         i915_gem_object_unpin(obj);
1996 }
1997
1998 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1999  * is assumed to be a power-of-two. */
2000 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2001                                                unsigned int bpp,
2002                                                unsigned int pitch)
2003 {
2004         int tile_rows, tiles;
2005
2006         tile_rows = *y / 8;
2007         *y %= 8;
2008         tiles = *x / (512/bpp);
2009         *x %= 512/bpp;
2010
2011         return tile_rows * pitch * 8 + tiles * 4096;
2012 }
2013
2014 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2015                              int x, int y)
2016 {
2017         struct drm_device *dev = crtc->dev;
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2020         struct intel_framebuffer *intel_fb;
2021         struct drm_i915_gem_object *obj;
2022         int plane = intel_crtc->plane;
2023         unsigned long linear_offset;
2024         u32 dspcntr;
2025         u32 reg;
2026
2027         switch (plane) {
2028         case 0:
2029         case 1:
2030                 break;
2031         default:
2032                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2033                 return -EINVAL;
2034         }
2035
2036         intel_fb = to_intel_framebuffer(fb);
2037         obj = intel_fb->obj;
2038
2039         reg = DSPCNTR(plane);
2040         dspcntr = I915_READ(reg);
2041         /* Mask out pixel format bits in case we change it */
2042         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2043         switch (fb->pixel_format) {
2044         case DRM_FORMAT_C8:
2045                 dspcntr |= DISPPLANE_8BPP;
2046                 break;
2047         case DRM_FORMAT_XRGB1555:
2048         case DRM_FORMAT_ARGB1555:
2049                 dspcntr |= DISPPLANE_BGRX555;
2050                 break;
2051         case DRM_FORMAT_RGB565:
2052                 dspcntr |= DISPPLANE_BGRX565;
2053                 break;
2054         case DRM_FORMAT_XRGB8888:
2055         case DRM_FORMAT_ARGB8888:
2056                 dspcntr |= DISPPLANE_BGRX888;
2057                 break;
2058         case DRM_FORMAT_XBGR8888:
2059         case DRM_FORMAT_ABGR8888:
2060                 dspcntr |= DISPPLANE_RGBX888;
2061                 break;
2062         case DRM_FORMAT_XRGB2101010:
2063         case DRM_FORMAT_ARGB2101010:
2064                 dspcntr |= DISPPLANE_BGRX101010;
2065                 break;
2066         case DRM_FORMAT_XBGR2101010:
2067         case DRM_FORMAT_ABGR2101010:
2068                 dspcntr |= DISPPLANE_RGBX101010;
2069                 break;
2070         default:
2071                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2072                 return -EINVAL;
2073         }
2074
2075         if (INTEL_INFO(dev)->gen >= 4) {
2076                 if (obj->tiling_mode != I915_TILING_NONE)
2077                         dspcntr |= DISPPLANE_TILED;
2078                 else
2079                         dspcntr &= ~DISPPLANE_TILED;
2080         }
2081
2082         I915_WRITE(reg, dspcntr);
2083
2084         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2085
2086         if (INTEL_INFO(dev)->gen >= 4) {
2087                 intel_crtc->dspaddr_offset =
2088                         intel_gen4_compute_offset_xtiled(&x, &y,
2089                                                          fb->bits_per_pixel / 8,
2090                                                          fb->pitches[0]);
2091                 linear_offset -= intel_crtc->dspaddr_offset;
2092         } else {
2093                 intel_crtc->dspaddr_offset = linear_offset;
2094         }
2095
2096         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2097                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2098         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2099         if (INTEL_INFO(dev)->gen >= 4) {
2100                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2102                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         } else
2105                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2106         POSTING_READ(reg);
2107
2108         return 0;
2109 }
2110
2111 static int ironlake_update_plane(struct drm_crtc *crtc,
2112                                  struct drm_framebuffer *fb, int x, int y)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2117         struct intel_framebuffer *intel_fb;
2118         struct drm_i915_gem_object *obj;
2119         int plane = intel_crtc->plane;
2120         unsigned long linear_offset;
2121         u32 dspcntr;
2122         u32 reg;
2123
2124         switch (plane) {
2125         case 0:
2126         case 1:
2127         case 2:
2128                 break;
2129         default:
2130                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2131                 return -EINVAL;
2132         }
2133
2134         intel_fb = to_intel_framebuffer(fb);
2135         obj = intel_fb->obj;
2136
2137         reg = DSPCNTR(plane);
2138         dspcntr = I915_READ(reg);
2139         /* Mask out pixel format bits in case we change it */
2140         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2141         switch (fb->pixel_format) {
2142         case DRM_FORMAT_C8:
2143                 dspcntr |= DISPPLANE_8BPP;
2144                 break;
2145         case DRM_FORMAT_RGB565:
2146                 dspcntr |= DISPPLANE_BGRX565;
2147                 break;
2148         case DRM_FORMAT_XRGB8888:
2149         case DRM_FORMAT_ARGB8888:
2150                 dspcntr |= DISPPLANE_BGRX888;
2151                 break;
2152         case DRM_FORMAT_XBGR8888:
2153         case DRM_FORMAT_ABGR8888:
2154                 dspcntr |= DISPPLANE_RGBX888;
2155                 break;
2156         case DRM_FORMAT_XRGB2101010:
2157         case DRM_FORMAT_ARGB2101010:
2158                 dspcntr |= DISPPLANE_BGRX101010;
2159                 break;
2160         case DRM_FORMAT_XBGR2101010:
2161         case DRM_FORMAT_ABGR2101010:
2162                 dspcntr |= DISPPLANE_RGBX101010;
2163                 break;
2164         default:
2165                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2166                 return -EINVAL;
2167         }
2168
2169         if (obj->tiling_mode != I915_TILING_NONE)
2170                 dspcntr |= DISPPLANE_TILED;
2171         else
2172                 dspcntr &= ~DISPPLANE_TILED;
2173
2174         /* must disable */
2175         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2176
2177         I915_WRITE(reg, dspcntr);
2178
2179         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2180         intel_crtc->dspaddr_offset =
2181                 intel_gen4_compute_offset_xtiled(&x, &y,
2182                                                  fb->bits_per_pixel / 8,
2183                                                  fb->pitches[0]);
2184         linear_offset -= intel_crtc->dspaddr_offset;
2185
2186         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2187                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2188         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2189         I915_MODIFY_DISPBASE(DSPSURF(plane),
2190                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2191         if (IS_HASWELL(dev)) {
2192                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2193         } else {
2194                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2195                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2196         }
2197         POSTING_READ(reg);
2198
2199         return 0;
2200 }
2201
2202 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2203 static int
2204 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2205                            int x, int y, enum mode_set_atomic state)
2206 {
2207         struct drm_device *dev = crtc->dev;
2208         struct drm_i915_private *dev_priv = dev->dev_private;
2209
2210         if (dev_priv->display.disable_fbc)
2211                 dev_priv->display.disable_fbc(dev);
2212         intel_increase_pllclock(crtc);
2213
2214         return dev_priv->display.update_plane(crtc, fb, x, y);
2215 }
2216
2217 static int
2218 intel_finish_fb(struct drm_framebuffer *old_fb)
2219 {
2220         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2221         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2222         bool was_interruptible = dev_priv->mm.interruptible;
2223         int ret;
2224
2225         wait_event(dev_priv->pending_flip_queue,
2226                    atomic_read(&dev_priv->mm.wedged) ||
2227                    atomic_read(&obj->pending_flip) == 0);
2228
2229         /* Big Hammer, we also need to ensure that any pending
2230          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231          * current scanout is retired before unpinning the old
2232          * framebuffer.
2233          *
2234          * This should only fail upon a hung GPU, in which case we
2235          * can safely continue.
2236          */
2237         dev_priv->mm.interruptible = false;
2238         ret = i915_gem_object_finish_gpu(obj);
2239         dev_priv->mm.interruptible = was_interruptible;
2240
2241         return ret;
2242 }
2243
2244 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245 {
2246         struct drm_device *dev = crtc->dev;
2247         struct drm_i915_master_private *master_priv;
2248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250         if (!dev->primary->master)
2251                 return;
2252
2253         master_priv = dev->primary->master->driver_priv;
2254         if (!master_priv->sarea_priv)
2255                 return;
2256
2257         switch (intel_crtc->pipe) {
2258         case 0:
2259                 master_priv->sarea_priv->pipeA_x = x;
2260                 master_priv->sarea_priv->pipeA_y = y;
2261                 break;
2262         case 1:
2263                 master_priv->sarea_priv->pipeB_x = x;
2264                 master_priv->sarea_priv->pipeB_y = y;
2265                 break;
2266         default:
2267                 break;
2268         }
2269 }
2270
2271 static int
2272 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2273                     struct drm_framebuffer *fb)
2274 {
2275         struct drm_device *dev = crtc->dev;
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2278         struct drm_framebuffer *old_fb;
2279         int ret;
2280
2281         /* no fb bound */
2282         if (!fb) {
2283                 DRM_ERROR("No FB bound\n");
2284                 return 0;
2285         }
2286
2287         if(intel_crtc->plane > dev_priv->num_pipe) {
2288                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289                                 intel_crtc->plane,
2290                                 dev_priv->num_pipe);
2291                 return -EINVAL;
2292         }
2293
2294         mutex_lock(&dev->struct_mutex);
2295         ret = intel_pin_and_fence_fb_obj(dev,
2296                                          to_intel_framebuffer(fb)->obj,
2297                                          NULL);
2298         if (ret != 0) {
2299                 mutex_unlock(&dev->struct_mutex);
2300                 DRM_ERROR("pin & fence failed\n");
2301                 return ret;
2302         }
2303
2304         if (crtc->fb)
2305                 intel_finish_fb(crtc->fb);
2306
2307         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2308         if (ret) {
2309                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2310                 mutex_unlock(&dev->struct_mutex);
2311                 DRM_ERROR("failed to update base address\n");
2312                 return ret;
2313         }
2314
2315         old_fb = crtc->fb;
2316         crtc->fb = fb;
2317         crtc->x = x;
2318         crtc->y = y;
2319
2320         if (old_fb) {
2321                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2322                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2323         }
2324
2325         intel_update_fbc(dev);
2326         mutex_unlock(&dev->struct_mutex);
2327
2328         intel_crtc_update_sarea_pos(crtc, x, y);
2329
2330         return 0;
2331 }
2332
2333 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2334 {
2335         struct drm_device *dev = crtc->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         u32 dpa_ctl;
2338
2339         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2340         dpa_ctl = I915_READ(DP_A);
2341         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2342
2343         if (clock < 200000) {
2344                 u32 temp;
2345                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2346                 /* workaround for 160Mhz:
2347                    1) program 0x4600c bits 15:0 = 0x8124
2348                    2) program 0x46010 bit 0 = 1
2349                    3) program 0x46034 bit 24 = 1
2350                    4) program 0x64000 bit 14 = 1
2351                    */
2352                 temp = I915_READ(0x4600c);
2353                 temp &= 0xffff0000;
2354                 I915_WRITE(0x4600c, temp | 0x8124);
2355
2356                 temp = I915_READ(0x46010);
2357                 I915_WRITE(0x46010, temp | 1);
2358
2359                 temp = I915_READ(0x46034);
2360                 I915_WRITE(0x46034, temp | (1 << 24));
2361         } else {
2362                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2363         }
2364         I915_WRITE(DP_A, dpa_ctl);
2365
2366         POSTING_READ(DP_A);
2367         udelay(500);
2368 }
2369
2370 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2371 {
2372         struct drm_device *dev = crtc->dev;
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2375         int pipe = intel_crtc->pipe;
2376         u32 reg, temp;
2377
2378         /* enable normal train */
2379         reg = FDI_TX_CTL(pipe);
2380         temp = I915_READ(reg);
2381         if (IS_IVYBRIDGE(dev)) {
2382                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2384         } else {
2385                 temp &= ~FDI_LINK_TRAIN_NONE;
2386                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2387         }
2388         I915_WRITE(reg, temp);
2389
2390         reg = FDI_RX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         if (HAS_PCH_CPT(dev)) {
2393                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2394                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2395         } else {
2396                 temp &= ~FDI_LINK_TRAIN_NONE;
2397                 temp |= FDI_LINK_TRAIN_NONE;
2398         }
2399         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2400
2401         /* wait one idle pattern time */
2402         POSTING_READ(reg);
2403         udelay(1000);
2404
2405         /* IVB wants error correction enabled */
2406         if (IS_IVYBRIDGE(dev))
2407                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2408                            FDI_FE_ERRC_ENABLE);
2409 }
2410
2411 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2412 {
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         u32 flags = I915_READ(SOUTH_CHICKEN1);
2415
2416         flags |= FDI_PHASE_SYNC_OVR(pipe);
2417         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2418         flags |= FDI_PHASE_SYNC_EN(pipe);
2419         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2420         POSTING_READ(SOUTH_CHICKEN1);
2421 }
2422
2423 static void ivb_modeset_global_resources(struct drm_device *dev)
2424 {
2425         struct drm_i915_private *dev_priv = dev->dev_private;
2426         struct intel_crtc *pipe_B_crtc =
2427                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2428         struct intel_crtc *pipe_C_crtc =
2429                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2430         uint32_t temp;
2431
2432         /* When everything is off disable fdi C so that we could enable fdi B
2433          * with all lanes. XXX: This misses the case where a pipe is not using
2434          * any pch resources and so doesn't need any fdi lanes. */
2435         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2436                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2437                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2438
2439                 temp = I915_READ(SOUTH_CHICKEN1);
2440                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2441                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2442                 I915_WRITE(SOUTH_CHICKEN1, temp);
2443         }
2444 }
2445
2446 /* The FDI link training functions for ILK/Ibexpeak. */
2447 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2448 {
2449         struct drm_device *dev = crtc->dev;
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2452         int pipe = intel_crtc->pipe;
2453         int plane = intel_crtc->plane;
2454         u32 reg, temp, tries;
2455
2456         /* FDI needs bits from pipe & plane first */
2457         assert_pipe_enabled(dev_priv, pipe);
2458         assert_plane_enabled(dev_priv, plane);
2459
2460         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2461            for train result */
2462         reg = FDI_RX_IMR(pipe);
2463         temp = I915_READ(reg);
2464         temp &= ~FDI_RX_SYMBOL_LOCK;
2465         temp &= ~FDI_RX_BIT_LOCK;
2466         I915_WRITE(reg, temp);
2467         I915_READ(reg);
2468         udelay(150);
2469
2470         /* enable CPU FDI TX and PCH FDI RX */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~(7 << 19);
2474         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475         temp &= ~FDI_LINK_TRAIN_NONE;
2476         temp |= FDI_LINK_TRAIN_PATTERN_1;
2477         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2478
2479         reg = FDI_RX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~FDI_LINK_TRAIN_NONE;
2482         temp |= FDI_LINK_TRAIN_PATTERN_1;
2483         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485         POSTING_READ(reg);
2486         udelay(150);
2487
2488         /* Ironlake workaround, enable clock pointer after FDI enable*/
2489         if (HAS_PCH_IBX(dev)) {
2490                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2491                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2492                            FDI_RX_PHASE_SYNC_POINTER_EN);
2493         }
2494
2495         reg = FDI_RX_IIR(pipe);
2496         for (tries = 0; tries < 5; tries++) {
2497                 temp = I915_READ(reg);
2498                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500                 if ((temp & FDI_RX_BIT_LOCK)) {
2501                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2502                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2503                         break;
2504                 }
2505         }
2506         if (tries == 5)
2507                 DRM_ERROR("FDI train 1 fail!\n");
2508
2509         /* Train 2 */
2510         reg = FDI_TX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_LINK_TRAIN_NONE;
2513         temp |= FDI_LINK_TRAIN_PATTERN_2;
2514         I915_WRITE(reg, temp);
2515
2516         reg = FDI_RX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_LINK_TRAIN_NONE;
2519         temp |= FDI_LINK_TRAIN_PATTERN_2;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         reg = FDI_RX_IIR(pipe);
2526         for (tries = 0; tries < 5; tries++) {
2527                 temp = I915_READ(reg);
2528                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529
2530                 if (temp & FDI_RX_SYMBOL_LOCK) {
2531                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2532                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2533                         break;
2534                 }
2535         }
2536         if (tries == 5)
2537                 DRM_ERROR("FDI train 2 fail!\n");
2538
2539         DRM_DEBUG_KMS("FDI train done\n");
2540
2541 }
2542
2543 static const int snb_b_fdi_train_param[] = {
2544         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2545         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2546         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2547         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2548 };
2549
2550 /* The FDI link training functions for SNB/Cougarpoint. */
2551 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556         int pipe = intel_crtc->pipe;
2557         u32 reg, temp, i, retry;
2558
2559         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2560            for train result */
2561         reg = FDI_RX_IMR(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_RX_SYMBOL_LOCK;
2564         temp &= ~FDI_RX_BIT_LOCK;
2565         I915_WRITE(reg, temp);
2566
2567         POSTING_READ(reg);
2568         udelay(150);
2569
2570         /* enable CPU FDI TX and PCH FDI RX */
2571         reg = FDI_TX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~(7 << 19);
2574         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2575         temp &= ~FDI_LINK_TRAIN_NONE;
2576         temp |= FDI_LINK_TRAIN_PATTERN_1;
2577         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2578         /* SNB-B */
2579         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2580         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2581
2582         I915_WRITE(FDI_RX_MISC(pipe),
2583                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         if (HAS_PCH_CPT(dev)) {
2588                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         } else {
2591                 temp &= ~FDI_LINK_TRAIN_NONE;
2592                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2593         }
2594         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2595
2596         POSTING_READ(reg);
2597         udelay(150);
2598
2599         if (HAS_PCH_CPT(dev))
2600                 cpt_phase_pointer_enable(dev, pipe);
2601
2602         for (i = 0; i < 4; i++) {
2603                 reg = FDI_TX_CTL(pipe);
2604                 temp = I915_READ(reg);
2605                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2606                 temp |= snb_b_fdi_train_param[i];
2607                 I915_WRITE(reg, temp);
2608
2609                 POSTING_READ(reg);
2610                 udelay(500);
2611
2612                 for (retry = 0; retry < 5; retry++) {
2613                         reg = FDI_RX_IIR(pipe);
2614                         temp = I915_READ(reg);
2615                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2616                         if (temp & FDI_RX_BIT_LOCK) {
2617                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2618                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2619                                 break;
2620                         }
2621                         udelay(50);
2622                 }
2623                 if (retry < 5)
2624                         break;
2625         }
2626         if (i == 4)
2627                 DRM_ERROR("FDI train 1 fail!\n");
2628
2629         /* Train 2 */
2630         reg = FDI_TX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~FDI_LINK_TRAIN_NONE;
2633         temp |= FDI_LINK_TRAIN_PATTERN_2;
2634         if (IS_GEN6(dev)) {
2635                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2636                 /* SNB-B */
2637                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2638         }
2639         I915_WRITE(reg, temp);
2640
2641         reg = FDI_RX_CTL(pipe);
2642         temp = I915_READ(reg);
2643         if (HAS_PCH_CPT(dev)) {
2644                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2646         } else {
2647                 temp &= ~FDI_LINK_TRAIN_NONE;
2648                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2649         }
2650         I915_WRITE(reg, temp);
2651
2652         POSTING_READ(reg);
2653         udelay(150);
2654
2655         for (i = 0; i < 4; i++) {
2656                 reg = FDI_TX_CTL(pipe);
2657                 temp = I915_READ(reg);
2658                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2659                 temp |= snb_b_fdi_train_param[i];
2660                 I915_WRITE(reg, temp);
2661
2662                 POSTING_READ(reg);
2663                 udelay(500);
2664
2665                 for (retry = 0; retry < 5; retry++) {
2666                         reg = FDI_RX_IIR(pipe);
2667                         temp = I915_READ(reg);
2668                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2669                         if (temp & FDI_RX_SYMBOL_LOCK) {
2670                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2671                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2672                                 break;
2673                         }
2674                         udelay(50);
2675                 }
2676                 if (retry < 5)
2677                         break;
2678         }
2679         if (i == 4)
2680                 DRM_ERROR("FDI train 2 fail!\n");
2681
2682         DRM_DEBUG_KMS("FDI train done.\n");
2683 }
2684
2685 /* Manual link training for Ivy Bridge A0 parts */
2686 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2687 {
2688         struct drm_device *dev = crtc->dev;
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691         int pipe = intel_crtc->pipe;
2692         u32 reg, temp, i;
2693
2694         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2695            for train result */
2696         reg = FDI_RX_IMR(pipe);
2697         temp = I915_READ(reg);
2698         temp &= ~FDI_RX_SYMBOL_LOCK;
2699         temp &= ~FDI_RX_BIT_LOCK;
2700         I915_WRITE(reg, temp);
2701
2702         POSTING_READ(reg);
2703         udelay(150);
2704
2705         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2706                       I915_READ(FDI_RX_IIR(pipe)));
2707
2708         /* enable CPU FDI TX and PCH FDI RX */
2709         reg = FDI_TX_CTL(pipe);
2710         temp = I915_READ(reg);
2711         temp &= ~(7 << 19);
2712         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2713         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2714         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2715         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717         temp |= FDI_COMPOSITE_SYNC;
2718         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2719
2720         I915_WRITE(FDI_RX_MISC(pipe),
2721                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2722
2723         reg = FDI_RX_CTL(pipe);
2724         temp = I915_READ(reg);
2725         temp &= ~FDI_LINK_TRAIN_AUTO;
2726         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2727         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2728         temp |= FDI_COMPOSITE_SYNC;
2729         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2730
2731         POSTING_READ(reg);
2732         udelay(150);
2733
2734         if (HAS_PCH_CPT(dev))
2735                 cpt_phase_pointer_enable(dev, pipe);
2736
2737         for (i = 0; i < 4; i++) {
2738                 reg = FDI_TX_CTL(pipe);
2739                 temp = I915_READ(reg);
2740                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741                 temp |= snb_b_fdi_train_param[i];
2742                 I915_WRITE(reg, temp);
2743
2744                 POSTING_READ(reg);
2745                 udelay(500);
2746
2747                 reg = FDI_RX_IIR(pipe);
2748                 temp = I915_READ(reg);
2749                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2750
2751                 if (temp & FDI_RX_BIT_LOCK ||
2752                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2753                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2754                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2755                         break;
2756                 }
2757         }
2758         if (i == 4)
2759                 DRM_ERROR("FDI train 1 fail!\n");
2760
2761         /* Train 2 */
2762         reg = FDI_TX_CTL(pipe);
2763         temp = I915_READ(reg);
2764         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2765         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2766         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2767         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2773         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2774         I915_WRITE(reg, temp);
2775
2776         POSTING_READ(reg);
2777         udelay(150);
2778
2779         for (i = 0; i < 4; i++) {
2780                 reg = FDI_TX_CTL(pipe);
2781                 temp = I915_READ(reg);
2782                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783                 temp |= snb_b_fdi_train_param[i];
2784                 I915_WRITE(reg, temp);
2785
2786                 POSTING_READ(reg);
2787                 udelay(500);
2788
2789                 reg = FDI_RX_IIR(pipe);
2790                 temp = I915_READ(reg);
2791                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2792
2793                 if (temp & FDI_RX_SYMBOL_LOCK) {
2794                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2795                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2796                         break;
2797                 }
2798         }
2799         if (i == 4)
2800                 DRM_ERROR("FDI train 2 fail!\n");
2801
2802         DRM_DEBUG_KMS("FDI train done.\n");
2803 }
2804
2805 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812
2813         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~((0x7 << 19) | (0x7 << 16));
2817         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(200);
2823
2824         /* Switch from Rawclk to PCDclk */
2825         temp = I915_READ(reg);
2826         I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828         POSTING_READ(reg);
2829         udelay(200);
2830
2831         /* On Haswell, the PLL configuration for ports and pipes is handled
2832          * separately, as part of DDI setup */
2833         if (!IS_HASWELL(dev)) {
2834                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835                 reg = FDI_TX_CTL(pipe);
2836                 temp = I915_READ(reg);
2837                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                         POSTING_READ(reg);
2841                         udelay(100);
2842                 }
2843         }
2844 }
2845
2846 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2847 {
2848         struct drm_device *dev = intel_crtc->base.dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* Switch from PCDclk to Rawclk */
2854         reg = FDI_RX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2857
2858         /* Disable CPU FDI TX PLL */
2859         reg = FDI_TX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2862
2863         POSTING_READ(reg);
2864         udelay(100);
2865
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2869
2870         /* Wait for the clocks to turn off. */
2871         POSTING_READ(reg);
2872         udelay(100);
2873 }
2874
2875 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2876 {
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         u32 flags = I915_READ(SOUTH_CHICKEN1);
2879
2880         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2881         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2882         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2883         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2884         POSTING_READ(SOUTH_CHICKEN1);
2885 }
2886 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2887 {
2888         struct drm_device *dev = crtc->dev;
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2891         int pipe = intel_crtc->pipe;
2892         u32 reg, temp;
2893
2894         /* disable CPU FDI tx and PCH FDI rx */
2895         reg = FDI_TX_CTL(pipe);
2896         temp = I915_READ(reg);
2897         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2898         POSTING_READ(reg);
2899
2900         reg = FDI_RX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         temp &= ~(0x7 << 16);
2903         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2904         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2905
2906         POSTING_READ(reg);
2907         udelay(100);
2908
2909         /* Ironlake workaround, disable clock pointer after downing FDI */
2910         if (HAS_PCH_IBX(dev)) {
2911                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2912                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2913                            I915_READ(FDI_RX_CHICKEN(pipe) &
2914                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2915         } else if (HAS_PCH_CPT(dev)) {
2916                 cpt_phase_pointer_disable(dev, pipe);
2917         }
2918
2919         /* still set train pattern 1 */
2920         reg = FDI_TX_CTL(pipe);
2921         temp = I915_READ(reg);
2922         temp &= ~FDI_LINK_TRAIN_NONE;
2923         temp |= FDI_LINK_TRAIN_PATTERN_1;
2924         I915_WRITE(reg, temp);
2925
2926         reg = FDI_RX_CTL(pipe);
2927         temp = I915_READ(reg);
2928         if (HAS_PCH_CPT(dev)) {
2929                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2930                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2931         } else {
2932                 temp &= ~FDI_LINK_TRAIN_NONE;
2933                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2934         }
2935         /* BPC in FDI rx is consistent with that in PIPECONF */
2936         temp &= ~(0x07 << 16);
2937         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2938         I915_WRITE(reg, temp);
2939
2940         POSTING_READ(reg);
2941         udelay(100);
2942 }
2943
2944 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2945 {
2946         struct drm_device *dev = crtc->dev;
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948         unsigned long flags;
2949         bool pending;
2950
2951         if (atomic_read(&dev_priv->mm.wedged))
2952                 return false;
2953
2954         spin_lock_irqsave(&dev->event_lock, flags);
2955         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2956         spin_unlock_irqrestore(&dev->event_lock, flags);
2957
2958         return pending;
2959 }
2960
2961 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2962 {
2963         struct drm_device *dev = crtc->dev;
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965
2966         if (crtc->fb == NULL)
2967                 return;
2968
2969         wait_event(dev_priv->pending_flip_queue,
2970                    !intel_crtc_has_pending_flip(crtc));
2971
2972         mutex_lock(&dev->struct_mutex);
2973         intel_finish_fb(crtc->fb);
2974         mutex_unlock(&dev->struct_mutex);
2975 }
2976
2977 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct intel_encoder *intel_encoder;
2981
2982         /*
2983          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2984          * must be driven by its own crtc; no sharing is possible.
2985          */
2986         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2987                 switch (intel_encoder->type) {
2988                 case INTEL_OUTPUT_EDP:
2989                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2990                                 return false;
2991                         continue;
2992                 }
2993         }
2994
2995         return true;
2996 }
2997
2998 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2999 {
3000         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3001 }
3002
3003 /* Program iCLKIP clock to the desired frequency */
3004 static void lpt_program_iclkip(struct drm_crtc *crtc)
3005 {
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3009         u32 temp;
3010
3011         /* It is necessary to ungate the pixclk gate prior to programming
3012          * the divisors, and gate it back when it is done.
3013          */
3014         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3015
3016         /* Disable SSCCTL */
3017         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3018                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3019                                         SBI_SSCCTL_DISABLE);
3020
3021         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3022         if (crtc->mode.clock == 20000) {
3023                 auxdiv = 1;
3024                 divsel = 0x41;
3025                 phaseinc = 0x20;
3026         } else {
3027                 /* The iCLK virtual clock root frequency is in MHz,
3028                  * but the crtc->mode.clock in in KHz. To get the divisors,
3029                  * it is necessary to divide one by another, so we
3030                  * convert the virtual clock precision to KHz here for higher
3031                  * precision.
3032                  */
3033                 u32 iclk_virtual_root_freq = 172800 * 1000;
3034                 u32 iclk_pi_range = 64;
3035                 u32 desired_divisor, msb_divisor_value, pi_value;
3036
3037                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3038                 msb_divisor_value = desired_divisor / iclk_pi_range;
3039                 pi_value = desired_divisor % iclk_pi_range;
3040
3041                 auxdiv = 0;
3042                 divsel = msb_divisor_value - 2;
3043                 phaseinc = pi_value;
3044         }
3045
3046         /* This should not happen with any sane values */
3047         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3048                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3049         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3050                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3051
3052         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3053                         crtc->mode.clock,
3054                         auxdiv,
3055                         divsel,
3056                         phasedir,
3057                         phaseinc);
3058
3059         /* Program SSCDIVINTPHASE6 */
3060         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3061         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3062         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3063         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3064         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3065         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3066         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3067
3068         intel_sbi_write(dev_priv,
3069                         SBI_SSCDIVINTPHASE6,
3070                         temp);
3071
3072         /* Program SSCAUXDIV */
3073         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3074         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3075         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3076         intel_sbi_write(dev_priv,
3077                         SBI_SSCAUXDIV6,
3078                         temp);
3079
3080
3081         /* Enable modulator and associated divider */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3083         temp &= ~SBI_SSCCTL_DISABLE;
3084         intel_sbi_write(dev_priv,
3085                         SBI_SSCCTL6,
3086                         temp);
3087
3088         /* Wait for initialization time */
3089         udelay(24);
3090
3091         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3092 }
3093
3094 /*
3095  * Enable PCH resources required for PCH ports:
3096  *   - PCH PLLs
3097  *   - FDI training & RX/TX
3098  *   - update transcoder timings
3099  *   - DP transcoding bits
3100  *   - transcoder
3101  */
3102 static void ironlake_pch_enable(struct drm_crtc *crtc)
3103 {
3104         struct drm_device *dev = crtc->dev;
3105         struct drm_i915_private *dev_priv = dev->dev_private;
3106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107         int pipe = intel_crtc->pipe;
3108         u32 reg, temp;
3109
3110         assert_transcoder_disabled(dev_priv, pipe);
3111
3112         /* Write the TU size bits before fdi link training, so that error
3113          * detection works. */
3114         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3115                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3116
3117         /* For PCH output, training FDI link */
3118         dev_priv->display.fdi_link_train(crtc);
3119
3120         /* XXX: pch pll's can be enabled any time before we enable the PCH
3121          * transcoder, and we actually should do this to not upset any PCH
3122          * transcoder that already use the clock when we share it.
3123          *
3124          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3125          * unconditionally resets the pll - we need that to have the right LVDS
3126          * enable sequence. */
3127         ironlake_enable_pch_pll(intel_crtc);
3128
3129         if (HAS_PCH_CPT(dev)) {
3130                 u32 sel;
3131
3132                 temp = I915_READ(PCH_DPLL_SEL);
3133                 switch (pipe) {
3134                 default:
3135                 case 0:
3136                         temp |= TRANSA_DPLL_ENABLE;
3137                         sel = TRANSA_DPLLB_SEL;
3138                         break;
3139                 case 1:
3140                         temp |= TRANSB_DPLL_ENABLE;
3141                         sel = TRANSB_DPLLB_SEL;
3142                         break;
3143                 case 2:
3144                         temp |= TRANSC_DPLL_ENABLE;
3145                         sel = TRANSC_DPLLB_SEL;
3146                         break;
3147                 }
3148                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3149                         temp |= sel;
3150                 else
3151                         temp &= ~sel;
3152                 I915_WRITE(PCH_DPLL_SEL, temp);
3153         }
3154
3155         /* set transcoder timing, panel must allow it */
3156         assert_panel_unlocked(dev_priv, pipe);
3157         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3158         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3159         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3160
3161         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3162         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3163         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3164         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3165
3166         intel_fdi_normal_train(crtc);
3167
3168         /* For PCH DP, enable TRANS_DP_CTL */
3169         if (HAS_PCH_CPT(dev) &&
3170             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3171              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3172                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3173                 reg = TRANS_DP_CTL(pipe);
3174                 temp = I915_READ(reg);
3175                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3176                           TRANS_DP_SYNC_MASK |
3177                           TRANS_DP_BPC_MASK);
3178                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3179                          TRANS_DP_ENH_FRAMING);
3180                 temp |= bpc << 9; /* same format but at 11:9 */
3181
3182                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3183                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3184                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3185                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3186
3187                 switch (intel_trans_dp_port_sel(crtc)) {
3188                 case PCH_DP_B:
3189                         temp |= TRANS_DP_PORT_SEL_B;
3190                         break;
3191                 case PCH_DP_C:
3192                         temp |= TRANS_DP_PORT_SEL_C;
3193                         break;
3194                 case PCH_DP_D:
3195                         temp |= TRANS_DP_PORT_SEL_D;
3196                         break;
3197                 default:
3198                         BUG();
3199                 }
3200
3201                 I915_WRITE(reg, temp);
3202         }
3203
3204         ironlake_enable_pch_transcoder(dev_priv, pipe);
3205 }
3206
3207 static void lpt_pch_enable(struct drm_crtc *crtc)
3208 {
3209         struct drm_device *dev = crtc->dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212         int pipe = intel_crtc->pipe;
3213         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3214
3215         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3216
3217         /* Write the TU size bits before fdi link training, so that error
3218          * detection works. */
3219         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3220                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3221
3222         /* For PCH output, training FDI link */
3223         dev_priv->display.fdi_link_train(crtc);
3224
3225         lpt_program_iclkip(crtc);
3226
3227         /* Set transcoder timing. */
3228         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3231
3232         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3236
3237         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3238 }
3239
3240 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241 {
3242         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244         if (pll == NULL)
3245                 return;
3246
3247         if (pll->refcount == 0) {
3248                 WARN(1, "bad PCH PLL refcount\n");
3249                 return;
3250         }
3251
3252         --pll->refcount;
3253         intel_crtc->pch_pll = NULL;
3254 }
3255
3256 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257 {
3258         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259         struct intel_pch_pll *pll;
3260         int i;
3261
3262         pll = intel_crtc->pch_pll;
3263         if (pll) {
3264                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265                               intel_crtc->base.base.id, pll->pll_reg);
3266                 goto prepare;
3267         }
3268
3269         if (HAS_PCH_IBX(dev_priv->dev)) {
3270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271                 i = intel_crtc->pipe;
3272                 pll = &dev_priv->pch_plls[i];
3273
3274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275                               intel_crtc->base.base.id, pll->pll_reg);
3276
3277                 goto found;
3278         }
3279
3280         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 /* Only want to check enabled timings first */
3284                 if (pll->refcount == 0)
3285                         continue;
3286
3287                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288                     fp == I915_READ(pll->fp0_reg)) {
3289                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290                                       intel_crtc->base.base.id,
3291                                       pll->pll_reg, pll->refcount, pll->active);
3292
3293                         goto found;
3294                 }
3295         }
3296
3297         /* Ok no matching timings, maybe there's a free one? */
3298         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299                 pll = &dev_priv->pch_plls[i];
3300                 if (pll->refcount == 0) {
3301                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302                                       intel_crtc->base.base.id, pll->pll_reg);
3303                         goto found;
3304                 }
3305         }
3306
3307         return NULL;
3308
3309 found:
3310         intel_crtc->pch_pll = pll;
3311         pll->refcount++;
3312         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313 prepare: /* separate function? */
3314         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3315
3316         /* Wait for the clocks to stabilize before rewriting the regs */
3317         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3318         POSTING_READ(pll->pll_reg);
3319         udelay(150);
3320
3321         I915_WRITE(pll->fp0_reg, fp);
3322         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3323         pll->on = false;
3324         return pll;
3325 }
3326
3327 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 /* Without this, mode sets may fail silently on FDI */
3337                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3338                 udelay(250);
3339                 I915_WRITE(tc2reg, 0);
3340                 if (wait_for(I915_READ(dslreg) != temp, 5))
3341                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3342         }
3343 }
3344
3345 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353         u32 temp;
3354         bool is_pch_port;
3355
3356         WARN_ON(!crtc->enabled);
3357
3358         if (intel_crtc->active)
3359                 return;
3360
3361         intel_crtc->active = true;
3362         intel_update_watermarks(dev);
3363
3364         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3365                 temp = I915_READ(PCH_LVDS);
3366                 if ((temp & LVDS_PORT_EN) == 0)
3367                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3368         }
3369
3370         is_pch_port = ironlake_crtc_driving_pch(crtc);
3371
3372         if (is_pch_port) {
3373                 /* Note: FDI PLL enabling _must_ be done before we enable the
3374                  * cpu pipes, hence this is separate from all the other fdi/pch
3375                  * enabling. */
3376                 ironlake_fdi_pll_enable(intel_crtc);
3377         } else {
3378                 assert_fdi_tx_disabled(dev_priv, pipe);
3379                 assert_fdi_rx_disabled(dev_priv, pipe);
3380         }
3381
3382         for_each_encoder_on_crtc(dev, crtc, encoder)
3383                 if (encoder->pre_enable)
3384                         encoder->pre_enable(encoder);
3385
3386         /* Enable panel fitting for LVDS */
3387         if (dev_priv->pch_pf_size &&
3388             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3389                 /* Force use of hard-coded filter coefficients
3390                  * as some pre-programmed values are broken,
3391                  * e.g. x201.
3392                  */
3393                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3394                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3395                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3396         }
3397
3398         /*
3399          * On ILK+ LUT must be loaded before the pipe is running but with
3400          * clocks enabled
3401          */
3402         intel_crtc_load_lut(crtc);
3403
3404         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405         intel_enable_plane(dev_priv, plane, pipe);
3406
3407         if (is_pch_port)
3408                 ironlake_pch_enable(crtc);
3409
3410         mutex_lock(&dev->struct_mutex);
3411         intel_update_fbc(dev);
3412         mutex_unlock(&dev->struct_mutex);
3413
3414         intel_crtc_update_cursor(crtc, true);
3415
3416         for_each_encoder_on_crtc(dev, crtc, encoder)
3417                 encoder->enable(encoder);
3418
3419         if (HAS_PCH_CPT(dev))
3420                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3421
3422         /*
3423          * There seems to be a race in PCH platform hw (at least on some
3424          * outputs) where an enabled pipe still completes any pageflip right
3425          * away (as if the pipe is off) instead of waiting for vblank. As soon
3426          * as the first vblank happend, everything works as expected. Hence just
3427          * wait for one vblank before returning to avoid strange things
3428          * happening.
3429          */
3430         intel_wait_for_vblank(dev, intel_crtc->pipe);
3431 }
3432
3433 static void haswell_crtc_enable(struct drm_crtc *crtc)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438         struct intel_encoder *encoder;
3439         int pipe = intel_crtc->pipe;
3440         int plane = intel_crtc->plane;
3441         bool is_pch_port;
3442
3443         WARN_ON(!crtc->enabled);
3444
3445         if (intel_crtc->active)
3446                 return;
3447
3448         intel_crtc->active = true;
3449         intel_update_watermarks(dev);
3450
3451         is_pch_port = haswell_crtc_driving_pch(crtc);
3452
3453         if (is_pch_port)
3454                 ironlake_fdi_pll_enable(intel_crtc);
3455
3456         for_each_encoder_on_crtc(dev, crtc, encoder)
3457                 if (encoder->pre_enable)
3458                         encoder->pre_enable(encoder);
3459
3460         intel_ddi_enable_pipe_clock(intel_crtc);
3461
3462         /* Enable panel fitting for eDP */
3463         if (dev_priv->pch_pf_size && HAS_eDP) {
3464                 /* Force use of hard-coded filter coefficients
3465                  * as some pre-programmed values are broken,
3466                  * e.g. x201.
3467                  */
3468                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3469                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3471         }
3472
3473         /*
3474          * On ILK+ LUT must be loaded before the pipe is running but with
3475          * clocks enabled
3476          */
3477         intel_crtc_load_lut(crtc);
3478
3479         intel_ddi_set_pipe_settings(crtc);
3480         intel_ddi_enable_pipe_func(crtc);
3481
3482         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3483         intel_enable_plane(dev_priv, plane, pipe);
3484
3485         if (is_pch_port)
3486                 lpt_pch_enable(crtc);
3487
3488         mutex_lock(&dev->struct_mutex);
3489         intel_update_fbc(dev);
3490         mutex_unlock(&dev->struct_mutex);
3491
3492         intel_crtc_update_cursor(crtc, true);
3493
3494         for_each_encoder_on_crtc(dev, crtc, encoder)
3495                 encoder->enable(encoder);
3496
3497         /*
3498          * There seems to be a race in PCH platform hw (at least on some
3499          * outputs) where an enabled pipe still completes any pageflip right
3500          * away (as if the pipe is off) instead of waiting for vblank. As soon
3501          * as the first vblank happend, everything works as expected. Hence just
3502          * wait for one vblank before returning to avoid strange things
3503          * happening.
3504          */
3505         intel_wait_for_vblank(dev, intel_crtc->pipe);
3506 }
3507
3508 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3509 {
3510         struct drm_device *dev = crtc->dev;
3511         struct drm_i915_private *dev_priv = dev->dev_private;
3512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513         struct intel_encoder *encoder;
3514         int pipe = intel_crtc->pipe;
3515         int plane = intel_crtc->plane;
3516         u32 reg, temp;
3517
3518
3519         if (!intel_crtc->active)
3520                 return;
3521
3522         for_each_encoder_on_crtc(dev, crtc, encoder)
3523                 encoder->disable(encoder);
3524
3525         intel_crtc_wait_for_pending_flips(crtc);
3526         drm_vblank_off(dev, pipe);
3527         intel_crtc_update_cursor(crtc, false);
3528
3529         intel_disable_plane(dev_priv, plane, pipe);
3530
3531         if (dev_priv->cfb_plane == plane)
3532                 intel_disable_fbc(dev);
3533
3534         intel_disable_pipe(dev_priv, pipe);
3535
3536         /* Disable PF */
3537         I915_WRITE(PF_CTL(pipe), 0);
3538         I915_WRITE(PF_WIN_SZ(pipe), 0);
3539
3540         for_each_encoder_on_crtc(dev, crtc, encoder)
3541                 if (encoder->post_disable)
3542                         encoder->post_disable(encoder);
3543
3544         ironlake_fdi_disable(crtc);
3545
3546         ironlake_disable_pch_transcoder(dev_priv, pipe);
3547
3548         if (HAS_PCH_CPT(dev)) {
3549                 /* disable TRANS_DP_CTL */
3550                 reg = TRANS_DP_CTL(pipe);
3551                 temp = I915_READ(reg);
3552                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3553                 temp |= TRANS_DP_PORT_SEL_NONE;
3554                 I915_WRITE(reg, temp);
3555
3556                 /* disable DPLL_SEL */
3557                 temp = I915_READ(PCH_DPLL_SEL);
3558                 switch (pipe) {
3559                 case 0:
3560                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3561                         break;
3562                 case 1:
3563                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3564                         break;
3565                 case 2:
3566                         /* C shares PLL A or B */
3567                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3568                         break;
3569                 default:
3570                         BUG(); /* wtf */
3571                 }
3572                 I915_WRITE(PCH_DPLL_SEL, temp);
3573         }
3574
3575         /* disable PCH DPLL */
3576         intel_disable_pch_pll(intel_crtc);
3577
3578         ironlake_fdi_pll_disable(intel_crtc);
3579
3580         intel_crtc->active = false;
3581         intel_update_watermarks(dev);
3582
3583         mutex_lock(&dev->struct_mutex);
3584         intel_update_fbc(dev);
3585         mutex_unlock(&dev->struct_mutex);
3586 }
3587
3588 static void haswell_crtc_disable(struct drm_crtc *crtc)
3589 {
3590         struct drm_device *dev = crtc->dev;
3591         struct drm_i915_private *dev_priv = dev->dev_private;
3592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593         struct intel_encoder *encoder;
3594         int pipe = intel_crtc->pipe;
3595         int plane = intel_crtc->plane;
3596         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3597         bool is_pch_port;
3598
3599         if (!intel_crtc->active)
3600                 return;
3601
3602         is_pch_port = haswell_crtc_driving_pch(crtc);
3603
3604         for_each_encoder_on_crtc(dev, crtc, encoder)
3605                 encoder->disable(encoder);
3606
3607         intel_crtc_wait_for_pending_flips(crtc);
3608         drm_vblank_off(dev, pipe);
3609         intel_crtc_update_cursor(crtc, false);
3610
3611         intel_disable_plane(dev_priv, plane, pipe);
3612
3613         if (dev_priv->cfb_plane == plane)
3614                 intel_disable_fbc(dev);
3615
3616         intel_disable_pipe(dev_priv, pipe);
3617
3618         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3619
3620         /* Disable PF */
3621         I915_WRITE(PF_CTL(pipe), 0);
3622         I915_WRITE(PF_WIN_SZ(pipe), 0);
3623
3624         intel_ddi_disable_pipe_clock(intel_crtc);
3625
3626         for_each_encoder_on_crtc(dev, crtc, encoder)
3627                 if (encoder->post_disable)
3628                         encoder->post_disable(encoder);
3629
3630         if (is_pch_port) {
3631                 ironlake_fdi_disable(crtc);
3632                 lpt_disable_pch_transcoder(dev_priv, pipe);
3633                 intel_disable_pch_pll(intel_crtc);
3634                 ironlake_fdi_pll_disable(intel_crtc);
3635         }
3636
3637         intel_crtc->active = false;
3638         intel_update_watermarks(dev);
3639
3640         mutex_lock(&dev->struct_mutex);
3641         intel_update_fbc(dev);
3642         mutex_unlock(&dev->struct_mutex);
3643 }
3644
3645 static void ironlake_crtc_off(struct drm_crtc *crtc)
3646 {
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         intel_put_pch_pll(intel_crtc);
3649 }
3650
3651 static void haswell_crtc_off(struct drm_crtc *crtc)
3652 {
3653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654
3655         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3656          * start using it. */
3657         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3658
3659         intel_ddi_put_crtc_pll(crtc);
3660 }
3661
3662 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3663 {
3664         if (!enable && intel_crtc->overlay) {
3665                 struct drm_device *dev = intel_crtc->base.dev;
3666                 struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668                 mutex_lock(&dev->struct_mutex);
3669                 dev_priv->mm.interruptible = false;
3670                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3671                 dev_priv->mm.interruptible = true;
3672                 mutex_unlock(&dev->struct_mutex);
3673         }
3674
3675         /* Let userspace switch the overlay on again. In most cases userspace
3676          * has to recompute where to put it anyway.
3677          */
3678 }
3679
3680 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3681 {
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685         struct intel_encoder *encoder;
3686         int pipe = intel_crtc->pipe;
3687         int plane = intel_crtc->plane;
3688
3689         WARN_ON(!crtc->enabled);
3690
3691         if (intel_crtc->active)
3692                 return;
3693
3694         intel_crtc->active = true;
3695         intel_update_watermarks(dev);
3696
3697         intel_enable_pll(dev_priv, pipe);
3698         intel_enable_pipe(dev_priv, pipe, false);
3699         intel_enable_plane(dev_priv, plane, pipe);
3700
3701         intel_crtc_load_lut(crtc);
3702         intel_update_fbc(dev);
3703
3704         /* Give the overlay scaler a chance to enable if it's on this pipe */
3705         intel_crtc_dpms_overlay(intel_crtc, true);
3706         intel_crtc_update_cursor(crtc, true);
3707
3708         for_each_encoder_on_crtc(dev, crtc, encoder)
3709                 encoder->enable(encoder);
3710 }
3711
3712 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717         struct intel_encoder *encoder;
3718         int pipe = intel_crtc->pipe;
3719         int plane = intel_crtc->plane;
3720
3721
3722         if (!intel_crtc->active)
3723                 return;
3724
3725         for_each_encoder_on_crtc(dev, crtc, encoder)
3726                 encoder->disable(encoder);
3727
3728         /* Give the overlay scaler a chance to disable if it's on this pipe */
3729         intel_crtc_wait_for_pending_flips(crtc);
3730         drm_vblank_off(dev, pipe);
3731         intel_crtc_dpms_overlay(intel_crtc, false);
3732         intel_crtc_update_cursor(crtc, false);
3733
3734         if (dev_priv->cfb_plane == plane)
3735                 intel_disable_fbc(dev);
3736
3737         intel_disable_plane(dev_priv, plane, pipe);
3738         intel_disable_pipe(dev_priv, pipe);
3739         intel_disable_pll(dev_priv, pipe);
3740
3741         intel_crtc->active = false;
3742         intel_update_fbc(dev);
3743         intel_update_watermarks(dev);
3744 }
3745
3746 static void i9xx_crtc_off(struct drm_crtc *crtc)
3747 {
3748 }
3749
3750 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3751                                     bool enabled)
3752 {
3753         struct drm_device *dev = crtc->dev;
3754         struct drm_i915_master_private *master_priv;
3755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756         int pipe = intel_crtc->pipe;
3757
3758         if (!dev->primary->master)
3759                 return;
3760
3761         master_priv = dev->primary->master->driver_priv;
3762         if (!master_priv->sarea_priv)
3763                 return;
3764
3765         switch (pipe) {
3766         case 0:
3767                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3768                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3769                 break;
3770         case 1:
3771                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3772                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3773                 break;
3774         default:
3775                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3776                 break;
3777         }
3778 }
3779
3780 /**
3781  * Sets the power management mode of the pipe and plane.
3782  */
3783 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3784 {
3785         struct drm_device *dev = crtc->dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         struct intel_encoder *intel_encoder;
3788         bool enable = false;
3789
3790         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3791                 enable |= intel_encoder->connectors_active;
3792
3793         if (enable)
3794                 dev_priv->display.crtc_enable(crtc);
3795         else
3796                 dev_priv->display.crtc_disable(crtc);
3797
3798         intel_crtc_update_sarea(crtc, enable);
3799 }
3800
3801 static void intel_crtc_noop(struct drm_crtc *crtc)
3802 {
3803 }
3804
3805 static void intel_crtc_disable(struct drm_crtc *crtc)
3806 {
3807         struct drm_device *dev = crtc->dev;
3808         struct drm_connector *connector;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810
3811         /* crtc should still be enabled when we disable it. */
3812         WARN_ON(!crtc->enabled);
3813
3814         dev_priv->display.crtc_disable(crtc);
3815         intel_crtc_update_sarea(crtc, false);
3816         dev_priv->display.off(crtc);
3817
3818         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3819         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3820
3821         if (crtc->fb) {
3822                 mutex_lock(&dev->struct_mutex);
3823                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3824                 mutex_unlock(&dev->struct_mutex);
3825                 crtc->fb = NULL;
3826         }
3827
3828         /* Update computed state. */
3829         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3830                 if (!connector->encoder || !connector->encoder->crtc)
3831                         continue;
3832
3833                 if (connector->encoder->crtc != crtc)
3834                         continue;
3835
3836                 connector->dpms = DRM_MODE_DPMS_OFF;
3837                 to_intel_encoder(connector->encoder)->connectors_active = false;
3838         }
3839 }
3840
3841 void intel_modeset_disable(struct drm_device *dev)
3842 {
3843         struct drm_crtc *crtc;
3844
3845         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3846                 if (crtc->enabled)
3847                         intel_crtc_disable(crtc);
3848         }
3849 }
3850
3851 void intel_encoder_noop(struct drm_encoder *encoder)
3852 {
3853 }
3854
3855 void intel_encoder_destroy(struct drm_encoder *encoder)
3856 {
3857         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3858
3859         drm_encoder_cleanup(encoder);
3860         kfree(intel_encoder);
3861 }
3862
3863 /* Simple dpms helper for encodres with just one connector, no cloning and only
3864  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3865  * state of the entire output pipe. */
3866 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3867 {
3868         if (mode == DRM_MODE_DPMS_ON) {
3869                 encoder->connectors_active = true;
3870
3871                 intel_crtc_update_dpms(encoder->base.crtc);
3872         } else {
3873                 encoder->connectors_active = false;
3874
3875                 intel_crtc_update_dpms(encoder->base.crtc);
3876         }
3877 }
3878
3879 /* Cross check the actual hw state with our own modeset state tracking (and it's
3880  * internal consistency). */
3881 static void intel_connector_check_state(struct intel_connector *connector)
3882 {
3883         if (connector->get_hw_state(connector)) {
3884                 struct intel_encoder *encoder = connector->encoder;
3885                 struct drm_crtc *crtc;
3886                 bool encoder_enabled;
3887                 enum pipe pipe;
3888
3889                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3890                               connector->base.base.id,
3891                               drm_get_connector_name(&connector->base));
3892
3893                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3894                      "wrong connector dpms state\n");
3895                 WARN(connector->base.encoder != &encoder->base,
3896                      "active connector not linked to encoder\n");
3897                 WARN(!encoder->connectors_active,
3898                      "encoder->connectors_active not set\n");
3899
3900                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3901                 WARN(!encoder_enabled, "encoder not enabled\n");
3902                 if (WARN_ON(!encoder->base.crtc))
3903                         return;
3904
3905                 crtc = encoder->base.crtc;
3906
3907                 WARN(!crtc->enabled, "crtc not enabled\n");
3908                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3909                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3910                      "encoder active on the wrong pipe\n");
3911         }
3912 }
3913
3914 /* Even simpler default implementation, if there's really no special case to
3915  * consider. */
3916 void intel_connector_dpms(struct drm_connector *connector, int mode)
3917 {
3918         struct intel_encoder *encoder = intel_attached_encoder(connector);
3919
3920         /* All the simple cases only support two dpms states. */
3921         if (mode != DRM_MODE_DPMS_ON)
3922                 mode = DRM_MODE_DPMS_OFF;
3923
3924         if (mode == connector->dpms)
3925                 return;
3926
3927         connector->dpms = mode;
3928
3929         /* Only need to change hw state when actually enabled */
3930         if (encoder->base.crtc)
3931                 intel_encoder_dpms(encoder, mode);
3932         else
3933                 WARN_ON(encoder->connectors_active != false);
3934
3935         intel_modeset_check_state(connector->dev);
3936 }
3937
3938 /* Simple connector->get_hw_state implementation for encoders that support only
3939  * one connector and no cloning and hence the encoder state determines the state
3940  * of the connector. */
3941 bool intel_connector_get_hw_state(struct intel_connector *connector)
3942 {
3943         enum pipe pipe = 0;
3944         struct intel_encoder *encoder = connector->encoder;
3945
3946         return encoder->get_hw_state(encoder, &pipe);
3947 }
3948
3949 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3950                                   const struct drm_display_mode *mode,
3951                                   struct drm_display_mode *adjusted_mode)
3952 {
3953         struct drm_device *dev = crtc->dev;
3954
3955         if (HAS_PCH_SPLIT(dev)) {
3956                 /* FDI link clock is fixed at 2.7G */
3957                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3958                         return false;
3959         }
3960
3961         /* All interlaced capable intel hw wants timings in frames. Note though
3962          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963          * timings, so we need to be careful not to clobber these.*/
3964         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3965                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3966
3967         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968          * with a hsync front porch of 0.
3969          */
3970         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972                 return false;
3973
3974         return true;
3975 }
3976
3977 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3978 {
3979         return 400000; /* FIXME */
3980 }
3981
3982 static int i945_get_display_clock_speed(struct drm_device *dev)
3983 {
3984         return 400000;
3985 }
3986
3987 static int i915_get_display_clock_speed(struct drm_device *dev)
3988 {
3989         return 333000;
3990 }
3991
3992 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3993 {
3994         return 200000;
3995 }
3996
3997 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3998 {
3999         u16 gcfgc = 0;
4000
4001         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4002
4003         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4004                 return 133000;
4005         else {
4006                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4007                 case GC_DISPLAY_CLOCK_333_MHZ:
4008                         return 333000;
4009                 default:
4010                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4011                         return 190000;
4012                 }
4013         }
4014 }
4015
4016 static int i865_get_display_clock_speed(struct drm_device *dev)
4017 {
4018         return 266000;
4019 }
4020
4021 static int i855_get_display_clock_speed(struct drm_device *dev)
4022 {
4023         u16 hpllcc = 0;
4024         /* Assume that the hardware is in the high speed state.  This
4025          * should be the default.
4026          */
4027         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4028         case GC_CLOCK_133_200:
4029         case GC_CLOCK_100_200:
4030                 return 200000;
4031         case GC_CLOCK_166_250:
4032                 return 250000;
4033         case GC_CLOCK_100_133:
4034                 return 133000;
4035         }
4036
4037         /* Shouldn't happen */
4038         return 0;
4039 }
4040
4041 static int i830_get_display_clock_speed(struct drm_device *dev)
4042 {
4043         return 133000;
4044 }
4045
4046 struct fdi_m_n {
4047         u32        tu;
4048         u32        gmch_m;
4049         u32        gmch_n;
4050         u32        link_m;
4051         u32        link_n;
4052 };
4053
4054 static void
4055 fdi_reduce_ratio(u32 *num, u32 *den)
4056 {
4057         while (*num > 0xffffff || *den > 0xffffff) {
4058                 *num >>= 1;
4059                 *den >>= 1;
4060         }
4061 }
4062
4063 static void
4064 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4065                      int link_clock, struct fdi_m_n *m_n)
4066 {
4067         m_n->tu = 64; /* default size */
4068
4069         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4070         m_n->gmch_m = bits_per_pixel * pixel_clock;
4071         m_n->gmch_n = link_clock * nlanes * 8;
4072         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4073
4074         m_n->link_m = pixel_clock;
4075         m_n->link_n = link_clock;
4076         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4077 }
4078
4079 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4080 {
4081         if (i915_panel_use_ssc >= 0)
4082                 return i915_panel_use_ssc != 0;
4083         return dev_priv->lvds_use_ssc
4084                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4085 }
4086
4087 /**
4088  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4089  * @crtc: CRTC structure
4090  * @mode: requested mode
4091  *
4092  * A pipe may be connected to one or more outputs.  Based on the depth of the
4093  * attached framebuffer, choose a good color depth to use on the pipe.
4094  *
4095  * If possible, match the pipe depth to the fb depth.  In some cases, this
4096  * isn't ideal, because the connected output supports a lesser or restricted
4097  * set of depths.  Resolve that here:
4098  *    LVDS typically supports only 6bpc, so clamp down in that case
4099  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4100  *    Displays may support a restricted set as well, check EDID and clamp as
4101  *      appropriate.
4102  *    DP may want to dither down to 6bpc to fit larger modes
4103  *
4104  * RETURNS:
4105  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4106  * true if they don't match).
4107  */
4108 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4109                                          struct drm_framebuffer *fb,
4110                                          unsigned int *pipe_bpp,
4111                                          struct drm_display_mode *mode)
4112 {
4113         struct drm_device *dev = crtc->dev;
4114         struct drm_i915_private *dev_priv = dev->dev_private;
4115         struct drm_connector *connector;
4116         struct intel_encoder *intel_encoder;
4117         unsigned int display_bpc = UINT_MAX, bpc;
4118
4119         /* Walk the encoders & connectors on this crtc, get min bpc */
4120         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4121
4122                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4123                         unsigned int lvds_bpc;
4124
4125                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4126                             LVDS_A3_POWER_UP)
4127                                 lvds_bpc = 8;
4128                         else
4129                                 lvds_bpc = 6;
4130
4131                         if (lvds_bpc < display_bpc) {
4132                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4133                                 display_bpc = lvds_bpc;
4134                         }
4135                         continue;
4136                 }
4137
4138                 /* Not one of the known troublemakers, check the EDID */
4139                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4140                                     head) {
4141                         if (connector->encoder != &intel_encoder->base)
4142                                 continue;
4143
4144                         /* Don't use an invalid EDID bpc value */
4145                         if (connector->display_info.bpc &&
4146                             connector->display_info.bpc < display_bpc) {
4147                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4148                                 display_bpc = connector->display_info.bpc;
4149                         }
4150                 }
4151
4152                 /*
4153                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4154                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4155                  */
4156                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4157                         if (display_bpc > 8 && display_bpc < 12) {
4158                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4159                                 display_bpc = 12;
4160                         } else {
4161                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4162                                 display_bpc = 8;
4163                         }
4164                 }
4165         }
4166
4167         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4168                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4169                 display_bpc = 6;
4170         }
4171
4172         /*
4173          * We could just drive the pipe at the highest bpc all the time and
4174          * enable dithering as needed, but that costs bandwidth.  So choose
4175          * the minimum value that expresses the full color range of the fb but
4176          * also stays within the max display bpc discovered above.
4177          */
4178
4179         switch (fb->depth) {
4180         case 8:
4181                 bpc = 8; /* since we go through a colormap */
4182                 break;
4183         case 15:
4184         case 16:
4185                 bpc = 6; /* min is 18bpp */
4186                 break;
4187         case 24:
4188                 bpc = 8;
4189                 break;
4190         case 30:
4191                 bpc = 10;
4192                 break;
4193         case 48:
4194                 bpc = 12;
4195                 break;
4196         default:
4197                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4198                 bpc = min((unsigned int)8, display_bpc);
4199                 break;
4200         }
4201
4202         display_bpc = min(display_bpc, bpc);
4203
4204         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4205                       bpc, display_bpc);
4206
4207         *pipe_bpp = display_bpc * 3;
4208
4209         return display_bpc != bpc;
4210 }
4211
4212 static int vlv_get_refclk(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         int refclk = 27000; /* for DP & HDMI */
4217
4218         return 100000; /* only one validated so far */
4219
4220         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4221                 refclk = 96000;
4222         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4223                 if (intel_panel_use_ssc(dev_priv))
4224                         refclk = 100000;
4225                 else
4226                         refclk = 96000;
4227         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4228                 refclk = 100000;
4229         }
4230
4231         return refclk;
4232 }
4233
4234 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         int refclk;
4239
4240         if (IS_VALLEYVIEW(dev)) {
4241                 refclk = vlv_get_refclk(crtc);
4242         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4243             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4244                 refclk = dev_priv->lvds_ssc_freq * 1000;
4245                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4246                               refclk / 1000);
4247         } else if (!IS_GEN2(dev)) {
4248                 refclk = 96000;
4249         } else {
4250                 refclk = 48000;
4251         }
4252
4253         return refclk;
4254 }
4255
4256 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4257                                       intel_clock_t *clock)
4258 {
4259         /* SDVO TV has fixed PLL values depend on its clock range,
4260            this mirrors vbios setting. */
4261         if (adjusted_mode->clock >= 100000
4262             && adjusted_mode->clock < 140500) {
4263                 clock->p1 = 2;
4264                 clock->p2 = 10;
4265                 clock->n = 3;
4266                 clock->m1 = 16;
4267                 clock->m2 = 8;
4268         } else if (adjusted_mode->clock >= 140500
4269                    && adjusted_mode->clock <= 200000) {
4270                 clock->p1 = 1;
4271                 clock->p2 = 10;
4272                 clock->n = 6;
4273                 clock->m1 = 12;
4274                 clock->m2 = 8;
4275         }
4276 }
4277
4278 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4279                                      intel_clock_t *clock,
4280                                      intel_clock_t *reduced_clock)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285         int pipe = intel_crtc->pipe;
4286         u32 fp, fp2 = 0;
4287
4288         if (IS_PINEVIEW(dev)) {
4289                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4290                 if (reduced_clock)
4291                         fp2 = (1 << reduced_clock->n) << 16 |
4292                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4293         } else {
4294                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4295                 if (reduced_clock)
4296                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4297                                 reduced_clock->m2;
4298         }
4299
4300         I915_WRITE(FP0(pipe), fp);
4301
4302         intel_crtc->lowfreq_avail = false;
4303         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4304             reduced_clock && i915_powersave) {
4305                 I915_WRITE(FP1(pipe), fp2);
4306                 intel_crtc->lowfreq_avail = true;
4307         } else {
4308                 I915_WRITE(FP1(pipe), fp);
4309         }
4310 }
4311
4312 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4313                               struct drm_display_mode *adjusted_mode)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4318         int pipe = intel_crtc->pipe;
4319         u32 temp;
4320
4321         temp = I915_READ(LVDS);
4322         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4323         if (pipe == 1) {
4324                 temp |= LVDS_PIPEB_SELECT;
4325         } else {
4326                 temp &= ~LVDS_PIPEB_SELECT;
4327         }
4328         /* set the corresponsding LVDS_BORDER bit */
4329         temp |= dev_priv->lvds_border_bits;
4330         /* Set the B0-B3 data pairs corresponding to whether we're going to
4331          * set the DPLLs for dual-channel mode or not.
4332          */
4333         if (clock->p2 == 7)
4334                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4335         else
4336                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4337
4338         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4339          * appropriately here, but we need to look more thoroughly into how
4340          * panels behave in the two modes.
4341          */
4342         /* set the dithering flag on LVDS as needed */
4343         if (INTEL_INFO(dev)->gen >= 4) {
4344                 if (dev_priv->lvds_dither)
4345                         temp |= LVDS_ENABLE_DITHER;
4346                 else
4347                         temp &= ~LVDS_ENABLE_DITHER;
4348         }
4349         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4350         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4351                 temp |= LVDS_HSYNC_POLARITY;
4352         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4353                 temp |= LVDS_VSYNC_POLARITY;
4354         I915_WRITE(LVDS, temp);
4355 }
4356
4357 static void vlv_update_pll(struct drm_crtc *crtc,
4358                            struct drm_display_mode *mode,
4359                            struct drm_display_mode *adjusted_mode,
4360                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4361                            int num_connectors)
4362 {
4363         struct drm_device *dev = crtc->dev;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366         int pipe = intel_crtc->pipe;
4367         u32 dpll, mdiv, pdiv;
4368         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4369         bool is_sdvo;
4370         u32 temp;
4371
4372         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4373                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4374
4375         dpll = DPLL_VGA_MODE_DIS;
4376         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4377         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4378         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4379
4380         I915_WRITE(DPLL(pipe), dpll);
4381         POSTING_READ(DPLL(pipe));
4382
4383         bestn = clock->n;
4384         bestm1 = clock->m1;
4385         bestm2 = clock->m2;
4386         bestp1 = clock->p1;
4387         bestp2 = clock->p2;
4388
4389         /*
4390          * In Valleyview PLL and program lane counter registers are exposed
4391          * through DPIO interface
4392          */
4393         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4394         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4395         mdiv |= ((bestn << DPIO_N_SHIFT));
4396         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4397         mdiv |= (1 << DPIO_K_SHIFT);
4398         mdiv |= DPIO_ENABLE_CALIBRATION;
4399         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4400
4401         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4402
4403         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4404                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4405                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4406                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4407         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4408
4409         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4410
4411         dpll |= DPLL_VCO_ENABLE;
4412         I915_WRITE(DPLL(pipe), dpll);
4413         POSTING_READ(DPLL(pipe));
4414         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4415                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4416
4417         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4418
4419         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4420                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4421
4422         I915_WRITE(DPLL(pipe), dpll);
4423
4424         /* Wait for the clocks to stabilize. */
4425         POSTING_READ(DPLL(pipe));
4426         udelay(150);
4427
4428         temp = 0;
4429         if (is_sdvo) {
4430                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4431                 if (temp > 1)
4432                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4433                 else
4434                         temp = 0;
4435         }
4436         I915_WRITE(DPLL_MD(pipe), temp);
4437         POSTING_READ(DPLL_MD(pipe));
4438
4439         /* Now program lane control registers */
4440         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4441                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4442         {
4443                 temp = 0x1000C4;
4444                 if(pipe == 1)
4445                         temp |= (1 << 21);
4446                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4447         }
4448         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4449         {
4450                 temp = 0x1000C4;
4451                 if(pipe == 1)
4452                         temp |= (1 << 21);
4453                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4454         }
4455 }
4456
4457 static void i9xx_update_pll(struct drm_crtc *crtc,
4458                             struct drm_display_mode *mode,
4459                             struct drm_display_mode *adjusted_mode,
4460                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4461                             int num_connectors)
4462 {
4463         struct drm_device *dev = crtc->dev;
4464         struct drm_i915_private *dev_priv = dev->dev_private;
4465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4466         int pipe = intel_crtc->pipe;
4467         u32 dpll;
4468         bool is_sdvo;
4469
4470         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4471
4472         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4473                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4474
4475         dpll = DPLL_VGA_MODE_DIS;
4476
4477         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4478                 dpll |= DPLLB_MODE_LVDS;
4479         else
4480                 dpll |= DPLLB_MODE_DAC_SERIAL;
4481         if (is_sdvo) {
4482                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4483                 if (pixel_multiplier > 1) {
4484                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4485                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4486                 }
4487                 dpll |= DPLL_DVO_HIGH_SPEED;
4488         }
4489         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4490                 dpll |= DPLL_DVO_HIGH_SPEED;
4491
4492         /* compute bitmask from p1 value */
4493         if (IS_PINEVIEW(dev))
4494                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4495         else {
4496                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4497                 if (IS_G4X(dev) && reduced_clock)
4498                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4499         }
4500         switch (clock->p2) {
4501         case 5:
4502                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4503                 break;
4504         case 7:
4505                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4506                 break;
4507         case 10:
4508                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4509                 break;
4510         case 14:
4511                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4512                 break;
4513         }
4514         if (INTEL_INFO(dev)->gen >= 4)
4515                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4516
4517         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4518                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4519         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4520                 /* XXX: just matching BIOS for now */
4521                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4522                 dpll |= 3;
4523         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4524                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4525                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4526         else
4527                 dpll |= PLL_REF_INPUT_DREFCLK;
4528
4529         dpll |= DPLL_VCO_ENABLE;
4530         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4531         POSTING_READ(DPLL(pipe));
4532         udelay(150);
4533
4534         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4535          * This is an exception to the general rule that mode_set doesn't turn
4536          * things on.
4537          */
4538         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4539                 intel_update_lvds(crtc, clock, adjusted_mode);
4540
4541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4542                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4543
4544         I915_WRITE(DPLL(pipe), dpll);
4545
4546         /* Wait for the clocks to stabilize. */
4547         POSTING_READ(DPLL(pipe));
4548         udelay(150);
4549
4550         if (INTEL_INFO(dev)->gen >= 4) {
4551                 u32 temp = 0;
4552                 if (is_sdvo) {
4553                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4554                         if (temp > 1)
4555                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4556                         else
4557                                 temp = 0;
4558                 }
4559                 I915_WRITE(DPLL_MD(pipe), temp);
4560         } else {
4561                 /* The pixel multiplier can only be updated once the
4562                  * DPLL is enabled and the clocks are stable.
4563                  *
4564                  * So write it again.
4565                  */
4566                 I915_WRITE(DPLL(pipe), dpll);
4567         }
4568 }
4569
4570 static void i8xx_update_pll(struct drm_crtc *crtc,
4571                             struct drm_display_mode *adjusted_mode,
4572                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4573                             int num_connectors)
4574 {
4575         struct drm_device *dev = crtc->dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4578         int pipe = intel_crtc->pipe;
4579         u32 dpll;
4580
4581         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4582
4583         dpll = DPLL_VGA_MODE_DIS;
4584
4585         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4586                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4587         } else {
4588                 if (clock->p1 == 2)
4589                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4590                 else
4591                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592                 if (clock->p2 == 4)
4593                         dpll |= PLL_P2_DIVIDE_BY_4;
4594         }
4595
4596         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4597                 /* XXX: just matching BIOS for now */
4598                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4599                 dpll |= 3;
4600         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4601                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4602                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4603         else
4604                 dpll |= PLL_REF_INPUT_DREFCLK;
4605
4606         dpll |= DPLL_VCO_ENABLE;
4607         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4608         POSTING_READ(DPLL(pipe));
4609         udelay(150);
4610
4611         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4612          * This is an exception to the general rule that mode_set doesn't turn
4613          * things on.
4614          */
4615         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4616                 intel_update_lvds(crtc, clock, adjusted_mode);
4617
4618         I915_WRITE(DPLL(pipe), dpll);
4619
4620         /* Wait for the clocks to stabilize. */
4621         POSTING_READ(DPLL(pipe));
4622         udelay(150);
4623
4624         /* The pixel multiplier can only be updated once the
4625          * DPLL is enabled and the clocks are stable.
4626          *
4627          * So write it again.
4628          */
4629         I915_WRITE(DPLL(pipe), dpll);
4630 }
4631
4632 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4633                                    struct drm_display_mode *mode,
4634                                    struct drm_display_mode *adjusted_mode)
4635 {
4636         struct drm_device *dev = intel_crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         enum pipe pipe = intel_crtc->pipe;
4639         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4640         uint32_t vsyncshift;
4641
4642         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4643                 /* the chip adds 2 halflines automatically */
4644                 adjusted_mode->crtc_vtotal -= 1;
4645                 adjusted_mode->crtc_vblank_end -= 1;
4646                 vsyncshift = adjusted_mode->crtc_hsync_start
4647                              - adjusted_mode->crtc_htotal / 2;
4648         } else {
4649                 vsyncshift = 0;
4650         }
4651
4652         if (INTEL_INFO(dev)->gen > 3)
4653                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4654
4655         I915_WRITE(HTOTAL(cpu_transcoder),
4656                    (adjusted_mode->crtc_hdisplay - 1) |
4657                    ((adjusted_mode->crtc_htotal - 1) << 16));
4658         I915_WRITE(HBLANK(cpu_transcoder),
4659                    (adjusted_mode->crtc_hblank_start - 1) |
4660                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4661         I915_WRITE(HSYNC(cpu_transcoder),
4662                    (adjusted_mode->crtc_hsync_start - 1) |
4663                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664
4665         I915_WRITE(VTOTAL(cpu_transcoder),
4666                    (adjusted_mode->crtc_vdisplay - 1) |
4667                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4668         I915_WRITE(VBLANK(cpu_transcoder),
4669                    (adjusted_mode->crtc_vblank_start - 1) |
4670                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4671         I915_WRITE(VSYNC(cpu_transcoder),
4672                    (adjusted_mode->crtc_vsync_start - 1) |
4673                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674
4675         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4676          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4677          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678          * bits. */
4679         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4680             (pipe == PIPE_B || pipe == PIPE_C))
4681                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682
4683         /* pipesrc controls the size that is scaled from, which should
4684          * always be the user's requested size.
4685          */
4686         I915_WRITE(PIPESRC(pipe),
4687                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688 }
4689
4690 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4691                               struct drm_display_mode *mode,
4692                               struct drm_display_mode *adjusted_mode,
4693                               int x, int y,
4694                               struct drm_framebuffer *fb)
4695 {
4696         struct drm_device *dev = crtc->dev;
4697         struct drm_i915_private *dev_priv = dev->dev_private;
4698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699         int pipe = intel_crtc->pipe;
4700         int plane = intel_crtc->plane;
4701         int refclk, num_connectors = 0;
4702         intel_clock_t clock, reduced_clock;
4703         u32 dspcntr, pipeconf;
4704         bool ok, has_reduced_clock = false, is_sdvo = false;
4705         bool is_lvds = false, is_tv = false, is_dp = false;
4706         struct intel_encoder *encoder;
4707         const intel_limit_t *limit;
4708         int ret;
4709
4710         for_each_encoder_on_crtc(dev, crtc, encoder) {
4711                 switch (encoder->type) {
4712                 case INTEL_OUTPUT_LVDS:
4713                         is_lvds = true;
4714                         break;
4715                 case INTEL_OUTPUT_SDVO:
4716                 case INTEL_OUTPUT_HDMI:
4717                         is_sdvo = true;
4718                         if (encoder->needs_tv_clock)
4719                                 is_tv = true;
4720                         break;
4721                 case INTEL_OUTPUT_TVOUT:
4722                         is_tv = true;
4723                         break;
4724                 case INTEL_OUTPUT_DISPLAYPORT:
4725                         is_dp = true;
4726                         break;
4727                 }
4728
4729                 num_connectors++;
4730         }
4731
4732         refclk = i9xx_get_refclk(crtc, num_connectors);
4733
4734         /*
4735          * Returns a set of divisors for the desired target clock with the given
4736          * refclk, or FALSE.  The returned values represent the clock equation:
4737          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4738          */
4739         limit = intel_limit(crtc, refclk);
4740         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4741                              &clock);
4742         if (!ok) {
4743                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4744                 return -EINVAL;
4745         }
4746
4747         /* Ensure that the cursor is valid for the new mode before changing... */
4748         intel_crtc_update_cursor(crtc, true);
4749
4750         if (is_lvds && dev_priv->lvds_downclock_avail) {
4751                 /*
4752                  * Ensure we match the reduced clock's P to the target clock.
4753                  * If the clocks don't match, we can't switch the display clock
4754                  * by using the FP0/FP1. In such case we will disable the LVDS
4755                  * downclock feature.
4756                 */
4757                 has_reduced_clock = limit->find_pll(limit, crtc,
4758                                                     dev_priv->lvds_downclock,
4759                                                     refclk,
4760                                                     &clock,
4761                                                     &reduced_clock);
4762         }
4763
4764         if (is_sdvo && is_tv)
4765                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4766
4767         if (IS_GEN2(dev))
4768                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4769                                 has_reduced_clock ? &reduced_clock : NULL,
4770                                 num_connectors);
4771         else if (IS_VALLEYVIEW(dev))
4772                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4773                                 has_reduced_clock ? &reduced_clock : NULL,
4774                                 num_connectors);
4775         else
4776                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4777                                 has_reduced_clock ? &reduced_clock : NULL,
4778                                 num_connectors);
4779
4780         /* setup pipeconf */
4781         pipeconf = I915_READ(PIPECONF(pipe));
4782
4783         /* Set up the display plane register */
4784         dspcntr = DISPPLANE_GAMMA_ENABLE;
4785
4786         if (pipe == 0)
4787                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4788         else
4789                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4790
4791         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4792                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4793                  * core speed.
4794                  *
4795                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4796                  * pipe == 0 check?
4797                  */
4798                 if (mode->clock >
4799                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4800                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4801                 else
4802                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4803         }
4804
4805         /* default to 8bpc */
4806         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4807         if (is_dp) {
4808                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4809                         pipeconf |= PIPECONF_BPP_6 |
4810                                     PIPECONF_DITHER_EN |
4811                                     PIPECONF_DITHER_TYPE_SP;
4812                 }
4813         }
4814
4815         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4816                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4817                         pipeconf |= PIPECONF_BPP_6 |
4818                                         PIPECONF_ENABLE |
4819                                         I965_PIPECONF_ACTIVE;
4820                 }
4821         }
4822
4823         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4824         drm_mode_debug_printmodeline(mode);
4825
4826         if (HAS_PIPE_CXSR(dev)) {
4827                 if (intel_crtc->lowfreq_avail) {
4828                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4829                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4830                 } else {
4831                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4832                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4833                 }
4834         }
4835
4836         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4837         if (!IS_GEN2(dev) &&
4838             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4839                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4840         else
4841                 pipeconf |= PIPECONF_PROGRESSIVE;
4842
4843         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4844
4845         /* pipesrc and dspsize control the size that is scaled from,
4846          * which should always be the user's requested size.
4847          */
4848         I915_WRITE(DSPSIZE(plane),
4849                    ((mode->vdisplay - 1) << 16) |
4850                    (mode->hdisplay - 1));
4851         I915_WRITE(DSPPOS(plane), 0);
4852
4853         I915_WRITE(PIPECONF(pipe), pipeconf);
4854         POSTING_READ(PIPECONF(pipe));
4855         intel_enable_pipe(dev_priv, pipe, false);
4856
4857         intel_wait_for_vblank(dev, pipe);
4858
4859         I915_WRITE(DSPCNTR(plane), dspcntr);
4860         POSTING_READ(DSPCNTR(plane));
4861
4862         ret = intel_pipe_set_base(crtc, x, y, fb);
4863
4864         intel_update_watermarks(dev);
4865
4866         return ret;
4867 }
4868
4869 /*
4870  * Initialize reference clocks when the driver loads
4871  */
4872 void ironlake_init_pch_refclk(struct drm_device *dev)
4873 {
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875         struct drm_mode_config *mode_config = &dev->mode_config;
4876         struct intel_encoder *encoder;
4877         u32 temp;
4878         bool has_lvds = false;
4879         bool has_cpu_edp = false;
4880         bool has_pch_edp = false;
4881         bool has_panel = false;
4882         bool has_ck505 = false;
4883         bool can_ssc = false;
4884
4885         /* We need to take the global config into account */
4886         list_for_each_entry(encoder, &mode_config->encoder_list,
4887                             base.head) {
4888                 switch (encoder->type) {
4889                 case INTEL_OUTPUT_LVDS:
4890                         has_panel = true;
4891                         has_lvds = true;
4892                         break;
4893                 case INTEL_OUTPUT_EDP:
4894                         has_panel = true;
4895                         if (intel_encoder_is_pch_edp(&encoder->base))
4896                                 has_pch_edp = true;
4897                         else
4898                                 has_cpu_edp = true;
4899                         break;
4900                 }
4901         }
4902
4903         if (HAS_PCH_IBX(dev)) {
4904                 has_ck505 = dev_priv->display_clock_mode;
4905                 can_ssc = has_ck505;
4906         } else {
4907                 has_ck505 = false;
4908                 can_ssc = true;
4909         }
4910
4911         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4912                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4913                       has_ck505);
4914
4915         /* Ironlake: try to setup display ref clock before DPLL
4916          * enabling. This is only under driver's control after
4917          * PCH B stepping, previous chipset stepping should be
4918          * ignoring this setting.
4919          */
4920         temp = I915_READ(PCH_DREF_CONTROL);
4921         /* Always enable nonspread source */
4922         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4923
4924         if (has_ck505)
4925                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4926         else
4927                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4928
4929         if (has_panel) {
4930                 temp &= ~DREF_SSC_SOURCE_MASK;
4931                 temp |= DREF_SSC_SOURCE_ENABLE;
4932
4933                 /* SSC must be turned on before enabling the CPU output  */
4934                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4935                         DRM_DEBUG_KMS("Using SSC on panel\n");
4936                         temp |= DREF_SSC1_ENABLE;
4937                 } else
4938                         temp &= ~DREF_SSC1_ENABLE;
4939
4940                 /* Get SSC going before enabling the outputs */
4941                 I915_WRITE(PCH_DREF_CONTROL, temp);
4942                 POSTING_READ(PCH_DREF_CONTROL);
4943                 udelay(200);
4944
4945                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4946
4947                 /* Enable CPU source on CPU attached eDP */
4948                 if (has_cpu_edp) {
4949                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4950                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4951                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4952                         }
4953                         else
4954                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4955                 } else
4956                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4957
4958                 I915_WRITE(PCH_DREF_CONTROL, temp);
4959                 POSTING_READ(PCH_DREF_CONTROL);
4960                 udelay(200);
4961         } else {
4962                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4963
4964                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4965
4966                 /* Turn off CPU output */
4967                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968
4969                 I915_WRITE(PCH_DREF_CONTROL, temp);
4970                 POSTING_READ(PCH_DREF_CONTROL);
4971                 udelay(200);
4972
4973                 /* Turn off the SSC source */
4974                 temp &= ~DREF_SSC_SOURCE_MASK;
4975                 temp |= DREF_SSC_SOURCE_DISABLE;
4976
4977                 /* Turn off SSC1 */
4978                 temp &= ~ DREF_SSC1_ENABLE;
4979
4980                 I915_WRITE(PCH_DREF_CONTROL, temp);
4981                 POSTING_READ(PCH_DREF_CONTROL);
4982                 udelay(200);
4983         }
4984 }
4985
4986 static int ironlake_get_refclk(struct drm_crtc *crtc)
4987 {
4988         struct drm_device *dev = crtc->dev;
4989         struct drm_i915_private *dev_priv = dev->dev_private;
4990         struct intel_encoder *encoder;
4991         struct intel_encoder *edp_encoder = NULL;
4992         int num_connectors = 0;
4993         bool is_lvds = false;
4994
4995         for_each_encoder_on_crtc(dev, crtc, encoder) {
4996                 switch (encoder->type) {
4997                 case INTEL_OUTPUT_LVDS:
4998                         is_lvds = true;
4999                         break;
5000                 case INTEL_OUTPUT_EDP:
5001                         edp_encoder = encoder;
5002                         break;
5003                 }
5004                 num_connectors++;
5005         }
5006
5007         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5008                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5009                               dev_priv->lvds_ssc_freq);
5010                 return dev_priv->lvds_ssc_freq * 1000;
5011         }
5012
5013         return 120000;
5014 }
5015
5016 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5017                                   struct drm_display_mode *adjusted_mode,
5018                                   bool dither)
5019 {
5020         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5022         int pipe = intel_crtc->pipe;
5023         uint32_t val;
5024
5025         val = I915_READ(PIPECONF(pipe));
5026
5027         val &= ~PIPE_BPC_MASK;
5028         switch (intel_crtc->bpp) {
5029         case 18:
5030                 val |= PIPE_6BPC;
5031                 break;
5032         case 24:
5033                 val |= PIPE_8BPC;
5034                 break;
5035         case 30:
5036                 val |= PIPE_10BPC;
5037                 break;
5038         case 36:
5039                 val |= PIPE_12BPC;
5040                 break;
5041         default:
5042                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5043                 BUG();
5044         }
5045
5046         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5047         if (dither)
5048                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5049
5050         val &= ~PIPECONF_INTERLACE_MASK;
5051         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5052                 val |= PIPECONF_INTERLACED_ILK;
5053         else
5054                 val |= PIPECONF_PROGRESSIVE;
5055
5056         I915_WRITE(PIPECONF(pipe), val);
5057         POSTING_READ(PIPECONF(pipe));
5058 }
5059
5060 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5061                                  struct drm_display_mode *adjusted_mode,
5062                                  bool dither)
5063 {
5064         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5067         uint32_t val;
5068
5069         val = I915_READ(PIPECONF(cpu_transcoder));
5070
5071         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5072         if (dither)
5073                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5074
5075         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5076         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5077                 val |= PIPECONF_INTERLACED_ILK;
5078         else
5079                 val |= PIPECONF_PROGRESSIVE;
5080
5081         I915_WRITE(PIPECONF(cpu_transcoder), val);
5082         POSTING_READ(PIPECONF(cpu_transcoder));
5083 }
5084
5085 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5086                                     struct drm_display_mode *adjusted_mode,
5087                                     intel_clock_t *clock,
5088                                     bool *has_reduced_clock,
5089                                     intel_clock_t *reduced_clock)
5090 {
5091         struct drm_device *dev = crtc->dev;
5092         struct drm_i915_private *dev_priv = dev->dev_private;
5093         struct intel_encoder *intel_encoder;
5094         int refclk;
5095         const intel_limit_t *limit;
5096         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5097
5098         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5099                 switch (intel_encoder->type) {
5100                 case INTEL_OUTPUT_LVDS:
5101                         is_lvds = true;
5102                         break;
5103                 case INTEL_OUTPUT_SDVO:
5104                 case INTEL_OUTPUT_HDMI:
5105                         is_sdvo = true;
5106                         if (intel_encoder->needs_tv_clock)
5107                                 is_tv = true;
5108                         break;
5109                 case INTEL_OUTPUT_TVOUT:
5110                         is_tv = true;
5111                         break;
5112                 }
5113         }
5114
5115         refclk = ironlake_get_refclk(crtc);
5116
5117         /*
5118          * Returns a set of divisors for the desired target clock with the given
5119          * refclk, or FALSE.  The returned values represent the clock equation:
5120          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5121          */
5122         limit = intel_limit(crtc, refclk);
5123         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5124                               clock);
5125         if (!ret)
5126                 return false;
5127
5128         if (is_lvds && dev_priv->lvds_downclock_avail) {
5129                 /*
5130                  * Ensure we match the reduced clock's P to the target clock.
5131                  * If the clocks don't match, we can't switch the display clock
5132                  * by using the FP0/FP1. In such case we will disable the LVDS
5133                  * downclock feature.
5134                 */
5135                 *has_reduced_clock = limit->find_pll(limit, crtc,
5136                                                      dev_priv->lvds_downclock,
5137                                                      refclk,
5138                                                      clock,
5139                                                      reduced_clock);
5140         }
5141
5142         if (is_sdvo && is_tv)
5143                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5144
5145         return true;
5146 }
5147
5148 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5149 {
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         uint32_t temp;
5152
5153         temp = I915_READ(SOUTH_CHICKEN1);
5154         if (temp & FDI_BC_BIFURCATION_SELECT)
5155                 return;
5156
5157         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5158         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5159
5160         temp |= FDI_BC_BIFURCATION_SELECT;
5161         DRM_DEBUG_KMS("enabling fdi C rx\n");
5162         I915_WRITE(SOUTH_CHICKEN1, temp);
5163         POSTING_READ(SOUTH_CHICKEN1);
5164 }
5165
5166 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5167 {
5168         struct drm_device *dev = intel_crtc->base.dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         struct intel_crtc *pipe_B_crtc =
5171                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5172
5173         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5174                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5175         if (intel_crtc->fdi_lanes > 4) {
5176                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5177                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5178                 /* Clamp lanes to avoid programming the hw with bogus values. */
5179                 intel_crtc->fdi_lanes = 4;
5180
5181                 return false;
5182         }
5183
5184         if (dev_priv->num_pipe == 2)
5185                 return true;
5186
5187         switch (intel_crtc->pipe) {
5188         case PIPE_A:
5189                 return true;
5190         case PIPE_B:
5191                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5192                     intel_crtc->fdi_lanes > 2) {
5193                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5194                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5195                         /* Clamp lanes to avoid programming the hw with bogus values. */
5196                         intel_crtc->fdi_lanes = 2;
5197
5198                         return false;
5199                 }
5200
5201                 if (intel_crtc->fdi_lanes > 2)
5202                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5203                 else
5204                         cpt_enable_fdi_bc_bifurcation(dev);
5205
5206                 return true;
5207         case PIPE_C:
5208                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5209                         if (intel_crtc->fdi_lanes > 2) {
5210                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5211                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5212                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5213                                 intel_crtc->fdi_lanes = 2;
5214
5215                                 return false;
5216                         }
5217                 } else {
5218                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5219                         return false;
5220                 }
5221
5222                 cpt_enable_fdi_bc_bifurcation(dev);
5223
5224                 return true;
5225         default:
5226                 BUG();
5227         }
5228 }
5229
5230 static void ironlake_set_m_n(struct drm_crtc *crtc,
5231                              struct drm_display_mode *mode,
5232                              struct drm_display_mode *adjusted_mode)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5238         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5239         struct fdi_m_n m_n = {0};
5240         int target_clock, pixel_multiplier, lane, link_bw;
5241         bool is_dp = false, is_cpu_edp = false;
5242
5243         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5244                 switch (intel_encoder->type) {
5245                 case INTEL_OUTPUT_DISPLAYPORT:
5246                         is_dp = true;
5247                         break;
5248                 case INTEL_OUTPUT_EDP:
5249                         is_dp = true;
5250                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5251                                 is_cpu_edp = true;
5252                         edp_encoder = intel_encoder;
5253                         break;
5254                 }
5255         }
5256
5257         /* FDI link */
5258         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5259         lane = 0;
5260         /* CPU eDP doesn't require FDI link, so just set DP M/N
5261            according to current link config */
5262         if (is_cpu_edp) {
5263                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5264         } else {
5265                 /* FDI is a binary signal running at ~2.7GHz, encoding
5266                  * each output octet as 10 bits. The actual frequency
5267                  * is stored as a divider into a 100MHz clock, and the
5268                  * mode pixel clock is stored in units of 1KHz.
5269                  * Hence the bw of each lane in terms of the mode signal
5270                  * is:
5271                  */
5272                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5273         }
5274
5275         /* [e]DP over FDI requires target mode clock instead of link clock. */
5276         if (edp_encoder)
5277                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5278         else if (is_dp)
5279                 target_clock = mode->clock;
5280         else
5281                 target_clock = adjusted_mode->clock;
5282
5283         if (!lane) {
5284                 /*
5285                  * Account for spread spectrum to avoid
5286                  * oversubscribing the link. Max center spread
5287                  * is 2.5%; use 5% for safety's sake.
5288                  */
5289                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5290                 lane = bps / (link_bw * 8) + 1;
5291         }
5292
5293         intel_crtc->fdi_lanes = lane;
5294
5295         if (pixel_multiplier > 1)
5296                 link_bw *= pixel_multiplier;
5297         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5298                              &m_n);
5299
5300         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5301         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5302         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5303         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5304 }
5305
5306 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5307                                       struct drm_display_mode *adjusted_mode,
5308                                       intel_clock_t *clock, u32 fp)
5309 {
5310         struct drm_crtc *crtc = &intel_crtc->base;
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         struct intel_encoder *intel_encoder;
5314         uint32_t dpll;
5315         int factor, pixel_multiplier, num_connectors = 0;
5316         bool is_lvds = false, is_sdvo = false, is_tv = false;
5317         bool is_dp = false, is_cpu_edp = false;
5318
5319         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5320                 switch (intel_encoder->type) {
5321                 case INTEL_OUTPUT_LVDS:
5322                         is_lvds = true;
5323                         break;
5324                 case INTEL_OUTPUT_SDVO:
5325                 case INTEL_OUTPUT_HDMI:
5326                         is_sdvo = true;
5327                         if (intel_encoder->needs_tv_clock)
5328                                 is_tv = true;
5329                         break;
5330                 case INTEL_OUTPUT_TVOUT:
5331                         is_tv = true;
5332                         break;
5333                 case INTEL_OUTPUT_DISPLAYPORT:
5334                         is_dp = true;
5335                         break;
5336                 case INTEL_OUTPUT_EDP:
5337                         is_dp = true;
5338                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5339                                 is_cpu_edp = true;
5340                         break;
5341                 }
5342
5343                 num_connectors++;
5344         }
5345
5346         /* Enable autotuning of the PLL clock (if permissible) */
5347         factor = 21;
5348         if (is_lvds) {
5349                 if ((intel_panel_use_ssc(dev_priv) &&
5350                      dev_priv->lvds_ssc_freq == 100) ||
5351                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5352                         factor = 25;
5353         } else if (is_sdvo && is_tv)
5354                 factor = 20;
5355
5356         if (clock->m < factor * clock->n)
5357                 fp |= FP_CB_TUNE;
5358
5359         dpll = 0;
5360
5361         if (is_lvds)
5362                 dpll |= DPLLB_MODE_LVDS;
5363         else
5364                 dpll |= DPLLB_MODE_DAC_SERIAL;
5365         if (is_sdvo) {
5366                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5367                 if (pixel_multiplier > 1) {
5368                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5369                 }
5370                 dpll |= DPLL_DVO_HIGH_SPEED;
5371         }
5372         if (is_dp && !is_cpu_edp)
5373                 dpll |= DPLL_DVO_HIGH_SPEED;
5374
5375         /* compute bitmask from p1 value */
5376         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5377         /* also FPA1 */
5378         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5379
5380         switch (clock->p2) {
5381         case 5:
5382                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5383                 break;
5384         case 7:
5385                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5386                 break;
5387         case 10:
5388                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5389                 break;
5390         case 14:
5391                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5392                 break;
5393         }
5394
5395         if (is_sdvo && is_tv)
5396                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5397         else if (is_tv)
5398                 /* XXX: just matching BIOS for now */
5399                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5400                 dpll |= 3;
5401         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5402                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5403         else
5404                 dpll |= PLL_REF_INPUT_DREFCLK;
5405
5406         return dpll;
5407 }
5408
5409 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5410                                   struct drm_display_mode *mode,
5411                                   struct drm_display_mode *adjusted_mode,
5412                                   int x, int y,
5413                                   struct drm_framebuffer *fb)
5414 {
5415         struct drm_device *dev = crtc->dev;
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418         int pipe = intel_crtc->pipe;
5419         int plane = intel_crtc->plane;
5420         int num_connectors = 0;
5421         intel_clock_t clock, reduced_clock;
5422         u32 dpll, fp = 0, fp2 = 0;
5423         bool ok, has_reduced_clock = false;
5424         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5425         struct intel_encoder *encoder;
5426         u32 temp;
5427         int ret;
5428         bool dither, fdi_config_ok;
5429
5430         for_each_encoder_on_crtc(dev, crtc, encoder) {
5431                 switch (encoder->type) {
5432                 case INTEL_OUTPUT_LVDS:
5433                         is_lvds = true;
5434                         break;
5435                 case INTEL_OUTPUT_DISPLAYPORT:
5436                         is_dp = true;
5437                         break;
5438                 case INTEL_OUTPUT_EDP:
5439                         is_dp = true;
5440                         if (!intel_encoder_is_pch_edp(&encoder->base))
5441                                 is_cpu_edp = true;
5442                         break;
5443                 }
5444
5445                 num_connectors++;
5446         }
5447
5448         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5449              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5450
5451         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5452                                      &has_reduced_clock, &reduced_clock);
5453         if (!ok) {
5454                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5455                 return -EINVAL;
5456         }
5457
5458         /* Ensure that the cursor is valid for the new mode before changing... */
5459         intel_crtc_update_cursor(crtc, true);
5460
5461         /* determine panel color depth */
5462         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5463                                               adjusted_mode);
5464         if (is_lvds && dev_priv->lvds_dither)
5465                 dither = true;
5466
5467         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5468         if (has_reduced_clock)
5469                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5470                         reduced_clock.m2;
5471
5472         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5473
5474         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5475         drm_mode_debug_printmodeline(mode);
5476
5477         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5478         if (!is_cpu_edp) {
5479                 struct intel_pch_pll *pll;
5480
5481                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5482                 if (pll == NULL) {
5483                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5484                                          pipe);
5485                         return -EINVAL;
5486                 }
5487         } else
5488                 intel_put_pch_pll(intel_crtc);
5489
5490         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5491          * This is an exception to the general rule that mode_set doesn't turn
5492          * things on.
5493          */
5494         if (is_lvds) {
5495                 temp = I915_READ(PCH_LVDS);
5496                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5497                 if (HAS_PCH_CPT(dev)) {
5498                         temp &= ~PORT_TRANS_SEL_MASK;
5499                         temp |= PORT_TRANS_SEL_CPT(pipe);
5500                 } else {
5501                         if (pipe == 1)
5502                                 temp |= LVDS_PIPEB_SELECT;
5503                         else
5504                                 temp &= ~LVDS_PIPEB_SELECT;
5505                 }
5506
5507                 /* set the corresponsding LVDS_BORDER bit */
5508                 temp |= dev_priv->lvds_border_bits;
5509                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5510                  * set the DPLLs for dual-channel mode or not.
5511                  */
5512                 if (clock.p2 == 7)
5513                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5514                 else
5515                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5516
5517                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5518                  * appropriately here, but we need to look more thoroughly into how
5519                  * panels behave in the two modes.
5520                  */
5521                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5522                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5523                         temp |= LVDS_HSYNC_POLARITY;
5524                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5525                         temp |= LVDS_VSYNC_POLARITY;
5526                 I915_WRITE(PCH_LVDS, temp);
5527         }
5528
5529         if (is_dp && !is_cpu_edp) {
5530                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5531         } else {
5532                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5533                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5534                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5535                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5536                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5537         }
5538
5539         if (intel_crtc->pch_pll) {
5540                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5541
5542                 /* Wait for the clocks to stabilize. */
5543                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5544                 udelay(150);
5545
5546                 /* The pixel multiplier can only be updated once the
5547                  * DPLL is enabled and the clocks are stable.
5548                  *
5549                  * So write it again.
5550                  */
5551                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5552         }
5553
5554         intel_crtc->lowfreq_avail = false;
5555         if (intel_crtc->pch_pll) {
5556                 if (is_lvds && has_reduced_clock && i915_powersave) {
5557                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5558                         intel_crtc->lowfreq_avail = true;
5559                 } else {
5560                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5561                 }
5562         }
5563
5564         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5565
5566         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5567          * ironlake_check_fdi_lanes. */
5568         ironlake_set_m_n(crtc, mode, adjusted_mode);
5569
5570         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5571
5572         if (is_cpu_edp)
5573                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5574
5575         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5576
5577         intel_wait_for_vblank(dev, pipe);
5578
5579         /* Set up the display plane register */
5580         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5581         POSTING_READ(DSPCNTR(plane));
5582
5583         ret = intel_pipe_set_base(crtc, x, y, fb);
5584
5585         intel_update_watermarks(dev);
5586
5587         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5588
5589         return fdi_config_ok ? ret : -EINVAL;
5590 }
5591
5592 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5593                                  struct drm_display_mode *mode,
5594                                  struct drm_display_mode *adjusted_mode,
5595                                  int x, int y,
5596                                  struct drm_framebuffer *fb)
5597 {
5598         struct drm_device *dev = crtc->dev;
5599         struct drm_i915_private *dev_priv = dev->dev_private;
5600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601         int pipe = intel_crtc->pipe;
5602         int plane = intel_crtc->plane;
5603         int num_connectors = 0;
5604         intel_clock_t clock, reduced_clock;
5605         u32 dpll = 0, fp = 0, fp2 = 0;
5606         bool ok, has_reduced_clock = false;
5607         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5608         struct intel_encoder *encoder;
5609         u32 temp;
5610         int ret;
5611         bool dither;
5612
5613         for_each_encoder_on_crtc(dev, crtc, encoder) {
5614                 switch (encoder->type) {
5615                 case INTEL_OUTPUT_LVDS:
5616                         is_lvds = true;
5617                         break;
5618                 case INTEL_OUTPUT_DISPLAYPORT:
5619                         is_dp = true;
5620                         break;
5621                 case INTEL_OUTPUT_EDP:
5622                         is_dp = true;
5623                         if (!intel_encoder_is_pch_edp(&encoder->base))
5624                                 is_cpu_edp = true;
5625                         break;
5626                 }
5627
5628                 num_connectors++;
5629         }
5630
5631         if (is_cpu_edp)
5632                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5633         else
5634                 intel_crtc->cpu_transcoder = pipe;
5635
5636         /* We are not sure yet this won't happen. */
5637         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5638              INTEL_PCH_TYPE(dev));
5639
5640         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5641              num_connectors, pipe_name(pipe));
5642
5643         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5644                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5645
5646         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5647
5648         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5649                 return -EINVAL;
5650
5651         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5652                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5653                                              &has_reduced_clock,
5654                                              &reduced_clock);
5655                 if (!ok) {
5656                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5657                         return -EINVAL;
5658                 }
5659         }
5660
5661         /* Ensure that the cursor is valid for the new mode before changing... */
5662         intel_crtc_update_cursor(crtc, true);
5663
5664         /* determine panel color depth */
5665         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5666                                               adjusted_mode);
5667         if (is_lvds && dev_priv->lvds_dither)
5668                 dither = true;
5669
5670         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5671         drm_mode_debug_printmodeline(mode);
5672
5673         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5674                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5675                 if (has_reduced_clock)
5676                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5677                               reduced_clock.m2;
5678
5679                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5680                                              fp);
5681
5682                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5683                  * own on pre-Haswell/LPT generation */
5684                 if (!is_cpu_edp) {
5685                         struct intel_pch_pll *pll;
5686
5687                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5688                         if (pll == NULL) {
5689                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5690                                                  pipe);
5691                                 return -EINVAL;
5692                         }
5693                 } else
5694                         intel_put_pch_pll(intel_crtc);
5695
5696                 /* The LVDS pin pair needs to be on before the DPLLs are
5697                  * enabled.  This is an exception to the general rule that
5698                  * mode_set doesn't turn things on.
5699                  */
5700                 if (is_lvds) {
5701                         temp = I915_READ(PCH_LVDS);
5702                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5703                         if (HAS_PCH_CPT(dev)) {
5704                                 temp &= ~PORT_TRANS_SEL_MASK;
5705                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5706                         } else {
5707                                 if (pipe == 1)
5708                                         temp |= LVDS_PIPEB_SELECT;
5709                                 else
5710                                         temp &= ~LVDS_PIPEB_SELECT;
5711                         }
5712
5713                         /* set the corresponsding LVDS_BORDER bit */
5714                         temp |= dev_priv->lvds_border_bits;
5715                         /* Set the B0-B3 data pairs corresponding to whether
5716                          * we're going to set the DPLLs for dual-channel mode or
5717                          * not.
5718                          */
5719                         if (clock.p2 == 7)
5720                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5721                         else
5722                                 temp &= ~(LVDS_B0B3_POWER_UP |
5723                                           LVDS_CLKB_POWER_UP);
5724
5725                         /* It would be nice to set 24 vs 18-bit mode
5726                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5727                          * look more thoroughly into how panels behave in the
5728                          * two modes.
5729                          */
5730                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5731                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5732                                 temp |= LVDS_HSYNC_POLARITY;
5733                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5734                                 temp |= LVDS_VSYNC_POLARITY;
5735                         I915_WRITE(PCH_LVDS, temp);
5736                 }
5737         }
5738
5739         if (is_dp && !is_cpu_edp) {
5740                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5741         } else {
5742                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5743                         /* For non-DP output, clear any trans DP clock recovery
5744                          * setting.*/
5745                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5746                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5747                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5748                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5749                 }
5750         }
5751
5752         intel_crtc->lowfreq_avail = false;
5753         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5754                 if (intel_crtc->pch_pll) {
5755                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5756
5757                         /* Wait for the clocks to stabilize. */
5758                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5759                         udelay(150);
5760
5761                         /* The pixel multiplier can only be updated once the
5762                          * DPLL is enabled and the clocks are stable.
5763                          *
5764                          * So write it again.
5765                          */
5766                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5767                 }
5768
5769                 if (intel_crtc->pch_pll) {
5770                         if (is_lvds && has_reduced_clock && i915_powersave) {
5771                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5772                                 intel_crtc->lowfreq_avail = true;
5773                         } else {
5774                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5775                         }
5776                 }
5777         }
5778
5779         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5780
5781         if (!is_dp || is_cpu_edp)
5782                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5783
5784         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5785                 if (is_cpu_edp)
5786                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5787
5788         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5789
5790         /* Set up the display plane register */
5791         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5792         POSTING_READ(DSPCNTR(plane));
5793
5794         ret = intel_pipe_set_base(crtc, x, y, fb);
5795
5796         intel_update_watermarks(dev);
5797
5798         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5799
5800         return ret;
5801 }
5802
5803 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5804                                struct drm_display_mode *mode,
5805                                struct drm_display_mode *adjusted_mode,
5806                                int x, int y,
5807                                struct drm_framebuffer *fb)
5808 {
5809         struct drm_device *dev = crtc->dev;
5810         struct drm_i915_private *dev_priv = dev->dev_private;
5811         struct drm_encoder_helper_funcs *encoder_funcs;
5812         struct intel_encoder *encoder;
5813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5814         int pipe = intel_crtc->pipe;
5815         int ret;
5816
5817         drm_vblank_pre_modeset(dev, pipe);
5818
5819         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5820                                               x, y, fb);
5821         drm_vblank_post_modeset(dev, pipe);
5822
5823         if (ret != 0)
5824                 return ret;
5825
5826         for_each_encoder_on_crtc(dev, crtc, encoder) {
5827                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5828                         encoder->base.base.id,
5829                         drm_get_encoder_name(&encoder->base),
5830                         mode->base.id, mode->name);
5831                 encoder_funcs = encoder->base.helper_private;
5832                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5833         }
5834
5835         return 0;
5836 }
5837
5838 static bool intel_eld_uptodate(struct drm_connector *connector,
5839                                int reg_eldv, uint32_t bits_eldv,
5840                                int reg_elda, uint32_t bits_elda,
5841                                int reg_edid)
5842 {
5843         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5844         uint8_t *eld = connector->eld;
5845         uint32_t i;
5846
5847         i = I915_READ(reg_eldv);
5848         i &= bits_eldv;
5849
5850         if (!eld[0])
5851                 return !i;
5852
5853         if (!i)
5854                 return false;
5855
5856         i = I915_READ(reg_elda);
5857         i &= ~bits_elda;
5858         I915_WRITE(reg_elda, i);
5859
5860         for (i = 0; i < eld[2]; i++)
5861                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5862                         return false;
5863
5864         return true;
5865 }
5866
5867 static void g4x_write_eld(struct drm_connector *connector,
5868                           struct drm_crtc *crtc)
5869 {
5870         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5871         uint8_t *eld = connector->eld;
5872         uint32_t eldv;
5873         uint32_t len;
5874         uint32_t i;
5875
5876         i = I915_READ(G4X_AUD_VID_DID);
5877
5878         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5879                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5880         else
5881                 eldv = G4X_ELDV_DEVCTG;
5882
5883         if (intel_eld_uptodate(connector,
5884                                G4X_AUD_CNTL_ST, eldv,
5885                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5886                                G4X_HDMIW_HDMIEDID))
5887                 return;
5888
5889         i = I915_READ(G4X_AUD_CNTL_ST);
5890         i &= ~(eldv | G4X_ELD_ADDR);
5891         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5892         I915_WRITE(G4X_AUD_CNTL_ST, i);
5893
5894         if (!eld[0])
5895                 return;
5896
5897         len = min_t(uint8_t, eld[2], len);
5898         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5899         for (i = 0; i < len; i++)
5900                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5901
5902         i = I915_READ(G4X_AUD_CNTL_ST);
5903         i |= eldv;
5904         I915_WRITE(G4X_AUD_CNTL_ST, i);
5905 }
5906
5907 static void haswell_write_eld(struct drm_connector *connector,
5908                                      struct drm_crtc *crtc)
5909 {
5910         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5911         uint8_t *eld = connector->eld;
5912         struct drm_device *dev = crtc->dev;
5913         uint32_t eldv;
5914         uint32_t i;
5915         int len;
5916         int pipe = to_intel_crtc(crtc)->pipe;
5917         int tmp;
5918
5919         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5920         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5921         int aud_config = HSW_AUD_CFG(pipe);
5922         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5923
5924
5925         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5926
5927         /* Audio output enable */
5928         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5929         tmp = I915_READ(aud_cntrl_st2);
5930         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5931         I915_WRITE(aud_cntrl_st2, tmp);
5932
5933         /* Wait for 1 vertical blank */
5934         intel_wait_for_vblank(dev, pipe);
5935
5936         /* Set ELD valid state */
5937         tmp = I915_READ(aud_cntrl_st2);
5938         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5939         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5940         I915_WRITE(aud_cntrl_st2, tmp);
5941         tmp = I915_READ(aud_cntrl_st2);
5942         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5943
5944         /* Enable HDMI mode */
5945         tmp = I915_READ(aud_config);
5946         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5947         /* clear N_programing_enable and N_value_index */
5948         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5949         I915_WRITE(aud_config, tmp);
5950
5951         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5952
5953         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5954
5955         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5956                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5957                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5958                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5959         } else
5960                 I915_WRITE(aud_config, 0);
5961
5962         if (intel_eld_uptodate(connector,
5963                                aud_cntrl_st2, eldv,
5964                                aud_cntl_st, IBX_ELD_ADDRESS,
5965                                hdmiw_hdmiedid))
5966                 return;
5967
5968         i = I915_READ(aud_cntrl_st2);
5969         i &= ~eldv;
5970         I915_WRITE(aud_cntrl_st2, i);
5971
5972         if (!eld[0])
5973                 return;
5974
5975         i = I915_READ(aud_cntl_st);
5976         i &= ~IBX_ELD_ADDRESS;
5977         I915_WRITE(aud_cntl_st, i);
5978         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5979         DRM_DEBUG_DRIVER("port num:%d\n", i);
5980
5981         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5982         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5983         for (i = 0; i < len; i++)
5984                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5985
5986         i = I915_READ(aud_cntrl_st2);
5987         i |= eldv;
5988         I915_WRITE(aud_cntrl_st2, i);
5989
5990 }
5991
5992 static void ironlake_write_eld(struct drm_connector *connector,
5993                                      struct drm_crtc *crtc)
5994 {
5995         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5996         uint8_t *eld = connector->eld;
5997         uint32_t eldv;
5998         uint32_t i;
5999         int len;
6000         int hdmiw_hdmiedid;
6001         int aud_config;
6002         int aud_cntl_st;
6003         int aud_cntrl_st2;
6004         int pipe = to_intel_crtc(crtc)->pipe;
6005
6006         if (HAS_PCH_IBX(connector->dev)) {
6007                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6008                 aud_config = IBX_AUD_CFG(pipe);
6009                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6010                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6011         } else {
6012                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6013                 aud_config = CPT_AUD_CFG(pipe);
6014                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6015                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6016         }
6017
6018         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6019
6020         i = I915_READ(aud_cntl_st);
6021         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6022         if (!i) {
6023                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6024                 /* operate blindly on all ports */
6025                 eldv = IBX_ELD_VALIDB;
6026                 eldv |= IBX_ELD_VALIDB << 4;
6027                 eldv |= IBX_ELD_VALIDB << 8;
6028         } else {
6029                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6030                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6031         }
6032
6033         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6034                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6035                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6036                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6037         } else
6038                 I915_WRITE(aud_config, 0);
6039
6040         if (intel_eld_uptodate(connector,
6041                                aud_cntrl_st2, eldv,
6042                                aud_cntl_st, IBX_ELD_ADDRESS,
6043                                hdmiw_hdmiedid))
6044                 return;
6045
6046         i = I915_READ(aud_cntrl_st2);
6047         i &= ~eldv;
6048         I915_WRITE(aud_cntrl_st2, i);
6049
6050         if (!eld[0])
6051                 return;
6052
6053         i = I915_READ(aud_cntl_st);
6054         i &= ~IBX_ELD_ADDRESS;
6055         I915_WRITE(aud_cntl_st, i);
6056
6057         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6058         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6059         for (i = 0; i < len; i++)
6060                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6061
6062         i = I915_READ(aud_cntrl_st2);
6063         i |= eldv;
6064         I915_WRITE(aud_cntrl_st2, i);
6065 }
6066
6067 void intel_write_eld(struct drm_encoder *encoder,
6068                      struct drm_display_mode *mode)
6069 {
6070         struct drm_crtc *crtc = encoder->crtc;
6071         struct drm_connector *connector;
6072         struct drm_device *dev = encoder->dev;
6073         struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075         connector = drm_select_eld(encoder, mode);
6076         if (!connector)
6077                 return;
6078
6079         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6080                          connector->base.id,
6081                          drm_get_connector_name(connector),
6082                          connector->encoder->base.id,
6083                          drm_get_encoder_name(connector->encoder));
6084
6085         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6086
6087         if (dev_priv->display.write_eld)
6088                 dev_priv->display.write_eld(connector, crtc);
6089 }
6090
6091 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6092 void intel_crtc_load_lut(struct drm_crtc *crtc)
6093 {
6094         struct drm_device *dev = crtc->dev;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097         int palreg = PALETTE(intel_crtc->pipe);
6098         int i;
6099
6100         /* The clocks have to be on to load the palette. */
6101         if (!crtc->enabled || !intel_crtc->active)
6102                 return;
6103
6104         /* use legacy palette for Ironlake */
6105         if (HAS_PCH_SPLIT(dev))
6106                 palreg = LGC_PALETTE(intel_crtc->pipe);
6107
6108         for (i = 0; i < 256; i++) {
6109                 I915_WRITE(palreg + 4 * i,
6110                            (intel_crtc->lut_r[i] << 16) |
6111                            (intel_crtc->lut_g[i] << 8) |
6112                            intel_crtc->lut_b[i]);
6113         }
6114 }
6115
6116 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6117 {
6118         struct drm_device *dev = crtc->dev;
6119         struct drm_i915_private *dev_priv = dev->dev_private;
6120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6121         bool visible = base != 0;
6122         u32 cntl;
6123
6124         if (intel_crtc->cursor_visible == visible)
6125                 return;
6126
6127         cntl = I915_READ(_CURACNTR);
6128         if (visible) {
6129                 /* On these chipsets we can only modify the base whilst
6130                  * the cursor is disabled.
6131                  */
6132                 I915_WRITE(_CURABASE, base);
6133
6134                 cntl &= ~(CURSOR_FORMAT_MASK);
6135                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6136                 cntl |= CURSOR_ENABLE |
6137                         CURSOR_GAMMA_ENABLE |
6138                         CURSOR_FORMAT_ARGB;
6139         } else
6140                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6141         I915_WRITE(_CURACNTR, cntl);
6142
6143         intel_crtc->cursor_visible = visible;
6144 }
6145
6146 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6147 {
6148         struct drm_device *dev = crtc->dev;
6149         struct drm_i915_private *dev_priv = dev->dev_private;
6150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151         int pipe = intel_crtc->pipe;
6152         bool visible = base != 0;
6153
6154         if (intel_crtc->cursor_visible != visible) {
6155                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6156                 if (base) {
6157                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6158                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6159                         cntl |= pipe << 28; /* Connect to correct pipe */
6160                 } else {
6161                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6162                         cntl |= CURSOR_MODE_DISABLE;
6163                 }
6164                 I915_WRITE(CURCNTR(pipe), cntl);
6165
6166                 intel_crtc->cursor_visible = visible;
6167         }
6168         /* and commit changes on next vblank */
6169         I915_WRITE(CURBASE(pipe), base);
6170 }
6171
6172 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6173 {
6174         struct drm_device *dev = crtc->dev;
6175         struct drm_i915_private *dev_priv = dev->dev_private;
6176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6177         int pipe = intel_crtc->pipe;
6178         bool visible = base != 0;
6179
6180         if (intel_crtc->cursor_visible != visible) {
6181                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6182                 if (base) {
6183                         cntl &= ~CURSOR_MODE;
6184                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6185                 } else {
6186                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6187                         cntl |= CURSOR_MODE_DISABLE;
6188                 }
6189                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6190
6191                 intel_crtc->cursor_visible = visible;
6192         }
6193         /* and commit changes on next vblank */
6194         I915_WRITE(CURBASE_IVB(pipe), base);
6195 }
6196
6197 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6198 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6199                                      bool on)
6200 {
6201         struct drm_device *dev = crtc->dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204         int pipe = intel_crtc->pipe;
6205         int x = intel_crtc->cursor_x;
6206         int y = intel_crtc->cursor_y;
6207         u32 base, pos;
6208         bool visible;
6209
6210         pos = 0;
6211
6212         if (on && crtc->enabled && crtc->fb) {
6213                 base = intel_crtc->cursor_addr;
6214                 if (x > (int) crtc->fb->width)
6215                         base = 0;
6216
6217                 if (y > (int) crtc->fb->height)
6218                         base = 0;
6219         } else
6220                 base = 0;
6221
6222         if (x < 0) {
6223                 if (x + intel_crtc->cursor_width < 0)
6224                         base = 0;
6225
6226                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6227                 x = -x;
6228         }
6229         pos |= x << CURSOR_X_SHIFT;
6230
6231         if (y < 0) {
6232                 if (y + intel_crtc->cursor_height < 0)
6233                         base = 0;
6234
6235                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6236                 y = -y;
6237         }
6238         pos |= y << CURSOR_Y_SHIFT;
6239
6240         visible = base != 0;
6241         if (!visible && !intel_crtc->cursor_visible)
6242                 return;
6243
6244         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6245                 I915_WRITE(CURPOS_IVB(pipe), pos);
6246                 ivb_update_cursor(crtc, base);
6247         } else {
6248                 I915_WRITE(CURPOS(pipe), pos);
6249                 if (IS_845G(dev) || IS_I865G(dev))
6250                         i845_update_cursor(crtc, base);
6251                 else
6252                         i9xx_update_cursor(crtc, base);
6253         }
6254 }
6255
6256 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6257                                  struct drm_file *file,
6258                                  uint32_t handle,
6259                                  uint32_t width, uint32_t height)
6260 {
6261         struct drm_device *dev = crtc->dev;
6262         struct drm_i915_private *dev_priv = dev->dev_private;
6263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264         struct drm_i915_gem_object *obj;
6265         uint32_t addr;
6266         int ret;
6267
6268         /* if we want to turn off the cursor ignore width and height */
6269         if (!handle) {
6270                 DRM_DEBUG_KMS("cursor off\n");
6271                 addr = 0;
6272                 obj = NULL;
6273                 mutex_lock(&dev->struct_mutex);
6274                 goto finish;
6275         }
6276
6277         /* Currently we only support 64x64 cursors */
6278         if (width != 64 || height != 64) {
6279                 DRM_ERROR("we currently only support 64x64 cursors\n");
6280                 return -EINVAL;
6281         }
6282
6283         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6284         if (&obj->base == NULL)
6285                 return -ENOENT;
6286
6287         if (obj->base.size < width * height * 4) {
6288                 DRM_ERROR("buffer is to small\n");
6289                 ret = -ENOMEM;
6290                 goto fail;
6291         }
6292
6293         /* we only need to pin inside GTT if cursor is non-phy */
6294         mutex_lock(&dev->struct_mutex);
6295         if (!dev_priv->info->cursor_needs_physical) {
6296                 if (obj->tiling_mode) {
6297                         DRM_ERROR("cursor cannot be tiled\n");
6298                         ret = -EINVAL;
6299                         goto fail_locked;
6300                 }
6301
6302                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6303                 if (ret) {
6304                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6305                         goto fail_locked;
6306                 }
6307
6308                 ret = i915_gem_object_put_fence(obj);
6309                 if (ret) {
6310                         DRM_ERROR("failed to release fence for cursor");
6311                         goto fail_unpin;
6312                 }
6313
6314                 addr = obj->gtt_offset;
6315         } else {
6316                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6317                 ret = i915_gem_attach_phys_object(dev, obj,
6318                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6319                                                   align);
6320                 if (ret) {
6321                         DRM_ERROR("failed to attach phys object\n");
6322                         goto fail_locked;
6323                 }
6324                 addr = obj->phys_obj->handle->busaddr;
6325         }
6326
6327         if (IS_GEN2(dev))
6328                 I915_WRITE(CURSIZE, (height << 12) | width);
6329
6330  finish:
6331         if (intel_crtc->cursor_bo) {
6332                 if (dev_priv->info->cursor_needs_physical) {
6333                         if (intel_crtc->cursor_bo != obj)
6334                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6335                 } else
6336                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6337                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6338         }
6339
6340         mutex_unlock(&dev->struct_mutex);
6341
6342         intel_crtc->cursor_addr = addr;
6343         intel_crtc->cursor_bo = obj;
6344         intel_crtc->cursor_width = width;
6345         intel_crtc->cursor_height = height;
6346
6347         intel_crtc_update_cursor(crtc, true);
6348
6349         return 0;
6350 fail_unpin:
6351         i915_gem_object_unpin(obj);
6352 fail_locked:
6353         mutex_unlock(&dev->struct_mutex);
6354 fail:
6355         drm_gem_object_unreference_unlocked(&obj->base);
6356         return ret;
6357 }
6358
6359 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6360 {
6361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362
6363         intel_crtc->cursor_x = x;
6364         intel_crtc->cursor_y = y;
6365
6366         intel_crtc_update_cursor(crtc, true);
6367
6368         return 0;
6369 }
6370
6371 /** Sets the color ramps on behalf of RandR */
6372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6373                                  u16 blue, int regno)
6374 {
6375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376
6377         intel_crtc->lut_r[regno] = red >> 8;
6378         intel_crtc->lut_g[regno] = green >> 8;
6379         intel_crtc->lut_b[regno] = blue >> 8;
6380 }
6381
6382 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6383                              u16 *blue, int regno)
6384 {
6385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386
6387         *red = intel_crtc->lut_r[regno] << 8;
6388         *green = intel_crtc->lut_g[regno] << 8;
6389         *blue = intel_crtc->lut_b[regno] << 8;
6390 }
6391
6392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6393                                  u16 *blue, uint32_t start, uint32_t size)
6394 {
6395         int end = (start + size > 256) ? 256 : start + size, i;
6396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397
6398         for (i = start; i < end; i++) {
6399                 intel_crtc->lut_r[i] = red[i] >> 8;
6400                 intel_crtc->lut_g[i] = green[i] >> 8;
6401                 intel_crtc->lut_b[i] = blue[i] >> 8;
6402         }
6403
6404         intel_crtc_load_lut(crtc);
6405 }
6406
6407 /**
6408  * Get a pipe with a simple mode set on it for doing load-based monitor
6409  * detection.
6410  *
6411  * It will be up to the load-detect code to adjust the pipe as appropriate for
6412  * its requirements.  The pipe will be connected to no other encoders.
6413  *
6414  * Currently this code will only succeed if there is a pipe with no encoders
6415  * configured for it.  In the future, it could choose to temporarily disable
6416  * some outputs to free up a pipe for its use.
6417  *
6418  * \return crtc, or NULL if no pipes are available.
6419  */
6420
6421 /* VESA 640x480x72Hz mode to set on the pipe */
6422 static struct drm_display_mode load_detect_mode = {
6423         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6424                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6425 };
6426
6427 static struct drm_framebuffer *
6428 intel_framebuffer_create(struct drm_device *dev,
6429                          struct drm_mode_fb_cmd2 *mode_cmd,
6430                          struct drm_i915_gem_object *obj)
6431 {
6432         struct intel_framebuffer *intel_fb;
6433         int ret;
6434
6435         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6436         if (!intel_fb) {
6437                 drm_gem_object_unreference_unlocked(&obj->base);
6438                 return ERR_PTR(-ENOMEM);
6439         }
6440
6441         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6442         if (ret) {
6443                 drm_gem_object_unreference_unlocked(&obj->base);
6444                 kfree(intel_fb);
6445                 return ERR_PTR(ret);
6446         }
6447
6448         return &intel_fb->base;
6449 }
6450
6451 static u32
6452 intel_framebuffer_pitch_for_width(int width, int bpp)
6453 {
6454         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6455         return ALIGN(pitch, 64);
6456 }
6457
6458 static u32
6459 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6460 {
6461         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6462         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6463 }
6464
6465 static struct drm_framebuffer *
6466 intel_framebuffer_create_for_mode(struct drm_device *dev,
6467                                   struct drm_display_mode *mode,
6468                                   int depth, int bpp)
6469 {
6470         struct drm_i915_gem_object *obj;
6471         struct drm_mode_fb_cmd2 mode_cmd;
6472
6473         obj = i915_gem_alloc_object(dev,
6474                                     intel_framebuffer_size_for_mode(mode, bpp));
6475         if (obj == NULL)
6476                 return ERR_PTR(-ENOMEM);
6477
6478         mode_cmd.width = mode->hdisplay;
6479         mode_cmd.height = mode->vdisplay;
6480         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6481                                                                 bpp);
6482         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6483
6484         return intel_framebuffer_create(dev, &mode_cmd, obj);
6485 }
6486
6487 static struct drm_framebuffer *
6488 mode_fits_in_fbdev(struct drm_device *dev,
6489                    struct drm_display_mode *mode)
6490 {
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         struct drm_i915_gem_object *obj;
6493         struct drm_framebuffer *fb;
6494
6495         if (dev_priv->fbdev == NULL)
6496                 return NULL;
6497
6498         obj = dev_priv->fbdev->ifb.obj;
6499         if (obj == NULL)
6500                 return NULL;
6501
6502         fb = &dev_priv->fbdev->ifb.base;
6503         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6504                                                                fb->bits_per_pixel))
6505                 return NULL;
6506
6507         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6508                 return NULL;
6509
6510         return fb;
6511 }
6512
6513 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6514                                 struct drm_display_mode *mode,
6515                                 struct intel_load_detect_pipe *old)
6516 {
6517         struct intel_crtc *intel_crtc;
6518         struct intel_encoder *intel_encoder =
6519                 intel_attached_encoder(connector);
6520         struct drm_crtc *possible_crtc;
6521         struct drm_encoder *encoder = &intel_encoder->base;
6522         struct drm_crtc *crtc = NULL;
6523         struct drm_device *dev = encoder->dev;
6524         struct drm_framebuffer *fb;
6525         int i = -1;
6526
6527         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6528                       connector->base.id, drm_get_connector_name(connector),
6529                       encoder->base.id, drm_get_encoder_name(encoder));
6530
6531         /*
6532          * Algorithm gets a little messy:
6533          *
6534          *   - if the connector already has an assigned crtc, use it (but make
6535          *     sure it's on first)
6536          *
6537          *   - try to find the first unused crtc that can drive this connector,
6538          *     and use that if we find one
6539          */
6540
6541         /* See if we already have a CRTC for this connector */
6542         if (encoder->crtc) {
6543                 crtc = encoder->crtc;
6544
6545                 old->dpms_mode = connector->dpms;
6546                 old->load_detect_temp = false;
6547
6548                 /* Make sure the crtc and connector are running */
6549                 if (connector->dpms != DRM_MODE_DPMS_ON)
6550                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6551
6552                 return true;
6553         }
6554
6555         /* Find an unused one (if possible) */
6556         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6557                 i++;
6558                 if (!(encoder->possible_crtcs & (1 << i)))
6559                         continue;
6560                 if (!possible_crtc->enabled) {
6561                         crtc = possible_crtc;
6562                         break;
6563                 }
6564         }
6565
6566         /*
6567          * If we didn't find an unused CRTC, don't use any.
6568          */
6569         if (!crtc) {
6570                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6571                 return false;
6572         }
6573
6574         intel_encoder->new_crtc = to_intel_crtc(crtc);
6575         to_intel_connector(connector)->new_encoder = intel_encoder;
6576
6577         intel_crtc = to_intel_crtc(crtc);
6578         old->dpms_mode = connector->dpms;
6579         old->load_detect_temp = true;
6580         old->release_fb = NULL;
6581
6582         if (!mode)
6583                 mode = &load_detect_mode;
6584
6585         /* We need a framebuffer large enough to accommodate all accesses
6586          * that the plane may generate whilst we perform load detection.
6587          * We can not rely on the fbcon either being present (we get called
6588          * during its initialisation to detect all boot displays, or it may
6589          * not even exist) or that it is large enough to satisfy the
6590          * requested mode.
6591          */
6592         fb = mode_fits_in_fbdev(dev, mode);
6593         if (fb == NULL) {
6594                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6595                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6596                 old->release_fb = fb;
6597         } else
6598                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6599         if (IS_ERR(fb)) {
6600                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6601                 goto fail;
6602         }
6603
6604         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6605                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6606                 if (old->release_fb)
6607                         old->release_fb->funcs->destroy(old->release_fb);
6608                 goto fail;
6609         }
6610
6611         /* let the connector get through one full cycle before testing */
6612         intel_wait_for_vblank(dev, intel_crtc->pipe);
6613
6614         return true;
6615 fail:
6616         connector->encoder = NULL;
6617         encoder->crtc = NULL;
6618         return false;
6619 }
6620
6621 void intel_release_load_detect_pipe(struct drm_connector *connector,
6622                                     struct intel_load_detect_pipe *old)
6623 {
6624         struct intel_encoder *intel_encoder =
6625                 intel_attached_encoder(connector);
6626         struct drm_encoder *encoder = &intel_encoder->base;
6627
6628         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6629                       connector->base.id, drm_get_connector_name(connector),
6630                       encoder->base.id, drm_get_encoder_name(encoder));
6631
6632         if (old->load_detect_temp) {
6633                 struct drm_crtc *crtc = encoder->crtc;
6634
6635                 to_intel_connector(connector)->new_encoder = NULL;
6636                 intel_encoder->new_crtc = NULL;
6637                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6638
6639                 if (old->release_fb)
6640                         old->release_fb->funcs->destroy(old->release_fb);
6641
6642                 return;
6643         }
6644
6645         /* Switch crtc and encoder back off if necessary */
6646         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6647                 connector->funcs->dpms(connector, old->dpms_mode);
6648 }
6649
6650 /* Returns the clock of the currently programmed mode of the given pipe. */
6651 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6652 {
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655         int pipe = intel_crtc->pipe;
6656         u32 dpll = I915_READ(DPLL(pipe));
6657         u32 fp;
6658         intel_clock_t clock;
6659
6660         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6661                 fp = I915_READ(FP0(pipe));
6662         else
6663                 fp = I915_READ(FP1(pipe));
6664
6665         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6666         if (IS_PINEVIEW(dev)) {
6667                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6668                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6669         } else {
6670                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6671                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6672         }
6673
6674         if (!IS_GEN2(dev)) {
6675                 if (IS_PINEVIEW(dev))
6676                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6677                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6678                 else
6679                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6680                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6681
6682                 switch (dpll & DPLL_MODE_MASK) {
6683                 case DPLLB_MODE_DAC_SERIAL:
6684                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6685                                 5 : 10;
6686                         break;
6687                 case DPLLB_MODE_LVDS:
6688                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6689                                 7 : 14;
6690                         break;
6691                 default:
6692                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6693                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6694                         return 0;
6695                 }
6696
6697                 /* XXX: Handle the 100Mhz refclk */
6698                 intel_clock(dev, 96000, &clock);
6699         } else {
6700                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6701
6702                 if (is_lvds) {
6703                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6704                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6705                         clock.p2 = 14;
6706
6707                         if ((dpll & PLL_REF_INPUT_MASK) ==
6708                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6709                                 /* XXX: might not be 66MHz */
6710                                 intel_clock(dev, 66000, &clock);
6711                         } else
6712                                 intel_clock(dev, 48000, &clock);
6713                 } else {
6714                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6715                                 clock.p1 = 2;
6716                         else {
6717                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6718                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6719                         }
6720                         if (dpll & PLL_P2_DIVIDE_BY_4)
6721                                 clock.p2 = 4;
6722                         else
6723                                 clock.p2 = 2;
6724
6725                         intel_clock(dev, 48000, &clock);
6726                 }
6727         }
6728
6729         /* XXX: It would be nice to validate the clocks, but we can't reuse
6730          * i830PllIsValid() because it relies on the xf86_config connector
6731          * configuration being accurate, which it isn't necessarily.
6732          */
6733
6734         return clock.dot;
6735 }
6736
6737 /** Returns the currently programmed mode of the given pipe. */
6738 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6739                                              struct drm_crtc *crtc)
6740 {
6741         struct drm_i915_private *dev_priv = dev->dev_private;
6742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6743         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6744         struct drm_display_mode *mode;
6745         int htot = I915_READ(HTOTAL(cpu_transcoder));
6746         int hsync = I915_READ(HSYNC(cpu_transcoder));
6747         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6748         int vsync = I915_READ(VSYNC(cpu_transcoder));
6749
6750         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6751         if (!mode)
6752                 return NULL;
6753
6754         mode->clock = intel_crtc_clock_get(dev, crtc);
6755         mode->hdisplay = (htot & 0xffff) + 1;
6756         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6757         mode->hsync_start = (hsync & 0xffff) + 1;
6758         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6759         mode->vdisplay = (vtot & 0xffff) + 1;
6760         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6761         mode->vsync_start = (vsync & 0xffff) + 1;
6762         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6763
6764         drm_mode_set_name(mode);
6765
6766         return mode;
6767 }
6768
6769 static void intel_increase_pllclock(struct drm_crtc *crtc)
6770 {
6771         struct drm_device *dev = crtc->dev;
6772         drm_i915_private_t *dev_priv = dev->dev_private;
6773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6774         int pipe = intel_crtc->pipe;
6775         int dpll_reg = DPLL(pipe);
6776         int dpll;
6777
6778         if (HAS_PCH_SPLIT(dev))
6779                 return;
6780
6781         if (!dev_priv->lvds_downclock_avail)
6782                 return;
6783
6784         dpll = I915_READ(dpll_reg);
6785         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6786                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6787
6788                 assert_panel_unlocked(dev_priv, pipe);
6789
6790                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6791                 I915_WRITE(dpll_reg, dpll);
6792                 intel_wait_for_vblank(dev, pipe);
6793
6794                 dpll = I915_READ(dpll_reg);
6795                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6796                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6797         }
6798 }
6799
6800 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6801 {
6802         struct drm_device *dev = crtc->dev;
6803         drm_i915_private_t *dev_priv = dev->dev_private;
6804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6805
6806         if (HAS_PCH_SPLIT(dev))
6807                 return;
6808
6809         if (!dev_priv->lvds_downclock_avail)
6810                 return;
6811
6812         /*
6813          * Since this is called by a timer, we should never get here in
6814          * the manual case.
6815          */
6816         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6817                 int pipe = intel_crtc->pipe;
6818                 int dpll_reg = DPLL(pipe);
6819                 int dpll;
6820
6821                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6822
6823                 assert_panel_unlocked(dev_priv, pipe);
6824
6825                 dpll = I915_READ(dpll_reg);
6826                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6827                 I915_WRITE(dpll_reg, dpll);
6828                 intel_wait_for_vblank(dev, pipe);
6829                 dpll = I915_READ(dpll_reg);
6830                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6831                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6832         }
6833
6834 }
6835
6836 void intel_mark_busy(struct drm_device *dev)
6837 {
6838         i915_update_gfx_val(dev->dev_private);
6839 }
6840
6841 void intel_mark_idle(struct drm_device *dev)
6842 {
6843 }
6844
6845 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6846 {
6847         struct drm_device *dev = obj->base.dev;
6848         struct drm_crtc *crtc;
6849
6850         if (!i915_powersave)
6851                 return;
6852
6853         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6854                 if (!crtc->fb)
6855                         continue;
6856
6857                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6858                         intel_increase_pllclock(crtc);
6859         }
6860 }
6861
6862 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6863 {
6864         struct drm_device *dev = obj->base.dev;
6865         struct drm_crtc *crtc;
6866
6867         if (!i915_powersave)
6868                 return;
6869
6870         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6871                 if (!crtc->fb)
6872                         continue;
6873
6874                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6875                         intel_decrease_pllclock(crtc);
6876         }
6877 }
6878
6879 static void intel_crtc_destroy(struct drm_crtc *crtc)
6880 {
6881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6882         struct drm_device *dev = crtc->dev;
6883         struct intel_unpin_work *work;
6884         unsigned long flags;
6885
6886         spin_lock_irqsave(&dev->event_lock, flags);
6887         work = intel_crtc->unpin_work;
6888         intel_crtc->unpin_work = NULL;
6889         spin_unlock_irqrestore(&dev->event_lock, flags);
6890
6891         if (work) {
6892                 cancel_work_sync(&work->work);
6893                 kfree(work);
6894         }
6895
6896         drm_crtc_cleanup(crtc);
6897
6898         kfree(intel_crtc);
6899 }
6900
6901 static void intel_unpin_work_fn(struct work_struct *__work)
6902 {
6903         struct intel_unpin_work *work =
6904                 container_of(__work, struct intel_unpin_work, work);
6905
6906         mutex_lock(&work->dev->struct_mutex);
6907         intel_unpin_fb_obj(work->old_fb_obj);
6908         drm_gem_object_unreference(&work->pending_flip_obj->base);
6909         drm_gem_object_unreference(&work->old_fb_obj->base);
6910
6911         intel_update_fbc(work->dev);
6912         mutex_unlock(&work->dev->struct_mutex);
6913         kfree(work);
6914 }
6915
6916 static void do_intel_finish_page_flip(struct drm_device *dev,
6917                                       struct drm_crtc *crtc)
6918 {
6919         drm_i915_private_t *dev_priv = dev->dev_private;
6920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6921         struct intel_unpin_work *work;
6922         struct drm_i915_gem_object *obj;
6923         struct drm_pending_vblank_event *e;
6924         struct timeval tvbl;
6925         unsigned long flags;
6926
6927         /* Ignore early vblank irqs */
6928         if (intel_crtc == NULL)
6929                 return;
6930
6931         spin_lock_irqsave(&dev->event_lock, flags);
6932         work = intel_crtc->unpin_work;
6933         if (work == NULL || !work->pending) {
6934                 spin_unlock_irqrestore(&dev->event_lock, flags);
6935                 return;
6936         }
6937
6938         intel_crtc->unpin_work = NULL;
6939
6940         if (work->event) {
6941                 e = work->event;
6942                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6943
6944                 e->event.tv_sec = tvbl.tv_sec;
6945                 e->event.tv_usec = tvbl.tv_usec;
6946
6947                 list_add_tail(&e->base.link,
6948                               &e->base.file_priv->event_list);
6949                 wake_up_interruptible(&e->base.file_priv->event_wait);
6950         }
6951
6952         drm_vblank_put(dev, intel_crtc->pipe);
6953
6954         spin_unlock_irqrestore(&dev->event_lock, flags);
6955
6956         obj = work->old_fb_obj;
6957
6958         atomic_clear_mask(1 << intel_crtc->plane,
6959                           &obj->pending_flip.counter);
6960
6961         wake_up(&dev_priv->pending_flip_queue);
6962         schedule_work(&work->work);
6963
6964         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6965 }
6966
6967 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6968 {
6969         drm_i915_private_t *dev_priv = dev->dev_private;
6970         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6971
6972         do_intel_finish_page_flip(dev, crtc);
6973 }
6974
6975 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6976 {
6977         drm_i915_private_t *dev_priv = dev->dev_private;
6978         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6979
6980         do_intel_finish_page_flip(dev, crtc);
6981 }
6982
6983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6984 {
6985         drm_i915_private_t *dev_priv = dev->dev_private;
6986         struct intel_crtc *intel_crtc =
6987                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6988         unsigned long flags;
6989
6990         spin_lock_irqsave(&dev->event_lock, flags);
6991         if (intel_crtc->unpin_work) {
6992                 if ((++intel_crtc->unpin_work->pending) > 1)
6993                         DRM_ERROR("Prepared flip multiple times\n");
6994         } else {
6995                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6996         }
6997         spin_unlock_irqrestore(&dev->event_lock, flags);
6998 }
6999
7000 static int intel_gen2_queue_flip(struct drm_device *dev,
7001                                  struct drm_crtc *crtc,
7002                                  struct drm_framebuffer *fb,
7003                                  struct drm_i915_gem_object *obj)
7004 {
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007         u32 flip_mask;
7008         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7009         int ret;
7010
7011         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7012         if (ret)
7013                 goto err;
7014
7015         ret = intel_ring_begin(ring, 6);
7016         if (ret)
7017                 goto err_unpin;
7018
7019         /* Can't queue multiple flips, so wait for the previous
7020          * one to finish before executing the next.
7021          */
7022         if (intel_crtc->plane)
7023                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7024         else
7025                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7026         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7027         intel_ring_emit(ring, MI_NOOP);
7028         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7029                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7030         intel_ring_emit(ring, fb->pitches[0]);
7031         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7032         intel_ring_emit(ring, 0); /* aux display base address, unused */
7033         intel_ring_advance(ring);
7034         return 0;
7035
7036 err_unpin:
7037         intel_unpin_fb_obj(obj);
7038 err:
7039         return ret;
7040 }
7041
7042 static int intel_gen3_queue_flip(struct drm_device *dev,
7043                                  struct drm_crtc *crtc,
7044                                  struct drm_framebuffer *fb,
7045                                  struct drm_i915_gem_object *obj)
7046 {
7047         struct drm_i915_private *dev_priv = dev->dev_private;
7048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7049         u32 flip_mask;
7050         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7051         int ret;
7052
7053         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7054         if (ret)
7055                 goto err;
7056
7057         ret = intel_ring_begin(ring, 6);
7058         if (ret)
7059                 goto err_unpin;
7060
7061         if (intel_crtc->plane)
7062                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7063         else
7064                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7065         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7066         intel_ring_emit(ring, MI_NOOP);
7067         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7068                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7069         intel_ring_emit(ring, fb->pitches[0]);
7070         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7071         intel_ring_emit(ring, MI_NOOP);
7072
7073         intel_ring_advance(ring);
7074         return 0;
7075
7076 err_unpin:
7077         intel_unpin_fb_obj(obj);
7078 err:
7079         return ret;
7080 }
7081
7082 static int intel_gen4_queue_flip(struct drm_device *dev,
7083                                  struct drm_crtc *crtc,
7084                                  struct drm_framebuffer *fb,
7085                                  struct drm_i915_gem_object *obj)
7086 {
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089         uint32_t pf, pipesrc;
7090         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7091         int ret;
7092
7093         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7094         if (ret)
7095                 goto err;
7096
7097         ret = intel_ring_begin(ring, 4);
7098         if (ret)
7099                 goto err_unpin;
7100
7101         /* i965+ uses the linear or tiled offsets from the
7102          * Display Registers (which do not change across a page-flip)
7103          * so we need only reprogram the base address.
7104          */
7105         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7106                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7107         intel_ring_emit(ring, fb->pitches[0]);
7108         intel_ring_emit(ring,
7109                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7110                         obj->tiling_mode);
7111
7112         /* XXX Enabling the panel-fitter across page-flip is so far
7113          * untested on non-native modes, so ignore it for now.
7114          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7115          */
7116         pf = 0;
7117         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7118         intel_ring_emit(ring, pf | pipesrc);
7119         intel_ring_advance(ring);
7120         return 0;
7121
7122 err_unpin:
7123         intel_unpin_fb_obj(obj);
7124 err:
7125         return ret;
7126 }
7127
7128 static int intel_gen6_queue_flip(struct drm_device *dev,
7129                                  struct drm_crtc *crtc,
7130                                  struct drm_framebuffer *fb,
7131                                  struct drm_i915_gem_object *obj)
7132 {
7133         struct drm_i915_private *dev_priv = dev->dev_private;
7134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7136         uint32_t pf, pipesrc;
7137         int ret;
7138
7139         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7140         if (ret)
7141                 goto err;
7142
7143         ret = intel_ring_begin(ring, 4);
7144         if (ret)
7145                 goto err_unpin;
7146
7147         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7148                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7149         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7150         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7151
7152         /* Contrary to the suggestions in the documentation,
7153          * "Enable Panel Fitter" does not seem to be required when page
7154          * flipping with a non-native mode, and worse causes a normal
7155          * modeset to fail.
7156          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7157          */
7158         pf = 0;
7159         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7160         intel_ring_emit(ring, pf | pipesrc);
7161         intel_ring_advance(ring);
7162         return 0;
7163
7164 err_unpin:
7165         intel_unpin_fb_obj(obj);
7166 err:
7167         return ret;
7168 }
7169
7170 /*
7171  * On gen7 we currently use the blit ring because (in early silicon at least)
7172  * the render ring doesn't give us interrpts for page flip completion, which
7173  * means clients will hang after the first flip is queued.  Fortunately the
7174  * blit ring generates interrupts properly, so use it instead.
7175  */
7176 static int intel_gen7_queue_flip(struct drm_device *dev,
7177                                  struct drm_crtc *crtc,
7178                                  struct drm_framebuffer *fb,
7179                                  struct drm_i915_gem_object *obj)
7180 {
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7184         uint32_t plane_bit = 0;
7185         int ret;
7186
7187         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7188         if (ret)
7189                 goto err;
7190
7191         switch(intel_crtc->plane) {
7192         case PLANE_A:
7193                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7194                 break;
7195         case PLANE_B:
7196                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7197                 break;
7198         case PLANE_C:
7199                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7200                 break;
7201         default:
7202                 WARN_ONCE(1, "unknown plane in flip command\n");
7203                 ret = -ENODEV;
7204                 goto err_unpin;
7205         }
7206
7207         ret = intel_ring_begin(ring, 4);
7208         if (ret)
7209                 goto err_unpin;
7210
7211         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7212         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7213         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7214         intel_ring_emit(ring, (MI_NOOP));
7215         intel_ring_advance(ring);
7216         return 0;
7217
7218 err_unpin:
7219         intel_unpin_fb_obj(obj);
7220 err:
7221         return ret;
7222 }
7223
7224 static int intel_default_queue_flip(struct drm_device *dev,
7225                                     struct drm_crtc *crtc,
7226                                     struct drm_framebuffer *fb,
7227                                     struct drm_i915_gem_object *obj)
7228 {
7229         return -ENODEV;
7230 }
7231
7232 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7233                                 struct drm_framebuffer *fb,
7234                                 struct drm_pending_vblank_event *event)
7235 {
7236         struct drm_device *dev = crtc->dev;
7237         struct drm_i915_private *dev_priv = dev->dev_private;
7238         struct intel_framebuffer *intel_fb;
7239         struct drm_i915_gem_object *obj;
7240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7241         struct intel_unpin_work *work;
7242         unsigned long flags;
7243         int ret;
7244
7245         /* Can't change pixel format via MI display flips. */
7246         if (fb->pixel_format != crtc->fb->pixel_format)
7247                 return -EINVAL;
7248
7249         /*
7250          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7251          * Note that pitch changes could also affect these register.
7252          */
7253         if (INTEL_INFO(dev)->gen > 3 &&
7254             (fb->offsets[0] != crtc->fb->offsets[0] ||
7255              fb->pitches[0] != crtc->fb->pitches[0]))
7256                 return -EINVAL;
7257
7258         work = kzalloc(sizeof *work, GFP_KERNEL);
7259         if (work == NULL)
7260                 return -ENOMEM;
7261
7262         work->event = event;
7263         work->dev = crtc->dev;
7264         intel_fb = to_intel_framebuffer(crtc->fb);
7265         work->old_fb_obj = intel_fb->obj;
7266         INIT_WORK(&work->work, intel_unpin_work_fn);
7267
7268         ret = drm_vblank_get(dev, intel_crtc->pipe);
7269         if (ret)
7270                 goto free_work;
7271
7272         /* We borrow the event spin lock for protecting unpin_work */
7273         spin_lock_irqsave(&dev->event_lock, flags);
7274         if (intel_crtc->unpin_work) {
7275                 spin_unlock_irqrestore(&dev->event_lock, flags);
7276                 kfree(work);
7277                 drm_vblank_put(dev, intel_crtc->pipe);
7278
7279                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7280                 return -EBUSY;
7281         }
7282         intel_crtc->unpin_work = work;
7283         spin_unlock_irqrestore(&dev->event_lock, flags);
7284
7285         intel_fb = to_intel_framebuffer(fb);
7286         obj = intel_fb->obj;
7287
7288         ret = i915_mutex_lock_interruptible(dev);
7289         if (ret)
7290                 goto cleanup;
7291
7292         /* Reference the objects for the scheduled work. */
7293         drm_gem_object_reference(&work->old_fb_obj->base);
7294         drm_gem_object_reference(&obj->base);
7295
7296         crtc->fb = fb;
7297
7298         work->pending_flip_obj = obj;
7299
7300         work->enable_stall_check = true;
7301
7302         /* Block clients from rendering to the new back buffer until
7303          * the flip occurs and the object is no longer visible.
7304          */
7305         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7306
7307         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7308         if (ret)
7309                 goto cleanup_pending;
7310
7311         intel_disable_fbc(dev);
7312         intel_mark_fb_busy(obj);
7313         mutex_unlock(&dev->struct_mutex);
7314
7315         trace_i915_flip_request(intel_crtc->plane, obj);
7316
7317         return 0;
7318
7319 cleanup_pending:
7320         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7321         drm_gem_object_unreference(&work->old_fb_obj->base);
7322         drm_gem_object_unreference(&obj->base);
7323         mutex_unlock(&dev->struct_mutex);
7324
7325 cleanup:
7326         spin_lock_irqsave(&dev->event_lock, flags);
7327         intel_crtc->unpin_work = NULL;
7328         spin_unlock_irqrestore(&dev->event_lock, flags);
7329
7330         drm_vblank_put(dev, intel_crtc->pipe);
7331 free_work:
7332         kfree(work);
7333
7334         return ret;
7335 }
7336
7337 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7338         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7339         .load_lut = intel_crtc_load_lut,
7340         .disable = intel_crtc_noop,
7341 };
7342
7343 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7344 {
7345         struct intel_encoder *other_encoder;
7346         struct drm_crtc *crtc = &encoder->new_crtc->base;
7347
7348         if (WARN_ON(!crtc))
7349                 return false;
7350
7351         list_for_each_entry(other_encoder,
7352                             &crtc->dev->mode_config.encoder_list,
7353                             base.head) {
7354
7355                 if (&other_encoder->new_crtc->base != crtc ||
7356                     encoder == other_encoder)
7357                         continue;
7358                 else
7359                         return true;
7360         }
7361
7362         return false;
7363 }
7364
7365 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7366                                   struct drm_crtc *crtc)
7367 {
7368         struct drm_device *dev;
7369         struct drm_crtc *tmp;
7370         int crtc_mask = 1;
7371
7372         WARN(!crtc, "checking null crtc?\n");
7373
7374         dev = crtc->dev;
7375
7376         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7377                 if (tmp == crtc)
7378                         break;
7379                 crtc_mask <<= 1;
7380         }
7381
7382         if (encoder->possible_crtcs & crtc_mask)
7383                 return true;
7384         return false;
7385 }
7386
7387 /**
7388  * intel_modeset_update_staged_output_state
7389  *
7390  * Updates the staged output configuration state, e.g. after we've read out the
7391  * current hw state.
7392  */
7393 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7394 {
7395         struct intel_encoder *encoder;
7396         struct intel_connector *connector;
7397
7398         list_for_each_entry(connector, &dev->mode_config.connector_list,
7399                             base.head) {
7400                 connector->new_encoder =
7401                         to_intel_encoder(connector->base.encoder);
7402         }
7403
7404         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7405                             base.head) {
7406                 encoder->new_crtc =
7407                         to_intel_crtc(encoder->base.crtc);
7408         }
7409 }
7410
7411 /**
7412  * intel_modeset_commit_output_state
7413  *
7414  * This function copies the stage display pipe configuration to the real one.
7415  */
7416 static void intel_modeset_commit_output_state(struct drm_device *dev)
7417 {
7418         struct intel_encoder *encoder;
7419         struct intel_connector *connector;
7420
7421         list_for_each_entry(connector, &dev->mode_config.connector_list,
7422                             base.head) {
7423                 connector->base.encoder = &connector->new_encoder->base;
7424         }
7425
7426         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7427                             base.head) {
7428                 encoder->base.crtc = &encoder->new_crtc->base;
7429         }
7430 }
7431
7432 static struct drm_display_mode *
7433 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7434                             struct drm_display_mode *mode)
7435 {
7436         struct drm_device *dev = crtc->dev;
7437         struct drm_display_mode *adjusted_mode;
7438         struct drm_encoder_helper_funcs *encoder_funcs;
7439         struct intel_encoder *encoder;
7440
7441         adjusted_mode = drm_mode_duplicate(dev, mode);
7442         if (!adjusted_mode)
7443                 return ERR_PTR(-ENOMEM);
7444
7445         /* Pass our mode to the connectors and the CRTC to give them a chance to
7446          * adjust it according to limitations or connector properties, and also
7447          * a chance to reject the mode entirely.
7448          */
7449         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7450                             base.head) {
7451
7452                 if (&encoder->new_crtc->base != crtc)
7453                         continue;
7454                 encoder_funcs = encoder->base.helper_private;
7455                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7456                                                 adjusted_mode))) {
7457                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7458                         goto fail;
7459                 }
7460         }
7461
7462         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7463                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7464                 goto fail;
7465         }
7466         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7467
7468         return adjusted_mode;
7469 fail:
7470         drm_mode_destroy(dev, adjusted_mode);
7471         return ERR_PTR(-EINVAL);
7472 }
7473
7474 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7475  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7476 static void
7477 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7478                              unsigned *prepare_pipes, unsigned *disable_pipes)
7479 {
7480         struct intel_crtc *intel_crtc;
7481         struct drm_device *dev = crtc->dev;
7482         struct intel_encoder *encoder;
7483         struct intel_connector *connector;
7484         struct drm_crtc *tmp_crtc;
7485
7486         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7487
7488         /* Check which crtcs have changed outputs connected to them, these need
7489          * to be part of the prepare_pipes mask. We don't (yet) support global
7490          * modeset across multiple crtcs, so modeset_pipes will only have one
7491          * bit set at most. */
7492         list_for_each_entry(connector, &dev->mode_config.connector_list,
7493                             base.head) {
7494                 if (connector->base.encoder == &connector->new_encoder->base)
7495                         continue;
7496
7497                 if (connector->base.encoder) {
7498                         tmp_crtc = connector->base.encoder->crtc;
7499
7500                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7501                 }
7502
7503                 if (connector->new_encoder)
7504                         *prepare_pipes |=
7505                                 1 << connector->new_encoder->new_crtc->pipe;
7506         }
7507
7508         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7509                             base.head) {
7510                 if (encoder->base.crtc == &encoder->new_crtc->base)
7511                         continue;
7512
7513                 if (encoder->base.crtc) {
7514                         tmp_crtc = encoder->base.crtc;
7515
7516                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7517                 }
7518
7519                 if (encoder->new_crtc)
7520                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7521         }
7522
7523         /* Check for any pipes that will be fully disabled ... */
7524         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7525                             base.head) {
7526                 bool used = false;
7527
7528                 /* Don't try to disable disabled crtcs. */
7529                 if (!intel_crtc->base.enabled)
7530                         continue;
7531
7532                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7533                                     base.head) {
7534                         if (encoder->new_crtc == intel_crtc)
7535                                 used = true;
7536                 }
7537
7538                 if (!used)
7539                         *disable_pipes |= 1 << intel_crtc->pipe;
7540         }
7541
7542
7543         /* set_mode is also used to update properties on life display pipes. */
7544         intel_crtc = to_intel_crtc(crtc);
7545         if (crtc->enabled)
7546                 *prepare_pipes |= 1 << intel_crtc->pipe;
7547
7548         /* We only support modeset on one single crtc, hence we need to do that
7549          * only for the passed in crtc iff we change anything else than just
7550          * disable crtcs.
7551          *
7552          * This is actually not true, to be fully compatible with the old crtc
7553          * helper we automatically disable _any_ output (i.e. doesn't need to be
7554          * connected to the crtc we're modesetting on) if it's disconnected.
7555          * Which is a rather nutty api (since changed the output configuration
7556          * without userspace's explicit request can lead to confusion), but
7557          * alas. Hence we currently need to modeset on all pipes we prepare. */
7558         if (*prepare_pipes)
7559                 *modeset_pipes = *prepare_pipes;
7560
7561         /* ... and mask these out. */
7562         *modeset_pipes &= ~(*disable_pipes);
7563         *prepare_pipes &= ~(*disable_pipes);
7564 }
7565
7566 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7567 {
7568         struct drm_encoder *encoder;
7569         struct drm_device *dev = crtc->dev;
7570
7571         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7572                 if (encoder->crtc == crtc)
7573                         return true;
7574
7575         return false;
7576 }
7577
7578 static void
7579 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7580 {
7581         struct intel_encoder *intel_encoder;
7582         struct intel_crtc *intel_crtc;
7583         struct drm_connector *connector;
7584
7585         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7586                             base.head) {
7587                 if (!intel_encoder->base.crtc)
7588                         continue;
7589
7590                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7591
7592                 if (prepare_pipes & (1 << intel_crtc->pipe))
7593                         intel_encoder->connectors_active = false;
7594         }
7595
7596         intel_modeset_commit_output_state(dev);
7597
7598         /* Update computed state. */
7599         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7600                             base.head) {
7601                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7602         }
7603
7604         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7605                 if (!connector->encoder || !connector->encoder->crtc)
7606                         continue;
7607
7608                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7609
7610                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7611                         struct drm_property *dpms_property =
7612                                 dev->mode_config.dpms_property;
7613
7614                         connector->dpms = DRM_MODE_DPMS_ON;
7615                         drm_connector_property_set_value(connector,
7616                                                          dpms_property,
7617                                                          DRM_MODE_DPMS_ON);
7618
7619                         intel_encoder = to_intel_encoder(connector->encoder);
7620                         intel_encoder->connectors_active = true;
7621                 }
7622         }
7623
7624 }
7625
7626 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7627         list_for_each_entry((intel_crtc), \
7628                             &(dev)->mode_config.crtc_list, \
7629                             base.head) \
7630                 if (mask & (1 <<(intel_crtc)->pipe)) \
7631
7632 void
7633 intel_modeset_check_state(struct drm_device *dev)
7634 {
7635         struct intel_crtc *crtc;
7636         struct intel_encoder *encoder;
7637         struct intel_connector *connector;
7638
7639         list_for_each_entry(connector, &dev->mode_config.connector_list,
7640                             base.head) {
7641                 /* This also checks the encoder/connector hw state with the
7642                  * ->get_hw_state callbacks. */
7643                 intel_connector_check_state(connector);
7644
7645                 WARN(&connector->new_encoder->base != connector->base.encoder,
7646                      "connector's staged encoder doesn't match current encoder\n");
7647         }
7648
7649         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7650                             base.head) {
7651                 bool enabled = false;
7652                 bool active = false;
7653                 enum pipe pipe, tracked_pipe;
7654
7655                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7656                               encoder->base.base.id,
7657                               drm_get_encoder_name(&encoder->base));
7658
7659                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7660                      "encoder's stage crtc doesn't match current crtc\n");
7661                 WARN(encoder->connectors_active && !encoder->base.crtc,
7662                      "encoder's active_connectors set, but no crtc\n");
7663
7664                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7665                                     base.head) {
7666                         if (connector->base.encoder != &encoder->base)
7667                                 continue;
7668                         enabled = true;
7669                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7670                                 active = true;
7671                 }
7672                 WARN(!!encoder->base.crtc != enabled,
7673                      "encoder's enabled state mismatch "
7674                      "(expected %i, found %i)\n",
7675                      !!encoder->base.crtc, enabled);
7676                 WARN(active && !encoder->base.crtc,
7677                      "active encoder with no crtc\n");
7678
7679                 WARN(encoder->connectors_active != active,
7680                      "encoder's computed active state doesn't match tracked active state "
7681                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7682
7683                 active = encoder->get_hw_state(encoder, &pipe);
7684                 WARN(active != encoder->connectors_active,
7685                      "encoder's hw state doesn't match sw tracking "
7686                      "(expected %i, found %i)\n",
7687                      encoder->connectors_active, active);
7688
7689                 if (!encoder->base.crtc)
7690                         continue;
7691
7692                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7693                 WARN(active && pipe != tracked_pipe,
7694                      "active encoder's pipe doesn't match"
7695                      "(expected %i, found %i)\n",
7696                      tracked_pipe, pipe);
7697
7698         }
7699
7700         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7701                             base.head) {
7702                 bool enabled = false;
7703                 bool active = false;
7704
7705                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7706                               crtc->base.base.id);
7707
7708                 WARN(crtc->active && !crtc->base.enabled,
7709                      "active crtc, but not enabled in sw tracking\n");
7710
7711                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7712                                     base.head) {
7713                         if (encoder->base.crtc != &crtc->base)
7714                                 continue;
7715                         enabled = true;
7716                         if (encoder->connectors_active)
7717                                 active = true;
7718                 }
7719                 WARN(active != crtc->active,
7720                      "crtc's computed active state doesn't match tracked active state "
7721                      "(expected %i, found %i)\n", active, crtc->active);
7722                 WARN(enabled != crtc->base.enabled,
7723                      "crtc's computed enabled state doesn't match tracked enabled state "
7724                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7725
7726                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7727         }
7728 }
7729
7730 bool intel_set_mode(struct drm_crtc *crtc,
7731                     struct drm_display_mode *mode,
7732                     int x, int y, struct drm_framebuffer *fb)
7733 {
7734         struct drm_device *dev = crtc->dev;
7735         drm_i915_private_t *dev_priv = dev->dev_private;
7736         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7737         struct intel_crtc *intel_crtc;
7738         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7739         bool ret = true;
7740
7741         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7742                                      &prepare_pipes, &disable_pipes);
7743
7744         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7745                       modeset_pipes, prepare_pipes, disable_pipes);
7746
7747         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7748                 intel_crtc_disable(&intel_crtc->base);
7749
7750         saved_hwmode = crtc->hwmode;
7751         saved_mode = crtc->mode;
7752
7753         /* Hack: Because we don't (yet) support global modeset on multiple
7754          * crtcs, we don't keep track of the new mode for more than one crtc.
7755          * Hence simply check whether any bit is set in modeset_pipes in all the
7756          * pieces of code that are not yet converted to deal with mutliple crtcs
7757          * changing their mode at the same time. */
7758         adjusted_mode = NULL;
7759         if (modeset_pipes) {
7760                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7761                 if (IS_ERR(adjusted_mode)) {
7762                         return false;
7763                 }
7764         }
7765
7766         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7767                 if (intel_crtc->base.enabled)
7768                         dev_priv->display.crtc_disable(&intel_crtc->base);
7769         }
7770
7771         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7772          * to set it here already despite that we pass it down the callchain.
7773          */
7774         if (modeset_pipes)
7775                 crtc->mode = *mode;
7776
7777         /* Only after disabling all output pipelines that will be changed can we
7778          * update the the output configuration. */
7779         intel_modeset_update_state(dev, prepare_pipes);
7780
7781         if (dev_priv->display.modeset_global_resources)
7782                 dev_priv->display.modeset_global_resources(dev);
7783
7784         /* Set up the DPLL and any encoders state that needs to adjust or depend
7785          * on the DPLL.
7786          */
7787         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7788                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7789                                            mode, adjusted_mode,
7790                                            x, y, fb);
7791                 if (!ret)
7792                     goto done;
7793         }
7794
7795         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7796         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7797                 dev_priv->display.crtc_enable(&intel_crtc->base);
7798
7799         if (modeset_pipes) {
7800                 /* Store real post-adjustment hardware mode. */
7801                 crtc->hwmode = *adjusted_mode;
7802
7803                 /* Calculate and store various constants which
7804                  * are later needed by vblank and swap-completion
7805                  * timestamping. They are derived from true hwmode.
7806                  */
7807                 drm_calc_timestamping_constants(crtc);
7808         }
7809
7810         /* FIXME: add subpixel order */
7811 done:
7812         drm_mode_destroy(dev, adjusted_mode);
7813         if (!ret && crtc->enabled) {
7814                 crtc->hwmode = saved_hwmode;
7815                 crtc->mode = saved_mode;
7816         } else {
7817                 intel_modeset_check_state(dev);
7818         }
7819
7820         return ret;
7821 }
7822
7823 #undef for_each_intel_crtc_masked
7824
7825 static void intel_set_config_free(struct intel_set_config *config)
7826 {
7827         if (!config)
7828                 return;
7829
7830         kfree(config->save_connector_encoders);
7831         kfree(config->save_encoder_crtcs);
7832         kfree(config);
7833 }
7834
7835 static int intel_set_config_save_state(struct drm_device *dev,
7836                                        struct intel_set_config *config)
7837 {
7838         struct drm_encoder *encoder;
7839         struct drm_connector *connector;
7840         int count;
7841
7842         config->save_encoder_crtcs =
7843                 kcalloc(dev->mode_config.num_encoder,
7844                         sizeof(struct drm_crtc *), GFP_KERNEL);
7845         if (!config->save_encoder_crtcs)
7846                 return -ENOMEM;
7847
7848         config->save_connector_encoders =
7849                 kcalloc(dev->mode_config.num_connector,
7850                         sizeof(struct drm_encoder *), GFP_KERNEL);
7851         if (!config->save_connector_encoders)
7852                 return -ENOMEM;
7853
7854         /* Copy data. Note that driver private data is not affected.
7855          * Should anything bad happen only the expected state is
7856          * restored, not the drivers personal bookkeeping.
7857          */
7858         count = 0;
7859         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7860                 config->save_encoder_crtcs[count++] = encoder->crtc;
7861         }
7862
7863         count = 0;
7864         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7865                 config->save_connector_encoders[count++] = connector->encoder;
7866         }
7867
7868         return 0;
7869 }
7870
7871 static void intel_set_config_restore_state(struct drm_device *dev,
7872                                            struct intel_set_config *config)
7873 {
7874         struct intel_encoder *encoder;
7875         struct intel_connector *connector;
7876         int count;
7877
7878         count = 0;
7879         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7880                 encoder->new_crtc =
7881                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7882         }
7883
7884         count = 0;
7885         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7886                 connector->new_encoder =
7887                         to_intel_encoder(config->save_connector_encoders[count++]);
7888         }
7889 }
7890
7891 static void
7892 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7893                                       struct intel_set_config *config)
7894 {
7895
7896         /* We should be able to check here if the fb has the same properties
7897          * and then just flip_or_move it */
7898         if (set->crtc->fb != set->fb) {
7899                 /* If we have no fb then treat it as a full mode set */
7900                 if (set->crtc->fb == NULL) {
7901                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7902                         config->mode_changed = true;
7903                 } else if (set->fb == NULL) {
7904                         config->mode_changed = true;
7905                 } else if (set->fb->depth != set->crtc->fb->depth) {
7906                         config->mode_changed = true;
7907                 } else if (set->fb->bits_per_pixel !=
7908                            set->crtc->fb->bits_per_pixel) {
7909                         config->mode_changed = true;
7910                 } else
7911                         config->fb_changed = true;
7912         }
7913
7914         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7915                 config->fb_changed = true;
7916
7917         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7918                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7919                 drm_mode_debug_printmodeline(&set->crtc->mode);
7920                 drm_mode_debug_printmodeline(set->mode);
7921                 config->mode_changed = true;
7922         }
7923 }
7924
7925 static int
7926 intel_modeset_stage_output_state(struct drm_device *dev,
7927                                  struct drm_mode_set *set,
7928                                  struct intel_set_config *config)
7929 {
7930         struct drm_crtc *new_crtc;
7931         struct intel_connector *connector;
7932         struct intel_encoder *encoder;
7933         int count, ro;
7934
7935         /* The upper layers ensure that we either disabl a crtc or have a list
7936          * of connectors. For paranoia, double-check this. */
7937         WARN_ON(!set->fb && (set->num_connectors != 0));
7938         WARN_ON(set->fb && (set->num_connectors == 0));
7939
7940         count = 0;
7941         list_for_each_entry(connector, &dev->mode_config.connector_list,
7942                             base.head) {
7943                 /* Otherwise traverse passed in connector list and get encoders
7944                  * for them. */
7945                 for (ro = 0; ro < set->num_connectors; ro++) {
7946                         if (set->connectors[ro] == &connector->base) {
7947                                 connector->new_encoder = connector->encoder;
7948                                 break;
7949                         }
7950                 }
7951
7952                 /* If we disable the crtc, disable all its connectors. Also, if
7953                  * the connector is on the changing crtc but not on the new
7954                  * connector list, disable it. */
7955                 if ((!set->fb || ro == set->num_connectors) &&
7956                     connector->base.encoder &&
7957                     connector->base.encoder->crtc == set->crtc) {
7958                         connector->new_encoder = NULL;
7959
7960                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7961                                 connector->base.base.id,
7962                                 drm_get_connector_name(&connector->base));
7963                 }
7964
7965
7966                 if (&connector->new_encoder->base != connector->base.encoder) {
7967                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7968                         config->mode_changed = true;
7969                 }
7970
7971                 /* Disable all disconnected encoders. */
7972                 if (connector->base.status == connector_status_disconnected)
7973                         connector->new_encoder = NULL;
7974         }
7975         /* connector->new_encoder is now updated for all connectors. */
7976
7977         /* Update crtc of enabled connectors. */
7978         count = 0;
7979         list_for_each_entry(connector, &dev->mode_config.connector_list,
7980                             base.head) {
7981                 if (!connector->new_encoder)
7982                         continue;
7983
7984                 new_crtc = connector->new_encoder->base.crtc;
7985
7986                 for (ro = 0; ro < set->num_connectors; ro++) {
7987                         if (set->connectors[ro] == &connector->base)
7988                                 new_crtc = set->crtc;
7989                 }
7990
7991                 /* Make sure the new CRTC will work with the encoder */
7992                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7993                                            new_crtc)) {
7994                         return -EINVAL;
7995                 }
7996                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7997
7998                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7999                         connector->base.base.id,
8000                         drm_get_connector_name(&connector->base),
8001                         new_crtc->base.id);
8002         }
8003
8004         /* Check for any encoders that needs to be disabled. */
8005         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8006                             base.head) {
8007                 list_for_each_entry(connector,
8008                                     &dev->mode_config.connector_list,
8009                                     base.head) {
8010                         if (connector->new_encoder == encoder) {
8011                                 WARN_ON(!connector->new_encoder->new_crtc);
8012
8013                                 goto next_encoder;
8014                         }
8015                 }
8016                 encoder->new_crtc = NULL;
8017 next_encoder:
8018                 /* Only now check for crtc changes so we don't miss encoders
8019                  * that will be disabled. */
8020                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8021                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8022                         config->mode_changed = true;
8023                 }
8024         }
8025         /* Now we've also updated encoder->new_crtc for all encoders. */
8026
8027         return 0;
8028 }
8029
8030 static int intel_crtc_set_config(struct drm_mode_set *set)
8031 {
8032         struct drm_device *dev;
8033         struct drm_mode_set save_set;
8034         struct intel_set_config *config;
8035         int ret;
8036
8037         BUG_ON(!set);
8038         BUG_ON(!set->crtc);
8039         BUG_ON(!set->crtc->helper_private);
8040
8041         if (!set->mode)
8042                 set->fb = NULL;
8043
8044         /* The fb helper likes to play gross jokes with ->mode_set_config.
8045          * Unfortunately the crtc helper doesn't do much at all for this case,
8046          * so we have to cope with this madness until the fb helper is fixed up. */
8047         if (set->fb && set->num_connectors == 0)
8048                 return 0;
8049
8050         if (set->fb) {
8051                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8052                                 set->crtc->base.id, set->fb->base.id,
8053                                 (int)set->num_connectors, set->x, set->y);
8054         } else {
8055                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8056         }
8057
8058         dev = set->crtc->dev;
8059
8060         ret = -ENOMEM;
8061         config = kzalloc(sizeof(*config), GFP_KERNEL);
8062         if (!config)
8063                 goto out_config;
8064
8065         ret = intel_set_config_save_state(dev, config);
8066         if (ret)
8067                 goto out_config;
8068
8069         save_set.crtc = set->crtc;
8070         save_set.mode = &set->crtc->mode;
8071         save_set.x = set->crtc->x;
8072         save_set.y = set->crtc->y;
8073         save_set.fb = set->crtc->fb;
8074
8075         /* Compute whether we need a full modeset, only an fb base update or no
8076          * change at all. In the future we might also check whether only the
8077          * mode changed, e.g. for LVDS where we only change the panel fitter in
8078          * such cases. */
8079         intel_set_config_compute_mode_changes(set, config);
8080
8081         ret = intel_modeset_stage_output_state(dev, set, config);
8082         if (ret)
8083                 goto fail;
8084
8085         if (config->mode_changed) {
8086                 if (set->mode) {
8087                         DRM_DEBUG_KMS("attempting to set mode from"
8088                                         " userspace\n");
8089                         drm_mode_debug_printmodeline(set->mode);
8090                 }
8091
8092                 if (!intel_set_mode(set->crtc, set->mode,
8093                                     set->x, set->y, set->fb)) {
8094                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8095                                   set->crtc->base.id);
8096                         ret = -EINVAL;
8097                         goto fail;
8098                 }
8099         } else if (config->fb_changed) {
8100                 ret = intel_pipe_set_base(set->crtc,
8101                                           set->x, set->y, set->fb);
8102         }
8103
8104         intel_set_config_free(config);
8105
8106         return 0;
8107
8108 fail:
8109         intel_set_config_restore_state(dev, config);
8110
8111         /* Try to restore the config */
8112         if (config->mode_changed &&
8113             !intel_set_mode(save_set.crtc, save_set.mode,
8114                             save_set.x, save_set.y, save_set.fb))
8115                 DRM_ERROR("failed to restore config after modeset failure\n");
8116
8117 out_config:
8118         intel_set_config_free(config);
8119         return ret;
8120 }
8121
8122 static const struct drm_crtc_funcs intel_crtc_funcs = {
8123         .cursor_set = intel_crtc_cursor_set,
8124         .cursor_move = intel_crtc_cursor_move,
8125         .gamma_set = intel_crtc_gamma_set,
8126         .set_config = intel_crtc_set_config,
8127         .destroy = intel_crtc_destroy,
8128         .page_flip = intel_crtc_page_flip,
8129 };
8130
8131 static void intel_cpu_pll_init(struct drm_device *dev)
8132 {
8133         if (IS_HASWELL(dev))
8134                 intel_ddi_pll_init(dev);
8135 }
8136
8137 static void intel_pch_pll_init(struct drm_device *dev)
8138 {
8139         drm_i915_private_t *dev_priv = dev->dev_private;
8140         int i;
8141
8142         if (dev_priv->num_pch_pll == 0) {
8143                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8144                 return;
8145         }
8146
8147         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8148                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8149                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8150                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8151         }
8152 }
8153
8154 static void intel_crtc_init(struct drm_device *dev, int pipe)
8155 {
8156         drm_i915_private_t *dev_priv = dev->dev_private;
8157         struct intel_crtc *intel_crtc;
8158         int i;
8159
8160         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8161         if (intel_crtc == NULL)
8162                 return;
8163
8164         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8165
8166         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8167         for (i = 0; i < 256; i++) {
8168                 intel_crtc->lut_r[i] = i;
8169                 intel_crtc->lut_g[i] = i;
8170                 intel_crtc->lut_b[i] = i;
8171         }
8172
8173         /* Swap pipes & planes for FBC on pre-965 */
8174         intel_crtc->pipe = pipe;
8175         intel_crtc->plane = pipe;
8176         intel_crtc->cpu_transcoder = pipe;
8177         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8178                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8179                 intel_crtc->plane = !pipe;
8180         }
8181
8182         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8183                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8184         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8185         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8186
8187         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8188
8189         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8190 }
8191
8192 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8193                                 struct drm_file *file)
8194 {
8195         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8196         struct drm_mode_object *drmmode_obj;
8197         struct intel_crtc *crtc;
8198
8199         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8200                 return -ENODEV;
8201
8202         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8203                         DRM_MODE_OBJECT_CRTC);
8204
8205         if (!drmmode_obj) {
8206                 DRM_ERROR("no such CRTC id\n");
8207                 return -EINVAL;
8208         }
8209
8210         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8211         pipe_from_crtc_id->pipe = crtc->pipe;
8212
8213         return 0;
8214 }
8215
8216 static int intel_encoder_clones(struct intel_encoder *encoder)
8217 {
8218         struct drm_device *dev = encoder->base.dev;
8219         struct intel_encoder *source_encoder;
8220         int index_mask = 0;
8221         int entry = 0;
8222
8223         list_for_each_entry(source_encoder,
8224                             &dev->mode_config.encoder_list, base.head) {
8225
8226                 if (encoder == source_encoder)
8227                         index_mask |= (1 << entry);
8228
8229                 /* Intel hw has only one MUX where enocoders could be cloned. */
8230                 if (encoder->cloneable && source_encoder->cloneable)
8231                         index_mask |= (1 << entry);
8232
8233                 entry++;
8234         }
8235
8236         return index_mask;
8237 }
8238
8239 static bool has_edp_a(struct drm_device *dev)
8240 {
8241         struct drm_i915_private *dev_priv = dev->dev_private;
8242
8243         if (!IS_MOBILE(dev))
8244                 return false;
8245
8246         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8247                 return false;
8248
8249         if (IS_GEN5(dev) &&
8250             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8251                 return false;
8252
8253         return true;
8254 }
8255
8256 static void intel_setup_outputs(struct drm_device *dev)
8257 {
8258         struct drm_i915_private *dev_priv = dev->dev_private;
8259         struct intel_encoder *encoder;
8260         bool dpd_is_edp = false;
8261         bool has_lvds;
8262
8263         has_lvds = intel_lvds_init(dev);
8264         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8265                 /* disable the panel fitter on everything but LVDS */
8266                 I915_WRITE(PFIT_CONTROL, 0);
8267         }
8268
8269         if (HAS_PCH_SPLIT(dev)) {
8270                 dpd_is_edp = intel_dpd_is_edp(dev);
8271
8272                 if (has_edp_a(dev))
8273                         intel_dp_init(dev, DP_A, PORT_A);
8274
8275                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8276                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8277         }
8278
8279         intel_crt_init(dev);
8280
8281         if (IS_HASWELL(dev)) {
8282                 int found;
8283
8284                 /* Haswell uses DDI functions to detect digital outputs */
8285                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8286                 /* DDI A only supports eDP */
8287                 if (found)
8288                         intel_ddi_init(dev, PORT_A);
8289
8290                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8291                  * register */
8292                 found = I915_READ(SFUSE_STRAP);
8293
8294                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8295                         intel_ddi_init(dev, PORT_B);
8296                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8297                         intel_ddi_init(dev, PORT_C);
8298                 if (found & SFUSE_STRAP_DDID_DETECTED)
8299                         intel_ddi_init(dev, PORT_D);
8300         } else if (HAS_PCH_SPLIT(dev)) {
8301                 int found;
8302
8303                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8304                         /* PCH SDVOB multiplex with HDMIB */
8305                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8306                         if (!found)
8307                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8308                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8309                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8310                 }
8311
8312                 if (I915_READ(HDMIC) & PORT_DETECTED)
8313                         intel_hdmi_init(dev, HDMIC, PORT_C);
8314
8315                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8316                         intel_hdmi_init(dev, HDMID, PORT_D);
8317
8318                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8319                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8320
8321                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8322                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8323         } else if (IS_VALLEYVIEW(dev)) {
8324                 int found;
8325
8326                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8327                 if (I915_READ(DP_C) & DP_DETECTED)
8328                         intel_dp_init(dev, DP_C, PORT_C);
8329
8330                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8331                         /* SDVOB multiplex with HDMIB */
8332                         found = intel_sdvo_init(dev, SDVOB, true);
8333                         if (!found)
8334                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8335                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8336                                 intel_dp_init(dev, DP_B, PORT_B);
8337                 }
8338
8339                 if (I915_READ(SDVOC) & PORT_DETECTED)
8340                         intel_hdmi_init(dev, SDVOC, PORT_C);
8341
8342         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8343                 bool found = false;
8344
8345                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8346                         DRM_DEBUG_KMS("probing SDVOB\n");
8347                         found = intel_sdvo_init(dev, SDVOB, true);
8348                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8349                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8350                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8351                         }
8352
8353                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8354                                 DRM_DEBUG_KMS("probing DP_B\n");
8355                                 intel_dp_init(dev, DP_B, PORT_B);
8356                         }
8357                 }
8358
8359                 /* Before G4X SDVOC doesn't have its own detect register */
8360
8361                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8362                         DRM_DEBUG_KMS("probing SDVOC\n");
8363                         found = intel_sdvo_init(dev, SDVOC, false);
8364                 }
8365
8366                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8367
8368                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8369                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8370                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8371                         }
8372                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8373                                 DRM_DEBUG_KMS("probing DP_C\n");
8374                                 intel_dp_init(dev, DP_C, PORT_C);
8375                         }
8376                 }
8377
8378                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8379                     (I915_READ(DP_D) & DP_DETECTED)) {
8380                         DRM_DEBUG_KMS("probing DP_D\n");
8381                         intel_dp_init(dev, DP_D, PORT_D);
8382                 }
8383         } else if (IS_GEN2(dev))
8384                 intel_dvo_init(dev);
8385
8386         if (SUPPORTS_TV(dev))
8387                 intel_tv_init(dev);
8388
8389         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8390                 encoder->base.possible_crtcs = encoder->crtc_mask;
8391                 encoder->base.possible_clones =
8392                         intel_encoder_clones(encoder);
8393         }
8394
8395         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8396                 ironlake_init_pch_refclk(dev);
8397 }
8398
8399 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8400 {
8401         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8402
8403         drm_framebuffer_cleanup(fb);
8404         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8405
8406         kfree(intel_fb);
8407 }
8408
8409 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8410                                                 struct drm_file *file,
8411                                                 unsigned int *handle)
8412 {
8413         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8414         struct drm_i915_gem_object *obj = intel_fb->obj;
8415
8416         return drm_gem_handle_create(file, &obj->base, handle);
8417 }
8418
8419 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8420         .destroy = intel_user_framebuffer_destroy,
8421         .create_handle = intel_user_framebuffer_create_handle,
8422 };
8423
8424 int intel_framebuffer_init(struct drm_device *dev,
8425                            struct intel_framebuffer *intel_fb,
8426                            struct drm_mode_fb_cmd2 *mode_cmd,
8427                            struct drm_i915_gem_object *obj)
8428 {
8429         int ret;
8430
8431         if (obj->tiling_mode == I915_TILING_Y)
8432                 return -EINVAL;
8433
8434         if (mode_cmd->pitches[0] & 63)
8435                 return -EINVAL;
8436
8437         /* FIXME <= Gen4 stride limits are bit unclear */
8438         if (mode_cmd->pitches[0] > 32768)
8439                 return -EINVAL;
8440
8441         if (obj->tiling_mode != I915_TILING_NONE &&
8442             mode_cmd->pitches[0] != obj->stride)
8443                 return -EINVAL;
8444
8445         /* Reject formats not supported by any plane early. */
8446         switch (mode_cmd->pixel_format) {
8447         case DRM_FORMAT_C8:
8448         case DRM_FORMAT_RGB565:
8449         case DRM_FORMAT_XRGB8888:
8450         case DRM_FORMAT_ARGB8888:
8451                 break;
8452         case DRM_FORMAT_XRGB1555:
8453         case DRM_FORMAT_ARGB1555:
8454                 if (INTEL_INFO(dev)->gen > 3)
8455                         return -EINVAL;
8456                 break;
8457         case DRM_FORMAT_XBGR8888:
8458         case DRM_FORMAT_ABGR8888:
8459         case DRM_FORMAT_XRGB2101010:
8460         case DRM_FORMAT_ARGB2101010:
8461         case DRM_FORMAT_XBGR2101010:
8462         case DRM_FORMAT_ABGR2101010:
8463                 if (INTEL_INFO(dev)->gen < 4)
8464                         return -EINVAL;
8465                 break;
8466         case DRM_FORMAT_YUYV:
8467         case DRM_FORMAT_UYVY:
8468         case DRM_FORMAT_YVYU:
8469         case DRM_FORMAT_VYUY:
8470                 if (INTEL_INFO(dev)->gen < 6)
8471                         return -EINVAL;
8472                 break;
8473         default:
8474                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8475                 return -EINVAL;
8476         }
8477
8478         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8479         if (mode_cmd->offsets[0] != 0)
8480                 return -EINVAL;
8481
8482         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8483         if (ret) {
8484                 DRM_ERROR("framebuffer init failed %d\n", ret);
8485                 return ret;
8486         }
8487
8488         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8489         intel_fb->obj = obj;
8490         return 0;
8491 }
8492
8493 static struct drm_framebuffer *
8494 intel_user_framebuffer_create(struct drm_device *dev,
8495                               struct drm_file *filp,
8496                               struct drm_mode_fb_cmd2 *mode_cmd)
8497 {
8498         struct drm_i915_gem_object *obj;
8499
8500         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8501                                                 mode_cmd->handles[0]));
8502         if (&obj->base == NULL)
8503                 return ERR_PTR(-ENOENT);
8504
8505         return intel_framebuffer_create(dev, mode_cmd, obj);
8506 }
8507
8508 static const struct drm_mode_config_funcs intel_mode_funcs = {
8509         .fb_create = intel_user_framebuffer_create,
8510         .output_poll_changed = intel_fb_output_poll_changed,
8511 };
8512
8513 /* Set up chip specific display functions */
8514 static void intel_init_display(struct drm_device *dev)
8515 {
8516         struct drm_i915_private *dev_priv = dev->dev_private;
8517
8518         /* We always want a DPMS function */
8519         if (IS_HASWELL(dev)) {
8520                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8521                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8522                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8523                 dev_priv->display.off = haswell_crtc_off;
8524                 dev_priv->display.update_plane = ironlake_update_plane;
8525         } else if (HAS_PCH_SPLIT(dev)) {
8526                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8527                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8528                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8529                 dev_priv->display.off = ironlake_crtc_off;
8530                 dev_priv->display.update_plane = ironlake_update_plane;
8531         } else {
8532                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8533                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8534                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8535                 dev_priv->display.off = i9xx_crtc_off;
8536                 dev_priv->display.update_plane = i9xx_update_plane;
8537         }
8538
8539         /* Returns the core display clock speed */
8540         if (IS_VALLEYVIEW(dev))
8541                 dev_priv->display.get_display_clock_speed =
8542                         valleyview_get_display_clock_speed;
8543         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8544                 dev_priv->display.get_display_clock_speed =
8545                         i945_get_display_clock_speed;
8546         else if (IS_I915G(dev))
8547                 dev_priv->display.get_display_clock_speed =
8548                         i915_get_display_clock_speed;
8549         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8550                 dev_priv->display.get_display_clock_speed =
8551                         i9xx_misc_get_display_clock_speed;
8552         else if (IS_I915GM(dev))
8553                 dev_priv->display.get_display_clock_speed =
8554                         i915gm_get_display_clock_speed;
8555         else if (IS_I865G(dev))
8556                 dev_priv->display.get_display_clock_speed =
8557                         i865_get_display_clock_speed;
8558         else if (IS_I85X(dev))
8559                 dev_priv->display.get_display_clock_speed =
8560                         i855_get_display_clock_speed;
8561         else /* 852, 830 */
8562                 dev_priv->display.get_display_clock_speed =
8563                         i830_get_display_clock_speed;
8564
8565         if (HAS_PCH_SPLIT(dev)) {
8566                 if (IS_GEN5(dev)) {
8567                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8568                         dev_priv->display.write_eld = ironlake_write_eld;
8569                 } else if (IS_GEN6(dev)) {
8570                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8571                         dev_priv->display.write_eld = ironlake_write_eld;
8572                 } else if (IS_IVYBRIDGE(dev)) {
8573                         /* FIXME: detect B0+ stepping and use auto training */
8574                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8575                         dev_priv->display.write_eld = ironlake_write_eld;
8576                         dev_priv->display.modeset_global_resources =
8577                                 ivb_modeset_global_resources;
8578                 } else if (IS_HASWELL(dev)) {
8579                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8580                         dev_priv->display.write_eld = haswell_write_eld;
8581                 } else
8582                         dev_priv->display.update_wm = NULL;
8583         } else if (IS_G4X(dev)) {
8584                 dev_priv->display.write_eld = g4x_write_eld;
8585         }
8586
8587         /* Default just returns -ENODEV to indicate unsupported */
8588         dev_priv->display.queue_flip = intel_default_queue_flip;
8589
8590         switch (INTEL_INFO(dev)->gen) {
8591         case 2:
8592                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8593                 break;
8594
8595         case 3:
8596                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8597                 break;
8598
8599         case 4:
8600         case 5:
8601                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8602                 break;
8603
8604         case 6:
8605                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8606                 break;
8607         case 7:
8608                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8609                 break;
8610         }
8611 }
8612
8613 /*
8614  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8615  * resume, or other times.  This quirk makes sure that's the case for
8616  * affected systems.
8617  */
8618 static void quirk_pipea_force(struct drm_device *dev)
8619 {
8620         struct drm_i915_private *dev_priv = dev->dev_private;
8621
8622         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8623         DRM_INFO("applying pipe a force quirk\n");
8624 }
8625
8626 /*
8627  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8628  */
8629 static void quirk_ssc_force_disable(struct drm_device *dev)
8630 {
8631         struct drm_i915_private *dev_priv = dev->dev_private;
8632         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8633         DRM_INFO("applying lvds SSC disable quirk\n");
8634 }
8635
8636 /*
8637  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8638  * brightness value
8639  */
8640 static void quirk_invert_brightness(struct drm_device *dev)
8641 {
8642         struct drm_i915_private *dev_priv = dev->dev_private;
8643         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8644         DRM_INFO("applying inverted panel brightness quirk\n");
8645 }
8646
8647 struct intel_quirk {
8648         int device;
8649         int subsystem_vendor;
8650         int subsystem_device;
8651         void (*hook)(struct drm_device *dev);
8652 };
8653
8654 static struct intel_quirk intel_quirks[] = {
8655         /* HP Mini needs pipe A force quirk (LP: #322104) */
8656         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8657
8658         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8659         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8660
8661         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8662         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8663
8664         /* 830/845 need to leave pipe A & dpll A up */
8665         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8666         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8667
8668         /* Lenovo U160 cannot use SSC on LVDS */
8669         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8670
8671         /* Sony Vaio Y cannot use SSC on LVDS */
8672         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8673
8674         /* Acer Aspire 5734Z must invert backlight brightness */
8675         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8676 };
8677
8678 static void intel_init_quirks(struct drm_device *dev)
8679 {
8680         struct pci_dev *d = dev->pdev;
8681         int i;
8682
8683         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8684                 struct intel_quirk *q = &intel_quirks[i];
8685
8686                 if (d->device == q->device &&
8687                     (d->subsystem_vendor == q->subsystem_vendor ||
8688                      q->subsystem_vendor == PCI_ANY_ID) &&
8689                     (d->subsystem_device == q->subsystem_device ||
8690                      q->subsystem_device == PCI_ANY_ID))
8691                         q->hook(dev);
8692         }
8693 }
8694
8695 /* Disable the VGA plane that we never use */
8696 static void i915_disable_vga(struct drm_device *dev)
8697 {
8698         struct drm_i915_private *dev_priv = dev->dev_private;
8699         u8 sr1;
8700         u32 vga_reg;
8701
8702         if (HAS_PCH_SPLIT(dev))
8703                 vga_reg = CPU_VGACNTRL;
8704         else
8705                 vga_reg = VGACNTRL;
8706
8707         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8708         outb(SR01, VGA_SR_INDEX);
8709         sr1 = inb(VGA_SR_DATA);
8710         outb(sr1 | 1<<5, VGA_SR_DATA);
8711         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8712         udelay(300);
8713
8714         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8715         POSTING_READ(vga_reg);
8716 }
8717
8718 void intel_modeset_init_hw(struct drm_device *dev)
8719 {
8720         /* We attempt to init the necessary power wells early in the initialization
8721          * time, so the subsystems that expect power to be enabled can work.
8722          */
8723         intel_init_power_wells(dev);
8724
8725         intel_prepare_ddi(dev);
8726
8727         intel_init_clock_gating(dev);
8728
8729         mutex_lock(&dev->struct_mutex);
8730         intel_enable_gt_powersave(dev);
8731         mutex_unlock(&dev->struct_mutex);
8732 }
8733
8734 void intel_modeset_init(struct drm_device *dev)
8735 {
8736         struct drm_i915_private *dev_priv = dev->dev_private;
8737         int i, ret;
8738
8739         drm_mode_config_init(dev);
8740
8741         dev->mode_config.min_width = 0;
8742         dev->mode_config.min_height = 0;
8743
8744         dev->mode_config.preferred_depth = 24;
8745         dev->mode_config.prefer_shadow = 1;
8746
8747         dev->mode_config.funcs = &intel_mode_funcs;
8748
8749         intel_init_quirks(dev);
8750
8751         intel_init_pm(dev);
8752
8753         intel_init_display(dev);
8754
8755         if (IS_GEN2(dev)) {
8756                 dev->mode_config.max_width = 2048;
8757                 dev->mode_config.max_height = 2048;
8758         } else if (IS_GEN3(dev)) {
8759                 dev->mode_config.max_width = 4096;
8760                 dev->mode_config.max_height = 4096;
8761         } else {
8762                 dev->mode_config.max_width = 8192;
8763                 dev->mode_config.max_height = 8192;
8764         }
8765         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8766
8767         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8768                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8769
8770         for (i = 0; i < dev_priv->num_pipe; i++) {
8771                 intel_crtc_init(dev, i);
8772                 ret = intel_plane_init(dev, i);
8773                 if (ret)
8774                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8775         }
8776
8777         intel_cpu_pll_init(dev);
8778         intel_pch_pll_init(dev);
8779
8780         /* Just disable it once at startup */
8781         i915_disable_vga(dev);
8782         intel_setup_outputs(dev);
8783 }
8784
8785 static void
8786 intel_connector_break_all_links(struct intel_connector *connector)
8787 {
8788         connector->base.dpms = DRM_MODE_DPMS_OFF;
8789         connector->base.encoder = NULL;
8790         connector->encoder->connectors_active = false;
8791         connector->encoder->base.crtc = NULL;
8792 }
8793
8794 static void intel_enable_pipe_a(struct drm_device *dev)
8795 {
8796         struct intel_connector *connector;
8797         struct drm_connector *crt = NULL;
8798         struct intel_load_detect_pipe load_detect_temp;
8799
8800         /* We can't just switch on the pipe A, we need to set things up with a
8801          * proper mode and output configuration. As a gross hack, enable pipe A
8802          * by enabling the load detect pipe once. */
8803         list_for_each_entry(connector,
8804                             &dev->mode_config.connector_list,
8805                             base.head) {
8806                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8807                         crt = &connector->base;
8808                         break;
8809                 }
8810         }
8811
8812         if (!crt)
8813                 return;
8814
8815         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8816                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8817
8818
8819 }
8820
8821 static bool
8822 intel_check_plane_mapping(struct intel_crtc *crtc)
8823 {
8824         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8825         u32 reg, val;
8826
8827         if (dev_priv->num_pipe == 1)
8828                 return true;
8829
8830         reg = DSPCNTR(!crtc->plane);
8831         val = I915_READ(reg);
8832
8833         if ((val & DISPLAY_PLANE_ENABLE) &&
8834             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8835                 return false;
8836
8837         return true;
8838 }
8839
8840 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8841 {
8842         struct drm_device *dev = crtc->base.dev;
8843         struct drm_i915_private *dev_priv = dev->dev_private;
8844         u32 reg;
8845
8846         /* Clear any frame start delays used for debugging left by the BIOS */
8847         reg = PIPECONF(crtc->cpu_transcoder);
8848         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8849
8850         /* We need to sanitize the plane -> pipe mapping first because this will
8851          * disable the crtc (and hence change the state) if it is wrong. Note
8852          * that gen4+ has a fixed plane -> pipe mapping.  */
8853         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8854                 struct intel_connector *connector;
8855                 bool plane;
8856
8857                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8858                               crtc->base.base.id);
8859
8860                 /* Pipe has the wrong plane attached and the plane is active.
8861                  * Temporarily change the plane mapping and disable everything
8862                  * ...  */
8863                 plane = crtc->plane;
8864                 crtc->plane = !plane;
8865                 dev_priv->display.crtc_disable(&crtc->base);
8866                 crtc->plane = plane;
8867
8868                 /* ... and break all links. */
8869                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8870                                     base.head) {
8871                         if (connector->encoder->base.crtc != &crtc->base)
8872                                 continue;
8873
8874                         intel_connector_break_all_links(connector);
8875                 }
8876
8877                 WARN_ON(crtc->active);
8878                 crtc->base.enabled = false;
8879         }
8880
8881         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8882             crtc->pipe == PIPE_A && !crtc->active) {
8883                 /* BIOS forgot to enable pipe A, this mostly happens after
8884                  * resume. Force-enable the pipe to fix this, the update_dpms
8885                  * call below we restore the pipe to the right state, but leave
8886                  * the required bits on. */
8887                 intel_enable_pipe_a(dev);
8888         }
8889
8890         /* Adjust the state of the output pipe according to whether we
8891          * have active connectors/encoders. */
8892         intel_crtc_update_dpms(&crtc->base);
8893
8894         if (crtc->active != crtc->base.enabled) {
8895                 struct intel_encoder *encoder;
8896
8897                 /* This can happen either due to bugs in the get_hw_state
8898                  * functions or because the pipe is force-enabled due to the
8899                  * pipe A quirk. */
8900                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8901                               crtc->base.base.id,
8902                               crtc->base.enabled ? "enabled" : "disabled",
8903                               crtc->active ? "enabled" : "disabled");
8904
8905                 crtc->base.enabled = crtc->active;
8906
8907                 /* Because we only establish the connector -> encoder ->
8908                  * crtc links if something is active, this means the
8909                  * crtc is now deactivated. Break the links. connector
8910                  * -> encoder links are only establish when things are
8911                  *  actually up, hence no need to break them. */
8912                 WARN_ON(crtc->active);
8913
8914                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8915                         WARN_ON(encoder->connectors_active);
8916                         encoder->base.crtc = NULL;
8917                 }
8918         }
8919 }
8920
8921 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8922 {
8923         struct intel_connector *connector;
8924         struct drm_device *dev = encoder->base.dev;
8925
8926         /* We need to check both for a crtc link (meaning that the
8927          * encoder is active and trying to read from a pipe) and the
8928          * pipe itself being active. */
8929         bool has_active_crtc = encoder->base.crtc &&
8930                 to_intel_crtc(encoder->base.crtc)->active;
8931
8932         if (encoder->connectors_active && !has_active_crtc) {
8933                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8934                               encoder->base.base.id,
8935                               drm_get_encoder_name(&encoder->base));
8936
8937                 /* Connector is active, but has no active pipe. This is
8938                  * fallout from our resume register restoring. Disable
8939                  * the encoder manually again. */
8940                 if (encoder->base.crtc) {
8941                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8942                                       encoder->base.base.id,
8943                                       drm_get_encoder_name(&encoder->base));
8944                         encoder->disable(encoder);
8945                 }
8946
8947                 /* Inconsistent output/port/pipe state happens presumably due to
8948                  * a bug in one of the get_hw_state functions. Or someplace else
8949                  * in our code, like the register restore mess on resume. Clamp
8950                  * things to off as a safer default. */
8951                 list_for_each_entry(connector,
8952                                     &dev->mode_config.connector_list,
8953                                     base.head) {
8954                         if (connector->encoder != encoder)
8955                                 continue;
8956
8957                         intel_connector_break_all_links(connector);
8958                 }
8959         }
8960         /* Enabled encoders without active connectors will be fixed in
8961          * the crtc fixup. */
8962 }
8963
8964 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8965  * and i915 state tracking structures. */
8966 void intel_modeset_setup_hw_state(struct drm_device *dev)
8967 {
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         enum pipe pipe;
8970         u32 tmp;
8971         struct intel_crtc *crtc;
8972         struct intel_encoder *encoder;
8973         struct intel_connector *connector;
8974
8975         if (IS_HASWELL(dev)) {
8976                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8977
8978                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8979                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8980                         case TRANS_DDI_EDP_INPUT_A_ON:
8981                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8982                                 pipe = PIPE_A;
8983                                 break;
8984                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8985                                 pipe = PIPE_B;
8986                                 break;
8987                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8988                                 pipe = PIPE_C;
8989                                 break;
8990                         }
8991
8992                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8993                         crtc->cpu_transcoder = TRANSCODER_EDP;
8994
8995                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8996                                       pipe_name(pipe));
8997                 }
8998         }
8999
9000         for_each_pipe(pipe) {
9001                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9002
9003                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9004                 if (tmp & PIPECONF_ENABLE)
9005                         crtc->active = true;
9006                 else
9007                         crtc->active = false;
9008
9009                 crtc->base.enabled = crtc->active;
9010
9011                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9012                               crtc->base.base.id,
9013                               crtc->active ? "enabled" : "disabled");
9014         }
9015
9016         if (IS_HASWELL(dev))
9017                 intel_ddi_setup_hw_pll_state(dev);
9018
9019         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9020                             base.head) {
9021                 pipe = 0;
9022
9023                 if (encoder->get_hw_state(encoder, &pipe)) {
9024                         encoder->base.crtc =
9025                                 dev_priv->pipe_to_crtc_mapping[pipe];
9026                 } else {
9027                         encoder->base.crtc = NULL;
9028                 }
9029
9030                 encoder->connectors_active = false;
9031                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9032                               encoder->base.base.id,
9033                               drm_get_encoder_name(&encoder->base),
9034                               encoder->base.crtc ? "enabled" : "disabled",
9035                               pipe);
9036         }
9037
9038         list_for_each_entry(connector, &dev->mode_config.connector_list,
9039                             base.head) {
9040                 if (connector->get_hw_state(connector)) {
9041                         connector->base.dpms = DRM_MODE_DPMS_ON;
9042                         connector->encoder->connectors_active = true;
9043                         connector->base.encoder = &connector->encoder->base;
9044                 } else {
9045                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9046                         connector->base.encoder = NULL;
9047                 }
9048                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9049                               connector->base.base.id,
9050                               drm_get_connector_name(&connector->base),
9051                               connector->base.encoder ? "enabled" : "disabled");
9052         }
9053
9054         /* HW state is read out, now we need to sanitize this mess. */
9055         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056                             base.head) {
9057                 intel_sanitize_encoder(encoder);
9058         }
9059
9060         for_each_pipe(pipe) {
9061                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9062                 intel_sanitize_crtc(crtc);
9063         }
9064
9065         intel_modeset_update_staged_output_state(dev);
9066
9067         intel_modeset_check_state(dev);
9068
9069         drm_mode_config_reset(dev);
9070 }
9071
9072 void intel_modeset_gem_init(struct drm_device *dev)
9073 {
9074         intel_modeset_init_hw(dev);
9075
9076         intel_setup_overlay(dev);
9077
9078         intel_modeset_setup_hw_state(dev);
9079 }
9080
9081 void intel_modeset_cleanup(struct drm_device *dev)
9082 {
9083         struct drm_i915_private *dev_priv = dev->dev_private;
9084         struct drm_crtc *crtc;
9085         struct intel_crtc *intel_crtc;
9086
9087         drm_kms_helper_poll_fini(dev);
9088         mutex_lock(&dev->struct_mutex);
9089
9090         intel_unregister_dsm_handler();
9091
9092
9093         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9094                 /* Skip inactive CRTCs */
9095                 if (!crtc->fb)
9096                         continue;
9097
9098                 intel_crtc = to_intel_crtc(crtc);
9099                 intel_increase_pllclock(crtc);
9100         }
9101
9102         intel_disable_fbc(dev);
9103
9104         intel_disable_gt_powersave(dev);
9105
9106         ironlake_teardown_rc6(dev);
9107
9108         if (IS_VALLEYVIEW(dev))
9109                 vlv_init_dpio(dev);
9110
9111         mutex_unlock(&dev->struct_mutex);
9112
9113         /* Disable the irq before mode object teardown, for the irq might
9114          * enqueue unpin/hotplug work. */
9115         drm_irq_uninstall(dev);
9116         cancel_work_sync(&dev_priv->hotplug_work);
9117         cancel_work_sync(&dev_priv->rps.work);
9118
9119         /* flush any delayed tasks or pending work */
9120         flush_scheduled_work();
9121
9122         drm_mode_config_cleanup(dev);
9123 }
9124
9125 /*
9126  * Return which encoder is currently attached for connector.
9127  */
9128 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9129 {
9130         return &intel_attached_encoder(connector)->base;
9131 }
9132
9133 void intel_connector_attach_encoder(struct intel_connector *connector,
9134                                     struct intel_encoder *encoder)
9135 {
9136         connector->encoder = encoder;
9137         drm_mode_connector_attach_encoder(&connector->base,
9138                                           &encoder->base);
9139 }
9140
9141 /*
9142  * set vga decode state - true == enable VGA decode
9143  */
9144 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9145 {
9146         struct drm_i915_private *dev_priv = dev->dev_private;
9147         u16 gmch_ctrl;
9148
9149         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9150         if (state)
9151                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9152         else
9153                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9154         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9155         return 0;
9156 }
9157
9158 #ifdef CONFIG_DEBUG_FS
9159 #include <linux/seq_file.h>
9160
9161 struct intel_display_error_state {
9162         struct intel_cursor_error_state {
9163                 u32 control;
9164                 u32 position;
9165                 u32 base;
9166                 u32 size;
9167         } cursor[I915_MAX_PIPES];
9168
9169         struct intel_pipe_error_state {
9170                 u32 conf;
9171                 u32 source;
9172
9173                 u32 htotal;
9174                 u32 hblank;
9175                 u32 hsync;
9176                 u32 vtotal;
9177                 u32 vblank;
9178                 u32 vsync;
9179         } pipe[I915_MAX_PIPES];
9180
9181         struct intel_plane_error_state {
9182                 u32 control;
9183                 u32 stride;
9184                 u32 size;
9185                 u32 pos;
9186                 u32 addr;
9187                 u32 surface;
9188                 u32 tile_offset;
9189         } plane[I915_MAX_PIPES];
9190 };
9191
9192 struct intel_display_error_state *
9193 intel_display_capture_error_state(struct drm_device *dev)
9194 {
9195         drm_i915_private_t *dev_priv = dev->dev_private;
9196         struct intel_display_error_state *error;
9197         enum transcoder cpu_transcoder;
9198         int i;
9199
9200         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9201         if (error == NULL)
9202                 return NULL;
9203
9204         for_each_pipe(i) {
9205                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9206
9207                 error->cursor[i].control = I915_READ(CURCNTR(i));
9208                 error->cursor[i].position = I915_READ(CURPOS(i));
9209                 error->cursor[i].base = I915_READ(CURBASE(i));
9210
9211                 error->plane[i].control = I915_READ(DSPCNTR(i));
9212                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9213                 error->plane[i].size = I915_READ(DSPSIZE(i));
9214                 error->plane[i].pos = I915_READ(DSPPOS(i));
9215                 error->plane[i].addr = I915_READ(DSPADDR(i));
9216                 if (INTEL_INFO(dev)->gen >= 4) {
9217                         error->plane[i].surface = I915_READ(DSPSURF(i));
9218                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9219                 }
9220
9221                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9222                 error->pipe[i].source = I915_READ(PIPESRC(i));
9223                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9224                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9225                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9226                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9227                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9228                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9229         }
9230
9231         return error;
9232 }
9233
9234 void
9235 intel_display_print_error_state(struct seq_file *m,
9236                                 struct drm_device *dev,
9237                                 struct intel_display_error_state *error)
9238 {
9239         drm_i915_private_t *dev_priv = dev->dev_private;
9240         int i;
9241
9242         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9243         for_each_pipe(i) {
9244                 seq_printf(m, "Pipe [%d]:\n", i);
9245                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9246                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9247                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9248                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9249                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9250                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9251                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9252                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9253
9254                 seq_printf(m, "Plane [%d]:\n", i);
9255                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9256                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9257                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9258                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9259                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9260                 if (INTEL_INFO(dev)->gen >= 4) {
9261                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9262                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9263                 }
9264
9265                 seq_printf(m, "Cursor [%d]:\n", i);
9266                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9267                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9268                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9269         }
9270 }
9271 #endif