2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device *dev)
84 struct drm_i915_private *dev_priv = dev->dev_private;
86 WARN_ON(!HAS_PCH_SPLIT(dev));
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
194 .find_pll = intel_g4x_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
238 .find_pll = intel_g4x_find_best_PLL,
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
435 val = I915_READ(DPIO_DATA);
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464 static void vlv_init_dpio(struct drm_device *dev)
466 struct drm_i915_private *dev_priv = dev->dev_private;
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 { } /* terminating entry */
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
502 if (dmi_check_system(intel_dual_link_lvds))
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
534 limit = &intel_limits_ironlake_dual_lvds;
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
539 limit = &intel_limits_ironlake_single_lvds;
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
545 limit = &intel_limits_ironlake_dac;
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
601 limit = &intel_limits_i9xx_sdvo;
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
606 limit = &intel_limits_i8xx_dvo;
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
633 * Returns whether any output on the specified pipe is of the specified type
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
704 clock.p2 = limit->p2.p2_slow;
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
709 clock.p2 = limit->p2.p2_fast;
712 memset(best_clock, 0, sizeof(*best_clock));
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
732 clock.p != match_clock->p)
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
745 return (err != target);
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765 if (HAS_PCH_SPLIT(dev))
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
771 clock.p2 = limit->p2.p2_fast;
773 clock.p2 = limit->p2.p2_slow;
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
778 clock.p2 = limit->p2.p2_fast;
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
799 clock.p != match_clock->p)
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
821 struct drm_device *dev = crtc->dev;
824 if (target < 200000) {
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
849 if (target < 200000) {
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
881 dotclk = target * 1000;
884 fastclk = dotclk / (2*100);
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
912 if (absppm < bestppm - 10) {
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
944 return intel_crtc->cpu_transcoder;
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
952 frame = I915_READ(frame_reg);
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
959 * intel_wait_for_vblank - wait for vblank on a given pipe
961 * @pipe: pipe to wait for
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
996 DRM_DEBUG_KMS("vblank wait timed out\n");
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1002 * @pipe: pipe to wait for
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1028 WARN(1, "pipe_off wait timed out\n");
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035 line_mask = DSL_LINEMASK_GEN2;
1037 line_mask = DSL_LINEMASK_GEN3;
1039 /* Wait for the display line to settle */
1041 last_line = I915_READ(reg) & line_mask;
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1050 static const char *state_string(bool enabled)
1052 return enabled ? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1152 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1153 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_ENABLE);
1160 WARN(cur_state != state,
1161 "FDI RX state assertion failure (expected %s, current %s)\n",
1162 state_string(state), state_string(cur_state));
1164 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1165 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1167 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1173 /* ILK FDI PLL is always enabled */
1174 if (dev_priv->info->gen == 5)
1177 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1178 if (IS_HASWELL(dev_priv->dev))
1181 reg = FDI_TX_CTL(pipe);
1182 val = I915_READ(reg);
1183 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1192 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg);
1198 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 int pp_reg, lvds_reg;
1206 enum pipe panel_pipe = PIPE_A;
1209 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1210 pp_reg = PCH_PP_CONTROL;
1211 lvds_reg = PCH_LVDS;
1213 pp_reg = PP_CONTROL;
1217 val = I915_READ(pp_reg);
1218 if (!(val & PANEL_POWER_ON) ||
1219 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1225 WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1230 void assert_pipe(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1236 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 /* if we need the pipe A quirk it must be always on */
1240 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 reg = PIPECONF(cpu_transcoder);
1244 val = I915_READ(reg);
1245 cur_state = !!(val & PIPECONF_ENABLE);
1246 WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1276 /* Planes are fixed to pipes on ILK+ */
1277 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1278 reg = DSPCNTR(pipe);
1279 val = I915_READ(reg);
1280 WARN((val & DISPLAY_PLANE_ENABLE),
1281 "plane %c assertion failure, should be disabled but not\n",
1286 /* Need to check both planes against the pipe */
1287 for (i = 0; i < 2; i++) {
1289 val = I915_READ(reg);
1290 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1291 DISPPLANE_SEL_PIPE_SHIFT;
1292 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1293 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1294 plane_name(i), pipe_name(pipe));
1298 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1332 if ((val & DP_PORT_EN) == 0)
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1350 if ((val & PORT_ENABLE) == 0)
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
1354 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1366 if ((val & LVDS_PORT_EN) == 0)
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, int reg, u32 port_sel)
1397 u32 val = I915_READ(reg);
1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400 reg, pipe_name(pipe));
1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
1404 "IBX PCH dp port still using transcoder B\n");
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1410 u32 val = I915_READ(reg);
1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1416 && (val & SDVO_PIPE_B_SELECT),
1417 "IBX PCH hdmi port still using transcoder B\n");
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431 val = I915_READ(reg);
1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
1437 val = I915_READ(reg);
1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1456 * Note! This is for pre-ILK only.
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1460 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1465 /* No really, not for ILK+ */
1466 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1468 /* PLL is protected by panel, make sure we can write it */
1469 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1470 assert_panel_unlocked(dev_priv, pipe);
1473 val = I915_READ(reg);
1474 val |= DPLL_VCO_ENABLE;
1476 /* We do this three times for luck */
1477 I915_WRITE(reg, val);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, val);
1482 udelay(150); /* wait for warmup */
1483 I915_WRITE(reg, val);
1485 udelay(150); /* wait for warmup */
1489 * intel_disable_pll - disable a PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to disable
1493 * Disable the PLL for @pipe, making sure the pipe is off first.
1495 * Note! This is for pre-ILK only.
1497 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1502 /* Don't disable pipe A or pipe A PLLs if needed */
1503 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 /* Make sure the pipe isn't still relying on us */
1507 assert_pipe_disabled(dev_priv, pipe);
1510 val = I915_READ(reg);
1511 val &= ~DPLL_VCO_ENABLE;
1512 I915_WRITE(reg, val);
1518 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1520 unsigned long flags;
1522 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1523 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1525 DRM_ERROR("timeout waiting for SBI to become ready\n");
1529 I915_WRITE(SBI_ADDR,
1531 I915_WRITE(SBI_DATA,
1533 I915_WRITE(SBI_CTL_STAT,
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1539 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1544 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1548 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1550 unsigned long flags;
1553 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1554 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1556 DRM_ERROR("timeout waiting for SBI to become ready\n");
1560 I915_WRITE(SBI_ADDR,
1562 I915_WRITE(SBI_CTL_STAT,
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1568 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1572 value = I915_READ(SBI_DATA);
1575 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1580 * ironlake_enable_pch_pll - enable PCH PLL
1581 * @dev_priv: i915 private structure
1582 * @pipe: pipe PLL to enable
1584 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1585 * drives the transcoder clock.
1587 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1589 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1590 struct intel_pch_pll *pll;
1594 /* PCH PLLs only available on ILK, SNB and IVB */
1595 BUG_ON(dev_priv->info->gen < 5);
1596 pll = intel_crtc->pch_pll;
1600 if (WARN_ON(pll->refcount == 0))
1603 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1604 pll->pll_reg, pll->active, pll->on,
1605 intel_crtc->base.base.id);
1607 /* PCH refclock must be enabled first */
1608 assert_pch_refclk_enabled(dev_priv);
1610 if (pll->active++ && pll->on) {
1611 assert_pch_pll_enabled(dev_priv, pll, NULL);
1615 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618 val = I915_READ(reg);
1619 val |= DPLL_VCO_ENABLE;
1620 I915_WRITE(reg, val);
1627 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1629 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1630 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1634 /* PCH only available on ILK+ */
1635 BUG_ON(dev_priv->info->gen < 5);
1639 if (WARN_ON(pll->refcount == 0))
1642 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1643 pll->pll_reg, pll->active, pll->on,
1644 intel_crtc->base.base.id);
1646 if (WARN_ON(pll->active == 0)) {
1647 assert_pch_pll_disabled(dev_priv, pll, NULL);
1651 if (--pll->active) {
1652 assert_pch_pll_enabled(dev_priv, pll, NULL);
1656 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1658 /* Make sure transcoder isn't still depending on us */
1659 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662 val = I915_READ(reg);
1663 val &= ~DPLL_VCO_ENABLE;
1664 I915_WRITE(reg, val);
1671 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 struct drm_device *dev = dev_priv->dev;
1675 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1676 uint32_t reg, val, pipeconf_val;
1678 /* PCH only available on ILK+ */
1679 BUG_ON(dev_priv->info->gen < 5);
1681 /* Make sure PCH DPLL is enabled */
1682 assert_pch_pll_enabled(dev_priv,
1683 to_intel_crtc(crtc)->pch_pll,
1684 to_intel_crtc(crtc));
1686 /* FDI must be feeding us bits for PCH ports */
1687 assert_fdi_tx_enabled(dev_priv, pipe);
1688 assert_fdi_rx_enabled(dev_priv, pipe);
1690 if (HAS_PCH_CPT(dev)) {
1691 /* Workaround: Set the timing override bit before enabling the
1692 * pch transcoder. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1699 reg = TRANSCONF(pipe);
1700 val = I915_READ(reg);
1701 pipeconf_val = I915_READ(PIPECONF(pipe));
1703 if (HAS_PCH_IBX(dev_priv->dev)) {
1705 * make the BPC in transcoder be consistent with
1706 * that in pipeconf reg.
1708 val &= ~PIPE_BPC_MASK;
1709 val |= pipeconf_val & PIPE_BPC_MASK;
1712 val &= ~TRANS_INTERLACE_MASK;
1713 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1714 if (HAS_PCH_IBX(dev_priv->dev) &&
1715 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1716 val |= TRANS_LEGACY_INTERLACED_ILK;
1718 val |= TRANS_INTERLACED;
1720 val |= TRANS_PROGRESSIVE;
1722 I915_WRITE(reg, val | TRANS_ENABLE);
1723 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1724 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728 enum transcoder cpu_transcoder)
1730 u32 val, pipeconf_val;
1732 /* PCH only available on ILK+ */
1733 BUG_ON(dev_priv->info->gen < 5);
1735 /* FDI must be feeding us bits for PCH ports */
1736 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1737 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1739 /* Workaround: set timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
1741 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1742 I915_WRITE(_TRANSA_CHICKEN2, val);
1745 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1747 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748 PIPECONF_INTERLACED_ILK)
1749 val |= TRANS_INTERLACED;
1751 val |= TRANS_PROGRESSIVE;
1753 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1754 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1761 struct drm_device *dev = dev_priv->dev;
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1771 reg = TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1777 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1779 if (!HAS_PCH_IBX(dev)) {
1780 /* Workaround: Clear the timing override chicken bit again. */
1781 reg = TRANS_CHICKEN2(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784 I915_WRITE(reg, val);
1788 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1792 val = I915_READ(_TRANSACONF);
1793 val &= ~TRANS_ENABLE;
1794 I915_WRITE(_TRANSACONF, val);
1795 /* wait for PCH transcoder off, transcoder state */
1796 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1797 DRM_ERROR("Failed to disable PCH transcoder\n");
1799 /* Workaround: clear timing override bit. */
1800 val = I915_READ(_TRANSA_CHICKEN2);
1801 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1802 I915_WRITE(_TRANSA_CHICKEN2, val);
1806 * intel_enable_pipe - enable a pipe, asserting requirements
1807 * @dev_priv: i915 private structure
1808 * @pipe: pipe to enable
1809 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1811 * Enable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1814 * @pipe should be %PIPE_A or %PIPE_B.
1816 * Will wait until the pipe is actually running (i.e. first vblank) before
1819 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1822 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1828 * A pipe without a PLL won't actually be able to drive bits from
1829 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1832 if (!HAS_PCH_SPLIT(dev_priv->dev))
1833 assert_pll_enabled(dev_priv, pipe);
1836 /* if driving the PCH, we need FDI enabled */
1837 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1838 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1840 /* FIXME: assert CPU port conditions for SNB+ */
1843 reg = PIPECONF(cpu_transcoder);
1844 val = I915_READ(reg);
1845 if (val & PIPECONF_ENABLE)
1848 I915_WRITE(reg, val | PIPECONF_ENABLE);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1853 * intel_disable_pipe - disable a pipe, asserting requirements
1854 * @dev_priv: i915 private structure
1855 * @pipe: pipe to disable
1857 * Disable @pipe, making sure that various hardware specific requirements
1858 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860 * @pipe should be %PIPE_A or %PIPE_B.
1862 * Will wait until the pipe has shut down before returning.
1864 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1867 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1873 * Make sure planes won't keep trying to pump pixels to us,
1874 * or we might hang the display.
1876 assert_planes_disabled(dev_priv, pipe);
1878 /* Don't disable pipe A or pipe A PLLs if needed */
1879 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1882 reg = PIPECONF(cpu_transcoder);
1883 val = I915_READ(reg);
1884 if ((val & PIPECONF_ENABLE) == 0)
1887 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1888 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1892 * Plane regs are double buffered, going from enabled->disabled needs a
1893 * trigger in order to latch. The display address reg provides this.
1895 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1898 if (dev_priv->info->gen >= 4)
1899 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1905 * intel_enable_plane - enable a display plane on a given pipe
1906 * @dev_priv: i915 private structure
1907 * @plane: plane to enable
1908 * @pipe: pipe being fed
1910 * Enable @plane on @pipe, making sure that @pipe is running first.
1912 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1913 enum plane plane, enum pipe pipe)
1918 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1919 assert_pipe_enabled(dev_priv, pipe);
1921 reg = DSPCNTR(plane);
1922 val = I915_READ(reg);
1923 if (val & DISPLAY_PLANE_ENABLE)
1926 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1927 intel_flush_display_plane(dev_priv, plane);
1928 intel_wait_for_vblank(dev_priv->dev, pipe);
1932 * intel_disable_plane - disable a display plane
1933 * @dev_priv: i915 private structure
1934 * @plane: plane to disable
1935 * @pipe: pipe consuming the data
1937 * Disable @plane; should be an independent operation.
1939 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1940 enum plane plane, enum pipe pipe)
1945 reg = DSPCNTR(plane);
1946 val = I915_READ(reg);
1947 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1950 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1951 intel_flush_display_plane(dev_priv, plane);
1952 intel_wait_for_vblank(dev_priv->dev, pipe);
1956 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1957 struct drm_i915_gem_object *obj,
1958 struct intel_ring_buffer *pipelined)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1964 switch (obj->tiling_mode) {
1965 case I915_TILING_NONE:
1966 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1967 alignment = 128 * 1024;
1968 else if (INTEL_INFO(dev)->gen >= 4)
1969 alignment = 4 * 1024;
1971 alignment = 64 * 1024;
1974 /* pin() will align the object as required by fence */
1978 /* FIXME: Is this true? */
1979 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1985 dev_priv->mm.interruptible = false;
1986 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1988 goto err_interruptible;
1990 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1991 * fence, whereas 965+ only requires a fence if using
1992 * framebuffer compression. For simplicity, we always install
1993 * a fence as the cost is not that onerous.
1995 ret = i915_gem_object_get_fence(obj);
1999 i915_gem_object_pin_fence(obj);
2001 dev_priv->mm.interruptible = true;
2005 i915_gem_object_unpin(obj);
2007 dev_priv->mm.interruptible = true;
2011 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013 i915_gem_object_unpin_fence(obj);
2014 i915_gem_object_unpin(obj);
2017 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2018 * is assumed to be a power-of-two. */
2019 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2023 int tile_rows, tiles;
2027 tiles = *x / (512/bpp);
2030 return tile_rows * pitch * 8 + tiles * 4096;
2033 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2039 struct intel_framebuffer *intel_fb;
2040 struct drm_i915_gem_object *obj;
2041 int plane = intel_crtc->plane;
2042 unsigned long linear_offset;
2051 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2055 intel_fb = to_intel_framebuffer(fb);
2056 obj = intel_fb->obj;
2058 reg = DSPCNTR(plane);
2059 dspcntr = I915_READ(reg);
2060 /* Mask out pixel format bits in case we change it */
2061 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2062 switch (fb->pixel_format) {
2064 dspcntr |= DISPPLANE_8BPP;
2066 case DRM_FORMAT_XRGB1555:
2067 case DRM_FORMAT_ARGB1555:
2068 dspcntr |= DISPPLANE_BGRX555;
2070 case DRM_FORMAT_RGB565:
2071 dspcntr |= DISPPLANE_BGRX565;
2073 case DRM_FORMAT_XRGB8888:
2074 case DRM_FORMAT_ARGB8888:
2075 dspcntr |= DISPPLANE_BGRX888;
2077 case DRM_FORMAT_XBGR8888:
2078 case DRM_FORMAT_ABGR8888:
2079 dspcntr |= DISPPLANE_RGBX888;
2081 case DRM_FORMAT_XRGB2101010:
2082 case DRM_FORMAT_ARGB2101010:
2083 dspcntr |= DISPPLANE_BGRX101010;
2085 case DRM_FORMAT_XBGR2101010:
2086 case DRM_FORMAT_ABGR2101010:
2087 dspcntr |= DISPPLANE_RGBX101010;
2090 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2094 if (INTEL_INFO(dev)->gen >= 4) {
2095 if (obj->tiling_mode != I915_TILING_NONE)
2096 dspcntr |= DISPPLANE_TILED;
2098 dspcntr &= ~DISPPLANE_TILED;
2101 I915_WRITE(reg, dspcntr);
2103 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2105 if (INTEL_INFO(dev)->gen >= 4) {
2106 intel_crtc->dspaddr_offset =
2107 intel_gen4_compute_offset_xtiled(&x, &y,
2108 fb->bits_per_pixel / 8,
2110 linear_offset -= intel_crtc->dspaddr_offset;
2112 intel_crtc->dspaddr_offset = linear_offset;
2115 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2116 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2117 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2118 if (INTEL_INFO(dev)->gen >= 4) {
2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
2120 obj->gtt_offset + intel_crtc->dspaddr_offset);
2121 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2122 I915_WRITE(DSPLINOFF(plane), linear_offset);
2124 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2130 static int ironlake_update_plane(struct drm_crtc *crtc,
2131 struct drm_framebuffer *fb, int x, int y)
2133 struct drm_device *dev = crtc->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136 struct intel_framebuffer *intel_fb;
2137 struct drm_i915_gem_object *obj;
2138 int plane = intel_crtc->plane;
2139 unsigned long linear_offset;
2149 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2153 intel_fb = to_intel_framebuffer(fb);
2154 obj = intel_fb->obj;
2156 reg = DSPCNTR(plane);
2157 dspcntr = I915_READ(reg);
2158 /* Mask out pixel format bits in case we change it */
2159 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2160 switch (fb->pixel_format) {
2162 dspcntr |= DISPPLANE_8BPP;
2164 case DRM_FORMAT_RGB565:
2165 dspcntr |= DISPPLANE_BGRX565;
2167 case DRM_FORMAT_XRGB8888:
2168 case DRM_FORMAT_ARGB8888:
2169 dspcntr |= DISPPLANE_BGRX888;
2171 case DRM_FORMAT_XBGR8888:
2172 case DRM_FORMAT_ABGR8888:
2173 dspcntr |= DISPPLANE_RGBX888;
2175 case DRM_FORMAT_XRGB2101010:
2176 case DRM_FORMAT_ARGB2101010:
2177 dspcntr |= DISPPLANE_BGRX101010;
2179 case DRM_FORMAT_XBGR2101010:
2180 case DRM_FORMAT_ABGR2101010:
2181 dspcntr |= DISPPLANE_RGBX101010;
2184 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2188 if (obj->tiling_mode != I915_TILING_NONE)
2189 dspcntr |= DISPPLANE_TILED;
2191 dspcntr &= ~DISPPLANE_TILED;
2194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196 I915_WRITE(reg, dspcntr);
2198 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2199 intel_crtc->dspaddr_offset =
2200 intel_gen4_compute_offset_xtiled(&x, &y,
2201 fb->bits_per_pixel / 8,
2203 linear_offset -= intel_crtc->dspaddr_offset;
2205 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2206 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208 I915_MODIFY_DISPBASE(DSPSURF(plane),
2209 obj->gtt_offset + intel_crtc->dspaddr_offset);
2210 if (IS_HASWELL(dev)) {
2211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
2231 intel_increase_pllclock(crtc);
2233 return dev_priv->display.update_plane(crtc, fb, x, y);
2237 intel_finish_fb(struct drm_framebuffer *old_fb)
2239 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 bool was_interruptible = dev_priv->mm.interruptible;
2244 wait_event(dev_priv->pending_flip_queue,
2245 atomic_read(&dev_priv->mm.wedged) ||
2246 atomic_read(&obj->pending_flip) == 0);
2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_finish_gpu(obj);
2258 dev_priv->mm.interruptible = was_interruptible;
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 struct drm_device *dev = crtc->dev;
2266 struct drm_i915_master_private *master_priv;
2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 if (!dev->primary->master)
2272 master_priv = dev->primary->master->driver_priv;
2273 if (!master_priv->sarea_priv)
2276 switch (intel_crtc->pipe) {
2278 master_priv->sarea_priv->pipeA_x = x;
2279 master_priv->sarea_priv->pipeA_y = y;
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2291 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2292 struct drm_framebuffer *fb)
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 struct drm_framebuffer *old_fb;
2302 DRM_ERROR("No FB bound\n");
2306 if(intel_crtc->plane > dev_priv->num_pipe) {
2307 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309 dev_priv->num_pipe);
2313 mutex_lock(&dev->struct_mutex);
2314 ret = intel_pin_and_fence_fb_obj(dev,
2315 to_intel_framebuffer(fb)->obj,
2318 mutex_unlock(&dev->struct_mutex);
2319 DRM_ERROR("pin & fence failed\n");
2324 intel_finish_fb(crtc->fb);
2326 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2328 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2329 mutex_unlock(&dev->struct_mutex);
2330 DRM_ERROR("failed to update base address\n");
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2344 intel_update_fbc(dev);
2345 mutex_unlock(&dev->struct_mutex);
2347 intel_crtc_update_sarea_pos(crtc, x, y);
2352 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2359 dpa_ctl = I915_READ(DP_A);
2360 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362 if (clock < 200000) {
2364 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2365 /* workaround for 160Mhz:
2366 1) program 0x4600c bits 15:0 = 0x8124
2367 2) program 0x46010 bit 0 = 1
2368 3) program 0x46034 bit 24 = 1
2369 4) program 0x64000 bit 14 = 1
2371 temp = I915_READ(0x4600c);
2373 I915_WRITE(0x4600c, temp | 0x8124);
2375 temp = I915_READ(0x46010);
2376 I915_WRITE(0x46010, temp | 1);
2378 temp = I915_READ(0x46034);
2379 I915_WRITE(0x46034, temp | (1 << 24));
2381 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383 I915_WRITE(DP_A, dpa_ctl);
2389 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391 struct drm_device *dev = crtc->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 int pipe = intel_crtc->pipe;
2397 /* enable normal train */
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 if (IS_IVYBRIDGE(dev)) {
2401 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2402 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2407 I915_WRITE(reg, temp);
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 if (HAS_PCH_CPT(dev)) {
2412 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2413 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_NONE;
2418 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420 /* wait one idle pattern time */
2424 /* IVB wants error correction enabled */
2425 if (IS_IVYBRIDGE(dev))
2426 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2427 FDI_FE_ERRC_ENABLE);
2430 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 u32 flags = I915_READ(SOUTH_CHICKEN1);
2435 flags |= FDI_PHASE_SYNC_OVR(pipe);
2436 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2437 flags |= FDI_PHASE_SYNC_EN(pipe);
2438 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2439 POSTING_READ(SOUTH_CHICKEN1);
2442 static void ivb_modeset_global_resources(struct drm_device *dev)
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_crtc *pipe_B_crtc =
2446 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2447 struct intel_crtc *pipe_C_crtc =
2448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2451 /* When everything is off disable fdi C so that we could enable fdi B
2452 * with all lanes. XXX: This misses the case where a pipe is not using
2453 * any pch resources and so doesn't need any fdi lanes. */
2454 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2455 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2456 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2458 temp = I915_READ(SOUTH_CHICKEN1);
2459 temp &= ~FDI_BC_BIFURCATION_SELECT;
2460 DRM_DEBUG_KMS("disabling fdi C rx\n");
2461 I915_WRITE(SOUTH_CHICKEN1, temp);
2465 /* The FDI link training functions for ILK/Ibexpeak. */
2466 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 int pipe = intel_crtc->pipe;
2472 int plane = intel_crtc->plane;
2473 u32 reg, temp, tries;
2475 /* FDI needs bits from pipe & plane first */
2476 assert_pipe_enabled(dev_priv, pipe);
2477 assert_plane_enabled(dev_priv, plane);
2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
2485 I915_WRITE(reg, temp);
2489 /* enable CPU FDI TX and PCH FDI RX */
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2494 temp &= ~FDI_LINK_TRAIN_NONE;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507 /* Ironlake workaround, enable clock pointer after FDI enable*/
2508 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2509 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2510 FDI_RX_PHASE_SYNC_POINTER_EN);
2512 reg = FDI_RX_IIR(pipe);
2513 for (tries = 0; tries < 5; tries++) {
2514 temp = I915_READ(reg);
2515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517 if ((temp & FDI_RX_BIT_LOCK)) {
2518 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524 DRM_ERROR("FDI train 1 fail!\n");
2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
2531 I915_WRITE(reg, temp);
2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 I915_WRITE(reg, temp);
2542 reg = FDI_RX_IIR(pipe);
2543 for (tries = 0; tries < 5; tries++) {
2544 temp = I915_READ(reg);
2545 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547 if (temp & FDI_RX_SYMBOL_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549 DRM_DEBUG_KMS("FDI train 2 done.\n");
2554 DRM_ERROR("FDI train 2 fail!\n");
2556 DRM_DEBUG_KMS("FDI train done\n");
2560 static const int snb_b_fdi_train_param[] = {
2561 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2562 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2563 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2564 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2567 /* The FDI link training functions for SNB/Cougarpoint. */
2568 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2573 int pipe = intel_crtc->pipe;
2574 u32 reg, temp, i, retry;
2576 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2578 reg = FDI_RX_IMR(pipe);
2579 temp = I915_READ(reg);
2580 temp &= ~FDI_RX_SYMBOL_LOCK;
2581 temp &= ~FDI_RX_BIT_LOCK;
2582 I915_WRITE(reg, temp);
2587 /* enable CPU FDI TX and PCH FDI RX */
2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
2591 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2599 I915_WRITE(FDI_RX_MISC(pipe),
2600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2602 reg = FDI_RX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 if (HAS_PCH_CPT(dev)) {
2605 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2608 temp &= ~FDI_LINK_TRAIN_NONE;
2609 temp |= FDI_LINK_TRAIN_PATTERN_1;
2611 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2616 cpt_phase_pointer_enable(dev, pipe);
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2628 for (retry = 0; retry < 5; retry++) {
2629 reg = FDI_RX_IIR(pipe);
2630 temp = I915_READ(reg);
2631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632 if (temp & FDI_RX_BIT_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2634 DRM_DEBUG_KMS("FDI train 1 done.\n");
2643 DRM_ERROR("FDI train 1 fail!\n");
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2653 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2655 I915_WRITE(reg, temp);
2657 reg = FDI_RX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 if (HAS_PCH_CPT(dev)) {
2660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2663 temp &= ~FDI_LINK_TRAIN_NONE;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2;
2666 I915_WRITE(reg, temp);
2671 for (i = 0; i < 4; i++) {
2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= snb_b_fdi_train_param[i];
2676 I915_WRITE(reg, temp);
2681 for (retry = 0; retry < 5; retry++) {
2682 reg = FDI_RX_IIR(pipe);
2683 temp = I915_READ(reg);
2684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685 if (temp & FDI_RX_SYMBOL_LOCK) {
2686 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687 DRM_DEBUG_KMS("FDI train 2 done.\n");
2696 DRM_ERROR("FDI train 2 fail!\n");
2698 DRM_DEBUG_KMS("FDI train done.\n");
2701 /* Manual link training for Ivy Bridge A0 parts */
2702 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2710 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2712 reg = FDI_RX_IMR(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~FDI_RX_SYMBOL_LOCK;
2715 temp &= ~FDI_RX_BIT_LOCK;
2716 I915_WRITE(reg, temp);
2721 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2722 I915_READ(FDI_RX_IIR(pipe)));
2724 /* enable CPU FDI TX and PCH FDI RX */
2725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2736 I915_WRITE(FDI_RX_MISC(pipe),
2737 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_AUTO;
2742 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2743 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2744 temp |= FDI_COMPOSITE_SYNC;
2745 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750 cpt_phase_pointer_enable(dev, pipe);
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= snb_b_fdi_train_param[i];
2757 I915_WRITE(reg, temp);
2762 reg = FDI_RX_IIR(pipe);
2763 temp = I915_READ(reg);
2764 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2766 if (temp & FDI_RX_BIT_LOCK ||
2767 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2768 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2769 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2774 DRM_ERROR("FDI train 1 fail!\n");
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2780 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2782 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2783 I915_WRITE(reg, temp);
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2789 I915_WRITE(reg, temp);
2794 for (i = 0; i < 4; i++) {
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2798 temp |= snb_b_fdi_train_param[i];
2799 I915_WRITE(reg, temp);
2804 reg = FDI_RX_IIR(pipe);
2805 temp = I915_READ(reg);
2806 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2808 if (temp & FDI_RX_SYMBOL_LOCK) {
2809 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2810 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2815 DRM_ERROR("FDI train 2 fail!\n");
2817 DRM_DEBUG_KMS("FDI train done.\n");
2820 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2822 struct drm_device *dev = intel_crtc->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 int pipe = intel_crtc->pipe;
2828 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~((0x7 << 19) | (0x7 << 16));
2832 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2833 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2834 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2839 /* Switch from Rawclk to PCDclk */
2840 temp = I915_READ(reg);
2841 I915_WRITE(reg, temp | FDI_PCDCLK);
2846 /* On Haswell, the PLL configuration for ports and pipes is handled
2847 * separately, as part of DDI setup */
2848 if (!IS_HASWELL(dev)) {
2849 /* Enable CPU FDI TX PLL, always on for Ironlake */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2853 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2861 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2885 /* Wait for the clocks to turn off. */
2890 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 u32 flags = I915_READ(SOUTH_CHICKEN1);
2895 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2896 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2897 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2898 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2899 POSTING_READ(SOUTH_CHICKEN1);
2901 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2909 /* disable CPU FDI tx and PCH FDI rx */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2915 reg = FDI_RX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 temp &= ~(0x7 << 16);
2918 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2919 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2924 /* Ironlake workaround, disable clock pointer after downing FDI */
2925 if (HAS_PCH_IBX(dev)) {
2926 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2927 } else if (HAS_PCH_CPT(dev)) {
2928 cpt_phase_pointer_disable(dev, pipe);
2931 /* still set train pattern 1 */
2932 reg = FDI_TX_CTL(pipe);
2933 temp = I915_READ(reg);
2934 temp &= ~FDI_LINK_TRAIN_NONE;
2935 temp |= FDI_LINK_TRAIN_PATTERN_1;
2936 I915_WRITE(reg, temp);
2938 reg = FDI_RX_CTL(pipe);
2939 temp = I915_READ(reg);
2940 if (HAS_PCH_CPT(dev)) {
2941 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2944 temp &= ~FDI_LINK_TRAIN_NONE;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1;
2947 /* BPC in FDI rx is consistent with that in PIPECONF */
2948 temp &= ~(0x07 << 16);
2949 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2950 I915_WRITE(reg, temp);
2956 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 unsigned long flags;
2963 if (atomic_read(&dev_priv->mm.wedged))
2966 spin_lock_irqsave(&dev->event_lock, flags);
2967 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2968 spin_unlock_irqrestore(&dev->event_lock, flags);
2973 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2975 struct drm_device *dev = crtc->dev;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2978 if (crtc->fb == NULL)
2981 wait_event(dev_priv->pending_flip_queue,
2982 !intel_crtc_has_pending_flip(crtc));
2984 mutex_lock(&dev->struct_mutex);
2985 intel_finish_fb(crtc->fb);
2986 mutex_unlock(&dev->struct_mutex);
2989 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2991 struct drm_device *dev = crtc->dev;
2992 struct intel_encoder *intel_encoder;
2995 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2996 * must be driven by its own crtc; no sharing is possible.
2998 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2999 switch (intel_encoder->type) {
3000 case INTEL_OUTPUT_EDP:
3001 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3010 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3012 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3015 /* Program iCLKIP clock to the desired frequency */
3016 static void lpt_program_iclkip(struct drm_crtc *crtc)
3018 struct drm_device *dev = crtc->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3023 /* It is necessary to ungate the pixclk gate prior to programming
3024 * the divisors, and gate it back when it is done.
3026 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3028 /* Disable SSCCTL */
3029 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3030 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3031 SBI_SSCCTL_DISABLE);
3033 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3034 if (crtc->mode.clock == 20000) {
3039 /* The iCLK virtual clock root frequency is in MHz,
3040 * but the crtc->mode.clock in in KHz. To get the divisors,
3041 * it is necessary to divide one by another, so we
3042 * convert the virtual clock precision to KHz here for higher
3045 u32 iclk_virtual_root_freq = 172800 * 1000;
3046 u32 iclk_pi_range = 64;
3047 u32 desired_divisor, msb_divisor_value, pi_value;
3049 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3050 msb_divisor_value = desired_divisor / iclk_pi_range;
3051 pi_value = desired_divisor % iclk_pi_range;
3054 divsel = msb_divisor_value - 2;
3055 phaseinc = pi_value;
3058 /* This should not happen with any sane values */
3059 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3060 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3061 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3062 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3064 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3071 /* Program SSCDIVINTPHASE6 */
3072 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3073 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3074 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3075 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3076 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3077 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3078 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3080 intel_sbi_write(dev_priv,
3081 SBI_SSCDIVINTPHASE6,
3084 /* Program SSCAUXDIV */
3085 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3086 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3087 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3088 intel_sbi_write(dev_priv,
3093 /* Enable modulator and associated divider */
3094 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3095 temp &= ~SBI_SSCCTL_DISABLE;
3096 intel_sbi_write(dev_priv,
3100 /* Wait for initialization time */
3103 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3107 * Enable PCH resources required for PCH ports:
3109 * - FDI training & RX/TX
3110 * - update transcoder timings
3111 * - DP transcoding bits
3114 static void ironlake_pch_enable(struct drm_crtc *crtc)
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 int pipe = intel_crtc->pipe;
3122 assert_transcoder_disabled(dev_priv, pipe);
3124 /* Write the TU size bits before fdi link training, so that error
3125 * detection works. */
3126 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3127 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3129 /* For PCH output, training FDI link */
3130 dev_priv->display.fdi_link_train(crtc);
3132 /* XXX: pch pll's can be enabled any time before we enable the PCH
3133 * transcoder, and we actually should do this to not upset any PCH
3134 * transcoder that already use the clock when we share it.
3136 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3137 * unconditionally resets the pll - we need that to have the right LVDS
3138 * enable sequence. */
3139 ironlake_enable_pch_pll(intel_crtc);
3141 if (HAS_PCH_CPT(dev)) {
3144 temp = I915_READ(PCH_DPLL_SEL);
3148 temp |= TRANSA_DPLL_ENABLE;
3149 sel = TRANSA_DPLLB_SEL;
3152 temp |= TRANSB_DPLL_ENABLE;
3153 sel = TRANSB_DPLLB_SEL;
3156 temp |= TRANSC_DPLL_ENABLE;
3157 sel = TRANSC_DPLLB_SEL;
3160 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3164 I915_WRITE(PCH_DPLL_SEL, temp);
3167 /* set transcoder timing, panel must allow it */
3168 assert_panel_unlocked(dev_priv, pipe);
3169 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3170 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3171 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3173 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3174 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3175 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3176 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3178 intel_fdi_normal_train(crtc);
3180 /* For PCH DP, enable TRANS_DP_CTL */
3181 if (HAS_PCH_CPT(dev) &&
3182 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3183 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3184 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3185 reg = TRANS_DP_CTL(pipe);
3186 temp = I915_READ(reg);
3187 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3188 TRANS_DP_SYNC_MASK |
3190 temp |= (TRANS_DP_OUTPUT_ENABLE |
3191 TRANS_DP_ENH_FRAMING);
3192 temp |= bpc << 9; /* same format but at 11:9 */
3194 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3195 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3196 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3197 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3199 switch (intel_trans_dp_port_sel(crtc)) {
3201 temp |= TRANS_DP_PORT_SEL_B;
3204 temp |= TRANS_DP_PORT_SEL_C;
3207 temp |= TRANS_DP_PORT_SEL_D;
3213 I915_WRITE(reg, temp);
3216 ironlake_enable_pch_transcoder(dev_priv, pipe);
3219 static void lpt_pch_enable(struct drm_crtc *crtc)
3221 struct drm_device *dev = crtc->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3226 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3228 lpt_program_iclkip(crtc);
3230 /* Set transcoder timing. */
3231 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3232 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3233 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3235 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3236 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3237 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3238 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3240 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3243 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3245 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3250 if (pll->refcount == 0) {
3251 WARN(1, "bad PCH PLL refcount\n");
3256 intel_crtc->pch_pll = NULL;
3259 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3261 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3262 struct intel_pch_pll *pll;
3265 pll = intel_crtc->pch_pll;
3267 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3268 intel_crtc->base.base.id, pll->pll_reg);
3272 if (HAS_PCH_IBX(dev_priv->dev)) {
3273 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3274 i = intel_crtc->pipe;
3275 pll = &dev_priv->pch_plls[i];
3277 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3278 intel_crtc->base.base.id, pll->pll_reg);
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3286 /* Only want to check enabled timings first */
3287 if (pll->refcount == 0)
3290 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3291 fp == I915_READ(pll->fp0_reg)) {
3292 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3293 intel_crtc->base.base.id,
3294 pll->pll_reg, pll->refcount, pll->active);
3300 /* Ok no matching timings, maybe there's a free one? */
3301 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3302 pll = &dev_priv->pch_plls[i];
3303 if (pll->refcount == 0) {
3304 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3305 intel_crtc->base.base.id, pll->pll_reg);
3313 intel_crtc->pch_pll = pll;
3315 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3316 prepare: /* separate function? */
3317 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3319 /* Wait for the clocks to stabilize before rewriting the regs */
3320 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3321 POSTING_READ(pll->pll_reg);
3324 I915_WRITE(pll->fp0_reg, fp);
3325 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3330 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 int dslreg = PIPEDSL(pipe);
3336 temp = I915_READ(dslreg);
3338 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3339 if (wait_for(I915_READ(dslreg) != temp, 5))
3340 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3344 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3346 struct drm_device *dev = crtc->dev;
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349 struct intel_encoder *encoder;
3350 int pipe = intel_crtc->pipe;
3351 int plane = intel_crtc->plane;
3355 WARN_ON(!crtc->enabled);
3357 if (intel_crtc->active)
3360 intel_crtc->active = true;
3361 intel_update_watermarks(dev);
3363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3364 temp = I915_READ(PCH_LVDS);
3365 if ((temp & LVDS_PORT_EN) == 0)
3366 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3369 is_pch_port = ironlake_crtc_driving_pch(crtc);
3372 /* Note: FDI PLL enabling _must_ be done before we enable the
3373 * cpu pipes, hence this is separate from all the other fdi/pch
3375 ironlake_fdi_pll_enable(intel_crtc);
3377 assert_fdi_tx_disabled(dev_priv, pipe);
3378 assert_fdi_rx_disabled(dev_priv, pipe);
3381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 if (encoder->pre_enable)
3383 encoder->pre_enable(encoder);
3385 /* Enable panel fitting for LVDS */
3386 if (dev_priv->pch_pf_size &&
3387 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3388 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3389 /* Force use of hard-coded filter coefficients
3390 * as some pre-programmed values are broken,
3393 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3394 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3395 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3399 * On ILK+ LUT must be loaded before the pipe is running but with
3402 intel_crtc_load_lut(crtc);
3404 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405 intel_enable_plane(dev_priv, plane, pipe);
3408 ironlake_pch_enable(crtc);
3410 mutex_lock(&dev->struct_mutex);
3411 intel_update_fbc(dev);
3412 mutex_unlock(&dev->struct_mutex);
3414 intel_crtc_update_cursor(crtc, true);
3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->enable(encoder);
3419 if (HAS_PCH_CPT(dev))
3420 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3423 * There seems to be a race in PCH platform hw (at least on some
3424 * outputs) where an enabled pipe still completes any pageflip right
3425 * away (as if the pipe is off) instead of waiting for vblank. As soon
3426 * as the first vblank happend, everything works as expected. Hence just
3427 * wait for one vblank before returning to avoid strange things
3430 intel_wait_for_vblank(dev, intel_crtc->pipe);
3433 static void haswell_crtc_enable(struct drm_crtc *crtc)
3435 struct drm_device *dev = crtc->dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438 struct intel_encoder *encoder;
3439 int pipe = intel_crtc->pipe;
3440 int plane = intel_crtc->plane;
3443 WARN_ON(!crtc->enabled);
3445 if (intel_crtc->active)
3448 intel_crtc->active = true;
3449 intel_update_watermarks(dev);
3451 is_pch_port = haswell_crtc_driving_pch(crtc);
3454 dev_priv->display.fdi_link_train(crtc);
3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 if (encoder->pre_enable)
3458 encoder->pre_enable(encoder);
3460 intel_ddi_enable_pipe_clock(intel_crtc);
3462 /* Enable panel fitting for eDP */
3463 if (dev_priv->pch_pf_size &&
3464 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3465 /* Force use of hard-coded filter coefficients
3466 * as some pre-programmed values are broken,
3469 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3470 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3471 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3475 * On ILK+ LUT must be loaded before the pipe is running but with
3478 intel_crtc_load_lut(crtc);
3480 intel_ddi_set_pipe_settings(crtc);
3481 intel_ddi_enable_pipe_func(crtc);
3483 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3484 intel_enable_plane(dev_priv, plane, pipe);
3487 lpt_pch_enable(crtc);
3489 mutex_lock(&dev->struct_mutex);
3490 intel_update_fbc(dev);
3491 mutex_unlock(&dev->struct_mutex);
3493 intel_crtc_update_cursor(crtc, true);
3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->enable(encoder);
3499 * There seems to be a race in PCH platform hw (at least on some
3500 * outputs) where an enabled pipe still completes any pageflip right
3501 * away (as if the pipe is off) instead of waiting for vblank. As soon
3502 * as the first vblank happend, everything works as expected. Hence just
3503 * wait for one vblank before returning to avoid strange things
3506 intel_wait_for_vblank(dev, intel_crtc->pipe);
3509 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3520 if (!intel_crtc->active)
3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 encoder->disable(encoder);
3526 intel_crtc_wait_for_pending_flips(crtc);
3527 drm_vblank_off(dev, pipe);
3528 intel_crtc_update_cursor(crtc, false);
3530 intel_disable_plane(dev_priv, plane, pipe);
3532 if (dev_priv->cfb_plane == plane)
3533 intel_disable_fbc(dev);
3535 intel_disable_pipe(dev_priv, pipe);
3538 I915_WRITE(PF_CTL(pipe), 0);
3539 I915_WRITE(PF_WIN_SZ(pipe), 0);
3541 for_each_encoder_on_crtc(dev, crtc, encoder)
3542 if (encoder->post_disable)
3543 encoder->post_disable(encoder);
3545 ironlake_fdi_disable(crtc);
3547 ironlake_disable_pch_transcoder(dev_priv, pipe);
3549 if (HAS_PCH_CPT(dev)) {
3550 /* disable TRANS_DP_CTL */
3551 reg = TRANS_DP_CTL(pipe);
3552 temp = I915_READ(reg);
3553 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3554 temp |= TRANS_DP_PORT_SEL_NONE;
3555 I915_WRITE(reg, temp);
3557 /* disable DPLL_SEL */
3558 temp = I915_READ(PCH_DPLL_SEL);
3561 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3564 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3567 /* C shares PLL A or B */
3568 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3573 I915_WRITE(PCH_DPLL_SEL, temp);
3576 /* disable PCH DPLL */
3577 intel_disable_pch_pll(intel_crtc);
3579 ironlake_fdi_pll_disable(intel_crtc);
3581 intel_crtc->active = false;
3582 intel_update_watermarks(dev);
3584 mutex_lock(&dev->struct_mutex);
3585 intel_update_fbc(dev);
3586 mutex_unlock(&dev->struct_mutex);
3589 static void haswell_crtc_disable(struct drm_crtc *crtc)
3591 struct drm_device *dev = crtc->dev;
3592 struct drm_i915_private *dev_priv = dev->dev_private;
3593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594 struct intel_encoder *encoder;
3595 int pipe = intel_crtc->pipe;
3596 int plane = intel_crtc->plane;
3597 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3600 if (!intel_crtc->active)
3603 is_pch_port = haswell_crtc_driving_pch(crtc);
3605 for_each_encoder_on_crtc(dev, crtc, encoder)
3606 encoder->disable(encoder);
3608 intel_crtc_wait_for_pending_flips(crtc);
3609 drm_vblank_off(dev, pipe);
3610 intel_crtc_update_cursor(crtc, false);
3612 intel_disable_plane(dev_priv, plane, pipe);
3614 if (dev_priv->cfb_plane == plane)
3615 intel_disable_fbc(dev);
3617 intel_disable_pipe(dev_priv, pipe);
3619 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3622 I915_WRITE(PF_CTL(pipe), 0);
3623 I915_WRITE(PF_WIN_SZ(pipe), 0);
3625 intel_ddi_disable_pipe_clock(intel_crtc);
3627 for_each_encoder_on_crtc(dev, crtc, encoder)
3628 if (encoder->post_disable)
3629 encoder->post_disable(encoder);
3632 lpt_disable_pch_transcoder(dev_priv);
3633 intel_ddi_fdi_disable(crtc);
3636 intel_crtc->active = false;
3637 intel_update_watermarks(dev);
3639 mutex_lock(&dev->struct_mutex);
3640 intel_update_fbc(dev);
3641 mutex_unlock(&dev->struct_mutex);
3644 static void ironlake_crtc_off(struct drm_crtc *crtc)
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 intel_put_pch_pll(intel_crtc);
3650 static void haswell_crtc_off(struct drm_crtc *crtc)
3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3655 * start using it. */
3656 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3658 intel_ddi_put_crtc_pll(crtc);
3661 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3663 if (!enable && intel_crtc->overlay) {
3664 struct drm_device *dev = intel_crtc->base.dev;
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3667 mutex_lock(&dev->struct_mutex);
3668 dev_priv->mm.interruptible = false;
3669 (void) intel_overlay_switch_off(intel_crtc->overlay);
3670 dev_priv->mm.interruptible = true;
3671 mutex_unlock(&dev->struct_mutex);
3674 /* Let userspace switch the overlay on again. In most cases userspace
3675 * has to recompute where to put it anyway.
3679 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3681 struct drm_device *dev = crtc->dev;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684 struct intel_encoder *encoder;
3685 int pipe = intel_crtc->pipe;
3686 int plane = intel_crtc->plane;
3688 WARN_ON(!crtc->enabled);
3690 if (intel_crtc->active)
3693 intel_crtc->active = true;
3694 intel_update_watermarks(dev);
3696 intel_enable_pll(dev_priv, pipe);
3697 intel_enable_pipe(dev_priv, pipe, false);
3698 intel_enable_plane(dev_priv, plane, pipe);
3700 intel_crtc_load_lut(crtc);
3701 intel_update_fbc(dev);
3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc, true);
3705 intel_crtc_update_cursor(crtc, true);
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
3711 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 struct intel_encoder *encoder;
3717 int pipe = intel_crtc->pipe;
3718 int plane = intel_crtc->plane;
3721 if (!intel_crtc->active)
3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->disable(encoder);
3727 /* Give the overlay scaler a chance to disable if it's on this pipe */
3728 intel_crtc_wait_for_pending_flips(crtc);
3729 drm_vblank_off(dev, pipe);
3730 intel_crtc_dpms_overlay(intel_crtc, false);
3731 intel_crtc_update_cursor(crtc, false);
3733 if (dev_priv->cfb_plane == plane)
3734 intel_disable_fbc(dev);
3736 intel_disable_plane(dev_priv, plane, pipe);
3737 intel_disable_pipe(dev_priv, pipe);
3738 intel_disable_pll(dev_priv, pipe);
3740 intel_crtc->active = false;
3741 intel_update_fbc(dev);
3742 intel_update_watermarks(dev);
3745 static void i9xx_crtc_off(struct drm_crtc *crtc)
3749 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3752 struct drm_device *dev = crtc->dev;
3753 struct drm_i915_master_private *master_priv;
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755 int pipe = intel_crtc->pipe;
3757 if (!dev->primary->master)
3760 master_priv = dev->primary->master->driver_priv;
3761 if (!master_priv->sarea_priv)
3766 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3767 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3770 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3771 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3774 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3780 * Sets the power management mode of the pipe and plane.
3782 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_encoder *intel_encoder;
3787 bool enable = false;
3789 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3790 enable |= intel_encoder->connectors_active;
3793 dev_priv->display.crtc_enable(crtc);
3795 dev_priv->display.crtc_disable(crtc);
3797 intel_crtc_update_sarea(crtc, enable);
3800 static void intel_crtc_noop(struct drm_crtc *crtc)
3804 static void intel_crtc_disable(struct drm_crtc *crtc)
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_connector *connector;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3810 /* crtc should still be enabled when we disable it. */
3811 WARN_ON(!crtc->enabled);
3813 dev_priv->display.crtc_disable(crtc);
3814 intel_crtc_update_sarea(crtc, false);
3815 dev_priv->display.off(crtc);
3817 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3818 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3821 mutex_lock(&dev->struct_mutex);
3822 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3823 mutex_unlock(&dev->struct_mutex);
3827 /* Update computed state. */
3828 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3829 if (!connector->encoder || !connector->encoder->crtc)
3832 if (connector->encoder->crtc != crtc)
3835 connector->dpms = DRM_MODE_DPMS_OFF;
3836 to_intel_encoder(connector->encoder)->connectors_active = false;
3840 void intel_modeset_disable(struct drm_device *dev)
3842 struct drm_crtc *crtc;
3844 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3846 intel_crtc_disable(crtc);
3850 void intel_encoder_noop(struct drm_encoder *encoder)
3854 void intel_encoder_destroy(struct drm_encoder *encoder)
3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
3862 /* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3870 intel_crtc_update_dpms(encoder->base.crtc);
3872 encoder->connectors_active = false;
3874 intel_crtc_update_dpms(encoder->base.crtc);
3878 /* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
3880 static void intel_connector_check_state(struct intel_connector *connector)
3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3904 crtc = encoder->base.crtc;
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3913 /* Even simpler default implementation, if there's really no special case to
3915 void intel_connector_dpms(struct drm_connector *connector, int mode)
3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
3923 if (mode == connector->dpms)
3926 connector->dpms = mode;
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3932 WARN_ON(encoder->connectors_active != false);
3934 intel_modeset_check_state(connector->dev);
3937 /* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 struct intel_encoder *encoder = connector->encoder;
3945 return encoder->get_hw_state(encoder, &pipe);
3948 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3949 const struct drm_display_mode *mode,
3950 struct drm_display_mode *adjusted_mode)
3952 struct drm_device *dev = crtc->dev;
3954 if (HAS_PCH_SPLIT(dev)) {
3955 /* FDI link clock is fixed at 2.7G */
3956 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3960 /* All interlaced capable intel hw wants timings in frames. Note though
3961 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3962 * timings, so we need to be careful not to clobber these.*/
3963 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3964 drm_mode_set_crtcinfo(adjusted_mode, 0);
3966 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3967 * with a hsync front porch of 0.
3969 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3970 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3976 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3978 return 400000; /* FIXME */
3981 static int i945_get_display_clock_speed(struct drm_device *dev)
3986 static int i915_get_display_clock_speed(struct drm_device *dev)
3991 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3996 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4000 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4002 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4005 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4006 case GC_DISPLAY_CLOCK_333_MHZ:
4009 case GC_DISPLAY_CLOCK_190_200_MHZ:
4015 static int i865_get_display_clock_speed(struct drm_device *dev)
4020 static int i855_get_display_clock_speed(struct drm_device *dev)
4023 /* Assume that the hardware is in the high speed state. This
4024 * should be the default.
4026 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4027 case GC_CLOCK_133_200:
4028 case GC_CLOCK_100_200:
4030 case GC_CLOCK_166_250:
4032 case GC_CLOCK_100_133:
4036 /* Shouldn't happen */
4040 static int i830_get_display_clock_speed(struct drm_device *dev)
4054 fdi_reduce_ratio(u32 *num, u32 *den)
4056 while (*num > 0xffffff || *den > 0xffffff) {
4063 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4064 int link_clock, struct fdi_m_n *m_n)
4066 m_n->tu = 64; /* default size */
4068 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
4071 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4073 m_n->link_m = pixel_clock;
4074 m_n->link_n = link_clock;
4075 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4078 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4080 if (i915_panel_use_ssc >= 0)
4081 return i915_panel_use_ssc != 0;
4082 return dev_priv->lvds_use_ssc
4083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4087 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4088 * @crtc: CRTC structure
4089 * @mode: requested mode
4091 * A pipe may be connected to one or more outputs. Based on the depth of the
4092 * attached framebuffer, choose a good color depth to use on the pipe.
4094 * If possible, match the pipe depth to the fb depth. In some cases, this
4095 * isn't ideal, because the connected output supports a lesser or restricted
4096 * set of depths. Resolve that here:
4097 * LVDS typically supports only 6bpc, so clamp down in that case
4098 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4099 * Displays may support a restricted set as well, check EDID and clamp as
4101 * DP may want to dither down to 6bpc to fit larger modes
4104 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4105 * true if they don't match).
4107 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4108 struct drm_framebuffer *fb,
4109 unsigned int *pipe_bpp,
4110 struct drm_display_mode *mode)
4112 struct drm_device *dev = crtc->dev;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 struct drm_connector *connector;
4115 struct intel_encoder *intel_encoder;
4116 unsigned int display_bpc = UINT_MAX, bpc;
4118 /* Walk the encoders & connectors on this crtc, get min bpc */
4119 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4121 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4122 unsigned int lvds_bpc;
4124 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4130 if (lvds_bpc < display_bpc) {
4131 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4132 display_bpc = lvds_bpc;
4137 /* Not one of the known troublemakers, check the EDID */
4138 list_for_each_entry(connector, &dev->mode_config.connector_list,
4140 if (connector->encoder != &intel_encoder->base)
4143 /* Don't use an invalid EDID bpc value */
4144 if (connector->display_info.bpc &&
4145 connector->display_info.bpc < display_bpc) {
4146 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4147 display_bpc = connector->display_info.bpc;
4152 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4153 * through, clamp it down. (Note: >12bpc will be caught below.)
4155 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4156 if (display_bpc > 8 && display_bpc < 12) {
4157 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4160 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4166 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4167 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4172 * We could just drive the pipe at the highest bpc all the time and
4173 * enable dithering as needed, but that costs bandwidth. So choose
4174 * the minimum value that expresses the full color range of the fb but
4175 * also stays within the max display bpc discovered above.
4178 switch (fb->depth) {
4180 bpc = 8; /* since we go through a colormap */
4184 bpc = 6; /* min is 18bpp */
4196 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4197 bpc = min((unsigned int)8, display_bpc);
4201 display_bpc = min(display_bpc, bpc);
4203 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4206 *pipe_bpp = display_bpc * 3;
4208 return display_bpc != bpc;
4211 static int vlv_get_refclk(struct drm_crtc *crtc)
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 int refclk = 27000; /* for DP & HDMI */
4217 return 100000; /* only one validated so far */
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4221 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4222 if (intel_panel_use_ssc(dev_priv))
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4233 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4239 if (IS_VALLEYVIEW(dev)) {
4240 refclk = vlv_get_refclk(crtc);
4241 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4242 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4243 refclk = dev_priv->lvds_ssc_freq * 1000;
4244 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4246 } else if (!IS_GEN2(dev)) {
4255 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4256 intel_clock_t *clock)
4258 /* SDVO TV has fixed PLL values depend on its clock range,
4259 this mirrors vbios setting. */
4260 if (adjusted_mode->clock >= 100000
4261 && adjusted_mode->clock < 140500) {
4267 } else if (adjusted_mode->clock >= 140500
4268 && adjusted_mode->clock <= 200000) {
4277 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4278 intel_clock_t *clock,
4279 intel_clock_t *reduced_clock)
4281 struct drm_device *dev = crtc->dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284 int pipe = intel_crtc->pipe;
4287 if (IS_PINEVIEW(dev)) {
4288 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4290 fp2 = (1 << reduced_clock->n) << 16 |
4291 reduced_clock->m1 << 8 | reduced_clock->m2;
4293 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4295 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4299 I915_WRITE(FP0(pipe), fp);
4301 intel_crtc->lowfreq_avail = false;
4302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4303 reduced_clock && i915_powersave) {
4304 I915_WRITE(FP1(pipe), fp2);
4305 intel_crtc->lowfreq_avail = true;
4307 I915_WRITE(FP1(pipe), fp);
4311 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4312 struct drm_display_mode *adjusted_mode)
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 int pipe = intel_crtc->pipe;
4320 temp = I915_READ(LVDS);
4321 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4323 temp |= LVDS_PIPEB_SELECT;
4325 temp &= ~LVDS_PIPEB_SELECT;
4327 /* set the corresponsding LVDS_BORDER bit */
4328 temp |= dev_priv->lvds_border_bits;
4329 /* Set the B0-B3 data pairs corresponding to whether we're going to
4330 * set the DPLLs for dual-channel mode or not.
4333 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4335 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4337 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4338 * appropriately here, but we need to look more thoroughly into how
4339 * panels behave in the two modes.
4341 /* set the dithering flag on LVDS as needed */
4342 if (INTEL_INFO(dev)->gen >= 4) {
4343 if (dev_priv->lvds_dither)
4344 temp |= LVDS_ENABLE_DITHER;
4346 temp &= ~LVDS_ENABLE_DITHER;
4348 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4349 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4350 temp |= LVDS_HSYNC_POLARITY;
4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4352 temp |= LVDS_VSYNC_POLARITY;
4353 I915_WRITE(LVDS, temp);
4356 static void vlv_update_pll(struct drm_crtc *crtc,
4357 struct drm_display_mode *mode,
4358 struct drm_display_mode *adjusted_mode,
4359 intel_clock_t *clock, intel_clock_t *reduced_clock,
4362 struct drm_device *dev = crtc->dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365 int pipe = intel_crtc->pipe;
4366 u32 dpll, mdiv, pdiv;
4367 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4371 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4372 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4374 dpll = DPLL_VGA_MODE_DIS;
4375 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4379 I915_WRITE(DPLL(pipe), dpll);
4380 POSTING_READ(DPLL(pipe));
4389 * In Valleyview PLL and program lane counter registers are exposed
4390 * through DPIO interface
4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
4395 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4396 mdiv |= (1 << DPIO_K_SHIFT);
4397 mdiv |= DPIO_ENABLE_CALIBRATION;
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4402 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4403 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4404 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4405 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4410 dpll |= DPLL_VCO_ENABLE;
4411 I915_WRITE(DPLL(pipe), dpll);
4412 POSTING_READ(DPLL(pipe));
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4416 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4421 I915_WRITE(DPLL(pipe), dpll);
4423 /* Wait for the clocks to stabilize. */
4424 POSTING_READ(DPLL(pipe));
4429 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4431 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4435 I915_WRITE(DPLL_MD(pipe), temp);
4436 POSTING_READ(DPLL_MD(pipe));
4438 /* Now program lane control registers */
4439 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4440 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4445 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4447 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4452 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4456 static void i9xx_update_pll(struct drm_crtc *crtc,
4457 struct drm_display_mode *mode,
4458 struct drm_display_mode *adjusted_mode,
4459 intel_clock_t *clock, intel_clock_t *reduced_clock,
4462 struct drm_device *dev = crtc->dev;
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 int pipe = intel_crtc->pipe;
4469 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4471 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4474 dpll = DPLL_VGA_MODE_DIS;
4476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477 dpll |= DPLLB_MODE_LVDS;
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4481 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482 if (pixel_multiplier > 1) {
4483 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4491 /* compute bitmask from p1 value */
4492 if (IS_PINEVIEW(dev))
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496 if (IS_G4X(dev) && reduced_clock)
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4499 switch (clock->p2) {
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4513 if (INTEL_INFO(dev)->gen >= 4)
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4516 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 /* XXX: just matching BIOS for now */
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4533 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4534 * This is an exception to the general rule that mode_set doesn't turn
4537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4538 intel_update_lvds(crtc, clock, adjusted_mode);
4540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4541 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4543 I915_WRITE(DPLL(pipe), dpll);
4545 /* Wait for the clocks to stabilize. */
4546 POSTING_READ(DPLL(pipe));
4549 if (INTEL_INFO(dev)->gen >= 4) {
4552 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4554 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4558 I915_WRITE(DPLL_MD(pipe), temp);
4560 /* The pixel multiplier can only be updated once the
4561 * DPLL is enabled and the clocks are stable.
4563 * So write it again.
4565 I915_WRITE(DPLL(pipe), dpll);
4569 static void i8xx_update_pll(struct drm_crtc *crtc,
4570 struct drm_display_mode *adjusted_mode,
4571 intel_clock_t *clock, intel_clock_t *reduced_clock,
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4580 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4582 dpll = DPLL_VGA_MODE_DIS;
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588 dpll |= PLL_P1_DIVIDE_BY_TWO;
4590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 dpll |= PLL_P2_DIVIDE_BY_4;
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4596 /* XXX: just matching BIOS for now */
4597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4599 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4603 dpll |= PLL_REF_INPUT_DREFCLK;
4605 dpll |= DPLL_VCO_ENABLE;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607 POSTING_READ(DPLL(pipe));
4610 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4611 * This is an exception to the general rule that mode_set doesn't turn
4614 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4615 intel_update_lvds(crtc, clock, adjusted_mode);
4617 I915_WRITE(DPLL(pipe), dpll);
4619 /* Wait for the clocks to stabilize. */
4620 POSTING_READ(DPLL(pipe));
4623 /* The pixel multiplier can only be updated once the
4624 * DPLL is enabled and the clocks are stable.
4626 * So write it again.
4628 I915_WRITE(DPLL(pipe), dpll);
4631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4632 struct drm_display_mode *mode,
4633 struct drm_display_mode *adjusted_mode)
4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 enum pipe pipe = intel_crtc->pipe;
4638 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4639 uint32_t vsyncshift;
4641 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vtotal -= 1;
4644 adjusted_mode->crtc_vblank_end -= 1;
4645 vsyncshift = adjusted_mode->crtc_hsync_start
4646 - adjusted_mode->crtc_htotal / 2;
4651 if (INTEL_INFO(dev)->gen > 3)
4652 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4654 I915_WRITE(HTOTAL(cpu_transcoder),
4655 (adjusted_mode->crtc_hdisplay - 1) |
4656 ((adjusted_mode->crtc_htotal - 1) << 16));
4657 I915_WRITE(HBLANK(cpu_transcoder),
4658 (adjusted_mode->crtc_hblank_start - 1) |
4659 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4660 I915_WRITE(HSYNC(cpu_transcoder),
4661 (adjusted_mode->crtc_hsync_start - 1) |
4662 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664 I915_WRITE(VTOTAL(cpu_transcoder),
4665 (adjusted_mode->crtc_vdisplay - 1) |
4666 ((adjusted_mode->crtc_vtotal - 1) << 16));
4667 I915_WRITE(VBLANK(cpu_transcoder),
4668 (adjusted_mode->crtc_vblank_start - 1) |
4669 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4670 I915_WRITE(VSYNC(cpu_transcoder),
4671 (adjusted_mode->crtc_vsync_start - 1) |
4672 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4675 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4676 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4679 (pipe == PIPE_B || pipe == PIPE_C))
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682 /* pipesrc controls the size that is scaled from, which should
4683 * always be the user's requested size.
4685 I915_WRITE(PIPESRC(pipe),
4686 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4690 struct drm_display_mode *mode,
4691 struct drm_display_mode *adjusted_mode,
4693 struct drm_framebuffer *fb)
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
4699 int plane = intel_crtc->plane;
4700 int refclk, num_connectors = 0;
4701 intel_clock_t clock, reduced_clock;
4702 u32 dspcntr, pipeconf;
4703 bool ok, has_reduced_clock = false, is_sdvo = false;
4704 bool is_lvds = false, is_tv = false, is_dp = false;
4705 struct intel_encoder *encoder;
4706 const intel_limit_t *limit;
4709 for_each_encoder_on_crtc(dev, crtc, encoder) {
4710 switch (encoder->type) {
4711 case INTEL_OUTPUT_LVDS:
4714 case INTEL_OUTPUT_SDVO:
4715 case INTEL_OUTPUT_HDMI:
4717 if (encoder->needs_tv_clock)
4720 case INTEL_OUTPUT_TVOUT:
4723 case INTEL_OUTPUT_DISPLAYPORT:
4731 refclk = i9xx_get_refclk(crtc, num_connectors);
4734 * Returns a set of divisors for the desired target clock with the given
4735 * refclk, or FALSE. The returned values represent the clock equation:
4736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4738 limit = intel_limit(crtc, refclk);
4739 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4742 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4746 /* Ensure that the cursor is valid for the new mode before changing... */
4747 intel_crtc_update_cursor(crtc, true);
4749 if (is_lvds && dev_priv->lvds_downclock_avail) {
4751 * Ensure we match the reduced clock's P to the target clock.
4752 * If the clocks don't match, we can't switch the display clock
4753 * by using the FP0/FP1. In such case we will disable the LVDS
4754 * downclock feature.
4756 has_reduced_clock = limit->find_pll(limit, crtc,
4757 dev_priv->lvds_downclock,
4763 if (is_sdvo && is_tv)
4764 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4767 i8xx_update_pll(crtc, adjusted_mode, &clock,
4768 has_reduced_clock ? &reduced_clock : NULL,
4770 else if (IS_VALLEYVIEW(dev))
4771 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4772 has_reduced_clock ? &reduced_clock : NULL,
4775 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4776 has_reduced_clock ? &reduced_clock : NULL,
4779 /* setup pipeconf */
4780 pipeconf = I915_READ(PIPECONF(pipe));
4782 /* Set up the display plane register */
4783 dspcntr = DISPPLANE_GAMMA_ENABLE;
4786 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4788 dspcntr |= DISPPLANE_SEL_PIPE_B;
4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4798 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799 pipeconf |= PIPECONF_DOUBLE_WIDE;
4801 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4804 /* default to 8bpc */
4805 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4807 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4808 pipeconf |= PIPECONF_BPP_6 |
4809 PIPECONF_DITHER_EN |
4810 PIPECONF_DITHER_TYPE_SP;
4814 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4815 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4816 pipeconf |= PIPECONF_BPP_6 |
4818 I965_PIPECONF_ACTIVE;
4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4823 drm_mode_debug_printmodeline(mode);
4825 if (HAS_PIPE_CXSR(dev)) {
4826 if (intel_crtc->lowfreq_avail) {
4827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4831 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4835 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4836 if (!IS_GEN2(dev) &&
4837 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4838 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4840 pipeconf |= PIPECONF_PROGRESSIVE;
4842 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4844 /* pipesrc and dspsize control the size that is scaled from,
4845 * which should always be the user's requested size.
4847 I915_WRITE(DSPSIZE(plane),
4848 ((mode->vdisplay - 1) << 16) |
4849 (mode->hdisplay - 1));
4850 I915_WRITE(DSPPOS(plane), 0);
4852 I915_WRITE(PIPECONF(pipe), pipeconf);
4853 POSTING_READ(PIPECONF(pipe));
4854 intel_enable_pipe(dev_priv, pipe, false);
4856 intel_wait_for_vblank(dev, pipe);
4858 I915_WRITE(DSPCNTR(plane), dspcntr);
4859 POSTING_READ(DSPCNTR(plane));
4861 ret = intel_pipe_set_base(crtc, x, y, fb);
4863 intel_update_watermarks(dev);
4869 * Initialize reference clocks when the driver loads
4871 void ironlake_init_pch_refclk(struct drm_device *dev)
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct drm_mode_config *mode_config = &dev->mode_config;
4875 struct intel_encoder *encoder;
4877 bool has_lvds = false;
4878 bool has_cpu_edp = false;
4879 bool has_pch_edp = false;
4880 bool has_panel = false;
4881 bool has_ck505 = false;
4882 bool can_ssc = false;
4884 /* We need to take the global config into account */
4885 list_for_each_entry(encoder, &mode_config->encoder_list,
4887 switch (encoder->type) {
4888 case INTEL_OUTPUT_LVDS:
4892 case INTEL_OUTPUT_EDP:
4894 if (intel_encoder_is_pch_edp(&encoder->base))
4902 if (HAS_PCH_IBX(dev)) {
4903 has_ck505 = dev_priv->display_clock_mode;
4904 can_ssc = has_ck505;
4910 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4911 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4914 /* Ironlake: try to setup display ref clock before DPLL
4915 * enabling. This is only under driver's control after
4916 * PCH B stepping, previous chipset stepping should be
4917 * ignoring this setting.
4919 temp = I915_READ(PCH_DREF_CONTROL);
4920 /* Always enable nonspread source */
4921 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4924 temp |= DREF_NONSPREAD_CK505_ENABLE;
4926 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4929 temp &= ~DREF_SSC_SOURCE_MASK;
4930 temp |= DREF_SSC_SOURCE_ENABLE;
4932 /* SSC must be turned on before enabling the CPU output */
4933 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4934 DRM_DEBUG_KMS("Using SSC on panel\n");
4935 temp |= DREF_SSC1_ENABLE;
4937 temp &= ~DREF_SSC1_ENABLE;
4939 /* Get SSC going before enabling the outputs */
4940 I915_WRITE(PCH_DREF_CONTROL, temp);
4941 POSTING_READ(PCH_DREF_CONTROL);
4944 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4946 /* Enable CPU source on CPU attached eDP */
4948 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4949 DRM_DEBUG_KMS("Using SSC on eDP\n");
4950 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4953 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4955 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4957 I915_WRITE(PCH_DREF_CONTROL, temp);
4958 POSTING_READ(PCH_DREF_CONTROL);
4961 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4963 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4965 /* Turn off CPU output */
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968 I915_WRITE(PCH_DREF_CONTROL, temp);
4969 POSTING_READ(PCH_DREF_CONTROL);
4972 /* Turn off the SSC source */
4973 temp &= ~DREF_SSC_SOURCE_MASK;
4974 temp |= DREF_SSC_SOURCE_DISABLE;
4977 temp &= ~ DREF_SSC1_ENABLE;
4979 I915_WRITE(PCH_DREF_CONTROL, temp);
4980 POSTING_READ(PCH_DREF_CONTROL);
4985 static int ironlake_get_refclk(struct drm_crtc *crtc)
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_encoder *encoder;
4990 struct intel_encoder *edp_encoder = NULL;
4991 int num_connectors = 0;
4992 bool is_lvds = false;
4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
4995 switch (encoder->type) {
4996 case INTEL_OUTPUT_LVDS:
4999 case INTEL_OUTPUT_EDP:
5000 edp_encoder = encoder;
5006 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008 dev_priv->lvds_ssc_freq);
5009 return dev_priv->lvds_ssc_freq * 1000;
5015 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5016 struct drm_display_mode *adjusted_mode,
5019 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021 int pipe = intel_crtc->pipe;
5024 val = I915_READ(PIPECONF(pipe));
5026 val &= ~PIPE_BPC_MASK;
5027 switch (intel_crtc->bpp) {
5041 /* Case prevented by intel_choose_pipe_bpp_dither. */
5045 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5047 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5049 val &= ~PIPECONF_INTERLACE_MASK;
5050 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5051 val |= PIPECONF_INTERLACED_ILK;
5053 val |= PIPECONF_PROGRESSIVE;
5055 I915_WRITE(PIPECONF(pipe), val);
5056 POSTING_READ(PIPECONF(pipe));
5059 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5060 struct drm_display_mode *adjusted_mode,
5063 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5068 val = I915_READ(PIPECONF(cpu_transcoder));
5070 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5072 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5074 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5075 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5076 val |= PIPECONF_INTERLACED_ILK;
5078 val |= PIPECONF_PROGRESSIVE;
5080 I915_WRITE(PIPECONF(cpu_transcoder), val);
5081 POSTING_READ(PIPECONF(cpu_transcoder));
5084 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5085 struct drm_display_mode *adjusted_mode,
5086 intel_clock_t *clock,
5087 bool *has_reduced_clock,
5088 intel_clock_t *reduced_clock)
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_encoder *intel_encoder;
5094 const intel_limit_t *limit;
5095 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5097 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5098 switch (intel_encoder->type) {
5099 case INTEL_OUTPUT_LVDS:
5102 case INTEL_OUTPUT_SDVO:
5103 case INTEL_OUTPUT_HDMI:
5105 if (intel_encoder->needs_tv_clock)
5108 case INTEL_OUTPUT_TVOUT:
5114 refclk = ironlake_get_refclk(crtc);
5117 * Returns a set of divisors for the desired target clock with the given
5118 * refclk, or FALSE. The returned values represent the clock equation:
5119 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5121 limit = intel_limit(crtc, refclk);
5122 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5127 if (is_lvds && dev_priv->lvds_downclock_avail) {
5129 * Ensure we match the reduced clock's P to the target clock.
5130 * If the clocks don't match, we can't switch the display clock
5131 * by using the FP0/FP1. In such case we will disable the LVDS
5132 * downclock feature.
5134 *has_reduced_clock = limit->find_pll(limit, crtc,
5135 dev_priv->lvds_downclock,
5141 if (is_sdvo && is_tv)
5142 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5147 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5152 temp = I915_READ(SOUTH_CHICKEN1);
5153 if (temp & FDI_BC_BIFURCATION_SELECT)
5156 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5157 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5159 temp |= FDI_BC_BIFURCATION_SELECT;
5160 DRM_DEBUG_KMS("enabling fdi C rx\n");
5161 I915_WRITE(SOUTH_CHICKEN1, temp);
5162 POSTING_READ(SOUTH_CHICKEN1);
5165 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5167 struct drm_device *dev = intel_crtc->base.dev;
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 struct intel_crtc *pipe_B_crtc =
5170 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5172 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5173 intel_crtc->pipe, intel_crtc->fdi_lanes);
5174 if (intel_crtc->fdi_lanes > 4) {
5175 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5176 intel_crtc->pipe, intel_crtc->fdi_lanes);
5177 /* Clamp lanes to avoid programming the hw with bogus values. */
5178 intel_crtc->fdi_lanes = 4;
5183 if (dev_priv->num_pipe == 2)
5186 switch (intel_crtc->pipe) {
5190 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5191 intel_crtc->fdi_lanes > 2) {
5192 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5193 intel_crtc->pipe, intel_crtc->fdi_lanes);
5194 /* Clamp lanes to avoid programming the hw with bogus values. */
5195 intel_crtc->fdi_lanes = 2;
5200 if (intel_crtc->fdi_lanes > 2)
5201 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5203 cpt_enable_fdi_bc_bifurcation(dev);
5207 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5208 if (intel_crtc->fdi_lanes > 2) {
5209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5210 intel_crtc->pipe, intel_crtc->fdi_lanes);
5211 /* Clamp lanes to avoid programming the hw with bogus values. */
5212 intel_crtc->fdi_lanes = 2;
5217 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5221 cpt_enable_fdi_bc_bifurcation(dev);
5229 static void ironlake_set_m_n(struct drm_crtc *crtc,
5230 struct drm_display_mode *mode,
5231 struct drm_display_mode *adjusted_mode)
5233 struct drm_device *dev = crtc->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5237 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5238 struct fdi_m_n m_n = {0};
5239 int target_clock, pixel_multiplier, lane, link_bw;
5240 bool is_dp = false, is_cpu_edp = false;
5242 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5243 switch (intel_encoder->type) {
5244 case INTEL_OUTPUT_DISPLAYPORT:
5247 case INTEL_OUTPUT_EDP:
5249 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5251 edp_encoder = intel_encoder;
5257 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5259 /* CPU eDP doesn't require FDI link, so just set DP M/N
5260 according to current link config */
5262 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5264 /* FDI is a binary signal running at ~2.7GHz, encoding
5265 * each output octet as 10 bits. The actual frequency
5266 * is stored as a divider into a 100MHz clock, and the
5267 * mode pixel clock is stored in units of 1KHz.
5268 * Hence the bw of each lane in terms of the mode signal
5271 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5274 /* [e]DP over FDI requires target mode clock instead of link clock. */
5276 target_clock = intel_edp_target_clock(edp_encoder, mode);
5278 target_clock = mode->clock;
5280 target_clock = adjusted_mode->clock;
5284 * Account for spread spectrum to avoid
5285 * oversubscribing the link. Max center spread
5286 * is 2.5%; use 5% for safety's sake.
5288 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5289 lane = bps / (link_bw * 8) + 1;
5292 intel_crtc->fdi_lanes = lane;
5294 if (pixel_multiplier > 1)
5295 link_bw *= pixel_multiplier;
5296 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5299 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5300 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5301 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5302 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5305 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5306 struct drm_display_mode *adjusted_mode,
5307 intel_clock_t *clock, u32 fp)
5309 struct drm_crtc *crtc = &intel_crtc->base;
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_encoder *intel_encoder;
5314 int factor, pixel_multiplier, num_connectors = 0;
5315 bool is_lvds = false, is_sdvo = false, is_tv = false;
5316 bool is_dp = false, is_cpu_edp = false;
5318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5319 switch (intel_encoder->type) {
5320 case INTEL_OUTPUT_LVDS:
5323 case INTEL_OUTPUT_SDVO:
5324 case INTEL_OUTPUT_HDMI:
5326 if (intel_encoder->needs_tv_clock)
5329 case INTEL_OUTPUT_TVOUT:
5332 case INTEL_OUTPUT_DISPLAYPORT:
5335 case INTEL_OUTPUT_EDP:
5337 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5345 /* Enable autotuning of the PLL clock (if permissible) */
5348 if ((intel_panel_use_ssc(dev_priv) &&
5349 dev_priv->lvds_ssc_freq == 100) ||
5350 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5352 } else if (is_sdvo && is_tv)
5355 if (clock->m < factor * clock->n)
5361 dpll |= DPLLB_MODE_LVDS;
5363 dpll |= DPLLB_MODE_DAC_SERIAL;
5365 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5366 if (pixel_multiplier > 1) {
5367 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5369 dpll |= DPLL_DVO_HIGH_SPEED;
5371 if (is_dp && !is_cpu_edp)
5372 dpll |= DPLL_DVO_HIGH_SPEED;
5374 /* compute bitmask from p1 value */
5375 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5377 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5379 switch (clock->p2) {
5381 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5384 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5387 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5390 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5394 if (is_sdvo && is_tv)
5395 dpll |= PLL_REF_INPUT_TVCLKINBC;
5397 /* XXX: just matching BIOS for now */
5398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5400 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5401 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5403 dpll |= PLL_REF_INPUT_DREFCLK;
5408 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5409 struct drm_display_mode *mode,
5410 struct drm_display_mode *adjusted_mode,
5412 struct drm_framebuffer *fb)
5414 struct drm_device *dev = crtc->dev;
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 int pipe = intel_crtc->pipe;
5418 int plane = intel_crtc->plane;
5419 int num_connectors = 0;
5420 intel_clock_t clock, reduced_clock;
5421 u32 dpll, fp = 0, fp2 = 0;
5422 bool ok, has_reduced_clock = false;
5423 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5424 struct intel_encoder *encoder;
5427 bool dither, fdi_config_ok;
5429 for_each_encoder_on_crtc(dev, crtc, encoder) {
5430 switch (encoder->type) {
5431 case INTEL_OUTPUT_LVDS:
5434 case INTEL_OUTPUT_DISPLAYPORT:
5437 case INTEL_OUTPUT_EDP:
5439 if (!intel_encoder_is_pch_edp(&encoder->base))
5447 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5448 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5450 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5451 &has_reduced_clock, &reduced_clock);
5453 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5457 /* Ensure that the cursor is valid for the new mode before changing... */
5458 intel_crtc_update_cursor(crtc, true);
5460 /* determine panel color depth */
5461 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5463 if (is_lvds && dev_priv->lvds_dither)
5466 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5467 if (has_reduced_clock)
5468 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5471 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5473 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5474 drm_mode_debug_printmodeline(mode);
5476 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5478 struct intel_pch_pll *pll;
5480 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5482 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5487 intel_put_pch_pll(intel_crtc);
5489 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5490 * This is an exception to the general rule that mode_set doesn't turn
5494 temp = I915_READ(PCH_LVDS);
5495 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5496 if (HAS_PCH_CPT(dev)) {
5497 temp &= ~PORT_TRANS_SEL_MASK;
5498 temp |= PORT_TRANS_SEL_CPT(pipe);
5501 temp |= LVDS_PIPEB_SELECT;
5503 temp &= ~LVDS_PIPEB_SELECT;
5506 /* set the corresponsding LVDS_BORDER bit */
5507 temp |= dev_priv->lvds_border_bits;
5508 /* Set the B0-B3 data pairs corresponding to whether we're going to
5509 * set the DPLLs for dual-channel mode or not.
5512 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5514 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5516 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5517 * appropriately here, but we need to look more thoroughly into how
5518 * panels behave in the two modes.
5520 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5521 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5522 temp |= LVDS_HSYNC_POLARITY;
5523 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5524 temp |= LVDS_VSYNC_POLARITY;
5525 I915_WRITE(PCH_LVDS, temp);
5528 if (is_dp && !is_cpu_edp) {
5529 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5531 /* For non-DP output, clear any trans DP clock recovery setting.*/
5532 I915_WRITE(TRANSDATA_M1(pipe), 0);
5533 I915_WRITE(TRANSDATA_N1(pipe), 0);
5534 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5535 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5538 if (intel_crtc->pch_pll) {
5539 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5541 /* Wait for the clocks to stabilize. */
5542 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5545 /* The pixel multiplier can only be updated once the
5546 * DPLL is enabled and the clocks are stable.
5548 * So write it again.
5550 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5553 intel_crtc->lowfreq_avail = false;
5554 if (intel_crtc->pch_pll) {
5555 if (is_lvds && has_reduced_clock && i915_powersave) {
5556 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5557 intel_crtc->lowfreq_avail = true;
5559 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5563 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5565 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5566 * ironlake_check_fdi_lanes. */
5567 ironlake_set_m_n(crtc, mode, adjusted_mode);
5569 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5572 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5574 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5576 intel_wait_for_vblank(dev, pipe);
5578 /* Set up the display plane register */
5579 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5580 POSTING_READ(DSPCNTR(plane));
5582 ret = intel_pipe_set_base(crtc, x, y, fb);
5584 intel_update_watermarks(dev);
5586 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5588 return fdi_config_ok ? ret : -EINVAL;
5591 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5592 struct drm_display_mode *mode,
5593 struct drm_display_mode *adjusted_mode,
5595 struct drm_framebuffer *fb)
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
5601 int plane = intel_crtc->plane;
5602 int num_connectors = 0;
5603 intel_clock_t clock, reduced_clock;
5604 u32 dpll = 0, fp = 0, fp2 = 0;
5605 bool ok, has_reduced_clock = false;
5606 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5607 struct intel_encoder *encoder;
5612 for_each_encoder_on_crtc(dev, crtc, encoder) {
5613 switch (encoder->type) {
5614 case INTEL_OUTPUT_LVDS:
5617 case INTEL_OUTPUT_DISPLAYPORT:
5620 case INTEL_OUTPUT_EDP:
5622 if (!intel_encoder_is_pch_edp(&encoder->base))
5631 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5633 intel_crtc->cpu_transcoder = pipe;
5635 /* We are not sure yet this won't happen. */
5636 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5637 INTEL_PCH_TYPE(dev));
5639 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5640 num_connectors, pipe_name(pipe));
5642 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5643 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5645 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5647 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5651 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5655 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5660 /* Ensure that the cursor is valid for the new mode before changing... */
5661 intel_crtc_update_cursor(crtc, true);
5663 /* determine panel color depth */
5664 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5666 if (is_lvds && dev_priv->lvds_dither)
5669 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5670 drm_mode_debug_printmodeline(mode);
5672 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5673 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5674 if (has_reduced_clock)
5675 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5678 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5681 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5682 * own on pre-Haswell/LPT generation */
5684 struct intel_pch_pll *pll;
5686 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5688 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5693 intel_put_pch_pll(intel_crtc);
5695 /* The LVDS pin pair needs to be on before the DPLLs are
5696 * enabled. This is an exception to the general rule that
5697 * mode_set doesn't turn things on.
5700 temp = I915_READ(PCH_LVDS);
5701 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5702 if (HAS_PCH_CPT(dev)) {
5703 temp &= ~PORT_TRANS_SEL_MASK;
5704 temp |= PORT_TRANS_SEL_CPT(pipe);
5707 temp |= LVDS_PIPEB_SELECT;
5709 temp &= ~LVDS_PIPEB_SELECT;
5712 /* set the corresponsding LVDS_BORDER bit */
5713 temp |= dev_priv->lvds_border_bits;
5714 /* Set the B0-B3 data pairs corresponding to whether
5715 * we're going to set the DPLLs for dual-channel mode or
5719 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5721 temp &= ~(LVDS_B0B3_POWER_UP |
5722 LVDS_CLKB_POWER_UP);
5724 /* It would be nice to set 24 vs 18-bit mode
5725 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5726 * look more thoroughly into how panels behave in the
5729 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5730 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5731 temp |= LVDS_HSYNC_POLARITY;
5732 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5733 temp |= LVDS_VSYNC_POLARITY;
5734 I915_WRITE(PCH_LVDS, temp);
5738 if (is_dp && !is_cpu_edp) {
5739 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5741 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5742 /* For non-DP output, clear any trans DP clock recovery
5744 I915_WRITE(TRANSDATA_M1(pipe), 0);
5745 I915_WRITE(TRANSDATA_N1(pipe), 0);
5746 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5747 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5751 intel_crtc->lowfreq_avail = false;
5752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5753 if (intel_crtc->pch_pll) {
5754 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5756 /* Wait for the clocks to stabilize. */
5757 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5760 /* The pixel multiplier can only be updated once the
5761 * DPLL is enabled and the clocks are stable.
5763 * So write it again.
5765 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768 if (intel_crtc->pch_pll) {
5769 if (is_lvds && has_reduced_clock && i915_powersave) {
5770 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5771 intel_crtc->lowfreq_avail = true;
5773 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5778 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5780 if (!is_dp || is_cpu_edp)
5781 ironlake_set_m_n(crtc, mode, adjusted_mode);
5783 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5785 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5787 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5789 /* Set up the display plane register */
5790 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5791 POSTING_READ(DSPCNTR(plane));
5793 ret = intel_pipe_set_base(crtc, x, y, fb);
5795 intel_update_watermarks(dev);
5797 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5802 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5803 struct drm_display_mode *mode,
5804 struct drm_display_mode *adjusted_mode,
5806 struct drm_framebuffer *fb)
5808 struct drm_device *dev = crtc->dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 struct drm_encoder_helper_funcs *encoder_funcs;
5811 struct intel_encoder *encoder;
5812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813 int pipe = intel_crtc->pipe;
5816 drm_vblank_pre_modeset(dev, pipe);
5818 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5820 drm_vblank_post_modeset(dev, pipe);
5825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5826 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827 encoder->base.base.id,
5828 drm_get_encoder_name(&encoder->base),
5829 mode->base.id, mode->name);
5830 encoder_funcs = encoder->base.helper_private;
5831 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5837 static bool intel_eld_uptodate(struct drm_connector *connector,
5838 int reg_eldv, uint32_t bits_eldv,
5839 int reg_elda, uint32_t bits_elda,
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5846 i = I915_READ(reg_eldv);
5855 i = I915_READ(reg_elda);
5857 I915_WRITE(reg_elda, i);
5859 for (i = 0; i < eld[2]; i++)
5860 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5866 static void g4x_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5875 i = I915_READ(G4X_AUD_VID_DID);
5877 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878 eldv = G4X_ELDV_DEVCL_DEVBLC;
5880 eldv = G4X_ELDV_DEVCTG;
5882 if (intel_eld_uptodate(connector,
5883 G4X_AUD_CNTL_ST, eldv,
5884 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885 G4X_HDMIW_HDMIEDID))
5888 i = I915_READ(G4X_AUD_CNTL_ST);
5889 i &= ~(eldv | G4X_ELD_ADDR);
5890 len = (i >> 9) & 0x1f; /* ELD buffer size */
5891 I915_WRITE(G4X_AUD_CNTL_ST, i);
5896 len = min_t(uint8_t, eld[2], len);
5897 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898 for (i = 0; i < len; i++)
5899 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5903 I915_WRITE(G4X_AUD_CNTL_ST, i);
5906 static void haswell_write_eld(struct drm_connector *connector,
5907 struct drm_crtc *crtc)
5909 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910 uint8_t *eld = connector->eld;
5911 struct drm_device *dev = crtc->dev;
5915 int pipe = to_intel_crtc(crtc)->pipe;
5918 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5919 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5920 int aud_config = HSW_AUD_CFG(pipe);
5921 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5924 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5926 /* Audio output enable */
5927 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5928 tmp = I915_READ(aud_cntrl_st2);
5929 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5930 I915_WRITE(aud_cntrl_st2, tmp);
5932 /* Wait for 1 vertical blank */
5933 intel_wait_for_vblank(dev, pipe);
5935 /* Set ELD valid state */
5936 tmp = I915_READ(aud_cntrl_st2);
5937 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5938 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5939 I915_WRITE(aud_cntrl_st2, tmp);
5940 tmp = I915_READ(aud_cntrl_st2);
5941 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5943 /* Enable HDMI mode */
5944 tmp = I915_READ(aud_config);
5945 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5946 /* clear N_programing_enable and N_value_index */
5947 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5948 I915_WRITE(aud_config, tmp);
5950 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5952 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5954 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5955 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5956 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5957 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5959 I915_WRITE(aud_config, 0);
5961 if (intel_eld_uptodate(connector,
5962 aud_cntrl_st2, eldv,
5963 aud_cntl_st, IBX_ELD_ADDRESS,
5967 i = I915_READ(aud_cntrl_st2);
5969 I915_WRITE(aud_cntrl_st2, i);
5974 i = I915_READ(aud_cntl_st);
5975 i &= ~IBX_ELD_ADDRESS;
5976 I915_WRITE(aud_cntl_st, i);
5977 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5978 DRM_DEBUG_DRIVER("port num:%d\n", i);
5980 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5981 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5982 for (i = 0; i < len; i++)
5983 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5985 i = I915_READ(aud_cntrl_st2);
5987 I915_WRITE(aud_cntrl_st2, i);
5991 static void ironlake_write_eld(struct drm_connector *connector,
5992 struct drm_crtc *crtc)
5994 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5995 uint8_t *eld = connector->eld;
6003 int pipe = to_intel_crtc(crtc)->pipe;
6005 if (HAS_PCH_IBX(connector->dev)) {
6006 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6007 aud_config = IBX_AUD_CFG(pipe);
6008 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6009 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6011 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6012 aud_config = CPT_AUD_CFG(pipe);
6013 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6014 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6017 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6019 i = I915_READ(aud_cntl_st);
6020 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6022 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6023 /* operate blindly on all ports */
6024 eldv = IBX_ELD_VALIDB;
6025 eldv |= IBX_ELD_VALIDB << 4;
6026 eldv |= IBX_ELD_VALIDB << 8;
6028 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6029 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6033 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6034 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6035 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6037 I915_WRITE(aud_config, 0);
6039 if (intel_eld_uptodate(connector,
6040 aud_cntrl_st2, eldv,
6041 aud_cntl_st, IBX_ELD_ADDRESS,
6045 i = I915_READ(aud_cntrl_st2);
6047 I915_WRITE(aud_cntrl_st2, i);
6052 i = I915_READ(aud_cntl_st);
6053 i &= ~IBX_ELD_ADDRESS;
6054 I915_WRITE(aud_cntl_st, i);
6056 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6057 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6058 for (i = 0; i < len; i++)
6059 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6061 i = I915_READ(aud_cntrl_st2);
6063 I915_WRITE(aud_cntrl_st2, i);
6066 void intel_write_eld(struct drm_encoder *encoder,
6067 struct drm_display_mode *mode)
6069 struct drm_crtc *crtc = encoder->crtc;
6070 struct drm_connector *connector;
6071 struct drm_device *dev = encoder->dev;
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6074 connector = drm_select_eld(encoder, mode);
6078 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6080 drm_get_connector_name(connector),
6081 connector->encoder->base.id,
6082 drm_get_encoder_name(connector->encoder));
6084 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6086 if (dev_priv->display.write_eld)
6087 dev_priv->display.write_eld(connector, crtc);
6090 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6091 void intel_crtc_load_lut(struct drm_crtc *crtc)
6093 struct drm_device *dev = crtc->dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 int palreg = PALETTE(intel_crtc->pipe);
6099 /* The clocks have to be on to load the palette. */
6100 if (!crtc->enabled || !intel_crtc->active)
6103 /* use legacy palette for Ironlake */
6104 if (HAS_PCH_SPLIT(dev))
6105 palreg = LGC_PALETTE(intel_crtc->pipe);
6107 for (i = 0; i < 256; i++) {
6108 I915_WRITE(palreg + 4 * i,
6109 (intel_crtc->lut_r[i] << 16) |
6110 (intel_crtc->lut_g[i] << 8) |
6111 intel_crtc->lut_b[i]);
6115 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6117 struct drm_device *dev = crtc->dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 bool visible = base != 0;
6123 if (intel_crtc->cursor_visible == visible)
6126 cntl = I915_READ(_CURACNTR);
6128 /* On these chipsets we can only modify the base whilst
6129 * the cursor is disabled.
6131 I915_WRITE(_CURABASE, base);
6133 cntl &= ~(CURSOR_FORMAT_MASK);
6134 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6135 cntl |= CURSOR_ENABLE |
6136 CURSOR_GAMMA_ENABLE |
6139 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6140 I915_WRITE(_CURACNTR, cntl);
6142 intel_crtc->cursor_visible = visible;
6145 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 int pipe = intel_crtc->pipe;
6151 bool visible = base != 0;
6153 if (intel_crtc->cursor_visible != visible) {
6154 uint32_t cntl = I915_READ(CURCNTR(pipe));
6156 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6157 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6158 cntl |= pipe << 28; /* Connect to correct pipe */
6160 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6161 cntl |= CURSOR_MODE_DISABLE;
6163 I915_WRITE(CURCNTR(pipe), cntl);
6165 intel_crtc->cursor_visible = visible;
6167 /* and commit changes on next vblank */
6168 I915_WRITE(CURBASE(pipe), base);
6171 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6173 struct drm_device *dev = crtc->dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6176 int pipe = intel_crtc->pipe;
6177 bool visible = base != 0;
6179 if (intel_crtc->cursor_visible != visible) {
6180 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6182 cntl &= ~CURSOR_MODE;
6183 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6185 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6186 cntl |= CURSOR_MODE_DISABLE;
6188 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6190 intel_crtc->cursor_visible = visible;
6192 /* and commit changes on next vblank */
6193 I915_WRITE(CURBASE_IVB(pipe), base);
6196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6197 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6200 struct drm_device *dev = crtc->dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 int pipe = intel_crtc->pipe;
6204 int x = intel_crtc->cursor_x;
6205 int y = intel_crtc->cursor_y;
6211 if (on && crtc->enabled && crtc->fb) {
6212 base = intel_crtc->cursor_addr;
6213 if (x > (int) crtc->fb->width)
6216 if (y > (int) crtc->fb->height)
6222 if (x + intel_crtc->cursor_width < 0)
6225 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6228 pos |= x << CURSOR_X_SHIFT;
6231 if (y + intel_crtc->cursor_height < 0)
6234 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6237 pos |= y << CURSOR_Y_SHIFT;
6239 visible = base != 0;
6240 if (!visible && !intel_crtc->cursor_visible)
6243 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6244 I915_WRITE(CURPOS_IVB(pipe), pos);
6245 ivb_update_cursor(crtc, base);
6247 I915_WRITE(CURPOS(pipe), pos);
6248 if (IS_845G(dev) || IS_I865G(dev))
6249 i845_update_cursor(crtc, base);
6251 i9xx_update_cursor(crtc, base);
6255 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6256 struct drm_file *file,
6258 uint32_t width, uint32_t height)
6260 struct drm_device *dev = crtc->dev;
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6263 struct drm_i915_gem_object *obj;
6267 /* if we want to turn off the cursor ignore width and height */
6269 DRM_DEBUG_KMS("cursor off\n");
6272 mutex_lock(&dev->struct_mutex);
6276 /* Currently we only support 64x64 cursors */
6277 if (width != 64 || height != 64) {
6278 DRM_ERROR("we currently only support 64x64 cursors\n");
6282 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6283 if (&obj->base == NULL)
6286 if (obj->base.size < width * height * 4) {
6287 DRM_ERROR("buffer is to small\n");
6292 /* we only need to pin inside GTT if cursor is non-phy */
6293 mutex_lock(&dev->struct_mutex);
6294 if (!dev_priv->info->cursor_needs_physical) {
6295 if (obj->tiling_mode) {
6296 DRM_ERROR("cursor cannot be tiled\n");
6301 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6303 DRM_ERROR("failed to move cursor bo into the GTT\n");
6307 ret = i915_gem_object_put_fence(obj);
6309 DRM_ERROR("failed to release fence for cursor");
6313 addr = obj->gtt_offset;
6315 int align = IS_I830(dev) ? 16 * 1024 : 256;
6316 ret = i915_gem_attach_phys_object(dev, obj,
6317 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6320 DRM_ERROR("failed to attach phys object\n");
6323 addr = obj->phys_obj->handle->busaddr;
6327 I915_WRITE(CURSIZE, (height << 12) | width);
6330 if (intel_crtc->cursor_bo) {
6331 if (dev_priv->info->cursor_needs_physical) {
6332 if (intel_crtc->cursor_bo != obj)
6333 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6335 i915_gem_object_unpin(intel_crtc->cursor_bo);
6336 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6339 mutex_unlock(&dev->struct_mutex);
6341 intel_crtc->cursor_addr = addr;
6342 intel_crtc->cursor_bo = obj;
6343 intel_crtc->cursor_width = width;
6344 intel_crtc->cursor_height = height;
6346 intel_crtc_update_cursor(crtc, true);
6350 i915_gem_object_unpin(obj);
6352 mutex_unlock(&dev->struct_mutex);
6354 drm_gem_object_unreference_unlocked(&obj->base);
6358 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 intel_crtc->cursor_x = x;
6363 intel_crtc->cursor_y = y;
6365 intel_crtc_update_cursor(crtc, true);
6370 /** Sets the color ramps on behalf of RandR */
6371 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6372 u16 blue, int regno)
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376 intel_crtc->lut_r[regno] = red >> 8;
6377 intel_crtc->lut_g[regno] = green >> 8;
6378 intel_crtc->lut_b[regno] = blue >> 8;
6381 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6382 u16 *blue, int regno)
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386 *red = intel_crtc->lut_r[regno] << 8;
6387 *green = intel_crtc->lut_g[regno] << 8;
6388 *blue = intel_crtc->lut_b[regno] << 8;
6391 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6392 u16 *blue, uint32_t start, uint32_t size)
6394 int end = (start + size > 256) ? 256 : start + size, i;
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397 for (i = start; i < end; i++) {
6398 intel_crtc->lut_r[i] = red[i] >> 8;
6399 intel_crtc->lut_g[i] = green[i] >> 8;
6400 intel_crtc->lut_b[i] = blue[i] >> 8;
6403 intel_crtc_load_lut(crtc);
6407 * Get a pipe with a simple mode set on it for doing load-based monitor
6410 * It will be up to the load-detect code to adjust the pipe as appropriate for
6411 * its requirements. The pipe will be connected to no other encoders.
6413 * Currently this code will only succeed if there is a pipe with no encoders
6414 * configured for it. In the future, it could choose to temporarily disable
6415 * some outputs to free up a pipe for its use.
6417 * \return crtc, or NULL if no pipes are available.
6420 /* VESA 640x480x72Hz mode to set on the pipe */
6421 static struct drm_display_mode load_detect_mode = {
6422 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6423 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6426 static struct drm_framebuffer *
6427 intel_framebuffer_create(struct drm_device *dev,
6428 struct drm_mode_fb_cmd2 *mode_cmd,
6429 struct drm_i915_gem_object *obj)
6431 struct intel_framebuffer *intel_fb;
6434 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6436 drm_gem_object_unreference_unlocked(&obj->base);
6437 return ERR_PTR(-ENOMEM);
6440 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6442 drm_gem_object_unreference_unlocked(&obj->base);
6444 return ERR_PTR(ret);
6447 return &intel_fb->base;
6451 intel_framebuffer_pitch_for_width(int width, int bpp)
6453 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6454 return ALIGN(pitch, 64);
6458 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6460 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6461 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6464 static struct drm_framebuffer *
6465 intel_framebuffer_create_for_mode(struct drm_device *dev,
6466 struct drm_display_mode *mode,
6469 struct drm_i915_gem_object *obj;
6470 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6472 obj = i915_gem_alloc_object(dev,
6473 intel_framebuffer_size_for_mode(mode, bpp));
6475 return ERR_PTR(-ENOMEM);
6477 mode_cmd.width = mode->hdisplay;
6478 mode_cmd.height = mode->vdisplay;
6479 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6481 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6483 return intel_framebuffer_create(dev, &mode_cmd, obj);
6486 static struct drm_framebuffer *
6487 mode_fits_in_fbdev(struct drm_device *dev,
6488 struct drm_display_mode *mode)
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct drm_i915_gem_object *obj;
6492 struct drm_framebuffer *fb;
6494 if (dev_priv->fbdev == NULL)
6497 obj = dev_priv->fbdev->ifb.obj;
6501 fb = &dev_priv->fbdev->ifb.base;
6502 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6503 fb->bits_per_pixel))
6506 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6512 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6513 struct drm_display_mode *mode,
6514 struct intel_load_detect_pipe *old)
6516 struct intel_crtc *intel_crtc;
6517 struct intel_encoder *intel_encoder =
6518 intel_attached_encoder(connector);
6519 struct drm_crtc *possible_crtc;
6520 struct drm_encoder *encoder = &intel_encoder->base;
6521 struct drm_crtc *crtc = NULL;
6522 struct drm_device *dev = encoder->dev;
6523 struct drm_framebuffer *fb;
6526 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6527 connector->base.id, drm_get_connector_name(connector),
6528 encoder->base.id, drm_get_encoder_name(encoder));
6531 * Algorithm gets a little messy:
6533 * - if the connector already has an assigned crtc, use it (but make
6534 * sure it's on first)
6536 * - try to find the first unused crtc that can drive this connector,
6537 * and use that if we find one
6540 /* See if we already have a CRTC for this connector */
6541 if (encoder->crtc) {
6542 crtc = encoder->crtc;
6544 old->dpms_mode = connector->dpms;
6545 old->load_detect_temp = false;
6547 /* Make sure the crtc and connector are running */
6548 if (connector->dpms != DRM_MODE_DPMS_ON)
6549 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6554 /* Find an unused one (if possible) */
6555 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6557 if (!(encoder->possible_crtcs & (1 << i)))
6559 if (!possible_crtc->enabled) {
6560 crtc = possible_crtc;
6566 * If we didn't find an unused CRTC, don't use any.
6569 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6573 intel_encoder->new_crtc = to_intel_crtc(crtc);
6574 to_intel_connector(connector)->new_encoder = intel_encoder;
6576 intel_crtc = to_intel_crtc(crtc);
6577 old->dpms_mode = connector->dpms;
6578 old->load_detect_temp = true;
6579 old->release_fb = NULL;
6582 mode = &load_detect_mode;
6584 /* We need a framebuffer large enough to accommodate all accesses
6585 * that the plane may generate whilst we perform load detection.
6586 * We can not rely on the fbcon either being present (we get called
6587 * during its initialisation to detect all boot displays, or it may
6588 * not even exist) or that it is large enough to satisfy the
6591 fb = mode_fits_in_fbdev(dev, mode);
6593 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6594 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6595 old->release_fb = fb;
6597 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6599 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6603 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6604 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6605 if (old->release_fb)
6606 old->release_fb->funcs->destroy(old->release_fb);
6610 /* let the connector get through one full cycle before testing */
6611 intel_wait_for_vblank(dev, intel_crtc->pipe);
6615 void intel_release_load_detect_pipe(struct drm_connector *connector,
6616 struct intel_load_detect_pipe *old)
6618 struct intel_encoder *intel_encoder =
6619 intel_attached_encoder(connector);
6620 struct drm_encoder *encoder = &intel_encoder->base;
6622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6623 connector->base.id, drm_get_connector_name(connector),
6624 encoder->base.id, drm_get_encoder_name(encoder));
6626 if (old->load_detect_temp) {
6627 struct drm_crtc *crtc = encoder->crtc;
6629 to_intel_connector(connector)->new_encoder = NULL;
6630 intel_encoder->new_crtc = NULL;
6631 intel_set_mode(crtc, NULL, 0, 0, NULL);
6633 if (old->release_fb)
6634 old->release_fb->funcs->destroy(old->release_fb);
6639 /* Switch crtc and encoder back off if necessary */
6640 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6641 connector->funcs->dpms(connector, old->dpms_mode);
6644 /* Returns the clock of the currently programmed mode of the given pipe. */
6645 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 int pipe = intel_crtc->pipe;
6650 u32 dpll = I915_READ(DPLL(pipe));
6652 intel_clock_t clock;
6654 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6655 fp = I915_READ(FP0(pipe));
6657 fp = I915_READ(FP1(pipe));
6659 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6660 if (IS_PINEVIEW(dev)) {
6661 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6662 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6664 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6665 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6668 if (!IS_GEN2(dev)) {
6669 if (IS_PINEVIEW(dev))
6670 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6671 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6673 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6674 DPLL_FPA01_P1_POST_DIV_SHIFT);
6676 switch (dpll & DPLL_MODE_MASK) {
6677 case DPLLB_MODE_DAC_SERIAL:
6678 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6681 case DPLLB_MODE_LVDS:
6682 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6686 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6687 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6691 /* XXX: Handle the 100Mhz refclk */
6692 intel_clock(dev, 96000, &clock);
6694 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6697 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6698 DPLL_FPA01_P1_POST_DIV_SHIFT);
6701 if ((dpll & PLL_REF_INPUT_MASK) ==
6702 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6703 /* XXX: might not be 66MHz */
6704 intel_clock(dev, 66000, &clock);
6706 intel_clock(dev, 48000, &clock);
6708 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6711 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6712 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6714 if (dpll & PLL_P2_DIVIDE_BY_4)
6719 intel_clock(dev, 48000, &clock);
6723 /* XXX: It would be nice to validate the clocks, but we can't reuse
6724 * i830PllIsValid() because it relies on the xf86_config connector
6725 * configuration being accurate, which it isn't necessarily.
6731 /** Returns the currently programmed mode of the given pipe. */
6732 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6733 struct drm_crtc *crtc)
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6738 struct drm_display_mode *mode;
6739 int htot = I915_READ(HTOTAL(cpu_transcoder));
6740 int hsync = I915_READ(HSYNC(cpu_transcoder));
6741 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6742 int vsync = I915_READ(VSYNC(cpu_transcoder));
6744 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6748 mode->clock = intel_crtc_clock_get(dev, crtc);
6749 mode->hdisplay = (htot & 0xffff) + 1;
6750 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6751 mode->hsync_start = (hsync & 0xffff) + 1;
6752 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6753 mode->vdisplay = (vtot & 0xffff) + 1;
6754 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6755 mode->vsync_start = (vsync & 0xffff) + 1;
6756 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6758 drm_mode_set_name(mode);
6763 static void intel_increase_pllclock(struct drm_crtc *crtc)
6765 struct drm_device *dev = crtc->dev;
6766 drm_i915_private_t *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6768 int pipe = intel_crtc->pipe;
6769 int dpll_reg = DPLL(pipe);
6772 if (HAS_PCH_SPLIT(dev))
6775 if (!dev_priv->lvds_downclock_avail)
6778 dpll = I915_READ(dpll_reg);
6779 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6780 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6782 assert_panel_unlocked(dev_priv, pipe);
6784 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6785 I915_WRITE(dpll_reg, dpll);
6786 intel_wait_for_vblank(dev, pipe);
6788 dpll = I915_READ(dpll_reg);
6789 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6790 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6796 struct drm_device *dev = crtc->dev;
6797 drm_i915_private_t *dev_priv = dev->dev_private;
6798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800 if (HAS_PCH_SPLIT(dev))
6803 if (!dev_priv->lvds_downclock_avail)
6807 * Since this is called by a timer, we should never get here in
6810 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6811 int pipe = intel_crtc->pipe;
6812 int dpll_reg = DPLL(pipe);
6815 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6817 assert_panel_unlocked(dev_priv, pipe);
6819 dpll = I915_READ(dpll_reg);
6820 dpll |= DISPLAY_RATE_SELECT_FPA1;
6821 I915_WRITE(dpll_reg, dpll);
6822 intel_wait_for_vblank(dev, pipe);
6823 dpll = I915_READ(dpll_reg);
6824 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6825 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6830 void intel_mark_busy(struct drm_device *dev)
6832 i915_update_gfx_val(dev->dev_private);
6835 void intel_mark_idle(struct drm_device *dev)
6839 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6841 struct drm_device *dev = obj->base.dev;
6842 struct drm_crtc *crtc;
6844 if (!i915_powersave)
6847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6851 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6852 intel_increase_pllclock(crtc);
6856 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6858 struct drm_device *dev = obj->base.dev;
6859 struct drm_crtc *crtc;
6861 if (!i915_powersave)
6864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6868 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6869 intel_decrease_pllclock(crtc);
6873 static void intel_crtc_destroy(struct drm_crtc *crtc)
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 struct drm_device *dev = crtc->dev;
6877 struct intel_unpin_work *work;
6878 unsigned long flags;
6880 spin_lock_irqsave(&dev->event_lock, flags);
6881 work = intel_crtc->unpin_work;
6882 intel_crtc->unpin_work = NULL;
6883 spin_unlock_irqrestore(&dev->event_lock, flags);
6886 cancel_work_sync(&work->work);
6890 drm_crtc_cleanup(crtc);
6895 static void intel_unpin_work_fn(struct work_struct *__work)
6897 struct intel_unpin_work *work =
6898 container_of(__work, struct intel_unpin_work, work);
6900 mutex_lock(&work->dev->struct_mutex);
6901 intel_unpin_fb_obj(work->old_fb_obj);
6902 drm_gem_object_unreference(&work->pending_flip_obj->base);
6903 drm_gem_object_unreference(&work->old_fb_obj->base);
6905 intel_update_fbc(work->dev);
6906 mutex_unlock(&work->dev->struct_mutex);
6910 static void do_intel_finish_page_flip(struct drm_device *dev,
6911 struct drm_crtc *crtc)
6913 drm_i915_private_t *dev_priv = dev->dev_private;
6914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915 struct intel_unpin_work *work;
6916 struct drm_i915_gem_object *obj;
6917 struct drm_pending_vblank_event *e;
6918 struct timeval tvbl;
6919 unsigned long flags;
6921 /* Ignore early vblank irqs */
6922 if (intel_crtc == NULL)
6925 spin_lock_irqsave(&dev->event_lock, flags);
6926 work = intel_crtc->unpin_work;
6927 if (work == NULL || !work->pending) {
6928 spin_unlock_irqrestore(&dev->event_lock, flags);
6932 intel_crtc->unpin_work = NULL;
6936 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6938 e->event.tv_sec = tvbl.tv_sec;
6939 e->event.tv_usec = tvbl.tv_usec;
6941 list_add_tail(&e->base.link,
6942 &e->base.file_priv->event_list);
6943 wake_up_interruptible(&e->base.file_priv->event_wait);
6946 drm_vblank_put(dev, intel_crtc->pipe);
6948 spin_unlock_irqrestore(&dev->event_lock, flags);
6950 obj = work->old_fb_obj;
6952 atomic_clear_mask(1 << intel_crtc->plane,
6953 &obj->pending_flip.counter);
6955 wake_up(&dev_priv->pending_flip_queue);
6956 schedule_work(&work->work);
6958 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6961 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6963 drm_i915_private_t *dev_priv = dev->dev_private;
6964 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6966 do_intel_finish_page_flip(dev, crtc);
6969 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6974 do_intel_finish_page_flip(dev, crtc);
6977 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6979 drm_i915_private_t *dev_priv = dev->dev_private;
6980 struct intel_crtc *intel_crtc =
6981 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6982 unsigned long flags;
6984 spin_lock_irqsave(&dev->event_lock, flags);
6985 if (intel_crtc->unpin_work) {
6986 if ((++intel_crtc->unpin_work->pending) > 1)
6987 DRM_ERROR("Prepared flip multiple times\n");
6989 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6991 spin_unlock_irqrestore(&dev->event_lock, flags);
6994 static int intel_gen2_queue_flip(struct drm_device *dev,
6995 struct drm_crtc *crtc,
6996 struct drm_framebuffer *fb,
6997 struct drm_i915_gem_object *obj)
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7005 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7009 ret = intel_ring_begin(ring, 6);
7013 /* Can't queue multiple flips, so wait for the previous
7014 * one to finish before executing the next.
7016 if (intel_crtc->plane)
7017 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7019 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7020 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7021 intel_ring_emit(ring, MI_NOOP);
7022 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7023 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7024 intel_ring_emit(ring, fb->pitches[0]);
7025 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7026 intel_ring_emit(ring, 0); /* aux display base address, unused */
7027 intel_ring_advance(ring);
7031 intel_unpin_fb_obj(obj);
7036 static int intel_gen3_queue_flip(struct drm_device *dev,
7037 struct drm_crtc *crtc,
7038 struct drm_framebuffer *fb,
7039 struct drm_i915_gem_object *obj)
7041 struct drm_i915_private *dev_priv = dev->dev_private;
7042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7044 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7047 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7051 ret = intel_ring_begin(ring, 6);
7055 if (intel_crtc->plane)
7056 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7058 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7059 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7060 intel_ring_emit(ring, MI_NOOP);
7061 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7063 intel_ring_emit(ring, fb->pitches[0]);
7064 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7065 intel_ring_emit(ring, MI_NOOP);
7067 intel_ring_advance(ring);
7071 intel_unpin_fb_obj(obj);
7076 static int intel_gen4_queue_flip(struct drm_device *dev,
7077 struct drm_crtc *crtc,
7078 struct drm_framebuffer *fb,
7079 struct drm_i915_gem_object *obj)
7081 struct drm_i915_private *dev_priv = dev->dev_private;
7082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7083 uint32_t pf, pipesrc;
7084 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7087 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7091 ret = intel_ring_begin(ring, 4);
7095 /* i965+ uses the linear or tiled offsets from the
7096 * Display Registers (which do not change across a page-flip)
7097 * so we need only reprogram the base address.
7099 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7100 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7101 intel_ring_emit(ring, fb->pitches[0]);
7102 intel_ring_emit(ring,
7103 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7106 /* XXX Enabling the panel-fitter across page-flip is so far
7107 * untested on non-native modes, so ignore it for now.
7108 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7111 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7112 intel_ring_emit(ring, pf | pipesrc);
7113 intel_ring_advance(ring);
7117 intel_unpin_fb_obj(obj);
7122 static int intel_gen6_queue_flip(struct drm_device *dev,
7123 struct drm_crtc *crtc,
7124 struct drm_framebuffer *fb,
7125 struct drm_i915_gem_object *obj)
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7129 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7130 uint32_t pf, pipesrc;
7133 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7137 ret = intel_ring_begin(ring, 4);
7141 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7142 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7144 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7146 /* Contrary to the suggestions in the documentation,
7147 * "Enable Panel Fitter" does not seem to be required when page
7148 * flipping with a non-native mode, and worse causes a normal
7150 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7153 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7154 intel_ring_emit(ring, pf | pipesrc);
7155 intel_ring_advance(ring);
7159 intel_unpin_fb_obj(obj);
7165 * On gen7 we currently use the blit ring because (in early silicon at least)
7166 * the render ring doesn't give us interrpts for page flip completion, which
7167 * means clients will hang after the first flip is queued. Fortunately the
7168 * blit ring generates interrupts properly, so use it instead.
7170 static int intel_gen7_queue_flip(struct drm_device *dev,
7171 struct drm_crtc *crtc,
7172 struct drm_framebuffer *fb,
7173 struct drm_i915_gem_object *obj)
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7178 uint32_t plane_bit = 0;
7181 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7185 switch(intel_crtc->plane) {
7187 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7190 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7193 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7196 WARN_ONCE(1, "unknown plane in flip command\n");
7201 ret = intel_ring_begin(ring, 4);
7205 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7206 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7207 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7208 intel_ring_emit(ring, (MI_NOOP));
7209 intel_ring_advance(ring);
7213 intel_unpin_fb_obj(obj);
7218 static int intel_default_queue_flip(struct drm_device *dev,
7219 struct drm_crtc *crtc,
7220 struct drm_framebuffer *fb,
7221 struct drm_i915_gem_object *obj)
7226 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7227 struct drm_framebuffer *fb,
7228 struct drm_pending_vblank_event *event)
7230 struct drm_device *dev = crtc->dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 struct intel_framebuffer *intel_fb;
7233 struct drm_i915_gem_object *obj;
7234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7235 struct intel_unpin_work *work;
7236 unsigned long flags;
7239 /* Can't change pixel format via MI display flips. */
7240 if (fb->pixel_format != crtc->fb->pixel_format)
7244 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7245 * Note that pitch changes could also affect these register.
7247 if (INTEL_INFO(dev)->gen > 3 &&
7248 (fb->offsets[0] != crtc->fb->offsets[0] ||
7249 fb->pitches[0] != crtc->fb->pitches[0]))
7252 work = kzalloc(sizeof *work, GFP_KERNEL);
7256 work->event = event;
7257 work->dev = crtc->dev;
7258 intel_fb = to_intel_framebuffer(crtc->fb);
7259 work->old_fb_obj = intel_fb->obj;
7260 INIT_WORK(&work->work, intel_unpin_work_fn);
7262 ret = drm_vblank_get(dev, intel_crtc->pipe);
7266 /* We borrow the event spin lock for protecting unpin_work */
7267 spin_lock_irqsave(&dev->event_lock, flags);
7268 if (intel_crtc->unpin_work) {
7269 spin_unlock_irqrestore(&dev->event_lock, flags);
7271 drm_vblank_put(dev, intel_crtc->pipe);
7273 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7276 intel_crtc->unpin_work = work;
7277 spin_unlock_irqrestore(&dev->event_lock, flags);
7279 intel_fb = to_intel_framebuffer(fb);
7280 obj = intel_fb->obj;
7282 ret = i915_mutex_lock_interruptible(dev);
7286 /* Reference the objects for the scheduled work. */
7287 drm_gem_object_reference(&work->old_fb_obj->base);
7288 drm_gem_object_reference(&obj->base);
7292 work->pending_flip_obj = obj;
7294 work->enable_stall_check = true;
7296 /* Block clients from rendering to the new back buffer until
7297 * the flip occurs and the object is no longer visible.
7299 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7301 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7303 goto cleanup_pending;
7305 intel_disable_fbc(dev);
7306 intel_mark_fb_busy(obj);
7307 mutex_unlock(&dev->struct_mutex);
7309 trace_i915_flip_request(intel_crtc->plane, obj);
7314 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7315 drm_gem_object_unreference(&work->old_fb_obj->base);
7316 drm_gem_object_unreference(&obj->base);
7317 mutex_unlock(&dev->struct_mutex);
7320 spin_lock_irqsave(&dev->event_lock, flags);
7321 intel_crtc->unpin_work = NULL;
7322 spin_unlock_irqrestore(&dev->event_lock, flags);
7324 drm_vblank_put(dev, intel_crtc->pipe);
7331 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7332 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7333 .load_lut = intel_crtc_load_lut,
7334 .disable = intel_crtc_noop,
7337 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7339 struct intel_encoder *other_encoder;
7340 struct drm_crtc *crtc = &encoder->new_crtc->base;
7345 list_for_each_entry(other_encoder,
7346 &crtc->dev->mode_config.encoder_list,
7349 if (&other_encoder->new_crtc->base != crtc ||
7350 encoder == other_encoder)
7359 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7360 struct drm_crtc *crtc)
7362 struct drm_device *dev;
7363 struct drm_crtc *tmp;
7366 WARN(!crtc, "checking null crtc?\n");
7370 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7376 if (encoder->possible_crtcs & crtc_mask)
7382 * intel_modeset_update_staged_output_state
7384 * Updates the staged output configuration state, e.g. after we've read out the
7387 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7389 struct intel_encoder *encoder;
7390 struct intel_connector *connector;
7392 list_for_each_entry(connector, &dev->mode_config.connector_list,
7394 connector->new_encoder =
7395 to_intel_encoder(connector->base.encoder);
7398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7401 to_intel_crtc(encoder->base.crtc);
7406 * intel_modeset_commit_output_state
7408 * This function copies the stage display pipe configuration to the real one.
7410 static void intel_modeset_commit_output_state(struct drm_device *dev)
7412 struct intel_encoder *encoder;
7413 struct intel_connector *connector;
7415 list_for_each_entry(connector, &dev->mode_config.connector_list,
7417 connector->base.encoder = &connector->new_encoder->base;
7420 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7422 encoder->base.crtc = &encoder->new_crtc->base;
7426 static struct drm_display_mode *
7427 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7428 struct drm_display_mode *mode)
7430 struct drm_device *dev = crtc->dev;
7431 struct drm_display_mode *adjusted_mode;
7432 struct drm_encoder_helper_funcs *encoder_funcs;
7433 struct intel_encoder *encoder;
7435 adjusted_mode = drm_mode_duplicate(dev, mode);
7437 return ERR_PTR(-ENOMEM);
7439 /* Pass our mode to the connectors and the CRTC to give them a chance to
7440 * adjust it according to limitations or connector properties, and also
7441 * a chance to reject the mode entirely.
7443 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7446 if (&encoder->new_crtc->base != crtc)
7448 encoder_funcs = encoder->base.helper_private;
7449 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7451 DRM_DEBUG_KMS("Encoder fixup failed\n");
7456 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7457 DRM_DEBUG_KMS("CRTC fixup failed\n");
7460 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7462 return adjusted_mode;
7464 drm_mode_destroy(dev, adjusted_mode);
7465 return ERR_PTR(-EINVAL);
7468 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7469 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7471 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7472 unsigned *prepare_pipes, unsigned *disable_pipes)
7474 struct intel_crtc *intel_crtc;
7475 struct drm_device *dev = crtc->dev;
7476 struct intel_encoder *encoder;
7477 struct intel_connector *connector;
7478 struct drm_crtc *tmp_crtc;
7480 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7482 /* Check which crtcs have changed outputs connected to them, these need
7483 * to be part of the prepare_pipes mask. We don't (yet) support global
7484 * modeset across multiple crtcs, so modeset_pipes will only have one
7485 * bit set at most. */
7486 list_for_each_entry(connector, &dev->mode_config.connector_list,
7488 if (connector->base.encoder == &connector->new_encoder->base)
7491 if (connector->base.encoder) {
7492 tmp_crtc = connector->base.encoder->crtc;
7494 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7497 if (connector->new_encoder)
7499 1 << connector->new_encoder->new_crtc->pipe;
7502 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7504 if (encoder->base.crtc == &encoder->new_crtc->base)
7507 if (encoder->base.crtc) {
7508 tmp_crtc = encoder->base.crtc;
7510 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7513 if (encoder->new_crtc)
7514 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7517 /* Check for any pipes that will be fully disabled ... */
7518 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7522 /* Don't try to disable disabled crtcs. */
7523 if (!intel_crtc->base.enabled)
7526 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7528 if (encoder->new_crtc == intel_crtc)
7533 *disable_pipes |= 1 << intel_crtc->pipe;
7537 /* set_mode is also used to update properties on life display pipes. */
7538 intel_crtc = to_intel_crtc(crtc);
7540 *prepare_pipes |= 1 << intel_crtc->pipe;
7542 /* We only support modeset on one single crtc, hence we need to do that
7543 * only for the passed in crtc iff we change anything else than just
7546 * This is actually not true, to be fully compatible with the old crtc
7547 * helper we automatically disable _any_ output (i.e. doesn't need to be
7548 * connected to the crtc we're modesetting on) if it's disconnected.
7549 * Which is a rather nutty api (since changed the output configuration
7550 * without userspace's explicit request can lead to confusion), but
7551 * alas. Hence we currently need to modeset on all pipes we prepare. */
7553 *modeset_pipes = *prepare_pipes;
7555 /* ... and mask these out. */
7556 *modeset_pipes &= ~(*disable_pipes);
7557 *prepare_pipes &= ~(*disable_pipes);
7560 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7562 struct drm_encoder *encoder;
7563 struct drm_device *dev = crtc->dev;
7565 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7566 if (encoder->crtc == crtc)
7573 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7575 struct intel_encoder *intel_encoder;
7576 struct intel_crtc *intel_crtc;
7577 struct drm_connector *connector;
7579 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7581 if (!intel_encoder->base.crtc)
7584 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7586 if (prepare_pipes & (1 << intel_crtc->pipe))
7587 intel_encoder->connectors_active = false;
7590 intel_modeset_commit_output_state(dev);
7592 /* Update computed state. */
7593 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7595 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7598 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7599 if (!connector->encoder || !connector->encoder->crtc)
7602 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7604 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7605 struct drm_property *dpms_property =
7606 dev->mode_config.dpms_property;
7608 connector->dpms = DRM_MODE_DPMS_ON;
7609 drm_connector_property_set_value(connector,
7613 intel_encoder = to_intel_encoder(connector->encoder);
7614 intel_encoder->connectors_active = true;
7620 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7621 list_for_each_entry((intel_crtc), \
7622 &(dev)->mode_config.crtc_list, \
7624 if (mask & (1 <<(intel_crtc)->pipe)) \
7627 intel_modeset_check_state(struct drm_device *dev)
7629 struct intel_crtc *crtc;
7630 struct intel_encoder *encoder;
7631 struct intel_connector *connector;
7633 list_for_each_entry(connector, &dev->mode_config.connector_list,
7635 /* This also checks the encoder/connector hw state with the
7636 * ->get_hw_state callbacks. */
7637 intel_connector_check_state(connector);
7639 WARN(&connector->new_encoder->base != connector->base.encoder,
7640 "connector's staged encoder doesn't match current encoder\n");
7643 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7645 bool enabled = false;
7646 bool active = false;
7647 enum pipe pipe, tracked_pipe;
7649 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7650 encoder->base.base.id,
7651 drm_get_encoder_name(&encoder->base));
7653 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7654 "encoder's stage crtc doesn't match current crtc\n");
7655 WARN(encoder->connectors_active && !encoder->base.crtc,
7656 "encoder's active_connectors set, but no crtc\n");
7658 list_for_each_entry(connector, &dev->mode_config.connector_list,
7660 if (connector->base.encoder != &encoder->base)
7663 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7666 WARN(!!encoder->base.crtc != enabled,
7667 "encoder's enabled state mismatch "
7668 "(expected %i, found %i)\n",
7669 !!encoder->base.crtc, enabled);
7670 WARN(active && !encoder->base.crtc,
7671 "active encoder with no crtc\n");
7673 WARN(encoder->connectors_active != active,
7674 "encoder's computed active state doesn't match tracked active state "
7675 "(expected %i, found %i)\n", active, encoder->connectors_active);
7677 active = encoder->get_hw_state(encoder, &pipe);
7678 WARN(active != encoder->connectors_active,
7679 "encoder's hw state doesn't match sw tracking "
7680 "(expected %i, found %i)\n",
7681 encoder->connectors_active, active);
7683 if (!encoder->base.crtc)
7686 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7687 WARN(active && pipe != tracked_pipe,
7688 "active encoder's pipe doesn't match"
7689 "(expected %i, found %i)\n",
7690 tracked_pipe, pipe);
7694 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7696 bool enabled = false;
7697 bool active = false;
7699 DRM_DEBUG_KMS("[CRTC:%d]\n",
7700 crtc->base.base.id);
7702 WARN(crtc->active && !crtc->base.enabled,
7703 "active crtc, but not enabled in sw tracking\n");
7705 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7707 if (encoder->base.crtc != &crtc->base)
7710 if (encoder->connectors_active)
7713 WARN(active != crtc->active,
7714 "crtc's computed active state doesn't match tracked active state "
7715 "(expected %i, found %i)\n", active, crtc->active);
7716 WARN(enabled != crtc->base.enabled,
7717 "crtc's computed enabled state doesn't match tracked enabled state "
7718 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7720 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7724 bool intel_set_mode(struct drm_crtc *crtc,
7725 struct drm_display_mode *mode,
7726 int x, int y, struct drm_framebuffer *fb)
7728 struct drm_device *dev = crtc->dev;
7729 drm_i915_private_t *dev_priv = dev->dev_private;
7730 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7731 struct intel_crtc *intel_crtc;
7732 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7735 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7736 &prepare_pipes, &disable_pipes);
7738 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7739 modeset_pipes, prepare_pipes, disable_pipes);
7741 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7742 intel_crtc_disable(&intel_crtc->base);
7744 saved_hwmode = crtc->hwmode;
7745 saved_mode = crtc->mode;
7747 /* Hack: Because we don't (yet) support global modeset on multiple
7748 * crtcs, we don't keep track of the new mode for more than one crtc.
7749 * Hence simply check whether any bit is set in modeset_pipes in all the
7750 * pieces of code that are not yet converted to deal with mutliple crtcs
7751 * changing their mode at the same time. */
7752 adjusted_mode = NULL;
7753 if (modeset_pipes) {
7754 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7755 if (IS_ERR(adjusted_mode)) {
7760 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7761 if (intel_crtc->base.enabled)
7762 dev_priv->display.crtc_disable(&intel_crtc->base);
7765 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7766 * to set it here already despite that we pass it down the callchain.
7771 /* Only after disabling all output pipelines that will be changed can we
7772 * update the the output configuration. */
7773 intel_modeset_update_state(dev, prepare_pipes);
7775 if (dev_priv->display.modeset_global_resources)
7776 dev_priv->display.modeset_global_resources(dev);
7778 /* Set up the DPLL and any encoders state that needs to adjust or depend
7781 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7782 ret = !intel_crtc_mode_set(&intel_crtc->base,
7783 mode, adjusted_mode,
7789 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7790 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7791 dev_priv->display.crtc_enable(&intel_crtc->base);
7793 if (modeset_pipes) {
7794 /* Store real post-adjustment hardware mode. */
7795 crtc->hwmode = *adjusted_mode;
7797 /* Calculate and store various constants which
7798 * are later needed by vblank and swap-completion
7799 * timestamping. They are derived from true hwmode.
7801 drm_calc_timestamping_constants(crtc);
7804 /* FIXME: add subpixel order */
7806 drm_mode_destroy(dev, adjusted_mode);
7807 if (!ret && crtc->enabled) {
7808 crtc->hwmode = saved_hwmode;
7809 crtc->mode = saved_mode;
7811 intel_modeset_check_state(dev);
7817 #undef for_each_intel_crtc_masked
7819 static void intel_set_config_free(struct intel_set_config *config)
7824 kfree(config->save_connector_encoders);
7825 kfree(config->save_encoder_crtcs);
7829 static int intel_set_config_save_state(struct drm_device *dev,
7830 struct intel_set_config *config)
7832 struct drm_encoder *encoder;
7833 struct drm_connector *connector;
7836 config->save_encoder_crtcs =
7837 kcalloc(dev->mode_config.num_encoder,
7838 sizeof(struct drm_crtc *), GFP_KERNEL);
7839 if (!config->save_encoder_crtcs)
7842 config->save_connector_encoders =
7843 kcalloc(dev->mode_config.num_connector,
7844 sizeof(struct drm_encoder *), GFP_KERNEL);
7845 if (!config->save_connector_encoders)
7848 /* Copy data. Note that driver private data is not affected.
7849 * Should anything bad happen only the expected state is
7850 * restored, not the drivers personal bookkeeping.
7853 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7854 config->save_encoder_crtcs[count++] = encoder->crtc;
7858 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7859 config->save_connector_encoders[count++] = connector->encoder;
7865 static void intel_set_config_restore_state(struct drm_device *dev,
7866 struct intel_set_config *config)
7868 struct intel_encoder *encoder;
7869 struct intel_connector *connector;
7873 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7875 to_intel_crtc(config->save_encoder_crtcs[count++]);
7879 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7880 connector->new_encoder =
7881 to_intel_encoder(config->save_connector_encoders[count++]);
7886 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7887 struct intel_set_config *config)
7890 /* We should be able to check here if the fb has the same properties
7891 * and then just flip_or_move it */
7892 if (set->crtc->fb != set->fb) {
7893 /* If we have no fb then treat it as a full mode set */
7894 if (set->crtc->fb == NULL) {
7895 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7896 config->mode_changed = true;
7897 } else if (set->fb == NULL) {
7898 config->mode_changed = true;
7899 } else if (set->fb->depth != set->crtc->fb->depth) {
7900 config->mode_changed = true;
7901 } else if (set->fb->bits_per_pixel !=
7902 set->crtc->fb->bits_per_pixel) {
7903 config->mode_changed = true;
7905 config->fb_changed = true;
7908 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7909 config->fb_changed = true;
7911 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7912 DRM_DEBUG_KMS("modes are different, full mode set\n");
7913 drm_mode_debug_printmodeline(&set->crtc->mode);
7914 drm_mode_debug_printmodeline(set->mode);
7915 config->mode_changed = true;
7920 intel_modeset_stage_output_state(struct drm_device *dev,
7921 struct drm_mode_set *set,
7922 struct intel_set_config *config)
7924 struct drm_crtc *new_crtc;
7925 struct intel_connector *connector;
7926 struct intel_encoder *encoder;
7929 /* The upper layers ensure that we either disabl a crtc or have a list
7930 * of connectors. For paranoia, double-check this. */
7931 WARN_ON(!set->fb && (set->num_connectors != 0));
7932 WARN_ON(set->fb && (set->num_connectors == 0));
7935 list_for_each_entry(connector, &dev->mode_config.connector_list,
7937 /* Otherwise traverse passed in connector list and get encoders
7939 for (ro = 0; ro < set->num_connectors; ro++) {
7940 if (set->connectors[ro] == &connector->base) {
7941 connector->new_encoder = connector->encoder;
7946 /* If we disable the crtc, disable all its connectors. Also, if
7947 * the connector is on the changing crtc but not on the new
7948 * connector list, disable it. */
7949 if ((!set->fb || ro == set->num_connectors) &&
7950 connector->base.encoder &&
7951 connector->base.encoder->crtc == set->crtc) {
7952 connector->new_encoder = NULL;
7954 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7955 connector->base.base.id,
7956 drm_get_connector_name(&connector->base));
7960 if (&connector->new_encoder->base != connector->base.encoder) {
7961 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7962 config->mode_changed = true;
7965 /* Disable all disconnected encoders. */
7966 if (connector->base.status == connector_status_disconnected)
7967 connector->new_encoder = NULL;
7969 /* connector->new_encoder is now updated for all connectors. */
7971 /* Update crtc of enabled connectors. */
7973 list_for_each_entry(connector, &dev->mode_config.connector_list,
7975 if (!connector->new_encoder)
7978 new_crtc = connector->new_encoder->base.crtc;
7980 for (ro = 0; ro < set->num_connectors; ro++) {
7981 if (set->connectors[ro] == &connector->base)
7982 new_crtc = set->crtc;
7985 /* Make sure the new CRTC will work with the encoder */
7986 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7990 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7992 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7993 connector->base.base.id,
7994 drm_get_connector_name(&connector->base),
7998 /* Check for any encoders that needs to be disabled. */
7999 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8001 list_for_each_entry(connector,
8002 &dev->mode_config.connector_list,
8004 if (connector->new_encoder == encoder) {
8005 WARN_ON(!connector->new_encoder->new_crtc);
8010 encoder->new_crtc = NULL;
8012 /* Only now check for crtc changes so we don't miss encoders
8013 * that will be disabled. */
8014 if (&encoder->new_crtc->base != encoder->base.crtc) {
8015 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8016 config->mode_changed = true;
8019 /* Now we've also updated encoder->new_crtc for all encoders. */
8024 static int intel_crtc_set_config(struct drm_mode_set *set)
8026 struct drm_device *dev;
8027 struct drm_mode_set save_set;
8028 struct intel_set_config *config;
8033 BUG_ON(!set->crtc->helper_private);
8038 /* The fb helper likes to play gross jokes with ->mode_set_config.
8039 * Unfortunately the crtc helper doesn't do much at all for this case,
8040 * so we have to cope with this madness until the fb helper is fixed up. */
8041 if (set->fb && set->num_connectors == 0)
8045 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8046 set->crtc->base.id, set->fb->base.id,
8047 (int)set->num_connectors, set->x, set->y);
8049 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8052 dev = set->crtc->dev;
8055 config = kzalloc(sizeof(*config), GFP_KERNEL);
8059 ret = intel_set_config_save_state(dev, config);
8063 save_set.crtc = set->crtc;
8064 save_set.mode = &set->crtc->mode;
8065 save_set.x = set->crtc->x;
8066 save_set.y = set->crtc->y;
8067 save_set.fb = set->crtc->fb;
8069 /* Compute whether we need a full modeset, only an fb base update or no
8070 * change at all. In the future we might also check whether only the
8071 * mode changed, e.g. for LVDS where we only change the panel fitter in
8073 intel_set_config_compute_mode_changes(set, config);
8075 ret = intel_modeset_stage_output_state(dev, set, config);
8079 if (config->mode_changed) {
8081 DRM_DEBUG_KMS("attempting to set mode from"
8083 drm_mode_debug_printmodeline(set->mode);
8086 if (!intel_set_mode(set->crtc, set->mode,
8087 set->x, set->y, set->fb)) {
8088 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8089 set->crtc->base.id);
8093 } else if (config->fb_changed) {
8094 ret = intel_pipe_set_base(set->crtc,
8095 set->x, set->y, set->fb);
8098 intel_set_config_free(config);
8103 intel_set_config_restore_state(dev, config);
8105 /* Try to restore the config */
8106 if (config->mode_changed &&
8107 !intel_set_mode(save_set.crtc, save_set.mode,
8108 save_set.x, save_set.y, save_set.fb))
8109 DRM_ERROR("failed to restore config after modeset failure\n");
8112 intel_set_config_free(config);
8116 static const struct drm_crtc_funcs intel_crtc_funcs = {
8117 .cursor_set = intel_crtc_cursor_set,
8118 .cursor_move = intel_crtc_cursor_move,
8119 .gamma_set = intel_crtc_gamma_set,
8120 .set_config = intel_crtc_set_config,
8121 .destroy = intel_crtc_destroy,
8122 .page_flip = intel_crtc_page_flip,
8125 static void intel_cpu_pll_init(struct drm_device *dev)
8127 if (IS_HASWELL(dev))
8128 intel_ddi_pll_init(dev);
8131 static void intel_pch_pll_init(struct drm_device *dev)
8133 drm_i915_private_t *dev_priv = dev->dev_private;
8136 if (dev_priv->num_pch_pll == 0) {
8137 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8141 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8142 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8143 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8144 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8148 static void intel_crtc_init(struct drm_device *dev, int pipe)
8150 drm_i915_private_t *dev_priv = dev->dev_private;
8151 struct intel_crtc *intel_crtc;
8154 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8155 if (intel_crtc == NULL)
8158 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8160 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8161 for (i = 0; i < 256; i++) {
8162 intel_crtc->lut_r[i] = i;
8163 intel_crtc->lut_g[i] = i;
8164 intel_crtc->lut_b[i] = i;
8167 /* Swap pipes & planes for FBC on pre-965 */
8168 intel_crtc->pipe = pipe;
8169 intel_crtc->plane = pipe;
8170 intel_crtc->cpu_transcoder = pipe;
8171 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8172 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8173 intel_crtc->plane = !pipe;
8176 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8177 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8179 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8181 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8183 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8186 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8187 struct drm_file *file)
8189 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8190 struct drm_mode_object *drmmode_obj;
8191 struct intel_crtc *crtc;
8193 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8196 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8197 DRM_MODE_OBJECT_CRTC);
8200 DRM_ERROR("no such CRTC id\n");
8204 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8205 pipe_from_crtc_id->pipe = crtc->pipe;
8210 static int intel_encoder_clones(struct intel_encoder *encoder)
8212 struct drm_device *dev = encoder->base.dev;
8213 struct intel_encoder *source_encoder;
8217 list_for_each_entry(source_encoder,
8218 &dev->mode_config.encoder_list, base.head) {
8220 if (encoder == source_encoder)
8221 index_mask |= (1 << entry);
8223 /* Intel hw has only one MUX where enocoders could be cloned. */
8224 if (encoder->cloneable && source_encoder->cloneable)
8225 index_mask |= (1 << entry);
8233 static bool has_edp_a(struct drm_device *dev)
8235 struct drm_i915_private *dev_priv = dev->dev_private;
8237 if (!IS_MOBILE(dev))
8240 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8244 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8250 static void intel_setup_outputs(struct drm_device *dev)
8252 struct drm_i915_private *dev_priv = dev->dev_private;
8253 struct intel_encoder *encoder;
8254 bool dpd_is_edp = false;
8257 has_lvds = intel_lvds_init(dev);
8258 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8259 /* disable the panel fitter on everything but LVDS */
8260 I915_WRITE(PFIT_CONTROL, 0);
8263 intel_crt_init(dev);
8265 if (IS_HASWELL(dev)) {
8268 /* Haswell uses DDI functions to detect digital outputs */
8269 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8270 /* DDI A only supports eDP */
8272 intel_ddi_init(dev, PORT_A);
8274 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8276 found = I915_READ(SFUSE_STRAP);
8278 if (found & SFUSE_STRAP_DDIB_DETECTED)
8279 intel_ddi_init(dev, PORT_B);
8280 if (found & SFUSE_STRAP_DDIC_DETECTED)
8281 intel_ddi_init(dev, PORT_C);
8282 if (found & SFUSE_STRAP_DDID_DETECTED)
8283 intel_ddi_init(dev, PORT_D);
8284 } else if (HAS_PCH_SPLIT(dev)) {
8286 dpd_is_edp = intel_dpd_is_edp(dev);
8289 intel_dp_init(dev, DP_A, PORT_A);
8291 if (I915_READ(HDMIB) & PORT_DETECTED) {
8292 /* PCH SDVOB multiplex with HDMIB */
8293 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8295 intel_hdmi_init(dev, HDMIB, PORT_B);
8296 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8297 intel_dp_init(dev, PCH_DP_B, PORT_B);
8300 if (I915_READ(HDMIC) & PORT_DETECTED)
8301 intel_hdmi_init(dev, HDMIC, PORT_C);
8303 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8304 intel_hdmi_init(dev, HDMID, PORT_D);
8306 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8307 intel_dp_init(dev, PCH_DP_C, PORT_C);
8309 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8310 intel_dp_init(dev, PCH_DP_D, PORT_D);
8311 } else if (IS_VALLEYVIEW(dev)) {
8314 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8315 if (I915_READ(DP_C) & DP_DETECTED)
8316 intel_dp_init(dev, DP_C, PORT_C);
8318 if (I915_READ(SDVOB) & PORT_DETECTED) {
8319 /* SDVOB multiplex with HDMIB */
8320 found = intel_sdvo_init(dev, SDVOB, true);
8322 intel_hdmi_init(dev, SDVOB, PORT_B);
8323 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8324 intel_dp_init(dev, DP_B, PORT_B);
8327 if (I915_READ(SDVOC) & PORT_DETECTED)
8328 intel_hdmi_init(dev, SDVOC, PORT_C);
8330 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8333 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8334 DRM_DEBUG_KMS("probing SDVOB\n");
8335 found = intel_sdvo_init(dev, SDVOB, true);
8336 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8337 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8338 intel_hdmi_init(dev, SDVOB, PORT_B);
8341 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8342 DRM_DEBUG_KMS("probing DP_B\n");
8343 intel_dp_init(dev, DP_B, PORT_B);
8347 /* Before G4X SDVOC doesn't have its own detect register */
8349 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8350 DRM_DEBUG_KMS("probing SDVOC\n");
8351 found = intel_sdvo_init(dev, SDVOC, false);
8354 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8356 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8357 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8358 intel_hdmi_init(dev, SDVOC, PORT_C);
8360 if (SUPPORTS_INTEGRATED_DP(dev)) {
8361 DRM_DEBUG_KMS("probing DP_C\n");
8362 intel_dp_init(dev, DP_C, PORT_C);
8366 if (SUPPORTS_INTEGRATED_DP(dev) &&
8367 (I915_READ(DP_D) & DP_DETECTED)) {
8368 DRM_DEBUG_KMS("probing DP_D\n");
8369 intel_dp_init(dev, DP_D, PORT_D);
8371 } else if (IS_GEN2(dev))
8372 intel_dvo_init(dev);
8374 if (SUPPORTS_TV(dev))
8377 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8378 encoder->base.possible_crtcs = encoder->crtc_mask;
8379 encoder->base.possible_clones =
8380 intel_encoder_clones(encoder);
8383 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8384 ironlake_init_pch_refclk(dev);
8386 drm_helper_move_panel_connectors_to_head(dev);
8389 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8391 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8393 drm_framebuffer_cleanup(fb);
8394 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8399 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8400 struct drm_file *file,
8401 unsigned int *handle)
8403 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8404 struct drm_i915_gem_object *obj = intel_fb->obj;
8406 return drm_gem_handle_create(file, &obj->base, handle);
8409 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8410 .destroy = intel_user_framebuffer_destroy,
8411 .create_handle = intel_user_framebuffer_create_handle,
8414 int intel_framebuffer_init(struct drm_device *dev,
8415 struct intel_framebuffer *intel_fb,
8416 struct drm_mode_fb_cmd2 *mode_cmd,
8417 struct drm_i915_gem_object *obj)
8421 if (obj->tiling_mode == I915_TILING_Y)
8424 if (mode_cmd->pitches[0] & 63)
8427 /* FIXME <= Gen4 stride limits are bit unclear */
8428 if (mode_cmd->pitches[0] > 32768)
8431 if (obj->tiling_mode != I915_TILING_NONE &&
8432 mode_cmd->pitches[0] != obj->stride)
8435 /* Reject formats not supported by any plane early. */
8436 switch (mode_cmd->pixel_format) {
8438 case DRM_FORMAT_RGB565:
8439 case DRM_FORMAT_XRGB8888:
8440 case DRM_FORMAT_ARGB8888:
8442 case DRM_FORMAT_XRGB1555:
8443 case DRM_FORMAT_ARGB1555:
8444 if (INTEL_INFO(dev)->gen > 3)
8447 case DRM_FORMAT_XBGR8888:
8448 case DRM_FORMAT_ABGR8888:
8449 case DRM_FORMAT_XRGB2101010:
8450 case DRM_FORMAT_ARGB2101010:
8451 case DRM_FORMAT_XBGR2101010:
8452 case DRM_FORMAT_ABGR2101010:
8453 if (INTEL_INFO(dev)->gen < 4)
8456 case DRM_FORMAT_YUYV:
8457 case DRM_FORMAT_UYVY:
8458 case DRM_FORMAT_YVYU:
8459 case DRM_FORMAT_VYUY:
8460 if (INTEL_INFO(dev)->gen < 6)
8464 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8468 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8469 if (mode_cmd->offsets[0] != 0)
8472 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8474 DRM_ERROR("framebuffer init failed %d\n", ret);
8478 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8479 intel_fb->obj = obj;
8483 static struct drm_framebuffer *
8484 intel_user_framebuffer_create(struct drm_device *dev,
8485 struct drm_file *filp,
8486 struct drm_mode_fb_cmd2 *mode_cmd)
8488 struct drm_i915_gem_object *obj;
8490 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8491 mode_cmd->handles[0]));
8492 if (&obj->base == NULL)
8493 return ERR_PTR(-ENOENT);
8495 return intel_framebuffer_create(dev, mode_cmd, obj);
8498 static const struct drm_mode_config_funcs intel_mode_funcs = {
8499 .fb_create = intel_user_framebuffer_create,
8500 .output_poll_changed = intel_fb_output_poll_changed,
8503 /* Set up chip specific display functions */
8504 static void intel_init_display(struct drm_device *dev)
8506 struct drm_i915_private *dev_priv = dev->dev_private;
8508 /* We always want a DPMS function */
8509 if (IS_HASWELL(dev)) {
8510 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8511 dev_priv->display.crtc_enable = haswell_crtc_enable;
8512 dev_priv->display.crtc_disable = haswell_crtc_disable;
8513 dev_priv->display.off = haswell_crtc_off;
8514 dev_priv->display.update_plane = ironlake_update_plane;
8515 } else if (HAS_PCH_SPLIT(dev)) {
8516 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8517 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8518 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8519 dev_priv->display.off = ironlake_crtc_off;
8520 dev_priv->display.update_plane = ironlake_update_plane;
8522 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8523 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8524 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8525 dev_priv->display.off = i9xx_crtc_off;
8526 dev_priv->display.update_plane = i9xx_update_plane;
8529 /* Returns the core display clock speed */
8530 if (IS_VALLEYVIEW(dev))
8531 dev_priv->display.get_display_clock_speed =
8532 valleyview_get_display_clock_speed;
8533 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8534 dev_priv->display.get_display_clock_speed =
8535 i945_get_display_clock_speed;
8536 else if (IS_I915G(dev))
8537 dev_priv->display.get_display_clock_speed =
8538 i915_get_display_clock_speed;
8539 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8540 dev_priv->display.get_display_clock_speed =
8541 i9xx_misc_get_display_clock_speed;
8542 else if (IS_I915GM(dev))
8543 dev_priv->display.get_display_clock_speed =
8544 i915gm_get_display_clock_speed;
8545 else if (IS_I865G(dev))
8546 dev_priv->display.get_display_clock_speed =
8547 i865_get_display_clock_speed;
8548 else if (IS_I85X(dev))
8549 dev_priv->display.get_display_clock_speed =
8550 i855_get_display_clock_speed;
8552 dev_priv->display.get_display_clock_speed =
8553 i830_get_display_clock_speed;
8555 if (HAS_PCH_SPLIT(dev)) {
8557 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8558 dev_priv->display.write_eld = ironlake_write_eld;
8559 } else if (IS_GEN6(dev)) {
8560 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8561 dev_priv->display.write_eld = ironlake_write_eld;
8562 } else if (IS_IVYBRIDGE(dev)) {
8563 /* FIXME: detect B0+ stepping and use auto training */
8564 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8565 dev_priv->display.write_eld = ironlake_write_eld;
8566 dev_priv->display.modeset_global_resources =
8567 ivb_modeset_global_resources;
8568 } else if (IS_HASWELL(dev)) {
8569 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8570 dev_priv->display.write_eld = haswell_write_eld;
8572 dev_priv->display.update_wm = NULL;
8573 } else if (IS_G4X(dev)) {
8574 dev_priv->display.write_eld = g4x_write_eld;
8577 /* Default just returns -ENODEV to indicate unsupported */
8578 dev_priv->display.queue_flip = intel_default_queue_flip;
8580 switch (INTEL_INFO(dev)->gen) {
8582 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8586 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8591 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8595 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8598 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8604 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8605 * resume, or other times. This quirk makes sure that's the case for
8608 static void quirk_pipea_force(struct drm_device *dev)
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8612 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8613 DRM_INFO("applying pipe a force quirk\n");
8617 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8619 static void quirk_ssc_force_disable(struct drm_device *dev)
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8622 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8623 DRM_INFO("applying lvds SSC disable quirk\n");
8627 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8630 static void quirk_invert_brightness(struct drm_device *dev)
8632 struct drm_i915_private *dev_priv = dev->dev_private;
8633 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8634 DRM_INFO("applying inverted panel brightness quirk\n");
8637 struct intel_quirk {
8639 int subsystem_vendor;
8640 int subsystem_device;
8641 void (*hook)(struct drm_device *dev);
8644 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8645 struct intel_dmi_quirk {
8646 void (*hook)(struct drm_device *dev);
8647 const struct dmi_system_id (*dmi_id_list)[];
8650 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8652 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8656 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8658 .dmi_id_list = &(const struct dmi_system_id[]) {
8660 .callback = intel_dmi_reverse_brightness,
8661 .ident = "NCR Corporation",
8662 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8663 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8666 { } /* terminating entry */
8668 .hook = quirk_invert_brightness,
8672 static struct intel_quirk intel_quirks[] = {
8673 /* HP Mini needs pipe A force quirk (LP: #322104) */
8674 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8676 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8677 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8679 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8680 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8682 /* 830/845 need to leave pipe A & dpll A up */
8683 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8684 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8686 /* Lenovo U160 cannot use SSC on LVDS */
8687 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8689 /* Sony Vaio Y cannot use SSC on LVDS */
8690 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8692 /* Acer Aspire 5734Z must invert backlight brightness */
8693 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8696 static void intel_init_quirks(struct drm_device *dev)
8698 struct pci_dev *d = dev->pdev;
8701 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8702 struct intel_quirk *q = &intel_quirks[i];
8704 if (d->device == q->device &&
8705 (d->subsystem_vendor == q->subsystem_vendor ||
8706 q->subsystem_vendor == PCI_ANY_ID) &&
8707 (d->subsystem_device == q->subsystem_device ||
8708 q->subsystem_device == PCI_ANY_ID))
8711 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8712 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8713 intel_dmi_quirks[i].hook(dev);
8717 /* Disable the VGA plane that we never use */
8718 static void i915_disable_vga(struct drm_device *dev)
8720 struct drm_i915_private *dev_priv = dev->dev_private;
8724 if (HAS_PCH_SPLIT(dev))
8725 vga_reg = CPU_VGACNTRL;
8729 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8730 outb(SR01, VGA_SR_INDEX);
8731 sr1 = inb(VGA_SR_DATA);
8732 outb(sr1 | 1<<5, VGA_SR_DATA);
8733 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8736 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8737 POSTING_READ(vga_reg);
8740 void intel_modeset_init_hw(struct drm_device *dev)
8742 /* We attempt to init the necessary power wells early in the initialization
8743 * time, so the subsystems that expect power to be enabled can work.
8745 intel_init_power_wells(dev);
8747 intel_prepare_ddi(dev);
8749 intel_init_clock_gating(dev);
8751 mutex_lock(&dev->struct_mutex);
8752 intel_enable_gt_powersave(dev);
8753 mutex_unlock(&dev->struct_mutex);
8756 void intel_modeset_init(struct drm_device *dev)
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8761 drm_mode_config_init(dev);
8763 dev->mode_config.min_width = 0;
8764 dev->mode_config.min_height = 0;
8766 dev->mode_config.preferred_depth = 24;
8767 dev->mode_config.prefer_shadow = 1;
8769 dev->mode_config.funcs = &intel_mode_funcs;
8771 intel_init_quirks(dev);
8775 intel_init_display(dev);
8778 dev->mode_config.max_width = 2048;
8779 dev->mode_config.max_height = 2048;
8780 } else if (IS_GEN3(dev)) {
8781 dev->mode_config.max_width = 4096;
8782 dev->mode_config.max_height = 4096;
8784 dev->mode_config.max_width = 8192;
8785 dev->mode_config.max_height = 8192;
8787 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8789 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8790 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8792 for (i = 0; i < dev_priv->num_pipe; i++) {
8793 intel_crtc_init(dev, i);
8794 ret = intel_plane_init(dev, i);
8796 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8799 intel_cpu_pll_init(dev);
8800 intel_pch_pll_init(dev);
8802 /* Just disable it once at startup */
8803 i915_disable_vga(dev);
8804 intel_setup_outputs(dev);
8808 intel_connector_break_all_links(struct intel_connector *connector)
8810 connector->base.dpms = DRM_MODE_DPMS_OFF;
8811 connector->base.encoder = NULL;
8812 connector->encoder->connectors_active = false;
8813 connector->encoder->base.crtc = NULL;
8816 static void intel_enable_pipe_a(struct drm_device *dev)
8818 struct intel_connector *connector;
8819 struct drm_connector *crt = NULL;
8820 struct intel_load_detect_pipe load_detect_temp;
8822 /* We can't just switch on the pipe A, we need to set things up with a
8823 * proper mode and output configuration. As a gross hack, enable pipe A
8824 * by enabling the load detect pipe once. */
8825 list_for_each_entry(connector,
8826 &dev->mode_config.connector_list,
8828 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8829 crt = &connector->base;
8837 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8838 intel_release_load_detect_pipe(crt, &load_detect_temp);
8844 intel_check_plane_mapping(struct intel_crtc *crtc)
8846 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8849 if (dev_priv->num_pipe == 1)
8852 reg = DSPCNTR(!crtc->plane);
8853 val = I915_READ(reg);
8855 if ((val & DISPLAY_PLANE_ENABLE) &&
8856 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8862 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8864 struct drm_device *dev = crtc->base.dev;
8865 struct drm_i915_private *dev_priv = dev->dev_private;
8868 /* Clear any frame start delays used for debugging left by the BIOS */
8869 reg = PIPECONF(crtc->cpu_transcoder);
8870 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8872 /* We need to sanitize the plane -> pipe mapping first because this will
8873 * disable the crtc (and hence change the state) if it is wrong. Note
8874 * that gen4+ has a fixed plane -> pipe mapping. */
8875 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8876 struct intel_connector *connector;
8879 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8880 crtc->base.base.id);
8882 /* Pipe has the wrong plane attached and the plane is active.
8883 * Temporarily change the plane mapping and disable everything
8885 plane = crtc->plane;
8886 crtc->plane = !plane;
8887 dev_priv->display.crtc_disable(&crtc->base);
8888 crtc->plane = plane;
8890 /* ... and break all links. */
8891 list_for_each_entry(connector, &dev->mode_config.connector_list,
8893 if (connector->encoder->base.crtc != &crtc->base)
8896 intel_connector_break_all_links(connector);
8899 WARN_ON(crtc->active);
8900 crtc->base.enabled = false;
8903 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8904 crtc->pipe == PIPE_A && !crtc->active) {
8905 /* BIOS forgot to enable pipe A, this mostly happens after
8906 * resume. Force-enable the pipe to fix this, the update_dpms
8907 * call below we restore the pipe to the right state, but leave
8908 * the required bits on. */
8909 intel_enable_pipe_a(dev);
8912 /* Adjust the state of the output pipe according to whether we
8913 * have active connectors/encoders. */
8914 intel_crtc_update_dpms(&crtc->base);
8916 if (crtc->active != crtc->base.enabled) {
8917 struct intel_encoder *encoder;
8919 /* This can happen either due to bugs in the get_hw_state
8920 * functions or because the pipe is force-enabled due to the
8922 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8924 crtc->base.enabled ? "enabled" : "disabled",
8925 crtc->active ? "enabled" : "disabled");
8927 crtc->base.enabled = crtc->active;
8929 /* Because we only establish the connector -> encoder ->
8930 * crtc links if something is active, this means the
8931 * crtc is now deactivated. Break the links. connector
8932 * -> encoder links are only establish when things are
8933 * actually up, hence no need to break them. */
8934 WARN_ON(crtc->active);
8936 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8937 WARN_ON(encoder->connectors_active);
8938 encoder->base.crtc = NULL;
8943 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8945 struct intel_connector *connector;
8946 struct drm_device *dev = encoder->base.dev;
8948 /* We need to check both for a crtc link (meaning that the
8949 * encoder is active and trying to read from a pipe) and the
8950 * pipe itself being active. */
8951 bool has_active_crtc = encoder->base.crtc &&
8952 to_intel_crtc(encoder->base.crtc)->active;
8954 if (encoder->connectors_active && !has_active_crtc) {
8955 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8956 encoder->base.base.id,
8957 drm_get_encoder_name(&encoder->base));
8959 /* Connector is active, but has no active pipe. This is
8960 * fallout from our resume register restoring. Disable
8961 * the encoder manually again. */
8962 if (encoder->base.crtc) {
8963 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8964 encoder->base.base.id,
8965 drm_get_encoder_name(&encoder->base));
8966 encoder->disable(encoder);
8969 /* Inconsistent output/port/pipe state happens presumably due to
8970 * a bug in one of the get_hw_state functions. Or someplace else
8971 * in our code, like the register restore mess on resume. Clamp
8972 * things to off as a safer default. */
8973 list_for_each_entry(connector,
8974 &dev->mode_config.connector_list,
8976 if (connector->encoder != encoder)
8979 intel_connector_break_all_links(connector);
8982 /* Enabled encoders without active connectors will be fixed in
8983 * the crtc fixup. */
8986 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8987 * and i915 state tracking structures. */
8988 void intel_modeset_setup_hw_state(struct drm_device *dev)
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8993 struct intel_crtc *crtc;
8994 struct intel_encoder *encoder;
8995 struct intel_connector *connector;
8997 if (IS_HASWELL(dev)) {
8998 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9000 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9001 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9002 case TRANS_DDI_EDP_INPUT_A_ON:
9003 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9006 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9009 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9014 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9015 crtc->cpu_transcoder = TRANSCODER_EDP;
9017 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9022 for_each_pipe(pipe) {
9023 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9025 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9026 if (tmp & PIPECONF_ENABLE)
9027 crtc->active = true;
9029 crtc->active = false;
9031 crtc->base.enabled = crtc->active;
9033 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9035 crtc->active ? "enabled" : "disabled");
9038 if (IS_HASWELL(dev))
9039 intel_ddi_setup_hw_pll_state(dev);
9041 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9045 if (encoder->get_hw_state(encoder, &pipe)) {
9046 encoder->base.crtc =
9047 dev_priv->pipe_to_crtc_mapping[pipe];
9049 encoder->base.crtc = NULL;
9052 encoder->connectors_active = false;
9053 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9054 encoder->base.base.id,
9055 drm_get_encoder_name(&encoder->base),
9056 encoder->base.crtc ? "enabled" : "disabled",
9060 list_for_each_entry(connector, &dev->mode_config.connector_list,
9062 if (connector->get_hw_state(connector)) {
9063 connector->base.dpms = DRM_MODE_DPMS_ON;
9064 connector->encoder->connectors_active = true;
9065 connector->base.encoder = &connector->encoder->base;
9067 connector->base.dpms = DRM_MODE_DPMS_OFF;
9068 connector->base.encoder = NULL;
9070 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9071 connector->base.base.id,
9072 drm_get_connector_name(&connector->base),
9073 connector->base.encoder ? "enabled" : "disabled");
9076 /* HW state is read out, now we need to sanitize this mess. */
9077 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9079 intel_sanitize_encoder(encoder);
9082 for_each_pipe(pipe) {
9083 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9084 intel_sanitize_crtc(crtc);
9087 intel_modeset_update_staged_output_state(dev);
9089 intel_modeset_check_state(dev);
9091 drm_mode_config_reset(dev);
9094 void intel_modeset_gem_init(struct drm_device *dev)
9096 intel_modeset_init_hw(dev);
9098 intel_setup_overlay(dev);
9100 intel_modeset_setup_hw_state(dev);
9103 void intel_modeset_cleanup(struct drm_device *dev)
9105 struct drm_i915_private *dev_priv = dev->dev_private;
9106 struct drm_crtc *crtc;
9107 struct intel_crtc *intel_crtc;
9109 drm_kms_helper_poll_fini(dev);
9110 mutex_lock(&dev->struct_mutex);
9112 intel_unregister_dsm_handler();
9115 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9116 /* Skip inactive CRTCs */
9120 intel_crtc = to_intel_crtc(crtc);
9121 intel_increase_pllclock(crtc);
9124 intel_disable_fbc(dev);
9126 intel_disable_gt_powersave(dev);
9128 ironlake_teardown_rc6(dev);
9130 if (IS_VALLEYVIEW(dev))
9133 mutex_unlock(&dev->struct_mutex);
9135 /* Disable the irq before mode object teardown, for the irq might
9136 * enqueue unpin/hotplug work. */
9137 drm_irq_uninstall(dev);
9138 cancel_work_sync(&dev_priv->hotplug_work);
9139 cancel_work_sync(&dev_priv->rps.work);
9141 /* flush any delayed tasks or pending work */
9142 flush_scheduled_work();
9144 drm_mode_config_cleanup(dev);
9148 * Return which encoder is currently attached for connector.
9150 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9152 return &intel_attached_encoder(connector)->base;
9155 void intel_connector_attach_encoder(struct intel_connector *connector,
9156 struct intel_encoder *encoder)
9158 connector->encoder = encoder;
9159 drm_mode_connector_attach_encoder(&connector->base,
9164 * set vga decode state - true == enable VGA decode
9166 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9171 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9173 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9175 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9176 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9180 #ifdef CONFIG_DEBUG_FS
9181 #include <linux/seq_file.h>
9183 struct intel_display_error_state {
9184 struct intel_cursor_error_state {
9189 } cursor[I915_MAX_PIPES];
9191 struct intel_pipe_error_state {
9201 } pipe[I915_MAX_PIPES];
9203 struct intel_plane_error_state {
9211 } plane[I915_MAX_PIPES];
9214 struct intel_display_error_state *
9215 intel_display_capture_error_state(struct drm_device *dev)
9217 drm_i915_private_t *dev_priv = dev->dev_private;
9218 struct intel_display_error_state *error;
9219 enum transcoder cpu_transcoder;
9222 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9227 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9229 error->cursor[i].control = I915_READ(CURCNTR(i));
9230 error->cursor[i].position = I915_READ(CURPOS(i));
9231 error->cursor[i].base = I915_READ(CURBASE(i));
9233 error->plane[i].control = I915_READ(DSPCNTR(i));
9234 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9235 error->plane[i].size = I915_READ(DSPSIZE(i));
9236 error->plane[i].pos = I915_READ(DSPPOS(i));
9237 error->plane[i].addr = I915_READ(DSPADDR(i));
9238 if (INTEL_INFO(dev)->gen >= 4) {
9239 error->plane[i].surface = I915_READ(DSPSURF(i));
9240 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9243 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9244 error->pipe[i].source = I915_READ(PIPESRC(i));
9245 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9246 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9247 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9248 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9249 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9250 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9257 intel_display_print_error_state(struct seq_file *m,
9258 struct drm_device *dev,
9259 struct intel_display_error_state *error)
9261 drm_i915_private_t *dev_priv = dev->dev_private;
9264 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9266 seq_printf(m, "Pipe [%d]:\n", i);
9267 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9268 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9269 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9270 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9271 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9272 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9273 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9274 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9276 seq_printf(m, "Plane [%d]:\n", i);
9277 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9278 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9279 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9280 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9281 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9282 if (INTEL_INFO(dev)->gen >= 4) {
9283 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9284 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9287 seq_printf(m, "Cursor [%d]:\n", i);
9288 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9289 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9290 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);