Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 10, .max = 22 },
 172         .m2 = { .min = 5, .max = 9 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         unsigned long flags;
 420         u32 val = 0;
 421
 422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO idle wait timed out\n");
 425                 goto out_unlock;
 426         }
 427
 428         I915_WRITE(DPIO_REG, reg);
 429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 430                    DPIO_BYTE);
 431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 432                 DRM_ERROR("DPIO read wait timed out\n");
 433                 goto out_unlock;
 434         }
 435         val = I915_READ(DPIO_DATA);
 436
 437 out_unlock:
 438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 439         return val;
 440 }
 441
 442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 443                              u32 val)
 444 {
 445         unsigned long flags;
 446
 447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 449                 DRM_ERROR("DPIO idle wait timed out\n");
 450                 goto out_unlock;
 451         }
 452
 453         I915_WRITE(DPIO_DATA, val);
 454         I915_WRITE(DPIO_REG, reg);
 455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 456                    DPIO_BYTE);
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 458                 DRM_ERROR("DPIO write wait timed out\n");
 459
 460 out_unlock:
 461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 462 }
 463
 464 static void vlv_init_dpio(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         /* Reset the DPIO config */
 469         I915_WRITE(DPIO_CTL, 0);
 470         POSTING_READ(DPIO_CTL);
 471         I915_WRITE(DPIO_CTL, 1);
 472         POSTING_READ(DPIO_CTL);
 473 }
 474
 475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 476 {
 477         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 478         return 1;
 479 }
 480
 481 static const struct dmi_system_id intel_dual_link_lvds[] = {
 482         {
 483                 .callback = intel_dual_link_lvds_callback,
 484                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 485                 .matches = {
 486                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 487                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 488                 },
 489         },
 490         { }     /* terminating entry */
 491 };
 492
 493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 494                               unsigned int reg)
 495 {
 496         unsigned int val;
 497
 498         /* use the module option value if specified */
 499         if (i915_lvds_channel_mode > 0)
 500                 return i915_lvds_channel_mode == 2;
 501
 502         if (dmi_check_system(intel_dual_link_lvds))
 503                 return true;
 504
 505         if (dev_priv->lvds_val)
 506                 val = dev_priv->lvds_val;
 507         else {
 508                 /* BIOS should set the proper LVDS register value at boot, but
 509                  * in reality, it doesn't set the value when the lid is closed;
 510                  * we need to check "the value to be set" in VBT when LVDS
 511                  * register is uninitialized.
 512                  */
 513                 val = I915_READ(reg);
 514                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 515                         val = dev_priv->bios_lvds_val;
 516                 dev_priv->lvds_val = val;
 517         }
 518         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 519 }
 520
 521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 522                                                 int refclk)
 523 {
 524         struct drm_device *dev = crtc->dev;
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         const intel_limit_t *limit;
 527
 528         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 529                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 530                         /* LVDS dual channel */
 531                         if (refclk == 100000)
 532                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 533                         else
 534                                 limit = &intel_limits_ironlake_dual_lvds;
 535                 } else {
 536                         if (refclk == 100000)
 537                                 limit = &intel_limits_ironlake_single_lvds_100m;
 538                         else
 539                                 limit = &intel_limits_ironlake_single_lvds;
 540                 }
 541         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 542                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 543                 limit = &intel_limits_ironlake_display_port;
 544         else
 545                 limit = &intel_limits_ironlake_dac;
 546
 547         return limit;
 548 }
 549
 550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         const intel_limit_t *limit;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 if (is_dual_link_lvds(dev_priv, LVDS))
 558                         /* LVDS with dual channel */
 559                         limit = &intel_limits_g4x_dual_channel_lvds;
 560                 else
 561                         /* LVDS with dual channel */
 562                         limit = &intel_limits_g4x_single_channel_lvds;
 563         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 564                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 565                 limit = &intel_limits_g4x_hdmi;
 566         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 567                 limit = &intel_limits_g4x_sdvo;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 569                 limit = &intel_limits_g4x_display_port;
 570         } else /* The option is for other outputs */
 571                 limit = &intel_limits_i9xx_sdvo;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 577 {
 578         struct drm_device *dev = crtc->dev;
 579         const intel_limit_t *limit;
 580
 581         if (HAS_PCH_SPLIT(dev))
 582                 limit = intel_ironlake_limit(crtc, refclk);
 583         else if (IS_G4X(dev)) {
 584                 limit = intel_g4x_limit(crtc);
 585         } else if (IS_PINEVIEW(dev)) {
 586                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 587                         limit = &intel_limits_pineview_lvds;
 588                 else
 589                         limit = &intel_limits_pineview_sdvo;
 590         } else if (IS_VALLEYVIEW(dev)) {
 591                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 592                         limit = &intel_limits_vlv_dac;
 593                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 594                         limit = &intel_limits_vlv_hdmi;
 595                 else
 596                         limit = &intel_limits_vlv_dp;
 597         } else if (!IS_GEN2(dev)) {
 598                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 599                         limit = &intel_limits_i9xx_lvds;
 600                 else
 601                         limit = &intel_limits_i9xx_sdvo;
 602         } else {
 603                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 604                         limit = &intel_limits_i8xx_lvds;
 605                 else
 606                         limit = &intel_limits_i8xx_dvo;
 607         }
 608         return limit;
 609 }
 610
 611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 612 static void pineview_clock(int refclk, intel_clock_t *clock)
 613 {
 614         clock->m = clock->m2 + 2;
 615         clock->p = clock->p1 * clock->p2;
 616         clock->vco = refclk * clock->m / clock->n;
 617         clock->dot = clock->vco / clock->p;
 618 }
 619
 620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 621 {
 622         if (IS_PINEVIEW(dev)) {
 623                 pineview_clock(refclk, clock);
 624                 return;
 625         }
 626         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 627         clock->p = clock->p1 * clock->p2;
 628         clock->vco = refclk * clock->m / (clock->n + 2);
 629         clock->dot = clock->vco / clock->p;
 630 }
 631
 632 /**
 633  * Returns whether any output on the specified pipe is of the specified type
 634  */
 635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 636 {
 637         struct drm_device *dev = crtc->dev;
 638         struct intel_encoder *encoder;
 639
 640         for_each_encoder_on_crtc(dev, crtc, encoder)
 641                 if (encoder->type == type)
 642                         return true;
 643
 644         return false;
 645 }
 646
 647 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 648 /**
 649  * Returns whether the given set of divisors are valid for a given refclk with
 650  * the given connectors.
 651  */
 652
 653 static bool intel_PLL_is_valid(struct drm_device *dev,
 654                                const intel_limit_t *limit,
 655                                const intel_clock_t *clock)
 656 {
 657         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 658                 INTELPllInvalid("p1 out of range\n");
 659         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 660                 INTELPllInvalid("p out of range\n");
 661         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 662                 INTELPllInvalid("m2 out of range\n");
 663         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 664                 INTELPllInvalid("m1 out of range\n");
 665         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 666                 INTELPllInvalid("m1 <= m2\n");
 667         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 668                 INTELPllInvalid("m out of range\n");
 669         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 670                 INTELPllInvalid("n out of range\n");
 671         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 672                 INTELPllInvalid("vco out of range\n");
 673         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 674          * connector, etc., rather than just a single range.
 675          */
 676         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 677                 INTELPllInvalid("dot out of range\n");
 678
 679         return true;
 680 }
 681
 682 static bool
 683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                     int target, int refclk, intel_clock_t *match_clock,
 685                     intel_clock_t *best_clock)
 686
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         intel_clock_t clock;
 691         int err = target;
 692
 693         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 694             (I915_READ(LVDS)) != 0) {
 695                 /*
 696                  * For LVDS, if the panel is on, just rely on its current
 697                  * settings for dual-channel.  We haven't figured out how to
 698                  * reliably set up different single/dual channel state, if we
 699                  * even can.
 700                  */
 701                 if (is_dual_link_lvds(dev_priv, LVDS))
 702                         clock.p2 = limit->p2.p2_fast;
 703                 else
 704                         clock.p2 = limit->p2.p2_slow;
 705         } else {
 706                 if (target < limit->p2.dot_limit)
 707                         clock.p2 = limit->p2.p2_slow;
 708                 else
 709                         clock.p2 = limit->p2.p2_fast;
 710         }
 711
 712         memset(best_clock, 0, sizeof(*best_clock));
 713
 714         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 715              clock.m1++) {
 716                 for (clock.m2 = limit->m2.min;
 717                      clock.m2 <= limit->m2.max; clock.m2++) {
 718                         /* m1 is always 0 in Pineview */
 719                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 720                                 break;
 721                         for (clock.n = limit->n.min;
 722                              clock.n <= limit->n.max; clock.n++) {
 723                                 for (clock.p1 = limit->p1.min;
 724                                         clock.p1 <= limit->p1.max; clock.p1++) {
 725                                         int this_err;
 726
 727                                         intel_clock(dev, refclk, &clock);
 728                                         if (!intel_PLL_is_valid(dev, limit,
 729                                                                 &clock))
 730                                                 continue;
 731                                         if (match_clock &&
 732                                             clock.p != match_clock->p)
 733                                                 continue;
 734
 735                                         this_err = abs(clock.dot - target);
 736                                         if (this_err < err) {
 737                                                 *best_clock = clock;
 738                                                 err = this_err;
 739                                         }
 740                                 }
 741                         }
 742                 }
 743         }
 744
 745         return (err != target);
 746 }
 747
 748 static bool
 749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 750                         int target, int refclk, intel_clock_t *match_clock,
 751                         intel_clock_t *best_clock)
 752 {
 753         struct drm_device *dev = crtc->dev;
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         intel_clock_t clock;
 756         int max_n;
 757         bool found;
 758         /* approximately equals target * 0.00585 */
 759         int err_most = (target >> 8) + (target >> 9);
 760         found = false;
 761
 762         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 763                 int lvds_reg;
 764
 765                 if (HAS_PCH_SPLIT(dev))
 766                         lvds_reg = PCH_LVDS;
 767                 else
 768                         lvds_reg = LVDS;
 769                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 770                     LVDS_CLKB_POWER_UP)
 771                         clock.p2 = limit->p2.p2_fast;
 772                 else
 773                         clock.p2 = limit->p2.p2_slow;
 774         } else {
 775                 if (target < limit->p2.dot_limit)
 776                         clock.p2 = limit->p2.p2_slow;
 777                 else
 778                         clock.p2 = limit->p2.p2_fast;
 779         }
 780
 781         memset(best_clock, 0, sizeof(*best_clock));
 782         max_n = limit->n.max;
 783         /* based on hardware requirement, prefer smaller n to precision */
 784         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 785                 /* based on hardware requirement, prefere larger m1,m2 */
 786                 for (clock.m1 = limit->m1.max;
 787                      clock.m1 >= limit->m1.min; clock.m1--) {
 788                         for (clock.m2 = limit->m2.max;
 789                              clock.m2 >= limit->m2.min; clock.m2--) {
 790                                 for (clock.p1 = limit->p1.max;
 791                                      clock.p1 >= limit->p1.min; clock.p1--) {
 792                                         int this_err;
 793
 794                                         intel_clock(dev, refclk, &clock);
 795                                         if (!intel_PLL_is_valid(dev, limit,
 796                                                                 &clock))
 797                                                 continue;
 798                                         if (match_clock &&
 799                                             clock.p != match_clock->p)
 800                                                 continue;
 801
 802                                         this_err = abs(clock.dot - target);
 803                                         if (this_err < err_most) {
 804                                                 *best_clock = clock;
 805                                                 err_most = this_err;
 806                                                 max_n = clock.n;
 807                                                 found = true;
 808                                         }
 809                                 }
 810                         }
 811                 }
 812         }
 813         return found;
 814 }
 815
 816 static bool
 817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                            int target, int refclk, intel_clock_t *match_clock,
 819                            intel_clock_t *best_clock)
 820 {
 821         struct drm_device *dev = crtc->dev;
 822         intel_clock_t clock;
 823
 824         if (target < 200000) {
 825                 clock.n = 1;
 826                 clock.p1 = 2;
 827                 clock.p2 = 10;
 828                 clock.m1 = 12;
 829                 clock.m2 = 9;
 830         } else {
 831                 clock.n = 2;
 832                 clock.p1 = 1;
 833                 clock.p2 = 10;
 834                 clock.m1 = 14;
 835                 clock.m2 = 8;
 836         }
 837         intel_clock(dev, refclk, &clock);
 838         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 839         return true;
 840 }
 841
 842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 843 static bool
 844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 845                       int target, int refclk, intel_clock_t *match_clock,
 846                       intel_clock_t *best_clock)
 847 {
 848         intel_clock_t clock;
 849         if (target < 200000) {
 850                 clock.p1 = 2;
 851                 clock.p2 = 10;
 852                 clock.n = 2;
 853                 clock.m1 = 23;
 854                 clock.m2 = 8;
 855         } else {
 856                 clock.p1 = 1;
 857                 clock.p2 = 10;
 858                 clock.n = 1;
 859                 clock.m1 = 14;
 860                 clock.m2 = 2;
 861         }
 862         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 863         clock.p = (clock.p1 * clock.p2);
 864         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 865         clock.vco = 0;
 866         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 867         return true;
 868 }
 869 static bool
 870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 871                         int target, int refclk, intel_clock_t *match_clock,
 872                         intel_clock_t *best_clock)
 873 {
 874         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 875         u32 m, n, fastclk;
 876         u32 updrate, minupdate, fracbits, p;
 877         unsigned long bestppm, ppm, absppm;
 878         int dotclk, flag;
 879
 880         flag = 0;
 881         dotclk = target * 1000;
 882         bestppm = 1000000;
 883         ppm = absppm = 0;
 884         fastclk = dotclk / (2*100);
 885         updrate = 0;
 886         minupdate = 19200;
 887         fracbits = 1;
 888         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 889         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 890
 891         /* based on hardware requirement, prefer smaller n to precision */
 892         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 893                 updrate = refclk / n;
 894                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 895                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 896                                 if (p2 > 10)
 897                                         p2 = p2 - 1;
 898                                 p = p1 * p2;
 899                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 900                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 901                                         m2 = (((2*(fastclk * p * n / m1 )) +
 902                                                refclk) / (2*refclk));
 903                                         m = m1 * m2;
 904                                         vco = updrate * m;
 905                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 906                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 907                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 908                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 909                                                         bestppm = 0;
 910                                                         flag = 1;
 911                                                 }
 912                                                 if (absppm < bestppm - 10) {
 913                                                         bestppm = absppm;
 914                                                         flag = 1;
 915                                                 }
 916                                                 if (flag) {
 917                                                         bestn = n;
 918                                                         bestm1 = m1;
 919                                                         bestm2 = m2;
 920                                                         bestp1 = p1;
 921                                                         bestp2 = p2;
 922                                                         flag = 0;
 923                                                 }
 924                                         }
 925                                 }
 926                         }
 927                 }
 928         }
 929         best_clock->n = bestn;
 930         best_clock->m1 = bestm1;
 931         best_clock->m2 = bestm2;
 932         best_clock->p1 = bestp1;
 933         best_clock->p2 = bestp2;
 934
 935         return true;
 936 }
 937
 938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 939                                              enum pipe pipe)
 940 {
 941         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 943
 944         return intel_crtc->cpu_transcoder;
 945 }
 946
 947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 948 {
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         u32 frame, frame_reg = PIPEFRAME(pipe);
 951
 952         frame = I915_READ(frame_reg);
 953
 954         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 955                 DRM_DEBUG_KMS("vblank wait timed out\n");
 956 }
 957
 958 /**
 959  * intel_wait_for_vblank - wait for vblank on a given pipe
 960  * @dev: drm device
 961  * @pipe: pipe to wait for
 962  *
 963  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 964  * mode setting code.
 965  */
 966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 967 {
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         int pipestat_reg = PIPESTAT(pipe);
 970
 971         if (INTEL_INFO(dev)->gen >= 5) {
 972                 ironlake_wait_for_vblank(dev, pipe);
 973                 return;
 974         }
 975
 976         /* Clear existing vblank status. Note this will clear any other
 977          * sticky status fields as well.
 978          *
 979          * This races with i915_driver_irq_handler() with the result
 980          * that either function could miss a vblank event.  Here it is not
 981          * fatal, as we will either wait upon the next vblank interrupt or
 982          * timeout.  Generally speaking intel_wait_for_vblank() is only
 983          * called during modeset at which time the GPU should be idle and
 984          * should *not* be performing page flips and thus not waiting on
 985          * vblanks...
 986          * Currently, the result of us stealing a vblank from the irq
 987          * handler is that a single frame will be skipped during swapbuffers.
 988          */
 989         I915_WRITE(pipestat_reg,
 990                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 991
 992         /* Wait for vblank interrupt bit to set */
 993         if (wait_for(I915_READ(pipestat_reg) &
 994                      PIPE_VBLANK_INTERRUPT_STATUS,
 995                      50))
 996                 DRM_DEBUG_KMS("vblank wait timed out\n");
 997 }
 998
 999 /*
1000  * intel_wait_for_pipe_off - wait for pipe to turn off
1001  * @dev: drm device
1002  * @pipe: pipe to wait for
1003  *
1004  * After disabling a pipe, we can't wait for vblank in the usual way,
1005  * spinning on the vblank interrupt status bit, since we won't actually
1006  * see an interrupt when the pipe is disabled.
1007  *
1008  * On Gen4 and above:
1009  *   wait for the pipe register state bit to turn off
1010  *
1011  * Otherwise:
1012  *   wait for the display line value to settle (it usually
1013  *   ends up stopping at the start of the next frame).
1014  *
1015  */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020                                                                       pipe);
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(cpu_transcoder);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126                                                                       pipe);
1127
1128         if (IS_HASWELL(dev_priv->dev)) {
1129                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 reg = FDI_TX_CTL(pipe);
1135                 val = I915_READ(reg);
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151
1152         reg = FDI_RX_CTL(pipe);
1153         val = I915_READ(reg);
1154         cur_state = !!(val & FDI_RX_ENABLE);
1155         WARN(cur_state != state,
1156              "FDI RX state assertion failure (expected %s, current %s)\n",
1157              state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163                                       enum pipe pipe)
1164 {
1165         int reg;
1166         u32 val;
1167
1168         /* ILK FDI PLL is always enabled */
1169         if (dev_priv->info->gen == 5)
1170                 return;
1171
1172         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173         if (IS_HASWELL(dev_priv->dev))
1174                 return;
1175
1176         reg = FDI_TX_CTL(pipe);
1177         val = I915_READ(reg);
1178         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182                                       enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         reg = FDI_RX_CTL(pipe);
1188         val = I915_READ(reg);
1189         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222                  enum pipe pipe, bool state)
1223 {
1224         int reg;
1225         u32 val;
1226         bool cur_state;
1227         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228                                                                       pipe);
1229
1230         /* if we need the pipe A quirk it must be always on */
1231         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232                 state = true;
1233
1234         reg = PIPECONF(cpu_transcoder);
1235         val = I915_READ(reg);
1236         cur_state = !!(val & PIPECONF_ENABLE);
1237         WARN(cur_state != state,
1238              "pipe %c assertion failure (expected %s, current %s)\n",
1239              pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243                          enum plane plane, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = DSPCNTR(plane);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252         WARN(cur_state != state,
1253              "plane %c assertion failure (expected %s, current %s)\n",
1254              plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261                                    enum pipe pipe)
1262 {
1263         int reg, i;
1264         u32 val;
1265         int cur_pipe;
1266
1267         /* Planes are fixed to pipes on ILK+ */
1268         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269                 reg = DSPCNTR(pipe);
1270                 val = I915_READ(reg);
1271                 WARN((val & DISPLAY_PLANE_ENABLE),
1272                      "plane %c assertion failure, should be disabled but not\n",
1273                      plane_name(pipe));
1274                 return;
1275         }
1276
1277         /* Need to check both planes against the pipe */
1278         for (i = 0; i < 2; i++) {
1279                 reg = DSPCNTR(i);
1280                 val = I915_READ(reg);
1281                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282                         DISPPLANE_SEL_PIPE_SHIFT;
1283                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285                      plane_name(i), pipe_name(pipe));
1286         }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291         u32 val;
1292         bool enabled;
1293
1294         if (HAS_PCH_LPT(dev_priv->dev)) {
1295                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296                 return;
1297         }
1298
1299         val = I915_READ(PCH_DREF_CONTROL);
1300         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301                             DREF_SUPERSPREAD_SOURCE_MASK));
1302         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306                                        enum pipe pipe)
1307 {
1308         int reg;
1309         u32 val;
1310         bool enabled;
1311
1312         reg = TRANSCONF(pipe);
1313         val = I915_READ(reg);
1314         enabled = !!(val & TRANS_ENABLE);
1315         WARN(enabled,
1316              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317              pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321                             enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323         if ((val & DP_PORT_EN) == 0)
1324                 return false;
1325
1326         if (HAS_PCH_CPT(dev_priv->dev)) {
1327                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330                         return false;
1331         } else {
1332                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333                         return false;
1334         }
1335         return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339                               enum pipe pipe, u32 val)
1340 {
1341         if ((val & PORT_ENABLE) == 0)
1342                 return false;
1343
1344         if (HAS_PCH_CPT(dev_priv->dev)) {
1345                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346                         return false;
1347         } else {
1348                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349                         return false;
1350         }
1351         return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355                               enum pipe pipe, u32 val)
1356 {
1357         if ((val & LVDS_PORT_EN) == 0)
1358                 return false;
1359
1360         if (HAS_PCH_CPT(dev_priv->dev)) {
1361                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & ADPA_DAC_ENABLE) == 0)
1374                 return false;
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe, int reg, u32 port_sel)
1387 {
1388         u32 val = I915_READ(reg);
1389         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391              reg, pipe_name(pipe));
1392
1393         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394              && (val & DP_PIPEB_SELECT),
1395              "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399                                      enum pipe pipe, int reg)
1400 {
1401         u32 val = I915_READ(reg);
1402         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404              reg, pipe_name(pipe));
1405
1406         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407              && (val & SDVO_PIPE_B_SELECT),
1408              "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412                                       enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421         reg = PCH_ADPA;
1422         val = I915_READ(reg);
1423         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424              "PCH VGA enabled on transcoder %c, should be disabled\n",
1425              pipe_name(pipe));
1426
1427         reg = PCH_LVDS;
1428         val = I915_READ(reg);
1429         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431              pipe_name(pipe));
1432
1433         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439  * intel_enable_pll - enable a PLL
1440  * @dev_priv: i915 private structure
1441  * @pipe: pipe PLL to enable
1442  *
1443  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1444  * make sure the PLL reg is writable first though, since the panel write
1445  * protect mechanism may be enabled.
1446  *
1447  * Note!  This is for pre-ILK only.
1448  *
1449  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450  */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453         int reg;
1454         u32 val;
1455
1456         /* No really, not for ILK+ */
1457         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459         /* PLL is protected by panel, make sure we can write it */
1460         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461                 assert_panel_unlocked(dev_priv, pipe);
1462
1463         reg = DPLL(pipe);
1464         val = I915_READ(reg);
1465         val |= DPLL_VCO_ENABLE;
1466
1467         /* We do this three times for luck */
1468         I915_WRITE(reg, val);
1469         POSTING_READ(reg);
1470         udelay(150); /* wait for warmup */
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, val);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480  * intel_disable_pll - disable a PLL
1481  * @dev_priv: i915 private structure
1482  * @pipe: pipe PLL to disable
1483  *
1484  * Disable the PLL for @pipe, making sure the pipe is off first.
1485  *
1486  * Note!  This is for pre-ILK only.
1487  */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490         int reg;
1491         u32 val;
1492
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         reg = DPLL(pipe);
1501         val = I915_READ(reg);
1502         val &= ~DPLL_VCO_ENABLE;
1503         I915_WRITE(reg, val);
1504         POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510 {
1511         unsigned long flags;
1512
1513         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517                 goto out_unlock;
1518         }
1519
1520         I915_WRITE(SBI_ADDR,
1521                         (reg << 16));
1522         I915_WRITE(SBI_DATA,
1523                         value);
1524         I915_WRITE(SBI_CTL_STAT,
1525                         SBI_BUSY |
1526                         SBI_CTL_OP_CRWR);
1527
1528         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1529                                 100)) {
1530                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531                 goto out_unlock;
1532         }
1533
1534 out_unlock:
1535         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536 }
1537
1538 static u32
1539 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540 {
1541         unsigned long flags;
1542         u32 value = 0;
1543
1544         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1545         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1546                                 100)) {
1547                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548                 goto out_unlock;
1549         }
1550
1551         I915_WRITE(SBI_ADDR,
1552                         (reg << 16));
1553         I915_WRITE(SBI_CTL_STAT,
1554                         SBI_BUSY |
1555                         SBI_CTL_OP_CRRD);
1556
1557         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1558                                 100)) {
1559                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560                 goto out_unlock;
1561         }
1562
1563         value = I915_READ(SBI_DATA);
1564
1565 out_unlock:
1566         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567         return value;
1568 }
1569
1570 /**
1571  * ironlake_enable_pch_pll - enable PCH PLL
1572  * @dev_priv: i915 private structure
1573  * @pipe: pipe PLL to enable
1574  *
1575  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576  * drives the transcoder clock.
1577  */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581         struct intel_pch_pll *pll;
1582         int reg;
1583         u32 val;
1584
1585         /* PCH PLLs only available on ILK, SNB and IVB */
1586         BUG_ON(dev_priv->info->gen < 5);
1587         pll = intel_crtc->pch_pll;
1588         if (pll == NULL)
1589                 return;
1590
1591         if (WARN_ON(pll->refcount == 0))
1592                 return;
1593
1594         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595                       pll->pll_reg, pll->active, pll->on,
1596                       intel_crtc->base.base.id);
1597
1598         /* PCH refclock must be enabled first */
1599         assert_pch_refclk_enabled(dev_priv);
1600
1601         if (pll->active++ && pll->on) {
1602                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603                 return;
1604         }
1605
1606         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608         reg = pll->pll_reg;
1609         val = I915_READ(reg);
1610         val |= DPLL_VCO_ENABLE;
1611         I915_WRITE(reg, val);
1612         POSTING_READ(reg);
1613         udelay(200);
1614
1615         pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622         int reg;
1623         u32 val;
1624
1625         /* PCH only available on ILK+ */
1626         BUG_ON(dev_priv->info->gen < 5);
1627         if (pll == NULL)
1628                return;
1629
1630         if (WARN_ON(pll->refcount == 0))
1631                 return;
1632
1633         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634                       pll->pll_reg, pll->active, pll->on,
1635                       intel_crtc->base.base.id);
1636
1637         if (WARN_ON(pll->active == 0)) {
1638                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639                 return;
1640         }
1641
1642         if (--pll->active) {
1643                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644                 return;
1645         }
1646
1647         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649         /* Make sure transcoder isn't still depending on us */
1650         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652         reg = pll->pll_reg;
1653         val = I915_READ(reg);
1654         val &= ~DPLL_VCO_ENABLE;
1655         I915_WRITE(reg, val);
1656         POSTING_READ(reg);
1657         udelay(200);
1658
1659         pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                            enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667         uint32_t reg, val, pipeconf_val;
1668
1669         /* PCH only available on ILK+ */
1670         BUG_ON(dev_priv->info->gen < 5);
1671
1672         /* Make sure PCH DPLL is enabled */
1673         assert_pch_pll_enabled(dev_priv,
1674                                to_intel_crtc(crtc)->pch_pll,
1675                                to_intel_crtc(crtc));
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, pipe);
1679         assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681         if (HAS_PCH_CPT(dev)) {
1682                 /* Workaround: Set the timing override bit before enabling the
1683                  * pch transcoder. */
1684                 reg = TRANS_CHICKEN2(pipe);
1685                 val = I915_READ(reg);
1686                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv->dev)) {
1695                 /*
1696                  * make the BPC in transcoder be consistent with
1697                  * that in pipeconf reg.
1698                  */
1699                 val &= ~PIPE_BPC_MASK;
1700                 val |= pipeconf_val & PIPE_BPC_MASK;
1701         }
1702
1703         val &= ~TRANS_INTERLACE_MASK;
1704         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705                 if (HAS_PCH_IBX(dev_priv->dev) &&
1706                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707                         val |= TRANS_LEGACY_INTERLACED_ILK;
1708                 else
1709                         val |= TRANS_INTERLACED;
1710         else
1711                 val |= TRANS_PROGRESSIVE;
1712
1713         I915_WRITE(reg, val | TRANS_ENABLE);
1714         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719                                       enum transcoder cpu_transcoder)
1720 {
1721         u32 val, pipeconf_val;
1722
1723         /* PCH only available on ILK+ */
1724         BUG_ON(dev_priv->info->gen < 5);
1725
1726         /* FDI must be feeding us bits for PCH ports */
1727         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730         /* Workaround: set timing override bit. */
1731         val = I915_READ(_TRANSA_CHICKEN2);
1732         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733         I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735         val = TRANS_ENABLE;
1736         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739             PIPECONF_INTERLACED_ILK)
1740                 val |= TRANS_INTERLACED;
1741         else
1742                 val |= TRANS_PROGRESSIVE;
1743
1744         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746                 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                             enum pipe pipe)
1751 {
1752         struct drm_device *dev = dev_priv->dev;
1753         uint32_t reg, val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = TRANSCONF(pipe);
1763         val = I915_READ(reg);
1764         val &= ~TRANS_ENABLE;
1765         I915_WRITE(reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770         if (!HAS_PCH_IBX(dev)) {
1771                 /* Workaround: Clear the timing override chicken bit again. */
1772                 reg = TRANS_CHICKEN2(pipe);
1773                 val = I915_READ(reg);
1774                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775                 I915_WRITE(reg, val);
1776         }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781         u32 val;
1782
1783         val = I915_READ(_TRANSACONF);
1784         val &= ~TRANS_ENABLE;
1785         I915_WRITE(_TRANSACONF, val);
1786         /* wait for PCH transcoder off, transcoder state */
1787         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788                 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790         /* Workaround: clear timing override bit. */
1791         val = I915_READ(_TRANSA_CHICKEN2);
1792         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793         I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797  * intel_enable_pipe - enable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to enable
1800  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801  *
1802  * Enable @pipe, making sure that various hardware specific requirements
1803  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804  *
1805  * @pipe should be %PIPE_A or %PIPE_B.
1806  *
1807  * Will wait until the pipe is actually running (i.e. first vblank) before
1808  * returning.
1809  */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811                               bool pch_port)
1812 {
1813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814                                                                       pipe);
1815         enum transcoder pch_transcoder;
1816         int reg;
1817         u32 val;
1818
1819         if (IS_HASWELL(dev_priv->dev))
1820                 pch_transcoder = TRANSCODER_A;
1821         else
1822                 pch_transcoder = pipe;
1823
1824         /*
1825          * A pipe without a PLL won't actually be able to drive bits from
1826          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1827          * need the check.
1828          */
1829         if (!HAS_PCH_SPLIT(dev_priv->dev))
1830                 assert_pll_enabled(dev_priv, pipe);
1831         else {
1832                 if (pch_port) {
1833                         /* if driving the PCH, we need FDI enabled */
1834                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1836                 }
1837                 /* FIXME: assert CPU port conditions for SNB+ */
1838         }
1839
1840         reg = PIPECONF(cpu_transcoder);
1841         val = I915_READ(reg);
1842         if (val & PIPECONF_ENABLE)
1843                 return;
1844
1845         I915_WRITE(reg, val | PIPECONF_ENABLE);
1846         intel_wait_for_vblank(dev_priv->dev, pipe);
1847 }
1848
1849 /**
1850  * intel_disable_pipe - disable a pipe, asserting requirements
1851  * @dev_priv: i915 private structure
1852  * @pipe: pipe to disable
1853  *
1854  * Disable @pipe, making sure that various hardware specific requirements
1855  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856  *
1857  * @pipe should be %PIPE_A or %PIPE_B.
1858  *
1859  * Will wait until the pipe has shut down before returning.
1860  */
1861 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862                                enum pipe pipe)
1863 {
1864         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865                                                                       pipe);
1866         int reg;
1867         u32 val;
1868
1869         /*
1870          * Make sure planes won't keep trying to pump pixels to us,
1871          * or we might hang the display.
1872          */
1873         assert_planes_disabled(dev_priv, pipe);
1874
1875         /* Don't disable pipe A or pipe A PLLs if needed */
1876         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877                 return;
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = I915_READ(reg);
1881         if ((val & PIPECONF_ENABLE) == 0)
1882                 return;
1883
1884         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1885         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886 }
1887
1888 /*
1889  * Plane regs are double buffered, going from enabled->disabled needs a
1890  * trigger in order to latch.  The display address reg provides this.
1891  */
1892 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1893                                       enum plane plane)
1894 {
1895         if (dev_priv->info->gen >= 4)
1896                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897         else
1898                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1899 }
1900
1901 /**
1902  * intel_enable_plane - enable a display plane on a given pipe
1903  * @dev_priv: i915 private structure
1904  * @plane: plane to enable
1905  * @pipe: pipe being fed
1906  *
1907  * Enable @plane on @pipe, making sure that @pipe is running first.
1908  */
1909 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910                                enum plane plane, enum pipe pipe)
1911 {
1912         int reg;
1913         u32 val;
1914
1915         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916         assert_pipe_enabled(dev_priv, pipe);
1917
1918         reg = DSPCNTR(plane);
1919         val = I915_READ(reg);
1920         if (val & DISPLAY_PLANE_ENABLE)
1921                 return;
1922
1923         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1924         intel_flush_display_plane(dev_priv, plane);
1925         intel_wait_for_vblank(dev_priv->dev, pipe);
1926 }
1927
1928 /**
1929  * intel_disable_plane - disable a display plane
1930  * @dev_priv: i915 private structure
1931  * @plane: plane to disable
1932  * @pipe: pipe consuming the data
1933  *
1934  * Disable @plane; should be an independent operation.
1935  */
1936 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937                                 enum plane plane, enum pipe pipe)
1938 {
1939         int reg;
1940         u32 val;
1941
1942         reg = DSPCNTR(plane);
1943         val = I915_READ(reg);
1944         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945                 return;
1946
1947         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1948         intel_flush_display_plane(dev_priv, plane);
1949         intel_wait_for_vblank(dev_priv->dev, pipe);
1950 }
1951
1952 int
1953 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1954                            struct drm_i915_gem_object *obj,
1955                            struct intel_ring_buffer *pipelined)
1956 {
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         u32 alignment;
1959         int ret;
1960
1961         switch (obj->tiling_mode) {
1962         case I915_TILING_NONE:
1963                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964                         alignment = 128 * 1024;
1965                 else if (INTEL_INFO(dev)->gen >= 4)
1966                         alignment = 4 * 1024;
1967                 else
1968                         alignment = 64 * 1024;
1969                 break;
1970         case I915_TILING_X:
1971                 /* pin() will align the object as required by fence */
1972                 alignment = 0;
1973                 break;
1974         case I915_TILING_Y:
1975                 /* FIXME: Is this true? */
1976                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977                 return -EINVAL;
1978         default:
1979                 BUG();
1980         }
1981
1982         dev_priv->mm.interruptible = false;
1983         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1984         if (ret)
1985                 goto err_interruptible;
1986
1987         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988          * fence, whereas 965+ only requires a fence if using
1989          * framebuffer compression.  For simplicity, we always install
1990          * a fence as the cost is not that onerous.
1991          */
1992         ret = i915_gem_object_get_fence(obj);
1993         if (ret)
1994                 goto err_unpin;
1995
1996         i915_gem_object_pin_fence(obj);
1997
1998         dev_priv->mm.interruptible = true;
1999         return 0;
2000
2001 err_unpin:
2002         i915_gem_object_unpin(obj);
2003 err_interruptible:
2004         dev_priv->mm.interruptible = true;
2005         return ret;
2006 }
2007
2008 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009 {
2010         i915_gem_object_unpin_fence(obj);
2011         i915_gem_object_unpin(obj);
2012 }
2013
2014 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015  * is assumed to be a power-of-two. */
2016 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017                                                unsigned int bpp,
2018                                                unsigned int pitch)
2019 {
2020         int tile_rows, tiles;
2021
2022         tile_rows = *y / 8;
2023         *y %= 8;
2024         tiles = *x / (512/bpp);
2025         *x %= 512/bpp;
2026
2027         return tile_rows * pitch * 8 + tiles * 4096;
2028 }
2029
2030 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031                              int x, int y)
2032 {
2033         struct drm_device *dev = crtc->dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036         struct intel_framebuffer *intel_fb;
2037         struct drm_i915_gem_object *obj;
2038         int plane = intel_crtc->plane;
2039         unsigned long linear_offset;
2040         u32 dspcntr;
2041         u32 reg;
2042
2043         switch (plane) {
2044         case 0:
2045         case 1:
2046                 break;
2047         default:
2048                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049                 return -EINVAL;
2050         }
2051
2052         intel_fb = to_intel_framebuffer(fb);
2053         obj = intel_fb->obj;
2054
2055         reg = DSPCNTR(plane);
2056         dspcntr = I915_READ(reg);
2057         /* Mask out pixel format bits in case we change it */
2058         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2059         switch (fb->pixel_format) {
2060         case DRM_FORMAT_C8:
2061                 dspcntr |= DISPPLANE_8BPP;
2062                 break;
2063         case DRM_FORMAT_XRGB1555:
2064         case DRM_FORMAT_ARGB1555:
2065                 dspcntr |= DISPPLANE_BGRX555;
2066                 break;
2067         case DRM_FORMAT_RGB565:
2068                 dspcntr |= DISPPLANE_BGRX565;
2069                 break;
2070         case DRM_FORMAT_XRGB8888:
2071         case DRM_FORMAT_ARGB8888:
2072                 dspcntr |= DISPPLANE_BGRX888;
2073                 break;
2074         case DRM_FORMAT_XBGR8888:
2075         case DRM_FORMAT_ABGR8888:
2076                 dspcntr |= DISPPLANE_RGBX888;
2077                 break;
2078         case DRM_FORMAT_XRGB2101010:
2079         case DRM_FORMAT_ARGB2101010:
2080                 dspcntr |= DISPPLANE_BGRX101010;
2081                 break;
2082         case DRM_FORMAT_XBGR2101010:
2083         case DRM_FORMAT_ABGR2101010:
2084                 dspcntr |= DISPPLANE_RGBX101010;
2085                 break;
2086         default:
2087                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2088                 return -EINVAL;
2089         }
2090
2091         if (INTEL_INFO(dev)->gen >= 4) {
2092                 if (obj->tiling_mode != I915_TILING_NONE)
2093                         dspcntr |= DISPPLANE_TILED;
2094                 else
2095                         dspcntr &= ~DISPPLANE_TILED;
2096         }
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_offset_xtiled(&x, &y,
2105                                                          fb->bits_per_pixel / 8,
2106                                                          fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2114         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2115         if (INTEL_INFO(dev)->gen >= 4) {
2116                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2118                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2119                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2120         } else
2121                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2122         POSTING_READ(reg);
2123
2124         return 0;
2125 }
2126
2127 static int ironlake_update_plane(struct drm_crtc *crtc,
2128                                  struct drm_framebuffer *fb, int x, int y)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         struct intel_framebuffer *intel_fb;
2134         struct drm_i915_gem_object *obj;
2135         int plane = intel_crtc->plane;
2136         unsigned long linear_offset;
2137         u32 dspcntr;
2138         u32 reg;
2139
2140         switch (plane) {
2141         case 0:
2142         case 1:
2143         case 2:
2144                 break;
2145         default:
2146                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147                 return -EINVAL;
2148         }
2149
2150         intel_fb = to_intel_framebuffer(fb);
2151         obj = intel_fb->obj;
2152
2153         reg = DSPCNTR(plane);
2154         dspcntr = I915_READ(reg);
2155         /* Mask out pixel format bits in case we change it */
2156         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2157         switch (fb->pixel_format) {
2158         case DRM_FORMAT_C8:
2159                 dspcntr |= DISPPLANE_8BPP;
2160                 break;
2161         case DRM_FORMAT_RGB565:
2162                 dspcntr |= DISPPLANE_BGRX565;
2163                 break;
2164         case DRM_FORMAT_XRGB8888:
2165         case DRM_FORMAT_ARGB8888:
2166                 dspcntr |= DISPPLANE_BGRX888;
2167                 break;
2168         case DRM_FORMAT_XBGR8888:
2169         case DRM_FORMAT_ABGR8888:
2170                 dspcntr |= DISPPLANE_RGBX888;
2171                 break;
2172         case DRM_FORMAT_XRGB2101010:
2173         case DRM_FORMAT_ARGB2101010:
2174                 dspcntr |= DISPPLANE_BGRX101010;
2175                 break;
2176         case DRM_FORMAT_XBGR2101010:
2177         case DRM_FORMAT_ABGR2101010:
2178                 dspcntr |= DISPPLANE_RGBX101010;
2179                 break;
2180         default:
2181                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2182                 return -EINVAL;
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         /* must disable */
2191         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193         I915_WRITE(reg, dspcntr);
2194
2195         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2196         intel_crtc->dspaddr_offset =
2197                 intel_gen4_compute_offset_xtiled(&x, &y,
2198                                                  fb->bits_per_pixel / 8,
2199                                                  fb->pitches[0]);
2200         linear_offset -= intel_crtc->dspaddr_offset;
2201
2202         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2204         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2205         I915_MODIFY_DISPBASE(DSPSURF(plane),
2206                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2207         if (IS_HASWELL(dev)) {
2208                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209         } else {
2210                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212         }
2213         POSTING_READ(reg);
2214
2215         return 0;
2216 }
2217
2218 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2219 static int
2220 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221                            int x, int y, enum mode_set_atomic state)
2222 {
2223         struct drm_device *dev = crtc->dev;
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225
2226         if (dev_priv->display.disable_fbc)
2227                 dev_priv->display.disable_fbc(dev);
2228         intel_increase_pllclock(crtc);
2229
2230         return dev_priv->display.update_plane(crtc, fb, x, y);
2231 }
2232
2233 static int
2234 intel_finish_fb(struct drm_framebuffer *old_fb)
2235 {
2236         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238         bool was_interruptible = dev_priv->mm.interruptible;
2239         int ret;
2240
2241         wait_event(dev_priv->pending_flip_queue,
2242                    atomic_read(&dev_priv->mm.wedged) ||
2243                    atomic_read(&obj->pending_flip) == 0);
2244
2245         /* Big Hammer, we also need to ensure that any pending
2246          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247          * current scanout is retired before unpinning the old
2248          * framebuffer.
2249          *
2250          * This should only fail upon a hung GPU, in which case we
2251          * can safely continue.
2252          */
2253         dev_priv->mm.interruptible = false;
2254         ret = i915_gem_object_finish_gpu(obj);
2255         dev_priv->mm.interruptible = was_interruptible;
2256
2257         return ret;
2258 }
2259
2260 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct drm_i915_master_private *master_priv;
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266         if (!dev->primary->master)
2267                 return;
2268
2269         master_priv = dev->primary->master->driver_priv;
2270         if (!master_priv->sarea_priv)
2271                 return;
2272
2273         switch (intel_crtc->pipe) {
2274         case 0:
2275                 master_priv->sarea_priv->pipeA_x = x;
2276                 master_priv->sarea_priv->pipeA_y = y;
2277                 break;
2278         case 1:
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281                 break;
2282         default:
2283                 break;
2284         }
2285 }
2286
2287 static int
2288 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2289                     struct drm_framebuffer *fb)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         struct drm_framebuffer *old_fb;
2295         int ret;
2296
2297         /* no fb bound */
2298         if (!fb) {
2299                 DRM_ERROR("No FB bound\n");
2300                 return 0;
2301         }
2302
2303         if(intel_crtc->plane > dev_priv->num_pipe) {
2304                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305                                 intel_crtc->plane,
2306                                 dev_priv->num_pipe);
2307                 return -EINVAL;
2308         }
2309
2310         mutex_lock(&dev->struct_mutex);
2311         ret = intel_pin_and_fence_fb_obj(dev,
2312                                          to_intel_framebuffer(fb)->obj,
2313                                          NULL);
2314         if (ret != 0) {
2315                 mutex_unlock(&dev->struct_mutex);
2316                 DRM_ERROR("pin & fence failed\n");
2317                 return ret;
2318         }
2319
2320         if (crtc->fb)
2321                 intel_finish_fb(crtc->fb);
2322
2323         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2324         if (ret) {
2325                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2326                 mutex_unlock(&dev->struct_mutex);
2327                 DRM_ERROR("failed to update base address\n");
2328                 return ret;
2329         }
2330
2331         old_fb = crtc->fb;
2332         crtc->fb = fb;
2333         crtc->x = x;
2334         crtc->y = y;
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         intel_update_fbc(dev);
2342         mutex_unlock(&dev->struct_mutex);
2343
2344         intel_crtc_update_sarea_pos(crtc, x, y);
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 static void ivb_modeset_global_resources(struct drm_device *dev)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *pipe_B_crtc =
2443                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444         struct intel_crtc *pipe_C_crtc =
2445                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446         uint32_t temp;
2447
2448         /* When everything is off disable fdi C so that we could enable fdi B
2449          * with all lanes. XXX: This misses the case where a pipe is not using
2450          * any pch resources and so doesn't need any fdi lanes. */
2451         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455                 temp = I915_READ(SOUTH_CHICKEN1);
2456                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458                 I915_WRITE(SOUTH_CHICKEN1, temp);
2459         }
2460 }
2461
2462 /* The FDI link training functions for ILK/Ibexpeak. */
2463 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468         int pipe = intel_crtc->pipe;
2469         int plane = intel_crtc->plane;
2470         u32 reg, temp, tries;
2471
2472         /* FDI needs bits from pipe & plane first */
2473         assert_pipe_enabled(dev_priv, pipe);
2474         assert_plane_enabled(dev_priv, plane);
2475
2476         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477            for train result */
2478         reg = FDI_RX_IMR(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_RX_SYMBOL_LOCK;
2481         temp &= ~FDI_RX_BIT_LOCK;
2482         I915_WRITE(reg, temp);
2483         I915_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         reg = FDI_RX_CTL(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_LINK_TRAIN_NONE;
2498         temp |= FDI_LINK_TRAIN_PATTERN_1;
2499         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         /* Ironlake workaround, enable clock pointer after FDI enable*/
2505         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2506         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507                    FDI_RX_PHASE_SYNC_POINTER_EN);
2508
2509         reg = FDI_RX_IIR(pipe);
2510         for (tries = 0; tries < 5; tries++) {
2511                 temp = I915_READ(reg);
2512                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514                 if ((temp & FDI_RX_BIT_LOCK)) {
2515                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2516                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2517                         break;
2518                 }
2519         }
2520         if (tries == 5)
2521                 DRM_ERROR("FDI train 1 fail!\n");
2522
2523         /* Train 2 */
2524         reg = FDI_TX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~FDI_LINK_TRAIN_NONE;
2527         temp |= FDI_LINK_TRAIN_PATTERN_2;
2528         I915_WRITE(reg, temp);
2529
2530         reg = FDI_RX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_LINK_TRAIN_NONE;
2533         temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         I915_WRITE(reg, temp);
2535
2536         POSTING_READ(reg);
2537         udelay(150);
2538
2539         reg = FDI_RX_IIR(pipe);
2540         for (tries = 0; tries < 5; tries++) {
2541                 temp = I915_READ(reg);
2542                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543
2544                 if (temp & FDI_RX_SYMBOL_LOCK) {
2545                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2546                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2547                         break;
2548                 }
2549         }
2550         if (tries == 5)
2551                 DRM_ERROR("FDI train 2 fail!\n");
2552
2553         DRM_DEBUG_KMS("FDI train done\n");
2554
2555 }
2556
2557 static const int snb_b_fdi_train_param[] = {
2558         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2559         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2560         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2561         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2562 };
2563
2564 /* The FDI link training functions for SNB/Cougarpoint. */
2565 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2566 {
2567         struct drm_device *dev = crtc->dev;
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570         int pipe = intel_crtc->pipe;
2571         u32 reg, temp, i, retry;
2572
2573         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2574            for train result */
2575         reg = FDI_RX_IMR(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_RX_SYMBOL_LOCK;
2578         temp &= ~FDI_RX_BIT_LOCK;
2579         I915_WRITE(reg, temp);
2580
2581         POSTING_READ(reg);
2582         udelay(150);
2583
2584         /* enable CPU FDI TX and PCH FDI RX */
2585         reg = FDI_TX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~(7 << 19);
2588         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_1;
2591         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592         /* SNB-B */
2593         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2594         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2595
2596         I915_WRITE(FDI_RX_MISC(pipe),
2597                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2598
2599         reg = FDI_RX_CTL(pipe);
2600         temp = I915_READ(reg);
2601         if (HAS_PCH_CPT(dev)) {
2602                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2603                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2604         } else {
2605                 temp &= ~FDI_LINK_TRAIN_NONE;
2606                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2607         }
2608         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2609
2610         POSTING_READ(reg);
2611         udelay(150);
2612
2613         cpt_phase_pointer_enable(dev, pipe);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_BIT_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 1 fail!\n");
2641
2642         /* Train 2 */
2643         reg = FDI_TX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2;
2647         if (IS_GEN6(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 /* SNB-B */
2650                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         reg = FDI_RX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         if (HAS_PCH_CPT(dev)) {
2657                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659         } else {
2660                 temp &= ~FDI_LINK_TRAIN_NONE;
2661                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662         }
2663         I915_WRITE(reg, temp);
2664
2665         POSTING_READ(reg);
2666         udelay(150);
2667
2668         for (i = 0; i < 4; i++) {
2669                 reg = FDI_TX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672                 temp |= snb_b_fdi_train_param[i];
2673                 I915_WRITE(reg, temp);
2674
2675                 POSTING_READ(reg);
2676                 udelay(500);
2677
2678                 for (retry = 0; retry < 5; retry++) {
2679                         reg = FDI_RX_IIR(pipe);
2680                         temp = I915_READ(reg);
2681                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682                         if (temp & FDI_RX_SYMBOL_LOCK) {
2683                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2684                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685                                 break;
2686                         }
2687                         udelay(50);
2688                 }
2689                 if (retry < 5)
2690                         break;
2691         }
2692         if (i == 4)
2693                 DRM_ERROR("FDI train 2 fail!\n");
2694
2695         DRM_DEBUG_KMS("FDI train done.\n");
2696 }
2697
2698 /* Manual link training for Ivy Bridge A0 parts */
2699 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2700 {
2701         struct drm_device *dev = crtc->dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704         int pipe = intel_crtc->pipe;
2705         u32 reg, temp, i;
2706
2707         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708            for train result */
2709         reg = FDI_RX_IMR(pipe);
2710         temp = I915_READ(reg);
2711         temp &= ~FDI_RX_SYMBOL_LOCK;
2712         temp &= ~FDI_RX_BIT_LOCK;
2713         I915_WRITE(reg, temp);
2714
2715         POSTING_READ(reg);
2716         udelay(150);
2717
2718         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719                       I915_READ(FDI_RX_IIR(pipe)));
2720
2721         /* enable CPU FDI TX and PCH FDI RX */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~(7 << 19);
2725         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2726         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2727         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2728         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2729         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2730         temp |= FDI_COMPOSITE_SYNC;
2731         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2732
2733         I915_WRITE(FDI_RX_MISC(pipe),
2734                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2735
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_LINK_TRAIN_AUTO;
2739         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2740         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2741         temp |= FDI_COMPOSITE_SYNC;
2742         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743
2744         POSTING_READ(reg);
2745         udelay(150);
2746
2747         cpt_phase_pointer_enable(dev, pipe);
2748
2749         for (i = 0; i < 4; i++) {
2750                 reg = FDI_TX_CTL(pipe);
2751                 temp = I915_READ(reg);
2752                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753                 temp |= snb_b_fdi_train_param[i];
2754                 I915_WRITE(reg, temp);
2755
2756                 POSTING_READ(reg);
2757                 udelay(500);
2758
2759                 reg = FDI_RX_IIR(pipe);
2760                 temp = I915_READ(reg);
2761                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2762
2763                 if (temp & FDI_RX_BIT_LOCK ||
2764                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2765                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2766                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2767                         break;
2768                 }
2769         }
2770         if (i == 4)
2771                 DRM_ERROR("FDI train 1 fail!\n");
2772
2773         /* Train 2 */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780         I915_WRITE(reg, temp);
2781
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2785         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2786         I915_WRITE(reg, temp);
2787
2788         POSTING_READ(reg);
2789         udelay(150);
2790
2791         for (i = 0; i < 4; i++) {
2792                 reg = FDI_TX_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795                 temp |= snb_b_fdi_train_param[i];
2796                 I915_WRITE(reg, temp);
2797
2798                 POSTING_READ(reg);
2799                 udelay(500);
2800
2801                 reg = FDI_RX_IIR(pipe);
2802                 temp = I915_READ(reg);
2803                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805                 if (temp & FDI_RX_SYMBOL_LOCK) {
2806                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2807                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2808                         break;
2809                 }
2810         }
2811         if (i == 4)
2812                 DRM_ERROR("FDI train 2 fail!\n");
2813
2814         DRM_DEBUG_KMS("FDI train done.\n");
2815 }
2816
2817 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2818 {
2819         struct drm_device *dev = intel_crtc->base.dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         int pipe = intel_crtc->pipe;
2822         u32 reg, temp;
2823
2824
2825         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         temp &= ~((0x7 << 19) | (0x7 << 16));
2829         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2830         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2832
2833         POSTING_READ(reg);
2834         udelay(200);
2835
2836         /* Switch from Rawclk to PCDclk */
2837         temp = I915_READ(reg);
2838         I915_WRITE(reg, temp | FDI_PCDCLK);
2839
2840         POSTING_READ(reg);
2841         udelay(200);
2842
2843         /* On Haswell, the PLL configuration for ports and pipes is handled
2844          * separately, as part of DDI setup */
2845         if (!IS_HASWELL(dev)) {
2846                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847                 reg = FDI_TX_CTL(pipe);
2848                 temp = I915_READ(reg);
2849                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2850                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2851
2852                         POSTING_READ(reg);
2853                         udelay(100);
2854                 }
2855         }
2856 }
2857
2858 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2859 {
2860         struct drm_device *dev = intel_crtc->base.dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         int pipe = intel_crtc->pipe;
2863         u32 reg, temp;
2864
2865         /* Switch from PCDclk to Rawclk */
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2869
2870         /* Disable CPU FDI TX PLL */
2871         reg = FDI_TX_CTL(pipe);
2872         temp = I915_READ(reg);
2873         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2874
2875         POSTING_READ(reg);
2876         udelay(100);
2877
2878         reg = FDI_RX_CTL(pipe);
2879         temp = I915_READ(reg);
2880         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2881
2882         /* Wait for the clocks to turn off. */
2883         POSTING_READ(reg);
2884         udelay(100);
2885 }
2886
2887 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2888 {
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890         u32 flags = I915_READ(SOUTH_CHICKEN1);
2891
2892         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2893         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2894         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2895         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2896         POSTING_READ(SOUTH_CHICKEN1);
2897 }
2898 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         u32 reg, temp;
2905
2906         /* disable CPU FDI tx and PCH FDI rx */
2907         reg = FDI_TX_CTL(pipe);
2908         temp = I915_READ(reg);
2909         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910         POSTING_READ(reg);
2911
2912         reg = FDI_RX_CTL(pipe);
2913         temp = I915_READ(reg);
2914         temp &= ~(0x7 << 16);
2915         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2916         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918         POSTING_READ(reg);
2919         udelay(100);
2920
2921         /* Ironlake workaround, disable clock pointer after downing FDI */
2922         if (HAS_PCH_IBX(dev)) {
2923                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2924         } else if (HAS_PCH_CPT(dev)) {
2925                 cpt_phase_pointer_disable(dev, pipe);
2926         }
2927
2928         /* still set train pattern 1 */
2929         reg = FDI_TX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_LINK_TRAIN_NONE;
2932         temp |= FDI_LINK_TRAIN_PATTERN_1;
2933         I915_WRITE(reg, temp);
2934
2935         reg = FDI_RX_CTL(pipe);
2936         temp = I915_READ(reg);
2937         if (HAS_PCH_CPT(dev)) {
2938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940         } else {
2941                 temp &= ~FDI_LINK_TRAIN_NONE;
2942                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943         }
2944         /* BPC in FDI rx is consistent with that in PIPECONF */
2945         temp &= ~(0x07 << 16);
2946         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947         I915_WRITE(reg, temp);
2948
2949         POSTING_READ(reg);
2950         udelay(100);
2951 }
2952
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954 {
2955         struct drm_device *dev = crtc->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         unsigned long flags;
2958         bool pending;
2959
2960         if (atomic_read(&dev_priv->mm.wedged))
2961                 return false;
2962
2963         spin_lock_irqsave(&dev->event_lock, flags);
2964         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965         spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967         return pending;
2968 }
2969
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974
2975         if (crtc->fb == NULL)
2976                 return;
2977
2978         wait_event(dev_priv->pending_flip_queue,
2979                    !intel_crtc_has_pending_flip(crtc));
2980
2981         mutex_lock(&dev->struct_mutex);
2982         intel_finish_fb(crtc->fb);
2983         mutex_unlock(&dev->struct_mutex);
2984 }
2985
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct intel_encoder *intel_encoder;
2990
2991         /*
2992          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993          * must be driven by its own crtc; no sharing is possible.
2994          */
2995         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2996                 switch (intel_encoder->type) {
2997                 case INTEL_OUTPUT_EDP:
2998                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2999                                 return false;
3000                         continue;
3001                 }
3002         }
3003
3004         return true;
3005 }
3006
3007 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008 {
3009         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010 }
3011
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc *crtc)
3014 {
3015         struct drm_device *dev = crtc->dev;
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018         u32 temp;
3019
3020         /* It is necessary to ungate the pixclk gate prior to programming
3021          * the divisors, and gate it back when it is done.
3022          */
3023         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025         /* Disable SSCCTL */
3026         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028                                         SBI_SSCCTL_DISABLE);
3029
3030         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031         if (crtc->mode.clock == 20000) {
3032                 auxdiv = 1;
3033                 divsel = 0x41;
3034                 phaseinc = 0x20;
3035         } else {
3036                 /* The iCLK virtual clock root frequency is in MHz,
3037                  * but the crtc->mode.clock in in KHz. To get the divisors,
3038                  * it is necessary to divide one by another, so we
3039                  * convert the virtual clock precision to KHz here for higher
3040                  * precision.
3041                  */
3042                 u32 iclk_virtual_root_freq = 172800 * 1000;
3043                 u32 iclk_pi_range = 64;
3044                 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047                 msb_divisor_value = desired_divisor / iclk_pi_range;
3048                 pi_value = desired_divisor % iclk_pi_range;
3049
3050                 auxdiv = 0;
3051                 divsel = msb_divisor_value - 2;
3052                 phaseinc = pi_value;
3053         }
3054
3055         /* This should not happen with any sane values */
3056         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062                         crtc->mode.clock,
3063                         auxdiv,
3064                         divsel,
3065                         phasedir,
3066                         phaseinc);
3067
3068         /* Program SSCDIVINTPHASE6 */
3069         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077         intel_sbi_write(dev_priv,
3078                         SBI_SSCDIVINTPHASE6,
3079                         temp);
3080
3081         /* Program SSCAUXDIV */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085         intel_sbi_write(dev_priv,
3086                         SBI_SSCAUXDIV6,
3087                         temp);
3088
3089
3090         /* Enable modulator and associated divider */
3091         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092         temp &= ~SBI_SSCCTL_DISABLE;
3093         intel_sbi_write(dev_priv,
3094                         SBI_SSCCTL6,
3095                         temp);
3096
3097         /* Wait for initialization time */
3098         udelay(24);
3099
3100         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101 }
3102
3103 /*
3104  * Enable PCH resources required for PCH ports:
3105  *   - PCH PLLs
3106  *   - FDI training & RX/TX
3107  *   - update transcoder timings
3108  *   - DP transcoding bits
3109  *   - transcoder
3110  */
3111 static void ironlake_pch_enable(struct drm_crtc *crtc)
3112 {
3113         struct drm_device *dev = crtc->dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116         int pipe = intel_crtc->pipe;
3117         u32 reg, temp;
3118
3119         assert_transcoder_disabled(dev_priv, pipe);
3120
3121         /* Write the TU size bits before fdi link training, so that error
3122          * detection works. */
3123         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
3126         /* For PCH output, training FDI link */
3127         dev_priv->display.fdi_link_train(crtc);
3128
3129         /* XXX: pch pll's can be enabled any time before we enable the PCH
3130          * transcoder, and we actually should do this to not upset any PCH
3131          * transcoder that already use the clock when we share it.
3132          *
3133          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134          * unconditionally resets the pll - we need that to have the right LVDS
3135          * enable sequence. */
3136         ironlake_enable_pch_pll(intel_crtc);
3137
3138         if (HAS_PCH_CPT(dev)) {
3139                 u32 sel;
3140
3141                 temp = I915_READ(PCH_DPLL_SEL);
3142                 switch (pipe) {
3143                 default:
3144                 case 0:
3145                         temp |= TRANSA_DPLL_ENABLE;
3146                         sel = TRANSA_DPLLB_SEL;
3147                         break;
3148                 case 1:
3149                         temp |= TRANSB_DPLL_ENABLE;
3150                         sel = TRANSB_DPLLB_SEL;
3151                         break;
3152                 case 2:
3153                         temp |= TRANSC_DPLL_ENABLE;
3154                         sel = TRANSC_DPLLB_SEL;
3155                         break;
3156                 }
3157                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158                         temp |= sel;
3159                 else
3160                         temp &= ~sel;
3161                 I915_WRITE(PCH_DPLL_SEL, temp);
3162         }
3163
3164         /* set transcoder timing, panel must allow it */
3165         assert_panel_unlocked(dev_priv, pipe);
3166         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3169
3170         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3173         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3174
3175         intel_fdi_normal_train(crtc);
3176
3177         /* For PCH DP, enable TRANS_DP_CTL */
3178         if (HAS_PCH_CPT(dev) &&
3179             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3181                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3185                           TRANS_DP_SYNC_MASK |
3186                           TRANS_DP_BPC_MASK);
3187                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188                          TRANS_DP_ENH_FRAMING);
3189                 temp |= bpc << 9; /* same format but at 11:9 */
3190
3191                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3192                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3193                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3194                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3195
3196                 switch (intel_trans_dp_port_sel(crtc)) {
3197                 case PCH_DP_B:
3198                         temp |= TRANS_DP_PORT_SEL_B;
3199                         break;
3200                 case PCH_DP_C:
3201                         temp |= TRANS_DP_PORT_SEL_C;
3202                         break;
3203                 case PCH_DP_D:
3204                         temp |= TRANS_DP_PORT_SEL_D;
3205                         break;
3206                 default:
3207                         BUG();
3208                 }
3209
3210                 I915_WRITE(reg, temp);
3211         }
3212
3213         ironlake_enable_pch_transcoder(dev_priv, pipe);
3214 }
3215
3216 static void lpt_pch_enable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3222
3223         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3224
3225         lpt_program_iclkip(crtc);
3226
3227         /* Set transcoder timing. */
3228         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3231
3232         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3236
3237         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3238 }
3239
3240 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241 {
3242         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244         if (pll == NULL)
3245                 return;
3246
3247         if (pll->refcount == 0) {
3248                 WARN(1, "bad PCH PLL refcount\n");
3249                 return;
3250         }
3251
3252         --pll->refcount;
3253         intel_crtc->pch_pll = NULL;
3254 }
3255
3256 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257 {
3258         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259         struct intel_pch_pll *pll;
3260         int i;
3261
3262         pll = intel_crtc->pch_pll;
3263         if (pll) {
3264                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265                               intel_crtc->base.base.id, pll->pll_reg);
3266                 goto prepare;
3267         }
3268
3269         if (HAS_PCH_IBX(dev_priv->dev)) {
3270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271                 i = intel_crtc->pipe;
3272                 pll = &dev_priv->pch_plls[i];
3273
3274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275                               intel_crtc->base.base.id, pll->pll_reg);
3276
3277                 goto found;
3278         }
3279
3280         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 /* Only want to check enabled timings first */
3284                 if (pll->refcount == 0)
3285                         continue;
3286
3287                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288                     fp == I915_READ(pll->fp0_reg)) {
3289                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290                                       intel_crtc->base.base.id,
3291                                       pll->pll_reg, pll->refcount, pll->active);
3292
3293                         goto found;
3294                 }
3295         }
3296
3297         /* Ok no matching timings, maybe there's a free one? */
3298         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299                 pll = &dev_priv->pch_plls[i];
3300                 if (pll->refcount == 0) {
3301                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302                                       intel_crtc->base.base.id, pll->pll_reg);
3303                         goto found;
3304                 }
3305         }
3306
3307         return NULL;
3308
3309 found:
3310         intel_crtc->pch_pll = pll;
3311         pll->refcount++;
3312         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313 prepare: /* separate function? */
3314         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3315
3316         /* Wait for the clocks to stabilize before rewriting the regs */
3317         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3318         POSTING_READ(pll->pll_reg);
3319         udelay(150);
3320
3321         I915_WRITE(pll->fp0_reg, fp);
3322         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3323         pll->on = false;
3324         return pll;
3325 }
3326
3327 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 if (wait_for(I915_READ(dslreg) != temp, 5))
3337                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338         }
3339 }
3340
3341 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         struct intel_encoder *encoder;
3347         int pipe = intel_crtc->pipe;
3348         int plane = intel_crtc->plane;
3349         u32 temp;
3350         bool is_pch_port;
3351
3352         WARN_ON(!crtc->enabled);
3353
3354         if (intel_crtc->active)
3355                 return;
3356
3357         intel_crtc->active = true;
3358         intel_update_watermarks(dev);
3359
3360         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3361                 temp = I915_READ(PCH_LVDS);
3362                 if ((temp & LVDS_PORT_EN) == 0)
3363                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3364         }
3365
3366         is_pch_port = ironlake_crtc_driving_pch(crtc);
3367
3368         if (is_pch_port) {
3369                 /* Note: FDI PLL enabling _must_ be done before we enable the
3370                  * cpu pipes, hence this is separate from all the other fdi/pch
3371                  * enabling. */
3372                 ironlake_fdi_pll_enable(intel_crtc);
3373         } else {
3374                 assert_fdi_tx_disabled(dev_priv, pipe);
3375                 assert_fdi_rx_disabled(dev_priv, pipe);
3376         }
3377
3378         for_each_encoder_on_crtc(dev, crtc, encoder)
3379                 if (encoder->pre_enable)
3380                         encoder->pre_enable(encoder);
3381
3382         /* Enable panel fitting for LVDS */
3383         if (dev_priv->pch_pf_size &&
3384             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3385              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3386                 /* Force use of hard-coded filter coefficients
3387                  * as some pre-programmed values are broken,
3388                  * e.g. x201.
3389                  */
3390                 if (IS_IVYBRIDGE(dev))
3391                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392                                                  PF_PIPE_SEL_IVB(pipe));
3393                 else
3394                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3395                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3396                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3397         }
3398
3399         /*
3400          * On ILK+ LUT must be loaded before the pipe is running but with
3401          * clocks enabled
3402          */
3403         intel_crtc_load_lut(crtc);
3404
3405         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3406         intel_enable_plane(dev_priv, plane, pipe);
3407
3408         if (is_pch_port)
3409                 ironlake_pch_enable(crtc);
3410
3411         mutex_lock(&dev->struct_mutex);
3412         intel_update_fbc(dev);
3413         mutex_unlock(&dev->struct_mutex);
3414
3415         intel_crtc_update_cursor(crtc, true);
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 encoder->enable(encoder);
3419
3420         if (HAS_PCH_CPT(dev))
3421                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3422
3423         /*
3424          * There seems to be a race in PCH platform hw (at least on some
3425          * outputs) where an enabled pipe still completes any pageflip right
3426          * away (as if the pipe is off) instead of waiting for vblank. As soon
3427          * as the first vblank happend, everything works as expected. Hence just
3428          * wait for one vblank before returning to avoid strange things
3429          * happening.
3430          */
3431         intel_wait_for_vblank(dev, intel_crtc->pipe);
3432 }
3433
3434 static void haswell_crtc_enable(struct drm_crtc *crtc)
3435 {
3436         struct drm_device *dev = crtc->dev;
3437         struct drm_i915_private *dev_priv = dev->dev_private;
3438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439         struct intel_encoder *encoder;
3440         int pipe = intel_crtc->pipe;
3441         int plane = intel_crtc->plane;
3442         bool is_pch_port;
3443
3444         WARN_ON(!crtc->enabled);
3445
3446         if (intel_crtc->active)
3447                 return;
3448
3449         intel_crtc->active = true;
3450         intel_update_watermarks(dev);
3451
3452         is_pch_port = haswell_crtc_driving_pch(crtc);
3453
3454         if (is_pch_port)
3455                 dev_priv->display.fdi_link_train(crtc);
3456
3457         for_each_encoder_on_crtc(dev, crtc, encoder)
3458                 if (encoder->pre_enable)
3459                         encoder->pre_enable(encoder);
3460
3461         intel_ddi_enable_pipe_clock(intel_crtc);
3462
3463         /* Enable panel fitting for eDP */
3464         if (dev_priv->pch_pf_size &&
3465             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3466                 /* Force use of hard-coded filter coefficients
3467                  * as some pre-programmed values are broken,
3468                  * e.g. x201.
3469                  */
3470                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3471                                          PF_PIPE_SEL_IVB(pipe));
3472                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3473                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3474         }
3475
3476         /*
3477          * On ILK+ LUT must be loaded before the pipe is running but with
3478          * clocks enabled
3479          */
3480         intel_crtc_load_lut(crtc);
3481
3482         intel_ddi_set_pipe_settings(crtc);
3483         intel_ddi_enable_pipe_func(crtc);
3484
3485         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3486         intel_enable_plane(dev_priv, plane, pipe);
3487
3488         if (is_pch_port)
3489                 lpt_pch_enable(crtc);
3490
3491         mutex_lock(&dev->struct_mutex);
3492         intel_update_fbc(dev);
3493         mutex_unlock(&dev->struct_mutex);
3494
3495         intel_crtc_update_cursor(crtc, true);
3496
3497         for_each_encoder_on_crtc(dev, crtc, encoder)
3498                 encoder->enable(encoder);
3499
3500         /*
3501          * There seems to be a race in PCH platform hw (at least on some
3502          * outputs) where an enabled pipe still completes any pageflip right
3503          * away (as if the pipe is off) instead of waiting for vblank. As soon
3504          * as the first vblank happend, everything works as expected. Hence just
3505          * wait for one vblank before returning to avoid strange things
3506          * happening.
3507          */
3508         intel_wait_for_vblank(dev, intel_crtc->pipe);
3509 }
3510
3511 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3512 {
3513         struct drm_device *dev = crtc->dev;
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         struct intel_encoder *encoder;
3517         int pipe = intel_crtc->pipe;
3518         int plane = intel_crtc->plane;
3519         u32 reg, temp;
3520
3521
3522         if (!intel_crtc->active)
3523                 return;
3524
3525         for_each_encoder_on_crtc(dev, crtc, encoder)
3526                 encoder->disable(encoder);
3527
3528         intel_crtc_wait_for_pending_flips(crtc);
3529         drm_vblank_off(dev, pipe);
3530         intel_crtc_update_cursor(crtc, false);
3531
3532         intel_disable_plane(dev_priv, plane, pipe);
3533
3534         if (dev_priv->cfb_plane == plane)
3535                 intel_disable_fbc(dev);
3536
3537         intel_disable_pipe(dev_priv, pipe);
3538
3539         /* Disable PF */
3540         I915_WRITE(PF_CTL(pipe), 0);
3541         I915_WRITE(PF_WIN_SZ(pipe), 0);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         ironlake_fdi_disable(crtc);
3548
3549         ironlake_disable_pch_transcoder(dev_priv, pipe);
3550
3551         if (HAS_PCH_CPT(dev)) {
3552                 /* disable TRANS_DP_CTL */
3553                 reg = TRANS_DP_CTL(pipe);
3554                 temp = I915_READ(reg);
3555                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3556                 temp |= TRANS_DP_PORT_SEL_NONE;
3557                 I915_WRITE(reg, temp);
3558
3559                 /* disable DPLL_SEL */
3560                 temp = I915_READ(PCH_DPLL_SEL);
3561                 switch (pipe) {
3562                 case 0:
3563                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3564                         break;
3565                 case 1:
3566                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3567                         break;
3568                 case 2:
3569                         /* C shares PLL A or B */
3570                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3571                         break;
3572                 default:
3573                         BUG(); /* wtf */
3574                 }
3575                 I915_WRITE(PCH_DPLL_SEL, temp);
3576         }
3577
3578         /* disable PCH DPLL */
3579         intel_disable_pch_pll(intel_crtc);
3580
3581         ironlake_fdi_pll_disable(intel_crtc);
3582
3583         intel_crtc->active = false;
3584         intel_update_watermarks(dev);
3585
3586         mutex_lock(&dev->struct_mutex);
3587         intel_update_fbc(dev);
3588         mutex_unlock(&dev->struct_mutex);
3589 }
3590
3591 static void haswell_crtc_disable(struct drm_crtc *crtc)
3592 {
3593         struct drm_device *dev = crtc->dev;
3594         struct drm_i915_private *dev_priv = dev->dev_private;
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         struct intel_encoder *encoder;
3597         int pipe = intel_crtc->pipe;
3598         int plane = intel_crtc->plane;
3599         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3600         bool is_pch_port;
3601
3602         if (!intel_crtc->active)
3603                 return;
3604
3605         is_pch_port = haswell_crtc_driving_pch(crtc);
3606
3607         for_each_encoder_on_crtc(dev, crtc, encoder)
3608                 encoder->disable(encoder);
3609
3610         intel_crtc_wait_for_pending_flips(crtc);
3611         drm_vblank_off(dev, pipe);
3612         intel_crtc_update_cursor(crtc, false);
3613
3614         intel_disable_plane(dev_priv, plane, pipe);
3615
3616         if (dev_priv->cfb_plane == plane)
3617                 intel_disable_fbc(dev);
3618
3619         intel_disable_pipe(dev_priv, pipe);
3620
3621         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3622
3623         /* Disable PF */
3624         I915_WRITE(PF_CTL(pipe), 0);
3625         I915_WRITE(PF_WIN_SZ(pipe), 0);
3626
3627         intel_ddi_disable_pipe_clock(intel_crtc);
3628
3629         for_each_encoder_on_crtc(dev, crtc, encoder)
3630                 if (encoder->post_disable)
3631                         encoder->post_disable(encoder);
3632
3633         if (is_pch_port) {
3634                 lpt_disable_pch_transcoder(dev_priv);
3635                 intel_ddi_fdi_disable(crtc);
3636         }
3637
3638         intel_crtc->active = false;
3639         intel_update_watermarks(dev);
3640
3641         mutex_lock(&dev->struct_mutex);
3642         intel_update_fbc(dev);
3643         mutex_unlock(&dev->struct_mutex);
3644 }
3645
3646 static void ironlake_crtc_off(struct drm_crtc *crtc)
3647 {
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         intel_put_pch_pll(intel_crtc);
3650 }
3651
3652 static void haswell_crtc_off(struct drm_crtc *crtc)
3653 {
3654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655
3656         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3657          * start using it. */
3658         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3659
3660         intel_ddi_put_crtc_pll(crtc);
3661 }
3662
3663 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3664 {
3665         if (!enable && intel_crtc->overlay) {
3666                 struct drm_device *dev = intel_crtc->base.dev;
3667                 struct drm_i915_private *dev_priv = dev->dev_private;
3668
3669                 mutex_lock(&dev->struct_mutex);
3670                 dev_priv->mm.interruptible = false;
3671                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3672                 dev_priv->mm.interruptible = true;
3673                 mutex_unlock(&dev->struct_mutex);
3674         }
3675
3676         /* Let userspace switch the overlay on again. In most cases userspace
3677          * has to recompute where to put it anyway.
3678          */
3679 }
3680
3681 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3682 {
3683         struct drm_device *dev = crtc->dev;
3684         struct drm_i915_private *dev_priv = dev->dev_private;
3685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3686         struct intel_encoder *encoder;
3687         int pipe = intel_crtc->pipe;
3688         int plane = intel_crtc->plane;
3689
3690         WARN_ON(!crtc->enabled);
3691
3692         if (intel_crtc->active)
3693                 return;
3694
3695         intel_crtc->active = true;
3696         intel_update_watermarks(dev);
3697
3698         intel_enable_pll(dev_priv, pipe);
3699         intel_enable_pipe(dev_priv, pipe, false);
3700         intel_enable_plane(dev_priv, plane, pipe);
3701
3702         intel_crtc_load_lut(crtc);
3703         intel_update_fbc(dev);
3704
3705         /* Give the overlay scaler a chance to enable if it's on this pipe */
3706         intel_crtc_dpms_overlay(intel_crtc, true);
3707         intel_crtc_update_cursor(crtc, true);
3708
3709         for_each_encoder_on_crtc(dev, crtc, encoder)
3710                 encoder->enable(encoder);
3711 }
3712
3713 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3714 {
3715         struct drm_device *dev = crtc->dev;
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3718         struct intel_encoder *encoder;
3719         int pipe = intel_crtc->pipe;
3720         int plane = intel_crtc->plane;
3721
3722
3723         if (!intel_crtc->active)
3724                 return;
3725
3726         for_each_encoder_on_crtc(dev, crtc, encoder)
3727                 encoder->disable(encoder);
3728
3729         /* Give the overlay scaler a chance to disable if it's on this pipe */
3730         intel_crtc_wait_for_pending_flips(crtc);
3731         drm_vblank_off(dev, pipe);
3732         intel_crtc_dpms_overlay(intel_crtc, false);
3733         intel_crtc_update_cursor(crtc, false);
3734
3735         if (dev_priv->cfb_plane == plane)
3736                 intel_disable_fbc(dev);
3737
3738         intel_disable_plane(dev_priv, plane, pipe);
3739         intel_disable_pipe(dev_priv, pipe);
3740         intel_disable_pll(dev_priv, pipe);
3741
3742         intel_crtc->active = false;
3743         intel_update_fbc(dev);
3744         intel_update_watermarks(dev);
3745 }
3746
3747 static void i9xx_crtc_off(struct drm_crtc *crtc)
3748 {
3749 }
3750
3751 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3752                                     bool enabled)
3753 {
3754         struct drm_device *dev = crtc->dev;
3755         struct drm_i915_master_private *master_priv;
3756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757         int pipe = intel_crtc->pipe;
3758
3759         if (!dev->primary->master)
3760                 return;
3761
3762         master_priv = dev->primary->master->driver_priv;
3763         if (!master_priv->sarea_priv)
3764                 return;
3765
3766         switch (pipe) {
3767         case 0:
3768                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3769                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3770                 break;
3771         case 1:
3772                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3773                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3774                 break;
3775         default:
3776                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3777                 break;
3778         }
3779 }
3780
3781 /**
3782  * Sets the power management mode of the pipe and plane.
3783  */
3784 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3785 {
3786         struct drm_device *dev = crtc->dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         struct intel_encoder *intel_encoder;
3789         bool enable = false;
3790
3791         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3792                 enable |= intel_encoder->connectors_active;
3793
3794         if (enable)
3795                 dev_priv->display.crtc_enable(crtc);
3796         else
3797                 dev_priv->display.crtc_disable(crtc);
3798
3799         intel_crtc_update_sarea(crtc, enable);
3800 }
3801
3802 static void intel_crtc_noop(struct drm_crtc *crtc)
3803 {
3804 }
3805
3806 static void intel_crtc_disable(struct drm_crtc *crtc)
3807 {
3808         struct drm_device *dev = crtc->dev;
3809         struct drm_connector *connector;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811
3812         /* crtc should still be enabled when we disable it. */
3813         WARN_ON(!crtc->enabled);
3814
3815         dev_priv->display.crtc_disable(crtc);
3816         intel_crtc_update_sarea(crtc, false);
3817         dev_priv->display.off(crtc);
3818
3819         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3820         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3821
3822         if (crtc->fb) {
3823                 mutex_lock(&dev->struct_mutex);
3824                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3825                 mutex_unlock(&dev->struct_mutex);
3826                 crtc->fb = NULL;
3827         }
3828
3829         /* Update computed state. */
3830         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3831                 if (!connector->encoder || !connector->encoder->crtc)
3832                         continue;
3833
3834                 if (connector->encoder->crtc != crtc)
3835                         continue;
3836
3837                 connector->dpms = DRM_MODE_DPMS_OFF;
3838                 to_intel_encoder(connector->encoder)->connectors_active = false;
3839         }
3840 }
3841
3842 void intel_modeset_disable(struct drm_device *dev)
3843 {
3844         struct drm_crtc *crtc;
3845
3846         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3847                 if (crtc->enabled)
3848                         intel_crtc_disable(crtc);
3849         }
3850 }
3851
3852 void intel_encoder_noop(struct drm_encoder *encoder)
3853 {
3854 }
3855
3856 void intel_encoder_destroy(struct drm_encoder *encoder)
3857 {
3858         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3859
3860         drm_encoder_cleanup(encoder);
3861         kfree(intel_encoder);
3862 }
3863
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866  * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3868 {
3869         if (mode == DRM_MODE_DPMS_ON) {
3870                 encoder->connectors_active = true;
3871
3872                 intel_crtc_update_dpms(encoder->base.crtc);
3873         } else {
3874                 encoder->connectors_active = false;
3875
3876                 intel_crtc_update_dpms(encoder->base.crtc);
3877         }
3878 }
3879
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881  * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector *connector)
3883 {
3884         if (connector->get_hw_state(connector)) {
3885                 struct intel_encoder *encoder = connector->encoder;
3886                 struct drm_crtc *crtc;
3887                 bool encoder_enabled;
3888                 enum pipe pipe;
3889
3890                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891                               connector->base.base.id,
3892                               drm_get_connector_name(&connector->base));
3893
3894                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895                      "wrong connector dpms state\n");
3896                 WARN(connector->base.encoder != &encoder->base,
3897                      "active connector not linked to encoder\n");
3898                 WARN(!encoder->connectors_active,
3899                      "encoder->connectors_active not set\n");
3900
3901                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902                 WARN(!encoder_enabled, "encoder not enabled\n");
3903                 if (WARN_ON(!encoder->base.crtc))
3904                         return;
3905
3906                 crtc = encoder->base.crtc;
3907
3908                 WARN(!crtc->enabled, "crtc not enabled\n");
3909                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911                      "encoder active on the wrong pipe\n");
3912         }
3913 }
3914
3915 /* Even simpler default implementation, if there's really no special case to
3916  * consider. */
3917 void intel_connector_dpms(struct drm_connector *connector, int mode)
3918 {
3919         struct intel_encoder *encoder = intel_attached_encoder(connector);
3920
3921         /* All the simple cases only support two dpms states. */
3922         if (mode != DRM_MODE_DPMS_ON)
3923                 mode = DRM_MODE_DPMS_OFF;
3924
3925         if (mode == connector->dpms)
3926                 return;
3927
3928         connector->dpms = mode;
3929
3930         /* Only need to change hw state when actually enabled */
3931         if (encoder->base.crtc)
3932                 intel_encoder_dpms(encoder, mode);
3933         else
3934                 WARN_ON(encoder->connectors_active != false);
3935
3936         intel_modeset_check_state(connector->dev);
3937 }
3938
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940  * one connector and no cloning and hence the encoder state determines the state
3941  * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 {
3944         enum pipe pipe = 0;
3945         struct intel_encoder *encoder = connector->encoder;
3946
3947         return encoder->get_hw_state(encoder, &pipe);
3948 }
3949
3950 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3951                                   const struct drm_display_mode *mode,
3952                                   struct drm_display_mode *adjusted_mode)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955
3956         if (HAS_PCH_SPLIT(dev)) {
3957                 /* FDI link clock is fixed at 2.7G */
3958                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3959                         return false;
3960         }
3961
3962         /* All interlaced capable intel hw wants timings in frames. Note though
3963          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3964          * timings, so we need to be careful not to clobber these.*/
3965         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3966                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3967
3968         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3969          * with a hsync front porch of 0.
3970          */
3971         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3972                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3973                 return false;
3974
3975         return true;
3976 }
3977
3978 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3979 {
3980         return 400000; /* FIXME */
3981 }
3982
3983 static int i945_get_display_clock_speed(struct drm_device *dev)
3984 {
3985         return 400000;
3986 }
3987
3988 static int i915_get_display_clock_speed(struct drm_device *dev)
3989 {
3990         return 333000;
3991 }
3992
3993 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3994 {
3995         return 200000;
3996 }
3997
3998 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3999 {
4000         u16 gcfgc = 0;
4001
4002         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4003
4004         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4005                 return 133000;
4006         else {
4007                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4008                 case GC_DISPLAY_CLOCK_333_MHZ:
4009                         return 333000;
4010                 default:
4011                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4012                         return 190000;
4013                 }
4014         }
4015 }
4016
4017 static int i865_get_display_clock_speed(struct drm_device *dev)
4018 {
4019         return 266000;
4020 }
4021
4022 static int i855_get_display_clock_speed(struct drm_device *dev)
4023 {
4024         u16 hpllcc = 0;
4025         /* Assume that the hardware is in the high speed state.  This
4026          * should be the default.
4027          */
4028         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4029         case GC_CLOCK_133_200:
4030         case GC_CLOCK_100_200:
4031                 return 200000;
4032         case GC_CLOCK_166_250:
4033                 return 250000;
4034         case GC_CLOCK_100_133:
4035                 return 133000;
4036         }
4037
4038         /* Shouldn't happen */
4039         return 0;
4040 }
4041
4042 static int i830_get_display_clock_speed(struct drm_device *dev)
4043 {
4044         return 133000;
4045 }
4046
4047 struct fdi_m_n {
4048         u32        tu;
4049         u32        gmch_m;
4050         u32        gmch_n;
4051         u32        link_m;
4052         u32        link_n;
4053 };
4054
4055 static void
4056 fdi_reduce_ratio(u32 *num, u32 *den)
4057 {
4058         while (*num > 0xffffff || *den > 0xffffff) {
4059                 *num >>= 1;
4060                 *den >>= 1;
4061         }
4062 }
4063
4064 static void
4065 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4066                      int link_clock, struct fdi_m_n *m_n)
4067 {
4068         m_n->tu = 64; /* default size */
4069
4070         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4071         m_n->gmch_m = bits_per_pixel * pixel_clock;
4072         m_n->gmch_n = link_clock * nlanes * 8;
4073         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4074
4075         m_n->link_m = pixel_clock;
4076         m_n->link_n = link_clock;
4077         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4078 }
4079
4080 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4081 {
4082         if (i915_panel_use_ssc >= 0)
4083                 return i915_panel_use_ssc != 0;
4084         return dev_priv->lvds_use_ssc
4085                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4086 }
4087
4088 /**
4089  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4090  * @crtc: CRTC structure
4091  * @mode: requested mode
4092  *
4093  * A pipe may be connected to one or more outputs.  Based on the depth of the
4094  * attached framebuffer, choose a good color depth to use on the pipe.
4095  *
4096  * If possible, match the pipe depth to the fb depth.  In some cases, this
4097  * isn't ideal, because the connected output supports a lesser or restricted
4098  * set of depths.  Resolve that here:
4099  *    LVDS typically supports only 6bpc, so clamp down in that case
4100  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4101  *    Displays may support a restricted set as well, check EDID and clamp as
4102  *      appropriate.
4103  *    DP may want to dither down to 6bpc to fit larger modes
4104  *
4105  * RETURNS:
4106  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4107  * true if they don't match).
4108  */
4109 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4110                                          struct drm_framebuffer *fb,
4111                                          unsigned int *pipe_bpp,
4112                                          struct drm_display_mode *mode)
4113 {
4114         struct drm_device *dev = crtc->dev;
4115         struct drm_i915_private *dev_priv = dev->dev_private;
4116         struct drm_connector *connector;
4117         struct intel_encoder *intel_encoder;
4118         unsigned int display_bpc = UINT_MAX, bpc;
4119
4120         /* Walk the encoders & connectors on this crtc, get min bpc */
4121         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4122
4123                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4124                         unsigned int lvds_bpc;
4125
4126                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4127                             LVDS_A3_POWER_UP)
4128                                 lvds_bpc = 8;
4129                         else
4130                                 lvds_bpc = 6;
4131
4132                         if (lvds_bpc < display_bpc) {
4133                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4134                                 display_bpc = lvds_bpc;
4135                         }
4136                         continue;
4137                 }
4138
4139                 /* Not one of the known troublemakers, check the EDID */
4140                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4141                                     head) {
4142                         if (connector->encoder != &intel_encoder->base)
4143                                 continue;
4144
4145                         /* Don't use an invalid EDID bpc value */
4146                         if (connector->display_info.bpc &&
4147                             connector->display_info.bpc < display_bpc) {
4148                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4149                                 display_bpc = connector->display_info.bpc;
4150                         }
4151                 }
4152
4153                 /*
4154                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4155                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4156                  */
4157                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4158                         if (display_bpc > 8 && display_bpc < 12) {
4159                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4160                                 display_bpc = 12;
4161                         } else {
4162                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4163                                 display_bpc = 8;
4164                         }
4165                 }
4166         }
4167
4168         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4169                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4170                 display_bpc = 6;
4171         }
4172
4173         /*
4174          * We could just drive the pipe at the highest bpc all the time and
4175          * enable dithering as needed, but that costs bandwidth.  So choose
4176          * the minimum value that expresses the full color range of the fb but
4177          * also stays within the max display bpc discovered above.
4178          */
4179
4180         switch (fb->depth) {
4181         case 8:
4182                 bpc = 8; /* since we go through a colormap */
4183                 break;
4184         case 15:
4185         case 16:
4186                 bpc = 6; /* min is 18bpp */
4187                 break;
4188         case 24:
4189                 bpc = 8;
4190                 break;
4191         case 30:
4192                 bpc = 10;
4193                 break;
4194         case 48:
4195                 bpc = 12;
4196                 break;
4197         default:
4198                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4199                 bpc = min((unsigned int)8, display_bpc);
4200                 break;
4201         }
4202
4203         display_bpc = min(display_bpc, bpc);
4204
4205         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4206                       bpc, display_bpc);
4207
4208         *pipe_bpp = display_bpc * 3;
4209
4210         return display_bpc != bpc;
4211 }
4212
4213 static int vlv_get_refclk(struct drm_crtc *crtc)
4214 {
4215         struct drm_device *dev = crtc->dev;
4216         struct drm_i915_private *dev_priv = dev->dev_private;
4217         int refclk = 27000; /* for DP & HDMI */
4218
4219         return 100000; /* only one validated so far */
4220
4221         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4222                 refclk = 96000;
4223         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4224                 if (intel_panel_use_ssc(dev_priv))
4225                         refclk = 100000;
4226                 else
4227                         refclk = 96000;
4228         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4229                 refclk = 100000;
4230         }
4231
4232         return refclk;
4233 }
4234
4235 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239         int refclk;
4240
4241         if (IS_VALLEYVIEW(dev)) {
4242                 refclk = vlv_get_refclk(crtc);
4243         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4244             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4245                 refclk = dev_priv->lvds_ssc_freq * 1000;
4246                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4247                               refclk / 1000);
4248         } else if (!IS_GEN2(dev)) {
4249                 refclk = 96000;
4250         } else {
4251                 refclk = 48000;
4252         }
4253
4254         return refclk;
4255 }
4256
4257 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4258                                       intel_clock_t *clock)
4259 {
4260         /* SDVO TV has fixed PLL values depend on its clock range,
4261            this mirrors vbios setting. */
4262         if (adjusted_mode->clock >= 100000
4263             && adjusted_mode->clock < 140500) {
4264                 clock->p1 = 2;
4265                 clock->p2 = 10;
4266                 clock->n = 3;
4267                 clock->m1 = 16;
4268                 clock->m2 = 8;
4269         } else if (adjusted_mode->clock >= 140500
4270                    && adjusted_mode->clock <= 200000) {
4271                 clock->p1 = 1;
4272                 clock->p2 = 10;
4273                 clock->n = 6;
4274                 clock->m1 = 12;
4275                 clock->m2 = 8;
4276         }
4277 }
4278
4279 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4280                                      intel_clock_t *clock,
4281                                      intel_clock_t *reduced_clock)
4282 {
4283         struct drm_device *dev = crtc->dev;
4284         struct drm_i915_private *dev_priv = dev->dev_private;
4285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286         int pipe = intel_crtc->pipe;
4287         u32 fp, fp2 = 0;
4288
4289         if (IS_PINEVIEW(dev)) {
4290                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4291                 if (reduced_clock)
4292                         fp2 = (1 << reduced_clock->n) << 16 |
4293                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4294         } else {
4295                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4296                 if (reduced_clock)
4297                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4298                                 reduced_clock->m2;
4299         }
4300
4301         I915_WRITE(FP0(pipe), fp);
4302
4303         intel_crtc->lowfreq_avail = false;
4304         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4305             reduced_clock && i915_powersave) {
4306                 I915_WRITE(FP1(pipe), fp2);
4307                 intel_crtc->lowfreq_avail = true;
4308         } else {
4309                 I915_WRITE(FP1(pipe), fp);
4310         }
4311 }
4312
4313 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4314                               struct drm_display_mode *adjusted_mode)
4315 {
4316         struct drm_device *dev = crtc->dev;
4317         struct drm_i915_private *dev_priv = dev->dev_private;
4318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319         int pipe = intel_crtc->pipe;
4320         u32 temp;
4321
4322         temp = I915_READ(LVDS);
4323         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4324         if (pipe == 1) {
4325                 temp |= LVDS_PIPEB_SELECT;
4326         } else {
4327                 temp &= ~LVDS_PIPEB_SELECT;
4328         }
4329         /* set the corresponsding LVDS_BORDER bit */
4330         temp |= dev_priv->lvds_border_bits;
4331         /* Set the B0-B3 data pairs corresponding to whether we're going to
4332          * set the DPLLs for dual-channel mode or not.
4333          */
4334         if (clock->p2 == 7)
4335                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4336         else
4337                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4338
4339         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4340          * appropriately here, but we need to look more thoroughly into how
4341          * panels behave in the two modes.
4342          */
4343         /* set the dithering flag on LVDS as needed */
4344         if (INTEL_INFO(dev)->gen >= 4) {
4345                 if (dev_priv->lvds_dither)
4346                         temp |= LVDS_ENABLE_DITHER;
4347                 else
4348                         temp &= ~LVDS_ENABLE_DITHER;
4349         }
4350         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4351         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4352                 temp |= LVDS_HSYNC_POLARITY;
4353         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4354                 temp |= LVDS_VSYNC_POLARITY;
4355         I915_WRITE(LVDS, temp);
4356 }
4357
4358 static void vlv_update_pll(struct drm_crtc *crtc,
4359                            struct drm_display_mode *mode,
4360                            struct drm_display_mode *adjusted_mode,
4361                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4362                            int num_connectors)
4363 {
4364         struct drm_device *dev = crtc->dev;
4365         struct drm_i915_private *dev_priv = dev->dev_private;
4366         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367         int pipe = intel_crtc->pipe;
4368         u32 dpll, mdiv, pdiv;
4369         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4370         bool is_sdvo;
4371         u32 temp;
4372
4373         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4374                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4375
4376         dpll = DPLL_VGA_MODE_DIS;
4377         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4378         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4379         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4380
4381         I915_WRITE(DPLL(pipe), dpll);
4382         POSTING_READ(DPLL(pipe));
4383
4384         bestn = clock->n;
4385         bestm1 = clock->m1;
4386         bestm2 = clock->m2;
4387         bestp1 = clock->p1;
4388         bestp2 = clock->p2;
4389
4390         /*
4391          * In Valleyview PLL and program lane counter registers are exposed
4392          * through DPIO interface
4393          */
4394         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4395         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4396         mdiv |= ((bestn << DPIO_N_SHIFT));
4397         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4398         mdiv |= (1 << DPIO_K_SHIFT);
4399         mdiv |= DPIO_ENABLE_CALIBRATION;
4400         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4401
4402         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4403
4404         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4405                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4406                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4407                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4408         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4409
4410         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4411
4412         dpll |= DPLL_VCO_ENABLE;
4413         I915_WRITE(DPLL(pipe), dpll);
4414         POSTING_READ(DPLL(pipe));
4415         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4416                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4417
4418         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4419
4420         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4421                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4422
4423         I915_WRITE(DPLL(pipe), dpll);
4424
4425         /* Wait for the clocks to stabilize. */
4426         POSTING_READ(DPLL(pipe));
4427         udelay(150);
4428
4429         temp = 0;
4430         if (is_sdvo) {
4431                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4432                 if (temp > 1)
4433                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4434                 else
4435                         temp = 0;
4436         }
4437         I915_WRITE(DPLL_MD(pipe), temp);
4438         POSTING_READ(DPLL_MD(pipe));
4439
4440         /* Now program lane control registers */
4441         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4442                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4443         {
4444                 temp = 0x1000C4;
4445                 if(pipe == 1)
4446                         temp |= (1 << 21);
4447                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4448         }
4449         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4450         {
4451                 temp = 0x1000C4;
4452                 if(pipe == 1)
4453                         temp |= (1 << 21);
4454                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4455         }
4456 }
4457
4458 static void i9xx_update_pll(struct drm_crtc *crtc,
4459                             struct drm_display_mode *mode,
4460                             struct drm_display_mode *adjusted_mode,
4461                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4462                             int num_connectors)
4463 {
4464         struct drm_device *dev = crtc->dev;
4465         struct drm_i915_private *dev_priv = dev->dev_private;
4466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4467         int pipe = intel_crtc->pipe;
4468         u32 dpll;
4469         bool is_sdvo;
4470
4471         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4472
4473         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4474                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4475
4476         dpll = DPLL_VGA_MODE_DIS;
4477
4478         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4479                 dpll |= DPLLB_MODE_LVDS;
4480         else
4481                 dpll |= DPLLB_MODE_DAC_SERIAL;
4482         if (is_sdvo) {
4483                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4484                 if (pixel_multiplier > 1) {
4485                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4486                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4487                 }
4488                 dpll |= DPLL_DVO_HIGH_SPEED;
4489         }
4490         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4491                 dpll |= DPLL_DVO_HIGH_SPEED;
4492
4493         /* compute bitmask from p1 value */
4494         if (IS_PINEVIEW(dev))
4495                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4496         else {
4497                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4498                 if (IS_G4X(dev) && reduced_clock)
4499                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4500         }
4501         switch (clock->p2) {
4502         case 5:
4503                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4504                 break;
4505         case 7:
4506                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4507                 break;
4508         case 10:
4509                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4510                 break;
4511         case 14:
4512                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4513                 break;
4514         }
4515         if (INTEL_INFO(dev)->gen >= 4)
4516                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4517
4518         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4520         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4521                 /* XXX: just matching BIOS for now */
4522                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4523                 dpll |= 3;
4524         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4525                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4526                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4527         else
4528                 dpll |= PLL_REF_INPUT_DREFCLK;
4529
4530         dpll |= DPLL_VCO_ENABLE;
4531         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4532         POSTING_READ(DPLL(pipe));
4533         udelay(150);
4534
4535         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4536          * This is an exception to the general rule that mode_set doesn't turn
4537          * things on.
4538          */
4539         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4540                 intel_update_lvds(crtc, clock, adjusted_mode);
4541
4542         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4543                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4544
4545         I915_WRITE(DPLL(pipe), dpll);
4546
4547         /* Wait for the clocks to stabilize. */
4548         POSTING_READ(DPLL(pipe));
4549         udelay(150);
4550
4551         if (INTEL_INFO(dev)->gen >= 4) {
4552                 u32 temp = 0;
4553                 if (is_sdvo) {
4554                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4555                         if (temp > 1)
4556                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4557                         else
4558                                 temp = 0;
4559                 }
4560                 I915_WRITE(DPLL_MD(pipe), temp);
4561         } else {
4562                 /* The pixel multiplier can only be updated once the
4563                  * DPLL is enabled and the clocks are stable.
4564                  *
4565                  * So write it again.
4566                  */
4567                 I915_WRITE(DPLL(pipe), dpll);
4568         }
4569 }
4570
4571 static void i8xx_update_pll(struct drm_crtc *crtc,
4572                             struct drm_display_mode *adjusted_mode,
4573                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4574                             int num_connectors)
4575 {
4576         struct drm_device *dev = crtc->dev;
4577         struct drm_i915_private *dev_priv = dev->dev_private;
4578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4579         int pipe = intel_crtc->pipe;
4580         u32 dpll;
4581
4582         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4583
4584         dpll = DPLL_VGA_MODE_DIS;
4585
4586         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4587                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4588         } else {
4589                 if (clock->p1 == 2)
4590                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4591                 else
4592                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4593                 if (clock->p2 == 4)
4594                         dpll |= PLL_P2_DIVIDE_BY_4;
4595         }
4596
4597         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4598                 /* XXX: just matching BIOS for now */
4599                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4600                 dpll |= 3;
4601         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4602                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4603                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4604         else
4605                 dpll |= PLL_REF_INPUT_DREFCLK;
4606
4607         dpll |= DPLL_VCO_ENABLE;
4608         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4609         POSTING_READ(DPLL(pipe));
4610         udelay(150);
4611
4612         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4613          * This is an exception to the general rule that mode_set doesn't turn
4614          * things on.
4615          */
4616         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4617                 intel_update_lvds(crtc, clock, adjusted_mode);
4618
4619         I915_WRITE(DPLL(pipe), dpll);
4620
4621         /* Wait for the clocks to stabilize. */
4622         POSTING_READ(DPLL(pipe));
4623         udelay(150);
4624
4625         /* The pixel multiplier can only be updated once the
4626          * DPLL is enabled and the clocks are stable.
4627          *
4628          * So write it again.
4629          */
4630         I915_WRITE(DPLL(pipe), dpll);
4631 }
4632
4633 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4634                                    struct drm_display_mode *mode,
4635                                    struct drm_display_mode *adjusted_mode)
4636 {
4637         struct drm_device *dev = intel_crtc->base.dev;
4638         struct drm_i915_private *dev_priv = dev->dev_private;
4639         enum pipe pipe = intel_crtc->pipe;
4640         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4641         uint32_t vsyncshift;
4642
4643         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644                 /* the chip adds 2 halflines automatically */
4645                 adjusted_mode->crtc_vtotal -= 1;
4646                 adjusted_mode->crtc_vblank_end -= 1;
4647                 vsyncshift = adjusted_mode->crtc_hsync_start
4648                              - adjusted_mode->crtc_htotal / 2;
4649         } else {
4650                 vsyncshift = 0;
4651         }
4652
4653         if (INTEL_INFO(dev)->gen > 3)
4654                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4655
4656         I915_WRITE(HTOTAL(cpu_transcoder),
4657                    (adjusted_mode->crtc_hdisplay - 1) |
4658                    ((adjusted_mode->crtc_htotal - 1) << 16));
4659         I915_WRITE(HBLANK(cpu_transcoder),
4660                    (adjusted_mode->crtc_hblank_start - 1) |
4661                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4662         I915_WRITE(HSYNC(cpu_transcoder),
4663                    (adjusted_mode->crtc_hsync_start - 1) |
4664                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
4666         I915_WRITE(VTOTAL(cpu_transcoder),
4667                    (adjusted_mode->crtc_vdisplay - 1) |
4668                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4669         I915_WRITE(VBLANK(cpu_transcoder),
4670                    (adjusted_mode->crtc_vblank_start - 1) |
4671                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4672         I915_WRITE(VSYNC(cpu_transcoder),
4673                    (adjusted_mode->crtc_vsync_start - 1) |
4674                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
4676         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679          * bits. */
4680         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681             (pipe == PIPE_B || pipe == PIPE_C))
4682                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
4684         /* pipesrc controls the size that is scaled from, which should
4685          * always be the user's requested size.
4686          */
4687         I915_WRITE(PIPESRC(pipe),
4688                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689 }
4690
4691 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4692                               struct drm_display_mode *mode,
4693                               struct drm_display_mode *adjusted_mode,
4694                               int x, int y,
4695                               struct drm_framebuffer *fb)
4696 {
4697         struct drm_device *dev = crtc->dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700         int pipe = intel_crtc->pipe;
4701         int plane = intel_crtc->plane;
4702         int refclk, num_connectors = 0;
4703         intel_clock_t clock, reduced_clock;
4704         u32 dspcntr, pipeconf;
4705         bool ok, has_reduced_clock = false, is_sdvo = false;
4706         bool is_lvds = false, is_tv = false, is_dp = false;
4707         struct intel_encoder *encoder;
4708         const intel_limit_t *limit;
4709         int ret;
4710
4711         for_each_encoder_on_crtc(dev, crtc, encoder) {
4712                 switch (encoder->type) {
4713                 case INTEL_OUTPUT_LVDS:
4714                         is_lvds = true;
4715                         break;
4716                 case INTEL_OUTPUT_SDVO:
4717                 case INTEL_OUTPUT_HDMI:
4718                         is_sdvo = true;
4719                         if (encoder->needs_tv_clock)
4720                                 is_tv = true;
4721                         break;
4722                 case INTEL_OUTPUT_TVOUT:
4723                         is_tv = true;
4724                         break;
4725                 case INTEL_OUTPUT_DISPLAYPORT:
4726                         is_dp = true;
4727                         break;
4728                 }
4729
4730                 num_connectors++;
4731         }
4732
4733         refclk = i9xx_get_refclk(crtc, num_connectors);
4734
4735         /*
4736          * Returns a set of divisors for the desired target clock with the given
4737          * refclk, or FALSE.  The returned values represent the clock equation:
4738          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4739          */
4740         limit = intel_limit(crtc, refclk);
4741         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4742                              &clock);
4743         if (!ok) {
4744                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4745                 return -EINVAL;
4746         }
4747
4748         /* Ensure that the cursor is valid for the new mode before changing... */
4749         intel_crtc_update_cursor(crtc, true);
4750
4751         if (is_lvds && dev_priv->lvds_downclock_avail) {
4752                 /*
4753                  * Ensure we match the reduced clock's P to the target clock.
4754                  * If the clocks don't match, we can't switch the display clock
4755                  * by using the FP0/FP1. In such case we will disable the LVDS
4756                  * downclock feature.
4757                 */
4758                 has_reduced_clock = limit->find_pll(limit, crtc,
4759                                                     dev_priv->lvds_downclock,
4760                                                     refclk,
4761                                                     &clock,
4762                                                     &reduced_clock);
4763         }
4764
4765         if (is_sdvo && is_tv)
4766                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4767
4768         if (IS_GEN2(dev))
4769                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4770                                 has_reduced_clock ? &reduced_clock : NULL,
4771                                 num_connectors);
4772         else if (IS_VALLEYVIEW(dev))
4773                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4774                                 has_reduced_clock ? &reduced_clock : NULL,
4775                                 num_connectors);
4776         else
4777                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4778                                 has_reduced_clock ? &reduced_clock : NULL,
4779                                 num_connectors);
4780
4781         /* setup pipeconf */
4782         pipeconf = I915_READ(PIPECONF(pipe));
4783
4784         /* Set up the display plane register */
4785         dspcntr = DISPPLANE_GAMMA_ENABLE;
4786
4787         if (pipe == 0)
4788                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4789         else
4790                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4791
4792         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4793                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4794                  * core speed.
4795                  *
4796                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4797                  * pipe == 0 check?
4798                  */
4799                 if (mode->clock >
4800                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4801                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4802                 else
4803                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4804         }
4805
4806         /* default to 8bpc */
4807         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4808         if (is_dp) {
4809                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4810                         pipeconf |= PIPECONF_BPP_6 |
4811                                     PIPECONF_DITHER_EN |
4812                                     PIPECONF_DITHER_TYPE_SP;
4813                 }
4814         }
4815
4816         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4817                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4818                         pipeconf |= PIPECONF_BPP_6 |
4819                                         PIPECONF_ENABLE |
4820                                         I965_PIPECONF_ACTIVE;
4821                 }
4822         }
4823
4824         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4825         drm_mode_debug_printmodeline(mode);
4826
4827         if (HAS_PIPE_CXSR(dev)) {
4828                 if (intel_crtc->lowfreq_avail) {
4829                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4830                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4831                 } else {
4832                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4833                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4834                 }
4835         }
4836
4837         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4838         if (!IS_GEN2(dev) &&
4839             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4840                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4841         else
4842                 pipeconf |= PIPECONF_PROGRESSIVE;
4843
4844         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4845
4846         /* pipesrc and dspsize control the size that is scaled from,
4847          * which should always be the user's requested size.
4848          */
4849         I915_WRITE(DSPSIZE(plane),
4850                    ((mode->vdisplay - 1) << 16) |
4851                    (mode->hdisplay - 1));
4852         I915_WRITE(DSPPOS(plane), 0);
4853
4854         I915_WRITE(PIPECONF(pipe), pipeconf);
4855         POSTING_READ(PIPECONF(pipe));
4856         intel_enable_pipe(dev_priv, pipe, false);
4857
4858         intel_wait_for_vblank(dev, pipe);
4859
4860         I915_WRITE(DSPCNTR(plane), dspcntr);
4861         POSTING_READ(DSPCNTR(plane));
4862
4863         ret = intel_pipe_set_base(crtc, x, y, fb);
4864
4865         intel_update_watermarks(dev);
4866
4867         return ret;
4868 }
4869
4870 /*
4871  * Initialize reference clocks when the driver loads
4872  */
4873 void ironlake_init_pch_refclk(struct drm_device *dev)
4874 {
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876         struct drm_mode_config *mode_config = &dev->mode_config;
4877         struct intel_encoder *encoder;
4878         u32 temp;
4879         bool has_lvds = false;
4880         bool has_cpu_edp = false;
4881         bool has_pch_edp = false;
4882         bool has_panel = false;
4883         bool has_ck505 = false;
4884         bool can_ssc = false;
4885
4886         /* We need to take the global config into account */
4887         list_for_each_entry(encoder, &mode_config->encoder_list,
4888                             base.head) {
4889                 switch (encoder->type) {
4890                 case INTEL_OUTPUT_LVDS:
4891                         has_panel = true;
4892                         has_lvds = true;
4893                         break;
4894                 case INTEL_OUTPUT_EDP:
4895                         has_panel = true;
4896                         if (intel_encoder_is_pch_edp(&encoder->base))
4897                                 has_pch_edp = true;
4898                         else
4899                                 has_cpu_edp = true;
4900                         break;
4901                 }
4902         }
4903
4904         if (HAS_PCH_IBX(dev)) {
4905                 has_ck505 = dev_priv->display_clock_mode;
4906                 can_ssc = has_ck505;
4907         } else {
4908                 has_ck505 = false;
4909                 can_ssc = true;
4910         }
4911
4912         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4913                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4914                       has_ck505);
4915
4916         /* Ironlake: try to setup display ref clock before DPLL
4917          * enabling. This is only under driver's control after
4918          * PCH B stepping, previous chipset stepping should be
4919          * ignoring this setting.
4920          */
4921         temp = I915_READ(PCH_DREF_CONTROL);
4922         /* Always enable nonspread source */
4923         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4924
4925         if (has_ck505)
4926                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4927         else
4928                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4929
4930         if (has_panel) {
4931                 temp &= ~DREF_SSC_SOURCE_MASK;
4932                 temp |= DREF_SSC_SOURCE_ENABLE;
4933
4934                 /* SSC must be turned on before enabling the CPU output  */
4935                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4936                         DRM_DEBUG_KMS("Using SSC on panel\n");
4937                         temp |= DREF_SSC1_ENABLE;
4938                 } else
4939                         temp &= ~DREF_SSC1_ENABLE;
4940
4941                 /* Get SSC going before enabling the outputs */
4942                 I915_WRITE(PCH_DREF_CONTROL, temp);
4943                 POSTING_READ(PCH_DREF_CONTROL);
4944                 udelay(200);
4945
4946                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4947
4948                 /* Enable CPU source on CPU attached eDP */
4949                 if (has_cpu_edp) {
4950                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4951                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4952                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4953                         }
4954                         else
4955                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4956                 } else
4957                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4958
4959                 I915_WRITE(PCH_DREF_CONTROL, temp);
4960                 POSTING_READ(PCH_DREF_CONTROL);
4961                 udelay(200);
4962         } else {
4963                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4964
4965                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4966
4967                 /* Turn off CPU output */
4968                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4969
4970                 I915_WRITE(PCH_DREF_CONTROL, temp);
4971                 POSTING_READ(PCH_DREF_CONTROL);
4972                 udelay(200);
4973
4974                 /* Turn off the SSC source */
4975                 temp &= ~DREF_SSC_SOURCE_MASK;
4976                 temp |= DREF_SSC_SOURCE_DISABLE;
4977
4978                 /* Turn off SSC1 */
4979                 temp &= ~ DREF_SSC1_ENABLE;
4980
4981                 I915_WRITE(PCH_DREF_CONTROL, temp);
4982                 POSTING_READ(PCH_DREF_CONTROL);
4983                 udelay(200);
4984         }
4985 }
4986
4987 static int ironlake_get_refclk(struct drm_crtc *crtc)
4988 {
4989         struct drm_device *dev = crtc->dev;
4990         struct drm_i915_private *dev_priv = dev->dev_private;
4991         struct intel_encoder *encoder;
4992         struct intel_encoder *edp_encoder = NULL;
4993         int num_connectors = 0;
4994         bool is_lvds = false;
4995
4996         for_each_encoder_on_crtc(dev, crtc, encoder) {
4997                 switch (encoder->type) {
4998                 case INTEL_OUTPUT_LVDS:
4999                         is_lvds = true;
5000                         break;
5001                 case INTEL_OUTPUT_EDP:
5002                         edp_encoder = encoder;
5003                         break;
5004                 }
5005                 num_connectors++;
5006         }
5007
5008         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5009                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5010                               dev_priv->lvds_ssc_freq);
5011                 return dev_priv->lvds_ssc_freq * 1000;
5012         }
5013
5014         return 120000;
5015 }
5016
5017 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5018                                   struct drm_display_mode *adjusted_mode,
5019                                   bool dither)
5020 {
5021         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023         int pipe = intel_crtc->pipe;
5024         uint32_t val;
5025
5026         val = I915_READ(PIPECONF(pipe));
5027
5028         val &= ~PIPE_BPC_MASK;
5029         switch (intel_crtc->bpp) {
5030         case 18:
5031                 val |= PIPE_6BPC;
5032                 break;
5033         case 24:
5034                 val |= PIPE_8BPC;
5035                 break;
5036         case 30:
5037                 val |= PIPE_10BPC;
5038                 break;
5039         case 36:
5040                 val |= PIPE_12BPC;
5041                 break;
5042         default:
5043                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5044                 BUG();
5045         }
5046
5047         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5048         if (dither)
5049                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5050
5051         val &= ~PIPECONF_INTERLACE_MASK;
5052         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5053                 val |= PIPECONF_INTERLACED_ILK;
5054         else
5055                 val |= PIPECONF_PROGRESSIVE;
5056
5057         I915_WRITE(PIPECONF(pipe), val);
5058         POSTING_READ(PIPECONF(pipe));
5059 }
5060
5061 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5062                                  struct drm_display_mode *adjusted_mode,
5063                                  bool dither)
5064 {
5065         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5067         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5068         uint32_t val;
5069
5070         val = I915_READ(PIPECONF(cpu_transcoder));
5071
5072         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5073         if (dither)
5074                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5075
5076         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5077         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5078                 val |= PIPECONF_INTERLACED_ILK;
5079         else
5080                 val |= PIPECONF_PROGRESSIVE;
5081
5082         I915_WRITE(PIPECONF(cpu_transcoder), val);
5083         POSTING_READ(PIPECONF(cpu_transcoder));
5084 }
5085
5086 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5087                                     struct drm_display_mode *adjusted_mode,
5088                                     intel_clock_t *clock,
5089                                     bool *has_reduced_clock,
5090                                     intel_clock_t *reduced_clock)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         struct intel_encoder *intel_encoder;
5095         int refclk;
5096         const intel_limit_t *limit;
5097         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5098
5099         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5100                 switch (intel_encoder->type) {
5101                 case INTEL_OUTPUT_LVDS:
5102                         is_lvds = true;
5103                         break;
5104                 case INTEL_OUTPUT_SDVO:
5105                 case INTEL_OUTPUT_HDMI:
5106                         is_sdvo = true;
5107                         if (intel_encoder->needs_tv_clock)
5108                                 is_tv = true;
5109                         break;
5110                 case INTEL_OUTPUT_TVOUT:
5111                         is_tv = true;
5112                         break;
5113                 }
5114         }
5115
5116         refclk = ironlake_get_refclk(crtc);
5117
5118         /*
5119          * Returns a set of divisors for the desired target clock with the given
5120          * refclk, or FALSE.  The returned values represent the clock equation:
5121          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5122          */
5123         limit = intel_limit(crtc, refclk);
5124         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5125                               clock);
5126         if (!ret)
5127                 return false;
5128
5129         if (is_lvds && dev_priv->lvds_downclock_avail) {
5130                 /*
5131                  * Ensure we match the reduced clock's P to the target clock.
5132                  * If the clocks don't match, we can't switch the display clock
5133                  * by using the FP0/FP1. In such case we will disable the LVDS
5134                  * downclock feature.
5135                 */
5136                 *has_reduced_clock = limit->find_pll(limit, crtc,
5137                                                      dev_priv->lvds_downclock,
5138                                                      refclk,
5139                                                      clock,
5140                                                      reduced_clock);
5141         }
5142
5143         if (is_sdvo && is_tv)
5144                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5145
5146         return true;
5147 }
5148
5149 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5150 {
5151         struct drm_i915_private *dev_priv = dev->dev_private;
5152         uint32_t temp;
5153
5154         temp = I915_READ(SOUTH_CHICKEN1);
5155         if (temp & FDI_BC_BIFURCATION_SELECT)
5156                 return;
5157
5158         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5159         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5160
5161         temp |= FDI_BC_BIFURCATION_SELECT;
5162         DRM_DEBUG_KMS("enabling fdi C rx\n");
5163         I915_WRITE(SOUTH_CHICKEN1, temp);
5164         POSTING_READ(SOUTH_CHICKEN1);
5165 }
5166
5167 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5168 {
5169         struct drm_device *dev = intel_crtc->base.dev;
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         struct intel_crtc *pipe_B_crtc =
5172                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5173
5174         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5175                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5176         if (intel_crtc->fdi_lanes > 4) {
5177                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5178                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5179                 /* Clamp lanes to avoid programming the hw with bogus values. */
5180                 intel_crtc->fdi_lanes = 4;
5181
5182                 return false;
5183         }
5184
5185         if (dev_priv->num_pipe == 2)
5186                 return true;
5187
5188         switch (intel_crtc->pipe) {
5189         case PIPE_A:
5190                 return true;
5191         case PIPE_B:
5192                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5193                     intel_crtc->fdi_lanes > 2) {
5194                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5195                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5196                         /* Clamp lanes to avoid programming the hw with bogus values. */
5197                         intel_crtc->fdi_lanes = 2;
5198
5199                         return false;
5200                 }
5201
5202                 if (intel_crtc->fdi_lanes > 2)
5203                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5204                 else
5205                         cpt_enable_fdi_bc_bifurcation(dev);
5206
5207                 return true;
5208         case PIPE_C:
5209                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5210                         if (intel_crtc->fdi_lanes > 2) {
5211                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5212                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5213                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5214                                 intel_crtc->fdi_lanes = 2;
5215
5216                                 return false;
5217                         }
5218                 } else {
5219                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5220                         return false;
5221                 }
5222
5223                 cpt_enable_fdi_bc_bifurcation(dev);
5224
5225                 return true;
5226         default:
5227                 BUG();
5228         }
5229 }
5230
5231 static void ironlake_set_m_n(struct drm_crtc *crtc,
5232                              struct drm_display_mode *mode,
5233                              struct drm_display_mode *adjusted_mode)
5234 {
5235         struct drm_device *dev = crtc->dev;
5236         struct drm_i915_private *dev_priv = dev->dev_private;
5237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5239         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5240         struct fdi_m_n m_n = {0};
5241         int target_clock, pixel_multiplier, lane, link_bw;
5242         bool is_dp = false, is_cpu_edp = false;
5243
5244         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5245                 switch (intel_encoder->type) {
5246                 case INTEL_OUTPUT_DISPLAYPORT:
5247                         is_dp = true;
5248                         break;
5249                 case INTEL_OUTPUT_EDP:
5250                         is_dp = true;
5251                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5252                                 is_cpu_edp = true;
5253                         edp_encoder = intel_encoder;
5254                         break;
5255                 }
5256         }
5257
5258         /* FDI link */
5259         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5260         lane = 0;
5261         /* CPU eDP doesn't require FDI link, so just set DP M/N
5262            according to current link config */
5263         if (is_cpu_edp) {
5264                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5265         } else {
5266                 /* FDI is a binary signal running at ~2.7GHz, encoding
5267                  * each output octet as 10 bits. The actual frequency
5268                  * is stored as a divider into a 100MHz clock, and the
5269                  * mode pixel clock is stored in units of 1KHz.
5270                  * Hence the bw of each lane in terms of the mode signal
5271                  * is:
5272                  */
5273                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5274         }
5275
5276         /* [e]DP over FDI requires target mode clock instead of link clock. */
5277         if (edp_encoder)
5278                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5279         else if (is_dp)
5280                 target_clock = mode->clock;
5281         else
5282                 target_clock = adjusted_mode->clock;
5283
5284         if (!lane) {
5285                 /*
5286                  * Account for spread spectrum to avoid
5287                  * oversubscribing the link. Max center spread
5288                  * is 2.5%; use 5% for safety's sake.
5289                  */
5290                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5291                 lane = bps / (link_bw * 8) + 1;
5292         }
5293
5294         intel_crtc->fdi_lanes = lane;
5295
5296         if (pixel_multiplier > 1)
5297                 link_bw *= pixel_multiplier;
5298         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5299                              &m_n);
5300
5301         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5302         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5303         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5304         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5305 }
5306
5307 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5308                                       struct drm_display_mode *adjusted_mode,
5309                                       intel_clock_t *clock, u32 fp)
5310 {
5311         struct drm_crtc *crtc = &intel_crtc->base;
5312         struct drm_device *dev = crtc->dev;
5313         struct drm_i915_private *dev_priv = dev->dev_private;
5314         struct intel_encoder *intel_encoder;
5315         uint32_t dpll;
5316         int factor, pixel_multiplier, num_connectors = 0;
5317         bool is_lvds = false, is_sdvo = false, is_tv = false;
5318         bool is_dp = false, is_cpu_edp = false;
5319
5320         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5321                 switch (intel_encoder->type) {
5322                 case INTEL_OUTPUT_LVDS:
5323                         is_lvds = true;
5324                         break;
5325                 case INTEL_OUTPUT_SDVO:
5326                 case INTEL_OUTPUT_HDMI:
5327                         is_sdvo = true;
5328                         if (intel_encoder->needs_tv_clock)
5329                                 is_tv = true;
5330                         break;
5331                 case INTEL_OUTPUT_TVOUT:
5332                         is_tv = true;
5333                         break;
5334                 case INTEL_OUTPUT_DISPLAYPORT:
5335                         is_dp = true;
5336                         break;
5337                 case INTEL_OUTPUT_EDP:
5338                         is_dp = true;
5339                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5340                                 is_cpu_edp = true;
5341                         break;
5342                 }
5343
5344                 num_connectors++;
5345         }
5346
5347         /* Enable autotuning of the PLL clock (if permissible) */
5348         factor = 21;
5349         if (is_lvds) {
5350                 if ((intel_panel_use_ssc(dev_priv) &&
5351                      dev_priv->lvds_ssc_freq == 100) ||
5352                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5353                         factor = 25;
5354         } else if (is_sdvo && is_tv)
5355                 factor = 20;
5356
5357         if (clock->m < factor * clock->n)
5358                 fp |= FP_CB_TUNE;
5359
5360         dpll = 0;
5361
5362         if (is_lvds)
5363                 dpll |= DPLLB_MODE_LVDS;
5364         else
5365                 dpll |= DPLLB_MODE_DAC_SERIAL;
5366         if (is_sdvo) {
5367                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5368                 if (pixel_multiplier > 1) {
5369                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5370                 }
5371                 dpll |= DPLL_DVO_HIGH_SPEED;
5372         }
5373         if (is_dp && !is_cpu_edp)
5374                 dpll |= DPLL_DVO_HIGH_SPEED;
5375
5376         /* compute bitmask from p1 value */
5377         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5378         /* also FPA1 */
5379         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5380
5381         switch (clock->p2) {
5382         case 5:
5383                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5384                 break;
5385         case 7:
5386                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5387                 break;
5388         case 10:
5389                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5390                 break;
5391         case 14:
5392                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5393                 break;
5394         }
5395
5396         if (is_sdvo && is_tv)
5397                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5398         else if (is_tv)
5399                 /* XXX: just matching BIOS for now */
5400                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5401                 dpll |= 3;
5402         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5403                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5404         else
5405                 dpll |= PLL_REF_INPUT_DREFCLK;
5406
5407         return dpll;
5408 }
5409
5410 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5411                                   struct drm_display_mode *mode,
5412                                   struct drm_display_mode *adjusted_mode,
5413                                   int x, int y,
5414                                   struct drm_framebuffer *fb)
5415 {
5416         struct drm_device *dev = crtc->dev;
5417         struct drm_i915_private *dev_priv = dev->dev_private;
5418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419         int pipe = intel_crtc->pipe;
5420         int plane = intel_crtc->plane;
5421         int num_connectors = 0;
5422         intel_clock_t clock, reduced_clock;
5423         u32 dpll, fp = 0, fp2 = 0;
5424         bool ok, has_reduced_clock = false;
5425         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5426         struct intel_encoder *encoder;
5427         u32 temp;
5428         int ret;
5429         bool dither, fdi_config_ok;
5430
5431         for_each_encoder_on_crtc(dev, crtc, encoder) {
5432                 switch (encoder->type) {
5433                 case INTEL_OUTPUT_LVDS:
5434                         is_lvds = true;
5435                         break;
5436                 case INTEL_OUTPUT_DISPLAYPORT:
5437                         is_dp = true;
5438                         break;
5439                 case INTEL_OUTPUT_EDP:
5440                         is_dp = true;
5441                         if (!intel_encoder_is_pch_edp(&encoder->base))
5442                                 is_cpu_edp = true;
5443                         break;
5444                 }
5445
5446                 num_connectors++;
5447         }
5448
5449         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5450              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5451
5452         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5453                                      &has_reduced_clock, &reduced_clock);
5454         if (!ok) {
5455                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5456                 return -EINVAL;
5457         }
5458
5459         /* Ensure that the cursor is valid for the new mode before changing... */
5460         intel_crtc_update_cursor(crtc, true);
5461
5462         /* determine panel color depth */
5463         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5464                                               adjusted_mode);
5465         if (is_lvds && dev_priv->lvds_dither)
5466                 dither = true;
5467
5468         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5469         if (has_reduced_clock)
5470                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5471                         reduced_clock.m2;
5472
5473         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5474
5475         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5476         drm_mode_debug_printmodeline(mode);
5477
5478         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5479         if (!is_cpu_edp) {
5480                 struct intel_pch_pll *pll;
5481
5482                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5483                 if (pll == NULL) {
5484                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5485                                          pipe);
5486                         return -EINVAL;
5487                 }
5488         } else
5489                 intel_put_pch_pll(intel_crtc);
5490
5491         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5492          * This is an exception to the general rule that mode_set doesn't turn
5493          * things on.
5494          */
5495         if (is_lvds) {
5496                 temp = I915_READ(PCH_LVDS);
5497                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5498                 if (HAS_PCH_CPT(dev)) {
5499                         temp &= ~PORT_TRANS_SEL_MASK;
5500                         temp |= PORT_TRANS_SEL_CPT(pipe);
5501                 } else {
5502                         if (pipe == 1)
5503                                 temp |= LVDS_PIPEB_SELECT;
5504                         else
5505                                 temp &= ~LVDS_PIPEB_SELECT;
5506                 }
5507
5508                 /* set the corresponsding LVDS_BORDER bit */
5509                 temp |= dev_priv->lvds_border_bits;
5510                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5511                  * set the DPLLs for dual-channel mode or not.
5512                  */
5513                 if (clock.p2 == 7)
5514                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5515                 else
5516                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5517
5518                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5519                  * appropriately here, but we need to look more thoroughly into how
5520                  * panels behave in the two modes.
5521                  */
5522                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5523                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5524                         temp |= LVDS_HSYNC_POLARITY;
5525                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5526                         temp |= LVDS_VSYNC_POLARITY;
5527                 I915_WRITE(PCH_LVDS, temp);
5528         }
5529
5530         if (is_dp && !is_cpu_edp) {
5531                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5532         } else {
5533                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5534                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5535                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5536                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5537                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5538         }
5539
5540         if (intel_crtc->pch_pll) {
5541                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5542
5543                 /* Wait for the clocks to stabilize. */
5544                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5545                 udelay(150);
5546
5547                 /* The pixel multiplier can only be updated once the
5548                  * DPLL is enabled and the clocks are stable.
5549                  *
5550                  * So write it again.
5551                  */
5552                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5553         }
5554
5555         intel_crtc->lowfreq_avail = false;
5556         if (intel_crtc->pch_pll) {
5557                 if (is_lvds && has_reduced_clock && i915_powersave) {
5558                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5559                         intel_crtc->lowfreq_avail = true;
5560                 } else {
5561                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5562                 }
5563         }
5564
5565         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5566
5567         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5568          * ironlake_check_fdi_lanes. */
5569         ironlake_set_m_n(crtc, mode, adjusted_mode);
5570
5571         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5572
5573         if (is_cpu_edp)
5574                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5575
5576         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5577
5578         intel_wait_for_vblank(dev, pipe);
5579
5580         /* Set up the display plane register */
5581         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5582         POSTING_READ(DSPCNTR(plane));
5583
5584         ret = intel_pipe_set_base(crtc, x, y, fb);
5585
5586         intel_update_watermarks(dev);
5587
5588         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5589
5590         return fdi_config_ok ? ret : -EINVAL;
5591 }
5592
5593 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5594                                  struct drm_display_mode *mode,
5595                                  struct drm_display_mode *adjusted_mode,
5596                                  int x, int y,
5597                                  struct drm_framebuffer *fb)
5598 {
5599         struct drm_device *dev = crtc->dev;
5600         struct drm_i915_private *dev_priv = dev->dev_private;
5601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602         int pipe = intel_crtc->pipe;
5603         int plane = intel_crtc->plane;
5604         int num_connectors = 0;
5605         intel_clock_t clock, reduced_clock;
5606         u32 dpll = 0, fp = 0, fp2 = 0;
5607         bool ok, has_reduced_clock = false;
5608         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5609         struct intel_encoder *encoder;
5610         u32 temp;
5611         int ret;
5612         bool dither;
5613
5614         for_each_encoder_on_crtc(dev, crtc, encoder) {
5615                 switch (encoder->type) {
5616                 case INTEL_OUTPUT_LVDS:
5617                         is_lvds = true;
5618                         break;
5619                 case INTEL_OUTPUT_DISPLAYPORT:
5620                         is_dp = true;
5621                         break;
5622                 case INTEL_OUTPUT_EDP:
5623                         is_dp = true;
5624                         if (!intel_encoder_is_pch_edp(&encoder->base))
5625                                 is_cpu_edp = true;
5626                         break;
5627                 }
5628
5629                 num_connectors++;
5630         }
5631
5632         if (is_cpu_edp)
5633                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5634         else
5635                 intel_crtc->cpu_transcoder = pipe;
5636
5637         /* We are not sure yet this won't happen. */
5638         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5639              INTEL_PCH_TYPE(dev));
5640
5641         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5642              num_connectors, pipe_name(pipe));
5643
5644         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5645                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5646
5647         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5648
5649         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5650                 return -EINVAL;
5651
5652         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5653                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5654                                              &has_reduced_clock,
5655                                              &reduced_clock);
5656                 if (!ok) {
5657                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5658                         return -EINVAL;
5659                 }
5660         }
5661
5662         /* Ensure that the cursor is valid for the new mode before changing... */
5663         intel_crtc_update_cursor(crtc, true);
5664
5665         /* determine panel color depth */
5666         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5667                                               adjusted_mode);
5668         if (is_lvds && dev_priv->lvds_dither)
5669                 dither = true;
5670
5671         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5672         drm_mode_debug_printmodeline(mode);
5673
5674         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5675                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5676                 if (has_reduced_clock)
5677                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5678                               reduced_clock.m2;
5679
5680                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5681                                              fp);
5682
5683                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5684                  * own on pre-Haswell/LPT generation */
5685                 if (!is_cpu_edp) {
5686                         struct intel_pch_pll *pll;
5687
5688                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5689                         if (pll == NULL) {
5690                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5691                                                  pipe);
5692                                 return -EINVAL;
5693                         }
5694                 } else
5695                         intel_put_pch_pll(intel_crtc);
5696
5697                 /* The LVDS pin pair needs to be on before the DPLLs are
5698                  * enabled.  This is an exception to the general rule that
5699                  * mode_set doesn't turn things on.
5700                  */
5701                 if (is_lvds) {
5702                         temp = I915_READ(PCH_LVDS);
5703                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5704                         if (HAS_PCH_CPT(dev)) {
5705                                 temp &= ~PORT_TRANS_SEL_MASK;
5706                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5707                         } else {
5708                                 if (pipe == 1)
5709                                         temp |= LVDS_PIPEB_SELECT;
5710                                 else
5711                                         temp &= ~LVDS_PIPEB_SELECT;
5712                         }
5713
5714                         /* set the corresponsding LVDS_BORDER bit */
5715                         temp |= dev_priv->lvds_border_bits;
5716                         /* Set the B0-B3 data pairs corresponding to whether
5717                          * we're going to set the DPLLs for dual-channel mode or
5718                          * not.
5719                          */
5720                         if (clock.p2 == 7)
5721                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5722                         else
5723                                 temp &= ~(LVDS_B0B3_POWER_UP |
5724                                           LVDS_CLKB_POWER_UP);
5725
5726                         /* It would be nice to set 24 vs 18-bit mode
5727                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5728                          * look more thoroughly into how panels behave in the
5729                          * two modes.
5730                          */
5731                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5732                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5733                                 temp |= LVDS_HSYNC_POLARITY;
5734                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5735                                 temp |= LVDS_VSYNC_POLARITY;
5736                         I915_WRITE(PCH_LVDS, temp);
5737                 }
5738         }
5739
5740         if (is_dp && !is_cpu_edp) {
5741                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5742         } else {
5743                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5744                         /* For non-DP output, clear any trans DP clock recovery
5745                          * setting.*/
5746                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5747                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5748                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5749                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5750                 }
5751         }
5752
5753         intel_crtc->lowfreq_avail = false;
5754         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5755                 if (intel_crtc->pch_pll) {
5756                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5757
5758                         /* Wait for the clocks to stabilize. */
5759                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5760                         udelay(150);
5761
5762                         /* The pixel multiplier can only be updated once the
5763                          * DPLL is enabled and the clocks are stable.
5764                          *
5765                          * So write it again.
5766                          */
5767                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768                 }
5769
5770                 if (intel_crtc->pch_pll) {
5771                         if (is_lvds && has_reduced_clock && i915_powersave) {
5772                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5773                                 intel_crtc->lowfreq_avail = true;
5774                         } else {
5775                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5776                         }
5777                 }
5778         }
5779
5780         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5781
5782         if (!is_dp || is_cpu_edp)
5783                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5784
5785         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5786                 if (is_cpu_edp)
5787                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5788
5789         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5790
5791         /* Set up the display plane register */
5792         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5793         POSTING_READ(DSPCNTR(plane));
5794
5795         ret = intel_pipe_set_base(crtc, x, y, fb);
5796
5797         intel_update_watermarks(dev);
5798
5799         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5800
5801         return ret;
5802 }
5803
5804 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5805                                struct drm_display_mode *mode,
5806                                struct drm_display_mode *adjusted_mode,
5807                                int x, int y,
5808                                struct drm_framebuffer *fb)
5809 {
5810         struct drm_device *dev = crtc->dev;
5811         struct drm_i915_private *dev_priv = dev->dev_private;
5812         struct drm_encoder_helper_funcs *encoder_funcs;
5813         struct intel_encoder *encoder;
5814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5815         int pipe = intel_crtc->pipe;
5816         int ret;
5817
5818         drm_vblank_pre_modeset(dev, pipe);
5819
5820         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5821                                               x, y, fb);
5822         drm_vblank_post_modeset(dev, pipe);
5823
5824         if (ret != 0)
5825                 return ret;
5826
5827         for_each_encoder_on_crtc(dev, crtc, encoder) {
5828                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5829                         encoder->base.base.id,
5830                         drm_get_encoder_name(&encoder->base),
5831                         mode->base.id, mode->name);
5832                 encoder_funcs = encoder->base.helper_private;
5833                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5834         }
5835
5836         return 0;
5837 }
5838
5839 static bool intel_eld_uptodate(struct drm_connector *connector,
5840                                int reg_eldv, uint32_t bits_eldv,
5841                                int reg_elda, uint32_t bits_elda,
5842                                int reg_edid)
5843 {
5844         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5845         uint8_t *eld = connector->eld;
5846         uint32_t i;
5847
5848         i = I915_READ(reg_eldv);
5849         i &= bits_eldv;
5850
5851         if (!eld[0])
5852                 return !i;
5853
5854         if (!i)
5855                 return false;
5856
5857         i = I915_READ(reg_elda);
5858         i &= ~bits_elda;
5859         I915_WRITE(reg_elda, i);
5860
5861         for (i = 0; i < eld[2]; i++)
5862                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5863                         return false;
5864
5865         return true;
5866 }
5867
5868 static void g4x_write_eld(struct drm_connector *connector,
5869                           struct drm_crtc *crtc)
5870 {
5871         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5872         uint8_t *eld = connector->eld;
5873         uint32_t eldv;
5874         uint32_t len;
5875         uint32_t i;
5876
5877         i = I915_READ(G4X_AUD_VID_DID);
5878
5879         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5880                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5881         else
5882                 eldv = G4X_ELDV_DEVCTG;
5883
5884         if (intel_eld_uptodate(connector,
5885                                G4X_AUD_CNTL_ST, eldv,
5886                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5887                                G4X_HDMIW_HDMIEDID))
5888                 return;
5889
5890         i = I915_READ(G4X_AUD_CNTL_ST);
5891         i &= ~(eldv | G4X_ELD_ADDR);
5892         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5893         I915_WRITE(G4X_AUD_CNTL_ST, i);
5894
5895         if (!eld[0])
5896                 return;
5897
5898         len = min_t(uint8_t, eld[2], len);
5899         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5900         for (i = 0; i < len; i++)
5901                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5902
5903         i = I915_READ(G4X_AUD_CNTL_ST);
5904         i |= eldv;
5905         I915_WRITE(G4X_AUD_CNTL_ST, i);
5906 }
5907
5908 static void haswell_write_eld(struct drm_connector *connector,
5909                                      struct drm_crtc *crtc)
5910 {
5911         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5912         uint8_t *eld = connector->eld;
5913         struct drm_device *dev = crtc->dev;
5914         uint32_t eldv;
5915         uint32_t i;
5916         int len;
5917         int pipe = to_intel_crtc(crtc)->pipe;
5918         int tmp;
5919
5920         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5921         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5922         int aud_config = HSW_AUD_CFG(pipe);
5923         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5924
5925
5926         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5927
5928         /* Audio output enable */
5929         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5930         tmp = I915_READ(aud_cntrl_st2);
5931         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5932         I915_WRITE(aud_cntrl_st2, tmp);
5933
5934         /* Wait for 1 vertical blank */
5935         intel_wait_for_vblank(dev, pipe);
5936
5937         /* Set ELD valid state */
5938         tmp = I915_READ(aud_cntrl_st2);
5939         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5940         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5941         I915_WRITE(aud_cntrl_st2, tmp);
5942         tmp = I915_READ(aud_cntrl_st2);
5943         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5944
5945         /* Enable HDMI mode */
5946         tmp = I915_READ(aud_config);
5947         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5948         /* clear N_programing_enable and N_value_index */
5949         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5950         I915_WRITE(aud_config, tmp);
5951
5952         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5953
5954         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5955
5956         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5957                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5958                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5959                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5960         } else
5961                 I915_WRITE(aud_config, 0);
5962
5963         if (intel_eld_uptodate(connector,
5964                                aud_cntrl_st2, eldv,
5965                                aud_cntl_st, IBX_ELD_ADDRESS,
5966                                hdmiw_hdmiedid))
5967                 return;
5968
5969         i = I915_READ(aud_cntrl_st2);
5970         i &= ~eldv;
5971         I915_WRITE(aud_cntrl_st2, i);
5972
5973         if (!eld[0])
5974                 return;
5975
5976         i = I915_READ(aud_cntl_st);
5977         i &= ~IBX_ELD_ADDRESS;
5978         I915_WRITE(aud_cntl_st, i);
5979         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5980         DRM_DEBUG_DRIVER("port num:%d\n", i);
5981
5982         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5983         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984         for (i = 0; i < len; i++)
5985                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5986
5987         i = I915_READ(aud_cntrl_st2);
5988         i |= eldv;
5989         I915_WRITE(aud_cntrl_st2, i);
5990
5991 }
5992
5993 static void ironlake_write_eld(struct drm_connector *connector,
5994                                      struct drm_crtc *crtc)
5995 {
5996         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5997         uint8_t *eld = connector->eld;
5998         uint32_t eldv;
5999         uint32_t i;
6000         int len;
6001         int hdmiw_hdmiedid;
6002         int aud_config;
6003         int aud_cntl_st;
6004         int aud_cntrl_st2;
6005         int pipe = to_intel_crtc(crtc)->pipe;
6006
6007         if (HAS_PCH_IBX(connector->dev)) {
6008                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6009                 aud_config = IBX_AUD_CFG(pipe);
6010                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6011                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6012         } else {
6013                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6014                 aud_config = CPT_AUD_CFG(pipe);
6015                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6016                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6017         }
6018
6019         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6020
6021         i = I915_READ(aud_cntl_st);
6022         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6023         if (!i) {
6024                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6025                 /* operate blindly on all ports */
6026                 eldv = IBX_ELD_VALIDB;
6027                 eldv |= IBX_ELD_VALIDB << 4;
6028                 eldv |= IBX_ELD_VALIDB << 8;
6029         } else {
6030                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6031                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6032         }
6033
6034         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6035                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6036                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6037                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6038         } else
6039                 I915_WRITE(aud_config, 0);
6040
6041         if (intel_eld_uptodate(connector,
6042                                aud_cntrl_st2, eldv,
6043                                aud_cntl_st, IBX_ELD_ADDRESS,
6044                                hdmiw_hdmiedid))
6045                 return;
6046
6047         i = I915_READ(aud_cntrl_st2);
6048         i &= ~eldv;
6049         I915_WRITE(aud_cntrl_st2, i);
6050
6051         if (!eld[0])
6052                 return;
6053
6054         i = I915_READ(aud_cntl_st);
6055         i &= ~IBX_ELD_ADDRESS;
6056         I915_WRITE(aud_cntl_st, i);
6057
6058         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6059         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6060         for (i = 0; i < len; i++)
6061                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6062
6063         i = I915_READ(aud_cntrl_st2);
6064         i |= eldv;
6065         I915_WRITE(aud_cntrl_st2, i);
6066 }
6067
6068 void intel_write_eld(struct drm_encoder *encoder,
6069                      struct drm_display_mode *mode)
6070 {
6071         struct drm_crtc *crtc = encoder->crtc;
6072         struct drm_connector *connector;
6073         struct drm_device *dev = encoder->dev;
6074         struct drm_i915_private *dev_priv = dev->dev_private;
6075
6076         connector = drm_select_eld(encoder, mode);
6077         if (!connector)
6078                 return;
6079
6080         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6081                          connector->base.id,
6082                          drm_get_connector_name(connector),
6083                          connector->encoder->base.id,
6084                          drm_get_encoder_name(connector->encoder));
6085
6086         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6087
6088         if (dev_priv->display.write_eld)
6089                 dev_priv->display.write_eld(connector, crtc);
6090 }
6091
6092 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6093 void intel_crtc_load_lut(struct drm_crtc *crtc)
6094 {
6095         struct drm_device *dev = crtc->dev;
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098         int palreg = PALETTE(intel_crtc->pipe);
6099         int i;
6100
6101         /* The clocks have to be on to load the palette. */
6102         if (!crtc->enabled || !intel_crtc->active)
6103                 return;
6104
6105         /* use legacy palette for Ironlake */
6106         if (HAS_PCH_SPLIT(dev))
6107                 palreg = LGC_PALETTE(intel_crtc->pipe);
6108
6109         for (i = 0; i < 256; i++) {
6110                 I915_WRITE(palreg + 4 * i,
6111                            (intel_crtc->lut_r[i] << 16) |
6112                            (intel_crtc->lut_g[i] << 8) |
6113                            intel_crtc->lut_b[i]);
6114         }
6115 }
6116
6117 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6118 {
6119         struct drm_device *dev = crtc->dev;
6120         struct drm_i915_private *dev_priv = dev->dev_private;
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122         bool visible = base != 0;
6123         u32 cntl;
6124
6125         if (intel_crtc->cursor_visible == visible)
6126                 return;
6127
6128         cntl = I915_READ(_CURACNTR);
6129         if (visible) {
6130                 /* On these chipsets we can only modify the base whilst
6131                  * the cursor is disabled.
6132                  */
6133                 I915_WRITE(_CURABASE, base);
6134
6135                 cntl &= ~(CURSOR_FORMAT_MASK);
6136                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6137                 cntl |= CURSOR_ENABLE |
6138                         CURSOR_GAMMA_ENABLE |
6139                         CURSOR_FORMAT_ARGB;
6140         } else
6141                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6142         I915_WRITE(_CURACNTR, cntl);
6143
6144         intel_crtc->cursor_visible = visible;
6145 }
6146
6147 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6148 {
6149         struct drm_device *dev = crtc->dev;
6150         struct drm_i915_private *dev_priv = dev->dev_private;
6151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6152         int pipe = intel_crtc->pipe;
6153         bool visible = base != 0;
6154
6155         if (intel_crtc->cursor_visible != visible) {
6156                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6157                 if (base) {
6158                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6159                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6160                         cntl |= pipe << 28; /* Connect to correct pipe */
6161                 } else {
6162                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6163                         cntl |= CURSOR_MODE_DISABLE;
6164                 }
6165                 I915_WRITE(CURCNTR(pipe), cntl);
6166
6167                 intel_crtc->cursor_visible = visible;
6168         }
6169         /* and commit changes on next vblank */
6170         I915_WRITE(CURBASE(pipe), base);
6171 }
6172
6173 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6174 {
6175         struct drm_device *dev = crtc->dev;
6176         struct drm_i915_private *dev_priv = dev->dev_private;
6177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178         int pipe = intel_crtc->pipe;
6179         bool visible = base != 0;
6180
6181         if (intel_crtc->cursor_visible != visible) {
6182                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6183                 if (base) {
6184                         cntl &= ~CURSOR_MODE;
6185                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6186                 } else {
6187                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6188                         cntl |= CURSOR_MODE_DISABLE;
6189                 }
6190                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6191
6192                 intel_crtc->cursor_visible = visible;
6193         }
6194         /* and commit changes on next vblank */
6195         I915_WRITE(CURBASE_IVB(pipe), base);
6196 }
6197
6198 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6199 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6200                                      bool on)
6201 {
6202         struct drm_device *dev = crtc->dev;
6203         struct drm_i915_private *dev_priv = dev->dev_private;
6204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6205         int pipe = intel_crtc->pipe;
6206         int x = intel_crtc->cursor_x;
6207         int y = intel_crtc->cursor_y;
6208         u32 base, pos;
6209         bool visible;
6210
6211         pos = 0;
6212
6213         if (on && crtc->enabled && crtc->fb) {
6214                 base = intel_crtc->cursor_addr;
6215                 if (x > (int) crtc->fb->width)
6216                         base = 0;
6217
6218                 if (y > (int) crtc->fb->height)
6219                         base = 0;
6220         } else
6221                 base = 0;
6222
6223         if (x < 0) {
6224                 if (x + intel_crtc->cursor_width < 0)
6225                         base = 0;
6226
6227                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6228                 x = -x;
6229         }
6230         pos |= x << CURSOR_X_SHIFT;
6231
6232         if (y < 0) {
6233                 if (y + intel_crtc->cursor_height < 0)
6234                         base = 0;
6235
6236                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6237                 y = -y;
6238         }
6239         pos |= y << CURSOR_Y_SHIFT;
6240
6241         visible = base != 0;
6242         if (!visible && !intel_crtc->cursor_visible)
6243                 return;
6244
6245         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6246                 I915_WRITE(CURPOS_IVB(pipe), pos);
6247                 ivb_update_cursor(crtc, base);
6248         } else {
6249                 I915_WRITE(CURPOS(pipe), pos);
6250                 if (IS_845G(dev) || IS_I865G(dev))
6251                         i845_update_cursor(crtc, base);
6252                 else
6253                         i9xx_update_cursor(crtc, base);
6254         }
6255 }
6256
6257 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6258                                  struct drm_file *file,
6259                                  uint32_t handle,
6260                                  uint32_t width, uint32_t height)
6261 {
6262         struct drm_device *dev = crtc->dev;
6263         struct drm_i915_private *dev_priv = dev->dev_private;
6264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265         struct drm_i915_gem_object *obj;
6266         uint32_t addr;
6267         int ret;
6268
6269         /* if we want to turn off the cursor ignore width and height */
6270         if (!handle) {
6271                 DRM_DEBUG_KMS("cursor off\n");
6272                 addr = 0;
6273                 obj = NULL;
6274                 mutex_lock(&dev->struct_mutex);
6275                 goto finish;
6276         }
6277
6278         /* Currently we only support 64x64 cursors */
6279         if (width != 64 || height != 64) {
6280                 DRM_ERROR("we currently only support 64x64 cursors\n");
6281                 return -EINVAL;
6282         }
6283
6284         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6285         if (&obj->base == NULL)
6286                 return -ENOENT;
6287
6288         if (obj->base.size < width * height * 4) {
6289                 DRM_ERROR("buffer is to small\n");
6290                 ret = -ENOMEM;
6291                 goto fail;
6292         }
6293
6294         /* we only need to pin inside GTT if cursor is non-phy */
6295         mutex_lock(&dev->struct_mutex);
6296         if (!dev_priv->info->cursor_needs_physical) {
6297                 if (obj->tiling_mode) {
6298                         DRM_ERROR("cursor cannot be tiled\n");
6299                         ret = -EINVAL;
6300                         goto fail_locked;
6301                 }
6302
6303                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6304                 if (ret) {
6305                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6306                         goto fail_locked;
6307                 }
6308
6309                 ret = i915_gem_object_put_fence(obj);
6310                 if (ret) {
6311                         DRM_ERROR("failed to release fence for cursor");
6312                         goto fail_unpin;
6313                 }
6314
6315                 addr = obj->gtt_offset;
6316         } else {
6317                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6318                 ret = i915_gem_attach_phys_object(dev, obj,
6319                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6320                                                   align);
6321                 if (ret) {
6322                         DRM_ERROR("failed to attach phys object\n");
6323                         goto fail_locked;
6324                 }
6325                 addr = obj->phys_obj->handle->busaddr;
6326         }
6327
6328         if (IS_GEN2(dev))
6329                 I915_WRITE(CURSIZE, (height << 12) | width);
6330
6331  finish:
6332         if (intel_crtc->cursor_bo) {
6333                 if (dev_priv->info->cursor_needs_physical) {
6334                         if (intel_crtc->cursor_bo != obj)
6335                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6336                 } else
6337                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6338                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6339         }
6340
6341         mutex_unlock(&dev->struct_mutex);
6342
6343         intel_crtc->cursor_addr = addr;
6344         intel_crtc->cursor_bo = obj;
6345         intel_crtc->cursor_width = width;
6346         intel_crtc->cursor_height = height;
6347
6348         intel_crtc_update_cursor(crtc, true);
6349
6350         return 0;
6351 fail_unpin:
6352         i915_gem_object_unpin(obj);
6353 fail_locked:
6354         mutex_unlock(&dev->struct_mutex);
6355 fail:
6356         drm_gem_object_unreference_unlocked(&obj->base);
6357         return ret;
6358 }
6359
6360 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6361 {
6362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363
6364         intel_crtc->cursor_x = x;
6365         intel_crtc->cursor_y = y;
6366
6367         intel_crtc_update_cursor(crtc, true);
6368
6369         return 0;
6370 }
6371
6372 /** Sets the color ramps on behalf of RandR */
6373 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6374                                  u16 blue, int regno)
6375 {
6376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6377
6378         intel_crtc->lut_r[regno] = red >> 8;
6379         intel_crtc->lut_g[regno] = green >> 8;
6380         intel_crtc->lut_b[regno] = blue >> 8;
6381 }
6382
6383 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6384                              u16 *blue, int regno)
6385 {
6386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387
6388         *red = intel_crtc->lut_r[regno] << 8;
6389         *green = intel_crtc->lut_g[regno] << 8;
6390         *blue = intel_crtc->lut_b[regno] << 8;
6391 }
6392
6393 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6394                                  u16 *blue, uint32_t start, uint32_t size)
6395 {
6396         int end = (start + size > 256) ? 256 : start + size, i;
6397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399         for (i = start; i < end; i++) {
6400                 intel_crtc->lut_r[i] = red[i] >> 8;
6401                 intel_crtc->lut_g[i] = green[i] >> 8;
6402                 intel_crtc->lut_b[i] = blue[i] >> 8;
6403         }
6404
6405         intel_crtc_load_lut(crtc);
6406 }
6407
6408 /**
6409  * Get a pipe with a simple mode set on it for doing load-based monitor
6410  * detection.
6411  *
6412  * It will be up to the load-detect code to adjust the pipe as appropriate for
6413  * its requirements.  The pipe will be connected to no other encoders.
6414  *
6415  * Currently this code will only succeed if there is a pipe with no encoders
6416  * configured for it.  In the future, it could choose to temporarily disable
6417  * some outputs to free up a pipe for its use.
6418  *
6419  * \return crtc, or NULL if no pipes are available.
6420  */
6421
6422 /* VESA 640x480x72Hz mode to set on the pipe */
6423 static struct drm_display_mode load_detect_mode = {
6424         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6425                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6426 };
6427
6428 static struct drm_framebuffer *
6429 intel_framebuffer_create(struct drm_device *dev,
6430                          struct drm_mode_fb_cmd2 *mode_cmd,
6431                          struct drm_i915_gem_object *obj)
6432 {
6433         struct intel_framebuffer *intel_fb;
6434         int ret;
6435
6436         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6437         if (!intel_fb) {
6438                 drm_gem_object_unreference_unlocked(&obj->base);
6439                 return ERR_PTR(-ENOMEM);
6440         }
6441
6442         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6443         if (ret) {
6444                 drm_gem_object_unreference_unlocked(&obj->base);
6445                 kfree(intel_fb);
6446                 return ERR_PTR(ret);
6447         }
6448
6449         return &intel_fb->base;
6450 }
6451
6452 static u32
6453 intel_framebuffer_pitch_for_width(int width, int bpp)
6454 {
6455         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6456         return ALIGN(pitch, 64);
6457 }
6458
6459 static u32
6460 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6461 {
6462         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6463         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6464 }
6465
6466 static struct drm_framebuffer *
6467 intel_framebuffer_create_for_mode(struct drm_device *dev,
6468                                   struct drm_display_mode *mode,
6469                                   int depth, int bpp)
6470 {
6471         struct drm_i915_gem_object *obj;
6472         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6473
6474         obj = i915_gem_alloc_object(dev,
6475                                     intel_framebuffer_size_for_mode(mode, bpp));
6476         if (obj == NULL)
6477                 return ERR_PTR(-ENOMEM);
6478
6479         mode_cmd.width = mode->hdisplay;
6480         mode_cmd.height = mode->vdisplay;
6481         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6482                                                                 bpp);
6483         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6484
6485         return intel_framebuffer_create(dev, &mode_cmd, obj);
6486 }
6487
6488 static struct drm_framebuffer *
6489 mode_fits_in_fbdev(struct drm_device *dev,
6490                    struct drm_display_mode *mode)
6491 {
6492         struct drm_i915_private *dev_priv = dev->dev_private;
6493         struct drm_i915_gem_object *obj;
6494         struct drm_framebuffer *fb;
6495
6496         if (dev_priv->fbdev == NULL)
6497                 return NULL;
6498
6499         obj = dev_priv->fbdev->ifb.obj;
6500         if (obj == NULL)
6501                 return NULL;
6502
6503         fb = &dev_priv->fbdev->ifb.base;
6504         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6505                                                                fb->bits_per_pixel))
6506                 return NULL;
6507
6508         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6509                 return NULL;
6510
6511         return fb;
6512 }
6513
6514 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6515                                 struct drm_display_mode *mode,
6516                                 struct intel_load_detect_pipe *old)
6517 {
6518         struct intel_crtc *intel_crtc;
6519         struct intel_encoder *intel_encoder =
6520                 intel_attached_encoder(connector);
6521         struct drm_crtc *possible_crtc;
6522         struct drm_encoder *encoder = &intel_encoder->base;
6523         struct drm_crtc *crtc = NULL;
6524         struct drm_device *dev = encoder->dev;
6525         struct drm_framebuffer *fb;
6526         int i = -1;
6527
6528         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6529                       connector->base.id, drm_get_connector_name(connector),
6530                       encoder->base.id, drm_get_encoder_name(encoder));
6531
6532         /*
6533          * Algorithm gets a little messy:
6534          *
6535          *   - if the connector already has an assigned crtc, use it (but make
6536          *     sure it's on first)
6537          *
6538          *   - try to find the first unused crtc that can drive this connector,
6539          *     and use that if we find one
6540          */
6541
6542         /* See if we already have a CRTC for this connector */
6543         if (encoder->crtc) {
6544                 crtc = encoder->crtc;
6545
6546                 old->dpms_mode = connector->dpms;
6547                 old->load_detect_temp = false;
6548
6549                 /* Make sure the crtc and connector are running */
6550                 if (connector->dpms != DRM_MODE_DPMS_ON)
6551                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6552
6553                 return true;
6554         }
6555
6556         /* Find an unused one (if possible) */
6557         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6558                 i++;
6559                 if (!(encoder->possible_crtcs & (1 << i)))
6560                         continue;
6561                 if (!possible_crtc->enabled) {
6562                         crtc = possible_crtc;
6563                         break;
6564                 }
6565         }
6566
6567         /*
6568          * If we didn't find an unused CRTC, don't use any.
6569          */
6570         if (!crtc) {
6571                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6572                 return false;
6573         }
6574
6575         intel_encoder->new_crtc = to_intel_crtc(crtc);
6576         to_intel_connector(connector)->new_encoder = intel_encoder;
6577
6578         intel_crtc = to_intel_crtc(crtc);
6579         old->dpms_mode = connector->dpms;
6580         old->load_detect_temp = true;
6581         old->release_fb = NULL;
6582
6583         if (!mode)
6584                 mode = &load_detect_mode;
6585
6586         /* We need a framebuffer large enough to accommodate all accesses
6587          * that the plane may generate whilst we perform load detection.
6588          * We can not rely on the fbcon either being present (we get called
6589          * during its initialisation to detect all boot displays, or it may
6590          * not even exist) or that it is large enough to satisfy the
6591          * requested mode.
6592          */
6593         fb = mode_fits_in_fbdev(dev, mode);
6594         if (fb == NULL) {
6595                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6596                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6597                 old->release_fb = fb;
6598         } else
6599                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6600         if (IS_ERR(fb)) {
6601                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6602                 return false;
6603         }
6604
6605         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6606                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6607                 if (old->release_fb)
6608                         old->release_fb->funcs->destroy(old->release_fb);
6609                 return false;
6610         }
6611
6612         /* let the connector get through one full cycle before testing */
6613         intel_wait_for_vblank(dev, intel_crtc->pipe);
6614         return true;
6615 }
6616
6617 void intel_release_load_detect_pipe(struct drm_connector *connector,
6618                                     struct intel_load_detect_pipe *old)
6619 {
6620         struct intel_encoder *intel_encoder =
6621                 intel_attached_encoder(connector);
6622         struct drm_encoder *encoder = &intel_encoder->base;
6623
6624         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6625                       connector->base.id, drm_get_connector_name(connector),
6626                       encoder->base.id, drm_get_encoder_name(encoder));
6627
6628         if (old->load_detect_temp) {
6629                 struct drm_crtc *crtc = encoder->crtc;
6630
6631                 to_intel_connector(connector)->new_encoder = NULL;
6632                 intel_encoder->new_crtc = NULL;
6633                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6634
6635                 if (old->release_fb)
6636                         old->release_fb->funcs->destroy(old->release_fb);
6637
6638                 return;
6639         }
6640
6641         /* Switch crtc and encoder back off if necessary */
6642         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6643                 connector->funcs->dpms(connector, old->dpms_mode);
6644 }
6645
6646 /* Returns the clock of the currently programmed mode of the given pipe. */
6647 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6648 {
6649         struct drm_i915_private *dev_priv = dev->dev_private;
6650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6651         int pipe = intel_crtc->pipe;
6652         u32 dpll = I915_READ(DPLL(pipe));
6653         u32 fp;
6654         intel_clock_t clock;
6655
6656         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6657                 fp = I915_READ(FP0(pipe));
6658         else
6659                 fp = I915_READ(FP1(pipe));
6660
6661         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6662         if (IS_PINEVIEW(dev)) {
6663                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6664                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6665         } else {
6666                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6667                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6668         }
6669
6670         if (!IS_GEN2(dev)) {
6671                 if (IS_PINEVIEW(dev))
6672                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6673                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6674                 else
6675                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6676                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6677
6678                 switch (dpll & DPLL_MODE_MASK) {
6679                 case DPLLB_MODE_DAC_SERIAL:
6680                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6681                                 5 : 10;
6682                         break;
6683                 case DPLLB_MODE_LVDS:
6684                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6685                                 7 : 14;
6686                         break;
6687                 default:
6688                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6689                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6690                         return 0;
6691                 }
6692
6693                 /* XXX: Handle the 100Mhz refclk */
6694                 intel_clock(dev, 96000, &clock);
6695         } else {
6696                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6697
6698                 if (is_lvds) {
6699                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6700                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6701                         clock.p2 = 14;
6702
6703                         if ((dpll & PLL_REF_INPUT_MASK) ==
6704                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6705                                 /* XXX: might not be 66MHz */
6706                                 intel_clock(dev, 66000, &clock);
6707                         } else
6708                                 intel_clock(dev, 48000, &clock);
6709                 } else {
6710                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6711                                 clock.p1 = 2;
6712                         else {
6713                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6714                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6715                         }
6716                         if (dpll & PLL_P2_DIVIDE_BY_4)
6717                                 clock.p2 = 4;
6718                         else
6719                                 clock.p2 = 2;
6720
6721                         intel_clock(dev, 48000, &clock);
6722                 }
6723         }
6724
6725         /* XXX: It would be nice to validate the clocks, but we can't reuse
6726          * i830PllIsValid() because it relies on the xf86_config connector
6727          * configuration being accurate, which it isn't necessarily.
6728          */
6729
6730         return clock.dot;
6731 }
6732
6733 /** Returns the currently programmed mode of the given pipe. */
6734 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6735                                              struct drm_crtc *crtc)
6736 {
6737         struct drm_i915_private *dev_priv = dev->dev_private;
6738         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6739         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6740         struct drm_display_mode *mode;
6741         int htot = I915_READ(HTOTAL(cpu_transcoder));
6742         int hsync = I915_READ(HSYNC(cpu_transcoder));
6743         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6744         int vsync = I915_READ(VSYNC(cpu_transcoder));
6745
6746         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6747         if (!mode)
6748                 return NULL;
6749
6750         mode->clock = intel_crtc_clock_get(dev, crtc);
6751         mode->hdisplay = (htot & 0xffff) + 1;
6752         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6753         mode->hsync_start = (hsync & 0xffff) + 1;
6754         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6755         mode->vdisplay = (vtot & 0xffff) + 1;
6756         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6757         mode->vsync_start = (vsync & 0xffff) + 1;
6758         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6759
6760         drm_mode_set_name(mode);
6761
6762         return mode;
6763 }
6764
6765 static void intel_increase_pllclock(struct drm_crtc *crtc)
6766 {
6767         struct drm_device *dev = crtc->dev;
6768         drm_i915_private_t *dev_priv = dev->dev_private;
6769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6770         int pipe = intel_crtc->pipe;
6771         int dpll_reg = DPLL(pipe);
6772         int dpll;
6773
6774         if (HAS_PCH_SPLIT(dev))
6775                 return;
6776
6777         if (!dev_priv->lvds_downclock_avail)
6778                 return;
6779
6780         dpll = I915_READ(dpll_reg);
6781         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6782                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6783
6784                 assert_panel_unlocked(dev_priv, pipe);
6785
6786                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6787                 I915_WRITE(dpll_reg, dpll);
6788                 intel_wait_for_vblank(dev, pipe);
6789
6790                 dpll = I915_READ(dpll_reg);
6791                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6792                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6793         }
6794 }
6795
6796 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6797 {
6798         struct drm_device *dev = crtc->dev;
6799         drm_i915_private_t *dev_priv = dev->dev_private;
6800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6801
6802         if (HAS_PCH_SPLIT(dev))
6803                 return;
6804
6805         if (!dev_priv->lvds_downclock_avail)
6806                 return;
6807
6808         /*
6809          * Since this is called by a timer, we should never get here in
6810          * the manual case.
6811          */
6812         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6813                 int pipe = intel_crtc->pipe;
6814                 int dpll_reg = DPLL(pipe);
6815                 int dpll;
6816
6817                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6818
6819                 assert_panel_unlocked(dev_priv, pipe);
6820
6821                 dpll = I915_READ(dpll_reg);
6822                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6823                 I915_WRITE(dpll_reg, dpll);
6824                 intel_wait_for_vblank(dev, pipe);
6825                 dpll = I915_READ(dpll_reg);
6826                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6827                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6828         }
6829
6830 }
6831
6832 void intel_mark_busy(struct drm_device *dev)
6833 {
6834         i915_update_gfx_val(dev->dev_private);
6835 }
6836
6837 void intel_mark_idle(struct drm_device *dev)
6838 {
6839 }
6840
6841 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6842 {
6843         struct drm_device *dev = obj->base.dev;
6844         struct drm_crtc *crtc;
6845
6846         if (!i915_powersave)
6847                 return;
6848
6849         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6850                 if (!crtc->fb)
6851                         continue;
6852
6853                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6854                         intel_increase_pllclock(crtc);
6855         }
6856 }
6857
6858 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6859 {
6860         struct drm_device *dev = obj->base.dev;
6861         struct drm_crtc *crtc;
6862
6863         if (!i915_powersave)
6864                 return;
6865
6866         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6867                 if (!crtc->fb)
6868                         continue;
6869
6870                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6871                         intel_decrease_pllclock(crtc);
6872         }
6873 }
6874
6875 static void intel_crtc_destroy(struct drm_crtc *crtc)
6876 {
6877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6878         struct drm_device *dev = crtc->dev;
6879         struct intel_unpin_work *work;
6880         unsigned long flags;
6881
6882         spin_lock_irqsave(&dev->event_lock, flags);
6883         work = intel_crtc->unpin_work;
6884         intel_crtc->unpin_work = NULL;
6885         spin_unlock_irqrestore(&dev->event_lock, flags);
6886
6887         if (work) {
6888                 cancel_work_sync(&work->work);
6889                 kfree(work);
6890         }
6891
6892         drm_crtc_cleanup(crtc);
6893
6894         kfree(intel_crtc);
6895 }
6896
6897 static void intel_unpin_work_fn(struct work_struct *__work)
6898 {
6899         struct intel_unpin_work *work =
6900                 container_of(__work, struct intel_unpin_work, work);
6901         struct drm_device *dev = work->crtc->dev;
6902
6903         mutex_lock(&dev->struct_mutex);
6904         intel_unpin_fb_obj(work->old_fb_obj);
6905         drm_gem_object_unreference(&work->pending_flip_obj->base);
6906         drm_gem_object_unreference(&work->old_fb_obj->base);
6907
6908         intel_update_fbc(dev);
6909         mutex_unlock(&dev->struct_mutex);
6910
6911         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6912         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6913
6914         kfree(work);
6915 }
6916
6917 static void do_intel_finish_page_flip(struct drm_device *dev,
6918                                       struct drm_crtc *crtc)
6919 {
6920         drm_i915_private_t *dev_priv = dev->dev_private;
6921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6922         struct intel_unpin_work *work;
6923         struct drm_i915_gem_object *obj;
6924         struct drm_pending_vblank_event *e;
6925         struct timeval tvbl;
6926         unsigned long flags;
6927
6928         /* Ignore early vblank irqs */
6929         if (intel_crtc == NULL)
6930                 return;
6931
6932         spin_lock_irqsave(&dev->event_lock, flags);
6933         work = intel_crtc->unpin_work;
6934         if (work == NULL || !work->pending) {
6935                 spin_unlock_irqrestore(&dev->event_lock, flags);
6936                 return;
6937         }
6938
6939         intel_crtc->unpin_work = NULL;
6940
6941         if (work->event) {
6942                 e = work->event;
6943                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6944
6945                 e->event.tv_sec = tvbl.tv_sec;
6946                 e->event.tv_usec = tvbl.tv_usec;
6947
6948                 list_add_tail(&e->base.link,
6949                               &e->base.file_priv->event_list);
6950                 wake_up_interruptible(&e->base.file_priv->event_wait);
6951         }
6952
6953         drm_vblank_put(dev, intel_crtc->pipe);
6954
6955         spin_unlock_irqrestore(&dev->event_lock, flags);
6956
6957         obj = work->old_fb_obj;
6958
6959         atomic_clear_mask(1 << intel_crtc->plane,
6960                           &obj->pending_flip.counter);
6961         wake_up(&dev_priv->pending_flip_queue);
6962
6963         queue_work(dev_priv->wq, &work->work);
6964
6965         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6966 }
6967
6968 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6969 {
6970         drm_i915_private_t *dev_priv = dev->dev_private;
6971         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6972
6973         do_intel_finish_page_flip(dev, crtc);
6974 }
6975
6976 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6977 {
6978         drm_i915_private_t *dev_priv = dev->dev_private;
6979         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6980
6981         do_intel_finish_page_flip(dev, crtc);
6982 }
6983
6984 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6985 {
6986         drm_i915_private_t *dev_priv = dev->dev_private;
6987         struct intel_crtc *intel_crtc =
6988                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6989         unsigned long flags;
6990
6991         spin_lock_irqsave(&dev->event_lock, flags);
6992         if (intel_crtc->unpin_work) {
6993                 if ((++intel_crtc->unpin_work->pending) > 1)
6994                         DRM_ERROR("Prepared flip multiple times\n");
6995         } else {
6996                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6997         }
6998         spin_unlock_irqrestore(&dev->event_lock, flags);
6999 }
7000
7001 static int intel_gen2_queue_flip(struct drm_device *dev,
7002                                  struct drm_crtc *crtc,
7003                                  struct drm_framebuffer *fb,
7004                                  struct drm_i915_gem_object *obj)
7005 {
7006         struct drm_i915_private *dev_priv = dev->dev_private;
7007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7008         u32 flip_mask;
7009         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7010         int ret;
7011
7012         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7013         if (ret)
7014                 goto err;
7015
7016         ret = intel_ring_begin(ring, 6);
7017         if (ret)
7018                 goto err_unpin;
7019
7020         /* Can't queue multiple flips, so wait for the previous
7021          * one to finish before executing the next.
7022          */
7023         if (intel_crtc->plane)
7024                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7025         else
7026                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7027         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7028         intel_ring_emit(ring, MI_NOOP);
7029         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7030                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7031         intel_ring_emit(ring, fb->pitches[0]);
7032         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7033         intel_ring_emit(ring, 0); /* aux display base address, unused */
7034         intel_ring_advance(ring);
7035         return 0;
7036
7037 err_unpin:
7038         intel_unpin_fb_obj(obj);
7039 err:
7040         return ret;
7041 }
7042
7043 static int intel_gen3_queue_flip(struct drm_device *dev,
7044                                  struct drm_crtc *crtc,
7045                                  struct drm_framebuffer *fb,
7046                                  struct drm_i915_gem_object *obj)
7047 {
7048         struct drm_i915_private *dev_priv = dev->dev_private;
7049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7050         u32 flip_mask;
7051         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7052         int ret;
7053
7054         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7055         if (ret)
7056                 goto err;
7057
7058         ret = intel_ring_begin(ring, 6);
7059         if (ret)
7060                 goto err_unpin;
7061
7062         if (intel_crtc->plane)
7063                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7064         else
7065                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7066         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7067         intel_ring_emit(ring, MI_NOOP);
7068         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7069                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7070         intel_ring_emit(ring, fb->pitches[0]);
7071         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7072         intel_ring_emit(ring, MI_NOOP);
7073
7074         intel_ring_advance(ring);
7075         return 0;
7076
7077 err_unpin:
7078         intel_unpin_fb_obj(obj);
7079 err:
7080         return ret;
7081 }
7082
7083 static int intel_gen4_queue_flip(struct drm_device *dev,
7084                                  struct drm_crtc *crtc,
7085                                  struct drm_framebuffer *fb,
7086                                  struct drm_i915_gem_object *obj)
7087 {
7088         struct drm_i915_private *dev_priv = dev->dev_private;
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090         uint32_t pf, pipesrc;
7091         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7092         int ret;
7093
7094         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7095         if (ret)
7096                 goto err;
7097
7098         ret = intel_ring_begin(ring, 4);
7099         if (ret)
7100                 goto err_unpin;
7101
7102         /* i965+ uses the linear or tiled offsets from the
7103          * Display Registers (which do not change across a page-flip)
7104          * so we need only reprogram the base address.
7105          */
7106         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7107                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7108         intel_ring_emit(ring, fb->pitches[0]);
7109         intel_ring_emit(ring,
7110                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7111                         obj->tiling_mode);
7112
7113         /* XXX Enabling the panel-fitter across page-flip is so far
7114          * untested on non-native modes, so ignore it for now.
7115          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7116          */
7117         pf = 0;
7118         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7119         intel_ring_emit(ring, pf | pipesrc);
7120         intel_ring_advance(ring);
7121         return 0;
7122
7123 err_unpin:
7124         intel_unpin_fb_obj(obj);
7125 err:
7126         return ret;
7127 }
7128
7129 static int intel_gen6_queue_flip(struct drm_device *dev,
7130                                  struct drm_crtc *crtc,
7131                                  struct drm_framebuffer *fb,
7132                                  struct drm_i915_gem_object *obj)
7133 {
7134         struct drm_i915_private *dev_priv = dev->dev_private;
7135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7136         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7137         uint32_t pf, pipesrc;
7138         int ret;
7139
7140         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7141         if (ret)
7142                 goto err;
7143
7144         ret = intel_ring_begin(ring, 4);
7145         if (ret)
7146                 goto err_unpin;
7147
7148         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7149                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7150         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7151         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7152
7153         /* Contrary to the suggestions in the documentation,
7154          * "Enable Panel Fitter" does not seem to be required when page
7155          * flipping with a non-native mode, and worse causes a normal
7156          * modeset to fail.
7157          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7158          */
7159         pf = 0;
7160         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7161         intel_ring_emit(ring, pf | pipesrc);
7162         intel_ring_advance(ring);
7163         return 0;
7164
7165 err_unpin:
7166         intel_unpin_fb_obj(obj);
7167 err:
7168         return ret;
7169 }
7170
7171 /*
7172  * On gen7 we currently use the blit ring because (in early silicon at least)
7173  * the render ring doesn't give us interrpts for page flip completion, which
7174  * means clients will hang after the first flip is queued.  Fortunately the
7175  * blit ring generates interrupts properly, so use it instead.
7176  */
7177 static int intel_gen7_queue_flip(struct drm_device *dev,
7178                                  struct drm_crtc *crtc,
7179                                  struct drm_framebuffer *fb,
7180                                  struct drm_i915_gem_object *obj)
7181 {
7182         struct drm_i915_private *dev_priv = dev->dev_private;
7183         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7184         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7185         uint32_t plane_bit = 0;
7186         int ret;
7187
7188         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7189         if (ret)
7190                 goto err;
7191
7192         switch(intel_crtc->plane) {
7193         case PLANE_A:
7194                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7195                 break;
7196         case PLANE_B:
7197                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7198                 break;
7199         case PLANE_C:
7200                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7201                 break;
7202         default:
7203                 WARN_ONCE(1, "unknown plane in flip command\n");
7204                 ret = -ENODEV;
7205                 goto err_unpin;
7206         }
7207
7208         ret = intel_ring_begin(ring, 4);
7209         if (ret)
7210                 goto err_unpin;
7211
7212         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7213         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7214         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7215         intel_ring_emit(ring, (MI_NOOP));
7216         intel_ring_advance(ring);
7217         return 0;
7218
7219 err_unpin:
7220         intel_unpin_fb_obj(obj);
7221 err:
7222         return ret;
7223 }
7224
7225 static int intel_default_queue_flip(struct drm_device *dev,
7226                                     struct drm_crtc *crtc,
7227                                     struct drm_framebuffer *fb,
7228                                     struct drm_i915_gem_object *obj)
7229 {
7230         return -ENODEV;
7231 }
7232
7233 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7234                                 struct drm_framebuffer *fb,
7235                                 struct drm_pending_vblank_event *event)
7236 {
7237         struct drm_device *dev = crtc->dev;
7238         struct drm_i915_private *dev_priv = dev->dev_private;
7239         struct intel_framebuffer *intel_fb;
7240         struct drm_i915_gem_object *obj;
7241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7242         struct intel_unpin_work *work;
7243         unsigned long flags;
7244         int ret;
7245
7246         /* Can't change pixel format via MI display flips. */
7247         if (fb->pixel_format != crtc->fb->pixel_format)
7248                 return -EINVAL;
7249
7250         /*
7251          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7252          * Note that pitch changes could also affect these register.
7253          */
7254         if (INTEL_INFO(dev)->gen > 3 &&
7255             (fb->offsets[0] != crtc->fb->offsets[0] ||
7256              fb->pitches[0] != crtc->fb->pitches[0]))
7257                 return -EINVAL;
7258
7259         work = kzalloc(sizeof *work, GFP_KERNEL);
7260         if (work == NULL)
7261                 return -ENOMEM;
7262
7263         work->event = event;
7264         work->crtc = crtc;
7265         intel_fb = to_intel_framebuffer(crtc->fb);
7266         work->old_fb_obj = intel_fb->obj;
7267         INIT_WORK(&work->work, intel_unpin_work_fn);
7268
7269         ret = drm_vblank_get(dev, intel_crtc->pipe);
7270         if (ret)
7271                 goto free_work;
7272
7273         /* We borrow the event spin lock for protecting unpin_work */
7274         spin_lock_irqsave(&dev->event_lock, flags);
7275         if (intel_crtc->unpin_work) {
7276                 spin_unlock_irqrestore(&dev->event_lock, flags);
7277                 kfree(work);
7278                 drm_vblank_put(dev, intel_crtc->pipe);
7279
7280                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7281                 return -EBUSY;
7282         }
7283         intel_crtc->unpin_work = work;
7284         spin_unlock_irqrestore(&dev->event_lock, flags);
7285
7286         intel_fb = to_intel_framebuffer(fb);
7287         obj = intel_fb->obj;
7288
7289         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7290                 flush_workqueue(dev_priv->wq);
7291
7292         ret = i915_mutex_lock_interruptible(dev);
7293         if (ret)
7294                 goto cleanup;
7295
7296         /* Reference the objects for the scheduled work. */
7297         drm_gem_object_reference(&work->old_fb_obj->base);
7298         drm_gem_object_reference(&obj->base);
7299
7300         crtc->fb = fb;
7301
7302         work->pending_flip_obj = obj;
7303
7304         work->enable_stall_check = true;
7305
7306         /* Block clients from rendering to the new back buffer until
7307          * the flip occurs and the object is no longer visible.
7308          */
7309         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7310         atomic_inc(&intel_crtc->unpin_work_count);
7311
7312         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7313         if (ret)
7314                 goto cleanup_pending;
7315
7316         intel_disable_fbc(dev);
7317         intel_mark_fb_busy(obj);
7318         mutex_unlock(&dev->struct_mutex);
7319
7320         trace_i915_flip_request(intel_crtc->plane, obj);
7321
7322         return 0;
7323
7324 cleanup_pending:
7325         atomic_dec(&intel_crtc->unpin_work_count);
7326         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7327         drm_gem_object_unreference(&work->old_fb_obj->base);
7328         drm_gem_object_unreference(&obj->base);
7329         mutex_unlock(&dev->struct_mutex);
7330
7331 cleanup:
7332         spin_lock_irqsave(&dev->event_lock, flags);
7333         intel_crtc->unpin_work = NULL;
7334         spin_unlock_irqrestore(&dev->event_lock, flags);
7335
7336         drm_vblank_put(dev, intel_crtc->pipe);
7337 free_work:
7338         kfree(work);
7339
7340         return ret;
7341 }
7342
7343 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7344         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7345         .load_lut = intel_crtc_load_lut,
7346         .disable = intel_crtc_noop,
7347 };
7348
7349 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7350 {
7351         struct intel_encoder *other_encoder;
7352         struct drm_crtc *crtc = &encoder->new_crtc->base;
7353
7354         if (WARN_ON(!crtc))
7355                 return false;
7356
7357         list_for_each_entry(other_encoder,
7358                             &crtc->dev->mode_config.encoder_list,
7359                             base.head) {
7360
7361                 if (&other_encoder->new_crtc->base != crtc ||
7362                     encoder == other_encoder)
7363                         continue;
7364                 else
7365                         return true;
7366         }
7367
7368         return false;
7369 }
7370
7371 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7372                                   struct drm_crtc *crtc)
7373 {
7374         struct drm_device *dev;
7375         struct drm_crtc *tmp;
7376         int crtc_mask = 1;
7377
7378         WARN(!crtc, "checking null crtc?\n");
7379
7380         dev = crtc->dev;
7381
7382         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7383                 if (tmp == crtc)
7384                         break;
7385                 crtc_mask <<= 1;
7386         }
7387
7388         if (encoder->possible_crtcs & crtc_mask)
7389                 return true;
7390         return false;
7391 }
7392
7393 /**
7394  * intel_modeset_update_staged_output_state
7395  *
7396  * Updates the staged output configuration state, e.g. after we've read out the
7397  * current hw state.
7398  */
7399 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7400 {
7401         struct intel_encoder *encoder;
7402         struct intel_connector *connector;
7403
7404         list_for_each_entry(connector, &dev->mode_config.connector_list,
7405                             base.head) {
7406                 connector->new_encoder =
7407                         to_intel_encoder(connector->base.encoder);
7408         }
7409
7410         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7411                             base.head) {
7412                 encoder->new_crtc =
7413                         to_intel_crtc(encoder->base.crtc);
7414         }
7415 }
7416
7417 /**
7418  * intel_modeset_commit_output_state
7419  *
7420  * This function copies the stage display pipe configuration to the real one.
7421  */
7422 static void intel_modeset_commit_output_state(struct drm_device *dev)
7423 {
7424         struct intel_encoder *encoder;
7425         struct intel_connector *connector;
7426
7427         list_for_each_entry(connector, &dev->mode_config.connector_list,
7428                             base.head) {
7429                 connector->base.encoder = &connector->new_encoder->base;
7430         }
7431
7432         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7433                             base.head) {
7434                 encoder->base.crtc = &encoder->new_crtc->base;
7435         }
7436 }
7437
7438 static struct drm_display_mode *
7439 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7440                             struct drm_display_mode *mode)
7441 {
7442         struct drm_device *dev = crtc->dev;
7443         struct drm_display_mode *adjusted_mode;
7444         struct drm_encoder_helper_funcs *encoder_funcs;
7445         struct intel_encoder *encoder;
7446
7447         adjusted_mode = drm_mode_duplicate(dev, mode);
7448         if (!adjusted_mode)
7449                 return ERR_PTR(-ENOMEM);
7450
7451         /* Pass our mode to the connectors and the CRTC to give them a chance to
7452          * adjust it according to limitations or connector properties, and also
7453          * a chance to reject the mode entirely.
7454          */
7455         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7456                             base.head) {
7457
7458                 if (&encoder->new_crtc->base != crtc)
7459                         continue;
7460                 encoder_funcs = encoder->base.helper_private;
7461                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7462                                                 adjusted_mode))) {
7463                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7464                         goto fail;
7465                 }
7466         }
7467
7468         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7469                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7470                 goto fail;
7471         }
7472         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7473
7474         return adjusted_mode;
7475 fail:
7476         drm_mode_destroy(dev, adjusted_mode);
7477         return ERR_PTR(-EINVAL);
7478 }
7479
7480 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7481  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7482 static void
7483 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7484                              unsigned *prepare_pipes, unsigned *disable_pipes)
7485 {
7486         struct intel_crtc *intel_crtc;
7487         struct drm_device *dev = crtc->dev;
7488         struct intel_encoder *encoder;
7489         struct intel_connector *connector;
7490         struct drm_crtc *tmp_crtc;
7491
7492         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7493
7494         /* Check which crtcs have changed outputs connected to them, these need
7495          * to be part of the prepare_pipes mask. We don't (yet) support global
7496          * modeset across multiple crtcs, so modeset_pipes will only have one
7497          * bit set at most. */
7498         list_for_each_entry(connector, &dev->mode_config.connector_list,
7499                             base.head) {
7500                 if (connector->base.encoder == &connector->new_encoder->base)
7501                         continue;
7502
7503                 if (connector->base.encoder) {
7504                         tmp_crtc = connector->base.encoder->crtc;
7505
7506                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7507                 }
7508
7509                 if (connector->new_encoder)
7510                         *prepare_pipes |=
7511                                 1 << connector->new_encoder->new_crtc->pipe;
7512         }
7513
7514         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7515                             base.head) {
7516                 if (encoder->base.crtc == &encoder->new_crtc->base)
7517                         continue;
7518
7519                 if (encoder->base.crtc) {
7520                         tmp_crtc = encoder->base.crtc;
7521
7522                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7523                 }
7524
7525                 if (encoder->new_crtc)
7526                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7527         }
7528
7529         /* Check for any pipes that will be fully disabled ... */
7530         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7531                             base.head) {
7532                 bool used = false;
7533
7534                 /* Don't try to disable disabled crtcs. */
7535                 if (!intel_crtc->base.enabled)
7536                         continue;
7537
7538                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7539                                     base.head) {
7540                         if (encoder->new_crtc == intel_crtc)
7541                                 used = true;
7542                 }
7543
7544                 if (!used)
7545                         *disable_pipes |= 1 << intel_crtc->pipe;
7546         }
7547
7548
7549         /* set_mode is also used to update properties on life display pipes. */
7550         intel_crtc = to_intel_crtc(crtc);
7551         if (crtc->enabled)
7552                 *prepare_pipes |= 1 << intel_crtc->pipe;
7553
7554         /* We only support modeset on one single crtc, hence we need to do that
7555          * only for the passed in crtc iff we change anything else than just
7556          * disable crtcs.
7557          *
7558          * This is actually not true, to be fully compatible with the old crtc
7559          * helper we automatically disable _any_ output (i.e. doesn't need to be
7560          * connected to the crtc we're modesetting on) if it's disconnected.
7561          * Which is a rather nutty api (since changed the output configuration
7562          * without userspace's explicit request can lead to confusion), but
7563          * alas. Hence we currently need to modeset on all pipes we prepare. */
7564         if (*prepare_pipes)
7565                 *modeset_pipes = *prepare_pipes;
7566
7567         /* ... and mask these out. */
7568         *modeset_pipes &= ~(*disable_pipes);
7569         *prepare_pipes &= ~(*disable_pipes);
7570 }
7571
7572 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7573 {
7574         struct drm_encoder *encoder;
7575         struct drm_device *dev = crtc->dev;
7576
7577         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7578                 if (encoder->crtc == crtc)
7579                         return true;
7580
7581         return false;
7582 }
7583
7584 static void
7585 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7586 {
7587         struct intel_encoder *intel_encoder;
7588         struct intel_crtc *intel_crtc;
7589         struct drm_connector *connector;
7590
7591         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7592                             base.head) {
7593                 if (!intel_encoder->base.crtc)
7594                         continue;
7595
7596                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7597
7598                 if (prepare_pipes & (1 << intel_crtc->pipe))
7599                         intel_encoder->connectors_active = false;
7600         }
7601
7602         intel_modeset_commit_output_state(dev);
7603
7604         /* Update computed state. */
7605         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7606                             base.head) {
7607                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7608         }
7609
7610         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7611                 if (!connector->encoder || !connector->encoder->crtc)
7612                         continue;
7613
7614                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7615
7616                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7617                         struct drm_property *dpms_property =
7618                                 dev->mode_config.dpms_property;
7619
7620                         connector->dpms = DRM_MODE_DPMS_ON;
7621                         drm_connector_property_set_value(connector,
7622                                                          dpms_property,
7623                                                          DRM_MODE_DPMS_ON);
7624
7625                         intel_encoder = to_intel_encoder(connector->encoder);
7626                         intel_encoder->connectors_active = true;
7627                 }
7628         }
7629
7630 }
7631
7632 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7633         list_for_each_entry((intel_crtc), \
7634                             &(dev)->mode_config.crtc_list, \
7635                             base.head) \
7636                 if (mask & (1 <<(intel_crtc)->pipe)) \
7637
7638 void
7639 intel_modeset_check_state(struct drm_device *dev)
7640 {
7641         struct intel_crtc *crtc;
7642         struct intel_encoder *encoder;
7643         struct intel_connector *connector;
7644
7645         list_for_each_entry(connector, &dev->mode_config.connector_list,
7646                             base.head) {
7647                 /* This also checks the encoder/connector hw state with the
7648                  * ->get_hw_state callbacks. */
7649                 intel_connector_check_state(connector);
7650
7651                 WARN(&connector->new_encoder->base != connector->base.encoder,
7652                      "connector's staged encoder doesn't match current encoder\n");
7653         }
7654
7655         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7656                             base.head) {
7657                 bool enabled = false;
7658                 bool active = false;
7659                 enum pipe pipe, tracked_pipe;
7660
7661                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7662                               encoder->base.base.id,
7663                               drm_get_encoder_name(&encoder->base));
7664
7665                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7666                      "encoder's stage crtc doesn't match current crtc\n");
7667                 WARN(encoder->connectors_active && !encoder->base.crtc,
7668                      "encoder's active_connectors set, but no crtc\n");
7669
7670                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7671                                     base.head) {
7672                         if (connector->base.encoder != &encoder->base)
7673                                 continue;
7674                         enabled = true;
7675                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7676                                 active = true;
7677                 }
7678                 WARN(!!encoder->base.crtc != enabled,
7679                      "encoder's enabled state mismatch "
7680                      "(expected %i, found %i)\n",
7681                      !!encoder->base.crtc, enabled);
7682                 WARN(active && !encoder->base.crtc,
7683                      "active encoder with no crtc\n");
7684
7685                 WARN(encoder->connectors_active != active,
7686                      "encoder's computed active state doesn't match tracked active state "
7687                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7688
7689                 active = encoder->get_hw_state(encoder, &pipe);
7690                 WARN(active != encoder->connectors_active,
7691                      "encoder's hw state doesn't match sw tracking "
7692                      "(expected %i, found %i)\n",
7693                      encoder->connectors_active, active);
7694
7695                 if (!encoder->base.crtc)
7696                         continue;
7697
7698                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7699                 WARN(active && pipe != tracked_pipe,
7700                      "active encoder's pipe doesn't match"
7701                      "(expected %i, found %i)\n",
7702                      tracked_pipe, pipe);
7703
7704         }
7705
7706         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7707                             base.head) {
7708                 bool enabled = false;
7709                 bool active = false;
7710
7711                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7712                               crtc->base.base.id);
7713
7714                 WARN(crtc->active && !crtc->base.enabled,
7715                      "active crtc, but not enabled in sw tracking\n");
7716
7717                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7718                                     base.head) {
7719                         if (encoder->base.crtc != &crtc->base)
7720                                 continue;
7721                         enabled = true;
7722                         if (encoder->connectors_active)
7723                                 active = true;
7724                 }
7725                 WARN(active != crtc->active,
7726                      "crtc's computed active state doesn't match tracked active state "
7727                      "(expected %i, found %i)\n", active, crtc->active);
7728                 WARN(enabled != crtc->base.enabled,
7729                      "crtc's computed enabled state doesn't match tracked enabled state "
7730                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7731
7732                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7733         }
7734 }
7735
7736 bool intel_set_mode(struct drm_crtc *crtc,
7737                     struct drm_display_mode *mode,
7738                     int x, int y, struct drm_framebuffer *fb)
7739 {
7740         struct drm_device *dev = crtc->dev;
7741         drm_i915_private_t *dev_priv = dev->dev_private;
7742         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7743         struct intel_crtc *intel_crtc;
7744         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7745         bool ret = true;
7746
7747         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7748                                      &prepare_pipes, &disable_pipes);
7749
7750         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7751                       modeset_pipes, prepare_pipes, disable_pipes);
7752
7753         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7754                 intel_crtc_disable(&intel_crtc->base);
7755
7756         saved_hwmode = crtc->hwmode;
7757         saved_mode = crtc->mode;
7758
7759         /* Hack: Because we don't (yet) support global modeset on multiple
7760          * crtcs, we don't keep track of the new mode for more than one crtc.
7761          * Hence simply check whether any bit is set in modeset_pipes in all the
7762          * pieces of code that are not yet converted to deal with mutliple crtcs
7763          * changing their mode at the same time. */
7764         adjusted_mode = NULL;
7765         if (modeset_pipes) {
7766                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7767                 if (IS_ERR(adjusted_mode)) {
7768                         return false;
7769                 }
7770         }
7771
7772         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7773                 if (intel_crtc->base.enabled)
7774                         dev_priv->display.crtc_disable(&intel_crtc->base);
7775         }
7776
7777         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7778          * to set it here already despite that we pass it down the callchain.
7779          */
7780         if (modeset_pipes)
7781                 crtc->mode = *mode;
7782
7783         /* Only after disabling all output pipelines that will be changed can we
7784          * update the the output configuration. */
7785         intel_modeset_update_state(dev, prepare_pipes);
7786
7787         if (dev_priv->display.modeset_global_resources)
7788                 dev_priv->display.modeset_global_resources(dev);
7789
7790         /* Set up the DPLL and any encoders state that needs to adjust or depend
7791          * on the DPLL.
7792          */
7793         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7794                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7795                                            mode, adjusted_mode,
7796                                            x, y, fb);
7797                 if (!ret)
7798                     goto done;
7799         }
7800
7801         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7802         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7803                 dev_priv->display.crtc_enable(&intel_crtc->base);
7804
7805         if (modeset_pipes) {
7806                 /* Store real post-adjustment hardware mode. */
7807                 crtc->hwmode = *adjusted_mode;
7808
7809                 /* Calculate and store various constants which
7810                  * are later needed by vblank and swap-completion
7811                  * timestamping. They are derived from true hwmode.
7812                  */
7813                 drm_calc_timestamping_constants(crtc);
7814         }
7815
7816         /* FIXME: add subpixel order */
7817 done:
7818         drm_mode_destroy(dev, adjusted_mode);
7819         if (!ret && crtc->enabled) {
7820                 crtc->hwmode = saved_hwmode;
7821                 crtc->mode = saved_mode;
7822         } else {
7823                 intel_modeset_check_state(dev);
7824         }
7825
7826         return ret;
7827 }
7828
7829 #undef for_each_intel_crtc_masked
7830
7831 static void intel_set_config_free(struct intel_set_config *config)
7832 {
7833         if (!config)
7834                 return;
7835
7836         kfree(config->save_connector_encoders);
7837         kfree(config->save_encoder_crtcs);
7838         kfree(config);
7839 }
7840
7841 static int intel_set_config_save_state(struct drm_device *dev,
7842                                        struct intel_set_config *config)
7843 {
7844         struct drm_encoder *encoder;
7845         struct drm_connector *connector;
7846         int count;
7847
7848         config->save_encoder_crtcs =
7849                 kcalloc(dev->mode_config.num_encoder,
7850                         sizeof(struct drm_crtc *), GFP_KERNEL);
7851         if (!config->save_encoder_crtcs)
7852                 return -ENOMEM;
7853
7854         config->save_connector_encoders =
7855                 kcalloc(dev->mode_config.num_connector,
7856                         sizeof(struct drm_encoder *), GFP_KERNEL);
7857         if (!config->save_connector_encoders)
7858                 return -ENOMEM;
7859
7860         /* Copy data. Note that driver private data is not affected.
7861          * Should anything bad happen only the expected state is
7862          * restored, not the drivers personal bookkeeping.
7863          */
7864         count = 0;
7865         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7866                 config->save_encoder_crtcs[count++] = encoder->crtc;
7867         }
7868
7869         count = 0;
7870         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7871                 config->save_connector_encoders[count++] = connector->encoder;
7872         }
7873
7874         return 0;
7875 }
7876
7877 static void intel_set_config_restore_state(struct drm_device *dev,
7878                                            struct intel_set_config *config)
7879 {
7880         struct intel_encoder *encoder;
7881         struct intel_connector *connector;
7882         int count;
7883
7884         count = 0;
7885         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7886                 encoder->new_crtc =
7887                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7888         }
7889
7890         count = 0;
7891         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7892                 connector->new_encoder =
7893                         to_intel_encoder(config->save_connector_encoders[count++]);
7894         }
7895 }
7896
7897 static void
7898 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7899                                       struct intel_set_config *config)
7900 {
7901
7902         /* We should be able to check here if the fb has the same properties
7903          * and then just flip_or_move it */
7904         if (set->crtc->fb != set->fb) {
7905                 /* If we have no fb then treat it as a full mode set */
7906                 if (set->crtc->fb == NULL) {
7907                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7908                         config->mode_changed = true;
7909                 } else if (set->fb == NULL) {
7910                         config->mode_changed = true;
7911                 } else if (set->fb->depth != set->crtc->fb->depth) {
7912                         config->mode_changed = true;
7913                 } else if (set->fb->bits_per_pixel !=
7914                            set->crtc->fb->bits_per_pixel) {
7915                         config->mode_changed = true;
7916                 } else
7917                         config->fb_changed = true;
7918         }
7919
7920         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7921                 config->fb_changed = true;
7922
7923         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7924                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7925                 drm_mode_debug_printmodeline(&set->crtc->mode);
7926                 drm_mode_debug_printmodeline(set->mode);
7927                 config->mode_changed = true;
7928         }
7929 }
7930
7931 static int
7932 intel_modeset_stage_output_state(struct drm_device *dev,
7933                                  struct drm_mode_set *set,
7934                                  struct intel_set_config *config)
7935 {
7936         struct drm_crtc *new_crtc;
7937         struct intel_connector *connector;
7938         struct intel_encoder *encoder;
7939         int count, ro;
7940
7941         /* The upper layers ensure that we either disabl a crtc or have a list
7942          * of connectors. For paranoia, double-check this. */
7943         WARN_ON(!set->fb && (set->num_connectors != 0));
7944         WARN_ON(set->fb && (set->num_connectors == 0));
7945
7946         count = 0;
7947         list_for_each_entry(connector, &dev->mode_config.connector_list,
7948                             base.head) {
7949                 /* Otherwise traverse passed in connector list and get encoders
7950                  * for them. */
7951                 for (ro = 0; ro < set->num_connectors; ro++) {
7952                         if (set->connectors[ro] == &connector->base) {
7953                                 connector->new_encoder = connector->encoder;
7954                                 break;
7955                         }
7956                 }
7957
7958                 /* If we disable the crtc, disable all its connectors. Also, if
7959                  * the connector is on the changing crtc but not on the new
7960                  * connector list, disable it. */
7961                 if ((!set->fb || ro == set->num_connectors) &&
7962                     connector->base.encoder &&
7963                     connector->base.encoder->crtc == set->crtc) {
7964                         connector->new_encoder = NULL;
7965
7966                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7967                                 connector->base.base.id,
7968                                 drm_get_connector_name(&connector->base));
7969                 }
7970
7971
7972                 if (&connector->new_encoder->base != connector->base.encoder) {
7973                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7974                         config->mode_changed = true;
7975                 }
7976
7977                 /* Disable all disconnected encoders. */
7978                 if (connector->base.status == connector_status_disconnected)
7979                         connector->new_encoder = NULL;
7980         }
7981         /* connector->new_encoder is now updated for all connectors. */
7982
7983         /* Update crtc of enabled connectors. */
7984         count = 0;
7985         list_for_each_entry(connector, &dev->mode_config.connector_list,
7986                             base.head) {
7987                 if (!connector->new_encoder)
7988                         continue;
7989
7990                 new_crtc = connector->new_encoder->base.crtc;
7991
7992                 for (ro = 0; ro < set->num_connectors; ro++) {
7993                         if (set->connectors[ro] == &connector->base)
7994                                 new_crtc = set->crtc;
7995                 }
7996
7997                 /* Make sure the new CRTC will work with the encoder */
7998                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7999                                            new_crtc)) {
8000                         return -EINVAL;
8001                 }
8002                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8003
8004                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8005                         connector->base.base.id,
8006                         drm_get_connector_name(&connector->base),
8007                         new_crtc->base.id);
8008         }
8009
8010         /* Check for any encoders that needs to be disabled. */
8011         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8012                             base.head) {
8013                 list_for_each_entry(connector,
8014                                     &dev->mode_config.connector_list,
8015                                     base.head) {
8016                         if (connector->new_encoder == encoder) {
8017                                 WARN_ON(!connector->new_encoder->new_crtc);
8018
8019                                 goto next_encoder;
8020                         }
8021                 }
8022                 encoder->new_crtc = NULL;
8023 next_encoder:
8024                 /* Only now check for crtc changes so we don't miss encoders
8025                  * that will be disabled. */
8026                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8027                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8028                         config->mode_changed = true;
8029                 }
8030         }
8031         /* Now we've also updated encoder->new_crtc for all encoders. */
8032
8033         return 0;
8034 }
8035
8036 static int intel_crtc_set_config(struct drm_mode_set *set)
8037 {
8038         struct drm_device *dev;
8039         struct drm_mode_set save_set;
8040         struct intel_set_config *config;
8041         int ret;
8042
8043         BUG_ON(!set);
8044         BUG_ON(!set->crtc);
8045         BUG_ON(!set->crtc->helper_private);
8046
8047         if (!set->mode)
8048                 set->fb = NULL;
8049
8050         /* The fb helper likes to play gross jokes with ->mode_set_config.
8051          * Unfortunately the crtc helper doesn't do much at all for this case,
8052          * so we have to cope with this madness until the fb helper is fixed up. */
8053         if (set->fb && set->num_connectors == 0)
8054                 return 0;
8055
8056         if (set->fb) {
8057                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8058                                 set->crtc->base.id, set->fb->base.id,
8059                                 (int)set->num_connectors, set->x, set->y);
8060         } else {
8061                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8062         }
8063
8064         dev = set->crtc->dev;
8065
8066         ret = -ENOMEM;
8067         config = kzalloc(sizeof(*config), GFP_KERNEL);
8068         if (!config)
8069                 goto out_config;
8070
8071         ret = intel_set_config_save_state(dev, config);
8072         if (ret)
8073                 goto out_config;
8074
8075         save_set.crtc = set->crtc;
8076         save_set.mode = &set->crtc->mode;
8077         save_set.x = set->crtc->x;
8078         save_set.y = set->crtc->y;
8079         save_set.fb = set->crtc->fb;
8080
8081         /* Compute whether we need a full modeset, only an fb base update or no
8082          * change at all. In the future we might also check whether only the
8083          * mode changed, e.g. for LVDS where we only change the panel fitter in
8084          * such cases. */
8085         intel_set_config_compute_mode_changes(set, config);
8086
8087         ret = intel_modeset_stage_output_state(dev, set, config);
8088         if (ret)
8089                 goto fail;
8090
8091         if (config->mode_changed) {
8092                 if (set->mode) {
8093                         DRM_DEBUG_KMS("attempting to set mode from"
8094                                         " userspace\n");
8095                         drm_mode_debug_printmodeline(set->mode);
8096                 }
8097
8098                 if (!intel_set_mode(set->crtc, set->mode,
8099                                     set->x, set->y, set->fb)) {
8100                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8101                                   set->crtc->base.id);
8102                         ret = -EINVAL;
8103                         goto fail;
8104                 }
8105         } else if (config->fb_changed) {
8106                 ret = intel_pipe_set_base(set->crtc,
8107                                           set->x, set->y, set->fb);
8108         }
8109
8110         intel_set_config_free(config);
8111
8112         return 0;
8113
8114 fail:
8115         intel_set_config_restore_state(dev, config);
8116
8117         /* Try to restore the config */
8118         if (config->mode_changed &&
8119             !intel_set_mode(save_set.crtc, save_set.mode,
8120                             save_set.x, save_set.y, save_set.fb))
8121                 DRM_ERROR("failed to restore config after modeset failure\n");
8122
8123 out_config:
8124         intel_set_config_free(config);
8125         return ret;
8126 }
8127
8128 static const struct drm_crtc_funcs intel_crtc_funcs = {
8129         .cursor_set = intel_crtc_cursor_set,
8130         .cursor_move = intel_crtc_cursor_move,
8131         .gamma_set = intel_crtc_gamma_set,
8132         .set_config = intel_crtc_set_config,
8133         .destroy = intel_crtc_destroy,
8134         .page_flip = intel_crtc_page_flip,
8135 };
8136
8137 static void intel_cpu_pll_init(struct drm_device *dev)
8138 {
8139         if (IS_HASWELL(dev))
8140                 intel_ddi_pll_init(dev);
8141 }
8142
8143 static void intel_pch_pll_init(struct drm_device *dev)
8144 {
8145         drm_i915_private_t *dev_priv = dev->dev_private;
8146         int i;
8147
8148         if (dev_priv->num_pch_pll == 0) {
8149                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8150                 return;
8151         }
8152
8153         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8154                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8155                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8156                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8157         }
8158 }
8159
8160 static void intel_crtc_init(struct drm_device *dev, int pipe)
8161 {
8162         drm_i915_private_t *dev_priv = dev->dev_private;
8163         struct intel_crtc *intel_crtc;
8164         int i;
8165
8166         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8167         if (intel_crtc == NULL)
8168                 return;
8169
8170         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8171
8172         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8173         for (i = 0; i < 256; i++) {
8174                 intel_crtc->lut_r[i] = i;
8175                 intel_crtc->lut_g[i] = i;
8176                 intel_crtc->lut_b[i] = i;
8177         }
8178
8179         /* Swap pipes & planes for FBC on pre-965 */
8180         intel_crtc->pipe = pipe;
8181         intel_crtc->plane = pipe;
8182         intel_crtc->cpu_transcoder = pipe;
8183         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8184                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8185                 intel_crtc->plane = !pipe;
8186         }
8187
8188         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8189                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8190         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8191         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8192
8193         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8194
8195         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8196 }
8197
8198 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8199                                 struct drm_file *file)
8200 {
8201         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8202         struct drm_mode_object *drmmode_obj;
8203         struct intel_crtc *crtc;
8204
8205         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8206                 return -ENODEV;
8207
8208         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8209                         DRM_MODE_OBJECT_CRTC);
8210
8211         if (!drmmode_obj) {
8212                 DRM_ERROR("no such CRTC id\n");
8213                 return -EINVAL;
8214         }
8215
8216         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8217         pipe_from_crtc_id->pipe = crtc->pipe;
8218
8219         return 0;
8220 }
8221
8222 static int intel_encoder_clones(struct intel_encoder *encoder)
8223 {
8224         struct drm_device *dev = encoder->base.dev;
8225         struct intel_encoder *source_encoder;
8226         int index_mask = 0;
8227         int entry = 0;
8228
8229         list_for_each_entry(source_encoder,
8230                             &dev->mode_config.encoder_list, base.head) {
8231
8232                 if (encoder == source_encoder)
8233                         index_mask |= (1 << entry);
8234
8235                 /* Intel hw has only one MUX where enocoders could be cloned. */
8236                 if (encoder->cloneable && source_encoder->cloneable)
8237                         index_mask |= (1 << entry);
8238
8239                 entry++;
8240         }
8241
8242         return index_mask;
8243 }
8244
8245 static bool has_edp_a(struct drm_device *dev)
8246 {
8247         struct drm_i915_private *dev_priv = dev->dev_private;
8248
8249         if (!IS_MOBILE(dev))
8250                 return false;
8251
8252         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8253                 return false;
8254
8255         if (IS_GEN5(dev) &&
8256             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8257                 return false;
8258
8259         return true;
8260 }
8261
8262 static void intel_setup_outputs(struct drm_device *dev)
8263 {
8264         struct drm_i915_private *dev_priv = dev->dev_private;
8265         struct intel_encoder *encoder;
8266         bool dpd_is_edp = false;
8267         bool has_lvds;
8268
8269         has_lvds = intel_lvds_init(dev);
8270         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8271                 /* disable the panel fitter on everything but LVDS */
8272                 I915_WRITE(PFIT_CONTROL, 0);
8273         }
8274
8275         if (!(IS_HASWELL(dev) &&
8276               (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8277                 intel_crt_init(dev);
8278
8279         if (IS_HASWELL(dev)) {
8280                 int found;
8281
8282                 /* Haswell uses DDI functions to detect digital outputs */
8283                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8284                 /* DDI A only supports eDP */
8285                 if (found)
8286                         intel_ddi_init(dev, PORT_A);
8287
8288                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8289                  * register */
8290                 found = I915_READ(SFUSE_STRAP);
8291
8292                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8293                         intel_ddi_init(dev, PORT_B);
8294                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8295                         intel_ddi_init(dev, PORT_C);
8296                 if (found & SFUSE_STRAP_DDID_DETECTED)
8297                         intel_ddi_init(dev, PORT_D);
8298         } else if (HAS_PCH_SPLIT(dev)) {
8299                 int found;
8300                 dpd_is_edp = intel_dpd_is_edp(dev);
8301
8302                 if (has_edp_a(dev))
8303                         intel_dp_init(dev, DP_A, PORT_A);
8304
8305                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8306                         /* PCH SDVOB multiplex with HDMIB */
8307                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8308                         if (!found)
8309                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8310                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8311                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8312                 }
8313
8314                 if (I915_READ(HDMIC) & PORT_DETECTED)
8315                         intel_hdmi_init(dev, HDMIC, PORT_C);
8316
8317                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8318                         intel_hdmi_init(dev, HDMID, PORT_D);
8319
8320                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8321                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8322
8323                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8324                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8325         } else if (IS_VALLEYVIEW(dev)) {
8326                 int found;
8327
8328                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8329                 if (I915_READ(DP_C) & DP_DETECTED)
8330                         intel_dp_init(dev, DP_C, PORT_C);
8331
8332                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8333                         /* SDVOB multiplex with HDMIB */
8334                         found = intel_sdvo_init(dev, SDVOB, true);
8335                         if (!found)
8336                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8337                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8338                                 intel_dp_init(dev, DP_B, PORT_B);
8339                 }
8340
8341                 if (I915_READ(SDVOC) & PORT_DETECTED)
8342                         intel_hdmi_init(dev, SDVOC, PORT_C);
8343
8344         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8345                 bool found = false;
8346
8347                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8348                         DRM_DEBUG_KMS("probing SDVOB\n");
8349                         found = intel_sdvo_init(dev, SDVOB, true);
8350                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8351                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8352                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8353                         }
8354
8355                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8356                                 DRM_DEBUG_KMS("probing DP_B\n");
8357                                 intel_dp_init(dev, DP_B, PORT_B);
8358                         }
8359                 }
8360
8361                 /* Before G4X SDVOC doesn't have its own detect register */
8362
8363                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8364                         DRM_DEBUG_KMS("probing SDVOC\n");
8365                         found = intel_sdvo_init(dev, SDVOC, false);
8366                 }
8367
8368                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8369
8370                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8371                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8372                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8373                         }
8374                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8375                                 DRM_DEBUG_KMS("probing DP_C\n");
8376                                 intel_dp_init(dev, DP_C, PORT_C);
8377                         }
8378                 }
8379
8380                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8381                     (I915_READ(DP_D) & DP_DETECTED)) {
8382                         DRM_DEBUG_KMS("probing DP_D\n");
8383                         intel_dp_init(dev, DP_D, PORT_D);
8384                 }
8385         } else if (IS_GEN2(dev))
8386                 intel_dvo_init(dev);
8387
8388         if (SUPPORTS_TV(dev))
8389                 intel_tv_init(dev);
8390
8391         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8392                 encoder->base.possible_crtcs = encoder->crtc_mask;
8393                 encoder->base.possible_clones =
8394                         intel_encoder_clones(encoder);
8395         }
8396
8397         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8398                 ironlake_init_pch_refclk(dev);
8399
8400         drm_helper_move_panel_connectors_to_head(dev);
8401 }
8402
8403 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8404 {
8405         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8406
8407         drm_framebuffer_cleanup(fb);
8408         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8409
8410         kfree(intel_fb);
8411 }
8412
8413 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8414                                                 struct drm_file *file,
8415                                                 unsigned int *handle)
8416 {
8417         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8418         struct drm_i915_gem_object *obj = intel_fb->obj;
8419
8420         return drm_gem_handle_create(file, &obj->base, handle);
8421 }
8422
8423 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8424         .destroy = intel_user_framebuffer_destroy,
8425         .create_handle = intel_user_framebuffer_create_handle,
8426 };
8427
8428 int intel_framebuffer_init(struct drm_device *dev,
8429                            struct intel_framebuffer *intel_fb,
8430                            struct drm_mode_fb_cmd2 *mode_cmd,
8431                            struct drm_i915_gem_object *obj)
8432 {
8433         int ret;
8434
8435         if (obj->tiling_mode == I915_TILING_Y)
8436                 return -EINVAL;
8437
8438         if (mode_cmd->pitches[0] & 63)
8439                 return -EINVAL;
8440
8441         /* FIXME <= Gen4 stride limits are bit unclear */
8442         if (mode_cmd->pitches[0] > 32768)
8443                 return -EINVAL;
8444
8445         if (obj->tiling_mode != I915_TILING_NONE &&
8446             mode_cmd->pitches[0] != obj->stride)
8447                 return -EINVAL;
8448
8449         /* Reject formats not supported by any plane early. */
8450         switch (mode_cmd->pixel_format) {
8451         case DRM_FORMAT_C8:
8452         case DRM_FORMAT_RGB565:
8453         case DRM_FORMAT_XRGB8888:
8454         case DRM_FORMAT_ARGB8888:
8455                 break;
8456         case DRM_FORMAT_XRGB1555:
8457         case DRM_FORMAT_ARGB1555:
8458                 if (INTEL_INFO(dev)->gen > 3)
8459                         return -EINVAL;
8460                 break;
8461         case DRM_FORMAT_XBGR8888:
8462         case DRM_FORMAT_ABGR8888:
8463         case DRM_FORMAT_XRGB2101010:
8464         case DRM_FORMAT_ARGB2101010:
8465         case DRM_FORMAT_XBGR2101010:
8466         case DRM_FORMAT_ABGR2101010:
8467                 if (INTEL_INFO(dev)->gen < 4)
8468                         return -EINVAL;
8469                 break;
8470         case DRM_FORMAT_YUYV:
8471         case DRM_FORMAT_UYVY:
8472         case DRM_FORMAT_YVYU:
8473         case DRM_FORMAT_VYUY:
8474                 if (INTEL_INFO(dev)->gen < 6)
8475                         return -EINVAL;
8476                 break;
8477         default:
8478                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8479                 return -EINVAL;
8480         }
8481
8482         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8483         if (mode_cmd->offsets[0] != 0)
8484                 return -EINVAL;
8485
8486         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8487         if (ret) {
8488                 DRM_ERROR("framebuffer init failed %d\n", ret);
8489                 return ret;
8490         }
8491
8492         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8493         intel_fb->obj = obj;
8494         return 0;
8495 }
8496
8497 static struct drm_framebuffer *
8498 intel_user_framebuffer_create(struct drm_device *dev,
8499                               struct drm_file *filp,
8500                               struct drm_mode_fb_cmd2 *mode_cmd)
8501 {
8502         struct drm_i915_gem_object *obj;
8503
8504         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8505                                                 mode_cmd->handles[0]));
8506         if (&obj->base == NULL)
8507                 return ERR_PTR(-ENOENT);
8508
8509         return intel_framebuffer_create(dev, mode_cmd, obj);
8510 }
8511
8512 static const struct drm_mode_config_funcs intel_mode_funcs = {
8513         .fb_create = intel_user_framebuffer_create,
8514         .output_poll_changed = intel_fb_output_poll_changed,
8515 };
8516
8517 /* Set up chip specific display functions */
8518 static void intel_init_display(struct drm_device *dev)
8519 {
8520         struct drm_i915_private *dev_priv = dev->dev_private;
8521
8522         /* We always want a DPMS function */
8523         if (IS_HASWELL(dev)) {
8524                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8525                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8526                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8527                 dev_priv->display.off = haswell_crtc_off;
8528                 dev_priv->display.update_plane = ironlake_update_plane;
8529         } else if (HAS_PCH_SPLIT(dev)) {
8530                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8531                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8532                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8533                 dev_priv->display.off = ironlake_crtc_off;
8534                 dev_priv->display.update_plane = ironlake_update_plane;
8535         } else {
8536                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8537                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8538                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8539                 dev_priv->display.off = i9xx_crtc_off;
8540                 dev_priv->display.update_plane = i9xx_update_plane;
8541         }
8542
8543         /* Returns the core display clock speed */
8544         if (IS_VALLEYVIEW(dev))
8545                 dev_priv->display.get_display_clock_speed =
8546                         valleyview_get_display_clock_speed;
8547         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8548                 dev_priv->display.get_display_clock_speed =
8549                         i945_get_display_clock_speed;
8550         else if (IS_I915G(dev))
8551                 dev_priv->display.get_display_clock_speed =
8552                         i915_get_display_clock_speed;
8553         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8554                 dev_priv->display.get_display_clock_speed =
8555                         i9xx_misc_get_display_clock_speed;
8556         else if (IS_I915GM(dev))
8557                 dev_priv->display.get_display_clock_speed =
8558                         i915gm_get_display_clock_speed;
8559         else if (IS_I865G(dev))
8560                 dev_priv->display.get_display_clock_speed =
8561                         i865_get_display_clock_speed;
8562         else if (IS_I85X(dev))
8563                 dev_priv->display.get_display_clock_speed =
8564                         i855_get_display_clock_speed;
8565         else /* 852, 830 */
8566                 dev_priv->display.get_display_clock_speed =
8567                         i830_get_display_clock_speed;
8568
8569         if (HAS_PCH_SPLIT(dev)) {
8570                 if (IS_GEN5(dev)) {
8571                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8572                         dev_priv->display.write_eld = ironlake_write_eld;
8573                 } else if (IS_GEN6(dev)) {
8574                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8575                         dev_priv->display.write_eld = ironlake_write_eld;
8576                 } else if (IS_IVYBRIDGE(dev)) {
8577                         /* FIXME: detect B0+ stepping and use auto training */
8578                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8579                         dev_priv->display.write_eld = ironlake_write_eld;
8580                         dev_priv->display.modeset_global_resources =
8581                                 ivb_modeset_global_resources;
8582                 } else if (IS_HASWELL(dev)) {
8583                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8584                         dev_priv->display.write_eld = haswell_write_eld;
8585                 } else
8586                         dev_priv->display.update_wm = NULL;
8587         } else if (IS_G4X(dev)) {
8588                 dev_priv->display.write_eld = g4x_write_eld;
8589         }
8590
8591         /* Default just returns -ENODEV to indicate unsupported */
8592         dev_priv->display.queue_flip = intel_default_queue_flip;
8593
8594         switch (INTEL_INFO(dev)->gen) {
8595         case 2:
8596                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8597                 break;
8598
8599         case 3:
8600                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8601                 break;
8602
8603         case 4:
8604         case 5:
8605                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8606                 break;
8607
8608         case 6:
8609                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8610                 break;
8611         case 7:
8612                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8613                 break;
8614         }
8615 }
8616
8617 /*
8618  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8619  * resume, or other times.  This quirk makes sure that's the case for
8620  * affected systems.
8621  */
8622 static void quirk_pipea_force(struct drm_device *dev)
8623 {
8624         struct drm_i915_private *dev_priv = dev->dev_private;
8625
8626         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8627         DRM_INFO("applying pipe a force quirk\n");
8628 }
8629
8630 /*
8631  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8632  */
8633 static void quirk_ssc_force_disable(struct drm_device *dev)
8634 {
8635         struct drm_i915_private *dev_priv = dev->dev_private;
8636         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8637         DRM_INFO("applying lvds SSC disable quirk\n");
8638 }
8639
8640 /*
8641  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8642  * brightness value
8643  */
8644 static void quirk_invert_brightness(struct drm_device *dev)
8645 {
8646         struct drm_i915_private *dev_priv = dev->dev_private;
8647         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8648         DRM_INFO("applying inverted panel brightness quirk\n");
8649 }
8650
8651 struct intel_quirk {
8652         int device;
8653         int subsystem_vendor;
8654         int subsystem_device;
8655         void (*hook)(struct drm_device *dev);
8656 };
8657
8658 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8659 struct intel_dmi_quirk {
8660         void (*hook)(struct drm_device *dev);
8661         const struct dmi_system_id (*dmi_id_list)[];
8662 };
8663
8664 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8665 {
8666         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8667         return 1;
8668 }
8669
8670 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8671         {
8672                 .dmi_id_list = &(const struct dmi_system_id[]) {
8673                         {
8674                                 .callback = intel_dmi_reverse_brightness,
8675                                 .ident = "NCR Corporation",
8676                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8677                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8678                                 },
8679                         },
8680                         { }  /* terminating entry */
8681                 },
8682                 .hook = quirk_invert_brightness,
8683         },
8684 };
8685
8686 static struct intel_quirk intel_quirks[] = {
8687         /* HP Mini needs pipe A force quirk (LP: #322104) */
8688         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8689
8690         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8691         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8692
8693         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8694         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8695
8696         /* 830/845 need to leave pipe A & dpll A up */
8697         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8698         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8699
8700         /* Lenovo U160 cannot use SSC on LVDS */
8701         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8702
8703         /* Sony Vaio Y cannot use SSC on LVDS */
8704         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8705
8706         /* Acer Aspire 5734Z must invert backlight brightness */
8707         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8708 };
8709
8710 static void intel_init_quirks(struct drm_device *dev)
8711 {
8712         struct pci_dev *d = dev->pdev;
8713         int i;
8714
8715         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8716                 struct intel_quirk *q = &intel_quirks[i];
8717
8718                 if (d->device == q->device &&
8719                     (d->subsystem_vendor == q->subsystem_vendor ||
8720                      q->subsystem_vendor == PCI_ANY_ID) &&
8721                     (d->subsystem_device == q->subsystem_device ||
8722                      q->subsystem_device == PCI_ANY_ID))
8723                         q->hook(dev);
8724         }
8725         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8726                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8727                         intel_dmi_quirks[i].hook(dev);
8728         }
8729 }
8730
8731 /* Disable the VGA plane that we never use */
8732 static void i915_disable_vga(struct drm_device *dev)
8733 {
8734         struct drm_i915_private *dev_priv = dev->dev_private;
8735         u8 sr1;
8736         u32 vga_reg;
8737
8738         if (HAS_PCH_SPLIT(dev))
8739                 vga_reg = CPU_VGACNTRL;
8740         else
8741                 vga_reg = VGACNTRL;
8742
8743         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8744         outb(SR01, VGA_SR_INDEX);
8745         sr1 = inb(VGA_SR_DATA);
8746         outb(sr1 | 1<<5, VGA_SR_DATA);
8747         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8748         udelay(300);
8749
8750         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8751         POSTING_READ(vga_reg);
8752 }
8753
8754 void intel_modeset_init_hw(struct drm_device *dev)
8755 {
8756         /* We attempt to init the necessary power wells early in the initialization
8757          * time, so the subsystems that expect power to be enabled can work.
8758          */
8759         intel_init_power_wells(dev);
8760
8761         intel_prepare_ddi(dev);
8762
8763         intel_init_clock_gating(dev);
8764
8765         mutex_lock(&dev->struct_mutex);
8766         intel_enable_gt_powersave(dev);
8767         mutex_unlock(&dev->struct_mutex);
8768 }
8769
8770 void intel_modeset_init(struct drm_device *dev)
8771 {
8772         struct drm_i915_private *dev_priv = dev->dev_private;
8773         int i, ret;
8774
8775         drm_mode_config_init(dev);
8776
8777         dev->mode_config.min_width = 0;
8778         dev->mode_config.min_height = 0;
8779
8780         dev->mode_config.preferred_depth = 24;
8781         dev->mode_config.prefer_shadow = 1;
8782
8783         dev->mode_config.funcs = &intel_mode_funcs;
8784
8785         intel_init_quirks(dev);
8786
8787         intel_init_pm(dev);
8788
8789         intel_init_display(dev);
8790
8791         if (IS_GEN2(dev)) {
8792                 dev->mode_config.max_width = 2048;
8793                 dev->mode_config.max_height = 2048;
8794         } else if (IS_GEN3(dev)) {
8795                 dev->mode_config.max_width = 4096;
8796                 dev->mode_config.max_height = 4096;
8797         } else {
8798                 dev->mode_config.max_width = 8192;
8799                 dev->mode_config.max_height = 8192;
8800         }
8801         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8802
8803         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8804                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8805
8806         for (i = 0; i < dev_priv->num_pipe; i++) {
8807                 intel_crtc_init(dev, i);
8808                 ret = intel_plane_init(dev, i);
8809                 if (ret)
8810                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8811         }
8812
8813         intel_cpu_pll_init(dev);
8814         intel_pch_pll_init(dev);
8815
8816         /* Just disable it once at startup */
8817         i915_disable_vga(dev);
8818         intel_setup_outputs(dev);
8819 }
8820
8821 static void
8822 intel_connector_break_all_links(struct intel_connector *connector)
8823 {
8824         connector->base.dpms = DRM_MODE_DPMS_OFF;
8825         connector->base.encoder = NULL;
8826         connector->encoder->connectors_active = false;
8827         connector->encoder->base.crtc = NULL;
8828 }
8829
8830 static void intel_enable_pipe_a(struct drm_device *dev)
8831 {
8832         struct intel_connector *connector;
8833         struct drm_connector *crt = NULL;
8834         struct intel_load_detect_pipe load_detect_temp;
8835
8836         /* We can't just switch on the pipe A, we need to set things up with a
8837          * proper mode and output configuration. As a gross hack, enable pipe A
8838          * by enabling the load detect pipe once. */
8839         list_for_each_entry(connector,
8840                             &dev->mode_config.connector_list,
8841                             base.head) {
8842                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8843                         crt = &connector->base;
8844                         break;
8845                 }
8846         }
8847
8848         if (!crt)
8849                 return;
8850
8851         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8852                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8853
8854
8855 }
8856
8857 static bool
8858 intel_check_plane_mapping(struct intel_crtc *crtc)
8859 {
8860         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8861         u32 reg, val;
8862
8863         if (dev_priv->num_pipe == 1)
8864                 return true;
8865
8866         reg = DSPCNTR(!crtc->plane);
8867         val = I915_READ(reg);
8868
8869         if ((val & DISPLAY_PLANE_ENABLE) &&
8870             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8871                 return false;
8872
8873         return true;
8874 }
8875
8876 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8877 {
8878         struct drm_device *dev = crtc->base.dev;
8879         struct drm_i915_private *dev_priv = dev->dev_private;
8880         u32 reg;
8881
8882         /* Clear any frame start delays used for debugging left by the BIOS */
8883         reg = PIPECONF(crtc->cpu_transcoder);
8884         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8885
8886         /* We need to sanitize the plane -> pipe mapping first because this will
8887          * disable the crtc (and hence change the state) if it is wrong. Note
8888          * that gen4+ has a fixed plane -> pipe mapping.  */
8889         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8890                 struct intel_connector *connector;
8891                 bool plane;
8892
8893                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8894                               crtc->base.base.id);
8895
8896                 /* Pipe has the wrong plane attached and the plane is active.
8897                  * Temporarily change the plane mapping and disable everything
8898                  * ...  */
8899                 plane = crtc->plane;
8900                 crtc->plane = !plane;
8901                 dev_priv->display.crtc_disable(&crtc->base);
8902                 crtc->plane = plane;
8903
8904                 /* ... and break all links. */
8905                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8906                                     base.head) {
8907                         if (connector->encoder->base.crtc != &crtc->base)
8908                                 continue;
8909
8910                         intel_connector_break_all_links(connector);
8911                 }
8912
8913                 WARN_ON(crtc->active);
8914                 crtc->base.enabled = false;
8915         }
8916
8917         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8918             crtc->pipe == PIPE_A && !crtc->active) {
8919                 /* BIOS forgot to enable pipe A, this mostly happens after
8920                  * resume. Force-enable the pipe to fix this, the update_dpms
8921                  * call below we restore the pipe to the right state, but leave
8922                  * the required bits on. */
8923                 intel_enable_pipe_a(dev);
8924         }
8925
8926         /* Adjust the state of the output pipe according to whether we
8927          * have active connectors/encoders. */
8928         intel_crtc_update_dpms(&crtc->base);
8929
8930         if (crtc->active != crtc->base.enabled) {
8931                 struct intel_encoder *encoder;
8932
8933                 /* This can happen either due to bugs in the get_hw_state
8934                  * functions or because the pipe is force-enabled due to the
8935                  * pipe A quirk. */
8936                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8937                               crtc->base.base.id,
8938                               crtc->base.enabled ? "enabled" : "disabled",
8939                               crtc->active ? "enabled" : "disabled");
8940
8941                 crtc->base.enabled = crtc->active;
8942
8943                 /* Because we only establish the connector -> encoder ->
8944                  * crtc links if something is active, this means the
8945                  * crtc is now deactivated. Break the links. connector
8946                  * -> encoder links are only establish when things are
8947                  *  actually up, hence no need to break them. */
8948                 WARN_ON(crtc->active);
8949
8950                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8951                         WARN_ON(encoder->connectors_active);
8952                         encoder->base.crtc = NULL;
8953                 }
8954         }
8955 }
8956
8957 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8958 {
8959         struct intel_connector *connector;
8960         struct drm_device *dev = encoder->base.dev;
8961
8962         /* We need to check both for a crtc link (meaning that the
8963          * encoder is active and trying to read from a pipe) and the
8964          * pipe itself being active. */
8965         bool has_active_crtc = encoder->base.crtc &&
8966                 to_intel_crtc(encoder->base.crtc)->active;
8967
8968         if (encoder->connectors_active && !has_active_crtc) {
8969                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8970                               encoder->base.base.id,
8971                               drm_get_encoder_name(&encoder->base));
8972
8973                 /* Connector is active, but has no active pipe. This is
8974                  * fallout from our resume register restoring. Disable
8975                  * the encoder manually again. */
8976                 if (encoder->base.crtc) {
8977                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8978                                       encoder->base.base.id,
8979                                       drm_get_encoder_name(&encoder->base));
8980                         encoder->disable(encoder);
8981                 }
8982
8983                 /* Inconsistent output/port/pipe state happens presumably due to
8984                  * a bug in one of the get_hw_state functions. Or someplace else
8985                  * in our code, like the register restore mess on resume. Clamp
8986                  * things to off as a safer default. */
8987                 list_for_each_entry(connector,
8988                                     &dev->mode_config.connector_list,
8989                                     base.head) {
8990                         if (connector->encoder != encoder)
8991                                 continue;
8992
8993                         intel_connector_break_all_links(connector);
8994                 }
8995         }
8996         /* Enabled encoders without active connectors will be fixed in
8997          * the crtc fixup. */
8998 }
8999
9000 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9001  * and i915 state tracking structures. */
9002 void intel_modeset_setup_hw_state(struct drm_device *dev)
9003 {
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         enum pipe pipe;
9006         u32 tmp;
9007         struct intel_crtc *crtc;
9008         struct intel_encoder *encoder;
9009         struct intel_connector *connector;
9010
9011         if (IS_HASWELL(dev)) {
9012                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9013
9014                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9015                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9016                         case TRANS_DDI_EDP_INPUT_A_ON:
9017                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9018                                 pipe = PIPE_A;
9019                                 break;
9020                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9021                                 pipe = PIPE_B;
9022                                 break;
9023                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9024                                 pipe = PIPE_C;
9025                                 break;
9026                         }
9027
9028                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9029                         crtc->cpu_transcoder = TRANSCODER_EDP;
9030
9031                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9032                                       pipe_name(pipe));
9033                 }
9034         }
9035
9036         for_each_pipe(pipe) {
9037                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9038
9039                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9040                 if (tmp & PIPECONF_ENABLE)
9041                         crtc->active = true;
9042                 else
9043                         crtc->active = false;
9044
9045                 crtc->base.enabled = crtc->active;
9046
9047                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9048                               crtc->base.base.id,
9049                               crtc->active ? "enabled" : "disabled");
9050         }
9051
9052         if (IS_HASWELL(dev))
9053                 intel_ddi_setup_hw_pll_state(dev);
9054
9055         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056                             base.head) {
9057                 pipe = 0;
9058
9059                 if (encoder->get_hw_state(encoder, &pipe)) {
9060                         encoder->base.crtc =
9061                                 dev_priv->pipe_to_crtc_mapping[pipe];
9062                 } else {
9063                         encoder->base.crtc = NULL;
9064                 }
9065
9066                 encoder->connectors_active = false;
9067                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9068                               encoder->base.base.id,
9069                               drm_get_encoder_name(&encoder->base),
9070                               encoder->base.crtc ? "enabled" : "disabled",
9071                               pipe);
9072         }
9073
9074         list_for_each_entry(connector, &dev->mode_config.connector_list,
9075                             base.head) {
9076                 if (connector->get_hw_state(connector)) {
9077                         connector->base.dpms = DRM_MODE_DPMS_ON;
9078                         connector->encoder->connectors_active = true;
9079                         connector->base.encoder = &connector->encoder->base;
9080                 } else {
9081                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9082                         connector->base.encoder = NULL;
9083                 }
9084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9085                               connector->base.base.id,
9086                               drm_get_connector_name(&connector->base),
9087                               connector->base.encoder ? "enabled" : "disabled");
9088         }
9089
9090         /* HW state is read out, now we need to sanitize this mess. */
9091         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9092                             base.head) {
9093                 intel_sanitize_encoder(encoder);
9094         }
9095
9096         for_each_pipe(pipe) {
9097                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9098                 intel_sanitize_crtc(crtc);
9099         }
9100
9101         intel_modeset_update_staged_output_state(dev);
9102
9103         intel_modeset_check_state(dev);
9104
9105         drm_mode_config_reset(dev);
9106 }
9107
9108 void intel_modeset_gem_init(struct drm_device *dev)
9109 {
9110         intel_modeset_init_hw(dev);
9111
9112         intel_setup_overlay(dev);
9113
9114         intel_modeset_setup_hw_state(dev);
9115 }
9116
9117 void intel_modeset_cleanup(struct drm_device *dev)
9118 {
9119         struct drm_i915_private *dev_priv = dev->dev_private;
9120         struct drm_crtc *crtc;
9121         struct intel_crtc *intel_crtc;
9122
9123         drm_kms_helper_poll_fini(dev);
9124         mutex_lock(&dev->struct_mutex);
9125
9126         intel_unregister_dsm_handler();
9127
9128
9129         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9130                 /* Skip inactive CRTCs */
9131                 if (!crtc->fb)
9132                         continue;
9133
9134                 intel_crtc = to_intel_crtc(crtc);
9135                 intel_increase_pllclock(crtc);
9136         }
9137
9138         intel_disable_fbc(dev);
9139
9140         intel_disable_gt_powersave(dev);
9141
9142         ironlake_teardown_rc6(dev);
9143
9144         if (IS_VALLEYVIEW(dev))
9145                 vlv_init_dpio(dev);
9146
9147         mutex_unlock(&dev->struct_mutex);
9148
9149         /* Disable the irq before mode object teardown, for the irq might
9150          * enqueue unpin/hotplug work. */
9151         drm_irq_uninstall(dev);
9152         cancel_work_sync(&dev_priv->hotplug_work);
9153         cancel_work_sync(&dev_priv->rps.work);
9154
9155         /* flush any delayed tasks or pending work */
9156         flush_scheduled_work();
9157
9158         drm_mode_config_cleanup(dev);
9159 }
9160
9161 /*
9162  * Return which encoder is currently attached for connector.
9163  */
9164 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9165 {
9166         return &intel_attached_encoder(connector)->base;
9167 }
9168
9169 void intel_connector_attach_encoder(struct intel_connector *connector,
9170                                     struct intel_encoder *encoder)
9171 {
9172         connector->encoder = encoder;
9173         drm_mode_connector_attach_encoder(&connector->base,
9174                                           &encoder->base);
9175 }
9176
9177 /*
9178  * set vga decode state - true == enable VGA decode
9179  */
9180 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9181 {
9182         struct drm_i915_private *dev_priv = dev->dev_private;
9183         u16 gmch_ctrl;
9184
9185         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9186         if (state)
9187                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9188         else
9189                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9190         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9191         return 0;
9192 }
9193
9194 #ifdef CONFIG_DEBUG_FS
9195 #include <linux/seq_file.h>
9196
9197 struct intel_display_error_state {
9198         struct intel_cursor_error_state {
9199                 u32 control;
9200                 u32 position;
9201                 u32 base;
9202                 u32 size;
9203         } cursor[I915_MAX_PIPES];
9204
9205         struct intel_pipe_error_state {
9206                 u32 conf;
9207                 u32 source;
9208
9209                 u32 htotal;
9210                 u32 hblank;
9211                 u32 hsync;
9212                 u32 vtotal;
9213                 u32 vblank;
9214                 u32 vsync;
9215         } pipe[I915_MAX_PIPES];
9216
9217         struct intel_plane_error_state {
9218                 u32 control;
9219                 u32 stride;
9220                 u32 size;
9221                 u32 pos;
9222                 u32 addr;
9223                 u32 surface;
9224                 u32 tile_offset;
9225         } plane[I915_MAX_PIPES];
9226 };
9227
9228 struct intel_display_error_state *
9229 intel_display_capture_error_state(struct drm_device *dev)
9230 {
9231         drm_i915_private_t *dev_priv = dev->dev_private;
9232         struct intel_display_error_state *error;
9233         enum transcoder cpu_transcoder;
9234         int i;
9235
9236         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9237         if (error == NULL)
9238                 return NULL;
9239
9240         for_each_pipe(i) {
9241                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9242
9243                 error->cursor[i].control = I915_READ(CURCNTR(i));
9244                 error->cursor[i].position = I915_READ(CURPOS(i));
9245                 error->cursor[i].base = I915_READ(CURBASE(i));
9246
9247                 error->plane[i].control = I915_READ(DSPCNTR(i));
9248                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9249                 error->plane[i].size = I915_READ(DSPSIZE(i));
9250                 error->plane[i].pos = I915_READ(DSPPOS(i));
9251                 error->plane[i].addr = I915_READ(DSPADDR(i));
9252                 if (INTEL_INFO(dev)->gen >= 4) {
9253                         error->plane[i].surface = I915_READ(DSPSURF(i));
9254                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9255                 }
9256
9257                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9258                 error->pipe[i].source = I915_READ(PIPESRC(i));
9259                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9260                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9261                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9262                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9263                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9264                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9265         }
9266
9267         return error;
9268 }
9269
9270 void
9271 intel_display_print_error_state(struct seq_file *m,
9272                                 struct drm_device *dev,
9273                                 struct intel_display_error_state *error)
9274 {
9275         drm_i915_private_t *dev_priv = dev->dev_private;
9276         int i;
9277
9278         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9279         for_each_pipe(i) {
9280                 seq_printf(m, "Pipe [%d]:\n", i);
9281                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9282                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9283                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9284                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9285                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9286                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9287                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9288                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9289
9290                 seq_printf(m, "Plane [%d]:\n", i);
9291                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9292                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9293                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9294                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9295                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9296                 if (INTEL_INFO(dev)->gen >= 4) {
9297                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9298                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9299                 }
9300
9301                 seq_printf(m, "Cursor [%d]:\n", i);
9302                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9303                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9304                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9305         }
9306 }
9307 #endif