Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  *
1433  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434  */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* No really, not for ILK+ */
1441         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445                 assert_panel_unlocked(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val |= DPLL_VCO_ENABLE;
1450
1451         /* We do this three times for luck */
1452         I915_WRITE(reg, val);
1453         POSTING_READ(reg);
1454         udelay(150); /* wait for warmup */
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         udelay(150); /* wait for warmup */
1458         I915_WRITE(reg, val);
1459         POSTING_READ(reg);
1460         udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464  * intel_disable_pll - disable a PLL
1465  * @dev_priv: i915 private structure
1466  * @pipe: pipe PLL to disable
1467  *
1468  * Disable the PLL for @pipe, making sure the pipe is off first.
1469  *
1470  * Note!  This is for pre-ILK only.
1471  */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* Don't disable pipe A or pipe A PLLs if needed */
1478         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479                 return;
1480
1481         /* Make sure the pipe isn't still relying on us */
1482         assert_pipe_disabled(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val &= ~DPLL_VCO_ENABLE;
1487         I915_WRITE(reg, val);
1488         POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495         unsigned long flags;
1496
1497         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499                                 100)) {
1500                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501                 goto out_unlock;
1502         }
1503
1504         I915_WRITE(SBI_ADDR,
1505                         (reg << 16));
1506         I915_WRITE(SBI_DATA,
1507                         value);
1508         I915_WRITE(SBI_CTL_STAT,
1509                         SBI_BUSY |
1510                         SBI_CTL_OP_CRWR);
1511
1512         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513                                 100)) {
1514                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515                 goto out_unlock;
1516         }
1517
1518 out_unlock:
1519         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525         unsigned long flags;
1526         u32 value = 0;
1527
1528         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530                                 100)) {
1531                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532                 goto out_unlock;
1533         }
1534
1535         I915_WRITE(SBI_ADDR,
1536                         (reg << 16));
1537         I915_WRITE(SBI_CTL_STAT,
1538                         SBI_BUSY |
1539                         SBI_CTL_OP_CRRD);
1540
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544                 goto out_unlock;
1545         }
1546
1547         value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551         return value;
1552 }
1553
1554 /**
1555  * intel_enable_pch_pll - enable PCH PLL
1556  * @dev_priv: i915 private structure
1557  * @pipe: pipe PLL to enable
1558  *
1559  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560  * drives the transcoder clock.
1561  */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565         struct intel_pch_pll *pll;
1566         int reg;
1567         u32 val;
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(dev_priv->info->gen < 5);
1571         pll = intel_crtc->pch_pll;
1572         if (pll == NULL)
1573                 return;
1574
1575         if (WARN_ON(pll->refcount == 0))
1576                 return;
1577
1578         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579                       pll->pll_reg, pll->active, pll->on,
1580                       intel_crtc->base.base.id);
1581
1582         /* PCH refclock must be enabled first */
1583         assert_pch_refclk_enabled(dev_priv);
1584
1585         if (pll->active++ && pll->on) {
1586                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587                 return;
1588         }
1589
1590         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592         reg = pll->pll_reg;
1593         val = I915_READ(reg);
1594         val |= DPLL_VCO_ENABLE;
1595         I915_WRITE(reg, val);
1596         POSTING_READ(reg);
1597         udelay(200);
1598
1599         pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606         int reg;
1607         u32 val;
1608
1609         /* PCH only available on ILK+ */
1610         BUG_ON(dev_priv->info->gen < 5);
1611         if (pll == NULL)
1612                return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         if (WARN_ON(pll->active == 0)) {
1622                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623                 return;
1624         }
1625
1626         if (--pll->active) {
1627                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628                 return;
1629         }
1630
1631         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633         /* Make sure transcoder isn't still depending on us */
1634         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636         reg = pll->pll_reg;
1637         val = I915_READ(reg);
1638         val &= ~DPLL_VCO_ENABLE;
1639         I915_WRITE(reg, val);
1640         POSTING_READ(reg);
1641         udelay(200);
1642
1643         pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647                                     enum pipe pipe)
1648 {
1649         int reg;
1650         u32 val, pipeconf_val;
1651         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653         /* PCH only available on ILK+ */
1654         BUG_ON(dev_priv->info->gen < 5);
1655
1656         /* Make sure PCH DPLL is enabled */
1657         assert_pch_pll_enabled(dev_priv,
1658                                to_intel_crtc(crtc)->pch_pll,
1659                                to_intel_crtc(crtc));
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667                 return;
1668         }
1669         reg = TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv->dev)) {
1674                 /*
1675                  * make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg.
1677                  */
1678                 val &= ~PIPE_BPC_MASK;
1679                 val |= pipeconf_val & PIPE_BPC_MASK;
1680         }
1681
1682         val &= ~TRANS_INTERLACE_MASK;
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684                 if (HAS_PCH_IBX(dev_priv->dev) &&
1685                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686                         val |= TRANS_LEGACY_INTERLACED_ILK;
1687                 else
1688                         val |= TRANS_INTERLACED;
1689         else
1690                 val |= TRANS_PROGRESSIVE;
1691
1692         I915_WRITE(reg, val | TRANS_ENABLE);
1693         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698                                      enum pipe pipe)
1699 {
1700         int reg;
1701         u32 val;
1702
1703         /* FDI relies on the transcoder */
1704         assert_fdi_tx_disabled(dev_priv, pipe);
1705         assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707         /* Ports must be off as well */
1708         assert_pch_ports_disabled(dev_priv, pipe);
1709
1710         reg = TRANSCONF(pipe);
1711         val = I915_READ(reg);
1712         val &= ~TRANS_ENABLE;
1713         I915_WRITE(reg, val);
1714         /* wait for PCH transcoder off, transcoder state */
1715         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720  * intel_enable_pipe - enable a pipe, asserting requirements
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe to enable
1723  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724  *
1725  * Enable @pipe, making sure that various hardware specific requirements
1726  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727  *
1728  * @pipe should be %PIPE_A or %PIPE_B.
1729  *
1730  * Will wait until the pipe is actually running (i.e. first vblank) before
1731  * returning.
1732  */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734                               bool pch_port)
1735 {
1736         int reg;
1737         u32 val;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751                 }
1752                 /* FIXME: assert CPU port conditions for SNB+ */
1753         }
1754
1755         reg = PIPECONF(pipe);
1756         val = I915_READ(reg);
1757         if (val & PIPECONF_ENABLE)
1758                 return;
1759
1760         I915_WRITE(reg, val | PIPECONF_ENABLE);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_pipe - disable a pipe, asserting requirements
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe to disable
1768  *
1769  * Disable @pipe, making sure that various hardware specific requirements
1770  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771  *
1772  * @pipe should be %PIPE_A or %PIPE_B.
1773  *
1774  * Will wait until the pipe has shut down before returning.
1775  */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777                                enum pipe pipe)
1778 {
1779         int reg;
1780         u32 val;
1781
1782         /*
1783          * Make sure planes won't keep trying to pump pixels to us,
1784          * or we might hang the display.
1785          */
1786         assert_planes_disabled(dev_priv, pipe);
1787
1788         /* Don't disable pipe A or pipe A PLLs if needed */
1789         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790                 return;
1791
1792         reg = PIPECONF(pipe);
1793         val = I915_READ(reg);
1794         if ((val & PIPECONF_ENABLE) == 0)
1795                 return;
1796
1797         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802  * Plane regs are double buffered, going from enabled->disabled needs a
1803  * trigger in order to latch.  The display address reg provides this.
1804  */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806                                       enum plane plane)
1807 {
1808         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813  * intel_enable_plane - enable a display plane on a given pipe
1814  * @dev_priv: i915 private structure
1815  * @plane: plane to enable
1816  * @pipe: pipe being fed
1817  *
1818  * Enable @plane on @pipe, making sure that @pipe is running first.
1819  */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane, enum pipe pipe)
1822 {
1823         int reg;
1824         u32 val;
1825
1826         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827         assert_pipe_enabled(dev_priv, pipe);
1828
1829         reg = DSPCNTR(plane);
1830         val = I915_READ(reg);
1831         if (val & DISPLAY_PLANE_ENABLE)
1832                 return;
1833
1834         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835         intel_flush_display_plane(dev_priv, plane);
1836         intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840  * intel_disable_plane - disable a display plane
1841  * @dev_priv: i915 private structure
1842  * @plane: plane to disable
1843  * @pipe: pipe consuming the data
1844  *
1845  * Disable @plane; should be an independent operation.
1846  */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848                                 enum plane plane, enum pipe pipe)
1849 {
1850         int reg;
1851         u32 val;
1852
1853         reg = DSPCNTR(plane);
1854         val = I915_READ(reg);
1855         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856                 return;
1857
1858         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859         intel_flush_display_plane(dev_priv, plane);
1860         intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864                            enum pipe pipe, int reg, u32 port_sel)
1865 {
1866         u32 val = I915_READ(reg);
1867         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869                 I915_WRITE(reg, val & ~DP_PORT_EN);
1870         }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874                              enum pipe pipe, int reg)
1875 {
1876         u32 val = I915_READ(reg);
1877         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879                               reg, pipe);
1880                 I915_WRITE(reg, val & ~PORT_ENABLE);
1881         }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886                                     enum pipe pipe)
1887 {
1888         u32 reg, val;
1889
1890         val = I915_READ(PCH_PP_CONTROL);
1891         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897         reg = PCH_ADPA;
1898         val = I915_READ(reg);
1899         if (adpa_pipe_enabled(dev_priv, pipe, val))
1900                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902         reg = PCH_LVDS;
1903         val = I915_READ(reg);
1904         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907                 POSTING_READ(reg);
1908                 udelay(100);
1909         }
1910
1911         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913         disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918                            struct drm_i915_gem_object *obj,
1919                            struct intel_ring_buffer *pipelined)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         u32 alignment;
1923         int ret;
1924
1925         switch (obj->tiling_mode) {
1926         case I915_TILING_NONE:
1927                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928                         alignment = 128 * 1024;
1929                 else if (INTEL_INFO(dev)->gen >= 4)
1930                         alignment = 4 * 1024;
1931                 else
1932                         alignment = 64 * 1024;
1933                 break;
1934         case I915_TILING_X:
1935                 /* pin() will align the object as required by fence */
1936                 alignment = 0;
1937                 break;
1938         case I915_TILING_Y:
1939                 /* FIXME: Is this true? */
1940                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941                 return -EINVAL;
1942         default:
1943                 BUG();
1944         }
1945
1946         dev_priv->mm.interruptible = false;
1947         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948         if (ret)
1949                 goto err_interruptible;
1950
1951         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952          * fence, whereas 965+ only requires a fence if using
1953          * framebuffer compression.  For simplicity, we always install
1954          * a fence as the cost is not that onerous.
1955          */
1956         ret = i915_gem_object_get_fence(obj);
1957         if (ret)
1958                 goto err_unpin;
1959
1960         i915_gem_object_pin_fence(obj);
1961
1962         dev_priv->mm.interruptible = true;
1963         return 0;
1964
1965 err_unpin:
1966         i915_gem_object_unpin(obj);
1967 err_interruptible:
1968         dev_priv->mm.interruptible = true;
1969         return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974         i915_gem_object_unpin_fence(obj);
1975         i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979  * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981                                                         unsigned int bpp,
1982                                                         unsigned int pitch)
1983 {
1984         int tile_rows, tiles;
1985
1986         tile_rows = *y / 8;
1987         *y %= 8;
1988         tiles = *x / (512/bpp);
1989         *x %= 512/bpp;
1990
1991         return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->bits_per_pixel) {
2024         case 8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case 16:
2028                 if (fb->depth == 15)
2029                         dspcntr |= DISPPLANE_15_16BPP;
2030                 else
2031                         dspcntr |= DISPPLANE_16BPP;
2032                 break;
2033         case 24:
2034         case 32:
2035                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036                 break;
2037         default:
2038                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039                 return -EINVAL;
2040         }
2041         if (INTEL_INFO(dev)->gen >= 4) {
2042                 if (obj->tiling_mode != I915_TILING_NONE)
2043                         dspcntr |= DISPPLANE_TILED;
2044                 else
2045                         dspcntr &= ~DISPPLANE_TILED;
2046         }
2047
2048         I915_WRITE(reg, dspcntr);
2049
2050         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052         if (INTEL_INFO(dev)->gen >= 4) {
2053                 intel_crtc->dspaddr_offset =
2054                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055                                                            fb->bits_per_pixel / 8,
2056                                                            fb->pitches[0]);
2057                 linear_offset -= intel_crtc->dspaddr_offset;
2058         } else {
2059                 intel_crtc->dspaddr_offset = linear_offset;
2060         }
2061
2062         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065         if (INTEL_INFO(dev)->gen >= 4) {
2066                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072         POSTING_READ(reg);
2073
2074         return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078                                  struct drm_framebuffer *fb, int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long linear_offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093         case 2:
2094                 break;
2095         default:
2096                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097                 return -EINVAL;
2098         }
2099
2100         intel_fb = to_intel_framebuffer(fb);
2101         obj = intel_fb->obj;
2102
2103         reg = DSPCNTR(plane);
2104         dspcntr = I915_READ(reg);
2105         /* Mask out pixel format bits in case we change it */
2106         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107         switch (fb->bits_per_pixel) {
2108         case 8:
2109                 dspcntr |= DISPPLANE_8BPP;
2110                 break;
2111         case 16:
2112                 if (fb->depth != 16)
2113                         return -EINVAL;
2114
2115                 dspcntr |= DISPPLANE_16BPP;
2116                 break;
2117         case 24:
2118         case 32:
2119                 if (fb->depth == 24)
2120                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121                 else if (fb->depth == 30)
2122                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123                 else
2124                         return -EINVAL;
2125                 break;
2126         default:
2127                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128                 return -EINVAL;
2129         }
2130
2131         if (obj->tiling_mode != I915_TILING_NONE)
2132                 dspcntr |= DISPPLANE_TILED;
2133         else
2134                 dspcntr &= ~DISPPLANE_TILED;
2135
2136         /* must disable */
2137         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139         I915_WRITE(reg, dspcntr);
2140
2141         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142         intel_crtc->dspaddr_offset =
2143                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144                                                    fb->bits_per_pixel / 8,
2145                                                    fb->pitches[0]);
2146         linear_offset -= intel_crtc->dspaddr_offset;
2147
2148         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151         I915_MODIFY_DISPBASE(DSPSURF(plane),
2152                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2153         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154         I915_WRITE(DSPLINOFF(plane), linear_offset);
2155         POSTING_READ(reg);
2156
2157         return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163                            int x, int y, enum mode_set_atomic state)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         if (dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170         intel_increase_pllclock(crtc);
2171
2172         return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180         bool was_interruptible = dev_priv->mm.interruptible;
2181         int ret;
2182
2183         wait_event(dev_priv->pending_flip_queue,
2184                    atomic_read(&dev_priv->mm.wedged) ||
2185                    atomic_read(&obj->pending_flip) == 0);
2186
2187         /* Big Hammer, we also need to ensure that any pending
2188          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189          * current scanout is retired before unpinning the old
2190          * framebuffer.
2191          *
2192          * This should only fail upon a hung GPU, in which case we
2193          * can safely continue.
2194          */
2195         dev_priv->mm.interruptible = false;
2196         ret = i915_gem_object_finish_gpu(obj);
2197         dev_priv->mm.interruptible = was_interruptible;
2198
2199         return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *old_fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_master_private *master_priv;
2209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210         int ret;
2211
2212         /* no fb bound */
2213         if (!crtc->fb) {
2214                 DRM_ERROR("No FB bound\n");
2215                 return 0;
2216         }
2217
2218         if(intel_crtc->plane > dev_priv->num_pipe) {
2219                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220                                 intel_crtc->plane,
2221                                 dev_priv->num_pipe);
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 DRM_ERROR("pin & fence failed\n");
2232                 return ret;
2233         }
2234
2235         if (old_fb)
2236                 intel_finish_fb(old_fb);
2237
2238         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239         if (ret) {
2240                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241                 mutex_unlock(&dev->struct_mutex);
2242                 DRM_ERROR("failed to update base address\n");
2243                 return ret;
2244         }
2245
2246         if (old_fb) {
2247                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249         }
2250
2251         intel_update_fbc(dev);
2252         mutex_unlock(&dev->struct_mutex);
2253
2254         if (!dev->primary->master)
2255                 return 0;
2256
2257         master_priv = dev->primary->master->driver_priv;
2258         if (!master_priv->sarea_priv)
2259                 return 0;
2260
2261         if (intel_crtc->pipe) {
2262                 master_priv->sarea_priv->pipeB_x = x;
2263                 master_priv->sarea_priv->pipeB_y = y;
2264         } else {
2265                 master_priv->sarea_priv->pipeA_x = x;
2266                 master_priv->sarea_priv->pipeA_y = y;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274         struct drm_device *dev = crtc->dev;
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         u32 dpa_ctl;
2277
2278         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279         dpa_ctl = I915_READ(DP_A);
2280         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282         if (clock < 200000) {
2283                 u32 temp;
2284                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285                 /* workaround for 160Mhz:
2286                    1) program 0x4600c bits 15:0 = 0x8124
2287                    2) program 0x46010 bit 0 = 1
2288                    3) program 0x46034 bit 24 = 1
2289                    4) program 0x64000 bit 14 = 1
2290                    */
2291                 temp = I915_READ(0x4600c);
2292                 temp &= 0xffff0000;
2293                 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295                 temp = I915_READ(0x46010);
2296                 I915_WRITE(0x46010, temp | 1);
2297
2298                 temp = I915_READ(0x46034);
2299                 I915_WRITE(0x46034, temp | (1 << 24));
2300         } else {
2301                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302         }
2303         I915_WRITE(DP_A, dpa_ctl);
2304
2305         POSTING_READ(DP_A);
2306         udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311         struct drm_device *dev = crtc->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314         int pipe = intel_crtc->pipe;
2315         u32 reg, temp;
2316
2317         /* enable normal train */
2318         reg = FDI_TX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         if (IS_IVYBRIDGE(dev)) {
2321                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323         } else {
2324                 temp &= ~FDI_LINK_TRAIN_NONE;
2325                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326         }
2327         I915_WRITE(reg, temp);
2328
2329         reg = FDI_RX_CTL(pipe);
2330         temp = I915_READ(reg);
2331         if (HAS_PCH_CPT(dev)) {
2332                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334         } else {
2335                 temp &= ~FDI_LINK_TRAIN_NONE;
2336                 temp |= FDI_LINK_TRAIN_NONE;
2337         }
2338         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340         /* wait one idle pattern time */
2341         POSTING_READ(reg);
2342         udelay(1000);
2343
2344         /* IVB wants error correction enabled */
2345         if (IS_IVYBRIDGE(dev))
2346                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347                            FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355         flags |= FDI_PHASE_SYNC_OVR(pipe);
2356         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357         flags |= FDI_PHASE_SYNC_EN(pipe);
2358         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359         POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365         struct drm_device *dev = crtc->dev;
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368         int pipe = intel_crtc->pipe;
2369         int plane = intel_crtc->plane;
2370         u32 reg, temp, tries;
2371
2372         /* FDI needs bits from pipe & plane first */
2373         assert_pipe_enabled(dev_priv, pipe);
2374         assert_plane_enabled(dev_priv, plane);
2375
2376         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377            for train result */
2378         reg = FDI_RX_IMR(pipe);
2379         temp = I915_READ(reg);
2380         temp &= ~FDI_RX_SYMBOL_LOCK;
2381         temp &= ~FDI_RX_BIT_LOCK;
2382         I915_WRITE(reg, temp);
2383         I915_READ(reg);
2384         udelay(150);
2385
2386         /* enable CPU FDI TX and PCH FDI RX */
2387         reg = FDI_TX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~(7 << 19);
2390         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395         reg = FDI_RX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_LINK_TRAIN_NONE;
2398         temp |= FDI_LINK_TRAIN_PATTERN_1;
2399         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401         POSTING_READ(reg);
2402         udelay(150);
2403
2404         /* Ironlake workaround, enable clock pointer after FDI enable*/
2405         if (HAS_PCH_IBX(dev)) {
2406                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408                            FDI_RX_PHASE_SYNC_POINTER_EN);
2409         }
2410
2411         reg = FDI_RX_IIR(pipe);
2412         for (tries = 0; tries < 5; tries++) {
2413                 temp = I915_READ(reg);
2414                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416                 if ((temp & FDI_RX_BIT_LOCK)) {
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419                         break;
2420                 }
2421         }
2422         if (tries == 5)
2423                 DRM_ERROR("FDI train 1 fail!\n");
2424
2425         /* Train 2 */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_LINK_TRAIN_NONE;
2429         temp |= FDI_LINK_TRAIN_PATTERN_2;
2430         I915_WRITE(reg, temp);
2431
2432         reg = FDI_RX_CTL(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_LINK_TRAIN_NONE;
2435         temp |= FDI_LINK_TRAIN_PATTERN_2;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         reg = FDI_RX_IIR(pipe);
2442         for (tries = 0; tries < 5; tries++) {
2443                 temp = I915_READ(reg);
2444                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446                 if (temp & FDI_RX_SYMBOL_LOCK) {
2447                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2449                         break;
2450                 }
2451         }
2452         if (tries == 5)
2453                 DRM_ERROR("FDI train 2 fail!\n");
2454
2455         DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469         struct drm_device *dev = crtc->dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472         int pipe = intel_crtc->pipe;
2473         u32 reg, temp, i, retry;
2474
2475         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476            for train result */
2477         reg = FDI_RX_IMR(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_RX_SYMBOL_LOCK;
2480         temp &= ~FDI_RX_BIT_LOCK;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494         /* SNB-B */
2495         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         if (HAS_PCH_CPT(dev))
2513                 cpt_phase_pointer_enable(dev, pipe);
2514
2515         for (i = 0; i < 4; i++) {
2516                 reg = FDI_TX_CTL(pipe);
2517                 temp = I915_READ(reg);
2518                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519                 temp |= snb_b_fdi_train_param[i];
2520                 I915_WRITE(reg, temp);
2521
2522                 POSTING_READ(reg);
2523                 udelay(500);
2524
2525                 for (retry = 0; retry < 5; retry++) {
2526                         reg = FDI_RX_IIR(pipe);
2527                         temp = I915_READ(reg);
2528                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529                         if (temp & FDI_RX_BIT_LOCK) {
2530                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532                                 break;
2533                         }
2534                         udelay(50);
2535                 }
2536                 if (retry < 5)
2537                         break;
2538         }
2539         if (i == 4)
2540                 DRM_ERROR("FDI train 1 fail!\n");
2541
2542         /* Train 2 */
2543         reg = FDI_TX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_LINK_TRAIN_NONE;
2546         temp |= FDI_LINK_TRAIN_PATTERN_2;
2547         if (IS_GEN6(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549                 /* SNB-B */
2550                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         }
2552         I915_WRITE(reg, temp);
2553
2554         reg = FDI_RX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         if (HAS_PCH_CPT(dev)) {
2557                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559         } else {
2560                 temp &= ~FDI_LINK_TRAIN_NONE;
2561                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         }
2563         I915_WRITE(reg, temp);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         for (i = 0; i < 4; i++) {
2569                 reg = FDI_TX_CTL(pipe);
2570                 temp = I915_READ(reg);
2571                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572                 temp |= snb_b_fdi_train_param[i];
2573                 I915_WRITE(reg, temp);
2574
2575                 POSTING_READ(reg);
2576                 udelay(500);
2577
2578                 for (retry = 0; retry < 5; retry++) {
2579                         reg = FDI_RX_IIR(pipe);
2580                         temp = I915_READ(reg);
2581                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582                         if (temp & FDI_RX_SYMBOL_LOCK) {
2583                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585                                 break;
2586                         }
2587                         udelay(50);
2588                 }
2589                 if (retry < 5)
2590                         break;
2591         }
2592         if (i == 4)
2593                 DRM_ERROR("FDI train 2 fail!\n");
2594
2595         DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601         struct drm_device *dev = crtc->dev;
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604         int pipe = intel_crtc->pipe;
2605         u32 reg, temp, i;
2606
2607         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608            for train result */
2609         reg = FDI_RX_IMR(pipe);
2610         temp = I915_READ(reg);
2611         temp &= ~FDI_RX_SYMBOL_LOCK;
2612         temp &= ~FDI_RX_BIT_LOCK;
2613         I915_WRITE(reg, temp);
2614
2615         POSTING_READ(reg);
2616         udelay(150);
2617
2618         /* enable CPU FDI TX and PCH FDI RX */
2619         reg = FDI_TX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~(7 << 19);
2622         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627         temp |= FDI_COMPOSITE_SYNC;
2628         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630         reg = FDI_RX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~FDI_LINK_TRAIN_AUTO;
2633         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635         temp |= FDI_COMPOSITE_SYNC;
2636         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         if (HAS_PCH_CPT(dev))
2642                 cpt_phase_pointer_enable(dev, pipe);
2643
2644         for (i = 0; i < 4; i++) {
2645                 reg = FDI_TX_CTL(pipe);
2646                 temp = I915_READ(reg);
2647                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648                 temp |= snb_b_fdi_train_param[i];
2649                 I915_WRITE(reg, temp);
2650
2651                 POSTING_READ(reg);
2652                 udelay(500);
2653
2654                 reg = FDI_RX_IIR(pipe);
2655                 temp = I915_READ(reg);
2656                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658                 if (temp & FDI_RX_BIT_LOCK ||
2659                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                         break;
2663                 }
2664         }
2665         if (i == 4)
2666                 DRM_ERROR("FDI train 1 fail!\n");
2667
2668         /* Train 2 */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675         I915_WRITE(reg, temp);
2676
2677         reg = FDI_RX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681         I915_WRITE(reg, temp);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_SYMBOL_LOCK) {
2701                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2703                         break;
2704                 }
2705         }
2706         if (i == 4)
2707                 DRM_ERROR("FDI train 2 fail!\n");
2708
2709         DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2713 {
2714         struct drm_device *dev = intel_crtc->base.dev;
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         int pipe = intel_crtc->pipe;
2717         u32 reg, temp;
2718
2719         /* Write the TU size bits so error detection works */
2720         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2722
2723         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~((0x7 << 19) | (0x7 << 16));
2727         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731         POSTING_READ(reg);
2732         udelay(200);
2733
2734         /* Switch from Rawclk to PCDclk */
2735         temp = I915_READ(reg);
2736         I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738         POSTING_READ(reg);
2739         udelay(200);
2740
2741         /* On Haswell, the PLL configuration for ports and pipes is handled
2742          * separately, as part of DDI setup */
2743         if (!IS_HASWELL(dev)) {
2744                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745                 reg = FDI_TX_CTL(pipe);
2746                 temp = I915_READ(reg);
2747                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749
2750                         POSTING_READ(reg);
2751                         udelay(100);
2752                 }
2753         }
2754 }
2755
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         int pipe = intel_crtc->pipe;
2761         u32 reg, temp;
2762
2763         /* Switch from PCDclk to Rawclk */
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768         /* Disable CPU FDI TX PLL */
2769         reg = FDI_TX_CTL(pipe);
2770         temp = I915_READ(reg);
2771         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773         POSTING_READ(reg);
2774         udelay(100);
2775
2776         reg = FDI_RX_CTL(pipe);
2777         temp = I915_READ(reg);
2778         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780         /* Wait for the clocks to turn off. */
2781         POSTING_READ(reg);
2782         udelay(100);
2783 }
2784
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786 {
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794         POSTING_READ(SOUTH_CHICKEN1);
2795 }
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         int pipe = intel_crtc->pipe;
2802         u32 reg, temp;
2803
2804         /* disable CPU FDI tx and PCH FDI rx */
2805         reg = FDI_TX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808         POSTING_READ(reg);
2809
2810         reg = FDI_RX_CTL(pipe);
2811         temp = I915_READ(reg);
2812         temp &= ~(0x7 << 16);
2813         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816         POSTING_READ(reg);
2817         udelay(100);
2818
2819         /* Ironlake workaround, disable clock pointer after downing FDI */
2820         if (HAS_PCH_IBX(dev)) {
2821                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823                            I915_READ(FDI_RX_CHICKEN(pipe) &
2824                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825         } else if (HAS_PCH_CPT(dev)) {
2826                 cpt_phase_pointer_disable(dev, pipe);
2827         }
2828
2829         /* still set train pattern 1 */
2830         reg = FDI_TX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~FDI_LINK_TRAIN_NONE;
2833         temp |= FDI_LINK_TRAIN_PATTERN_1;
2834         I915_WRITE(reg, temp);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         if (HAS_PCH_CPT(dev)) {
2839                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841         } else {
2842                 temp &= ~FDI_LINK_TRAIN_NONE;
2843                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844         }
2845         /* BPC in FDI rx is consistent with that in PIPECONF */
2846         temp &= ~(0x07 << 16);
2847         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848         I915_WRITE(reg, temp);
2849
2850         POSTING_READ(reg);
2851         udelay(100);
2852 }
2853
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->dev;
2857
2858         if (crtc->fb == NULL)
2859                 return;
2860
2861         mutex_lock(&dev->struct_mutex);
2862         intel_finish_fb(crtc->fb);
2863         mutex_unlock(&dev->struct_mutex);
2864 }
2865
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 {
2868         struct drm_device *dev = crtc->dev;
2869         struct intel_encoder *intel_encoder;
2870
2871         /*
2872          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873          * must be driven by its own crtc; no sharing is possible.
2874          */
2875         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2876
2877                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878                  * CPU handles all others */
2879                 if (IS_HASWELL(dev)) {
2880                         /* It is still unclear how this will work on PPT, so throw up a warning */
2881                         WARN_ON(!HAS_PCH_LPT(dev));
2882
2883                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885                                 return true;
2886                         } else {
2887                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888                                               intel_encoder->type);
2889                                 return false;
2890                         }
2891                 }
2892
2893                 switch (intel_encoder->type) {
2894                 case INTEL_OUTPUT_EDP:
2895                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2896                                 return false;
2897                         continue;
2898                 }
2899         }
2900
2901         return true;
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907         struct drm_device *dev = crtc->dev;
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910         u32 temp;
2911
2912         /* It is necessary to ungate the pixclk gate prior to programming
2913          * the divisors, and gate it back when it is done.
2914          */
2915         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917         /* Disable SSCCTL */
2918         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920                                         SBI_SSCCTL_DISABLE);
2921
2922         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923         if (crtc->mode.clock == 20000) {
2924                 auxdiv = 1;
2925                 divsel = 0x41;
2926                 phaseinc = 0x20;
2927         } else {
2928                 /* The iCLK virtual clock root frequency is in MHz,
2929                  * but the crtc->mode.clock in in KHz. To get the divisors,
2930                  * it is necessary to divide one by another, so we
2931                  * convert the virtual clock precision to KHz here for higher
2932                  * precision.
2933                  */
2934                 u32 iclk_virtual_root_freq = 172800 * 1000;
2935                 u32 iclk_pi_range = 64;
2936                 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939                 msb_divisor_value = desired_divisor / iclk_pi_range;
2940                 pi_value = desired_divisor % iclk_pi_range;
2941
2942                 auxdiv = 0;
2943                 divsel = msb_divisor_value - 2;
2944                 phaseinc = pi_value;
2945         }
2946
2947         /* This should not happen with any sane values */
2948         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954                         crtc->mode.clock,
2955                         auxdiv,
2956                         divsel,
2957                         phasedir,
2958                         phaseinc);
2959
2960         /* Program SSCDIVINTPHASE6 */
2961         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969         intel_sbi_write(dev_priv,
2970                         SBI_SSCDIVINTPHASE6,
2971                         temp);
2972
2973         /* Program SSCAUXDIV */
2974         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977         intel_sbi_write(dev_priv,
2978                         SBI_SSCAUXDIV6,
2979                         temp);
2980
2981
2982         /* Enable modulator and associated divider */
2983         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984         temp &= ~SBI_SSCCTL_DISABLE;
2985         intel_sbi_write(dev_priv,
2986                         SBI_SSCCTL6,
2987                         temp);
2988
2989         /* Wait for initialization time */
2990         udelay(24);
2991
2992         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993 }
2994
2995 /*
2996  * Enable PCH resources required for PCH ports:
2997  *   - PCH PLLs
2998  *   - FDI training & RX/TX
2999  *   - update transcoder timings
3000  *   - DP transcoding bits
3001  *   - transcoder
3002  */
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3004 {
3005         struct drm_device *dev = crtc->dev;
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008         int pipe = intel_crtc->pipe;
3009         u32 reg, temp;
3010
3011         assert_transcoder_disabled(dev_priv, pipe);
3012
3013         /* For PCH output, training FDI link */
3014         dev_priv->display.fdi_link_train(crtc);
3015
3016         intel_enable_pch_pll(intel_crtc);
3017
3018         if (HAS_PCH_LPT(dev)) {
3019                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020                 lpt_program_iclkip(crtc);
3021         } else if (HAS_PCH_CPT(dev)) {
3022                 u32 sel;
3023
3024                 temp = I915_READ(PCH_DPLL_SEL);
3025                 switch (pipe) {
3026                 default:
3027                 case 0:
3028                         temp |= TRANSA_DPLL_ENABLE;
3029                         sel = TRANSA_DPLLB_SEL;
3030                         break;
3031                 case 1:
3032                         temp |= TRANSB_DPLL_ENABLE;
3033                         sel = TRANSB_DPLLB_SEL;
3034                         break;
3035                 case 2:
3036                         temp |= TRANSC_DPLL_ENABLE;
3037                         sel = TRANSC_DPLLB_SEL;
3038                         break;
3039                 }
3040                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041                         temp |= sel;
3042                 else
3043                         temp &= ~sel;
3044                 I915_WRITE(PCH_DPLL_SEL, temp);
3045         }
3046
3047         /* set transcoder timing, panel must allow it */
3048         assert_panel_unlocked(dev_priv, pipe);
3049         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3052
3053         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3056         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3057
3058         if (!IS_HASWELL(dev))
3059                 intel_fdi_normal_train(crtc);
3060
3061         /* For PCH DP, enable TRANS_DP_CTL */
3062         if (HAS_PCH_CPT(dev) &&
3063             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066                 reg = TRANS_DP_CTL(pipe);
3067                 temp = I915_READ(reg);
3068                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069                           TRANS_DP_SYNC_MASK |
3070                           TRANS_DP_BPC_MASK);
3071                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072                          TRANS_DP_ENH_FRAMING);
3073                 temp |= bpc << 9; /* same format but at 11:9 */
3074
3075                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3079
3080                 switch (intel_trans_dp_port_sel(crtc)) {
3081                 case PCH_DP_B:
3082                         temp |= TRANS_DP_PORT_SEL_B;
3083                         break;
3084                 case PCH_DP_C:
3085                         temp |= TRANS_DP_PORT_SEL_C;
3086                         break;
3087                 case PCH_DP_D:
3088                         temp |= TRANS_DP_PORT_SEL_D;
3089                         break;
3090                 default:
3091                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092                         temp |= TRANS_DP_PORT_SEL_B;
3093                         break;
3094                 }
3095
3096                 I915_WRITE(reg, temp);
3097         }
3098
3099         intel_enable_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103 {
3104         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106         if (pll == NULL)
3107                 return;
3108
3109         if (pll->refcount == 0) {
3110                 WARN(1, "bad PCH PLL refcount\n");
3111                 return;
3112         }
3113
3114         --pll->refcount;
3115         intel_crtc->pch_pll = NULL;
3116 }
3117
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119 {
3120         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121         struct intel_pch_pll *pll;
3122         int i;
3123
3124         pll = intel_crtc->pch_pll;
3125         if (pll) {
3126                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127                               intel_crtc->base.base.id, pll->pll_reg);
3128                 goto prepare;
3129         }
3130
3131         if (HAS_PCH_IBX(dev_priv->dev)) {
3132                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133                 i = intel_crtc->pipe;
3134                 pll = &dev_priv->pch_plls[i];
3135
3136                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137                               intel_crtc->base.base.id, pll->pll_reg);
3138
3139                 goto found;
3140         }
3141
3142         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143                 pll = &dev_priv->pch_plls[i];
3144
3145                 /* Only want to check enabled timings first */
3146                 if (pll->refcount == 0)
3147                         continue;
3148
3149                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150                     fp == I915_READ(pll->fp0_reg)) {
3151                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152                                       intel_crtc->base.base.id,
3153                                       pll->pll_reg, pll->refcount, pll->active);
3154
3155                         goto found;
3156                 }
3157         }
3158
3159         /* Ok no matching timings, maybe there's a free one? */
3160         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161                 pll = &dev_priv->pch_plls[i];
3162                 if (pll->refcount == 0) {
3163                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164                                       intel_crtc->base.base.id, pll->pll_reg);
3165                         goto found;
3166                 }
3167         }
3168
3169         return NULL;
3170
3171 found:
3172         intel_crtc->pch_pll = pll;
3173         pll->refcount++;
3174         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3177
3178         /* Wait for the clocks to stabilize before rewriting the regs */
3179         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180         POSTING_READ(pll->pll_reg);
3181         udelay(150);
3182
3183         I915_WRITE(pll->fp0_reg, fp);
3184         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3185         pll->on = false;
3186         return pll;
3187 }
3188
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193         u32 temp;
3194
3195         temp = I915_READ(dslreg);
3196         udelay(500);
3197         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198                 /* Without this, mode sets may fail silently on FDI */
3199                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200                 udelay(250);
3201                 I915_WRITE(tc2reg, 0);
3202                 if (wait_for(I915_READ(dslreg) != temp, 5))
3203                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204         }
3205 }
3206
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208 {
3209         struct drm_device *dev = crtc->dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212         struct intel_encoder *encoder;
3213         int pipe = intel_crtc->pipe;
3214         int plane = intel_crtc->plane;
3215         u32 temp;
3216         bool is_pch_port;
3217
3218         /* XXX: For compatability with the crtc helper code, call the encoder's
3219          * enable function unconditionally for now. */
3220         if (intel_crtc->active)
3221                 goto encoders;
3222
3223         intel_crtc->active = true;
3224         intel_update_watermarks(dev);
3225
3226         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227                 temp = I915_READ(PCH_LVDS);
3228                 if ((temp & LVDS_PORT_EN) == 0)
3229                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230         }
3231
3232         is_pch_port = intel_crtc_driving_pch(crtc);
3233
3234         if (is_pch_port)
3235                 ironlake_fdi_pll_enable(intel_crtc);
3236         else
3237                 ironlake_fdi_disable(crtc);
3238
3239         /* Enable panel fitting for LVDS */
3240         if (dev_priv->pch_pf_size &&
3241             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3242                 /* Force use of hard-coded filter coefficients
3243                  * as some pre-programmed values are broken,
3244                  * e.g. x201.
3245                  */
3246                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3247                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3248                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3249         }
3250
3251         /*
3252          * On ILK+ LUT must be loaded before the pipe is running but with
3253          * clocks enabled
3254          */
3255         intel_crtc_load_lut(crtc);
3256
3257         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258         intel_enable_plane(dev_priv, plane, pipe);
3259
3260         if (is_pch_port)
3261                 ironlake_pch_enable(crtc);
3262
3263         mutex_lock(&dev->struct_mutex);
3264         intel_update_fbc(dev);
3265         mutex_unlock(&dev->struct_mutex);
3266
3267         intel_crtc_update_cursor(crtc, true);
3268
3269 encoders:
3270         for_each_encoder_on_crtc(dev, crtc, encoder)
3271                 encoder->enable(encoder);
3272
3273         if (HAS_PCH_CPT(dev))
3274                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3275 }
3276
3277 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282         struct intel_encoder *encoder;
3283         int pipe = intel_crtc->pipe;
3284         int plane = intel_crtc->plane;
3285         u32 reg, temp;
3286
3287         /* XXX: For compatability with the crtc helper code, call the encoder's
3288          * disable function unconditionally for now. */
3289         for_each_encoder_on_crtc(dev, crtc, encoder)
3290                 encoder->disable(encoder);
3291
3292         if (!intel_crtc->active)
3293                 return;
3294
3295         intel_crtc_wait_for_pending_flips(crtc);
3296         drm_vblank_off(dev, pipe);
3297         intel_crtc_update_cursor(crtc, false);
3298
3299         intel_disable_plane(dev_priv, plane, pipe);
3300
3301         if (dev_priv->cfb_plane == plane)
3302                 intel_disable_fbc(dev);
3303
3304         intel_disable_pipe(dev_priv, pipe);
3305
3306         /* Disable PF */
3307         I915_WRITE(PF_CTL(pipe), 0);
3308         I915_WRITE(PF_WIN_SZ(pipe), 0);
3309
3310         ironlake_fdi_disable(crtc);
3311
3312         /* This is a horrible layering violation; we should be doing this in
3313          * the connector/encoder ->prepare instead, but we don't always have
3314          * enough information there about the config to know whether it will
3315          * actually be necessary or just cause undesired flicker.
3316          */
3317         intel_disable_pch_ports(dev_priv, pipe);
3318
3319         intel_disable_transcoder(dev_priv, pipe);
3320
3321         if (HAS_PCH_CPT(dev)) {
3322                 /* disable TRANS_DP_CTL */
3323                 reg = TRANS_DP_CTL(pipe);
3324                 temp = I915_READ(reg);
3325                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3326                 temp |= TRANS_DP_PORT_SEL_NONE;
3327                 I915_WRITE(reg, temp);
3328
3329                 /* disable DPLL_SEL */
3330                 temp = I915_READ(PCH_DPLL_SEL);
3331                 switch (pipe) {
3332                 case 0:
3333                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3334                         break;
3335                 case 1:
3336                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3337                         break;
3338                 case 2:
3339                         /* C shares PLL A or B */
3340                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3341                         break;
3342                 default:
3343                         BUG(); /* wtf */
3344                 }
3345                 I915_WRITE(PCH_DPLL_SEL, temp);
3346         }
3347
3348         /* disable PCH DPLL */
3349         intel_disable_pch_pll(intel_crtc);
3350
3351         ironlake_fdi_pll_disable(intel_crtc);
3352
3353         intel_crtc->active = false;
3354         intel_update_watermarks(dev);
3355
3356         mutex_lock(&dev->struct_mutex);
3357         intel_update_fbc(dev);
3358         mutex_unlock(&dev->struct_mutex);
3359 }
3360
3361 static void ironlake_crtc_off(struct drm_crtc *crtc)
3362 {
3363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364         intel_put_pch_pll(intel_crtc);
3365 }
3366
3367 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3368 {
3369         if (!enable && intel_crtc->overlay) {
3370                 struct drm_device *dev = intel_crtc->base.dev;
3371                 struct drm_i915_private *dev_priv = dev->dev_private;
3372
3373                 mutex_lock(&dev->struct_mutex);
3374                 dev_priv->mm.interruptible = false;
3375                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3376                 dev_priv->mm.interruptible = true;
3377                 mutex_unlock(&dev->struct_mutex);
3378         }
3379
3380         /* Let userspace switch the overlay on again. In most cases userspace
3381          * has to recompute where to put it anyway.
3382          */
3383 }
3384
3385 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3386 {
3387         struct drm_device *dev = crtc->dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390         struct intel_encoder *encoder;
3391         int pipe = intel_crtc->pipe;
3392         int plane = intel_crtc->plane;
3393
3394         /* XXX: For compatability with the crtc helper code, call the encoder's
3395          * enable function unconditionally for now. */
3396         if (intel_crtc->active)
3397                 goto encoders;
3398
3399         intel_crtc->active = true;
3400         intel_update_watermarks(dev);
3401
3402         intel_enable_pll(dev_priv, pipe);
3403         intel_enable_pipe(dev_priv, pipe, false);
3404         intel_enable_plane(dev_priv, plane, pipe);
3405
3406         intel_crtc_load_lut(crtc);
3407         intel_update_fbc(dev);
3408
3409         /* Give the overlay scaler a chance to enable if it's on this pipe */
3410         intel_crtc_dpms_overlay(intel_crtc, true);
3411         intel_crtc_update_cursor(crtc, true);
3412
3413 encoders:
3414         for_each_encoder_on_crtc(dev, crtc, encoder)
3415                 encoder->enable(encoder);
3416 }
3417
3418 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3419 {
3420         struct drm_device *dev = crtc->dev;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3423         struct intel_encoder *encoder;
3424         int pipe = intel_crtc->pipe;
3425         int plane = intel_crtc->plane;
3426
3427         /* XXX: For compatability with the crtc helper code, call the encoder's
3428          * disable function unconditionally for now. */
3429         for_each_encoder_on_crtc(dev, crtc, encoder)
3430                 encoder->disable(encoder);
3431
3432         if (!intel_crtc->active)
3433                 return;
3434
3435         /* Give the overlay scaler a chance to disable if it's on this pipe */
3436         intel_crtc_wait_for_pending_flips(crtc);
3437         drm_vblank_off(dev, pipe);
3438         intel_crtc_dpms_overlay(intel_crtc, false);
3439         intel_crtc_update_cursor(crtc, false);
3440
3441         if (dev_priv->cfb_plane == plane)
3442                 intel_disable_fbc(dev);
3443
3444         intel_disable_plane(dev_priv, plane, pipe);
3445         intel_disable_pipe(dev_priv, pipe);
3446         intel_disable_pll(dev_priv, pipe);
3447
3448         intel_crtc->active = false;
3449         intel_update_fbc(dev);
3450         intel_update_watermarks(dev);
3451 }
3452
3453 static void i9xx_crtc_off(struct drm_crtc *crtc)
3454 {
3455 }
3456
3457 /**
3458  * Sets the power management mode of the pipe and plane.
3459  */
3460 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3461 {
3462         struct drm_device *dev = crtc->dev;
3463         struct drm_i915_private *dev_priv = dev->dev_private;
3464         struct drm_i915_master_private *master_priv;
3465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3466         struct intel_encoder *intel_encoder;
3467         int pipe = intel_crtc->pipe;
3468         bool enabled, enable = false;
3469         int mode;
3470
3471         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3472                 enable |= intel_encoder->connectors_active;
3473
3474         mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
3475
3476         if (intel_crtc->dpms_mode == mode)
3477                 return;
3478
3479         intel_crtc->dpms_mode = mode;
3480
3481         if (enable)
3482                 dev_priv->display.crtc_enable(crtc);
3483         else
3484                 dev_priv->display.crtc_disable(crtc);
3485
3486         if (!dev->primary->master)
3487                 return;
3488
3489         master_priv = dev->primary->master->driver_priv;
3490         if (!master_priv->sarea_priv)
3491                 return;
3492
3493         enabled = crtc->enabled && enable;
3494
3495         switch (pipe) {
3496         case 0:
3497                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3499                 break;
3500         case 1:
3501                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3503                 break;
3504         default:
3505                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3506                 break;
3507         }
3508 }
3509
3510 static void intel_crtc_disable(struct drm_crtc *crtc)
3511 {
3512         struct drm_device *dev = crtc->dev;
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514
3515         /* crtc->disable is only called when we have no encoders, hence this
3516          * will disable the pipe. */
3517         intel_crtc_update_dpms(crtc);
3518         dev_priv->display.off(crtc);
3519
3520         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3522
3523         if (crtc->fb) {
3524                 mutex_lock(&dev->struct_mutex);
3525                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3526                 mutex_unlock(&dev->struct_mutex);
3527         }
3528 }
3529
3530 void intel_encoder_noop(struct drm_encoder *encoder)
3531 {
3532 }
3533
3534 void intel_encoder_disable(struct drm_encoder *encoder)
3535 {
3536         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3537
3538         intel_encoder->disable(intel_encoder);
3539 }
3540
3541 void intel_encoder_destroy(struct drm_encoder *encoder)
3542 {
3543         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3544
3545         drm_encoder_cleanup(encoder);
3546         kfree(intel_encoder);
3547 }
3548
3549 /* Simple dpms helper for encodres with just one connector, no cloning and only
3550  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3551  * state of the entire output pipe. */
3552 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3553 {
3554         if (mode == DRM_MODE_DPMS_ON) {
3555                 encoder->connectors_active = true;
3556
3557                 intel_crtc_update_dpms(encoder->base.crtc);
3558         } else {
3559                 encoder->connectors_active = false;
3560
3561                 intel_crtc_update_dpms(encoder->base.crtc);
3562         }
3563 }
3564
3565 /* Even simpler default implementation, if there's really no special case to
3566  * consider. */
3567 void intel_connector_dpms(struct drm_connector *connector, int mode)
3568 {
3569         struct intel_encoder *encoder = intel_attached_encoder(connector);
3570
3571         /* All the simple cases only support two dpms states. */
3572         if (mode != DRM_MODE_DPMS_ON)
3573                 mode = DRM_MODE_DPMS_OFF;
3574
3575         if (mode == connector->dpms)
3576                 return;
3577
3578         connector->dpms = mode;
3579
3580         /* Only need to change hw state when actually enabled */
3581         if (encoder->base.crtc)
3582                 intel_encoder_dpms(encoder, mode);
3583         else
3584                 encoder->connectors_active = false;
3585 }
3586
3587 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3588                                   const struct drm_display_mode *mode,
3589                                   struct drm_display_mode *adjusted_mode)
3590 {
3591         struct drm_device *dev = crtc->dev;
3592
3593         if (HAS_PCH_SPLIT(dev)) {
3594                 /* FDI link clock is fixed at 2.7G */
3595                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3596                         return false;
3597         }
3598
3599         /* All interlaced capable intel hw wants timings in frames. Note though
3600          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3601          * timings, so we need to be careful not to clobber these.*/
3602         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3603                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3604
3605         return true;
3606 }
3607
3608 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3609 {
3610         return 400000; /* FIXME */
3611 }
3612
3613 static int i945_get_display_clock_speed(struct drm_device *dev)
3614 {
3615         return 400000;
3616 }
3617
3618 static int i915_get_display_clock_speed(struct drm_device *dev)
3619 {
3620         return 333000;
3621 }
3622
3623 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3624 {
3625         return 200000;
3626 }
3627
3628 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3629 {
3630         u16 gcfgc = 0;
3631
3632         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3633
3634         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3635                 return 133000;
3636         else {
3637                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3638                 case GC_DISPLAY_CLOCK_333_MHZ:
3639                         return 333000;
3640                 default:
3641                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3642                         return 190000;
3643                 }
3644         }
3645 }
3646
3647 static int i865_get_display_clock_speed(struct drm_device *dev)
3648 {
3649         return 266000;
3650 }
3651
3652 static int i855_get_display_clock_speed(struct drm_device *dev)
3653 {
3654         u16 hpllcc = 0;
3655         /* Assume that the hardware is in the high speed state.  This
3656          * should be the default.
3657          */
3658         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3659         case GC_CLOCK_133_200:
3660         case GC_CLOCK_100_200:
3661                 return 200000;
3662         case GC_CLOCK_166_250:
3663                 return 250000;
3664         case GC_CLOCK_100_133:
3665                 return 133000;
3666         }
3667
3668         /* Shouldn't happen */
3669         return 0;
3670 }
3671
3672 static int i830_get_display_clock_speed(struct drm_device *dev)
3673 {
3674         return 133000;
3675 }
3676
3677 struct fdi_m_n {
3678         u32        tu;
3679         u32        gmch_m;
3680         u32        gmch_n;
3681         u32        link_m;
3682         u32        link_n;
3683 };
3684
3685 static void
3686 fdi_reduce_ratio(u32 *num, u32 *den)
3687 {
3688         while (*num > 0xffffff || *den > 0xffffff) {
3689                 *num >>= 1;
3690                 *den >>= 1;
3691         }
3692 }
3693
3694 static void
3695 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3696                      int link_clock, struct fdi_m_n *m_n)
3697 {
3698         m_n->tu = 64; /* default size */
3699
3700         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3701         m_n->gmch_m = bits_per_pixel * pixel_clock;
3702         m_n->gmch_n = link_clock * nlanes * 8;
3703         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3704
3705         m_n->link_m = pixel_clock;
3706         m_n->link_n = link_clock;
3707         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3708 }
3709
3710 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3711 {
3712         if (i915_panel_use_ssc >= 0)
3713                 return i915_panel_use_ssc != 0;
3714         return dev_priv->lvds_use_ssc
3715                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3716 }
3717
3718 /**
3719  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3720  * @crtc: CRTC structure
3721  * @mode: requested mode
3722  *
3723  * A pipe may be connected to one or more outputs.  Based on the depth of the
3724  * attached framebuffer, choose a good color depth to use on the pipe.
3725  *
3726  * If possible, match the pipe depth to the fb depth.  In some cases, this
3727  * isn't ideal, because the connected output supports a lesser or restricted
3728  * set of depths.  Resolve that here:
3729  *    LVDS typically supports only 6bpc, so clamp down in that case
3730  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3731  *    Displays may support a restricted set as well, check EDID and clamp as
3732  *      appropriate.
3733  *    DP may want to dither down to 6bpc to fit larger modes
3734  *
3735  * RETURNS:
3736  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3737  * true if they don't match).
3738  */
3739 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3740                                          unsigned int *pipe_bpp,
3741                                          struct drm_display_mode *mode)
3742 {
3743         struct drm_device *dev = crtc->dev;
3744         struct drm_i915_private *dev_priv = dev->dev_private;
3745         struct drm_connector *connector;
3746         struct intel_encoder *intel_encoder;
3747         unsigned int display_bpc = UINT_MAX, bpc;
3748
3749         /* Walk the encoders & connectors on this crtc, get min bpc */
3750         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3751
3752                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3753                         unsigned int lvds_bpc;
3754
3755                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3756                             LVDS_A3_POWER_UP)
3757                                 lvds_bpc = 8;
3758                         else
3759                                 lvds_bpc = 6;
3760
3761                         if (lvds_bpc < display_bpc) {
3762                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3763                                 display_bpc = lvds_bpc;
3764                         }
3765                         continue;
3766                 }
3767
3768                 /* Not one of the known troublemakers, check the EDID */
3769                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3770                                     head) {
3771                         if (connector->encoder != &intel_encoder->base)
3772                                 continue;
3773
3774                         /* Don't use an invalid EDID bpc value */
3775                         if (connector->display_info.bpc &&
3776                             connector->display_info.bpc < display_bpc) {
3777                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3778                                 display_bpc = connector->display_info.bpc;
3779                         }
3780                 }
3781
3782                 /*
3783                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3784                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3785                  */
3786                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3787                         if (display_bpc > 8 && display_bpc < 12) {
3788                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3789                                 display_bpc = 12;
3790                         } else {
3791                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3792                                 display_bpc = 8;
3793                         }
3794                 }
3795         }
3796
3797         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3798                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3799                 display_bpc = 6;
3800         }
3801
3802         /*
3803          * We could just drive the pipe at the highest bpc all the time and
3804          * enable dithering as needed, but that costs bandwidth.  So choose
3805          * the minimum value that expresses the full color range of the fb but
3806          * also stays within the max display bpc discovered above.
3807          */
3808
3809         switch (crtc->fb->depth) {
3810         case 8:
3811                 bpc = 8; /* since we go through a colormap */
3812                 break;
3813         case 15:
3814         case 16:
3815                 bpc = 6; /* min is 18bpp */
3816                 break;
3817         case 24:
3818                 bpc = 8;
3819                 break;
3820         case 30:
3821                 bpc = 10;
3822                 break;
3823         case 48:
3824                 bpc = 12;
3825                 break;
3826         default:
3827                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3828                 bpc = min((unsigned int)8, display_bpc);
3829                 break;
3830         }
3831
3832         display_bpc = min(display_bpc, bpc);
3833
3834         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3835                       bpc, display_bpc);
3836
3837         *pipe_bpp = display_bpc * 3;
3838
3839         return display_bpc != bpc;
3840 }
3841
3842 static int vlv_get_refclk(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846         int refclk = 27000; /* for DP & HDMI */
3847
3848         return 100000; /* only one validated so far */
3849
3850         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3851                 refclk = 96000;
3852         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3853                 if (intel_panel_use_ssc(dev_priv))
3854                         refclk = 100000;
3855                 else
3856                         refclk = 96000;
3857         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3858                 refclk = 100000;
3859         }
3860
3861         return refclk;
3862 }
3863
3864 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3865 {
3866         struct drm_device *dev = crtc->dev;
3867         struct drm_i915_private *dev_priv = dev->dev_private;
3868         int refclk;
3869
3870         if (IS_VALLEYVIEW(dev)) {
3871                 refclk = vlv_get_refclk(crtc);
3872         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3873             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3874                 refclk = dev_priv->lvds_ssc_freq * 1000;
3875                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3876                               refclk / 1000);
3877         } else if (!IS_GEN2(dev)) {
3878                 refclk = 96000;
3879         } else {
3880                 refclk = 48000;
3881         }
3882
3883         return refclk;
3884 }
3885
3886 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3887                                       intel_clock_t *clock)
3888 {
3889         /* SDVO TV has fixed PLL values depend on its clock range,
3890            this mirrors vbios setting. */
3891         if (adjusted_mode->clock >= 100000
3892             && adjusted_mode->clock < 140500) {
3893                 clock->p1 = 2;
3894                 clock->p2 = 10;
3895                 clock->n = 3;
3896                 clock->m1 = 16;
3897                 clock->m2 = 8;
3898         } else if (adjusted_mode->clock >= 140500
3899                    && adjusted_mode->clock <= 200000) {
3900                 clock->p1 = 1;
3901                 clock->p2 = 10;
3902                 clock->n = 6;
3903                 clock->m1 = 12;
3904                 clock->m2 = 8;
3905         }
3906 }
3907
3908 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3909                                      intel_clock_t *clock,
3910                                      intel_clock_t *reduced_clock)
3911 {
3912         struct drm_device *dev = crtc->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3915         int pipe = intel_crtc->pipe;
3916         u32 fp, fp2 = 0;
3917
3918         if (IS_PINEVIEW(dev)) {
3919                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3920                 if (reduced_clock)
3921                         fp2 = (1 << reduced_clock->n) << 16 |
3922                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3923         } else {
3924                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3925                 if (reduced_clock)
3926                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3927                                 reduced_clock->m2;
3928         }
3929
3930         I915_WRITE(FP0(pipe), fp);
3931
3932         intel_crtc->lowfreq_avail = false;
3933         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3934             reduced_clock && i915_powersave) {
3935                 I915_WRITE(FP1(pipe), fp2);
3936                 intel_crtc->lowfreq_avail = true;
3937         } else {
3938                 I915_WRITE(FP1(pipe), fp);
3939         }
3940 }
3941
3942 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3943                               struct drm_display_mode *adjusted_mode)
3944 {
3945         struct drm_device *dev = crtc->dev;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948         int pipe = intel_crtc->pipe;
3949         u32 temp;
3950
3951         temp = I915_READ(LVDS);
3952         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3953         if (pipe == 1) {
3954                 temp |= LVDS_PIPEB_SELECT;
3955         } else {
3956                 temp &= ~LVDS_PIPEB_SELECT;
3957         }
3958         /* set the corresponsding LVDS_BORDER bit */
3959         temp |= dev_priv->lvds_border_bits;
3960         /* Set the B0-B3 data pairs corresponding to whether we're going to
3961          * set the DPLLs for dual-channel mode or not.
3962          */
3963         if (clock->p2 == 7)
3964                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3965         else
3966                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3967
3968         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3969          * appropriately here, but we need to look more thoroughly into how
3970          * panels behave in the two modes.
3971          */
3972         /* set the dithering flag on LVDS as needed */
3973         if (INTEL_INFO(dev)->gen >= 4) {
3974                 if (dev_priv->lvds_dither)
3975                         temp |= LVDS_ENABLE_DITHER;
3976                 else
3977                         temp &= ~LVDS_ENABLE_DITHER;
3978         }
3979         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3980         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3981                 temp |= LVDS_HSYNC_POLARITY;
3982         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3983                 temp |= LVDS_VSYNC_POLARITY;
3984         I915_WRITE(LVDS, temp);
3985 }
3986
3987 static void vlv_update_pll(struct drm_crtc *crtc,
3988                            struct drm_display_mode *mode,
3989                            struct drm_display_mode *adjusted_mode,
3990                            intel_clock_t *clock, intel_clock_t *reduced_clock,
3991                            int refclk, int num_connectors)
3992 {
3993         struct drm_device *dev = crtc->dev;
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996         int pipe = intel_crtc->pipe;
3997         u32 dpll, mdiv, pdiv;
3998         u32 bestn, bestm1, bestm2, bestp1, bestp2;
3999         bool is_hdmi;
4000
4001         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4002
4003         bestn = clock->n;
4004         bestm1 = clock->m1;
4005         bestm2 = clock->m2;
4006         bestp1 = clock->p1;
4007         bestp2 = clock->p2;
4008
4009         /* Enable DPIO clock input */
4010         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4011                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4012         I915_WRITE(DPLL(pipe), dpll);
4013         POSTING_READ(DPLL(pipe));
4014
4015         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4016         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4017         mdiv |= ((bestn << DPIO_N_SHIFT));
4018         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4019         mdiv |= (1 << DPIO_K_SHIFT);
4020         mdiv |= DPIO_ENABLE_CALIBRATION;
4021         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4022
4023         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4024
4025         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4026                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4027                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4028         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4029
4030         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4031
4032         dpll |= DPLL_VCO_ENABLE;
4033         I915_WRITE(DPLL(pipe), dpll);
4034         POSTING_READ(DPLL(pipe));
4035         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4036                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4037
4038         if (is_hdmi) {
4039                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4040
4041                 if (temp > 1)
4042                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4043                 else
4044                         temp = 0;
4045
4046                 I915_WRITE(DPLL_MD(pipe), temp);
4047                 POSTING_READ(DPLL_MD(pipe));
4048         }
4049
4050         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4051 }
4052
4053 static void i9xx_update_pll(struct drm_crtc *crtc,
4054                             struct drm_display_mode *mode,
4055                             struct drm_display_mode *adjusted_mode,
4056                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4057                             int num_connectors)
4058 {
4059         struct drm_device *dev = crtc->dev;
4060         struct drm_i915_private *dev_priv = dev->dev_private;
4061         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4062         int pipe = intel_crtc->pipe;
4063         u32 dpll;
4064         bool is_sdvo;
4065
4066         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4067                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4068
4069         dpll = DPLL_VGA_MODE_DIS;
4070
4071         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4072                 dpll |= DPLLB_MODE_LVDS;
4073         else
4074                 dpll |= DPLLB_MODE_DAC_SERIAL;
4075         if (is_sdvo) {
4076                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4077                 if (pixel_multiplier > 1) {
4078                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4079                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4080                 }
4081                 dpll |= DPLL_DVO_HIGH_SPEED;
4082         }
4083         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4084                 dpll |= DPLL_DVO_HIGH_SPEED;
4085
4086         /* compute bitmask from p1 value */
4087         if (IS_PINEVIEW(dev))
4088                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4089         else {
4090                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4091                 if (IS_G4X(dev) && reduced_clock)
4092                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4093         }
4094         switch (clock->p2) {
4095         case 5:
4096                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4097                 break;
4098         case 7:
4099                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4100                 break;
4101         case 10:
4102                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4103                 break;
4104         case 14:
4105                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4106                 break;
4107         }
4108         if (INTEL_INFO(dev)->gen >= 4)
4109                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4110
4111         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4112                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4113         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4114                 /* XXX: just matching BIOS for now */
4115                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4116                 dpll |= 3;
4117         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4118                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4119                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4120         else
4121                 dpll |= PLL_REF_INPUT_DREFCLK;
4122
4123         dpll |= DPLL_VCO_ENABLE;
4124         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4125         POSTING_READ(DPLL(pipe));
4126         udelay(150);
4127
4128         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4129          * This is an exception to the general rule that mode_set doesn't turn
4130          * things on.
4131          */
4132         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4133                 intel_update_lvds(crtc, clock, adjusted_mode);
4134
4135         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4136                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4137
4138         I915_WRITE(DPLL(pipe), dpll);
4139
4140         /* Wait for the clocks to stabilize. */
4141         POSTING_READ(DPLL(pipe));
4142         udelay(150);
4143
4144         if (INTEL_INFO(dev)->gen >= 4) {
4145                 u32 temp = 0;
4146                 if (is_sdvo) {
4147                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4148                         if (temp > 1)
4149                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4150                         else
4151                                 temp = 0;
4152                 }
4153                 I915_WRITE(DPLL_MD(pipe), temp);
4154         } else {
4155                 /* The pixel multiplier can only be updated once the
4156                  * DPLL is enabled and the clocks are stable.
4157                  *
4158                  * So write it again.
4159                  */
4160                 I915_WRITE(DPLL(pipe), dpll);
4161         }
4162 }
4163
4164 static void i8xx_update_pll(struct drm_crtc *crtc,
4165                             struct drm_display_mode *adjusted_mode,
4166                             intel_clock_t *clock,
4167                             int num_connectors)
4168 {
4169         struct drm_device *dev = crtc->dev;
4170         struct drm_i915_private *dev_priv = dev->dev_private;
4171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172         int pipe = intel_crtc->pipe;
4173         u32 dpll;
4174
4175         dpll = DPLL_VGA_MODE_DIS;
4176
4177         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4178                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4179         } else {
4180                 if (clock->p1 == 2)
4181                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4182                 else
4183                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4184                 if (clock->p2 == 4)
4185                         dpll |= PLL_P2_DIVIDE_BY_4;
4186         }
4187
4188         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4189                 /* XXX: just matching BIOS for now */
4190                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4191                 dpll |= 3;
4192         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4193                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4194                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4195         else
4196                 dpll |= PLL_REF_INPUT_DREFCLK;
4197
4198         dpll |= DPLL_VCO_ENABLE;
4199         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4200         POSTING_READ(DPLL(pipe));
4201         udelay(150);
4202
4203         I915_WRITE(DPLL(pipe), dpll);
4204
4205         /* Wait for the clocks to stabilize. */
4206         POSTING_READ(DPLL(pipe));
4207         udelay(150);
4208
4209         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4210          * This is an exception to the general rule that mode_set doesn't turn
4211          * things on.
4212          */
4213         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4214                 intel_update_lvds(crtc, clock, adjusted_mode);
4215
4216         /* The pixel multiplier can only be updated once the
4217          * DPLL is enabled and the clocks are stable.
4218          *
4219          * So write it again.
4220          */
4221         I915_WRITE(DPLL(pipe), dpll);
4222 }
4223
4224 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4225                               struct drm_display_mode *mode,
4226                               struct drm_display_mode *adjusted_mode,
4227                               int x, int y,
4228                               struct drm_framebuffer *old_fb)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         int plane = intel_crtc->plane;
4235         int refclk, num_connectors = 0;
4236         intel_clock_t clock, reduced_clock;
4237         u32 dspcntr, pipeconf, vsyncshift;
4238         bool ok, has_reduced_clock = false, is_sdvo = false;
4239         bool is_lvds = false, is_tv = false, is_dp = false;
4240         struct intel_encoder *encoder;
4241         const intel_limit_t *limit;
4242         int ret;
4243
4244         for_each_encoder_on_crtc(dev, crtc, encoder) {
4245                 switch (encoder->type) {
4246                 case INTEL_OUTPUT_LVDS:
4247                         is_lvds = true;
4248                         break;
4249                 case INTEL_OUTPUT_SDVO:
4250                 case INTEL_OUTPUT_HDMI:
4251                         is_sdvo = true;
4252                         if (encoder->needs_tv_clock)
4253                                 is_tv = true;
4254                         break;
4255                 case INTEL_OUTPUT_TVOUT:
4256                         is_tv = true;
4257                         break;
4258                 case INTEL_OUTPUT_DISPLAYPORT:
4259                         is_dp = true;
4260                         break;
4261                 }
4262
4263                 num_connectors++;
4264         }
4265
4266         refclk = i9xx_get_refclk(crtc, num_connectors);
4267
4268         /*
4269          * Returns a set of divisors for the desired target clock with the given
4270          * refclk, or FALSE.  The returned values represent the clock equation:
4271          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4272          */
4273         limit = intel_limit(crtc, refclk);
4274         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4275                              &clock);
4276         if (!ok) {
4277                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4278                 return -EINVAL;
4279         }
4280
4281         /* Ensure that the cursor is valid for the new mode before changing... */
4282         intel_crtc_update_cursor(crtc, true);
4283
4284         if (is_lvds && dev_priv->lvds_downclock_avail) {
4285                 /*
4286                  * Ensure we match the reduced clock's P to the target clock.
4287                  * If the clocks don't match, we can't switch the display clock
4288                  * by using the FP0/FP1. In such case we will disable the LVDS
4289                  * downclock feature.
4290                 */
4291                 has_reduced_clock = limit->find_pll(limit, crtc,
4292                                                     dev_priv->lvds_downclock,
4293                                                     refclk,
4294                                                     &clock,
4295                                                     &reduced_clock);
4296         }
4297
4298         if (is_sdvo && is_tv)
4299                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4300
4301         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4302                                  &reduced_clock : NULL);
4303
4304         if (IS_GEN2(dev))
4305                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4306         else if (IS_VALLEYVIEW(dev))
4307                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4308                                refclk, num_connectors);
4309         else
4310                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4311                                 has_reduced_clock ? &reduced_clock : NULL,
4312                                 num_connectors);
4313
4314         /* setup pipeconf */
4315         pipeconf = I915_READ(PIPECONF(pipe));
4316
4317         /* Set up the display plane register */
4318         dspcntr = DISPPLANE_GAMMA_ENABLE;
4319
4320         if (pipe == 0)
4321                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4322         else
4323                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4324
4325         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4326                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4327                  * core speed.
4328                  *
4329                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4330                  * pipe == 0 check?
4331                  */
4332                 if (mode->clock >
4333                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4334                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4335                 else
4336                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4337         }
4338
4339         /* default to 8bpc */
4340         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4341         if (is_dp) {
4342                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4343                         pipeconf |= PIPECONF_BPP_6 |
4344                                     PIPECONF_DITHER_EN |
4345                                     PIPECONF_DITHER_TYPE_SP;
4346                 }
4347         }
4348
4349         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4350         drm_mode_debug_printmodeline(mode);
4351
4352         if (HAS_PIPE_CXSR(dev)) {
4353                 if (intel_crtc->lowfreq_avail) {
4354                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4355                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4356                 } else {
4357                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4358                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4359                 }
4360         }
4361
4362         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4363         if (!IS_GEN2(dev) &&
4364             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4365                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4366                 /* the chip adds 2 halflines automatically */
4367                 adjusted_mode->crtc_vtotal -= 1;
4368                 adjusted_mode->crtc_vblank_end -= 1;
4369                 vsyncshift = adjusted_mode->crtc_hsync_start
4370                              - adjusted_mode->crtc_htotal/2;
4371         } else {
4372                 pipeconf |= PIPECONF_PROGRESSIVE;
4373                 vsyncshift = 0;
4374         }
4375
4376         if (!IS_GEN3(dev))
4377                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4378
4379         I915_WRITE(HTOTAL(pipe),
4380                    (adjusted_mode->crtc_hdisplay - 1) |
4381                    ((adjusted_mode->crtc_htotal - 1) << 16));
4382         I915_WRITE(HBLANK(pipe),
4383                    (adjusted_mode->crtc_hblank_start - 1) |
4384                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4385         I915_WRITE(HSYNC(pipe),
4386                    (adjusted_mode->crtc_hsync_start - 1) |
4387                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4388
4389         I915_WRITE(VTOTAL(pipe),
4390                    (adjusted_mode->crtc_vdisplay - 1) |
4391                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4392         I915_WRITE(VBLANK(pipe),
4393                    (adjusted_mode->crtc_vblank_start - 1) |
4394                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4395         I915_WRITE(VSYNC(pipe),
4396                    (adjusted_mode->crtc_vsync_start - 1) |
4397                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4398
4399         /* pipesrc and dspsize control the size that is scaled from,
4400          * which should always be the user's requested size.
4401          */
4402         I915_WRITE(DSPSIZE(plane),
4403                    ((mode->vdisplay - 1) << 16) |
4404                    (mode->hdisplay - 1));
4405         I915_WRITE(DSPPOS(plane), 0);
4406         I915_WRITE(PIPESRC(pipe),
4407                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4408
4409         I915_WRITE(PIPECONF(pipe), pipeconf);
4410         POSTING_READ(PIPECONF(pipe));
4411         intel_enable_pipe(dev_priv, pipe, false);
4412
4413         intel_wait_for_vblank(dev, pipe);
4414
4415         I915_WRITE(DSPCNTR(plane), dspcntr);
4416         POSTING_READ(DSPCNTR(plane));
4417
4418         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4419
4420         intel_update_watermarks(dev);
4421
4422         return ret;
4423 }
4424
4425 /*
4426  * Initialize reference clocks when the driver loads
4427  */
4428 void ironlake_init_pch_refclk(struct drm_device *dev)
4429 {
4430         struct drm_i915_private *dev_priv = dev->dev_private;
4431         struct drm_mode_config *mode_config = &dev->mode_config;
4432         struct intel_encoder *encoder;
4433         u32 temp;
4434         bool has_lvds = false;
4435         bool has_cpu_edp = false;
4436         bool has_pch_edp = false;
4437         bool has_panel = false;
4438         bool has_ck505 = false;
4439         bool can_ssc = false;
4440
4441         /* We need to take the global config into account */
4442         list_for_each_entry(encoder, &mode_config->encoder_list,
4443                             base.head) {
4444                 switch (encoder->type) {
4445                 case INTEL_OUTPUT_LVDS:
4446                         has_panel = true;
4447                         has_lvds = true;
4448                         break;
4449                 case INTEL_OUTPUT_EDP:
4450                         has_panel = true;
4451                         if (intel_encoder_is_pch_edp(&encoder->base))
4452                                 has_pch_edp = true;
4453                         else
4454                                 has_cpu_edp = true;
4455                         break;
4456                 }
4457         }
4458
4459         if (HAS_PCH_IBX(dev)) {
4460                 has_ck505 = dev_priv->display_clock_mode;
4461                 can_ssc = has_ck505;
4462         } else {
4463                 has_ck505 = false;
4464                 can_ssc = true;
4465         }
4466
4467         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4468                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4469                       has_ck505);
4470
4471         /* Ironlake: try to setup display ref clock before DPLL
4472          * enabling. This is only under driver's control after
4473          * PCH B stepping, previous chipset stepping should be
4474          * ignoring this setting.
4475          */
4476         temp = I915_READ(PCH_DREF_CONTROL);
4477         /* Always enable nonspread source */
4478         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4479
4480         if (has_ck505)
4481                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4482         else
4483                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4484
4485         if (has_panel) {
4486                 temp &= ~DREF_SSC_SOURCE_MASK;
4487                 temp |= DREF_SSC_SOURCE_ENABLE;
4488
4489                 /* SSC must be turned on before enabling the CPU output  */
4490                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4491                         DRM_DEBUG_KMS("Using SSC on panel\n");
4492                         temp |= DREF_SSC1_ENABLE;
4493                 } else
4494                         temp &= ~DREF_SSC1_ENABLE;
4495
4496                 /* Get SSC going before enabling the outputs */
4497                 I915_WRITE(PCH_DREF_CONTROL, temp);
4498                 POSTING_READ(PCH_DREF_CONTROL);
4499                 udelay(200);
4500
4501                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4502
4503                 /* Enable CPU source on CPU attached eDP */
4504                 if (has_cpu_edp) {
4505                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4506                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4507                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4508                         }
4509                         else
4510                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4511                 } else
4512                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4513
4514                 I915_WRITE(PCH_DREF_CONTROL, temp);
4515                 POSTING_READ(PCH_DREF_CONTROL);
4516                 udelay(200);
4517         } else {
4518                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4519
4520                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4521
4522                 /* Turn off CPU output */
4523                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4524
4525                 I915_WRITE(PCH_DREF_CONTROL, temp);
4526                 POSTING_READ(PCH_DREF_CONTROL);
4527                 udelay(200);
4528
4529                 /* Turn off the SSC source */
4530                 temp &= ~DREF_SSC_SOURCE_MASK;
4531                 temp |= DREF_SSC_SOURCE_DISABLE;
4532
4533                 /* Turn off SSC1 */
4534                 temp &= ~ DREF_SSC1_ENABLE;
4535
4536                 I915_WRITE(PCH_DREF_CONTROL, temp);
4537                 POSTING_READ(PCH_DREF_CONTROL);
4538                 udelay(200);
4539         }
4540 }
4541
4542 static int ironlake_get_refclk(struct drm_crtc *crtc)
4543 {
4544         struct drm_device *dev = crtc->dev;
4545         struct drm_i915_private *dev_priv = dev->dev_private;
4546         struct intel_encoder *encoder;
4547         struct intel_encoder *edp_encoder = NULL;
4548         int num_connectors = 0;
4549         bool is_lvds = false;
4550
4551         for_each_encoder_on_crtc(dev, crtc, encoder) {
4552                 switch (encoder->type) {
4553                 case INTEL_OUTPUT_LVDS:
4554                         is_lvds = true;
4555                         break;
4556                 case INTEL_OUTPUT_EDP:
4557                         edp_encoder = encoder;
4558                         break;
4559                 }
4560                 num_connectors++;
4561         }
4562
4563         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4564                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4565                               dev_priv->lvds_ssc_freq);
4566                 return dev_priv->lvds_ssc_freq * 1000;
4567         }
4568
4569         return 120000;
4570 }
4571
4572 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4573                                   struct drm_display_mode *mode,
4574                                   struct drm_display_mode *adjusted_mode,
4575                                   int x, int y,
4576                                   struct drm_framebuffer *old_fb)
4577 {
4578         struct drm_device *dev = crtc->dev;
4579         struct drm_i915_private *dev_priv = dev->dev_private;
4580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581         int pipe = intel_crtc->pipe;
4582         int plane = intel_crtc->plane;
4583         int refclk, num_connectors = 0;
4584         intel_clock_t clock, reduced_clock;
4585         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4586         bool ok, has_reduced_clock = false, is_sdvo = false;
4587         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4588         struct intel_encoder *encoder, *edp_encoder = NULL;
4589         const intel_limit_t *limit;
4590         int ret;
4591         struct fdi_m_n m_n = {0};
4592         u32 temp;
4593         int target_clock, pixel_multiplier, lane, link_bw, factor;
4594         unsigned int pipe_bpp;
4595         bool dither;
4596         bool is_cpu_edp = false, is_pch_edp = false;
4597
4598         for_each_encoder_on_crtc(dev, crtc, encoder) {
4599                 switch (encoder->type) {
4600                 case INTEL_OUTPUT_LVDS:
4601                         is_lvds = true;
4602                         break;
4603                 case INTEL_OUTPUT_SDVO:
4604                 case INTEL_OUTPUT_HDMI:
4605                         is_sdvo = true;
4606                         if (encoder->needs_tv_clock)
4607                                 is_tv = true;
4608                         break;
4609                 case INTEL_OUTPUT_TVOUT:
4610                         is_tv = true;
4611                         break;
4612                 case INTEL_OUTPUT_ANALOG:
4613                         is_crt = true;
4614                         break;
4615                 case INTEL_OUTPUT_DISPLAYPORT:
4616                         is_dp = true;
4617                         break;
4618                 case INTEL_OUTPUT_EDP:
4619                         is_dp = true;
4620                         if (intel_encoder_is_pch_edp(&encoder->base))
4621                                 is_pch_edp = true;
4622                         else
4623                                 is_cpu_edp = true;
4624                         edp_encoder = encoder;
4625                         break;
4626                 }
4627
4628                 num_connectors++;
4629         }
4630
4631         refclk = ironlake_get_refclk(crtc);
4632
4633         /*
4634          * Returns a set of divisors for the desired target clock with the given
4635          * refclk, or FALSE.  The returned values represent the clock equation:
4636          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4637          */
4638         limit = intel_limit(crtc, refclk);
4639         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4640                              &clock);
4641         if (!ok) {
4642                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4643                 return -EINVAL;
4644         }
4645
4646         /* Ensure that the cursor is valid for the new mode before changing... */
4647         intel_crtc_update_cursor(crtc, true);
4648
4649         if (is_lvds && dev_priv->lvds_downclock_avail) {
4650                 /*
4651                  * Ensure we match the reduced clock's P to the target clock.
4652                  * If the clocks don't match, we can't switch the display clock
4653                  * by using the FP0/FP1. In such case we will disable the LVDS
4654                  * downclock feature.
4655                 */
4656                 has_reduced_clock = limit->find_pll(limit, crtc,
4657                                                     dev_priv->lvds_downclock,
4658                                                     refclk,
4659                                                     &clock,
4660                                                     &reduced_clock);
4661         }
4662
4663         if (is_sdvo && is_tv)
4664                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4665
4666
4667         /* FDI link */
4668         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4669         lane = 0;
4670         /* CPU eDP doesn't require FDI link, so just set DP M/N
4671            according to current link config */
4672         if (is_cpu_edp) {
4673                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4674         } else {
4675                 /* FDI is a binary signal running at ~2.7GHz, encoding
4676                  * each output octet as 10 bits. The actual frequency
4677                  * is stored as a divider into a 100MHz clock, and the
4678                  * mode pixel clock is stored in units of 1KHz.
4679                  * Hence the bw of each lane in terms of the mode signal
4680                  * is:
4681                  */
4682                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4683         }
4684
4685         /* [e]DP over FDI requires target mode clock instead of link clock. */
4686         if (edp_encoder)
4687                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4688         else if (is_dp)
4689                 target_clock = mode->clock;
4690         else
4691                 target_clock = adjusted_mode->clock;
4692
4693         /* determine panel color depth */
4694         temp = I915_READ(PIPECONF(pipe));
4695         temp &= ~PIPE_BPC_MASK;
4696         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4697         switch (pipe_bpp) {
4698         case 18:
4699                 temp |= PIPE_6BPC;
4700                 break;
4701         case 24:
4702                 temp |= PIPE_8BPC;
4703                 break;
4704         case 30:
4705                 temp |= PIPE_10BPC;
4706                 break;
4707         case 36:
4708                 temp |= PIPE_12BPC;
4709                 break;
4710         default:
4711                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4712                         pipe_bpp);
4713                 temp |= PIPE_8BPC;
4714                 pipe_bpp = 24;
4715                 break;
4716         }
4717
4718         intel_crtc->bpp = pipe_bpp;
4719         I915_WRITE(PIPECONF(pipe), temp);
4720
4721         if (!lane) {
4722                 /*
4723                  * Account for spread spectrum to avoid
4724                  * oversubscribing the link. Max center spread
4725                  * is 2.5%; use 5% for safety's sake.
4726                  */
4727                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4728                 lane = bps / (link_bw * 8) + 1;
4729         }
4730
4731         intel_crtc->fdi_lanes = lane;
4732
4733         if (pixel_multiplier > 1)
4734                 link_bw *= pixel_multiplier;
4735         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4736                              &m_n);
4737
4738         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4739         if (has_reduced_clock)
4740                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4741                         reduced_clock.m2;
4742
4743         /* Enable autotuning of the PLL clock (if permissible) */
4744         factor = 21;
4745         if (is_lvds) {
4746                 if ((intel_panel_use_ssc(dev_priv) &&
4747                      dev_priv->lvds_ssc_freq == 100) ||
4748                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4749                         factor = 25;
4750         } else if (is_sdvo && is_tv)
4751                 factor = 20;
4752
4753         if (clock.m < factor * clock.n)
4754                 fp |= FP_CB_TUNE;
4755
4756         dpll = 0;
4757
4758         if (is_lvds)
4759                 dpll |= DPLLB_MODE_LVDS;
4760         else
4761                 dpll |= DPLLB_MODE_DAC_SERIAL;
4762         if (is_sdvo) {
4763                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4764                 if (pixel_multiplier > 1) {
4765                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4766                 }
4767                 dpll |= DPLL_DVO_HIGH_SPEED;
4768         }
4769         if (is_dp && !is_cpu_edp)
4770                 dpll |= DPLL_DVO_HIGH_SPEED;
4771
4772         /* compute bitmask from p1 value */
4773         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4774         /* also FPA1 */
4775         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4776
4777         switch (clock.p2) {
4778         case 5:
4779                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4780                 break;
4781         case 7:
4782                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4783                 break;
4784         case 10:
4785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4786                 break;
4787         case 14:
4788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4789                 break;
4790         }
4791
4792         if (is_sdvo && is_tv)
4793                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4794         else if (is_tv)
4795                 /* XXX: just matching BIOS for now */
4796                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4797                 dpll |= 3;
4798         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4799                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4800         else
4801                 dpll |= PLL_REF_INPUT_DREFCLK;
4802
4803         /* setup pipeconf */
4804         pipeconf = I915_READ(PIPECONF(pipe));
4805
4806         /* Set up the display plane register */
4807         dspcntr = DISPPLANE_GAMMA_ENABLE;
4808
4809         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4810         drm_mode_debug_printmodeline(mode);
4811
4812         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4813          * pre-Haswell/LPT generation */
4814         if (HAS_PCH_LPT(dev)) {
4815                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4816                                 pipe);
4817         } else if (!is_cpu_edp) {
4818                 struct intel_pch_pll *pll;
4819
4820                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4821                 if (pll == NULL) {
4822                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4823                                          pipe);
4824                         return -EINVAL;
4825                 }
4826         } else
4827                 intel_put_pch_pll(intel_crtc);
4828
4829         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4830          * This is an exception to the general rule that mode_set doesn't turn
4831          * things on.
4832          */
4833         if (is_lvds) {
4834                 temp = I915_READ(PCH_LVDS);
4835                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4836                 if (HAS_PCH_CPT(dev)) {
4837                         temp &= ~PORT_TRANS_SEL_MASK;
4838                         temp |= PORT_TRANS_SEL_CPT(pipe);
4839                 } else {
4840                         if (pipe == 1)
4841                                 temp |= LVDS_PIPEB_SELECT;
4842                         else
4843                                 temp &= ~LVDS_PIPEB_SELECT;
4844                 }
4845
4846                 /* set the corresponsding LVDS_BORDER bit */
4847                 temp |= dev_priv->lvds_border_bits;
4848                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4849                  * set the DPLLs for dual-channel mode or not.
4850                  */
4851                 if (clock.p2 == 7)
4852                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4853                 else
4854                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4855
4856                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4857                  * appropriately here, but we need to look more thoroughly into how
4858                  * panels behave in the two modes.
4859                  */
4860                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4861                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4862                         temp |= LVDS_HSYNC_POLARITY;
4863                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4864                         temp |= LVDS_VSYNC_POLARITY;
4865                 I915_WRITE(PCH_LVDS, temp);
4866         }
4867
4868         pipeconf &= ~PIPECONF_DITHER_EN;
4869         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4870         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4871                 pipeconf |= PIPECONF_DITHER_EN;
4872                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4873         }
4874         if (is_dp && !is_cpu_edp) {
4875                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4876         } else {
4877                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4878                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4879                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4880                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4881                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4882         }
4883
4884         if (intel_crtc->pch_pll) {
4885                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4886
4887                 /* Wait for the clocks to stabilize. */
4888                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4889                 udelay(150);
4890
4891                 /* The pixel multiplier can only be updated once the
4892                  * DPLL is enabled and the clocks are stable.
4893                  *
4894                  * So write it again.
4895                  */
4896                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4897         }
4898
4899         intel_crtc->lowfreq_avail = false;
4900         if (intel_crtc->pch_pll) {
4901                 if (is_lvds && has_reduced_clock && i915_powersave) {
4902                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4903                         intel_crtc->lowfreq_avail = true;
4904                 } else {
4905                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4906                 }
4907         }
4908
4909         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4910         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4911                 pipeconf |= PIPECONF_INTERLACED_ILK;
4912                 /* the chip adds 2 halflines automatically */
4913                 adjusted_mode->crtc_vtotal -= 1;
4914                 adjusted_mode->crtc_vblank_end -= 1;
4915                 I915_WRITE(VSYNCSHIFT(pipe),
4916                            adjusted_mode->crtc_hsync_start
4917                            - adjusted_mode->crtc_htotal/2);
4918         } else {
4919                 pipeconf |= PIPECONF_PROGRESSIVE;
4920                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4921         }
4922
4923         I915_WRITE(HTOTAL(pipe),
4924                    (adjusted_mode->crtc_hdisplay - 1) |
4925                    ((adjusted_mode->crtc_htotal - 1) << 16));
4926         I915_WRITE(HBLANK(pipe),
4927                    (adjusted_mode->crtc_hblank_start - 1) |
4928                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4929         I915_WRITE(HSYNC(pipe),
4930                    (adjusted_mode->crtc_hsync_start - 1) |
4931                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4932
4933         I915_WRITE(VTOTAL(pipe),
4934                    (adjusted_mode->crtc_vdisplay - 1) |
4935                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4936         I915_WRITE(VBLANK(pipe),
4937                    (adjusted_mode->crtc_vblank_start - 1) |
4938                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4939         I915_WRITE(VSYNC(pipe),
4940                    (adjusted_mode->crtc_vsync_start - 1) |
4941                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4942
4943         /* pipesrc controls the size that is scaled from, which should
4944          * always be the user's requested size.
4945          */
4946         I915_WRITE(PIPESRC(pipe),
4947                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4948
4949         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4950         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4951         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4952         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4953
4954         if (is_cpu_edp)
4955                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4956
4957         I915_WRITE(PIPECONF(pipe), pipeconf);
4958         POSTING_READ(PIPECONF(pipe));
4959
4960         intel_wait_for_vblank(dev, pipe);
4961
4962         I915_WRITE(DSPCNTR(plane), dspcntr);
4963         POSTING_READ(DSPCNTR(plane));
4964
4965         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4966
4967         intel_update_watermarks(dev);
4968
4969         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4970
4971         return ret;
4972 }
4973
4974 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4975                                struct drm_display_mode *mode,
4976                                struct drm_display_mode *adjusted_mode,
4977                                int x, int y,
4978                                struct drm_framebuffer *old_fb)
4979 {
4980         struct drm_device *dev = crtc->dev;
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4983         int pipe = intel_crtc->pipe;
4984         int ret;
4985
4986         drm_vblank_pre_modeset(dev, pipe);
4987
4988         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4989                                               x, y, old_fb);
4990         drm_vblank_post_modeset(dev, pipe);
4991
4992         if (ret)
4993                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4994         else
4995                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4996
4997         return ret;
4998 }
4999
5000 static bool intel_eld_uptodate(struct drm_connector *connector,
5001                                int reg_eldv, uint32_t bits_eldv,
5002                                int reg_elda, uint32_t bits_elda,
5003                                int reg_edid)
5004 {
5005         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5006         uint8_t *eld = connector->eld;
5007         uint32_t i;
5008
5009         i = I915_READ(reg_eldv);
5010         i &= bits_eldv;
5011
5012         if (!eld[0])
5013                 return !i;
5014
5015         if (!i)
5016                 return false;
5017
5018         i = I915_READ(reg_elda);
5019         i &= ~bits_elda;
5020         I915_WRITE(reg_elda, i);
5021
5022         for (i = 0; i < eld[2]; i++)
5023                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5024                         return false;
5025
5026         return true;
5027 }
5028
5029 static void g4x_write_eld(struct drm_connector *connector,
5030                           struct drm_crtc *crtc)
5031 {
5032         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5033         uint8_t *eld = connector->eld;
5034         uint32_t eldv;
5035         uint32_t len;
5036         uint32_t i;
5037
5038         i = I915_READ(G4X_AUD_VID_DID);
5039
5040         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5041                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5042         else
5043                 eldv = G4X_ELDV_DEVCTG;
5044
5045         if (intel_eld_uptodate(connector,
5046                                G4X_AUD_CNTL_ST, eldv,
5047                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5048                                G4X_HDMIW_HDMIEDID))
5049                 return;
5050
5051         i = I915_READ(G4X_AUD_CNTL_ST);
5052         i &= ~(eldv | G4X_ELD_ADDR);
5053         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5054         I915_WRITE(G4X_AUD_CNTL_ST, i);
5055
5056         if (!eld[0])
5057                 return;
5058
5059         len = min_t(uint8_t, eld[2], len);
5060         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5061         for (i = 0; i < len; i++)
5062                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5063
5064         i = I915_READ(G4X_AUD_CNTL_ST);
5065         i |= eldv;
5066         I915_WRITE(G4X_AUD_CNTL_ST, i);
5067 }
5068
5069 static void haswell_write_eld(struct drm_connector *connector,
5070                                      struct drm_crtc *crtc)
5071 {
5072         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073         uint8_t *eld = connector->eld;
5074         struct drm_device *dev = crtc->dev;
5075         uint32_t eldv;
5076         uint32_t i;
5077         int len;
5078         int pipe = to_intel_crtc(crtc)->pipe;
5079         int tmp;
5080
5081         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5082         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5083         int aud_config = HSW_AUD_CFG(pipe);
5084         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5085
5086
5087         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5088
5089         /* Audio output enable */
5090         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5091         tmp = I915_READ(aud_cntrl_st2);
5092         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5093         I915_WRITE(aud_cntrl_st2, tmp);
5094
5095         /* Wait for 1 vertical blank */
5096         intel_wait_for_vblank(dev, pipe);
5097
5098         /* Set ELD valid state */
5099         tmp = I915_READ(aud_cntrl_st2);
5100         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5101         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5102         I915_WRITE(aud_cntrl_st2, tmp);
5103         tmp = I915_READ(aud_cntrl_st2);
5104         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5105
5106         /* Enable HDMI mode */
5107         tmp = I915_READ(aud_config);
5108         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5109         /* clear N_programing_enable and N_value_index */
5110         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5111         I915_WRITE(aud_config, tmp);
5112
5113         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5114
5115         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5116
5117         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5118                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5119                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5120                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5121         } else
5122                 I915_WRITE(aud_config, 0);
5123
5124         if (intel_eld_uptodate(connector,
5125                                aud_cntrl_st2, eldv,
5126                                aud_cntl_st, IBX_ELD_ADDRESS,
5127                                hdmiw_hdmiedid))
5128                 return;
5129
5130         i = I915_READ(aud_cntrl_st2);
5131         i &= ~eldv;
5132         I915_WRITE(aud_cntrl_st2, i);
5133
5134         if (!eld[0])
5135                 return;
5136
5137         i = I915_READ(aud_cntl_st);
5138         i &= ~IBX_ELD_ADDRESS;
5139         I915_WRITE(aud_cntl_st, i);
5140         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5141         DRM_DEBUG_DRIVER("port num:%d\n", i);
5142
5143         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5144         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5145         for (i = 0; i < len; i++)
5146                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5147
5148         i = I915_READ(aud_cntrl_st2);
5149         i |= eldv;
5150         I915_WRITE(aud_cntrl_st2, i);
5151
5152 }
5153
5154 static void ironlake_write_eld(struct drm_connector *connector,
5155                                      struct drm_crtc *crtc)
5156 {
5157         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5158         uint8_t *eld = connector->eld;
5159         uint32_t eldv;
5160         uint32_t i;
5161         int len;
5162         int hdmiw_hdmiedid;
5163         int aud_config;
5164         int aud_cntl_st;
5165         int aud_cntrl_st2;
5166         int pipe = to_intel_crtc(crtc)->pipe;
5167
5168         if (HAS_PCH_IBX(connector->dev)) {
5169                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5170                 aud_config = IBX_AUD_CFG(pipe);
5171                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5172                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5173         } else {
5174                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5175                 aud_config = CPT_AUD_CFG(pipe);
5176                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5177                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5178         }
5179
5180         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5181
5182         i = I915_READ(aud_cntl_st);
5183         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5184         if (!i) {
5185                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5186                 /* operate blindly on all ports */
5187                 eldv = IBX_ELD_VALIDB;
5188                 eldv |= IBX_ELD_VALIDB << 4;
5189                 eldv |= IBX_ELD_VALIDB << 8;
5190         } else {
5191                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5192                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5193         }
5194
5195         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5196                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5197                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5198                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5199         } else
5200                 I915_WRITE(aud_config, 0);
5201
5202         if (intel_eld_uptodate(connector,
5203                                aud_cntrl_st2, eldv,
5204                                aud_cntl_st, IBX_ELD_ADDRESS,
5205                                hdmiw_hdmiedid))
5206                 return;
5207
5208         i = I915_READ(aud_cntrl_st2);
5209         i &= ~eldv;
5210         I915_WRITE(aud_cntrl_st2, i);
5211
5212         if (!eld[0])
5213                 return;
5214
5215         i = I915_READ(aud_cntl_st);
5216         i &= ~IBX_ELD_ADDRESS;
5217         I915_WRITE(aud_cntl_st, i);
5218
5219         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5220         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5221         for (i = 0; i < len; i++)
5222                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5223
5224         i = I915_READ(aud_cntrl_st2);
5225         i |= eldv;
5226         I915_WRITE(aud_cntrl_st2, i);
5227 }
5228
5229 void intel_write_eld(struct drm_encoder *encoder,
5230                      struct drm_display_mode *mode)
5231 {
5232         struct drm_crtc *crtc = encoder->crtc;
5233         struct drm_connector *connector;
5234         struct drm_device *dev = encoder->dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236
5237         connector = drm_select_eld(encoder, mode);
5238         if (!connector)
5239                 return;
5240
5241         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5242                          connector->base.id,
5243                          drm_get_connector_name(connector),
5244                          connector->encoder->base.id,
5245                          drm_get_encoder_name(connector->encoder));
5246
5247         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5248
5249         if (dev_priv->display.write_eld)
5250                 dev_priv->display.write_eld(connector, crtc);
5251 }
5252
5253 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5254 void intel_crtc_load_lut(struct drm_crtc *crtc)
5255 {
5256         struct drm_device *dev = crtc->dev;
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5259         int palreg = PALETTE(intel_crtc->pipe);
5260         int i;
5261
5262         /* The clocks have to be on to load the palette. */
5263         if (!crtc->enabled || !intel_crtc->active)
5264                 return;
5265
5266         /* use legacy palette for Ironlake */
5267         if (HAS_PCH_SPLIT(dev))
5268                 palreg = LGC_PALETTE(intel_crtc->pipe);
5269
5270         for (i = 0; i < 256; i++) {
5271                 I915_WRITE(palreg + 4 * i,
5272                            (intel_crtc->lut_r[i] << 16) |
5273                            (intel_crtc->lut_g[i] << 8) |
5274                            intel_crtc->lut_b[i]);
5275         }
5276 }
5277
5278 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5279 {
5280         struct drm_device *dev = crtc->dev;
5281         struct drm_i915_private *dev_priv = dev->dev_private;
5282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5283         bool visible = base != 0;
5284         u32 cntl;
5285
5286         if (intel_crtc->cursor_visible == visible)
5287                 return;
5288
5289         cntl = I915_READ(_CURACNTR);
5290         if (visible) {
5291                 /* On these chipsets we can only modify the base whilst
5292                  * the cursor is disabled.
5293                  */
5294                 I915_WRITE(_CURABASE, base);
5295
5296                 cntl &= ~(CURSOR_FORMAT_MASK);
5297                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5298                 cntl |= CURSOR_ENABLE |
5299                         CURSOR_GAMMA_ENABLE |
5300                         CURSOR_FORMAT_ARGB;
5301         } else
5302                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5303         I915_WRITE(_CURACNTR, cntl);
5304
5305         intel_crtc->cursor_visible = visible;
5306 }
5307
5308 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5309 {
5310         struct drm_device *dev = crtc->dev;
5311         struct drm_i915_private *dev_priv = dev->dev_private;
5312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313         int pipe = intel_crtc->pipe;
5314         bool visible = base != 0;
5315
5316         if (intel_crtc->cursor_visible != visible) {
5317                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5318                 if (base) {
5319                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5320                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5321                         cntl |= pipe << 28; /* Connect to correct pipe */
5322                 } else {
5323                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5324                         cntl |= CURSOR_MODE_DISABLE;
5325                 }
5326                 I915_WRITE(CURCNTR(pipe), cntl);
5327
5328                 intel_crtc->cursor_visible = visible;
5329         }
5330         /* and commit changes on next vblank */
5331         I915_WRITE(CURBASE(pipe), base);
5332 }
5333
5334 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5335 {
5336         struct drm_device *dev = crtc->dev;
5337         struct drm_i915_private *dev_priv = dev->dev_private;
5338         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5339         int pipe = intel_crtc->pipe;
5340         bool visible = base != 0;
5341
5342         if (intel_crtc->cursor_visible != visible) {
5343                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5344                 if (base) {
5345                         cntl &= ~CURSOR_MODE;
5346                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5347                 } else {
5348                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5349                         cntl |= CURSOR_MODE_DISABLE;
5350                 }
5351                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5352
5353                 intel_crtc->cursor_visible = visible;
5354         }
5355         /* and commit changes on next vblank */
5356         I915_WRITE(CURBASE_IVB(pipe), base);
5357 }
5358
5359 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5360 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5361                                      bool on)
5362 {
5363         struct drm_device *dev = crtc->dev;
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5366         int pipe = intel_crtc->pipe;
5367         int x = intel_crtc->cursor_x;
5368         int y = intel_crtc->cursor_y;
5369         u32 base, pos;
5370         bool visible;
5371
5372         pos = 0;
5373
5374         if (on && crtc->enabled && crtc->fb) {
5375                 base = intel_crtc->cursor_addr;
5376                 if (x > (int) crtc->fb->width)
5377                         base = 0;
5378
5379                 if (y > (int) crtc->fb->height)
5380                         base = 0;
5381         } else
5382                 base = 0;
5383
5384         if (x < 0) {
5385                 if (x + intel_crtc->cursor_width < 0)
5386                         base = 0;
5387
5388                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5389                 x = -x;
5390         }
5391         pos |= x << CURSOR_X_SHIFT;
5392
5393         if (y < 0) {
5394                 if (y + intel_crtc->cursor_height < 0)
5395                         base = 0;
5396
5397                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5398                 y = -y;
5399         }
5400         pos |= y << CURSOR_Y_SHIFT;
5401
5402         visible = base != 0;
5403         if (!visible && !intel_crtc->cursor_visible)
5404                 return;
5405
5406         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5407                 I915_WRITE(CURPOS_IVB(pipe), pos);
5408                 ivb_update_cursor(crtc, base);
5409         } else {
5410                 I915_WRITE(CURPOS(pipe), pos);
5411                 if (IS_845G(dev) || IS_I865G(dev))
5412                         i845_update_cursor(crtc, base);
5413                 else
5414                         i9xx_update_cursor(crtc, base);
5415         }
5416 }
5417
5418 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5419                                  struct drm_file *file,
5420                                  uint32_t handle,
5421                                  uint32_t width, uint32_t height)
5422 {
5423         struct drm_device *dev = crtc->dev;
5424         struct drm_i915_private *dev_priv = dev->dev_private;
5425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5426         struct drm_i915_gem_object *obj;
5427         uint32_t addr;
5428         int ret;
5429
5430         DRM_DEBUG_KMS("\n");
5431
5432         /* if we want to turn off the cursor ignore width and height */
5433         if (!handle) {
5434                 DRM_DEBUG_KMS("cursor off\n");
5435                 addr = 0;
5436                 obj = NULL;
5437                 mutex_lock(&dev->struct_mutex);
5438                 goto finish;
5439         }
5440
5441         /* Currently we only support 64x64 cursors */
5442         if (width != 64 || height != 64) {
5443                 DRM_ERROR("we currently only support 64x64 cursors\n");
5444                 return -EINVAL;
5445         }
5446
5447         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5448         if (&obj->base == NULL)
5449                 return -ENOENT;
5450
5451         if (obj->base.size < width * height * 4) {
5452                 DRM_ERROR("buffer is to small\n");
5453                 ret = -ENOMEM;
5454                 goto fail;
5455         }
5456
5457         /* we only need to pin inside GTT if cursor is non-phy */
5458         mutex_lock(&dev->struct_mutex);
5459         if (!dev_priv->info->cursor_needs_physical) {
5460                 if (obj->tiling_mode) {
5461                         DRM_ERROR("cursor cannot be tiled\n");
5462                         ret = -EINVAL;
5463                         goto fail_locked;
5464                 }
5465
5466                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5467                 if (ret) {
5468                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5469                         goto fail_locked;
5470                 }
5471
5472                 ret = i915_gem_object_put_fence(obj);
5473                 if (ret) {
5474                         DRM_ERROR("failed to release fence for cursor");
5475                         goto fail_unpin;
5476                 }
5477
5478                 addr = obj->gtt_offset;
5479         } else {
5480                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5481                 ret = i915_gem_attach_phys_object(dev, obj,
5482                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5483                                                   align);
5484                 if (ret) {
5485                         DRM_ERROR("failed to attach phys object\n");
5486                         goto fail_locked;
5487                 }
5488                 addr = obj->phys_obj->handle->busaddr;
5489         }
5490
5491         if (IS_GEN2(dev))
5492                 I915_WRITE(CURSIZE, (height << 12) | width);
5493
5494  finish:
5495         if (intel_crtc->cursor_bo) {
5496                 if (dev_priv->info->cursor_needs_physical) {
5497                         if (intel_crtc->cursor_bo != obj)
5498                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5499                 } else
5500                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5501                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5502         }
5503
5504         mutex_unlock(&dev->struct_mutex);
5505
5506         intel_crtc->cursor_addr = addr;
5507         intel_crtc->cursor_bo = obj;
5508         intel_crtc->cursor_width = width;
5509         intel_crtc->cursor_height = height;
5510
5511         intel_crtc_update_cursor(crtc, true);
5512
5513         return 0;
5514 fail_unpin:
5515         i915_gem_object_unpin(obj);
5516 fail_locked:
5517         mutex_unlock(&dev->struct_mutex);
5518 fail:
5519         drm_gem_object_unreference_unlocked(&obj->base);
5520         return ret;
5521 }
5522
5523 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5524 {
5525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5526
5527         intel_crtc->cursor_x = x;
5528         intel_crtc->cursor_y = y;
5529
5530         intel_crtc_update_cursor(crtc, true);
5531
5532         return 0;
5533 }
5534
5535 /** Sets the color ramps on behalf of RandR */
5536 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5537                                  u16 blue, int regno)
5538 {
5539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5540
5541         intel_crtc->lut_r[regno] = red >> 8;
5542         intel_crtc->lut_g[regno] = green >> 8;
5543         intel_crtc->lut_b[regno] = blue >> 8;
5544 }
5545
5546 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5547                              u16 *blue, int regno)
5548 {
5549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5550
5551         *red = intel_crtc->lut_r[regno] << 8;
5552         *green = intel_crtc->lut_g[regno] << 8;
5553         *blue = intel_crtc->lut_b[regno] << 8;
5554 }
5555
5556 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5557                                  u16 *blue, uint32_t start, uint32_t size)
5558 {
5559         int end = (start + size > 256) ? 256 : start + size, i;
5560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561
5562         for (i = start; i < end; i++) {
5563                 intel_crtc->lut_r[i] = red[i] >> 8;
5564                 intel_crtc->lut_g[i] = green[i] >> 8;
5565                 intel_crtc->lut_b[i] = blue[i] >> 8;
5566         }
5567
5568         intel_crtc_load_lut(crtc);
5569 }
5570
5571 /**
5572  * Get a pipe with a simple mode set on it for doing load-based monitor
5573  * detection.
5574  *
5575  * It will be up to the load-detect code to adjust the pipe as appropriate for
5576  * its requirements.  The pipe will be connected to no other encoders.
5577  *
5578  * Currently this code will only succeed if there is a pipe with no encoders
5579  * configured for it.  In the future, it could choose to temporarily disable
5580  * some outputs to free up a pipe for its use.
5581  *
5582  * \return crtc, or NULL if no pipes are available.
5583  */
5584
5585 /* VESA 640x480x72Hz mode to set on the pipe */
5586 static struct drm_display_mode load_detect_mode = {
5587         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5588                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5589 };
5590
5591 static struct drm_framebuffer *
5592 intel_framebuffer_create(struct drm_device *dev,
5593                          struct drm_mode_fb_cmd2 *mode_cmd,
5594                          struct drm_i915_gem_object *obj)
5595 {
5596         struct intel_framebuffer *intel_fb;
5597         int ret;
5598
5599         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5600         if (!intel_fb) {
5601                 drm_gem_object_unreference_unlocked(&obj->base);
5602                 return ERR_PTR(-ENOMEM);
5603         }
5604
5605         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5606         if (ret) {
5607                 drm_gem_object_unreference_unlocked(&obj->base);
5608                 kfree(intel_fb);
5609                 return ERR_PTR(ret);
5610         }
5611
5612         return &intel_fb->base;
5613 }
5614
5615 static u32
5616 intel_framebuffer_pitch_for_width(int width, int bpp)
5617 {
5618         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5619         return ALIGN(pitch, 64);
5620 }
5621
5622 static u32
5623 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5624 {
5625         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5626         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5627 }
5628
5629 static struct drm_framebuffer *
5630 intel_framebuffer_create_for_mode(struct drm_device *dev,
5631                                   struct drm_display_mode *mode,
5632                                   int depth, int bpp)
5633 {
5634         struct drm_i915_gem_object *obj;
5635         struct drm_mode_fb_cmd2 mode_cmd;
5636
5637         obj = i915_gem_alloc_object(dev,
5638                                     intel_framebuffer_size_for_mode(mode, bpp));
5639         if (obj == NULL)
5640                 return ERR_PTR(-ENOMEM);
5641
5642         mode_cmd.width = mode->hdisplay;
5643         mode_cmd.height = mode->vdisplay;
5644         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5645                                                                 bpp);
5646         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5647
5648         return intel_framebuffer_create(dev, &mode_cmd, obj);
5649 }
5650
5651 static struct drm_framebuffer *
5652 mode_fits_in_fbdev(struct drm_device *dev,
5653                    struct drm_display_mode *mode)
5654 {
5655         struct drm_i915_private *dev_priv = dev->dev_private;
5656         struct drm_i915_gem_object *obj;
5657         struct drm_framebuffer *fb;
5658
5659         if (dev_priv->fbdev == NULL)
5660                 return NULL;
5661
5662         obj = dev_priv->fbdev->ifb.obj;
5663         if (obj == NULL)
5664                 return NULL;
5665
5666         fb = &dev_priv->fbdev->ifb.base;
5667         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5668                                                                fb->bits_per_pixel))
5669                 return NULL;
5670
5671         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5672                 return NULL;
5673
5674         return fb;
5675 }
5676
5677 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5678                                 struct drm_display_mode *mode,
5679                                 struct intel_load_detect_pipe *old)
5680 {
5681         struct intel_crtc *intel_crtc;
5682         struct intel_encoder *intel_encoder =
5683                 intel_attached_encoder(connector);
5684         struct drm_crtc *possible_crtc;
5685         struct drm_encoder *encoder = &intel_encoder->base;
5686         struct drm_crtc *crtc = NULL;
5687         struct drm_device *dev = encoder->dev;
5688         struct drm_framebuffer *old_fb;
5689         int i = -1;
5690
5691         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5692                       connector->base.id, drm_get_connector_name(connector),
5693                       encoder->base.id, drm_get_encoder_name(encoder));
5694
5695         /*
5696          * Algorithm gets a little messy:
5697          *
5698          *   - if the connector already has an assigned crtc, use it (but make
5699          *     sure it's on first)
5700          *
5701          *   - try to find the first unused crtc that can drive this connector,
5702          *     and use that if we find one
5703          */
5704
5705         /* See if we already have a CRTC for this connector */
5706         if (encoder->crtc) {
5707                 crtc = encoder->crtc;
5708
5709                 old->dpms_mode = connector->dpms;
5710                 old->load_detect_temp = false;
5711
5712                 /* Make sure the crtc and connector are running */
5713                 if (connector->dpms != DRM_MODE_DPMS_ON)
5714                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5715
5716                 return true;
5717         }
5718
5719         /* Find an unused one (if possible) */
5720         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5721                 i++;
5722                 if (!(encoder->possible_crtcs & (1 << i)))
5723                         continue;
5724                 if (!possible_crtc->enabled) {
5725                         crtc = possible_crtc;
5726                         break;
5727                 }
5728         }
5729
5730         /*
5731          * If we didn't find an unused CRTC, don't use any.
5732          */
5733         if (!crtc) {
5734                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5735                 return false;
5736         }
5737
5738         encoder->crtc = crtc;
5739         connector->encoder = encoder;
5740
5741         intel_crtc = to_intel_crtc(crtc);
5742         old->dpms_mode = connector->dpms;
5743         old->load_detect_temp = true;
5744         old->release_fb = NULL;
5745
5746         if (!mode)
5747                 mode = &load_detect_mode;
5748
5749         old_fb = crtc->fb;
5750
5751         /* We need a framebuffer large enough to accommodate all accesses
5752          * that the plane may generate whilst we perform load detection.
5753          * We can not rely on the fbcon either being present (we get called
5754          * during its initialisation to detect all boot displays, or it may
5755          * not even exist) or that it is large enough to satisfy the
5756          * requested mode.
5757          */
5758         crtc->fb = mode_fits_in_fbdev(dev, mode);
5759         if (crtc->fb == NULL) {
5760                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5761                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5762                 old->release_fb = crtc->fb;
5763         } else
5764                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5765         if (IS_ERR(crtc->fb)) {
5766                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5767                 goto fail;
5768         }
5769
5770         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5771                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5772                 if (old->release_fb)
5773                         old->release_fb->funcs->destroy(old->release_fb);
5774                 goto fail;
5775         }
5776
5777         /* let the connector get through one full cycle before testing */
5778         intel_wait_for_vblank(dev, intel_crtc->pipe);
5779
5780         return true;
5781 fail:
5782         connector->encoder = NULL;
5783         encoder->crtc = NULL;
5784         crtc->fb = old_fb;
5785         return false;
5786 }
5787
5788 void intel_release_load_detect_pipe(struct drm_connector *connector,
5789                                     struct intel_load_detect_pipe *old)
5790 {
5791         struct intel_encoder *intel_encoder =
5792                 intel_attached_encoder(connector);
5793         struct drm_encoder *encoder = &intel_encoder->base;
5794         struct drm_device *dev = encoder->dev;
5795
5796         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5797                       connector->base.id, drm_get_connector_name(connector),
5798                       encoder->base.id, drm_get_encoder_name(encoder));
5799
5800         if (old->load_detect_temp) {
5801                 connector->encoder = NULL;
5802                 encoder->crtc = NULL;
5803                 drm_helper_disable_unused_functions(dev);
5804
5805                 if (old->release_fb)
5806                         old->release_fb->funcs->destroy(old->release_fb);
5807
5808                 return;
5809         }
5810
5811         /* Switch crtc and encoder back off if necessary */
5812         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5813                 connector->funcs->dpms(connector, old->dpms_mode);
5814 }
5815
5816 /* Returns the clock of the currently programmed mode of the given pipe. */
5817 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5818 {
5819         struct drm_i915_private *dev_priv = dev->dev_private;
5820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5821         int pipe = intel_crtc->pipe;
5822         u32 dpll = I915_READ(DPLL(pipe));
5823         u32 fp;
5824         intel_clock_t clock;
5825
5826         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5827                 fp = I915_READ(FP0(pipe));
5828         else
5829                 fp = I915_READ(FP1(pipe));
5830
5831         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5832         if (IS_PINEVIEW(dev)) {
5833                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5834                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5835         } else {
5836                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5837                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5838         }
5839
5840         if (!IS_GEN2(dev)) {
5841                 if (IS_PINEVIEW(dev))
5842                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5843                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5844                 else
5845                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5846                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5847
5848                 switch (dpll & DPLL_MODE_MASK) {
5849                 case DPLLB_MODE_DAC_SERIAL:
5850                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5851                                 5 : 10;
5852                         break;
5853                 case DPLLB_MODE_LVDS:
5854                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5855                                 7 : 14;
5856                         break;
5857                 default:
5858                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5859                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5860                         return 0;
5861                 }
5862
5863                 /* XXX: Handle the 100Mhz refclk */
5864                 intel_clock(dev, 96000, &clock);
5865         } else {
5866                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5867
5868                 if (is_lvds) {
5869                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5870                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5871                         clock.p2 = 14;
5872
5873                         if ((dpll & PLL_REF_INPUT_MASK) ==
5874                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5875                                 /* XXX: might not be 66MHz */
5876                                 intel_clock(dev, 66000, &clock);
5877                         } else
5878                                 intel_clock(dev, 48000, &clock);
5879                 } else {
5880                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5881                                 clock.p1 = 2;
5882                         else {
5883                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5884                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5885                         }
5886                         if (dpll & PLL_P2_DIVIDE_BY_4)
5887                                 clock.p2 = 4;
5888                         else
5889                                 clock.p2 = 2;
5890
5891                         intel_clock(dev, 48000, &clock);
5892                 }
5893         }
5894
5895         /* XXX: It would be nice to validate the clocks, but we can't reuse
5896          * i830PllIsValid() because it relies on the xf86_config connector
5897          * configuration being accurate, which it isn't necessarily.
5898          */
5899
5900         return clock.dot;
5901 }
5902
5903 /** Returns the currently programmed mode of the given pipe. */
5904 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5905                                              struct drm_crtc *crtc)
5906 {
5907         struct drm_i915_private *dev_priv = dev->dev_private;
5908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5909         int pipe = intel_crtc->pipe;
5910         struct drm_display_mode *mode;
5911         int htot = I915_READ(HTOTAL(pipe));
5912         int hsync = I915_READ(HSYNC(pipe));
5913         int vtot = I915_READ(VTOTAL(pipe));
5914         int vsync = I915_READ(VSYNC(pipe));
5915
5916         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5917         if (!mode)
5918                 return NULL;
5919
5920         mode->clock = intel_crtc_clock_get(dev, crtc);
5921         mode->hdisplay = (htot & 0xffff) + 1;
5922         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5923         mode->hsync_start = (hsync & 0xffff) + 1;
5924         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5925         mode->vdisplay = (vtot & 0xffff) + 1;
5926         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5927         mode->vsync_start = (vsync & 0xffff) + 1;
5928         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5929
5930         drm_mode_set_name(mode);
5931
5932         return mode;
5933 }
5934
5935 static void intel_increase_pllclock(struct drm_crtc *crtc)
5936 {
5937         struct drm_device *dev = crtc->dev;
5938         drm_i915_private_t *dev_priv = dev->dev_private;
5939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940         int pipe = intel_crtc->pipe;
5941         int dpll_reg = DPLL(pipe);
5942         int dpll;
5943
5944         if (HAS_PCH_SPLIT(dev))
5945                 return;
5946
5947         if (!dev_priv->lvds_downclock_avail)
5948                 return;
5949
5950         dpll = I915_READ(dpll_reg);
5951         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5952                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5953
5954                 assert_panel_unlocked(dev_priv, pipe);
5955
5956                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5957                 I915_WRITE(dpll_reg, dpll);
5958                 intel_wait_for_vblank(dev, pipe);
5959
5960                 dpll = I915_READ(dpll_reg);
5961                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5962                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5963         }
5964 }
5965
5966 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5967 {
5968         struct drm_device *dev = crtc->dev;
5969         drm_i915_private_t *dev_priv = dev->dev_private;
5970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5971
5972         if (HAS_PCH_SPLIT(dev))
5973                 return;
5974
5975         if (!dev_priv->lvds_downclock_avail)
5976                 return;
5977
5978         /*
5979          * Since this is called by a timer, we should never get here in
5980          * the manual case.
5981          */
5982         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5983                 int pipe = intel_crtc->pipe;
5984                 int dpll_reg = DPLL(pipe);
5985                 int dpll;
5986
5987                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5988
5989                 assert_panel_unlocked(dev_priv, pipe);
5990
5991                 dpll = I915_READ(dpll_reg);
5992                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5993                 I915_WRITE(dpll_reg, dpll);
5994                 intel_wait_for_vblank(dev, pipe);
5995                 dpll = I915_READ(dpll_reg);
5996                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5997                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5998         }
5999
6000 }
6001
6002 void intel_mark_busy(struct drm_device *dev)
6003 {
6004         i915_update_gfx_val(dev->dev_private);
6005 }
6006
6007 void intel_mark_idle(struct drm_device *dev)
6008 {
6009 }
6010
6011 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6012 {
6013         struct drm_device *dev = obj->base.dev;
6014         struct drm_crtc *crtc;
6015
6016         if (!i915_powersave)
6017                 return;
6018
6019         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6020                 if (!crtc->fb)
6021                         continue;
6022
6023                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6024                         intel_increase_pllclock(crtc);
6025         }
6026 }
6027
6028 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6029 {
6030         struct drm_device *dev = obj->base.dev;
6031         struct drm_crtc *crtc;
6032
6033         if (!i915_powersave)
6034                 return;
6035
6036         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6037                 if (!crtc->fb)
6038                         continue;
6039
6040                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6041                         intel_decrease_pllclock(crtc);
6042         }
6043 }
6044
6045 static void intel_crtc_destroy(struct drm_crtc *crtc)
6046 {
6047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048         struct drm_device *dev = crtc->dev;
6049         struct intel_unpin_work *work;
6050         unsigned long flags;
6051
6052         spin_lock_irqsave(&dev->event_lock, flags);
6053         work = intel_crtc->unpin_work;
6054         intel_crtc->unpin_work = NULL;
6055         spin_unlock_irqrestore(&dev->event_lock, flags);
6056
6057         if (work) {
6058                 cancel_work_sync(&work->work);
6059                 kfree(work);
6060         }
6061
6062         drm_crtc_cleanup(crtc);
6063
6064         kfree(intel_crtc);
6065 }
6066
6067 static void intel_unpin_work_fn(struct work_struct *__work)
6068 {
6069         struct intel_unpin_work *work =
6070                 container_of(__work, struct intel_unpin_work, work);
6071
6072         mutex_lock(&work->dev->struct_mutex);
6073         intel_unpin_fb_obj(work->old_fb_obj);
6074         drm_gem_object_unreference(&work->pending_flip_obj->base);
6075         drm_gem_object_unreference(&work->old_fb_obj->base);
6076
6077         intel_update_fbc(work->dev);
6078         mutex_unlock(&work->dev->struct_mutex);
6079         kfree(work);
6080 }
6081
6082 static void do_intel_finish_page_flip(struct drm_device *dev,
6083                                       struct drm_crtc *crtc)
6084 {
6085         drm_i915_private_t *dev_priv = dev->dev_private;
6086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087         struct intel_unpin_work *work;
6088         struct drm_i915_gem_object *obj;
6089         struct drm_pending_vblank_event *e;
6090         struct timeval tnow, tvbl;
6091         unsigned long flags;
6092
6093         /* Ignore early vblank irqs */
6094         if (intel_crtc == NULL)
6095                 return;
6096
6097         do_gettimeofday(&tnow);
6098
6099         spin_lock_irqsave(&dev->event_lock, flags);
6100         work = intel_crtc->unpin_work;
6101         if (work == NULL || !work->pending) {
6102                 spin_unlock_irqrestore(&dev->event_lock, flags);
6103                 return;
6104         }
6105
6106         intel_crtc->unpin_work = NULL;
6107
6108         if (work->event) {
6109                 e = work->event;
6110                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6111
6112                 /* Called before vblank count and timestamps have
6113                  * been updated for the vblank interval of flip
6114                  * completion? Need to increment vblank count and
6115                  * add one videorefresh duration to returned timestamp
6116                  * to account for this. We assume this happened if we
6117                  * get called over 0.9 frame durations after the last
6118                  * timestamped vblank.
6119                  *
6120                  * This calculation can not be used with vrefresh rates
6121                  * below 5Hz (10Hz to be on the safe side) without
6122                  * promoting to 64 integers.
6123                  */
6124                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6125                     9 * crtc->framedur_ns) {
6126                         e->event.sequence++;
6127                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6128                                              crtc->framedur_ns);
6129                 }
6130
6131                 e->event.tv_sec = tvbl.tv_sec;
6132                 e->event.tv_usec = tvbl.tv_usec;
6133
6134                 list_add_tail(&e->base.link,
6135                               &e->base.file_priv->event_list);
6136                 wake_up_interruptible(&e->base.file_priv->event_wait);
6137         }
6138
6139         drm_vblank_put(dev, intel_crtc->pipe);
6140
6141         spin_unlock_irqrestore(&dev->event_lock, flags);
6142
6143         obj = work->old_fb_obj;
6144
6145         atomic_clear_mask(1 << intel_crtc->plane,
6146                           &obj->pending_flip.counter);
6147         if (atomic_read(&obj->pending_flip) == 0)
6148                 wake_up(&dev_priv->pending_flip_queue);
6149
6150         schedule_work(&work->work);
6151
6152         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6153 }
6154
6155 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6156 {
6157         drm_i915_private_t *dev_priv = dev->dev_private;
6158         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6159
6160         do_intel_finish_page_flip(dev, crtc);
6161 }
6162
6163 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6164 {
6165         drm_i915_private_t *dev_priv = dev->dev_private;
6166         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6167
6168         do_intel_finish_page_flip(dev, crtc);
6169 }
6170
6171 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6172 {
6173         drm_i915_private_t *dev_priv = dev->dev_private;
6174         struct intel_crtc *intel_crtc =
6175                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6176         unsigned long flags;
6177
6178         spin_lock_irqsave(&dev->event_lock, flags);
6179         if (intel_crtc->unpin_work) {
6180                 if ((++intel_crtc->unpin_work->pending) > 1)
6181                         DRM_ERROR("Prepared flip multiple times\n");
6182         } else {
6183                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6184         }
6185         spin_unlock_irqrestore(&dev->event_lock, flags);
6186 }
6187
6188 static int intel_gen2_queue_flip(struct drm_device *dev,
6189                                  struct drm_crtc *crtc,
6190                                  struct drm_framebuffer *fb,
6191                                  struct drm_i915_gem_object *obj)
6192 {
6193         struct drm_i915_private *dev_priv = dev->dev_private;
6194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195         u32 flip_mask;
6196         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6197         int ret;
6198
6199         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6200         if (ret)
6201                 goto err;
6202
6203         ret = intel_ring_begin(ring, 6);
6204         if (ret)
6205                 goto err_unpin;
6206
6207         /* Can't queue multiple flips, so wait for the previous
6208          * one to finish before executing the next.
6209          */
6210         if (intel_crtc->plane)
6211                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6212         else
6213                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6214         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6215         intel_ring_emit(ring, MI_NOOP);
6216         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6217                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6218         intel_ring_emit(ring, fb->pitches[0]);
6219         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6220         intel_ring_emit(ring, 0); /* aux display base address, unused */
6221         intel_ring_advance(ring);
6222         return 0;
6223
6224 err_unpin:
6225         intel_unpin_fb_obj(obj);
6226 err:
6227         return ret;
6228 }
6229
6230 static int intel_gen3_queue_flip(struct drm_device *dev,
6231                                  struct drm_crtc *crtc,
6232                                  struct drm_framebuffer *fb,
6233                                  struct drm_i915_gem_object *obj)
6234 {
6235         struct drm_i915_private *dev_priv = dev->dev_private;
6236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237         u32 flip_mask;
6238         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6239         int ret;
6240
6241         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6242         if (ret)
6243                 goto err;
6244
6245         ret = intel_ring_begin(ring, 6);
6246         if (ret)
6247                 goto err_unpin;
6248
6249         if (intel_crtc->plane)
6250                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6251         else
6252                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6253         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6254         intel_ring_emit(ring, MI_NOOP);
6255         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6256                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6257         intel_ring_emit(ring, fb->pitches[0]);
6258         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6259         intel_ring_emit(ring, MI_NOOP);
6260
6261         intel_ring_advance(ring);
6262         return 0;
6263
6264 err_unpin:
6265         intel_unpin_fb_obj(obj);
6266 err:
6267         return ret;
6268 }
6269
6270 static int intel_gen4_queue_flip(struct drm_device *dev,
6271                                  struct drm_crtc *crtc,
6272                                  struct drm_framebuffer *fb,
6273                                  struct drm_i915_gem_object *obj)
6274 {
6275         struct drm_i915_private *dev_priv = dev->dev_private;
6276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6277         uint32_t pf, pipesrc;
6278         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6279         int ret;
6280
6281         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6282         if (ret)
6283                 goto err;
6284
6285         ret = intel_ring_begin(ring, 4);
6286         if (ret)
6287                 goto err_unpin;
6288
6289         /* i965+ uses the linear or tiled offsets from the
6290          * Display Registers (which do not change across a page-flip)
6291          * so we need only reprogram the base address.
6292          */
6293         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6294                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6295         intel_ring_emit(ring, fb->pitches[0]);
6296         intel_ring_emit(ring,
6297                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6298                         obj->tiling_mode);
6299
6300         /* XXX Enabling the panel-fitter across page-flip is so far
6301          * untested on non-native modes, so ignore it for now.
6302          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6303          */
6304         pf = 0;
6305         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6306         intel_ring_emit(ring, pf | pipesrc);
6307         intel_ring_advance(ring);
6308         return 0;
6309
6310 err_unpin:
6311         intel_unpin_fb_obj(obj);
6312 err:
6313         return ret;
6314 }
6315
6316 static int intel_gen6_queue_flip(struct drm_device *dev,
6317                                  struct drm_crtc *crtc,
6318                                  struct drm_framebuffer *fb,
6319                                  struct drm_i915_gem_object *obj)
6320 {
6321         struct drm_i915_private *dev_priv = dev->dev_private;
6322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6323         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6324         uint32_t pf, pipesrc;
6325         int ret;
6326
6327         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6328         if (ret)
6329                 goto err;
6330
6331         ret = intel_ring_begin(ring, 4);
6332         if (ret)
6333                 goto err_unpin;
6334
6335         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6336                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6337         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6338         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6339
6340         /* Contrary to the suggestions in the documentation,
6341          * "Enable Panel Fitter" does not seem to be required when page
6342          * flipping with a non-native mode, and worse causes a normal
6343          * modeset to fail.
6344          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6345          */
6346         pf = 0;
6347         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6348         intel_ring_emit(ring, pf | pipesrc);
6349         intel_ring_advance(ring);
6350         return 0;
6351
6352 err_unpin:
6353         intel_unpin_fb_obj(obj);
6354 err:
6355         return ret;
6356 }
6357
6358 /*
6359  * On gen7 we currently use the blit ring because (in early silicon at least)
6360  * the render ring doesn't give us interrpts for page flip completion, which
6361  * means clients will hang after the first flip is queued.  Fortunately the
6362  * blit ring generates interrupts properly, so use it instead.
6363  */
6364 static int intel_gen7_queue_flip(struct drm_device *dev,
6365                                  struct drm_crtc *crtc,
6366                                  struct drm_framebuffer *fb,
6367                                  struct drm_i915_gem_object *obj)
6368 {
6369         struct drm_i915_private *dev_priv = dev->dev_private;
6370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6372         uint32_t plane_bit = 0;
6373         int ret;
6374
6375         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6376         if (ret)
6377                 goto err;
6378
6379         switch(intel_crtc->plane) {
6380         case PLANE_A:
6381                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6382                 break;
6383         case PLANE_B:
6384                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6385                 break;
6386         case PLANE_C:
6387                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6388                 break;
6389         default:
6390                 WARN_ONCE(1, "unknown plane in flip command\n");
6391                 ret = -ENODEV;
6392                 goto err_unpin;
6393         }
6394
6395         ret = intel_ring_begin(ring, 4);
6396         if (ret)
6397                 goto err_unpin;
6398
6399         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6400         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6401         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6402         intel_ring_emit(ring, (MI_NOOP));
6403         intel_ring_advance(ring);
6404         return 0;
6405
6406 err_unpin:
6407         intel_unpin_fb_obj(obj);
6408 err:
6409         return ret;
6410 }
6411
6412 static int intel_default_queue_flip(struct drm_device *dev,
6413                                     struct drm_crtc *crtc,
6414                                     struct drm_framebuffer *fb,
6415                                     struct drm_i915_gem_object *obj)
6416 {
6417         return -ENODEV;
6418 }
6419
6420 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6421                                 struct drm_framebuffer *fb,
6422                                 struct drm_pending_vblank_event *event)
6423 {
6424         struct drm_device *dev = crtc->dev;
6425         struct drm_i915_private *dev_priv = dev->dev_private;
6426         struct intel_framebuffer *intel_fb;
6427         struct drm_i915_gem_object *obj;
6428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6429         struct intel_unpin_work *work;
6430         unsigned long flags;
6431         int ret;
6432
6433         /* Can't change pixel format via MI display flips. */
6434         if (fb->pixel_format != crtc->fb->pixel_format)
6435                 return -EINVAL;
6436
6437         /*
6438          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6439          * Note that pitch changes could also affect these register.
6440          */
6441         if (INTEL_INFO(dev)->gen > 3 &&
6442             (fb->offsets[0] != crtc->fb->offsets[0] ||
6443              fb->pitches[0] != crtc->fb->pitches[0]))
6444                 return -EINVAL;
6445
6446         work = kzalloc(sizeof *work, GFP_KERNEL);
6447         if (work == NULL)
6448                 return -ENOMEM;
6449
6450         work->event = event;
6451         work->dev = crtc->dev;
6452         intel_fb = to_intel_framebuffer(crtc->fb);
6453         work->old_fb_obj = intel_fb->obj;
6454         INIT_WORK(&work->work, intel_unpin_work_fn);
6455
6456         ret = drm_vblank_get(dev, intel_crtc->pipe);
6457         if (ret)
6458                 goto free_work;
6459
6460         /* We borrow the event spin lock for protecting unpin_work */
6461         spin_lock_irqsave(&dev->event_lock, flags);
6462         if (intel_crtc->unpin_work) {
6463                 spin_unlock_irqrestore(&dev->event_lock, flags);
6464                 kfree(work);
6465                 drm_vblank_put(dev, intel_crtc->pipe);
6466
6467                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6468                 return -EBUSY;
6469         }
6470         intel_crtc->unpin_work = work;
6471         spin_unlock_irqrestore(&dev->event_lock, flags);
6472
6473         intel_fb = to_intel_framebuffer(fb);
6474         obj = intel_fb->obj;
6475
6476         ret = i915_mutex_lock_interruptible(dev);
6477         if (ret)
6478                 goto cleanup;
6479
6480         /* Reference the objects for the scheduled work. */
6481         drm_gem_object_reference(&work->old_fb_obj->base);
6482         drm_gem_object_reference(&obj->base);
6483
6484         crtc->fb = fb;
6485
6486         work->pending_flip_obj = obj;
6487
6488         work->enable_stall_check = true;
6489
6490         /* Block clients from rendering to the new back buffer until
6491          * the flip occurs and the object is no longer visible.
6492          */
6493         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6494
6495         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6496         if (ret)
6497                 goto cleanup_pending;
6498
6499         intel_disable_fbc(dev);
6500         intel_mark_fb_busy(obj);
6501         mutex_unlock(&dev->struct_mutex);
6502
6503         trace_i915_flip_request(intel_crtc->plane, obj);
6504
6505         return 0;
6506
6507 cleanup_pending:
6508         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6509         drm_gem_object_unreference(&work->old_fb_obj->base);
6510         drm_gem_object_unreference(&obj->base);
6511         mutex_unlock(&dev->struct_mutex);
6512
6513 cleanup:
6514         spin_lock_irqsave(&dev->event_lock, flags);
6515         intel_crtc->unpin_work = NULL;
6516         spin_unlock_irqrestore(&dev->event_lock, flags);
6517
6518         drm_vblank_put(dev, intel_crtc->pipe);
6519 free_work:
6520         kfree(work);
6521
6522         return ret;
6523 }
6524
6525 static void intel_sanitize_modesetting(struct drm_device *dev,
6526                                        int pipe, int plane)
6527 {
6528         struct drm_i915_private *dev_priv = dev->dev_private;
6529         u32 reg, val;
6530         int i;
6531
6532         /* Clear any frame start delays used for debugging left by the BIOS */
6533         for_each_pipe(i) {
6534                 reg = PIPECONF(i);
6535                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6536         }
6537
6538         if (HAS_PCH_SPLIT(dev))
6539                 return;
6540
6541         /* Who knows what state these registers were left in by the BIOS or
6542          * grub?
6543          *
6544          * If we leave the registers in a conflicting state (e.g. with the
6545          * display plane reading from the other pipe than the one we intend
6546          * to use) then when we attempt to teardown the active mode, we will
6547          * not disable the pipes and planes in the correct order -- leaving
6548          * a plane reading from a disabled pipe and possibly leading to
6549          * undefined behaviour.
6550          */
6551
6552         reg = DSPCNTR(plane);
6553         val = I915_READ(reg);
6554
6555         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6556                 return;
6557         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6558                 return;
6559
6560         /* This display plane is active and attached to the other CPU pipe. */
6561         pipe = !pipe;
6562
6563         /* Disable the plane and wait for it to stop reading from the pipe. */
6564         intel_disable_plane(dev_priv, plane, pipe);
6565         intel_disable_pipe(dev_priv, pipe);
6566 }
6567
6568 static void intel_crtc_reset(struct drm_crtc *crtc)
6569 {
6570         struct drm_device *dev = crtc->dev;
6571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6572
6573         /* Reset flags back to the 'unknown' status so that they
6574          * will be correctly set on the initial modeset.
6575          */
6576         intel_crtc->dpms_mode = -1;
6577
6578         /* We need to fix up any BIOS configuration that conflicts with
6579          * our expectations.
6580          */
6581         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6582 }
6583
6584 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6585         .mode_fixup = intel_crtc_mode_fixup,
6586         .mode_set = intel_crtc_mode_set,
6587         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6588         .load_lut = intel_crtc_load_lut,
6589         .disable = intel_crtc_disable,
6590 };
6591
6592 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6593                                   struct drm_crtc *crtc)
6594 {
6595         struct drm_device *dev;
6596         struct drm_crtc *tmp;
6597         int crtc_mask = 1;
6598
6599         WARN(!crtc, "checking null crtc?\n");
6600
6601         dev = crtc->dev;
6602
6603         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6604                 if (tmp == crtc)
6605                         break;
6606                 crtc_mask <<= 1;
6607         }
6608
6609         if (encoder->possible_crtcs & crtc_mask)
6610                 return true;
6611         return false;
6612 }
6613
6614 static int
6615 intel_crtc_helper_disable(struct drm_crtc *crtc)
6616 {
6617         struct drm_device *dev = crtc->dev;
6618         struct drm_connector *connector;
6619         struct drm_encoder *encoder;
6620
6621         /* Decouple all encoders and their attached connectors from this crtc */
6622         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6623                 if (encoder->crtc != crtc)
6624                         continue;
6625
6626                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6627                         if (connector->encoder != encoder)
6628                                 continue;
6629
6630                         connector->encoder = NULL;
6631                 }
6632         }
6633
6634         drm_helper_disable_unused_functions(dev);
6635         return 0;
6636 }
6637
6638 static int intel_crtc_set_config(struct drm_mode_set *set)
6639 {
6640         struct drm_device *dev;
6641         struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6642         struct drm_encoder *save_encoders, *new_encoder, *encoder;
6643         struct drm_framebuffer *old_fb = NULL;
6644         bool mode_changed = false; /* if true do a full mode set */
6645         bool fb_changed = false; /* if true and !mode_changed just do a flip */
6646         struct drm_connector *save_connectors, *connector;
6647         int count = 0, ro, fail = 0;
6648         struct drm_mode_set save_set;
6649         int ret;
6650         int i;
6651
6652         DRM_DEBUG_KMS("\n");
6653
6654         if (!set)
6655                 return -EINVAL;
6656
6657         if (!set->crtc)
6658                 return -EINVAL;
6659
6660         if (!set->crtc->helper_private)
6661                 return -EINVAL;
6662
6663
6664         if (!set->mode)
6665                 set->fb = NULL;
6666
6667         if (set->fb) {
6668                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6669                                 set->crtc->base.id, set->fb->base.id,
6670                                 (int)set->num_connectors, set->x, set->y);
6671         } else {
6672                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6673                 return intel_crtc_helper_disable(set->crtc);
6674         }
6675
6676         dev = set->crtc->dev;
6677
6678         /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6679          * connector data. */
6680         save_crtcs = kzalloc(dev->mode_config.num_crtc *
6681                              sizeof(struct drm_crtc), GFP_KERNEL);
6682         if (!save_crtcs)
6683                 return -ENOMEM;
6684
6685         save_encoders = kzalloc(dev->mode_config.num_encoder *
6686                                 sizeof(struct drm_encoder), GFP_KERNEL);
6687         if (!save_encoders) {
6688                 kfree(save_crtcs);
6689                 return -ENOMEM;
6690         }
6691
6692         save_connectors = kzalloc(dev->mode_config.num_connector *
6693                                 sizeof(struct drm_connector), GFP_KERNEL);
6694         if (!save_connectors) {
6695                 kfree(save_crtcs);
6696                 kfree(save_encoders);
6697                 return -ENOMEM;
6698         }
6699
6700         /* Copy data. Note that driver private data is not affected.
6701          * Should anything bad happen only the expected state is
6702          * restored, not the drivers personal bookkeeping.
6703          */
6704         count = 0;
6705         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6706                 save_crtcs[count++] = *crtc;
6707         }
6708
6709         count = 0;
6710         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6711                 save_encoders[count++] = *encoder;
6712         }
6713
6714         count = 0;
6715         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6716                 save_connectors[count++] = *connector;
6717         }
6718
6719         save_set.crtc = set->crtc;
6720         save_set.mode = &set->crtc->mode;
6721         save_set.x = set->crtc->x;
6722         save_set.y = set->crtc->y;
6723         save_set.fb = set->crtc->fb;
6724
6725         /* We should be able to check here if the fb has the same properties
6726          * and then just flip_or_move it */
6727         if (set->crtc->fb != set->fb) {
6728                 /* If we have no fb then treat it as a full mode set */
6729                 if (set->crtc->fb == NULL) {
6730                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6731                         mode_changed = true;
6732                 } else if (set->fb == NULL) {
6733                         mode_changed = true;
6734                 } else if (set->fb->depth != set->crtc->fb->depth) {
6735                         mode_changed = true;
6736                 } else if (set->fb->bits_per_pixel !=
6737                            set->crtc->fb->bits_per_pixel) {
6738                         mode_changed = true;
6739                 } else
6740                         fb_changed = true;
6741         }
6742
6743         if (set->x != set->crtc->x || set->y != set->crtc->y)
6744                 fb_changed = true;
6745
6746         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6747                 DRM_DEBUG_KMS("modes are different, full mode set\n");
6748                 drm_mode_debug_printmodeline(&set->crtc->mode);
6749                 drm_mode_debug_printmodeline(set->mode);
6750                 mode_changed = true;
6751         }
6752
6753         /* a) traverse passed in connector list and get encoders for them */
6754         count = 0;
6755         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6756                 struct drm_connector_helper_funcs *connector_funcs =
6757                         connector->helper_private;
6758                 new_encoder = connector->encoder;
6759                 for (ro = 0; ro < set->num_connectors; ro++) {
6760                         if (set->connectors[ro] == connector) {
6761                                 new_encoder = connector_funcs->best_encoder(connector);
6762                                 /* if we can't get an encoder for a connector
6763                                    we are setting now - then fail */
6764                                 if (new_encoder == NULL)
6765                                         /* don't break so fail path works correct */
6766                                         fail = 1;
6767                                 break;
6768                         }
6769                 }
6770
6771                 if (new_encoder != connector->encoder) {
6772                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6773                         mode_changed = true;
6774                         /* If the encoder is reused for another connector, then
6775                          * the appropriate crtc will be set later.
6776                          */
6777                         if (connector->encoder)
6778                                 connector->encoder->crtc = NULL;
6779                         connector->encoder = new_encoder;
6780                 }
6781         }
6782
6783         if (fail) {
6784                 ret = -EINVAL;
6785                 goto fail;
6786         }
6787
6788         count = 0;
6789         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6790                 if (!connector->encoder)
6791                         continue;
6792
6793                 if (connector->encoder->crtc == set->crtc)
6794                         new_crtc = NULL;
6795                 else
6796                         new_crtc = connector->encoder->crtc;
6797
6798                 for (ro = 0; ro < set->num_connectors; ro++) {
6799                         if (set->connectors[ro] == connector)
6800                                 new_crtc = set->crtc;
6801                 }
6802
6803                 /* Make sure the new CRTC will work with the encoder */
6804                 if (new_crtc &&
6805                     !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6806                         ret = -EINVAL;
6807                         goto fail;
6808                 }
6809                 if (new_crtc != connector->encoder->crtc) {
6810                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6811                         mode_changed = true;
6812                         connector->encoder->crtc = new_crtc;
6813                 }
6814                 if (new_crtc) {
6815                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6816                                 connector->base.id, drm_get_connector_name(connector),
6817                                 new_crtc->base.id);
6818                 } else {
6819                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6820                                 connector->base.id, drm_get_connector_name(connector));
6821                 }
6822         }
6823
6824         if (mode_changed) {
6825                 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6826                 if (set->crtc->enabled) {
6827                         DRM_DEBUG_KMS("attempting to set mode from"
6828                                         " userspace\n");
6829                         drm_mode_debug_printmodeline(set->mode);
6830                         old_fb = set->crtc->fb;
6831                         set->crtc->fb = set->fb;
6832                         if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
6833                                                       set->x, set->y,
6834                                                       old_fb)) {
6835                                 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6836                                           set->crtc->base.id);
6837                                 set->crtc->fb = old_fb;
6838                                 ret = -EINVAL;
6839                                 goto fail;
6840                         }
6841                         DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6842                         for (i = 0; i < set->num_connectors; i++) {
6843                                 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6844                                               drm_get_connector_name(set->connectors[i]));
6845                                 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6846                         }
6847                 }
6848                 drm_helper_disable_unused_functions(dev);
6849         } else if (fb_changed) {
6850                 set->crtc->x = set->x;
6851                 set->crtc->y = set->y;
6852
6853                 old_fb = set->crtc->fb;
6854                 if (set->crtc->fb != set->fb)
6855                         set->crtc->fb = set->fb;
6856                 ret = intel_pipe_set_base(set->crtc,
6857                                           set->x, set->y, old_fb);
6858                 if (ret != 0) {
6859                         set->crtc->fb = old_fb;
6860                         goto fail;
6861                 }
6862         }
6863
6864         kfree(save_connectors);
6865         kfree(save_encoders);
6866         kfree(save_crtcs);
6867         return 0;
6868
6869 fail:
6870         /* Restore all previous data. */
6871         count = 0;
6872         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6873                 *crtc = save_crtcs[count++];
6874         }
6875
6876         count = 0;
6877         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6878                 *encoder = save_encoders[count++];
6879         }
6880
6881         count = 0;
6882         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6883                 *connector = save_connectors[count++];
6884         }
6885
6886         /* Try to restore the config */
6887         if (mode_changed &&
6888             !drm_crtc_helper_set_mode(save_set.crtc, save_set.mode, save_set.x,
6889                                       save_set.y, save_set.fb))
6890                 DRM_ERROR("failed to restore config after modeset failure\n");
6891
6892         kfree(save_connectors);
6893         kfree(save_encoders);
6894         kfree(save_crtcs);
6895         return ret;
6896 }
6897
6898 static const struct drm_crtc_funcs intel_crtc_funcs = {
6899         .reset = intel_crtc_reset,
6900         .cursor_set = intel_crtc_cursor_set,
6901         .cursor_move = intel_crtc_cursor_move,
6902         .gamma_set = intel_crtc_gamma_set,
6903         .set_config = intel_crtc_set_config,
6904         .destroy = intel_crtc_destroy,
6905         .page_flip = intel_crtc_page_flip,
6906 };
6907
6908 static void intel_pch_pll_init(struct drm_device *dev)
6909 {
6910         drm_i915_private_t *dev_priv = dev->dev_private;
6911         int i;
6912
6913         if (dev_priv->num_pch_pll == 0) {
6914                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6915                 return;
6916         }
6917
6918         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6919                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6920                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6921                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6922         }
6923 }
6924
6925 static void intel_crtc_init(struct drm_device *dev, int pipe)
6926 {
6927         drm_i915_private_t *dev_priv = dev->dev_private;
6928         struct intel_crtc *intel_crtc;
6929         int i;
6930
6931         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6932         if (intel_crtc == NULL)
6933                 return;
6934
6935         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6936
6937         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6938         for (i = 0; i < 256; i++) {
6939                 intel_crtc->lut_r[i] = i;
6940                 intel_crtc->lut_g[i] = i;
6941                 intel_crtc->lut_b[i] = i;
6942         }
6943
6944         /* Swap pipes & planes for FBC on pre-965 */
6945         intel_crtc->pipe = pipe;
6946         intel_crtc->plane = pipe;
6947         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6948                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6949                 intel_crtc->plane = !pipe;
6950         }
6951
6952         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6953                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6954         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6955         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6956
6957         intel_crtc_reset(&intel_crtc->base);
6958         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6959         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6960
6961         intel_helper_funcs.prepare = dev_priv->display.crtc_disable;
6962         intel_helper_funcs.commit = dev_priv->display.crtc_enable;
6963
6964         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6965 }
6966
6967 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6968                                 struct drm_file *file)
6969 {
6970         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6971         struct drm_mode_object *drmmode_obj;
6972         struct intel_crtc *crtc;
6973
6974         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6975                 return -ENODEV;
6976
6977         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6978                         DRM_MODE_OBJECT_CRTC);
6979
6980         if (!drmmode_obj) {
6981                 DRM_ERROR("no such CRTC id\n");
6982                 return -EINVAL;
6983         }
6984
6985         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6986         pipe_from_crtc_id->pipe = crtc->pipe;
6987
6988         return 0;
6989 }
6990
6991 static int intel_encoder_clones(struct intel_encoder *encoder)
6992 {
6993         struct drm_device *dev = encoder->base.dev;
6994         struct intel_encoder *source_encoder;
6995         int index_mask = 0;
6996         int entry = 0;
6997
6998         list_for_each_entry(source_encoder,
6999                             &dev->mode_config.encoder_list, base.head) {
7000
7001                 if (encoder == source_encoder)
7002                         index_mask |= (1 << entry);
7003
7004                 /* Intel hw has only one MUX where enocoders could be cloned. */
7005                 if (encoder->cloneable && source_encoder->cloneable)
7006                         index_mask |= (1 << entry);
7007
7008                 entry++;
7009         }
7010
7011         return index_mask;
7012 }
7013
7014 static bool has_edp_a(struct drm_device *dev)
7015 {
7016         struct drm_i915_private *dev_priv = dev->dev_private;
7017
7018         if (!IS_MOBILE(dev))
7019                 return false;
7020
7021         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7022                 return false;
7023
7024         if (IS_GEN5(dev) &&
7025             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7026                 return false;
7027
7028         return true;
7029 }
7030
7031 static void intel_setup_outputs(struct drm_device *dev)
7032 {
7033         struct drm_i915_private *dev_priv = dev->dev_private;
7034         struct intel_encoder *encoder;
7035         bool dpd_is_edp = false;
7036         bool has_lvds;
7037
7038         has_lvds = intel_lvds_init(dev);
7039         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7040                 /* disable the panel fitter on everything but LVDS */
7041                 I915_WRITE(PFIT_CONTROL, 0);
7042         }
7043
7044         if (HAS_PCH_SPLIT(dev)) {
7045                 dpd_is_edp = intel_dpd_is_edp(dev);
7046
7047                 if (has_edp_a(dev))
7048                         intel_dp_init(dev, DP_A, PORT_A);
7049
7050                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7051                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7052         }
7053
7054         intel_crt_init(dev);
7055
7056         if (IS_HASWELL(dev)) {
7057                 int found;
7058
7059                 /* Haswell uses DDI functions to detect digital outputs */
7060                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7061                 /* DDI A only supports eDP */
7062                 if (found)
7063                         intel_ddi_init(dev, PORT_A);
7064
7065                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7066                  * register */
7067                 found = I915_READ(SFUSE_STRAP);
7068
7069                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7070                         intel_ddi_init(dev, PORT_B);
7071                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7072                         intel_ddi_init(dev, PORT_C);
7073                 if (found & SFUSE_STRAP_DDID_DETECTED)
7074                         intel_ddi_init(dev, PORT_D);
7075         } else if (HAS_PCH_SPLIT(dev)) {
7076                 int found;
7077
7078                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7079                         /* PCH SDVOB multiplex with HDMIB */
7080                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7081                         if (!found)
7082                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7083                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7084                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7085                 }
7086
7087                 if (I915_READ(HDMIC) & PORT_DETECTED)
7088                         intel_hdmi_init(dev, HDMIC, PORT_C);
7089
7090                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7091                         intel_hdmi_init(dev, HDMID, PORT_D);
7092
7093                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7094                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7095
7096                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7097                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7098         } else if (IS_VALLEYVIEW(dev)) {
7099                 int found;
7100
7101                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7102                         /* SDVOB multiplex with HDMIB */
7103                         found = intel_sdvo_init(dev, SDVOB, true);
7104                         if (!found)
7105                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7106                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7107                                 intel_dp_init(dev, DP_B, PORT_B);
7108                 }
7109
7110                 if (I915_READ(SDVOC) & PORT_DETECTED)
7111                         intel_hdmi_init(dev, SDVOC, PORT_C);
7112
7113                 /* Shares lanes with HDMI on SDVOC */
7114                 if (I915_READ(DP_C) & DP_DETECTED)
7115                         intel_dp_init(dev, DP_C, PORT_C);
7116         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7117                 bool found = false;
7118
7119                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7120                         DRM_DEBUG_KMS("probing SDVOB\n");
7121                         found = intel_sdvo_init(dev, SDVOB, true);
7122                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7123                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7124                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7125                         }
7126
7127                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7128                                 DRM_DEBUG_KMS("probing DP_B\n");
7129                                 intel_dp_init(dev, DP_B, PORT_B);
7130                         }
7131                 }
7132
7133                 /* Before G4X SDVOC doesn't have its own detect register */
7134
7135                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7136                         DRM_DEBUG_KMS("probing SDVOC\n");
7137                         found = intel_sdvo_init(dev, SDVOC, false);
7138                 }
7139
7140                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7141
7142                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7143                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7144                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7145                         }
7146                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7147                                 DRM_DEBUG_KMS("probing DP_C\n");
7148                                 intel_dp_init(dev, DP_C, PORT_C);
7149                         }
7150                 }
7151
7152                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7153                     (I915_READ(DP_D) & DP_DETECTED)) {
7154                         DRM_DEBUG_KMS("probing DP_D\n");
7155                         intel_dp_init(dev, DP_D, PORT_D);
7156                 }
7157         } else if (IS_GEN2(dev))
7158                 intel_dvo_init(dev);
7159
7160         if (SUPPORTS_TV(dev))
7161                 intel_tv_init(dev);
7162
7163         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7164                 encoder->base.possible_crtcs = encoder->crtc_mask;
7165                 encoder->base.possible_clones =
7166                         intel_encoder_clones(encoder);
7167         }
7168
7169         /* disable all the possible outputs/crtcs before entering KMS mode */
7170         drm_helper_disable_unused_functions(dev);
7171
7172         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7173                 ironlake_init_pch_refclk(dev);
7174 }
7175
7176 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7177 {
7178         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7179
7180         drm_framebuffer_cleanup(fb);
7181         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7182
7183         kfree(intel_fb);
7184 }
7185
7186 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7187                                                 struct drm_file *file,
7188                                                 unsigned int *handle)
7189 {
7190         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7191         struct drm_i915_gem_object *obj = intel_fb->obj;
7192
7193         return drm_gem_handle_create(file, &obj->base, handle);
7194 }
7195
7196 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7197         .destroy = intel_user_framebuffer_destroy,
7198         .create_handle = intel_user_framebuffer_create_handle,
7199 };
7200
7201 int intel_framebuffer_init(struct drm_device *dev,
7202                            struct intel_framebuffer *intel_fb,
7203                            struct drm_mode_fb_cmd2 *mode_cmd,
7204                            struct drm_i915_gem_object *obj)
7205 {
7206         int ret;
7207
7208         if (obj->tiling_mode == I915_TILING_Y)
7209                 return -EINVAL;
7210
7211         if (mode_cmd->pitches[0] & 63)
7212                 return -EINVAL;
7213
7214         switch (mode_cmd->pixel_format) {
7215         case DRM_FORMAT_RGB332:
7216         case DRM_FORMAT_RGB565:
7217         case DRM_FORMAT_XRGB8888:
7218         case DRM_FORMAT_XBGR8888:
7219         case DRM_FORMAT_ARGB8888:
7220         case DRM_FORMAT_XRGB2101010:
7221         case DRM_FORMAT_ARGB2101010:
7222                 /* RGB formats are common across chipsets */
7223                 break;
7224         case DRM_FORMAT_YUYV:
7225         case DRM_FORMAT_UYVY:
7226         case DRM_FORMAT_YVYU:
7227         case DRM_FORMAT_VYUY:
7228                 break;
7229         default:
7230                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7231                                 mode_cmd->pixel_format);
7232                 return -EINVAL;
7233         }
7234
7235         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7236         if (ret) {
7237                 DRM_ERROR("framebuffer init failed %d\n", ret);
7238                 return ret;
7239         }
7240
7241         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7242         intel_fb->obj = obj;
7243         return 0;
7244 }
7245
7246 static struct drm_framebuffer *
7247 intel_user_framebuffer_create(struct drm_device *dev,
7248                               struct drm_file *filp,
7249                               struct drm_mode_fb_cmd2 *mode_cmd)
7250 {
7251         struct drm_i915_gem_object *obj;
7252
7253         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7254                                                 mode_cmd->handles[0]));
7255         if (&obj->base == NULL)
7256                 return ERR_PTR(-ENOENT);
7257
7258         return intel_framebuffer_create(dev, mode_cmd, obj);
7259 }
7260
7261 static const struct drm_mode_config_funcs intel_mode_funcs = {
7262         .fb_create = intel_user_framebuffer_create,
7263         .output_poll_changed = intel_fb_output_poll_changed,
7264 };
7265
7266 /* Set up chip specific display functions */
7267 static void intel_init_display(struct drm_device *dev)
7268 {
7269         struct drm_i915_private *dev_priv = dev->dev_private;
7270
7271         /* We always want a DPMS function */
7272         if (HAS_PCH_SPLIT(dev)) {
7273                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7274                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7275                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7276                 dev_priv->display.off = ironlake_crtc_off;
7277                 dev_priv->display.update_plane = ironlake_update_plane;
7278         } else {
7279                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7280                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7281                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7282                 dev_priv->display.off = i9xx_crtc_off;
7283                 dev_priv->display.update_plane = i9xx_update_plane;
7284         }
7285
7286         /* Returns the core display clock speed */
7287         if (IS_VALLEYVIEW(dev))
7288                 dev_priv->display.get_display_clock_speed =
7289                         valleyview_get_display_clock_speed;
7290         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7291                 dev_priv->display.get_display_clock_speed =
7292                         i945_get_display_clock_speed;
7293         else if (IS_I915G(dev))
7294                 dev_priv->display.get_display_clock_speed =
7295                         i915_get_display_clock_speed;
7296         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7297                 dev_priv->display.get_display_clock_speed =
7298                         i9xx_misc_get_display_clock_speed;
7299         else if (IS_I915GM(dev))
7300                 dev_priv->display.get_display_clock_speed =
7301                         i915gm_get_display_clock_speed;
7302         else if (IS_I865G(dev))
7303                 dev_priv->display.get_display_clock_speed =
7304                         i865_get_display_clock_speed;
7305         else if (IS_I85X(dev))
7306                 dev_priv->display.get_display_clock_speed =
7307                         i855_get_display_clock_speed;
7308         else /* 852, 830 */
7309                 dev_priv->display.get_display_clock_speed =
7310                         i830_get_display_clock_speed;
7311
7312         if (HAS_PCH_SPLIT(dev)) {
7313                 if (IS_GEN5(dev)) {
7314                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7315                         dev_priv->display.write_eld = ironlake_write_eld;
7316                 } else if (IS_GEN6(dev)) {
7317                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7318                         dev_priv->display.write_eld = ironlake_write_eld;
7319                 } else if (IS_IVYBRIDGE(dev)) {
7320                         /* FIXME: detect B0+ stepping and use auto training */
7321                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7322                         dev_priv->display.write_eld = ironlake_write_eld;
7323                 } else if (IS_HASWELL(dev)) {
7324                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7325                         dev_priv->display.write_eld = haswell_write_eld;
7326                 } else
7327                         dev_priv->display.update_wm = NULL;
7328         } else if (IS_G4X(dev)) {
7329                 dev_priv->display.write_eld = g4x_write_eld;
7330         }
7331
7332         /* Default just returns -ENODEV to indicate unsupported */
7333         dev_priv->display.queue_flip = intel_default_queue_flip;
7334
7335         switch (INTEL_INFO(dev)->gen) {
7336         case 2:
7337                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7338                 break;
7339
7340         case 3:
7341                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7342                 break;
7343
7344         case 4:
7345         case 5:
7346                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7347                 break;
7348
7349         case 6:
7350                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7351                 break;
7352         case 7:
7353                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7354                 break;
7355         }
7356 }
7357
7358 /*
7359  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7360  * resume, or other times.  This quirk makes sure that's the case for
7361  * affected systems.
7362  */
7363 static void quirk_pipea_force(struct drm_device *dev)
7364 {
7365         struct drm_i915_private *dev_priv = dev->dev_private;
7366
7367         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7368         DRM_INFO("applying pipe a force quirk\n");
7369 }
7370
7371 /*
7372  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7373  */
7374 static void quirk_ssc_force_disable(struct drm_device *dev)
7375 {
7376         struct drm_i915_private *dev_priv = dev->dev_private;
7377         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7378         DRM_INFO("applying lvds SSC disable quirk\n");
7379 }
7380
7381 /*
7382  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7383  * brightness value
7384  */
7385 static void quirk_invert_brightness(struct drm_device *dev)
7386 {
7387         struct drm_i915_private *dev_priv = dev->dev_private;
7388         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7389         DRM_INFO("applying inverted panel brightness quirk\n");
7390 }
7391
7392 struct intel_quirk {
7393         int device;
7394         int subsystem_vendor;
7395         int subsystem_device;
7396         void (*hook)(struct drm_device *dev);
7397 };
7398
7399 static struct intel_quirk intel_quirks[] = {
7400         /* HP Mini needs pipe A force quirk (LP: #322104) */
7401         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7402
7403         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7404         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7405
7406         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7407         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7408
7409         /* 855 & before need to leave pipe A & dpll A up */
7410         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7411         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7412         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7413
7414         /* Lenovo U160 cannot use SSC on LVDS */
7415         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7416
7417         /* Sony Vaio Y cannot use SSC on LVDS */
7418         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7419
7420         /* Acer Aspire 5734Z must invert backlight brightness */
7421         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7422 };
7423
7424 static void intel_init_quirks(struct drm_device *dev)
7425 {
7426         struct pci_dev *d = dev->pdev;
7427         int i;
7428
7429         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7430                 struct intel_quirk *q = &intel_quirks[i];
7431
7432                 if (d->device == q->device &&
7433                     (d->subsystem_vendor == q->subsystem_vendor ||
7434                      q->subsystem_vendor == PCI_ANY_ID) &&
7435                     (d->subsystem_device == q->subsystem_device ||
7436                      q->subsystem_device == PCI_ANY_ID))
7437                         q->hook(dev);
7438         }
7439 }
7440
7441 /* Disable the VGA plane that we never use */
7442 static void i915_disable_vga(struct drm_device *dev)
7443 {
7444         struct drm_i915_private *dev_priv = dev->dev_private;
7445         u8 sr1;
7446         u32 vga_reg;
7447
7448         if (HAS_PCH_SPLIT(dev))
7449                 vga_reg = CPU_VGACNTRL;
7450         else
7451                 vga_reg = VGACNTRL;
7452
7453         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7454         outb(SR01, VGA_SR_INDEX);
7455         sr1 = inb(VGA_SR_DATA);
7456         outb(sr1 | 1<<5, VGA_SR_DATA);
7457         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7458         udelay(300);
7459
7460         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7461         POSTING_READ(vga_reg);
7462 }
7463
7464 void intel_modeset_init_hw(struct drm_device *dev)
7465 {
7466         /* We attempt to init the necessary power wells early in the initialization
7467          * time, so the subsystems that expect power to be enabled can work.
7468          */
7469         intel_init_power_wells(dev);
7470
7471         intel_prepare_ddi(dev);
7472
7473         intel_init_clock_gating(dev);
7474
7475         mutex_lock(&dev->struct_mutex);
7476         intel_enable_gt_powersave(dev);
7477         mutex_unlock(&dev->struct_mutex);
7478 }
7479
7480 void intel_modeset_init(struct drm_device *dev)
7481 {
7482         struct drm_i915_private *dev_priv = dev->dev_private;
7483         int i, ret;
7484
7485         drm_mode_config_init(dev);
7486
7487         dev->mode_config.min_width = 0;
7488         dev->mode_config.min_height = 0;
7489
7490         dev->mode_config.preferred_depth = 24;
7491         dev->mode_config.prefer_shadow = 1;
7492
7493         dev->mode_config.funcs = &intel_mode_funcs;
7494
7495         intel_init_quirks(dev);
7496
7497         intel_init_pm(dev);
7498
7499         intel_init_display(dev);
7500
7501         if (IS_GEN2(dev)) {
7502                 dev->mode_config.max_width = 2048;
7503                 dev->mode_config.max_height = 2048;
7504         } else if (IS_GEN3(dev)) {
7505                 dev->mode_config.max_width = 4096;
7506                 dev->mode_config.max_height = 4096;
7507         } else {
7508                 dev->mode_config.max_width = 8192;
7509                 dev->mode_config.max_height = 8192;
7510         }
7511         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7512
7513         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7514                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7515
7516         for (i = 0; i < dev_priv->num_pipe; i++) {
7517                 intel_crtc_init(dev, i);
7518                 ret = intel_plane_init(dev, i);
7519                 if (ret)
7520                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7521         }
7522
7523         intel_pch_pll_init(dev);
7524
7525         /* Just disable it once at startup */
7526         i915_disable_vga(dev);
7527         intel_setup_outputs(dev);
7528 }
7529
7530 void intel_modeset_gem_init(struct drm_device *dev)
7531 {
7532         intel_modeset_init_hw(dev);
7533
7534         intel_setup_overlay(dev);
7535 }
7536
7537 void intel_modeset_cleanup(struct drm_device *dev)
7538 {
7539         struct drm_i915_private *dev_priv = dev->dev_private;
7540         struct drm_crtc *crtc;
7541         struct intel_crtc *intel_crtc;
7542
7543         drm_kms_helper_poll_fini(dev);
7544         mutex_lock(&dev->struct_mutex);
7545
7546         intel_unregister_dsm_handler();
7547
7548
7549         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7550                 /* Skip inactive CRTCs */
7551                 if (!crtc->fb)
7552                         continue;
7553
7554                 intel_crtc = to_intel_crtc(crtc);
7555                 intel_increase_pllclock(crtc);
7556         }
7557
7558         intel_disable_fbc(dev);
7559
7560         intel_disable_gt_powersave(dev);
7561
7562         ironlake_teardown_rc6(dev);
7563
7564         if (IS_VALLEYVIEW(dev))
7565                 vlv_init_dpio(dev);
7566
7567         mutex_unlock(&dev->struct_mutex);
7568
7569         /* Disable the irq before mode object teardown, for the irq might
7570          * enqueue unpin/hotplug work. */
7571         drm_irq_uninstall(dev);
7572         cancel_work_sync(&dev_priv->hotplug_work);
7573         cancel_work_sync(&dev_priv->rps.work);
7574
7575         /* flush any delayed tasks or pending work */
7576         flush_scheduled_work();
7577
7578         drm_mode_config_cleanup(dev);
7579 }
7580
7581 /*
7582  * Return which encoder is currently attached for connector.
7583  */
7584 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7585 {
7586         return &intel_attached_encoder(connector)->base;
7587 }
7588
7589 void intel_connector_attach_encoder(struct intel_connector *connector,
7590                                     struct intel_encoder *encoder)
7591 {
7592         connector->encoder = encoder;
7593         drm_mode_connector_attach_encoder(&connector->base,
7594                                           &encoder->base);
7595 }
7596
7597 /*
7598  * set vga decode state - true == enable VGA decode
7599  */
7600 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7601 {
7602         struct drm_i915_private *dev_priv = dev->dev_private;
7603         u16 gmch_ctrl;
7604
7605         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7606         if (state)
7607                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7608         else
7609                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7610         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7611         return 0;
7612 }
7613
7614 #ifdef CONFIG_DEBUG_FS
7615 #include <linux/seq_file.h>
7616
7617 struct intel_display_error_state {
7618         struct intel_cursor_error_state {
7619                 u32 control;
7620                 u32 position;
7621                 u32 base;
7622                 u32 size;
7623         } cursor[I915_MAX_PIPES];
7624
7625         struct intel_pipe_error_state {
7626                 u32 conf;
7627                 u32 source;
7628
7629                 u32 htotal;
7630                 u32 hblank;
7631                 u32 hsync;
7632                 u32 vtotal;
7633                 u32 vblank;
7634                 u32 vsync;
7635         } pipe[I915_MAX_PIPES];
7636
7637         struct intel_plane_error_state {
7638                 u32 control;
7639                 u32 stride;
7640                 u32 size;
7641                 u32 pos;
7642                 u32 addr;
7643                 u32 surface;
7644                 u32 tile_offset;
7645         } plane[I915_MAX_PIPES];
7646 };
7647
7648 struct intel_display_error_state *
7649 intel_display_capture_error_state(struct drm_device *dev)
7650 {
7651         drm_i915_private_t *dev_priv = dev->dev_private;
7652         struct intel_display_error_state *error;
7653         int i;
7654
7655         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7656         if (error == NULL)
7657                 return NULL;
7658
7659         for_each_pipe(i) {
7660                 error->cursor[i].control = I915_READ(CURCNTR(i));
7661                 error->cursor[i].position = I915_READ(CURPOS(i));
7662                 error->cursor[i].base = I915_READ(CURBASE(i));
7663
7664                 error->plane[i].control = I915_READ(DSPCNTR(i));
7665                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7666                 error->plane[i].size = I915_READ(DSPSIZE(i));
7667                 error->plane[i].pos = I915_READ(DSPPOS(i));
7668                 error->plane[i].addr = I915_READ(DSPADDR(i));
7669                 if (INTEL_INFO(dev)->gen >= 4) {
7670                         error->plane[i].surface = I915_READ(DSPSURF(i));
7671                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7672                 }
7673
7674                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7675                 error->pipe[i].source = I915_READ(PIPESRC(i));
7676                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7677                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7678                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7679                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7680                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7681                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7682         }
7683
7684         return error;
7685 }
7686
7687 void
7688 intel_display_print_error_state(struct seq_file *m,
7689                                 struct drm_device *dev,
7690                                 struct intel_display_error_state *error)
7691 {
7692         drm_i915_private_t *dev_priv = dev->dev_private;
7693         int i;
7694
7695         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7696         for_each_pipe(i) {
7697                 seq_printf(m, "Pipe [%d]:\n", i);
7698                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7699                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7700                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7701                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7702                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7703                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7704                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7705                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7706
7707                 seq_printf(m, "Plane [%d]:\n", i);
7708                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7709                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7710                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7711                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7712                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7713                 if (INTEL_INFO(dev)->gen >= 4) {
7714                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7715                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7716                 }
7717
7718                 seq_printf(m, "Cursor [%d]:\n", i);
7719                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7720                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7721                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7722         }
7723 }
7724 #endif