Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 }
1842
1843 /**
1844  * intel_enable_plane - enable a display plane on a given pipe
1845  * @dev_priv: i915 private structure
1846  * @plane: plane to enable
1847  * @pipe: pipe being fed
1848  *
1849  * Enable @plane on @pipe, making sure that @pipe is running first.
1850  */
1851 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane, enum pipe pipe)
1853 {
1854         int reg;
1855         u32 val;
1856
1857         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858         assert_pipe_enabled(dev_priv, pipe);
1859
1860         reg = DSPCNTR(plane);
1861         val = I915_READ(reg);
1862         if (val & DISPLAY_PLANE_ENABLE)
1863                 return;
1864
1865         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1866         intel_flush_display_plane(dev_priv, plane);
1867         intel_wait_for_vblank(dev_priv->dev, pipe);
1868 }
1869
1870 /**
1871  * intel_disable_plane - disable a display plane
1872  * @dev_priv: i915 private structure
1873  * @plane: plane to disable
1874  * @pipe: pipe consuming the data
1875  *
1876  * Disable @plane; should be an independent operation.
1877  */
1878 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879                                 enum plane plane, enum pipe pipe)
1880 {
1881         int reg;
1882         u32 val;
1883
1884         reg = DSPCNTR(plane);
1885         val = I915_READ(reg);
1886         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887                 return;
1888
1889         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1890         intel_flush_display_plane(dev_priv, plane);
1891         intel_wait_for_vblank(dev_priv->dev, pipe);
1892 }
1893
1894 int
1895 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1896                            struct drm_i915_gem_object *obj,
1897                            struct intel_ring_buffer *pipelined)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         u32 alignment;
1901         int ret;
1902
1903         switch (obj->tiling_mode) {
1904         case I915_TILING_NONE:
1905                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906                         alignment = 128 * 1024;
1907                 else if (INTEL_INFO(dev)->gen >= 4)
1908                         alignment = 4 * 1024;
1909                 else
1910                         alignment = 64 * 1024;
1911                 break;
1912         case I915_TILING_X:
1913                 /* pin() will align the object as required by fence */
1914                 alignment = 0;
1915                 break;
1916         case I915_TILING_Y:
1917                 /* FIXME: Is this true? */
1918                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919                 return -EINVAL;
1920         default:
1921                 BUG();
1922         }
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959                                                         unsigned int bpp,
1960                                                         unsigned int pitch)
1961 {
1962         int tile_rows, tiles;
1963
1964         tile_rows = *y / 8;
1965         *y %= 8;
1966         tiles = *x / (512/bpp);
1967         *x %= 512/bpp;
1968
1969         return tile_rows * pitch * 8 + tiles * 4096;
1970 }
1971
1972 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973                              int x, int y)
1974 {
1975         struct drm_device *dev = crtc->dev;
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978         struct intel_framebuffer *intel_fb;
1979         struct drm_i915_gem_object *obj;
1980         int plane = intel_crtc->plane;
1981         unsigned long linear_offset;
1982         u32 dspcntr;
1983         u32 reg;
1984
1985         switch (plane) {
1986         case 0:
1987         case 1:
1988                 break;
1989         default:
1990                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991                 return -EINVAL;
1992         }
1993
1994         intel_fb = to_intel_framebuffer(fb);
1995         obj = intel_fb->obj;
1996
1997         reg = DSPCNTR(plane);
1998         dspcntr = I915_READ(reg);
1999         /* Mask out pixel format bits in case we change it */
2000         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001         switch (fb->bits_per_pixel) {
2002         case 8:
2003                 dspcntr |= DISPPLANE_8BPP;
2004                 break;
2005         case 16:
2006                 if (fb->depth == 15)
2007                         dspcntr |= DISPPLANE_15_16BPP;
2008                 else
2009                         dspcntr |= DISPPLANE_16BPP;
2010                 break;
2011         case 24:
2012         case 32:
2013                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014                 break;
2015         default:
2016                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2017                 return -EINVAL;
2018         }
2019         if (INTEL_INFO(dev)->gen >= 4) {
2020                 if (obj->tiling_mode != I915_TILING_NONE)
2021                         dspcntr |= DISPPLANE_TILED;
2022                 else
2023                         dspcntr &= ~DISPPLANE_TILED;
2024         }
2025
2026         I915_WRITE(reg, dspcntr);
2027
2028         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2029
2030         if (INTEL_INFO(dev)->gen >= 4) {
2031                 intel_crtc->dspaddr_offset =
2032                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033                                                            fb->bits_per_pixel / 8,
2034                                                            fb->pitches[0]);
2035                 linear_offset -= intel_crtc->dspaddr_offset;
2036         } else {
2037                 intel_crtc->dspaddr_offset = linear_offset;
2038         }
2039
2040         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2042         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2046                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2047                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2048         } else
2049                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2050         POSTING_READ(reg);
2051
2052         return 0;
2053 }
2054
2055 static int ironlake_update_plane(struct drm_crtc *crtc,
2056                                  struct drm_framebuffer *fb, int x, int y)
2057 {
2058         struct drm_device *dev = crtc->dev;
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061         struct intel_framebuffer *intel_fb;
2062         struct drm_i915_gem_object *obj;
2063         int plane = intel_crtc->plane;
2064         unsigned long linear_offset;
2065         u32 dspcntr;
2066         u32 reg;
2067
2068         switch (plane) {
2069         case 0:
2070         case 1:
2071         case 2:
2072                 break;
2073         default:
2074                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075                 return -EINVAL;
2076         }
2077
2078         intel_fb = to_intel_framebuffer(fb);
2079         obj = intel_fb->obj;
2080
2081         reg = DSPCNTR(plane);
2082         dspcntr = I915_READ(reg);
2083         /* Mask out pixel format bits in case we change it */
2084         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085         switch (fb->bits_per_pixel) {
2086         case 8:
2087                 dspcntr |= DISPPLANE_8BPP;
2088                 break;
2089         case 16:
2090                 if (fb->depth != 16)
2091                         return -EINVAL;
2092
2093                 dspcntr |= DISPPLANE_16BPP;
2094                 break;
2095         case 24:
2096         case 32:
2097                 if (fb->depth == 24)
2098                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099                 else if (fb->depth == 30)
2100                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101                 else
2102                         return -EINVAL;
2103                 break;
2104         default:
2105                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106                 return -EINVAL;
2107         }
2108
2109         if (obj->tiling_mode != I915_TILING_NONE)
2110                 dspcntr |= DISPPLANE_TILED;
2111         else
2112                 dspcntr &= ~DISPPLANE_TILED;
2113
2114         /* must disable */
2115         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117         I915_WRITE(reg, dspcntr);
2118
2119         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2120         intel_crtc->dspaddr_offset =
2121                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122                                                    fb->bits_per_pixel / 8,
2123                                                    fb->pitches[0]);
2124         linear_offset -= intel_crtc->dspaddr_offset;
2125
2126         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2128         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2129         I915_MODIFY_DISPBASE(DSPSURF(plane),
2130                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2131         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2132         I915_WRITE(DSPLINOFF(plane), linear_offset);
2133         POSTING_READ(reg);
2134
2135         return 0;
2136 }
2137
2138 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2139 static int
2140 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141                            int x, int y, enum mode_set_atomic state)
2142 {
2143         struct drm_device *dev = crtc->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146         if (dev_priv->display.disable_fbc)
2147                 dev_priv->display.disable_fbc(dev);
2148         intel_increase_pllclock(crtc);
2149
2150         return dev_priv->display.update_plane(crtc, fb, x, y);
2151 }
2152
2153 static int
2154 intel_finish_fb(struct drm_framebuffer *old_fb)
2155 {
2156         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158         bool was_interruptible = dev_priv->mm.interruptible;
2159         int ret;
2160
2161         wait_event(dev_priv->pending_flip_queue,
2162                    atomic_read(&dev_priv->mm.wedged) ||
2163                    atomic_read(&obj->pending_flip) == 0);
2164
2165         /* Big Hammer, we also need to ensure that any pending
2166          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167          * current scanout is retired before unpinning the old
2168          * framebuffer.
2169          *
2170          * This should only fail upon a hung GPU, in which case we
2171          * can safely continue.
2172          */
2173         dev_priv->mm.interruptible = false;
2174         ret = i915_gem_object_finish_gpu(obj);
2175         dev_priv->mm.interruptible = was_interruptible;
2176
2177         return ret;
2178 }
2179
2180 static int
2181 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2182                     struct drm_framebuffer *fb)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188         struct drm_framebuffer *old_fb;
2189         int ret;
2190
2191         /* no fb bound */
2192         if (!fb) {
2193                 DRM_ERROR("No FB bound\n");
2194                 return 0;
2195         }
2196
2197         if(intel_crtc->plane > dev_priv->num_pipe) {
2198                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199                                 intel_crtc->plane,
2200                                 dev_priv->num_pipe);
2201                 return -EINVAL;
2202         }
2203
2204         mutex_lock(&dev->struct_mutex);
2205         ret = intel_pin_and_fence_fb_obj(dev,
2206                                          to_intel_framebuffer(fb)->obj,
2207                                          NULL);
2208         if (ret != 0) {
2209                 mutex_unlock(&dev->struct_mutex);
2210                 DRM_ERROR("pin & fence failed\n");
2211                 return ret;
2212         }
2213
2214         if (crtc->fb)
2215                 intel_finish_fb(crtc->fb);
2216
2217         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2218         if (ret) {
2219                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2220                 mutex_unlock(&dev->struct_mutex);
2221                 DRM_ERROR("failed to update base address\n");
2222                 return ret;
2223         }
2224
2225         old_fb = crtc->fb;
2226         crtc->fb = fb;
2227         crtc->x = x;
2228         crtc->y = y;
2229
2230         if (old_fb) {
2231                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2232                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2233         }
2234
2235         intel_update_fbc(dev);
2236         mutex_unlock(&dev->struct_mutex);
2237
2238         if (!dev->primary->master)
2239                 return 0;
2240
2241         master_priv = dev->primary->master->driver_priv;
2242         if (!master_priv->sarea_priv)
2243                 return 0;
2244
2245         if (intel_crtc->pipe) {
2246                 master_priv->sarea_priv->pipeB_x = x;
2247                 master_priv->sarea_priv->pipeB_y = y;
2248         } else {
2249                 master_priv->sarea_priv->pipeA_x = x;
2250                 master_priv->sarea_priv->pipeA_y = y;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2257 {
2258         struct drm_device *dev = crtc->dev;
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         u32 dpa_ctl;
2261
2262         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2263         dpa_ctl = I915_READ(DP_A);
2264         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266         if (clock < 200000) {
2267                 u32 temp;
2268                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269                 /* workaround for 160Mhz:
2270                    1) program 0x4600c bits 15:0 = 0x8124
2271                    2) program 0x46010 bit 0 = 1
2272                    3) program 0x46034 bit 24 = 1
2273                    4) program 0x64000 bit 14 = 1
2274                    */
2275                 temp = I915_READ(0x4600c);
2276                 temp &= 0xffff0000;
2277                 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279                 temp = I915_READ(0x46010);
2280                 I915_WRITE(0x46010, temp | 1);
2281
2282                 temp = I915_READ(0x46034);
2283                 I915_WRITE(0x46034, temp | (1 << 24));
2284         } else {
2285                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286         }
2287         I915_WRITE(DP_A, dpa_ctl);
2288
2289         POSTING_READ(DP_A);
2290         udelay(500);
2291 }
2292
2293 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         int pipe = intel_crtc->pipe;
2299         u32 reg, temp;
2300
2301         /* enable normal train */
2302         reg = FDI_TX_CTL(pipe);
2303         temp = I915_READ(reg);
2304         if (IS_IVYBRIDGE(dev)) {
2305                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2307         } else {
2308                 temp &= ~FDI_LINK_TRAIN_NONE;
2309                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2310         }
2311         I915_WRITE(reg, temp);
2312
2313         reg = FDI_RX_CTL(pipe);
2314         temp = I915_READ(reg);
2315         if (HAS_PCH_CPT(dev)) {
2316                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318         } else {
2319                 temp &= ~FDI_LINK_TRAIN_NONE;
2320                 temp |= FDI_LINK_TRAIN_NONE;
2321         }
2322         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324         /* wait one idle pattern time */
2325         POSTING_READ(reg);
2326         udelay(1000);
2327
2328         /* IVB wants error correction enabled */
2329         if (IS_IVYBRIDGE(dev))
2330                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331                            FDI_FE_ERRC_ENABLE);
2332 }
2333
2334 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339         flags |= FDI_PHASE_SYNC_OVR(pipe);
2340         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341         flags |= FDI_PHASE_SYNC_EN(pipe);
2342         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343         POSTING_READ(SOUTH_CHICKEN1);
2344 }
2345
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348 {
2349         struct drm_device *dev = crtc->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352         int pipe = intel_crtc->pipe;
2353         int plane = intel_crtc->plane;
2354         u32 reg, temp, tries;
2355
2356         /* FDI needs bits from pipe & plane first */
2357         assert_pipe_enabled(dev_priv, pipe);
2358         assert_plane_enabled(dev_priv, plane);
2359
2360         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361            for train result */
2362         reg = FDI_RX_IMR(pipe);
2363         temp = I915_READ(reg);
2364         temp &= ~FDI_RX_SYMBOL_LOCK;
2365         temp &= ~FDI_RX_BIT_LOCK;
2366         I915_WRITE(reg, temp);
2367         I915_READ(reg);
2368         udelay(150);
2369
2370         /* enable CPU FDI TX and PCH FDI RX */
2371         reg = FDI_TX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~(7 << 19);
2374         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2375         temp &= ~FDI_LINK_TRAIN_NONE;
2376         temp |= FDI_LINK_TRAIN_PATTERN_1;
2377         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2378
2379         reg = FDI_RX_CTL(pipe);
2380         temp = I915_READ(reg);
2381         temp &= ~FDI_LINK_TRAIN_NONE;
2382         temp |= FDI_LINK_TRAIN_PATTERN_1;
2383         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385         POSTING_READ(reg);
2386         udelay(150);
2387
2388         /* Ironlake workaround, enable clock pointer after FDI enable*/
2389         if (HAS_PCH_IBX(dev)) {
2390                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392                            FDI_RX_PHASE_SYNC_POINTER_EN);
2393         }
2394
2395         reg = FDI_RX_IIR(pipe);
2396         for (tries = 0; tries < 5; tries++) {
2397                 temp = I915_READ(reg);
2398                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400                 if ((temp & FDI_RX_BIT_LOCK)) {
2401                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2402                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2403                         break;
2404                 }
2405         }
2406         if (tries == 5)
2407                 DRM_ERROR("FDI train 1 fail!\n");
2408
2409         /* Train 2 */
2410         reg = FDI_TX_CTL(pipe);
2411         temp = I915_READ(reg);
2412         temp &= ~FDI_LINK_TRAIN_NONE;
2413         temp |= FDI_LINK_TRAIN_PATTERN_2;
2414         I915_WRITE(reg, temp);
2415
2416         reg = FDI_RX_CTL(pipe);
2417         temp = I915_READ(reg);
2418         temp &= ~FDI_LINK_TRAIN_NONE;
2419         temp |= FDI_LINK_TRAIN_PATTERN_2;
2420         I915_WRITE(reg, temp);
2421
2422         POSTING_READ(reg);
2423         udelay(150);
2424
2425         reg = FDI_RX_IIR(pipe);
2426         for (tries = 0; tries < 5; tries++) {
2427                 temp = I915_READ(reg);
2428                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430                 if (temp & FDI_RX_SYMBOL_LOCK) {
2431                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2433                         break;
2434                 }
2435         }
2436         if (tries == 5)
2437                 DRM_ERROR("FDI train 2 fail!\n");
2438
2439         DRM_DEBUG_KMS("FDI train done\n");
2440
2441 }
2442
2443 static const int snb_b_fdi_train_param[] = {
2444         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448 };
2449
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453         struct drm_device *dev = crtc->dev;
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456         int pipe = intel_crtc->pipe;
2457         u32 reg, temp, i, retry;
2458
2459         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460            for train result */
2461         reg = FDI_RX_IMR(pipe);
2462         temp = I915_READ(reg);
2463         temp &= ~FDI_RX_SYMBOL_LOCK;
2464         temp &= ~FDI_RX_BIT_LOCK;
2465         I915_WRITE(reg, temp);
2466
2467         POSTING_READ(reg);
2468         udelay(150);
2469
2470         /* enable CPU FDI TX and PCH FDI RX */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~(7 << 19);
2474         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475         temp &= ~FDI_LINK_TRAIN_NONE;
2476         temp |= FDI_LINK_TRAIN_PATTERN_1;
2477         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478         /* SNB-B */
2479         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2480         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481
2482         I915_WRITE(FDI_RX_MISC(pipe),
2483                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2484
2485         reg = FDI_RX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         if (HAS_PCH_CPT(dev)) {
2488                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2489                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2490         } else {
2491                 temp &= ~FDI_LINK_TRAIN_NONE;
2492                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         }
2494         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2495
2496         POSTING_READ(reg);
2497         udelay(150);
2498
2499         if (HAS_PCH_CPT(dev))
2500                 cpt_phase_pointer_enable(dev, pipe);
2501
2502         for (i = 0; i < 4; i++) {
2503                 reg = FDI_TX_CTL(pipe);
2504                 temp = I915_READ(reg);
2505                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2506                 temp |= snb_b_fdi_train_param[i];
2507                 I915_WRITE(reg, temp);
2508
2509                 POSTING_READ(reg);
2510                 udelay(500);
2511
2512                 for (retry = 0; retry < 5; retry++) {
2513                         reg = FDI_RX_IIR(pipe);
2514                         temp = I915_READ(reg);
2515                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2516                         if (temp & FDI_RX_BIT_LOCK) {
2517                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2518                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519                                 break;
2520                         }
2521                         udelay(50);
2522                 }
2523                 if (retry < 5)
2524                         break;
2525         }
2526         if (i == 4)
2527                 DRM_ERROR("FDI train 1 fail!\n");
2528
2529         /* Train 2 */
2530         reg = FDI_TX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_LINK_TRAIN_NONE;
2533         temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         if (IS_GEN6(dev)) {
2535                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536                 /* SNB-B */
2537                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2538         }
2539         I915_WRITE(reg, temp);
2540
2541         reg = FDI_RX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         if (HAS_PCH_CPT(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2545                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2546         } else {
2547                 temp &= ~FDI_LINK_TRAIN_NONE;
2548                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2549         }
2550         I915_WRITE(reg, temp);
2551
2552         POSTING_READ(reg);
2553         udelay(150);
2554
2555         for (i = 0; i < 4; i++) {
2556                 reg = FDI_TX_CTL(pipe);
2557                 temp = I915_READ(reg);
2558                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559                 temp |= snb_b_fdi_train_param[i];
2560                 I915_WRITE(reg, temp);
2561
2562                 POSTING_READ(reg);
2563                 udelay(500);
2564
2565                 for (retry = 0; retry < 5; retry++) {
2566                         reg = FDI_RX_IIR(pipe);
2567                         temp = I915_READ(reg);
2568                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569                         if (temp & FDI_RX_SYMBOL_LOCK) {
2570                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2571                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2572                                 break;
2573                         }
2574                         udelay(50);
2575                 }
2576                 if (retry < 5)
2577                         break;
2578         }
2579         if (i == 4)
2580                 DRM_ERROR("FDI train 2 fail!\n");
2581
2582         DRM_DEBUG_KMS("FDI train done.\n");
2583 }
2584
2585 /* Manual link training for Ivy Bridge A0 parts */
2586 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2587 {
2588         struct drm_device *dev = crtc->dev;
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591         int pipe = intel_crtc->pipe;
2592         u32 reg, temp, i;
2593
2594         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2595            for train result */
2596         reg = FDI_RX_IMR(pipe);
2597         temp = I915_READ(reg);
2598         temp &= ~FDI_RX_SYMBOL_LOCK;
2599         temp &= ~FDI_RX_BIT_LOCK;
2600         I915_WRITE(reg, temp);
2601
2602         POSTING_READ(reg);
2603         udelay(150);
2604
2605         /* enable CPU FDI TX and PCH FDI RX */
2606         reg = FDI_TX_CTL(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~(7 << 19);
2609         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2610         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2611         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2612         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614         temp |= FDI_COMPOSITE_SYNC;
2615         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2616
2617         I915_WRITE(FDI_RX_MISC(pipe),
2618                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2619
2620         reg = FDI_RX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_LINK_TRAIN_AUTO;
2623         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2624         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2625         temp |= FDI_COMPOSITE_SYNC;
2626         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2627
2628         POSTING_READ(reg);
2629         udelay(150);
2630
2631         if (HAS_PCH_CPT(dev))
2632                 cpt_phase_pointer_enable(dev, pipe);
2633
2634         for (i = 0; i < 4; i++) {
2635                 reg = FDI_TX_CTL(pipe);
2636                 temp = I915_READ(reg);
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 temp |= snb_b_fdi_train_param[i];
2639                 I915_WRITE(reg, temp);
2640
2641                 POSTING_READ(reg);
2642                 udelay(500);
2643
2644                 reg = FDI_RX_IIR(pipe);
2645                 temp = I915_READ(reg);
2646                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2647
2648                 if (temp & FDI_RX_BIT_LOCK ||
2649                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2650                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2651                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2652                         break;
2653                 }
2654         }
2655         if (i == 4)
2656                 DRM_ERROR("FDI train 1 fail!\n");
2657
2658         /* Train 2 */
2659         reg = FDI_TX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2662         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2663         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2665         I915_WRITE(reg, temp);
2666
2667         reg = FDI_RX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2671         I915_WRITE(reg, temp);
2672
2673         POSTING_READ(reg);
2674         udelay(150);
2675
2676         for (i = 0; i < 4; i++) {
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2680                 temp |= snb_b_fdi_train_param[i];
2681                 I915_WRITE(reg, temp);
2682
2683                 POSTING_READ(reg);
2684                 udelay(500);
2685
2686                 reg = FDI_RX_IIR(pipe);
2687                 temp = I915_READ(reg);
2688                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689
2690                 if (temp & FDI_RX_SYMBOL_LOCK) {
2691                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2692                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2693                         break;
2694                 }
2695         }
2696         if (i == 4)
2697                 DRM_ERROR("FDI train 2 fail!\n");
2698
2699         DRM_DEBUG_KMS("FDI train done.\n");
2700 }
2701
2702 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2703 {
2704         struct drm_device *dev = intel_crtc->base.dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         int pipe = intel_crtc->pipe;
2707         u32 reg, temp;
2708
2709
2710         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~((0x7 << 19) | (0x7 << 16));
2714         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2715         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2716         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2717
2718         POSTING_READ(reg);
2719         udelay(200);
2720
2721         /* Switch from Rawclk to PCDclk */
2722         temp = I915_READ(reg);
2723         I915_WRITE(reg, temp | FDI_PCDCLK);
2724
2725         POSTING_READ(reg);
2726         udelay(200);
2727
2728         /* On Haswell, the PLL configuration for ports and pipes is handled
2729          * separately, as part of DDI setup */
2730         if (!IS_HASWELL(dev)) {
2731                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2732                 reg = FDI_TX_CTL(pipe);
2733                 temp = I915_READ(reg);
2734                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2735                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2736
2737                         POSTING_READ(reg);
2738                         udelay(100);
2739                 }
2740         }
2741 }
2742
2743 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2744 {
2745         struct drm_device *dev = intel_crtc->base.dev;
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         int pipe = intel_crtc->pipe;
2748         u32 reg, temp;
2749
2750         /* Switch from PCDclk to Rawclk */
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2754
2755         /* Disable CPU FDI TX PLL */
2756         reg = FDI_TX_CTL(pipe);
2757         temp = I915_READ(reg);
2758         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2759
2760         POSTING_READ(reg);
2761         udelay(100);
2762
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2766
2767         /* Wait for the clocks to turn off. */
2768         POSTING_READ(reg);
2769         udelay(100);
2770 }
2771
2772 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         u32 flags = I915_READ(SOUTH_CHICKEN1);
2776
2777         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2778         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2779         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2780         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2781         POSTING_READ(SOUTH_CHICKEN1);
2782 }
2783 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2784 {
2785         struct drm_device *dev = crtc->dev;
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788         int pipe = intel_crtc->pipe;
2789         u32 reg, temp;
2790
2791         /* disable CPU FDI tx and PCH FDI rx */
2792         reg = FDI_TX_CTL(pipe);
2793         temp = I915_READ(reg);
2794         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795         POSTING_READ(reg);
2796
2797         reg = FDI_RX_CTL(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~(0x7 << 16);
2800         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2801         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2802
2803         POSTING_READ(reg);
2804         udelay(100);
2805
2806         /* Ironlake workaround, disable clock pointer after downing FDI */
2807         if (HAS_PCH_IBX(dev)) {
2808                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2809                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2810                            I915_READ(FDI_RX_CHICKEN(pipe) &
2811                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2812         } else if (HAS_PCH_CPT(dev)) {
2813                 cpt_phase_pointer_disable(dev, pipe);
2814         }
2815
2816         /* still set train pattern 1 */
2817         reg = FDI_TX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         temp &= ~FDI_LINK_TRAIN_NONE;
2820         temp |= FDI_LINK_TRAIN_PATTERN_1;
2821         I915_WRITE(reg, temp);
2822
2823         reg = FDI_RX_CTL(pipe);
2824         temp = I915_READ(reg);
2825         if (HAS_PCH_CPT(dev)) {
2826                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2827                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2828         } else {
2829                 temp &= ~FDI_LINK_TRAIN_NONE;
2830                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2831         }
2832         /* BPC in FDI rx is consistent with that in PIPECONF */
2833         temp &= ~(0x07 << 16);
2834         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2835         I915_WRITE(reg, temp);
2836
2837         POSTING_READ(reg);
2838         udelay(100);
2839 }
2840
2841 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2842 {
2843         struct drm_device *dev = crtc->dev;
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         unsigned long flags;
2846         bool pending;
2847
2848         if (atomic_read(&dev_priv->mm.wedged))
2849                 return false;
2850
2851         spin_lock_irqsave(&dev->event_lock, flags);
2852         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2853         spin_unlock_irqrestore(&dev->event_lock, flags);
2854
2855         return pending;
2856 }
2857
2858 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859 {
2860         struct drm_device *dev = crtc->dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862
2863         if (crtc->fb == NULL)
2864                 return;
2865
2866         wait_event(dev_priv->pending_flip_queue,
2867                    !intel_crtc_has_pending_flip(crtc));
2868
2869         mutex_lock(&dev->struct_mutex);
2870         intel_finish_fb(crtc->fb);
2871         mutex_unlock(&dev->struct_mutex);
2872 }
2873
2874 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct intel_encoder *intel_encoder;
2878
2879         /*
2880          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2881          * must be driven by its own crtc; no sharing is possible.
2882          */
2883         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2884                 switch (intel_encoder->type) {
2885                 case INTEL_OUTPUT_EDP:
2886                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2887                                 return false;
2888                         continue;
2889                 }
2890         }
2891
2892         return true;
2893 }
2894
2895 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2896 {
2897         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2898 }
2899
2900 /* Program iCLKIP clock to the desired frequency */
2901 static void lpt_program_iclkip(struct drm_crtc *crtc)
2902 {
2903         struct drm_device *dev = crtc->dev;
2904         struct drm_i915_private *dev_priv = dev->dev_private;
2905         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2906         u32 temp;
2907
2908         /* It is necessary to ungate the pixclk gate prior to programming
2909          * the divisors, and gate it back when it is done.
2910          */
2911         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2912
2913         /* Disable SSCCTL */
2914         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2915                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2916                                         SBI_SSCCTL_DISABLE);
2917
2918         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2919         if (crtc->mode.clock == 20000) {
2920                 auxdiv = 1;
2921                 divsel = 0x41;
2922                 phaseinc = 0x20;
2923         } else {
2924                 /* The iCLK virtual clock root frequency is in MHz,
2925                  * but the crtc->mode.clock in in KHz. To get the divisors,
2926                  * it is necessary to divide one by another, so we
2927                  * convert the virtual clock precision to KHz here for higher
2928                  * precision.
2929                  */
2930                 u32 iclk_virtual_root_freq = 172800 * 1000;
2931                 u32 iclk_pi_range = 64;
2932                 u32 desired_divisor, msb_divisor_value, pi_value;
2933
2934                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2935                 msb_divisor_value = desired_divisor / iclk_pi_range;
2936                 pi_value = desired_divisor % iclk_pi_range;
2937
2938                 auxdiv = 0;
2939                 divsel = msb_divisor_value - 2;
2940                 phaseinc = pi_value;
2941         }
2942
2943         /* This should not happen with any sane values */
2944         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2945                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2946         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2947                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2948
2949         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2950                         crtc->mode.clock,
2951                         auxdiv,
2952                         divsel,
2953                         phasedir,
2954                         phaseinc);
2955
2956         /* Program SSCDIVINTPHASE6 */
2957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2964
2965         intel_sbi_write(dev_priv,
2966                         SBI_SSCDIVINTPHASE6,
2967                         temp);
2968
2969         /* Program SSCAUXDIV */
2970         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2971         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2972         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2973         intel_sbi_write(dev_priv,
2974                         SBI_SSCAUXDIV6,
2975                         temp);
2976
2977
2978         /* Enable modulator and associated divider */
2979         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2980         temp &= ~SBI_SSCCTL_DISABLE;
2981         intel_sbi_write(dev_priv,
2982                         SBI_SSCCTL6,
2983                         temp);
2984
2985         /* Wait for initialization time */
2986         udelay(24);
2987
2988         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2989 }
2990
2991 /*
2992  * Enable PCH resources required for PCH ports:
2993  *   - PCH PLLs
2994  *   - FDI training & RX/TX
2995  *   - update transcoder timings
2996  *   - DP transcoding bits
2997  *   - transcoder
2998  */
2999 static void ironlake_pch_enable(struct drm_crtc *crtc)
3000 {
3001         struct drm_device *dev = crtc->dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004         int pipe = intel_crtc->pipe;
3005         u32 reg, temp;
3006
3007         assert_transcoder_disabled(dev_priv, pipe);
3008
3009         /* Write the TU size bits before fdi link training, so that error
3010          * detection works. */
3011         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3012                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3013
3014         /* For PCH output, training FDI link */
3015         dev_priv->display.fdi_link_train(crtc);
3016
3017         /* XXX: pch pll's can be enabled any time before we enable the PCH
3018          * transcoder, and we actually should do this to not upset any PCH
3019          * transcoder that already use the clock when we share it.
3020          *
3021          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3022          * unconditionally resets the pll - we need that to have the right LVDS
3023          * enable sequence. */
3024         intel_enable_pch_pll(intel_crtc);
3025
3026         if (HAS_PCH_LPT(dev)) {
3027                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3028                 lpt_program_iclkip(crtc);
3029         } else if (HAS_PCH_CPT(dev)) {
3030                 u32 sel;
3031
3032                 temp = I915_READ(PCH_DPLL_SEL);
3033                 switch (pipe) {
3034                 default:
3035                 case 0:
3036                         temp |= TRANSA_DPLL_ENABLE;
3037                         sel = TRANSA_DPLLB_SEL;
3038                         break;
3039                 case 1:
3040                         temp |= TRANSB_DPLL_ENABLE;
3041                         sel = TRANSB_DPLLB_SEL;
3042                         break;
3043                 case 2:
3044                         temp |= TRANSC_DPLL_ENABLE;
3045                         sel = TRANSC_DPLLB_SEL;
3046                         break;
3047                 }
3048                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3049                         temp |= sel;
3050                 else
3051                         temp &= ~sel;
3052                 I915_WRITE(PCH_DPLL_SEL, temp);
3053         }
3054
3055         /* set transcoder timing, panel must allow it */
3056         assert_panel_unlocked(dev_priv, pipe);
3057         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3058         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3059         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3060
3061         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3062         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3063         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3064         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3065
3066         if (!IS_HASWELL(dev))
3067                 intel_fdi_normal_train(crtc);
3068
3069         /* For PCH DP, enable TRANS_DP_CTL */
3070         if (HAS_PCH_CPT(dev) &&
3071             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3072              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3073                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3074                 reg = TRANS_DP_CTL(pipe);
3075                 temp = I915_READ(reg);
3076                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3077                           TRANS_DP_SYNC_MASK |
3078                           TRANS_DP_BPC_MASK);
3079                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3080                          TRANS_DP_ENH_FRAMING);
3081                 temp |= bpc << 9; /* same format but at 11:9 */
3082
3083                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3084                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3085                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3086                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3087
3088                 switch (intel_trans_dp_port_sel(crtc)) {
3089                 case PCH_DP_B:
3090                         temp |= TRANS_DP_PORT_SEL_B;
3091                         break;
3092                 case PCH_DP_C:
3093                         temp |= TRANS_DP_PORT_SEL_C;
3094                         break;
3095                 case PCH_DP_D:
3096                         temp |= TRANS_DP_PORT_SEL_D;
3097                         break;
3098                 default:
3099                         BUG();
3100                 }
3101
3102                 I915_WRITE(reg, temp);
3103         }
3104
3105         intel_enable_transcoder(dev_priv, pipe);
3106 }
3107
3108 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3109 {
3110         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3111
3112         if (pll == NULL)
3113                 return;
3114
3115         if (pll->refcount == 0) {
3116                 WARN(1, "bad PCH PLL refcount\n");
3117                 return;
3118         }
3119
3120         --pll->refcount;
3121         intel_crtc->pch_pll = NULL;
3122 }
3123
3124 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3125 {
3126         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3127         struct intel_pch_pll *pll;
3128         int i;
3129
3130         pll = intel_crtc->pch_pll;
3131         if (pll) {
3132                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3133                               intel_crtc->base.base.id, pll->pll_reg);
3134                 goto prepare;
3135         }
3136
3137         if (HAS_PCH_IBX(dev_priv->dev)) {
3138                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3139                 i = intel_crtc->pipe;
3140                 pll = &dev_priv->pch_plls[i];
3141
3142                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3143                               intel_crtc->base.base.id, pll->pll_reg);
3144
3145                 goto found;
3146         }
3147
3148         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3149                 pll = &dev_priv->pch_plls[i];
3150
3151                 /* Only want to check enabled timings first */
3152                 if (pll->refcount == 0)
3153                         continue;
3154
3155                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3156                     fp == I915_READ(pll->fp0_reg)) {
3157                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3158                                       intel_crtc->base.base.id,
3159                                       pll->pll_reg, pll->refcount, pll->active);
3160
3161                         goto found;
3162                 }
3163         }
3164
3165         /* Ok no matching timings, maybe there's a free one? */
3166         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3167                 pll = &dev_priv->pch_plls[i];
3168                 if (pll->refcount == 0) {
3169                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3170                                       intel_crtc->base.base.id, pll->pll_reg);
3171                         goto found;
3172                 }
3173         }
3174
3175         return NULL;
3176
3177 found:
3178         intel_crtc->pch_pll = pll;
3179         pll->refcount++;
3180         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3181 prepare: /* separate function? */
3182         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3183
3184         /* Wait for the clocks to stabilize before rewriting the regs */
3185         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3186         POSTING_READ(pll->pll_reg);
3187         udelay(150);
3188
3189         I915_WRITE(pll->fp0_reg, fp);
3190         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3191         pll->on = false;
3192         return pll;
3193 }
3194
3195 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3196 {
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3199         u32 temp;
3200
3201         temp = I915_READ(dslreg);
3202         udelay(500);
3203         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3204                 /* Without this, mode sets may fail silently on FDI */
3205                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3206                 udelay(250);
3207                 I915_WRITE(tc2reg, 0);
3208                 if (wait_for(I915_READ(dslreg) != temp, 5))
3209                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3210         }
3211 }
3212
3213 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3214 {
3215         struct drm_device *dev = crtc->dev;
3216         struct drm_i915_private *dev_priv = dev->dev_private;
3217         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218         struct intel_encoder *encoder;
3219         int pipe = intel_crtc->pipe;
3220         int plane = intel_crtc->plane;
3221         u32 temp;
3222         bool is_pch_port;
3223
3224         WARN_ON(!crtc->enabled);
3225
3226         if (intel_crtc->active)
3227                 return;
3228
3229         intel_crtc->active = true;
3230         intel_update_watermarks(dev);
3231
3232         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233                 temp = I915_READ(PCH_LVDS);
3234                 if ((temp & LVDS_PORT_EN) == 0)
3235                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236         }
3237
3238         is_pch_port = ironlake_crtc_driving_pch(crtc);
3239
3240         if (is_pch_port) {
3241                 /* Note: FDI PLL enabling _must_ be done before we enable the
3242                  * cpu pipes, hence this is separate from all the other fdi/pch
3243                  * enabling. */
3244                 ironlake_fdi_pll_enable(intel_crtc);
3245         } else {
3246                 assert_fdi_tx_disabled(dev_priv, pipe);
3247                 assert_fdi_rx_disabled(dev_priv, pipe);
3248         }
3249
3250         for_each_encoder_on_crtc(dev, crtc, encoder)
3251                 if (encoder->pre_enable)
3252                         encoder->pre_enable(encoder);
3253
3254         /* Enable panel fitting for LVDS */
3255         if (dev_priv->pch_pf_size &&
3256             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3257                 /* Force use of hard-coded filter coefficients
3258                  * as some pre-programmed values are broken,
3259                  * e.g. x201.
3260                  */
3261                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3263                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3264         }
3265
3266         /*
3267          * On ILK+ LUT must be loaded before the pipe is running but with
3268          * clocks enabled
3269          */
3270         intel_crtc_load_lut(crtc);
3271
3272         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3273         intel_enable_plane(dev_priv, plane, pipe);
3274
3275         if (is_pch_port)
3276                 ironlake_pch_enable(crtc);
3277
3278         mutex_lock(&dev->struct_mutex);
3279         intel_update_fbc(dev);
3280         mutex_unlock(&dev->struct_mutex);
3281
3282         intel_crtc_update_cursor(crtc, true);
3283
3284         for_each_encoder_on_crtc(dev, crtc, encoder)
3285                 encoder->enable(encoder);
3286
3287         if (HAS_PCH_CPT(dev))
3288                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3289
3290         /*
3291          * There seems to be a race in PCH platform hw (at least on some
3292          * outputs) where an enabled pipe still completes any pageflip right
3293          * away (as if the pipe is off) instead of waiting for vblank. As soon
3294          * as the first vblank happend, everything works as expected. Hence just
3295          * wait for one vblank before returning to avoid strange things
3296          * happening.
3297          */
3298         intel_wait_for_vblank(dev, intel_crtc->pipe);
3299 }
3300
3301 static void haswell_crtc_enable(struct drm_crtc *crtc)
3302 {
3303         struct drm_device *dev = crtc->dev;
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306         struct intel_encoder *encoder;
3307         int pipe = intel_crtc->pipe;
3308         int plane = intel_crtc->plane;
3309         bool is_pch_port;
3310
3311         WARN_ON(!crtc->enabled);
3312
3313         if (intel_crtc->active)
3314                 return;
3315
3316         intel_crtc->active = true;
3317         intel_update_watermarks(dev);
3318
3319         is_pch_port = haswell_crtc_driving_pch(crtc);
3320
3321         if (is_pch_port)
3322                 ironlake_fdi_pll_enable(intel_crtc);
3323
3324         for_each_encoder_on_crtc(dev, crtc, encoder)
3325                 if (encoder->pre_enable)
3326                         encoder->pre_enable(encoder);
3327
3328         intel_ddi_enable_pipe_clock(intel_crtc);
3329
3330         /* Enable panel fitting for eDP */
3331         if (dev_priv->pch_pf_size && HAS_eDP) {
3332                 /* Force use of hard-coded filter coefficients
3333                  * as some pre-programmed values are broken,
3334                  * e.g. x201.
3335                  */
3336                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3337                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3338                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3339         }
3340
3341         /*
3342          * On ILK+ LUT must be loaded before the pipe is running but with
3343          * clocks enabled
3344          */
3345         intel_crtc_load_lut(crtc);
3346
3347         intel_ddi_set_pipe_settings(crtc);
3348         intel_ddi_enable_pipe_func(crtc);
3349
3350         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3351         intel_enable_plane(dev_priv, plane, pipe);
3352
3353         if (is_pch_port)
3354                 ironlake_pch_enable(crtc);
3355
3356         mutex_lock(&dev->struct_mutex);
3357         intel_update_fbc(dev);
3358         mutex_unlock(&dev->struct_mutex);
3359
3360         intel_crtc_update_cursor(crtc, true);
3361
3362         for_each_encoder_on_crtc(dev, crtc, encoder)
3363                 encoder->enable(encoder);
3364
3365         /*
3366          * There seems to be a race in PCH platform hw (at least on some
3367          * outputs) where an enabled pipe still completes any pageflip right
3368          * away (as if the pipe is off) instead of waiting for vblank. As soon
3369          * as the first vblank happend, everything works as expected. Hence just
3370          * wait for one vblank before returning to avoid strange things
3371          * happening.
3372          */
3373         intel_wait_for_vblank(dev, intel_crtc->pipe);
3374 }
3375
3376 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3377 {
3378         struct drm_device *dev = crtc->dev;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381         struct intel_encoder *encoder;
3382         int pipe = intel_crtc->pipe;
3383         int plane = intel_crtc->plane;
3384         u32 reg, temp;
3385
3386
3387         if (!intel_crtc->active)
3388                 return;
3389
3390         for_each_encoder_on_crtc(dev, crtc, encoder)
3391                 encoder->disable(encoder);
3392
3393         intel_crtc_wait_for_pending_flips(crtc);
3394         drm_vblank_off(dev, pipe);
3395         intel_crtc_update_cursor(crtc, false);
3396
3397         intel_disable_plane(dev_priv, plane, pipe);
3398
3399         if (dev_priv->cfb_plane == plane)
3400                 intel_disable_fbc(dev);
3401
3402         intel_disable_pipe(dev_priv, pipe);
3403
3404         /* Disable PF */
3405         I915_WRITE(PF_CTL(pipe), 0);
3406         I915_WRITE(PF_WIN_SZ(pipe), 0);
3407
3408         for_each_encoder_on_crtc(dev, crtc, encoder)
3409                 if (encoder->post_disable)
3410                         encoder->post_disable(encoder);
3411
3412         ironlake_fdi_disable(crtc);
3413
3414         intel_disable_transcoder(dev_priv, pipe);
3415
3416         if (HAS_PCH_CPT(dev)) {
3417                 /* disable TRANS_DP_CTL */
3418                 reg = TRANS_DP_CTL(pipe);
3419                 temp = I915_READ(reg);
3420                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3421                 temp |= TRANS_DP_PORT_SEL_NONE;
3422                 I915_WRITE(reg, temp);
3423
3424                 /* disable DPLL_SEL */
3425                 temp = I915_READ(PCH_DPLL_SEL);
3426                 switch (pipe) {
3427                 case 0:
3428                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3429                         break;
3430                 case 1:
3431                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3432                         break;
3433                 case 2:
3434                         /* C shares PLL A or B */
3435                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3436                         break;
3437                 default:
3438                         BUG(); /* wtf */
3439                 }
3440                 I915_WRITE(PCH_DPLL_SEL, temp);
3441         }
3442
3443         /* disable PCH DPLL */
3444         intel_disable_pch_pll(intel_crtc);
3445
3446         ironlake_fdi_pll_disable(intel_crtc);
3447
3448         intel_crtc->active = false;
3449         intel_update_watermarks(dev);
3450
3451         mutex_lock(&dev->struct_mutex);
3452         intel_update_fbc(dev);
3453         mutex_unlock(&dev->struct_mutex);
3454 }
3455
3456 static void haswell_crtc_disable(struct drm_crtc *crtc)
3457 {
3458         struct drm_device *dev = crtc->dev;
3459         struct drm_i915_private *dev_priv = dev->dev_private;
3460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461         struct intel_encoder *encoder;
3462         int pipe = intel_crtc->pipe;
3463         int plane = intel_crtc->plane;
3464         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3465         bool is_pch_port;
3466
3467         if (!intel_crtc->active)
3468                 return;
3469
3470         is_pch_port = haswell_crtc_driving_pch(crtc);
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 encoder->disable(encoder);
3474
3475         intel_crtc_wait_for_pending_flips(crtc);
3476         drm_vblank_off(dev, pipe);
3477         intel_crtc_update_cursor(crtc, false);
3478
3479         intel_disable_plane(dev_priv, plane, pipe);
3480
3481         if (dev_priv->cfb_plane == plane)
3482                 intel_disable_fbc(dev);
3483
3484         intel_disable_pipe(dev_priv, pipe);
3485
3486         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3487
3488         /* Disable PF */
3489         I915_WRITE(PF_CTL(pipe), 0);
3490         I915_WRITE(PF_WIN_SZ(pipe), 0);
3491
3492         intel_ddi_disable_pipe_clock(intel_crtc);
3493
3494         for_each_encoder_on_crtc(dev, crtc, encoder)
3495                 if (encoder->post_disable)
3496                         encoder->post_disable(encoder);
3497
3498         if (is_pch_port) {
3499                 ironlake_fdi_disable(crtc);
3500                 intel_disable_transcoder(dev_priv, pipe);
3501                 intel_disable_pch_pll(intel_crtc);
3502                 ironlake_fdi_pll_disable(intel_crtc);
3503         }
3504
3505         intel_crtc->active = false;
3506         intel_update_watermarks(dev);
3507
3508         mutex_lock(&dev->struct_mutex);
3509         intel_update_fbc(dev);
3510         mutex_unlock(&dev->struct_mutex);
3511 }
3512
3513 static void ironlake_crtc_off(struct drm_crtc *crtc)
3514 {
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         intel_put_pch_pll(intel_crtc);
3517 }
3518
3519 static void haswell_crtc_off(struct drm_crtc *crtc)
3520 {
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522
3523         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3524          * start using it. */
3525         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3526
3527         intel_ddi_put_crtc_pll(crtc);
3528 }
3529
3530 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3531 {
3532         if (!enable && intel_crtc->overlay) {
3533                 struct drm_device *dev = intel_crtc->base.dev;
3534                 struct drm_i915_private *dev_priv = dev->dev_private;
3535
3536                 mutex_lock(&dev->struct_mutex);
3537                 dev_priv->mm.interruptible = false;
3538                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3539                 dev_priv->mm.interruptible = true;
3540                 mutex_unlock(&dev->struct_mutex);
3541         }
3542
3543         /* Let userspace switch the overlay on again. In most cases userspace
3544          * has to recompute where to put it anyway.
3545          */
3546 }
3547
3548 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         struct intel_encoder *encoder;
3554         int pipe = intel_crtc->pipe;
3555         int plane = intel_crtc->plane;
3556
3557         WARN_ON(!crtc->enabled);
3558
3559         if (intel_crtc->active)
3560                 return;
3561
3562         intel_crtc->active = true;
3563         intel_update_watermarks(dev);
3564
3565         intel_enable_pll(dev_priv, pipe);
3566         intel_enable_pipe(dev_priv, pipe, false);
3567         intel_enable_plane(dev_priv, plane, pipe);
3568
3569         intel_crtc_load_lut(crtc);
3570         intel_update_fbc(dev);
3571
3572         /* Give the overlay scaler a chance to enable if it's on this pipe */
3573         intel_crtc_dpms_overlay(intel_crtc, true);
3574         intel_crtc_update_cursor(crtc, true);
3575
3576         for_each_encoder_on_crtc(dev, crtc, encoder)
3577                 encoder->enable(encoder);
3578 }
3579
3580 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3581 {
3582         struct drm_device *dev = crtc->dev;
3583         struct drm_i915_private *dev_priv = dev->dev_private;
3584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585         struct intel_encoder *encoder;
3586         int pipe = intel_crtc->pipe;
3587         int plane = intel_crtc->plane;
3588
3589
3590         if (!intel_crtc->active)
3591                 return;
3592
3593         for_each_encoder_on_crtc(dev, crtc, encoder)
3594                 encoder->disable(encoder);
3595
3596         /* Give the overlay scaler a chance to disable if it's on this pipe */
3597         intel_crtc_wait_for_pending_flips(crtc);
3598         drm_vblank_off(dev, pipe);
3599         intel_crtc_dpms_overlay(intel_crtc, false);
3600         intel_crtc_update_cursor(crtc, false);
3601
3602         if (dev_priv->cfb_plane == plane)
3603                 intel_disable_fbc(dev);
3604
3605         intel_disable_plane(dev_priv, plane, pipe);
3606         intel_disable_pipe(dev_priv, pipe);
3607         intel_disable_pll(dev_priv, pipe);
3608
3609         intel_crtc->active = false;
3610         intel_update_fbc(dev);
3611         intel_update_watermarks(dev);
3612 }
3613
3614 static void i9xx_crtc_off(struct drm_crtc *crtc)
3615 {
3616 }
3617
3618 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3619                                     bool enabled)
3620 {
3621         struct drm_device *dev = crtc->dev;
3622         struct drm_i915_master_private *master_priv;
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624         int pipe = intel_crtc->pipe;
3625
3626         if (!dev->primary->master)
3627                 return;
3628
3629         master_priv = dev->primary->master->driver_priv;
3630         if (!master_priv->sarea_priv)
3631                 return;
3632
3633         switch (pipe) {
3634         case 0:
3635                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3636                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3637                 break;
3638         case 1:
3639                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3640                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3641                 break;
3642         default:
3643                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3644                 break;
3645         }
3646 }
3647
3648 /**
3649  * Sets the power management mode of the pipe and plane.
3650  */
3651 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_encoder *intel_encoder;
3656         bool enable = false;
3657
3658         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3659                 enable |= intel_encoder->connectors_active;
3660
3661         if (enable)
3662                 dev_priv->display.crtc_enable(crtc);
3663         else
3664                 dev_priv->display.crtc_disable(crtc);
3665
3666         intel_crtc_update_sarea(crtc, enable);
3667 }
3668
3669 static void intel_crtc_noop(struct drm_crtc *crtc)
3670 {
3671 }
3672
3673 static void intel_crtc_disable(struct drm_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->dev;
3676         struct drm_connector *connector;
3677         struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679         /* crtc should still be enabled when we disable it. */
3680         WARN_ON(!crtc->enabled);
3681
3682         dev_priv->display.crtc_disable(crtc);
3683         intel_crtc_update_sarea(crtc, false);
3684         dev_priv->display.off(crtc);
3685
3686         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3687         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3688
3689         if (crtc->fb) {
3690                 mutex_lock(&dev->struct_mutex);
3691                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3692                 mutex_unlock(&dev->struct_mutex);
3693                 crtc->fb = NULL;
3694         }
3695
3696         /* Update computed state. */
3697         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3698                 if (!connector->encoder || !connector->encoder->crtc)
3699                         continue;
3700
3701                 if (connector->encoder->crtc != crtc)
3702                         continue;
3703
3704                 connector->dpms = DRM_MODE_DPMS_OFF;
3705                 to_intel_encoder(connector->encoder)->connectors_active = false;
3706         }
3707 }
3708
3709 void intel_modeset_disable(struct drm_device *dev)
3710 {
3711         struct drm_crtc *crtc;
3712
3713         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3714                 if (crtc->enabled)
3715                         intel_crtc_disable(crtc);
3716         }
3717 }
3718
3719 void intel_encoder_noop(struct drm_encoder *encoder)
3720 {
3721 }
3722
3723 void intel_encoder_destroy(struct drm_encoder *encoder)
3724 {
3725         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3726
3727         drm_encoder_cleanup(encoder);
3728         kfree(intel_encoder);
3729 }
3730
3731 /* Simple dpms helper for encodres with just one connector, no cloning and only
3732  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3733  * state of the entire output pipe. */
3734 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3735 {
3736         if (mode == DRM_MODE_DPMS_ON) {
3737                 encoder->connectors_active = true;
3738
3739                 intel_crtc_update_dpms(encoder->base.crtc);
3740         } else {
3741                 encoder->connectors_active = false;
3742
3743                 intel_crtc_update_dpms(encoder->base.crtc);
3744         }
3745 }
3746
3747 /* Cross check the actual hw state with our own modeset state tracking (and it's
3748  * internal consistency). */
3749 static void intel_connector_check_state(struct intel_connector *connector)
3750 {
3751         if (connector->get_hw_state(connector)) {
3752                 struct intel_encoder *encoder = connector->encoder;
3753                 struct drm_crtc *crtc;
3754                 bool encoder_enabled;
3755                 enum pipe pipe;
3756
3757                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3758                               connector->base.base.id,
3759                               drm_get_connector_name(&connector->base));
3760
3761                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3762                      "wrong connector dpms state\n");
3763                 WARN(connector->base.encoder != &encoder->base,
3764                      "active connector not linked to encoder\n");
3765                 WARN(!encoder->connectors_active,
3766                      "encoder->connectors_active not set\n");
3767
3768                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3769                 WARN(!encoder_enabled, "encoder not enabled\n");
3770                 if (WARN_ON(!encoder->base.crtc))
3771                         return;
3772
3773                 crtc = encoder->base.crtc;
3774
3775                 WARN(!crtc->enabled, "crtc not enabled\n");
3776                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3777                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3778                      "encoder active on the wrong pipe\n");
3779         }
3780 }
3781
3782 /* Even simpler default implementation, if there's really no special case to
3783  * consider. */
3784 void intel_connector_dpms(struct drm_connector *connector, int mode)
3785 {
3786         struct intel_encoder *encoder = intel_attached_encoder(connector);
3787
3788         /* All the simple cases only support two dpms states. */
3789         if (mode != DRM_MODE_DPMS_ON)
3790                 mode = DRM_MODE_DPMS_OFF;
3791
3792         if (mode == connector->dpms)
3793                 return;
3794
3795         connector->dpms = mode;
3796
3797         /* Only need to change hw state when actually enabled */
3798         if (encoder->base.crtc)
3799                 intel_encoder_dpms(encoder, mode);
3800         else
3801                 WARN_ON(encoder->connectors_active != false);
3802
3803         intel_modeset_check_state(connector->dev);
3804 }
3805
3806 /* Simple connector->get_hw_state implementation for encoders that support only
3807  * one connector and no cloning and hence the encoder state determines the state
3808  * of the connector. */
3809 bool intel_connector_get_hw_state(struct intel_connector *connector)
3810 {
3811         enum pipe pipe = 0;
3812         struct intel_encoder *encoder = connector->encoder;
3813
3814         return encoder->get_hw_state(encoder, &pipe);
3815 }
3816
3817 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3818                                   const struct drm_display_mode *mode,
3819                                   struct drm_display_mode *adjusted_mode)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822
3823         if (HAS_PCH_SPLIT(dev)) {
3824                 /* FDI link clock is fixed at 2.7G */
3825                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3826                         return false;
3827         }
3828
3829         /* All interlaced capable intel hw wants timings in frames. Note though
3830          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3831          * timings, so we need to be careful not to clobber these.*/
3832         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3833                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3834
3835         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3836          * with a hsync front porch of 0.
3837          */
3838         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3839                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3840                 return false;
3841
3842         return true;
3843 }
3844
3845 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3846 {
3847         return 400000; /* FIXME */
3848 }
3849
3850 static int i945_get_display_clock_speed(struct drm_device *dev)
3851 {
3852         return 400000;
3853 }
3854
3855 static int i915_get_display_clock_speed(struct drm_device *dev)
3856 {
3857         return 333000;
3858 }
3859
3860 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3861 {
3862         return 200000;
3863 }
3864
3865 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3866 {
3867         u16 gcfgc = 0;
3868
3869         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3870
3871         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3872                 return 133000;
3873         else {
3874                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3875                 case GC_DISPLAY_CLOCK_333_MHZ:
3876                         return 333000;
3877                 default:
3878                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3879                         return 190000;
3880                 }
3881         }
3882 }
3883
3884 static int i865_get_display_clock_speed(struct drm_device *dev)
3885 {
3886         return 266000;
3887 }
3888
3889 static int i855_get_display_clock_speed(struct drm_device *dev)
3890 {
3891         u16 hpllcc = 0;
3892         /* Assume that the hardware is in the high speed state.  This
3893          * should be the default.
3894          */
3895         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3896         case GC_CLOCK_133_200:
3897         case GC_CLOCK_100_200:
3898                 return 200000;
3899         case GC_CLOCK_166_250:
3900                 return 250000;
3901         case GC_CLOCK_100_133:
3902                 return 133000;
3903         }
3904
3905         /* Shouldn't happen */
3906         return 0;
3907 }
3908
3909 static int i830_get_display_clock_speed(struct drm_device *dev)
3910 {
3911         return 133000;
3912 }
3913
3914 struct fdi_m_n {
3915         u32        tu;
3916         u32        gmch_m;
3917         u32        gmch_n;
3918         u32        link_m;
3919         u32        link_n;
3920 };
3921
3922 static void
3923 fdi_reduce_ratio(u32 *num, u32 *den)
3924 {
3925         while (*num > 0xffffff || *den > 0xffffff) {
3926                 *num >>= 1;
3927                 *den >>= 1;
3928         }
3929 }
3930
3931 static void
3932 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3933                      int link_clock, struct fdi_m_n *m_n)
3934 {
3935         m_n->tu = 64; /* default size */
3936
3937         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3938         m_n->gmch_m = bits_per_pixel * pixel_clock;
3939         m_n->gmch_n = link_clock * nlanes * 8;
3940         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3941
3942         m_n->link_m = pixel_clock;
3943         m_n->link_n = link_clock;
3944         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3945 }
3946
3947 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3948 {
3949         if (i915_panel_use_ssc >= 0)
3950                 return i915_panel_use_ssc != 0;
3951         return dev_priv->lvds_use_ssc
3952                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3953 }
3954
3955 /**
3956  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3957  * @crtc: CRTC structure
3958  * @mode: requested mode
3959  *
3960  * A pipe may be connected to one or more outputs.  Based on the depth of the
3961  * attached framebuffer, choose a good color depth to use on the pipe.
3962  *
3963  * If possible, match the pipe depth to the fb depth.  In some cases, this
3964  * isn't ideal, because the connected output supports a lesser or restricted
3965  * set of depths.  Resolve that here:
3966  *    LVDS typically supports only 6bpc, so clamp down in that case
3967  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3968  *    Displays may support a restricted set as well, check EDID and clamp as
3969  *      appropriate.
3970  *    DP may want to dither down to 6bpc to fit larger modes
3971  *
3972  * RETURNS:
3973  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3974  * true if they don't match).
3975  */
3976 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3977                                          struct drm_framebuffer *fb,
3978                                          unsigned int *pipe_bpp,
3979                                          struct drm_display_mode *mode)
3980 {
3981         struct drm_device *dev = crtc->dev;
3982         struct drm_i915_private *dev_priv = dev->dev_private;
3983         struct drm_connector *connector;
3984         struct intel_encoder *intel_encoder;
3985         unsigned int display_bpc = UINT_MAX, bpc;
3986
3987         /* Walk the encoders & connectors on this crtc, get min bpc */
3988         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3989
3990                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3991                         unsigned int lvds_bpc;
3992
3993                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3994                             LVDS_A3_POWER_UP)
3995                                 lvds_bpc = 8;
3996                         else
3997                                 lvds_bpc = 6;
3998
3999                         if (lvds_bpc < display_bpc) {
4000                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4001                                 display_bpc = lvds_bpc;
4002                         }
4003                         continue;
4004                 }
4005
4006                 /* Not one of the known troublemakers, check the EDID */
4007                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4008                                     head) {
4009                         if (connector->encoder != &intel_encoder->base)
4010                                 continue;
4011
4012                         /* Don't use an invalid EDID bpc value */
4013                         if (connector->display_info.bpc &&
4014                             connector->display_info.bpc < display_bpc) {
4015                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4016                                 display_bpc = connector->display_info.bpc;
4017                         }
4018                 }
4019
4020                 /*
4021                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4022                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4023                  */
4024                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4025                         if (display_bpc > 8 && display_bpc < 12) {
4026                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4027                                 display_bpc = 12;
4028                         } else {
4029                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4030                                 display_bpc = 8;
4031                         }
4032                 }
4033         }
4034
4035         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4036                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4037                 display_bpc = 6;
4038         }
4039
4040         /*
4041          * We could just drive the pipe at the highest bpc all the time and
4042          * enable dithering as needed, but that costs bandwidth.  So choose
4043          * the minimum value that expresses the full color range of the fb but
4044          * also stays within the max display bpc discovered above.
4045          */
4046
4047         switch (fb->depth) {
4048         case 8:
4049                 bpc = 8; /* since we go through a colormap */
4050                 break;
4051         case 15:
4052         case 16:
4053                 bpc = 6; /* min is 18bpp */
4054                 break;
4055         case 24:
4056                 bpc = 8;
4057                 break;
4058         case 30:
4059                 bpc = 10;
4060                 break;
4061         case 48:
4062                 bpc = 12;
4063                 break;
4064         default:
4065                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4066                 bpc = min((unsigned int)8, display_bpc);
4067                 break;
4068         }
4069
4070         display_bpc = min(display_bpc, bpc);
4071
4072         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4073                       bpc, display_bpc);
4074
4075         *pipe_bpp = display_bpc * 3;
4076
4077         return display_bpc != bpc;
4078 }
4079
4080 static int vlv_get_refclk(struct drm_crtc *crtc)
4081 {
4082         struct drm_device *dev = crtc->dev;
4083         struct drm_i915_private *dev_priv = dev->dev_private;
4084         int refclk = 27000; /* for DP & HDMI */
4085
4086         return 100000; /* only one validated so far */
4087
4088         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4089                 refclk = 96000;
4090         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4091                 if (intel_panel_use_ssc(dev_priv))
4092                         refclk = 100000;
4093                 else
4094                         refclk = 96000;
4095         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4096                 refclk = 100000;
4097         }
4098
4099         return refclk;
4100 }
4101
4102 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         int refclk;
4107
4108         if (IS_VALLEYVIEW(dev)) {
4109                 refclk = vlv_get_refclk(crtc);
4110         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4111             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4112                 refclk = dev_priv->lvds_ssc_freq * 1000;
4113                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4114                               refclk / 1000);
4115         } else if (!IS_GEN2(dev)) {
4116                 refclk = 96000;
4117         } else {
4118                 refclk = 48000;
4119         }
4120
4121         return refclk;
4122 }
4123
4124 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4125                                       intel_clock_t *clock)
4126 {
4127         /* SDVO TV has fixed PLL values depend on its clock range,
4128            this mirrors vbios setting. */
4129         if (adjusted_mode->clock >= 100000
4130             && adjusted_mode->clock < 140500) {
4131                 clock->p1 = 2;
4132                 clock->p2 = 10;
4133                 clock->n = 3;
4134                 clock->m1 = 16;
4135                 clock->m2 = 8;
4136         } else if (adjusted_mode->clock >= 140500
4137                    && adjusted_mode->clock <= 200000) {
4138                 clock->p1 = 1;
4139                 clock->p2 = 10;
4140                 clock->n = 6;
4141                 clock->m1 = 12;
4142                 clock->m2 = 8;
4143         }
4144 }
4145
4146 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4147                                      intel_clock_t *clock,
4148                                      intel_clock_t *reduced_clock)
4149 {
4150         struct drm_device *dev = crtc->dev;
4151         struct drm_i915_private *dev_priv = dev->dev_private;
4152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4153         int pipe = intel_crtc->pipe;
4154         u32 fp, fp2 = 0;
4155
4156         if (IS_PINEVIEW(dev)) {
4157                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4158                 if (reduced_clock)
4159                         fp2 = (1 << reduced_clock->n) << 16 |
4160                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4161         } else {
4162                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4163                 if (reduced_clock)
4164                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4165                                 reduced_clock->m2;
4166         }
4167
4168         I915_WRITE(FP0(pipe), fp);
4169
4170         intel_crtc->lowfreq_avail = false;
4171         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4172             reduced_clock && i915_powersave) {
4173                 I915_WRITE(FP1(pipe), fp2);
4174                 intel_crtc->lowfreq_avail = true;
4175         } else {
4176                 I915_WRITE(FP1(pipe), fp);
4177         }
4178 }
4179
4180 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4181                               struct drm_display_mode *adjusted_mode)
4182 {
4183         struct drm_device *dev = crtc->dev;
4184         struct drm_i915_private *dev_priv = dev->dev_private;
4185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4186         int pipe = intel_crtc->pipe;
4187         u32 temp;
4188
4189         temp = I915_READ(LVDS);
4190         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4191         if (pipe == 1) {
4192                 temp |= LVDS_PIPEB_SELECT;
4193         } else {
4194                 temp &= ~LVDS_PIPEB_SELECT;
4195         }
4196         /* set the corresponsding LVDS_BORDER bit */
4197         temp |= dev_priv->lvds_border_bits;
4198         /* Set the B0-B3 data pairs corresponding to whether we're going to
4199          * set the DPLLs for dual-channel mode or not.
4200          */
4201         if (clock->p2 == 7)
4202                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4203         else
4204                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4205
4206         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4207          * appropriately here, but we need to look more thoroughly into how
4208          * panels behave in the two modes.
4209          */
4210         /* set the dithering flag on LVDS as needed */
4211         if (INTEL_INFO(dev)->gen >= 4) {
4212                 if (dev_priv->lvds_dither)
4213                         temp |= LVDS_ENABLE_DITHER;
4214                 else
4215                         temp &= ~LVDS_ENABLE_DITHER;
4216         }
4217         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4218         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4219                 temp |= LVDS_HSYNC_POLARITY;
4220         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4221                 temp |= LVDS_VSYNC_POLARITY;
4222         I915_WRITE(LVDS, temp);
4223 }
4224
4225 static void vlv_update_pll(struct drm_crtc *crtc,
4226                            struct drm_display_mode *mode,
4227                            struct drm_display_mode *adjusted_mode,
4228                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4229                            int num_connectors)
4230 {
4231         struct drm_device *dev = crtc->dev;
4232         struct drm_i915_private *dev_priv = dev->dev_private;
4233         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234         int pipe = intel_crtc->pipe;
4235         u32 dpll, mdiv, pdiv;
4236         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4237         bool is_sdvo;
4238         u32 temp;
4239
4240         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4241                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4242
4243         dpll = DPLL_VGA_MODE_DIS;
4244         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4245         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4246         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4247
4248         I915_WRITE(DPLL(pipe), dpll);
4249         POSTING_READ(DPLL(pipe));
4250
4251         bestn = clock->n;
4252         bestm1 = clock->m1;
4253         bestm2 = clock->m2;
4254         bestp1 = clock->p1;
4255         bestp2 = clock->p2;
4256
4257         /*
4258          * In Valleyview PLL and program lane counter registers are exposed
4259          * through DPIO interface
4260          */
4261         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4262         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4263         mdiv |= ((bestn << DPIO_N_SHIFT));
4264         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4265         mdiv |= (1 << DPIO_K_SHIFT);
4266         mdiv |= DPIO_ENABLE_CALIBRATION;
4267         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4268
4269         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4270
4271         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4272                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4273                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4274                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4275         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4276
4277         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4278
4279         dpll |= DPLL_VCO_ENABLE;
4280         I915_WRITE(DPLL(pipe), dpll);
4281         POSTING_READ(DPLL(pipe));
4282         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4283                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4284
4285         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4286
4287         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4288                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4289
4290         I915_WRITE(DPLL(pipe), dpll);
4291
4292         /* Wait for the clocks to stabilize. */
4293         POSTING_READ(DPLL(pipe));
4294         udelay(150);
4295
4296         temp = 0;
4297         if (is_sdvo) {
4298                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4299                 if (temp > 1)
4300                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4301                 else
4302                         temp = 0;
4303         }
4304         I915_WRITE(DPLL_MD(pipe), temp);
4305         POSTING_READ(DPLL_MD(pipe));
4306
4307         /* Now program lane control registers */
4308         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4309                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4310         {
4311                 temp = 0x1000C4;
4312                 if(pipe == 1)
4313                         temp |= (1 << 21);
4314                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4315         }
4316         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4317         {
4318                 temp = 0x1000C4;
4319                 if(pipe == 1)
4320                         temp |= (1 << 21);
4321                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4322         }
4323 }
4324
4325 static void i9xx_update_pll(struct drm_crtc *crtc,
4326                             struct drm_display_mode *mode,
4327                             struct drm_display_mode *adjusted_mode,
4328                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4329                             int num_connectors)
4330 {
4331         struct drm_device *dev = crtc->dev;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4334         int pipe = intel_crtc->pipe;
4335         u32 dpll;
4336         bool is_sdvo;
4337
4338         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4339
4340         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4341                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4342
4343         dpll = DPLL_VGA_MODE_DIS;
4344
4345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4346                 dpll |= DPLLB_MODE_LVDS;
4347         else
4348                 dpll |= DPLLB_MODE_DAC_SERIAL;
4349         if (is_sdvo) {
4350                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4351                 if (pixel_multiplier > 1) {
4352                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4353                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4354                 }
4355                 dpll |= DPLL_DVO_HIGH_SPEED;
4356         }
4357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4358                 dpll |= DPLL_DVO_HIGH_SPEED;
4359
4360         /* compute bitmask from p1 value */
4361         if (IS_PINEVIEW(dev))
4362                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4363         else {
4364                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4365                 if (IS_G4X(dev) && reduced_clock)
4366                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4367         }
4368         switch (clock->p2) {
4369         case 5:
4370                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4371                 break;
4372         case 7:
4373                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4374                 break;
4375         case 10:
4376                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4377                 break;
4378         case 14:
4379                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4380                 break;
4381         }
4382         if (INTEL_INFO(dev)->gen >= 4)
4383                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4384
4385         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4386                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4387         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4388                 /* XXX: just matching BIOS for now */
4389                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4390                 dpll |= 3;
4391         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4392                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4393                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4394         else
4395                 dpll |= PLL_REF_INPUT_DREFCLK;
4396
4397         dpll |= DPLL_VCO_ENABLE;
4398         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4399         POSTING_READ(DPLL(pipe));
4400         udelay(150);
4401
4402         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4403          * This is an exception to the general rule that mode_set doesn't turn
4404          * things on.
4405          */
4406         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4407                 intel_update_lvds(crtc, clock, adjusted_mode);
4408
4409         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4410                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4411
4412         I915_WRITE(DPLL(pipe), dpll);
4413
4414         /* Wait for the clocks to stabilize. */
4415         POSTING_READ(DPLL(pipe));
4416         udelay(150);
4417
4418         if (INTEL_INFO(dev)->gen >= 4) {
4419                 u32 temp = 0;
4420                 if (is_sdvo) {
4421                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4422                         if (temp > 1)
4423                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4424                         else
4425                                 temp = 0;
4426                 }
4427                 I915_WRITE(DPLL_MD(pipe), temp);
4428         } else {
4429                 /* The pixel multiplier can only be updated once the
4430                  * DPLL is enabled and the clocks are stable.
4431                  *
4432                  * So write it again.
4433                  */
4434                 I915_WRITE(DPLL(pipe), dpll);
4435         }
4436 }
4437
4438 static void i8xx_update_pll(struct drm_crtc *crtc,
4439                             struct drm_display_mode *adjusted_mode,
4440                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4441                             int num_connectors)
4442 {
4443         struct drm_device *dev = crtc->dev;
4444         struct drm_i915_private *dev_priv = dev->dev_private;
4445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4446         int pipe = intel_crtc->pipe;
4447         u32 dpll;
4448
4449         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4450
4451         dpll = DPLL_VGA_MODE_DIS;
4452
4453         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4454                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4455         } else {
4456                 if (clock->p1 == 2)
4457                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4458                 else
4459                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4460                 if (clock->p2 == 4)
4461                         dpll |= PLL_P2_DIVIDE_BY_4;
4462         }
4463
4464         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4465                 /* XXX: just matching BIOS for now */
4466                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4467                 dpll |= 3;
4468         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4469                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4470                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4471         else
4472                 dpll |= PLL_REF_INPUT_DREFCLK;
4473
4474         dpll |= DPLL_VCO_ENABLE;
4475         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4476         POSTING_READ(DPLL(pipe));
4477         udelay(150);
4478
4479         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4480          * This is an exception to the general rule that mode_set doesn't turn
4481          * things on.
4482          */
4483         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4484                 intel_update_lvds(crtc, clock, adjusted_mode);
4485
4486         I915_WRITE(DPLL(pipe), dpll);
4487
4488         /* Wait for the clocks to stabilize. */
4489         POSTING_READ(DPLL(pipe));
4490         udelay(150);
4491
4492         /* The pixel multiplier can only be updated once the
4493          * DPLL is enabled and the clocks are stable.
4494          *
4495          * So write it again.
4496          */
4497         I915_WRITE(DPLL(pipe), dpll);
4498 }
4499
4500 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4501                                    struct drm_display_mode *mode,
4502                                    struct drm_display_mode *adjusted_mode)
4503 {
4504         struct drm_device *dev = intel_crtc->base.dev;
4505         struct drm_i915_private *dev_priv = dev->dev_private;
4506         enum pipe pipe = intel_crtc->pipe;
4507         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4508         uint32_t vsyncshift;
4509
4510         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4511                 /* the chip adds 2 halflines automatically */
4512                 adjusted_mode->crtc_vtotal -= 1;
4513                 adjusted_mode->crtc_vblank_end -= 1;
4514                 vsyncshift = adjusted_mode->crtc_hsync_start
4515                              - adjusted_mode->crtc_htotal / 2;
4516         } else {
4517                 vsyncshift = 0;
4518         }
4519
4520         if (INTEL_INFO(dev)->gen > 3)
4521                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4522
4523         I915_WRITE(HTOTAL(cpu_transcoder),
4524                    (adjusted_mode->crtc_hdisplay - 1) |
4525                    ((adjusted_mode->crtc_htotal - 1) << 16));
4526         I915_WRITE(HBLANK(cpu_transcoder),
4527                    (adjusted_mode->crtc_hblank_start - 1) |
4528                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4529         I915_WRITE(HSYNC(cpu_transcoder),
4530                    (adjusted_mode->crtc_hsync_start - 1) |
4531                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4532
4533         I915_WRITE(VTOTAL(cpu_transcoder),
4534                    (adjusted_mode->crtc_vdisplay - 1) |
4535                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4536         I915_WRITE(VBLANK(cpu_transcoder),
4537                    (adjusted_mode->crtc_vblank_start - 1) |
4538                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4539         I915_WRITE(VSYNC(cpu_transcoder),
4540                    (adjusted_mode->crtc_vsync_start - 1) |
4541                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4542
4543         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4544          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4545          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4546          * bits. */
4547         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4548             (pipe == PIPE_B || pipe == PIPE_C))
4549                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4550
4551         /* pipesrc controls the size that is scaled from, which should
4552          * always be the user's requested size.
4553          */
4554         I915_WRITE(PIPESRC(pipe),
4555                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4556 }
4557
4558 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4559                               struct drm_display_mode *mode,
4560                               struct drm_display_mode *adjusted_mode,
4561                               int x, int y,
4562                               struct drm_framebuffer *fb)
4563 {
4564         struct drm_device *dev = crtc->dev;
4565         struct drm_i915_private *dev_priv = dev->dev_private;
4566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4567         int pipe = intel_crtc->pipe;
4568         int plane = intel_crtc->plane;
4569         int refclk, num_connectors = 0;
4570         intel_clock_t clock, reduced_clock;
4571         u32 dspcntr, pipeconf;
4572         bool ok, has_reduced_clock = false, is_sdvo = false;
4573         bool is_lvds = false, is_tv = false, is_dp = false;
4574         struct intel_encoder *encoder;
4575         const intel_limit_t *limit;
4576         int ret;
4577
4578         for_each_encoder_on_crtc(dev, crtc, encoder) {
4579                 switch (encoder->type) {
4580                 case INTEL_OUTPUT_LVDS:
4581                         is_lvds = true;
4582                         break;
4583                 case INTEL_OUTPUT_SDVO:
4584                 case INTEL_OUTPUT_HDMI:
4585                         is_sdvo = true;
4586                         if (encoder->needs_tv_clock)
4587                                 is_tv = true;
4588                         break;
4589                 case INTEL_OUTPUT_TVOUT:
4590                         is_tv = true;
4591                         break;
4592                 case INTEL_OUTPUT_DISPLAYPORT:
4593                         is_dp = true;
4594                         break;
4595                 }
4596
4597                 num_connectors++;
4598         }
4599
4600         refclk = i9xx_get_refclk(crtc, num_connectors);
4601
4602         /*
4603          * Returns a set of divisors for the desired target clock with the given
4604          * refclk, or FALSE.  The returned values represent the clock equation:
4605          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4606          */
4607         limit = intel_limit(crtc, refclk);
4608         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4609                              &clock);
4610         if (!ok) {
4611                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4612                 return -EINVAL;
4613         }
4614
4615         /* Ensure that the cursor is valid for the new mode before changing... */
4616         intel_crtc_update_cursor(crtc, true);
4617
4618         if (is_lvds && dev_priv->lvds_downclock_avail) {
4619                 /*
4620                  * Ensure we match the reduced clock's P to the target clock.
4621                  * If the clocks don't match, we can't switch the display clock
4622                  * by using the FP0/FP1. In such case we will disable the LVDS
4623                  * downclock feature.
4624                 */
4625                 has_reduced_clock = limit->find_pll(limit, crtc,
4626                                                     dev_priv->lvds_downclock,
4627                                                     refclk,
4628                                                     &clock,
4629                                                     &reduced_clock);
4630         }
4631
4632         if (is_sdvo && is_tv)
4633                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4634
4635         if (IS_GEN2(dev))
4636                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4637                                 has_reduced_clock ? &reduced_clock : NULL,
4638                                 num_connectors);
4639         else if (IS_VALLEYVIEW(dev))
4640                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4641                                 has_reduced_clock ? &reduced_clock : NULL,
4642                                 num_connectors);
4643         else
4644                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4645                                 has_reduced_clock ? &reduced_clock : NULL,
4646                                 num_connectors);
4647
4648         /* setup pipeconf */
4649         pipeconf = I915_READ(PIPECONF(pipe));
4650
4651         /* Set up the display plane register */
4652         dspcntr = DISPPLANE_GAMMA_ENABLE;
4653
4654         if (pipe == 0)
4655                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4656         else
4657                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4658
4659         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4660                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4661                  * core speed.
4662                  *
4663                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4664                  * pipe == 0 check?
4665                  */
4666                 if (mode->clock >
4667                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4668                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4669                 else
4670                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4671         }
4672
4673         /* default to 8bpc */
4674         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4675         if (is_dp) {
4676                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4677                         pipeconf |= PIPECONF_BPP_6 |
4678                                     PIPECONF_DITHER_EN |
4679                                     PIPECONF_DITHER_TYPE_SP;
4680                 }
4681         }
4682
4683         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4684                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4685                         pipeconf |= PIPECONF_BPP_6 |
4686                                         PIPECONF_ENABLE |
4687                                         I965_PIPECONF_ACTIVE;
4688                 }
4689         }
4690
4691         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4692         drm_mode_debug_printmodeline(mode);
4693
4694         if (HAS_PIPE_CXSR(dev)) {
4695                 if (intel_crtc->lowfreq_avail) {
4696                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4697                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4698                 } else {
4699                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4700                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4701                 }
4702         }
4703
4704         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4705         if (!IS_GEN2(dev) &&
4706             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4707                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4708         else
4709                 pipeconf |= PIPECONF_PROGRESSIVE;
4710
4711         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4712
4713         /* pipesrc and dspsize control the size that is scaled from,
4714          * which should always be the user's requested size.
4715          */
4716         I915_WRITE(DSPSIZE(plane),
4717                    ((mode->vdisplay - 1) << 16) |
4718                    (mode->hdisplay - 1));
4719         I915_WRITE(DSPPOS(plane), 0);
4720
4721         I915_WRITE(PIPECONF(pipe), pipeconf);
4722         POSTING_READ(PIPECONF(pipe));
4723         intel_enable_pipe(dev_priv, pipe, false);
4724
4725         intel_wait_for_vblank(dev, pipe);
4726
4727         I915_WRITE(DSPCNTR(plane), dspcntr);
4728         POSTING_READ(DSPCNTR(plane));
4729
4730         ret = intel_pipe_set_base(crtc, x, y, fb);
4731
4732         intel_update_watermarks(dev);
4733
4734         return ret;
4735 }
4736
4737 /*
4738  * Initialize reference clocks when the driver loads
4739  */
4740 void ironlake_init_pch_refclk(struct drm_device *dev)
4741 {
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         struct drm_mode_config *mode_config = &dev->mode_config;
4744         struct intel_encoder *encoder;
4745         u32 temp;
4746         bool has_lvds = false;
4747         bool has_cpu_edp = false;
4748         bool has_pch_edp = false;
4749         bool has_panel = false;
4750         bool has_ck505 = false;
4751         bool can_ssc = false;
4752
4753         /* We need to take the global config into account */
4754         list_for_each_entry(encoder, &mode_config->encoder_list,
4755                             base.head) {
4756                 switch (encoder->type) {
4757                 case INTEL_OUTPUT_LVDS:
4758                         has_panel = true;
4759                         has_lvds = true;
4760                         break;
4761                 case INTEL_OUTPUT_EDP:
4762                         has_panel = true;
4763                         if (intel_encoder_is_pch_edp(&encoder->base))
4764                                 has_pch_edp = true;
4765                         else
4766                                 has_cpu_edp = true;
4767                         break;
4768                 }
4769         }
4770
4771         if (HAS_PCH_IBX(dev)) {
4772                 has_ck505 = dev_priv->display_clock_mode;
4773                 can_ssc = has_ck505;
4774         } else {
4775                 has_ck505 = false;
4776                 can_ssc = true;
4777         }
4778
4779         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4780                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4781                       has_ck505);
4782
4783         /* Ironlake: try to setup display ref clock before DPLL
4784          * enabling. This is only under driver's control after
4785          * PCH B stepping, previous chipset stepping should be
4786          * ignoring this setting.
4787          */
4788         temp = I915_READ(PCH_DREF_CONTROL);
4789         /* Always enable nonspread source */
4790         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4791
4792         if (has_ck505)
4793                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4794         else
4795                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4796
4797         if (has_panel) {
4798                 temp &= ~DREF_SSC_SOURCE_MASK;
4799                 temp |= DREF_SSC_SOURCE_ENABLE;
4800
4801                 /* SSC must be turned on before enabling the CPU output  */
4802                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4803                         DRM_DEBUG_KMS("Using SSC on panel\n");
4804                         temp |= DREF_SSC1_ENABLE;
4805                 } else
4806                         temp &= ~DREF_SSC1_ENABLE;
4807
4808                 /* Get SSC going before enabling the outputs */
4809                 I915_WRITE(PCH_DREF_CONTROL, temp);
4810                 POSTING_READ(PCH_DREF_CONTROL);
4811                 udelay(200);
4812
4813                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4814
4815                 /* Enable CPU source on CPU attached eDP */
4816                 if (has_cpu_edp) {
4817                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4818                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4819                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4820                         }
4821                         else
4822                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4823                 } else
4824                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4825
4826                 I915_WRITE(PCH_DREF_CONTROL, temp);
4827                 POSTING_READ(PCH_DREF_CONTROL);
4828                 udelay(200);
4829         } else {
4830                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4831
4832                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4833
4834                 /* Turn off CPU output */
4835                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4836
4837                 I915_WRITE(PCH_DREF_CONTROL, temp);
4838                 POSTING_READ(PCH_DREF_CONTROL);
4839                 udelay(200);
4840
4841                 /* Turn off the SSC source */
4842                 temp &= ~DREF_SSC_SOURCE_MASK;
4843                 temp |= DREF_SSC_SOURCE_DISABLE;
4844
4845                 /* Turn off SSC1 */
4846                 temp &= ~ DREF_SSC1_ENABLE;
4847
4848                 I915_WRITE(PCH_DREF_CONTROL, temp);
4849                 POSTING_READ(PCH_DREF_CONTROL);
4850                 udelay(200);
4851         }
4852 }
4853
4854 static int ironlake_get_refclk(struct drm_crtc *crtc)
4855 {
4856         struct drm_device *dev = crtc->dev;
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         struct intel_encoder *encoder;
4859         struct intel_encoder *edp_encoder = NULL;
4860         int num_connectors = 0;
4861         bool is_lvds = false;
4862
4863         for_each_encoder_on_crtc(dev, crtc, encoder) {
4864                 switch (encoder->type) {
4865                 case INTEL_OUTPUT_LVDS:
4866                         is_lvds = true;
4867                         break;
4868                 case INTEL_OUTPUT_EDP:
4869                         edp_encoder = encoder;
4870                         break;
4871                 }
4872                 num_connectors++;
4873         }
4874
4875         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4876                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4877                               dev_priv->lvds_ssc_freq);
4878                 return dev_priv->lvds_ssc_freq * 1000;
4879         }
4880
4881         return 120000;
4882 }
4883
4884 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4885                                   struct drm_display_mode *adjusted_mode,
4886                                   bool dither)
4887 {
4888         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4890         int pipe = intel_crtc->pipe;
4891         uint32_t val;
4892
4893         val = I915_READ(PIPECONF(pipe));
4894
4895         val &= ~PIPE_BPC_MASK;
4896         switch (intel_crtc->bpp) {
4897         case 18:
4898                 val |= PIPE_6BPC;
4899                 break;
4900         case 24:
4901                 val |= PIPE_8BPC;
4902                 break;
4903         case 30:
4904                 val |= PIPE_10BPC;
4905                 break;
4906         case 36:
4907                 val |= PIPE_12BPC;
4908                 break;
4909         default:
4910                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4911                 BUG();
4912         }
4913
4914         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4915         if (dither)
4916                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4917
4918         val &= ~PIPECONF_INTERLACE_MASK;
4919         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4920                 val |= PIPECONF_INTERLACED_ILK;
4921         else
4922                 val |= PIPECONF_PROGRESSIVE;
4923
4924         I915_WRITE(PIPECONF(pipe), val);
4925         POSTING_READ(PIPECONF(pipe));
4926 }
4927
4928 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4929                                  struct drm_display_mode *adjusted_mode,
4930                                  bool dither)
4931 {
4932         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4934         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4935         uint32_t val;
4936
4937         val = I915_READ(PIPECONF(cpu_transcoder));
4938
4939         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4940         if (dither)
4941                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4942
4943         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4944         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4945                 val |= PIPECONF_INTERLACED_ILK;
4946         else
4947                 val |= PIPECONF_PROGRESSIVE;
4948
4949         I915_WRITE(PIPECONF(cpu_transcoder), val);
4950         POSTING_READ(PIPECONF(cpu_transcoder));
4951 }
4952
4953 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4954                                     struct drm_display_mode *adjusted_mode,
4955                                     intel_clock_t *clock,
4956                                     bool *has_reduced_clock,
4957                                     intel_clock_t *reduced_clock)
4958 {
4959         struct drm_device *dev = crtc->dev;
4960         struct drm_i915_private *dev_priv = dev->dev_private;
4961         struct intel_encoder *intel_encoder;
4962         int refclk;
4963         const intel_limit_t *limit;
4964         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4965
4966         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4967                 switch (intel_encoder->type) {
4968                 case INTEL_OUTPUT_LVDS:
4969                         is_lvds = true;
4970                         break;
4971                 case INTEL_OUTPUT_SDVO:
4972                 case INTEL_OUTPUT_HDMI:
4973                         is_sdvo = true;
4974                         if (intel_encoder->needs_tv_clock)
4975                                 is_tv = true;
4976                         break;
4977                 case INTEL_OUTPUT_TVOUT:
4978                         is_tv = true;
4979                         break;
4980                 }
4981         }
4982
4983         refclk = ironlake_get_refclk(crtc);
4984
4985         /*
4986          * Returns a set of divisors for the desired target clock with the given
4987          * refclk, or FALSE.  The returned values represent the clock equation:
4988          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4989          */
4990         limit = intel_limit(crtc, refclk);
4991         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4992                               clock);
4993         if (!ret)
4994                 return false;
4995
4996         if (is_lvds && dev_priv->lvds_downclock_avail) {
4997                 /*
4998                  * Ensure we match the reduced clock's P to the target clock.
4999                  * If the clocks don't match, we can't switch the display clock
5000                  * by using the FP0/FP1. In such case we will disable the LVDS
5001                  * downclock feature.
5002                 */
5003                 *has_reduced_clock = limit->find_pll(limit, crtc,
5004                                                      dev_priv->lvds_downclock,
5005                                                      refclk,
5006                                                      clock,
5007                                                      reduced_clock);
5008         }
5009
5010         if (is_sdvo && is_tv)
5011                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5012
5013         return true;
5014 }
5015
5016 static void ironlake_set_m_n(struct drm_crtc *crtc,
5017                              struct drm_display_mode *mode,
5018                              struct drm_display_mode *adjusted_mode)
5019 {
5020         struct drm_device *dev = crtc->dev;
5021         struct drm_i915_private *dev_priv = dev->dev_private;
5022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5024         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5025         struct fdi_m_n m_n = {0};
5026         int target_clock, pixel_multiplier, lane, link_bw;
5027         bool is_dp = false, is_cpu_edp = false;
5028
5029         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5030                 switch (intel_encoder->type) {
5031                 case INTEL_OUTPUT_DISPLAYPORT:
5032                         is_dp = true;
5033                         break;
5034                 case INTEL_OUTPUT_EDP:
5035                         is_dp = true;
5036                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5037                                 is_cpu_edp = true;
5038                         edp_encoder = intel_encoder;
5039                         break;
5040                 }
5041         }
5042
5043         /* FDI link */
5044         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5045         lane = 0;
5046         /* CPU eDP doesn't require FDI link, so just set DP M/N
5047            according to current link config */
5048         if (is_cpu_edp) {
5049                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5050         } else {
5051                 /* FDI is a binary signal running at ~2.7GHz, encoding
5052                  * each output octet as 10 bits. The actual frequency
5053                  * is stored as a divider into a 100MHz clock, and the
5054                  * mode pixel clock is stored in units of 1KHz.
5055                  * Hence the bw of each lane in terms of the mode signal
5056                  * is:
5057                  */
5058                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5059         }
5060
5061         /* [e]DP over FDI requires target mode clock instead of link clock. */
5062         if (edp_encoder)
5063                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5064         else if (is_dp)
5065                 target_clock = mode->clock;
5066         else
5067                 target_clock = adjusted_mode->clock;
5068
5069         if (!lane) {
5070                 /*
5071                  * Account for spread spectrum to avoid
5072                  * oversubscribing the link. Max center spread
5073                  * is 2.5%; use 5% for safety's sake.
5074                  */
5075                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5076                 lane = bps / (link_bw * 8) + 1;
5077         }
5078
5079         intel_crtc->fdi_lanes = lane;
5080
5081         if (pixel_multiplier > 1)
5082                 link_bw *= pixel_multiplier;
5083         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5084                              &m_n);
5085
5086         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5087         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5088         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5089         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5090 }
5091
5092 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5093                                       struct drm_display_mode *adjusted_mode,
5094                                       intel_clock_t *clock, u32 fp)
5095 {
5096         struct drm_crtc *crtc = &intel_crtc->base;
5097         struct drm_device *dev = crtc->dev;
5098         struct drm_i915_private *dev_priv = dev->dev_private;
5099         struct intel_encoder *intel_encoder;
5100         uint32_t dpll;
5101         int factor, pixel_multiplier, num_connectors = 0;
5102         bool is_lvds = false, is_sdvo = false, is_tv = false;
5103         bool is_dp = false, is_cpu_edp = false;
5104
5105         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5106                 switch (intel_encoder->type) {
5107                 case INTEL_OUTPUT_LVDS:
5108                         is_lvds = true;
5109                         break;
5110                 case INTEL_OUTPUT_SDVO:
5111                 case INTEL_OUTPUT_HDMI:
5112                         is_sdvo = true;
5113                         if (intel_encoder->needs_tv_clock)
5114                                 is_tv = true;
5115                         break;
5116                 case INTEL_OUTPUT_TVOUT:
5117                         is_tv = true;
5118                         break;
5119                 case INTEL_OUTPUT_DISPLAYPORT:
5120                         is_dp = true;
5121                         break;
5122                 case INTEL_OUTPUT_EDP:
5123                         is_dp = true;
5124                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5125                                 is_cpu_edp = true;
5126                         break;
5127                 }
5128
5129                 num_connectors++;
5130         }
5131
5132         /* Enable autotuning of the PLL clock (if permissible) */
5133         factor = 21;
5134         if (is_lvds) {
5135                 if ((intel_panel_use_ssc(dev_priv) &&
5136                      dev_priv->lvds_ssc_freq == 100) ||
5137                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5138                         factor = 25;
5139         } else if (is_sdvo && is_tv)
5140                 factor = 20;
5141
5142         if (clock->m < factor * clock->n)
5143                 fp |= FP_CB_TUNE;
5144
5145         dpll = 0;
5146
5147         if (is_lvds)
5148                 dpll |= DPLLB_MODE_LVDS;
5149         else
5150                 dpll |= DPLLB_MODE_DAC_SERIAL;
5151         if (is_sdvo) {
5152                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5153                 if (pixel_multiplier > 1) {
5154                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5155                 }
5156                 dpll |= DPLL_DVO_HIGH_SPEED;
5157         }
5158         if (is_dp && !is_cpu_edp)
5159                 dpll |= DPLL_DVO_HIGH_SPEED;
5160
5161         /* compute bitmask from p1 value */
5162         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5163         /* also FPA1 */
5164         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5165
5166         switch (clock->p2) {
5167         case 5:
5168                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5169                 break;
5170         case 7:
5171                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5172                 break;
5173         case 10:
5174                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5175                 break;
5176         case 14:
5177                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5178                 break;
5179         }
5180
5181         if (is_sdvo && is_tv)
5182                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5183         else if (is_tv)
5184                 /* XXX: just matching BIOS for now */
5185                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5186                 dpll |= 3;
5187         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5188                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5189         else
5190                 dpll |= PLL_REF_INPUT_DREFCLK;
5191
5192         return dpll;
5193 }
5194
5195 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5196                                   struct drm_display_mode *mode,
5197                                   struct drm_display_mode *adjusted_mode,
5198                                   int x, int y,
5199                                   struct drm_framebuffer *fb)
5200 {
5201         struct drm_device *dev = crtc->dev;
5202         struct drm_i915_private *dev_priv = dev->dev_private;
5203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204         int pipe = intel_crtc->pipe;
5205         int plane = intel_crtc->plane;
5206         int num_connectors = 0;
5207         intel_clock_t clock, reduced_clock;
5208         u32 dpll, fp = 0, fp2 = 0;
5209         bool ok, has_reduced_clock = false;
5210         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5211         struct intel_encoder *encoder;
5212         u32 temp;
5213         int ret;
5214         bool dither;
5215
5216         for_each_encoder_on_crtc(dev, crtc, encoder) {
5217                 switch (encoder->type) {
5218                 case INTEL_OUTPUT_LVDS:
5219                         is_lvds = true;
5220                         break;
5221                 case INTEL_OUTPUT_DISPLAYPORT:
5222                         is_dp = true;
5223                         break;
5224                 case INTEL_OUTPUT_EDP:
5225                         is_dp = true;
5226                         if (!intel_encoder_is_pch_edp(&encoder->base))
5227                                 is_cpu_edp = true;
5228                         break;
5229                 }
5230
5231                 num_connectors++;
5232         }
5233
5234         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5235              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5236
5237         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5238                                      &has_reduced_clock, &reduced_clock);
5239         if (!ok) {
5240                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5241                 return -EINVAL;
5242         }
5243
5244         /* Ensure that the cursor is valid for the new mode before changing... */
5245         intel_crtc_update_cursor(crtc, true);
5246
5247         /* determine panel color depth */
5248         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5249                                               adjusted_mode);
5250         if (is_lvds && dev_priv->lvds_dither)
5251                 dither = true;
5252
5253         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5254         if (has_reduced_clock)
5255                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5256                         reduced_clock.m2;
5257
5258         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5259
5260         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5261         drm_mode_debug_printmodeline(mode);
5262
5263         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5264         if (!is_cpu_edp) {
5265                 struct intel_pch_pll *pll;
5266
5267                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5268                 if (pll == NULL) {
5269                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5270                                          pipe);
5271                         return -EINVAL;
5272                 }
5273         } else
5274                 intel_put_pch_pll(intel_crtc);
5275
5276         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5277          * This is an exception to the general rule that mode_set doesn't turn
5278          * things on.
5279          */
5280         if (is_lvds) {
5281                 temp = I915_READ(PCH_LVDS);
5282                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5283                 if (HAS_PCH_CPT(dev)) {
5284                         temp &= ~PORT_TRANS_SEL_MASK;
5285                         temp |= PORT_TRANS_SEL_CPT(pipe);
5286                 } else {
5287                         if (pipe == 1)
5288                                 temp |= LVDS_PIPEB_SELECT;
5289                         else
5290                                 temp &= ~LVDS_PIPEB_SELECT;
5291                 }
5292
5293                 /* set the corresponsding LVDS_BORDER bit */
5294                 temp |= dev_priv->lvds_border_bits;
5295                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5296                  * set the DPLLs for dual-channel mode or not.
5297                  */
5298                 if (clock.p2 == 7)
5299                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5300                 else
5301                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5302
5303                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5304                  * appropriately here, but we need to look more thoroughly into how
5305                  * panels behave in the two modes.
5306                  */
5307                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5308                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5309                         temp |= LVDS_HSYNC_POLARITY;
5310                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5311                         temp |= LVDS_VSYNC_POLARITY;
5312                 I915_WRITE(PCH_LVDS, temp);
5313         }
5314
5315         if (is_dp && !is_cpu_edp) {
5316                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5317         } else {
5318                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5319                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5320                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5321                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5322                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5323         }
5324
5325         if (intel_crtc->pch_pll) {
5326                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5327
5328                 /* Wait for the clocks to stabilize. */
5329                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5330                 udelay(150);
5331
5332                 /* The pixel multiplier can only be updated once the
5333                  * DPLL is enabled and the clocks are stable.
5334                  *
5335                  * So write it again.
5336                  */
5337                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5338         }
5339
5340         intel_crtc->lowfreq_avail = false;
5341         if (intel_crtc->pch_pll) {
5342                 if (is_lvds && has_reduced_clock && i915_powersave) {
5343                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5344                         intel_crtc->lowfreq_avail = true;
5345                 } else {
5346                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5347                 }
5348         }
5349
5350         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5351
5352         ironlake_set_m_n(crtc, mode, adjusted_mode);
5353
5354         if (is_cpu_edp)
5355                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5356
5357         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5358
5359         intel_wait_for_vblank(dev, pipe);
5360
5361         /* Set up the display plane register */
5362         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5363         POSTING_READ(DSPCNTR(plane));
5364
5365         ret = intel_pipe_set_base(crtc, x, y, fb);
5366
5367         intel_update_watermarks(dev);
5368
5369         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5370
5371         return ret;
5372 }
5373
5374 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5375                                  struct drm_display_mode *mode,
5376                                  struct drm_display_mode *adjusted_mode,
5377                                  int x, int y,
5378                                  struct drm_framebuffer *fb)
5379 {
5380         struct drm_device *dev = crtc->dev;
5381         struct drm_i915_private *dev_priv = dev->dev_private;
5382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383         int pipe = intel_crtc->pipe;
5384         int plane = intel_crtc->plane;
5385         int num_connectors = 0;
5386         intel_clock_t clock, reduced_clock;
5387         u32 dpll = 0, fp = 0, fp2 = 0;
5388         bool ok, has_reduced_clock = false;
5389         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5390         struct intel_encoder *encoder;
5391         u32 temp;
5392         int ret;
5393         bool dither;
5394
5395         for_each_encoder_on_crtc(dev, crtc, encoder) {
5396                 switch (encoder->type) {
5397                 case INTEL_OUTPUT_LVDS:
5398                         is_lvds = true;
5399                         break;
5400                 case INTEL_OUTPUT_DISPLAYPORT:
5401                         is_dp = true;
5402                         break;
5403                 case INTEL_OUTPUT_EDP:
5404                         is_dp = true;
5405                         if (!intel_encoder_is_pch_edp(&encoder->base))
5406                                 is_cpu_edp = true;
5407                         break;
5408                 }
5409
5410                 num_connectors++;
5411         }
5412
5413         if (is_cpu_edp)
5414                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5415         else
5416                 intel_crtc->cpu_transcoder = pipe;
5417
5418         /* We are not sure yet this won't happen. */
5419         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5420              INTEL_PCH_TYPE(dev));
5421
5422         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5423              num_connectors, pipe_name(pipe));
5424
5425         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5426                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5427
5428         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5429
5430         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5431                 return -EINVAL;
5432
5433         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5434                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5435                                              &has_reduced_clock,
5436                                              &reduced_clock);
5437                 if (!ok) {
5438                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5439                         return -EINVAL;
5440                 }
5441         }
5442
5443         /* Ensure that the cursor is valid for the new mode before changing... */
5444         intel_crtc_update_cursor(crtc, true);
5445
5446         /* determine panel color depth */
5447         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5448                                               adjusted_mode);
5449         if (is_lvds && dev_priv->lvds_dither)
5450                 dither = true;
5451
5452         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5453         drm_mode_debug_printmodeline(mode);
5454
5455         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5456                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5457                 if (has_reduced_clock)
5458                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5459                               reduced_clock.m2;
5460
5461                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5462                                              fp);
5463
5464                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5465                  * own on pre-Haswell/LPT generation */
5466                 if (!is_cpu_edp) {
5467                         struct intel_pch_pll *pll;
5468
5469                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5470                         if (pll == NULL) {
5471                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5472                                                  pipe);
5473                                 return -EINVAL;
5474                         }
5475                 } else
5476                         intel_put_pch_pll(intel_crtc);
5477
5478                 /* The LVDS pin pair needs to be on before the DPLLs are
5479                  * enabled.  This is an exception to the general rule that
5480                  * mode_set doesn't turn things on.
5481                  */
5482                 if (is_lvds) {
5483                         temp = I915_READ(PCH_LVDS);
5484                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5485                         if (HAS_PCH_CPT(dev)) {
5486                                 temp &= ~PORT_TRANS_SEL_MASK;
5487                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5488                         } else {
5489                                 if (pipe == 1)
5490                                         temp |= LVDS_PIPEB_SELECT;
5491                                 else
5492                                         temp &= ~LVDS_PIPEB_SELECT;
5493                         }
5494
5495                         /* set the corresponsding LVDS_BORDER bit */
5496                         temp |= dev_priv->lvds_border_bits;
5497                         /* Set the B0-B3 data pairs corresponding to whether
5498                          * we're going to set the DPLLs for dual-channel mode or
5499                          * not.
5500                          */
5501                         if (clock.p2 == 7)
5502                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5503                         else
5504                                 temp &= ~(LVDS_B0B3_POWER_UP |
5505                                           LVDS_CLKB_POWER_UP);
5506
5507                         /* It would be nice to set 24 vs 18-bit mode
5508                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5509                          * look more thoroughly into how panels behave in the
5510                          * two modes.
5511                          */
5512                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5513                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5514                                 temp |= LVDS_HSYNC_POLARITY;
5515                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5516                                 temp |= LVDS_VSYNC_POLARITY;
5517                         I915_WRITE(PCH_LVDS, temp);
5518                 }
5519         }
5520
5521         if (is_dp && !is_cpu_edp) {
5522                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5523         } else {
5524                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5525                         /* For non-DP output, clear any trans DP clock recovery
5526                          * setting.*/
5527                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5528                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5529                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5530                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5531                 }
5532         }
5533
5534         intel_crtc->lowfreq_avail = false;
5535         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5536                 if (intel_crtc->pch_pll) {
5537                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5538
5539                         /* Wait for the clocks to stabilize. */
5540                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5541                         udelay(150);
5542
5543                         /* The pixel multiplier can only be updated once the
5544                          * DPLL is enabled and the clocks are stable.
5545                          *
5546                          * So write it again.
5547                          */
5548                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5549                 }
5550
5551                 if (intel_crtc->pch_pll) {
5552                         if (is_lvds && has_reduced_clock && i915_powersave) {
5553                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5554                                 intel_crtc->lowfreq_avail = true;
5555                         } else {
5556                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5557                         }
5558                 }
5559         }
5560
5561         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5562
5563         if (!is_dp || is_cpu_edp)
5564                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5565
5566         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5567                 if (is_cpu_edp)
5568                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5569
5570         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5571
5572         /* Set up the display plane register */
5573         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5574         POSTING_READ(DSPCNTR(plane));
5575
5576         ret = intel_pipe_set_base(crtc, x, y, fb);
5577
5578         intel_update_watermarks(dev);
5579
5580         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5581
5582         return ret;
5583 }
5584
5585 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5586                                struct drm_display_mode *mode,
5587                                struct drm_display_mode *adjusted_mode,
5588                                int x, int y,
5589                                struct drm_framebuffer *fb)
5590 {
5591         struct drm_device *dev = crtc->dev;
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5594         int pipe = intel_crtc->pipe;
5595         int ret;
5596
5597         drm_vblank_pre_modeset(dev, pipe);
5598
5599         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5600                                               x, y, fb);
5601         drm_vblank_post_modeset(dev, pipe);
5602
5603         return ret;
5604 }
5605
5606 static bool intel_eld_uptodate(struct drm_connector *connector,
5607                                int reg_eldv, uint32_t bits_eldv,
5608                                int reg_elda, uint32_t bits_elda,
5609                                int reg_edid)
5610 {
5611         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5612         uint8_t *eld = connector->eld;
5613         uint32_t i;
5614
5615         i = I915_READ(reg_eldv);
5616         i &= bits_eldv;
5617
5618         if (!eld[0])
5619                 return !i;
5620
5621         if (!i)
5622                 return false;
5623
5624         i = I915_READ(reg_elda);
5625         i &= ~bits_elda;
5626         I915_WRITE(reg_elda, i);
5627
5628         for (i = 0; i < eld[2]; i++)
5629                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5630                         return false;
5631
5632         return true;
5633 }
5634
5635 static void g4x_write_eld(struct drm_connector *connector,
5636                           struct drm_crtc *crtc)
5637 {
5638         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5639         uint8_t *eld = connector->eld;
5640         uint32_t eldv;
5641         uint32_t len;
5642         uint32_t i;
5643
5644         i = I915_READ(G4X_AUD_VID_DID);
5645
5646         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5647                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5648         else
5649                 eldv = G4X_ELDV_DEVCTG;
5650
5651         if (intel_eld_uptodate(connector,
5652                                G4X_AUD_CNTL_ST, eldv,
5653                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5654                                G4X_HDMIW_HDMIEDID))
5655                 return;
5656
5657         i = I915_READ(G4X_AUD_CNTL_ST);
5658         i &= ~(eldv | G4X_ELD_ADDR);
5659         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5660         I915_WRITE(G4X_AUD_CNTL_ST, i);
5661
5662         if (!eld[0])
5663                 return;
5664
5665         len = min_t(uint8_t, eld[2], len);
5666         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5667         for (i = 0; i < len; i++)
5668                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5669
5670         i = I915_READ(G4X_AUD_CNTL_ST);
5671         i |= eldv;
5672         I915_WRITE(G4X_AUD_CNTL_ST, i);
5673 }
5674
5675 static void haswell_write_eld(struct drm_connector *connector,
5676                                      struct drm_crtc *crtc)
5677 {
5678         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5679         uint8_t *eld = connector->eld;
5680         struct drm_device *dev = crtc->dev;
5681         uint32_t eldv;
5682         uint32_t i;
5683         int len;
5684         int pipe = to_intel_crtc(crtc)->pipe;
5685         int tmp;
5686
5687         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5688         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5689         int aud_config = HSW_AUD_CFG(pipe);
5690         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5691
5692
5693         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5694
5695         /* Audio output enable */
5696         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5697         tmp = I915_READ(aud_cntrl_st2);
5698         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5699         I915_WRITE(aud_cntrl_st2, tmp);
5700
5701         /* Wait for 1 vertical blank */
5702         intel_wait_for_vblank(dev, pipe);
5703
5704         /* Set ELD valid state */
5705         tmp = I915_READ(aud_cntrl_st2);
5706         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5707         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5708         I915_WRITE(aud_cntrl_st2, tmp);
5709         tmp = I915_READ(aud_cntrl_st2);
5710         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5711
5712         /* Enable HDMI mode */
5713         tmp = I915_READ(aud_config);
5714         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5715         /* clear N_programing_enable and N_value_index */
5716         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5717         I915_WRITE(aud_config, tmp);
5718
5719         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5720
5721         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5722
5723         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5724                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5725                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5726                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5727         } else
5728                 I915_WRITE(aud_config, 0);
5729
5730         if (intel_eld_uptodate(connector,
5731                                aud_cntrl_st2, eldv,
5732                                aud_cntl_st, IBX_ELD_ADDRESS,
5733                                hdmiw_hdmiedid))
5734                 return;
5735
5736         i = I915_READ(aud_cntrl_st2);
5737         i &= ~eldv;
5738         I915_WRITE(aud_cntrl_st2, i);
5739
5740         if (!eld[0])
5741                 return;
5742
5743         i = I915_READ(aud_cntl_st);
5744         i &= ~IBX_ELD_ADDRESS;
5745         I915_WRITE(aud_cntl_st, i);
5746         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5747         DRM_DEBUG_DRIVER("port num:%d\n", i);
5748
5749         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5750         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5751         for (i = 0; i < len; i++)
5752                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5753
5754         i = I915_READ(aud_cntrl_st2);
5755         i |= eldv;
5756         I915_WRITE(aud_cntrl_st2, i);
5757
5758 }
5759
5760 static void ironlake_write_eld(struct drm_connector *connector,
5761                                      struct drm_crtc *crtc)
5762 {
5763         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5764         uint8_t *eld = connector->eld;
5765         uint32_t eldv;
5766         uint32_t i;
5767         int len;
5768         int hdmiw_hdmiedid;
5769         int aud_config;
5770         int aud_cntl_st;
5771         int aud_cntrl_st2;
5772         int pipe = to_intel_crtc(crtc)->pipe;
5773
5774         if (HAS_PCH_IBX(connector->dev)) {
5775                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5776                 aud_config = IBX_AUD_CFG(pipe);
5777                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5778                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5779         } else {
5780                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5781                 aud_config = CPT_AUD_CFG(pipe);
5782                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5783                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5784         }
5785
5786         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5787
5788         i = I915_READ(aud_cntl_st);
5789         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5790         if (!i) {
5791                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5792                 /* operate blindly on all ports */
5793                 eldv = IBX_ELD_VALIDB;
5794                 eldv |= IBX_ELD_VALIDB << 4;
5795                 eldv |= IBX_ELD_VALIDB << 8;
5796         } else {
5797                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5798                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5799         }
5800
5801         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5802                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5803                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5804                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5805         } else
5806                 I915_WRITE(aud_config, 0);
5807
5808         if (intel_eld_uptodate(connector,
5809                                aud_cntrl_st2, eldv,
5810                                aud_cntl_st, IBX_ELD_ADDRESS,
5811                                hdmiw_hdmiedid))
5812                 return;
5813
5814         i = I915_READ(aud_cntrl_st2);
5815         i &= ~eldv;
5816         I915_WRITE(aud_cntrl_st2, i);
5817
5818         if (!eld[0])
5819                 return;
5820
5821         i = I915_READ(aud_cntl_st);
5822         i &= ~IBX_ELD_ADDRESS;
5823         I915_WRITE(aud_cntl_st, i);
5824
5825         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5826         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5827         for (i = 0; i < len; i++)
5828                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5829
5830         i = I915_READ(aud_cntrl_st2);
5831         i |= eldv;
5832         I915_WRITE(aud_cntrl_st2, i);
5833 }
5834
5835 void intel_write_eld(struct drm_encoder *encoder,
5836                      struct drm_display_mode *mode)
5837 {
5838         struct drm_crtc *crtc = encoder->crtc;
5839         struct drm_connector *connector;
5840         struct drm_device *dev = encoder->dev;
5841         struct drm_i915_private *dev_priv = dev->dev_private;
5842
5843         connector = drm_select_eld(encoder, mode);
5844         if (!connector)
5845                 return;
5846
5847         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5848                          connector->base.id,
5849                          drm_get_connector_name(connector),
5850                          connector->encoder->base.id,
5851                          drm_get_encoder_name(connector->encoder));
5852
5853         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5854
5855         if (dev_priv->display.write_eld)
5856                 dev_priv->display.write_eld(connector, crtc);
5857 }
5858
5859 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5860 void intel_crtc_load_lut(struct drm_crtc *crtc)
5861 {
5862         struct drm_device *dev = crtc->dev;
5863         struct drm_i915_private *dev_priv = dev->dev_private;
5864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5865         int palreg = PALETTE(intel_crtc->pipe);
5866         int i;
5867
5868         /* The clocks have to be on to load the palette. */
5869         if (!crtc->enabled || !intel_crtc->active)
5870                 return;
5871
5872         /* use legacy palette for Ironlake */
5873         if (HAS_PCH_SPLIT(dev))
5874                 palreg = LGC_PALETTE(intel_crtc->pipe);
5875
5876         for (i = 0; i < 256; i++) {
5877                 I915_WRITE(palreg + 4 * i,
5878                            (intel_crtc->lut_r[i] << 16) |
5879                            (intel_crtc->lut_g[i] << 8) |
5880                            intel_crtc->lut_b[i]);
5881         }
5882 }
5883
5884 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5885 {
5886         struct drm_device *dev = crtc->dev;
5887         struct drm_i915_private *dev_priv = dev->dev_private;
5888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889         bool visible = base != 0;
5890         u32 cntl;
5891
5892         if (intel_crtc->cursor_visible == visible)
5893                 return;
5894
5895         cntl = I915_READ(_CURACNTR);
5896         if (visible) {
5897                 /* On these chipsets we can only modify the base whilst
5898                  * the cursor is disabled.
5899                  */
5900                 I915_WRITE(_CURABASE, base);
5901
5902                 cntl &= ~(CURSOR_FORMAT_MASK);
5903                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5904                 cntl |= CURSOR_ENABLE |
5905                         CURSOR_GAMMA_ENABLE |
5906                         CURSOR_FORMAT_ARGB;
5907         } else
5908                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5909         I915_WRITE(_CURACNTR, cntl);
5910
5911         intel_crtc->cursor_visible = visible;
5912 }
5913
5914 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5915 {
5916         struct drm_device *dev = crtc->dev;
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5919         int pipe = intel_crtc->pipe;
5920         bool visible = base != 0;
5921
5922         if (intel_crtc->cursor_visible != visible) {
5923                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5924                 if (base) {
5925                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5926                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5927                         cntl |= pipe << 28; /* Connect to correct pipe */
5928                 } else {
5929                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5930                         cntl |= CURSOR_MODE_DISABLE;
5931                 }
5932                 I915_WRITE(CURCNTR(pipe), cntl);
5933
5934                 intel_crtc->cursor_visible = visible;
5935         }
5936         /* and commit changes on next vblank */
5937         I915_WRITE(CURBASE(pipe), base);
5938 }
5939
5940 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5941 {
5942         struct drm_device *dev = crtc->dev;
5943         struct drm_i915_private *dev_priv = dev->dev_private;
5944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5945         int pipe = intel_crtc->pipe;
5946         bool visible = base != 0;
5947
5948         if (intel_crtc->cursor_visible != visible) {
5949                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5950                 if (base) {
5951                         cntl &= ~CURSOR_MODE;
5952                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5953                 } else {
5954                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5955                         cntl |= CURSOR_MODE_DISABLE;
5956                 }
5957                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5958
5959                 intel_crtc->cursor_visible = visible;
5960         }
5961         /* and commit changes on next vblank */
5962         I915_WRITE(CURBASE_IVB(pipe), base);
5963 }
5964
5965 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5966 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5967                                      bool on)
5968 {
5969         struct drm_device *dev = crtc->dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5972         int pipe = intel_crtc->pipe;
5973         int x = intel_crtc->cursor_x;
5974         int y = intel_crtc->cursor_y;
5975         u32 base, pos;
5976         bool visible;
5977
5978         pos = 0;
5979
5980         if (on && crtc->enabled && crtc->fb) {
5981                 base = intel_crtc->cursor_addr;
5982                 if (x > (int) crtc->fb->width)
5983                         base = 0;
5984
5985                 if (y > (int) crtc->fb->height)
5986                         base = 0;
5987         } else
5988                 base = 0;
5989
5990         if (x < 0) {
5991                 if (x + intel_crtc->cursor_width < 0)
5992                         base = 0;
5993
5994                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5995                 x = -x;
5996         }
5997         pos |= x << CURSOR_X_SHIFT;
5998
5999         if (y < 0) {
6000                 if (y + intel_crtc->cursor_height < 0)
6001                         base = 0;
6002
6003                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6004                 y = -y;
6005         }
6006         pos |= y << CURSOR_Y_SHIFT;
6007
6008         visible = base != 0;
6009         if (!visible && !intel_crtc->cursor_visible)
6010                 return;
6011
6012         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6013                 I915_WRITE(CURPOS_IVB(pipe), pos);
6014                 ivb_update_cursor(crtc, base);
6015         } else {
6016                 I915_WRITE(CURPOS(pipe), pos);
6017                 if (IS_845G(dev) || IS_I865G(dev))
6018                         i845_update_cursor(crtc, base);
6019                 else
6020                         i9xx_update_cursor(crtc, base);
6021         }
6022 }
6023
6024 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6025                                  struct drm_file *file,
6026                                  uint32_t handle,
6027                                  uint32_t width, uint32_t height)
6028 {
6029         struct drm_device *dev = crtc->dev;
6030         struct drm_i915_private *dev_priv = dev->dev_private;
6031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6032         struct drm_i915_gem_object *obj;
6033         uint32_t addr;
6034         int ret;
6035
6036         /* if we want to turn off the cursor ignore width and height */
6037         if (!handle) {
6038                 DRM_DEBUG_KMS("cursor off\n");
6039                 addr = 0;
6040                 obj = NULL;
6041                 mutex_lock(&dev->struct_mutex);
6042                 goto finish;
6043         }
6044
6045         /* Currently we only support 64x64 cursors */
6046         if (width != 64 || height != 64) {
6047                 DRM_ERROR("we currently only support 64x64 cursors\n");
6048                 return -EINVAL;
6049         }
6050
6051         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6052         if (&obj->base == NULL)
6053                 return -ENOENT;
6054
6055         if (obj->base.size < width * height * 4) {
6056                 DRM_ERROR("buffer is to small\n");
6057                 ret = -ENOMEM;
6058                 goto fail;
6059         }
6060
6061         /* we only need to pin inside GTT if cursor is non-phy */
6062         mutex_lock(&dev->struct_mutex);
6063         if (!dev_priv->info->cursor_needs_physical) {
6064                 if (obj->tiling_mode) {
6065                         DRM_ERROR("cursor cannot be tiled\n");
6066                         ret = -EINVAL;
6067                         goto fail_locked;
6068                 }
6069
6070                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6071                 if (ret) {
6072                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6073                         goto fail_locked;
6074                 }
6075
6076                 ret = i915_gem_object_put_fence(obj);
6077                 if (ret) {
6078                         DRM_ERROR("failed to release fence for cursor");
6079                         goto fail_unpin;
6080                 }
6081
6082                 addr = obj->gtt_offset;
6083         } else {
6084                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6085                 ret = i915_gem_attach_phys_object(dev, obj,
6086                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6087                                                   align);
6088                 if (ret) {
6089                         DRM_ERROR("failed to attach phys object\n");
6090                         goto fail_locked;
6091                 }
6092                 addr = obj->phys_obj->handle->busaddr;
6093         }
6094
6095         if (IS_GEN2(dev))
6096                 I915_WRITE(CURSIZE, (height << 12) | width);
6097
6098  finish:
6099         if (intel_crtc->cursor_bo) {
6100                 if (dev_priv->info->cursor_needs_physical) {
6101                         if (intel_crtc->cursor_bo != obj)
6102                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6103                 } else
6104                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6105                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6106         }
6107
6108         mutex_unlock(&dev->struct_mutex);
6109
6110         intel_crtc->cursor_addr = addr;
6111         intel_crtc->cursor_bo = obj;
6112         intel_crtc->cursor_width = width;
6113         intel_crtc->cursor_height = height;
6114
6115         intel_crtc_update_cursor(crtc, true);
6116
6117         return 0;
6118 fail_unpin:
6119         i915_gem_object_unpin(obj);
6120 fail_locked:
6121         mutex_unlock(&dev->struct_mutex);
6122 fail:
6123         drm_gem_object_unreference_unlocked(&obj->base);
6124         return ret;
6125 }
6126
6127 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6128 {
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130
6131         intel_crtc->cursor_x = x;
6132         intel_crtc->cursor_y = y;
6133
6134         intel_crtc_update_cursor(crtc, true);
6135
6136         return 0;
6137 }
6138
6139 /** Sets the color ramps on behalf of RandR */
6140 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6141                                  u16 blue, int regno)
6142 {
6143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6144
6145         intel_crtc->lut_r[regno] = red >> 8;
6146         intel_crtc->lut_g[regno] = green >> 8;
6147         intel_crtc->lut_b[regno] = blue >> 8;
6148 }
6149
6150 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6151                              u16 *blue, int regno)
6152 {
6153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154
6155         *red = intel_crtc->lut_r[regno] << 8;
6156         *green = intel_crtc->lut_g[regno] << 8;
6157         *blue = intel_crtc->lut_b[regno] << 8;
6158 }
6159
6160 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6161                                  u16 *blue, uint32_t start, uint32_t size)
6162 {
6163         int end = (start + size > 256) ? 256 : start + size, i;
6164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165
6166         for (i = start; i < end; i++) {
6167                 intel_crtc->lut_r[i] = red[i] >> 8;
6168                 intel_crtc->lut_g[i] = green[i] >> 8;
6169                 intel_crtc->lut_b[i] = blue[i] >> 8;
6170         }
6171
6172         intel_crtc_load_lut(crtc);
6173 }
6174
6175 /**
6176  * Get a pipe with a simple mode set on it for doing load-based monitor
6177  * detection.
6178  *
6179  * It will be up to the load-detect code to adjust the pipe as appropriate for
6180  * its requirements.  The pipe will be connected to no other encoders.
6181  *
6182  * Currently this code will only succeed if there is a pipe with no encoders
6183  * configured for it.  In the future, it could choose to temporarily disable
6184  * some outputs to free up a pipe for its use.
6185  *
6186  * \return crtc, or NULL if no pipes are available.
6187  */
6188
6189 /* VESA 640x480x72Hz mode to set on the pipe */
6190 static struct drm_display_mode load_detect_mode = {
6191         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6192                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6193 };
6194
6195 static struct drm_framebuffer *
6196 intel_framebuffer_create(struct drm_device *dev,
6197                          struct drm_mode_fb_cmd2 *mode_cmd,
6198                          struct drm_i915_gem_object *obj)
6199 {
6200         struct intel_framebuffer *intel_fb;
6201         int ret;
6202
6203         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6204         if (!intel_fb) {
6205                 drm_gem_object_unreference_unlocked(&obj->base);
6206                 return ERR_PTR(-ENOMEM);
6207         }
6208
6209         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6210         if (ret) {
6211                 drm_gem_object_unreference_unlocked(&obj->base);
6212                 kfree(intel_fb);
6213                 return ERR_PTR(ret);
6214         }
6215
6216         return &intel_fb->base;
6217 }
6218
6219 static u32
6220 intel_framebuffer_pitch_for_width(int width, int bpp)
6221 {
6222         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6223         return ALIGN(pitch, 64);
6224 }
6225
6226 static u32
6227 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6228 {
6229         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6230         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6231 }
6232
6233 static struct drm_framebuffer *
6234 intel_framebuffer_create_for_mode(struct drm_device *dev,
6235                                   struct drm_display_mode *mode,
6236                                   int depth, int bpp)
6237 {
6238         struct drm_i915_gem_object *obj;
6239         struct drm_mode_fb_cmd2 mode_cmd;
6240
6241         obj = i915_gem_alloc_object(dev,
6242                                     intel_framebuffer_size_for_mode(mode, bpp));
6243         if (obj == NULL)
6244                 return ERR_PTR(-ENOMEM);
6245
6246         mode_cmd.width = mode->hdisplay;
6247         mode_cmd.height = mode->vdisplay;
6248         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6249                                                                 bpp);
6250         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6251
6252         return intel_framebuffer_create(dev, &mode_cmd, obj);
6253 }
6254
6255 static struct drm_framebuffer *
6256 mode_fits_in_fbdev(struct drm_device *dev,
6257                    struct drm_display_mode *mode)
6258 {
6259         struct drm_i915_private *dev_priv = dev->dev_private;
6260         struct drm_i915_gem_object *obj;
6261         struct drm_framebuffer *fb;
6262
6263         if (dev_priv->fbdev == NULL)
6264                 return NULL;
6265
6266         obj = dev_priv->fbdev->ifb.obj;
6267         if (obj == NULL)
6268                 return NULL;
6269
6270         fb = &dev_priv->fbdev->ifb.base;
6271         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6272                                                                fb->bits_per_pixel))
6273                 return NULL;
6274
6275         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6276                 return NULL;
6277
6278         return fb;
6279 }
6280
6281 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6282                                 struct drm_display_mode *mode,
6283                                 struct intel_load_detect_pipe *old)
6284 {
6285         struct intel_crtc *intel_crtc;
6286         struct intel_encoder *intel_encoder =
6287                 intel_attached_encoder(connector);
6288         struct drm_crtc *possible_crtc;
6289         struct drm_encoder *encoder = &intel_encoder->base;
6290         struct drm_crtc *crtc = NULL;
6291         struct drm_device *dev = encoder->dev;
6292         struct drm_framebuffer *fb;
6293         int i = -1;
6294
6295         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6296                       connector->base.id, drm_get_connector_name(connector),
6297                       encoder->base.id, drm_get_encoder_name(encoder));
6298
6299         /*
6300          * Algorithm gets a little messy:
6301          *
6302          *   - if the connector already has an assigned crtc, use it (but make
6303          *     sure it's on first)
6304          *
6305          *   - try to find the first unused crtc that can drive this connector,
6306          *     and use that if we find one
6307          */
6308
6309         /* See if we already have a CRTC for this connector */
6310         if (encoder->crtc) {
6311                 crtc = encoder->crtc;
6312
6313                 old->dpms_mode = connector->dpms;
6314                 old->load_detect_temp = false;
6315
6316                 /* Make sure the crtc and connector are running */
6317                 if (connector->dpms != DRM_MODE_DPMS_ON)
6318                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6319
6320                 return true;
6321         }
6322
6323         /* Find an unused one (if possible) */
6324         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6325                 i++;
6326                 if (!(encoder->possible_crtcs & (1 << i)))
6327                         continue;
6328                 if (!possible_crtc->enabled) {
6329                         crtc = possible_crtc;
6330                         break;
6331                 }
6332         }
6333
6334         /*
6335          * If we didn't find an unused CRTC, don't use any.
6336          */
6337         if (!crtc) {
6338                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6339                 return false;
6340         }
6341
6342         intel_encoder->new_crtc = to_intel_crtc(crtc);
6343         to_intel_connector(connector)->new_encoder = intel_encoder;
6344
6345         intel_crtc = to_intel_crtc(crtc);
6346         old->dpms_mode = connector->dpms;
6347         old->load_detect_temp = true;
6348         old->release_fb = NULL;
6349
6350         if (!mode)
6351                 mode = &load_detect_mode;
6352
6353         /* We need a framebuffer large enough to accommodate all accesses
6354          * that the plane may generate whilst we perform load detection.
6355          * We can not rely on the fbcon either being present (we get called
6356          * during its initialisation to detect all boot displays, or it may
6357          * not even exist) or that it is large enough to satisfy the
6358          * requested mode.
6359          */
6360         fb = mode_fits_in_fbdev(dev, mode);
6361         if (fb == NULL) {
6362                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6363                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6364                 old->release_fb = fb;
6365         } else
6366                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6367         if (IS_ERR(fb)) {
6368                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6369                 goto fail;
6370         }
6371
6372         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6373                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6374                 if (old->release_fb)
6375                         old->release_fb->funcs->destroy(old->release_fb);
6376                 goto fail;
6377         }
6378
6379         /* let the connector get through one full cycle before testing */
6380         intel_wait_for_vblank(dev, intel_crtc->pipe);
6381
6382         return true;
6383 fail:
6384         connector->encoder = NULL;
6385         encoder->crtc = NULL;
6386         return false;
6387 }
6388
6389 void intel_release_load_detect_pipe(struct drm_connector *connector,
6390                                     struct intel_load_detect_pipe *old)
6391 {
6392         struct intel_encoder *intel_encoder =
6393                 intel_attached_encoder(connector);
6394         struct drm_encoder *encoder = &intel_encoder->base;
6395
6396         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6397                       connector->base.id, drm_get_connector_name(connector),
6398                       encoder->base.id, drm_get_encoder_name(encoder));
6399
6400         if (old->load_detect_temp) {
6401                 struct drm_crtc *crtc = encoder->crtc;
6402
6403                 to_intel_connector(connector)->new_encoder = NULL;
6404                 intel_encoder->new_crtc = NULL;
6405                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6406
6407                 if (old->release_fb)
6408                         old->release_fb->funcs->destroy(old->release_fb);
6409
6410                 return;
6411         }
6412
6413         /* Switch crtc and encoder back off if necessary */
6414         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6415                 connector->funcs->dpms(connector, old->dpms_mode);
6416 }
6417
6418 /* Returns the clock of the currently programmed mode of the given pipe. */
6419 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6420 {
6421         struct drm_i915_private *dev_priv = dev->dev_private;
6422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6423         int pipe = intel_crtc->pipe;
6424         u32 dpll = I915_READ(DPLL(pipe));
6425         u32 fp;
6426         intel_clock_t clock;
6427
6428         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6429                 fp = I915_READ(FP0(pipe));
6430         else
6431                 fp = I915_READ(FP1(pipe));
6432
6433         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6434         if (IS_PINEVIEW(dev)) {
6435                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6436                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6437         } else {
6438                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6439                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6440         }
6441
6442         if (!IS_GEN2(dev)) {
6443                 if (IS_PINEVIEW(dev))
6444                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6445                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6446                 else
6447                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6448                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6449
6450                 switch (dpll & DPLL_MODE_MASK) {
6451                 case DPLLB_MODE_DAC_SERIAL:
6452                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6453                                 5 : 10;
6454                         break;
6455                 case DPLLB_MODE_LVDS:
6456                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6457                                 7 : 14;
6458                         break;
6459                 default:
6460                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6461                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6462                         return 0;
6463                 }
6464
6465                 /* XXX: Handle the 100Mhz refclk */
6466                 intel_clock(dev, 96000, &clock);
6467         } else {
6468                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6469
6470                 if (is_lvds) {
6471                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6472                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6473                         clock.p2 = 14;
6474
6475                         if ((dpll & PLL_REF_INPUT_MASK) ==
6476                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6477                                 /* XXX: might not be 66MHz */
6478                                 intel_clock(dev, 66000, &clock);
6479                         } else
6480                                 intel_clock(dev, 48000, &clock);
6481                 } else {
6482                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6483                                 clock.p1 = 2;
6484                         else {
6485                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6486                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6487                         }
6488                         if (dpll & PLL_P2_DIVIDE_BY_4)
6489                                 clock.p2 = 4;
6490                         else
6491                                 clock.p2 = 2;
6492
6493                         intel_clock(dev, 48000, &clock);
6494                 }
6495         }
6496
6497         /* XXX: It would be nice to validate the clocks, but we can't reuse
6498          * i830PllIsValid() because it relies on the xf86_config connector
6499          * configuration being accurate, which it isn't necessarily.
6500          */
6501
6502         return clock.dot;
6503 }
6504
6505 /** Returns the currently programmed mode of the given pipe. */
6506 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6507                                              struct drm_crtc *crtc)
6508 {
6509         struct drm_i915_private *dev_priv = dev->dev_private;
6510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6511         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6512         struct drm_display_mode *mode;
6513         int htot = I915_READ(HTOTAL(cpu_transcoder));
6514         int hsync = I915_READ(HSYNC(cpu_transcoder));
6515         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6516         int vsync = I915_READ(VSYNC(cpu_transcoder));
6517
6518         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6519         if (!mode)
6520                 return NULL;
6521
6522         mode->clock = intel_crtc_clock_get(dev, crtc);
6523         mode->hdisplay = (htot & 0xffff) + 1;
6524         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6525         mode->hsync_start = (hsync & 0xffff) + 1;
6526         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6527         mode->vdisplay = (vtot & 0xffff) + 1;
6528         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6529         mode->vsync_start = (vsync & 0xffff) + 1;
6530         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6531
6532         drm_mode_set_name(mode);
6533
6534         return mode;
6535 }
6536
6537 static void intel_increase_pllclock(struct drm_crtc *crtc)
6538 {
6539         struct drm_device *dev = crtc->dev;
6540         drm_i915_private_t *dev_priv = dev->dev_private;
6541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6542         int pipe = intel_crtc->pipe;
6543         int dpll_reg = DPLL(pipe);
6544         int dpll;
6545
6546         if (HAS_PCH_SPLIT(dev))
6547                 return;
6548
6549         if (!dev_priv->lvds_downclock_avail)
6550                 return;
6551
6552         dpll = I915_READ(dpll_reg);
6553         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6554                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6555
6556                 assert_panel_unlocked(dev_priv, pipe);
6557
6558                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6559                 I915_WRITE(dpll_reg, dpll);
6560                 intel_wait_for_vblank(dev, pipe);
6561
6562                 dpll = I915_READ(dpll_reg);
6563                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6564                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6565         }
6566 }
6567
6568 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6569 {
6570         struct drm_device *dev = crtc->dev;
6571         drm_i915_private_t *dev_priv = dev->dev_private;
6572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6573
6574         if (HAS_PCH_SPLIT(dev))
6575                 return;
6576
6577         if (!dev_priv->lvds_downclock_avail)
6578                 return;
6579
6580         /*
6581          * Since this is called by a timer, we should never get here in
6582          * the manual case.
6583          */
6584         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6585                 int pipe = intel_crtc->pipe;
6586                 int dpll_reg = DPLL(pipe);
6587                 int dpll;
6588
6589                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6590
6591                 assert_panel_unlocked(dev_priv, pipe);
6592
6593                 dpll = I915_READ(dpll_reg);
6594                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6595                 I915_WRITE(dpll_reg, dpll);
6596                 intel_wait_for_vblank(dev, pipe);
6597                 dpll = I915_READ(dpll_reg);
6598                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6599                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6600         }
6601
6602 }
6603
6604 void intel_mark_busy(struct drm_device *dev)
6605 {
6606         i915_update_gfx_val(dev->dev_private);
6607 }
6608
6609 void intel_mark_idle(struct drm_device *dev)
6610 {
6611 }
6612
6613 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6614 {
6615         struct drm_device *dev = obj->base.dev;
6616         struct drm_crtc *crtc;
6617
6618         if (!i915_powersave)
6619                 return;
6620
6621         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6622                 if (!crtc->fb)
6623                         continue;
6624
6625                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6626                         intel_increase_pllclock(crtc);
6627         }
6628 }
6629
6630 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6631 {
6632         struct drm_device *dev = obj->base.dev;
6633         struct drm_crtc *crtc;
6634
6635         if (!i915_powersave)
6636                 return;
6637
6638         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6639                 if (!crtc->fb)
6640                         continue;
6641
6642                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6643                         intel_decrease_pllclock(crtc);
6644         }
6645 }
6646
6647 static void intel_crtc_destroy(struct drm_crtc *crtc)
6648 {
6649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650         struct drm_device *dev = crtc->dev;
6651         struct intel_unpin_work *work;
6652         unsigned long flags;
6653
6654         spin_lock_irqsave(&dev->event_lock, flags);
6655         work = intel_crtc->unpin_work;
6656         intel_crtc->unpin_work = NULL;
6657         spin_unlock_irqrestore(&dev->event_lock, flags);
6658
6659         if (work) {
6660                 cancel_work_sync(&work->work);
6661                 kfree(work);
6662         }
6663
6664         drm_crtc_cleanup(crtc);
6665
6666         kfree(intel_crtc);
6667 }
6668
6669 static void intel_unpin_work_fn(struct work_struct *__work)
6670 {
6671         struct intel_unpin_work *work =
6672                 container_of(__work, struct intel_unpin_work, work);
6673
6674         mutex_lock(&work->dev->struct_mutex);
6675         intel_unpin_fb_obj(work->old_fb_obj);
6676         drm_gem_object_unreference(&work->pending_flip_obj->base);
6677         drm_gem_object_unreference(&work->old_fb_obj->base);
6678
6679         intel_update_fbc(work->dev);
6680         mutex_unlock(&work->dev->struct_mutex);
6681         kfree(work);
6682 }
6683
6684 static void do_intel_finish_page_flip(struct drm_device *dev,
6685                                       struct drm_crtc *crtc)
6686 {
6687         drm_i915_private_t *dev_priv = dev->dev_private;
6688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6689         struct intel_unpin_work *work;
6690         struct drm_i915_gem_object *obj;
6691         struct drm_pending_vblank_event *e;
6692         struct timeval tvbl;
6693         unsigned long flags;
6694
6695         /* Ignore early vblank irqs */
6696         if (intel_crtc == NULL)
6697                 return;
6698
6699         spin_lock_irqsave(&dev->event_lock, flags);
6700         work = intel_crtc->unpin_work;
6701         if (work == NULL || !work->pending) {
6702                 spin_unlock_irqrestore(&dev->event_lock, flags);
6703                 return;
6704         }
6705
6706         intel_crtc->unpin_work = NULL;
6707
6708         if (work->event) {
6709                 e = work->event;
6710                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6711
6712                 e->event.tv_sec = tvbl.tv_sec;
6713                 e->event.tv_usec = tvbl.tv_usec;
6714
6715                 list_add_tail(&e->base.link,
6716                               &e->base.file_priv->event_list);
6717                 wake_up_interruptible(&e->base.file_priv->event_wait);
6718         }
6719
6720         drm_vblank_put(dev, intel_crtc->pipe);
6721
6722         spin_unlock_irqrestore(&dev->event_lock, flags);
6723
6724         obj = work->old_fb_obj;
6725
6726         atomic_clear_mask(1 << intel_crtc->plane,
6727                           &obj->pending_flip.counter);
6728
6729         wake_up(&dev_priv->pending_flip_queue);
6730         schedule_work(&work->work);
6731
6732         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6733 }
6734
6735 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6736 {
6737         drm_i915_private_t *dev_priv = dev->dev_private;
6738         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6739
6740         do_intel_finish_page_flip(dev, crtc);
6741 }
6742
6743 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6744 {
6745         drm_i915_private_t *dev_priv = dev->dev_private;
6746         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6747
6748         do_intel_finish_page_flip(dev, crtc);
6749 }
6750
6751 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6752 {
6753         drm_i915_private_t *dev_priv = dev->dev_private;
6754         struct intel_crtc *intel_crtc =
6755                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6756         unsigned long flags;
6757
6758         spin_lock_irqsave(&dev->event_lock, flags);
6759         if (intel_crtc->unpin_work) {
6760                 if ((++intel_crtc->unpin_work->pending) > 1)
6761                         DRM_ERROR("Prepared flip multiple times\n");
6762         } else {
6763                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6764         }
6765         spin_unlock_irqrestore(&dev->event_lock, flags);
6766 }
6767
6768 static int intel_gen2_queue_flip(struct drm_device *dev,
6769                                  struct drm_crtc *crtc,
6770                                  struct drm_framebuffer *fb,
6771                                  struct drm_i915_gem_object *obj)
6772 {
6773         struct drm_i915_private *dev_priv = dev->dev_private;
6774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6775         u32 flip_mask;
6776         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6777         int ret;
6778
6779         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6780         if (ret)
6781                 goto err;
6782
6783         ret = intel_ring_begin(ring, 6);
6784         if (ret)
6785                 goto err_unpin;
6786
6787         /* Can't queue multiple flips, so wait for the previous
6788          * one to finish before executing the next.
6789          */
6790         if (intel_crtc->plane)
6791                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6792         else
6793                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6794         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6795         intel_ring_emit(ring, MI_NOOP);
6796         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6797                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6798         intel_ring_emit(ring, fb->pitches[0]);
6799         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6800         intel_ring_emit(ring, 0); /* aux display base address, unused */
6801         intel_ring_advance(ring);
6802         return 0;
6803
6804 err_unpin:
6805         intel_unpin_fb_obj(obj);
6806 err:
6807         return ret;
6808 }
6809
6810 static int intel_gen3_queue_flip(struct drm_device *dev,
6811                                  struct drm_crtc *crtc,
6812                                  struct drm_framebuffer *fb,
6813                                  struct drm_i915_gem_object *obj)
6814 {
6815         struct drm_i915_private *dev_priv = dev->dev_private;
6816         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6817         u32 flip_mask;
6818         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6819         int ret;
6820
6821         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6822         if (ret)
6823                 goto err;
6824
6825         ret = intel_ring_begin(ring, 6);
6826         if (ret)
6827                 goto err_unpin;
6828
6829         if (intel_crtc->plane)
6830                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6831         else
6832                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6833         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6834         intel_ring_emit(ring, MI_NOOP);
6835         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6836                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6837         intel_ring_emit(ring, fb->pitches[0]);
6838         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6839         intel_ring_emit(ring, MI_NOOP);
6840
6841         intel_ring_advance(ring);
6842         return 0;
6843
6844 err_unpin:
6845         intel_unpin_fb_obj(obj);
6846 err:
6847         return ret;
6848 }
6849
6850 static int intel_gen4_queue_flip(struct drm_device *dev,
6851                                  struct drm_crtc *crtc,
6852                                  struct drm_framebuffer *fb,
6853                                  struct drm_i915_gem_object *obj)
6854 {
6855         struct drm_i915_private *dev_priv = dev->dev_private;
6856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6857         uint32_t pf, pipesrc;
6858         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6859         int ret;
6860
6861         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6862         if (ret)
6863                 goto err;
6864
6865         ret = intel_ring_begin(ring, 4);
6866         if (ret)
6867                 goto err_unpin;
6868
6869         /* i965+ uses the linear or tiled offsets from the
6870          * Display Registers (which do not change across a page-flip)
6871          * so we need only reprogram the base address.
6872          */
6873         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6874                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6875         intel_ring_emit(ring, fb->pitches[0]);
6876         intel_ring_emit(ring,
6877                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6878                         obj->tiling_mode);
6879
6880         /* XXX Enabling the panel-fitter across page-flip is so far
6881          * untested on non-native modes, so ignore it for now.
6882          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6883          */
6884         pf = 0;
6885         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6886         intel_ring_emit(ring, pf | pipesrc);
6887         intel_ring_advance(ring);
6888         return 0;
6889
6890 err_unpin:
6891         intel_unpin_fb_obj(obj);
6892 err:
6893         return ret;
6894 }
6895
6896 static int intel_gen6_queue_flip(struct drm_device *dev,
6897                                  struct drm_crtc *crtc,
6898                                  struct drm_framebuffer *fb,
6899                                  struct drm_i915_gem_object *obj)
6900 {
6901         struct drm_i915_private *dev_priv = dev->dev_private;
6902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6903         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6904         uint32_t pf, pipesrc;
6905         int ret;
6906
6907         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6908         if (ret)
6909                 goto err;
6910
6911         ret = intel_ring_begin(ring, 4);
6912         if (ret)
6913                 goto err_unpin;
6914
6915         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6916                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6917         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6918         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6919
6920         /* Contrary to the suggestions in the documentation,
6921          * "Enable Panel Fitter" does not seem to be required when page
6922          * flipping with a non-native mode, and worse causes a normal
6923          * modeset to fail.
6924          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6925          */
6926         pf = 0;
6927         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6928         intel_ring_emit(ring, pf | pipesrc);
6929         intel_ring_advance(ring);
6930         return 0;
6931
6932 err_unpin:
6933         intel_unpin_fb_obj(obj);
6934 err:
6935         return ret;
6936 }
6937
6938 /*
6939  * On gen7 we currently use the blit ring because (in early silicon at least)
6940  * the render ring doesn't give us interrpts for page flip completion, which
6941  * means clients will hang after the first flip is queued.  Fortunately the
6942  * blit ring generates interrupts properly, so use it instead.
6943  */
6944 static int intel_gen7_queue_flip(struct drm_device *dev,
6945                                  struct drm_crtc *crtc,
6946                                  struct drm_framebuffer *fb,
6947                                  struct drm_i915_gem_object *obj)
6948 {
6949         struct drm_i915_private *dev_priv = dev->dev_private;
6950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6952         uint32_t plane_bit = 0;
6953         int ret;
6954
6955         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6956         if (ret)
6957                 goto err;
6958
6959         switch(intel_crtc->plane) {
6960         case PLANE_A:
6961                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6962                 break;
6963         case PLANE_B:
6964                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6965                 break;
6966         case PLANE_C:
6967                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6968                 break;
6969         default:
6970                 WARN_ONCE(1, "unknown plane in flip command\n");
6971                 ret = -ENODEV;
6972                 goto err_unpin;
6973         }
6974
6975         ret = intel_ring_begin(ring, 4);
6976         if (ret)
6977                 goto err_unpin;
6978
6979         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6980         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6981         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6982         intel_ring_emit(ring, (MI_NOOP));
6983         intel_ring_advance(ring);
6984         return 0;
6985
6986 err_unpin:
6987         intel_unpin_fb_obj(obj);
6988 err:
6989         return ret;
6990 }
6991
6992 static int intel_default_queue_flip(struct drm_device *dev,
6993                                     struct drm_crtc *crtc,
6994                                     struct drm_framebuffer *fb,
6995                                     struct drm_i915_gem_object *obj)
6996 {
6997         return -ENODEV;
6998 }
6999
7000 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7001                                 struct drm_framebuffer *fb,
7002                                 struct drm_pending_vblank_event *event)
7003 {
7004         struct drm_device *dev = crtc->dev;
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006         struct intel_framebuffer *intel_fb;
7007         struct drm_i915_gem_object *obj;
7008         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7009         struct intel_unpin_work *work;
7010         unsigned long flags;
7011         int ret;
7012
7013         /* Can't change pixel format via MI display flips. */
7014         if (fb->pixel_format != crtc->fb->pixel_format)
7015                 return -EINVAL;
7016
7017         /*
7018          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7019          * Note that pitch changes could also affect these register.
7020          */
7021         if (INTEL_INFO(dev)->gen > 3 &&
7022             (fb->offsets[0] != crtc->fb->offsets[0] ||
7023              fb->pitches[0] != crtc->fb->pitches[0]))
7024                 return -EINVAL;
7025
7026         work = kzalloc(sizeof *work, GFP_KERNEL);
7027         if (work == NULL)
7028                 return -ENOMEM;
7029
7030         work->event = event;
7031         work->dev = crtc->dev;
7032         intel_fb = to_intel_framebuffer(crtc->fb);
7033         work->old_fb_obj = intel_fb->obj;
7034         INIT_WORK(&work->work, intel_unpin_work_fn);
7035
7036         ret = drm_vblank_get(dev, intel_crtc->pipe);
7037         if (ret)
7038                 goto free_work;
7039
7040         /* We borrow the event spin lock for protecting unpin_work */
7041         spin_lock_irqsave(&dev->event_lock, flags);
7042         if (intel_crtc->unpin_work) {
7043                 spin_unlock_irqrestore(&dev->event_lock, flags);
7044                 kfree(work);
7045                 drm_vblank_put(dev, intel_crtc->pipe);
7046
7047                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7048                 return -EBUSY;
7049         }
7050         intel_crtc->unpin_work = work;
7051         spin_unlock_irqrestore(&dev->event_lock, flags);
7052
7053         intel_fb = to_intel_framebuffer(fb);
7054         obj = intel_fb->obj;
7055
7056         ret = i915_mutex_lock_interruptible(dev);
7057         if (ret)
7058                 goto cleanup;
7059
7060         /* Reference the objects for the scheduled work. */
7061         drm_gem_object_reference(&work->old_fb_obj->base);
7062         drm_gem_object_reference(&obj->base);
7063
7064         crtc->fb = fb;
7065
7066         work->pending_flip_obj = obj;
7067
7068         work->enable_stall_check = true;
7069
7070         /* Block clients from rendering to the new back buffer until
7071          * the flip occurs and the object is no longer visible.
7072          */
7073         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7074
7075         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7076         if (ret)
7077                 goto cleanup_pending;
7078
7079         intel_disable_fbc(dev);
7080         intel_mark_fb_busy(obj);
7081         mutex_unlock(&dev->struct_mutex);
7082
7083         trace_i915_flip_request(intel_crtc->plane, obj);
7084
7085         return 0;
7086
7087 cleanup_pending:
7088         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7089         drm_gem_object_unreference(&work->old_fb_obj->base);
7090         drm_gem_object_unreference(&obj->base);
7091         mutex_unlock(&dev->struct_mutex);
7092
7093 cleanup:
7094         spin_lock_irqsave(&dev->event_lock, flags);
7095         intel_crtc->unpin_work = NULL;
7096         spin_unlock_irqrestore(&dev->event_lock, flags);
7097
7098         drm_vblank_put(dev, intel_crtc->pipe);
7099 free_work:
7100         kfree(work);
7101
7102         return ret;
7103 }
7104
7105 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7106         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7107         .load_lut = intel_crtc_load_lut,
7108         .disable = intel_crtc_noop,
7109 };
7110
7111 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7112 {
7113         struct intel_encoder *other_encoder;
7114         struct drm_crtc *crtc = &encoder->new_crtc->base;
7115
7116         if (WARN_ON(!crtc))
7117                 return false;
7118
7119         list_for_each_entry(other_encoder,
7120                             &crtc->dev->mode_config.encoder_list,
7121                             base.head) {
7122
7123                 if (&other_encoder->new_crtc->base != crtc ||
7124                     encoder == other_encoder)
7125                         continue;
7126                 else
7127                         return true;
7128         }
7129
7130         return false;
7131 }
7132
7133 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7134                                   struct drm_crtc *crtc)
7135 {
7136         struct drm_device *dev;
7137         struct drm_crtc *tmp;
7138         int crtc_mask = 1;
7139
7140         WARN(!crtc, "checking null crtc?\n");
7141
7142         dev = crtc->dev;
7143
7144         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7145                 if (tmp == crtc)
7146                         break;
7147                 crtc_mask <<= 1;
7148         }
7149
7150         if (encoder->possible_crtcs & crtc_mask)
7151                 return true;
7152         return false;
7153 }
7154
7155 /**
7156  * intel_modeset_update_staged_output_state
7157  *
7158  * Updates the staged output configuration state, e.g. after we've read out the
7159  * current hw state.
7160  */
7161 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7162 {
7163         struct intel_encoder *encoder;
7164         struct intel_connector *connector;
7165
7166         list_for_each_entry(connector, &dev->mode_config.connector_list,
7167                             base.head) {
7168                 connector->new_encoder =
7169                         to_intel_encoder(connector->base.encoder);
7170         }
7171
7172         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7173                             base.head) {
7174                 encoder->new_crtc =
7175                         to_intel_crtc(encoder->base.crtc);
7176         }
7177 }
7178
7179 /**
7180  * intel_modeset_commit_output_state
7181  *
7182  * This function copies the stage display pipe configuration to the real one.
7183  */
7184 static void intel_modeset_commit_output_state(struct drm_device *dev)
7185 {
7186         struct intel_encoder *encoder;
7187         struct intel_connector *connector;
7188
7189         list_for_each_entry(connector, &dev->mode_config.connector_list,
7190                             base.head) {
7191                 connector->base.encoder = &connector->new_encoder->base;
7192         }
7193
7194         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7195                             base.head) {
7196                 encoder->base.crtc = &encoder->new_crtc->base;
7197         }
7198 }
7199
7200 static struct drm_display_mode *
7201 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7202                             struct drm_display_mode *mode)
7203 {
7204         struct drm_device *dev = crtc->dev;
7205         struct drm_display_mode *adjusted_mode;
7206         struct drm_encoder_helper_funcs *encoder_funcs;
7207         struct intel_encoder *encoder;
7208
7209         adjusted_mode = drm_mode_duplicate(dev, mode);
7210         if (!adjusted_mode)
7211                 return ERR_PTR(-ENOMEM);
7212
7213         /* Pass our mode to the connectors and the CRTC to give them a chance to
7214          * adjust it according to limitations or connector properties, and also
7215          * a chance to reject the mode entirely.
7216          */
7217         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7218                             base.head) {
7219
7220                 if (&encoder->new_crtc->base != crtc)
7221                         continue;
7222                 encoder_funcs = encoder->base.helper_private;
7223                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7224                                                 adjusted_mode))) {
7225                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7226                         goto fail;
7227                 }
7228         }
7229
7230         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7231                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7232                 goto fail;
7233         }
7234         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7235
7236         return adjusted_mode;
7237 fail:
7238         drm_mode_destroy(dev, adjusted_mode);
7239         return ERR_PTR(-EINVAL);
7240 }
7241
7242 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7243  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7244 static void
7245 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7246                              unsigned *prepare_pipes, unsigned *disable_pipes)
7247 {
7248         struct intel_crtc *intel_crtc;
7249         struct drm_device *dev = crtc->dev;
7250         struct intel_encoder *encoder;
7251         struct intel_connector *connector;
7252         struct drm_crtc *tmp_crtc;
7253
7254         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7255
7256         /* Check which crtcs have changed outputs connected to them, these need
7257          * to be part of the prepare_pipes mask. We don't (yet) support global
7258          * modeset across multiple crtcs, so modeset_pipes will only have one
7259          * bit set at most. */
7260         list_for_each_entry(connector, &dev->mode_config.connector_list,
7261                             base.head) {
7262                 if (connector->base.encoder == &connector->new_encoder->base)
7263                         continue;
7264
7265                 if (connector->base.encoder) {
7266                         tmp_crtc = connector->base.encoder->crtc;
7267
7268                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7269                 }
7270
7271                 if (connector->new_encoder)
7272                         *prepare_pipes |=
7273                                 1 << connector->new_encoder->new_crtc->pipe;
7274         }
7275
7276         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7277                             base.head) {
7278                 if (encoder->base.crtc == &encoder->new_crtc->base)
7279                         continue;
7280
7281                 if (encoder->base.crtc) {
7282                         tmp_crtc = encoder->base.crtc;
7283
7284                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7285                 }
7286
7287                 if (encoder->new_crtc)
7288                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7289         }
7290
7291         /* Check for any pipes that will be fully disabled ... */
7292         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7293                             base.head) {
7294                 bool used = false;
7295
7296                 /* Don't try to disable disabled crtcs. */
7297                 if (!intel_crtc->base.enabled)
7298                         continue;
7299
7300                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7301                                     base.head) {
7302                         if (encoder->new_crtc == intel_crtc)
7303                                 used = true;
7304                 }
7305
7306                 if (!used)
7307                         *disable_pipes |= 1 << intel_crtc->pipe;
7308         }
7309
7310
7311         /* set_mode is also used to update properties on life display pipes. */
7312         intel_crtc = to_intel_crtc(crtc);
7313         if (crtc->enabled)
7314                 *prepare_pipes |= 1 << intel_crtc->pipe;
7315
7316         /* We only support modeset on one single crtc, hence we need to do that
7317          * only for the passed in crtc iff we change anything else than just
7318          * disable crtcs.
7319          *
7320          * This is actually not true, to be fully compatible with the old crtc
7321          * helper we automatically disable _any_ output (i.e. doesn't need to be
7322          * connected to the crtc we're modesetting on) if it's disconnected.
7323          * Which is a rather nutty api (since changed the output configuration
7324          * without userspace's explicit request can lead to confusion), but
7325          * alas. Hence we currently need to modeset on all pipes we prepare. */
7326         if (*prepare_pipes)
7327                 *modeset_pipes = *prepare_pipes;
7328
7329         /* ... and mask these out. */
7330         *modeset_pipes &= ~(*disable_pipes);
7331         *prepare_pipes &= ~(*disable_pipes);
7332 }
7333
7334 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7335 {
7336         struct drm_encoder *encoder;
7337         struct drm_device *dev = crtc->dev;
7338
7339         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7340                 if (encoder->crtc == crtc)
7341                         return true;
7342
7343         return false;
7344 }
7345
7346 static void
7347 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7348 {
7349         struct intel_encoder *intel_encoder;
7350         struct intel_crtc *intel_crtc;
7351         struct drm_connector *connector;
7352
7353         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7354                             base.head) {
7355                 if (!intel_encoder->base.crtc)
7356                         continue;
7357
7358                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7359
7360                 if (prepare_pipes & (1 << intel_crtc->pipe))
7361                         intel_encoder->connectors_active = false;
7362         }
7363
7364         intel_modeset_commit_output_state(dev);
7365
7366         /* Update computed state. */
7367         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7368                             base.head) {
7369                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7370         }
7371
7372         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7373                 if (!connector->encoder || !connector->encoder->crtc)
7374                         continue;
7375
7376                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7377
7378                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7379                         struct drm_property *dpms_property =
7380                                 dev->mode_config.dpms_property;
7381
7382                         connector->dpms = DRM_MODE_DPMS_ON;
7383                         drm_connector_property_set_value(connector,
7384                                                          dpms_property,
7385                                                          DRM_MODE_DPMS_ON);
7386
7387                         intel_encoder = to_intel_encoder(connector->encoder);
7388                         intel_encoder->connectors_active = true;
7389                 }
7390         }
7391
7392 }
7393
7394 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7395         list_for_each_entry((intel_crtc), \
7396                             &(dev)->mode_config.crtc_list, \
7397                             base.head) \
7398                 if (mask & (1 <<(intel_crtc)->pipe)) \
7399
7400 void
7401 intel_modeset_check_state(struct drm_device *dev)
7402 {
7403         struct intel_crtc *crtc;
7404         struct intel_encoder *encoder;
7405         struct intel_connector *connector;
7406
7407         list_for_each_entry(connector, &dev->mode_config.connector_list,
7408                             base.head) {
7409                 /* This also checks the encoder/connector hw state with the
7410                  * ->get_hw_state callbacks. */
7411                 intel_connector_check_state(connector);
7412
7413                 WARN(&connector->new_encoder->base != connector->base.encoder,
7414                      "connector's staged encoder doesn't match current encoder\n");
7415         }
7416
7417         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7418                             base.head) {
7419                 bool enabled = false;
7420                 bool active = false;
7421                 enum pipe pipe, tracked_pipe;
7422
7423                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7424                               encoder->base.base.id,
7425                               drm_get_encoder_name(&encoder->base));
7426
7427                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7428                      "encoder's stage crtc doesn't match current crtc\n");
7429                 WARN(encoder->connectors_active && !encoder->base.crtc,
7430                      "encoder's active_connectors set, but no crtc\n");
7431
7432                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7433                                     base.head) {
7434                         if (connector->base.encoder != &encoder->base)
7435                                 continue;
7436                         enabled = true;
7437                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7438                                 active = true;
7439                 }
7440                 WARN(!!encoder->base.crtc != enabled,
7441                      "encoder's enabled state mismatch "
7442                      "(expected %i, found %i)\n",
7443                      !!encoder->base.crtc, enabled);
7444                 WARN(active && !encoder->base.crtc,
7445                      "active encoder with no crtc\n");
7446
7447                 WARN(encoder->connectors_active != active,
7448                      "encoder's computed active state doesn't match tracked active state "
7449                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7450
7451                 active = encoder->get_hw_state(encoder, &pipe);
7452                 WARN(active != encoder->connectors_active,
7453                      "encoder's hw state doesn't match sw tracking "
7454                      "(expected %i, found %i)\n",
7455                      encoder->connectors_active, active);
7456
7457                 if (!encoder->base.crtc)
7458                         continue;
7459
7460                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7461                 WARN(active && pipe != tracked_pipe,
7462                      "active encoder's pipe doesn't match"
7463                      "(expected %i, found %i)\n",
7464                      tracked_pipe, pipe);
7465
7466         }
7467
7468         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7469                             base.head) {
7470                 bool enabled = false;
7471                 bool active = false;
7472
7473                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7474                               crtc->base.base.id);
7475
7476                 WARN(crtc->active && !crtc->base.enabled,
7477                      "active crtc, but not enabled in sw tracking\n");
7478
7479                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7480                                     base.head) {
7481                         if (encoder->base.crtc != &crtc->base)
7482                                 continue;
7483                         enabled = true;
7484                         if (encoder->connectors_active)
7485                                 active = true;
7486                 }
7487                 WARN(active != crtc->active,
7488                      "crtc's computed active state doesn't match tracked active state "
7489                      "(expected %i, found %i)\n", active, crtc->active);
7490                 WARN(enabled != crtc->base.enabled,
7491                      "crtc's computed enabled state doesn't match tracked enabled state "
7492                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7493
7494                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7495         }
7496 }
7497
7498 bool intel_set_mode(struct drm_crtc *crtc,
7499                     struct drm_display_mode *mode,
7500                     int x, int y, struct drm_framebuffer *fb)
7501 {
7502         struct drm_device *dev = crtc->dev;
7503         drm_i915_private_t *dev_priv = dev->dev_private;
7504         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7505         struct drm_encoder_helper_funcs *encoder_funcs;
7506         struct drm_encoder *encoder;
7507         struct intel_crtc *intel_crtc;
7508         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7509         bool ret = true;
7510
7511         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7512                                      &prepare_pipes, &disable_pipes);
7513
7514         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7515                       modeset_pipes, prepare_pipes, disable_pipes);
7516
7517         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7518                 intel_crtc_disable(&intel_crtc->base);
7519
7520         saved_hwmode = crtc->hwmode;
7521         saved_mode = crtc->mode;
7522
7523         /* Hack: Because we don't (yet) support global modeset on multiple
7524          * crtcs, we don't keep track of the new mode for more than one crtc.
7525          * Hence simply check whether any bit is set in modeset_pipes in all the
7526          * pieces of code that are not yet converted to deal with mutliple crtcs
7527          * changing their mode at the same time. */
7528         adjusted_mode = NULL;
7529         if (modeset_pipes) {
7530                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7531                 if (IS_ERR(adjusted_mode)) {
7532                         return false;
7533                 }
7534         }
7535
7536         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7537                 if (intel_crtc->base.enabled)
7538                         dev_priv->display.crtc_disable(&intel_crtc->base);
7539         }
7540
7541         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7542          * to set it here already despite that we pass it down the callchain.
7543          */
7544         if (modeset_pipes)
7545                 crtc->mode = *mode;
7546
7547         /* Only after disabling all output pipelines that will be changed can we
7548          * update the the output configuration. */
7549         intel_modeset_update_state(dev, prepare_pipes);
7550
7551         if (dev_priv->display.modeset_global_resources)
7552                 dev_priv->display.modeset_global_resources(dev);
7553
7554         /* Set up the DPLL and any encoders state that needs to adjust or depend
7555          * on the DPLL.
7556          */
7557         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7558                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7559                                            mode, adjusted_mode,
7560                                            x, y, fb);
7561                 if (!ret)
7562                     goto done;
7563
7564                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7565
7566                         if (encoder->crtc != &intel_crtc->base)
7567                                 continue;
7568
7569                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7570                                 encoder->base.id, drm_get_encoder_name(encoder),
7571                                 mode->base.id, mode->name);
7572                         encoder_funcs = encoder->helper_private;
7573                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7574                 }
7575         }
7576
7577         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7578         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7579                 dev_priv->display.crtc_enable(&intel_crtc->base);
7580
7581         if (modeset_pipes) {
7582                 /* Store real post-adjustment hardware mode. */
7583                 crtc->hwmode = *adjusted_mode;
7584
7585                 /* Calculate and store various constants which
7586                  * are later needed by vblank and swap-completion
7587                  * timestamping. They are derived from true hwmode.
7588                  */
7589                 drm_calc_timestamping_constants(crtc);
7590         }
7591
7592         /* FIXME: add subpixel order */
7593 done:
7594         drm_mode_destroy(dev, adjusted_mode);
7595         if (!ret && crtc->enabled) {
7596                 crtc->hwmode = saved_hwmode;
7597                 crtc->mode = saved_mode;
7598         } else {
7599                 intel_modeset_check_state(dev);
7600         }
7601
7602         return ret;
7603 }
7604
7605 #undef for_each_intel_crtc_masked
7606
7607 static void intel_set_config_free(struct intel_set_config *config)
7608 {
7609         if (!config)
7610                 return;
7611
7612         kfree(config->save_connector_encoders);
7613         kfree(config->save_encoder_crtcs);
7614         kfree(config);
7615 }
7616
7617 static int intel_set_config_save_state(struct drm_device *dev,
7618                                        struct intel_set_config *config)
7619 {
7620         struct drm_encoder *encoder;
7621         struct drm_connector *connector;
7622         int count;
7623
7624         config->save_encoder_crtcs =
7625                 kcalloc(dev->mode_config.num_encoder,
7626                         sizeof(struct drm_crtc *), GFP_KERNEL);
7627         if (!config->save_encoder_crtcs)
7628                 return -ENOMEM;
7629
7630         config->save_connector_encoders =
7631                 kcalloc(dev->mode_config.num_connector,
7632                         sizeof(struct drm_encoder *), GFP_KERNEL);
7633         if (!config->save_connector_encoders)
7634                 return -ENOMEM;
7635
7636         /* Copy data. Note that driver private data is not affected.
7637          * Should anything bad happen only the expected state is
7638          * restored, not the drivers personal bookkeeping.
7639          */
7640         count = 0;
7641         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7642                 config->save_encoder_crtcs[count++] = encoder->crtc;
7643         }
7644
7645         count = 0;
7646         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7647                 config->save_connector_encoders[count++] = connector->encoder;
7648         }
7649
7650         return 0;
7651 }
7652
7653 static void intel_set_config_restore_state(struct drm_device *dev,
7654                                            struct intel_set_config *config)
7655 {
7656         struct intel_encoder *encoder;
7657         struct intel_connector *connector;
7658         int count;
7659
7660         count = 0;
7661         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7662                 encoder->new_crtc =
7663                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7664         }
7665
7666         count = 0;
7667         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7668                 connector->new_encoder =
7669                         to_intel_encoder(config->save_connector_encoders[count++]);
7670         }
7671 }
7672
7673 static void
7674 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7675                                       struct intel_set_config *config)
7676 {
7677
7678         /* We should be able to check here if the fb has the same properties
7679          * and then just flip_or_move it */
7680         if (set->crtc->fb != set->fb) {
7681                 /* If we have no fb then treat it as a full mode set */
7682                 if (set->crtc->fb == NULL) {
7683                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7684                         config->mode_changed = true;
7685                 } else if (set->fb == NULL) {
7686                         config->mode_changed = true;
7687                 } else if (set->fb->depth != set->crtc->fb->depth) {
7688                         config->mode_changed = true;
7689                 } else if (set->fb->bits_per_pixel !=
7690                            set->crtc->fb->bits_per_pixel) {
7691                         config->mode_changed = true;
7692                 } else
7693                         config->fb_changed = true;
7694         }
7695
7696         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7697                 config->fb_changed = true;
7698
7699         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7700                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7701                 drm_mode_debug_printmodeline(&set->crtc->mode);
7702                 drm_mode_debug_printmodeline(set->mode);
7703                 config->mode_changed = true;
7704         }
7705 }
7706
7707 static int
7708 intel_modeset_stage_output_state(struct drm_device *dev,
7709                                  struct drm_mode_set *set,
7710                                  struct intel_set_config *config)
7711 {
7712         struct drm_crtc *new_crtc;
7713         struct intel_connector *connector;
7714         struct intel_encoder *encoder;
7715         int count, ro;
7716
7717         /* The upper layers ensure that we either disabl a crtc or have a list
7718          * of connectors. For paranoia, double-check this. */
7719         WARN_ON(!set->fb && (set->num_connectors != 0));
7720         WARN_ON(set->fb && (set->num_connectors == 0));
7721
7722         count = 0;
7723         list_for_each_entry(connector, &dev->mode_config.connector_list,
7724                             base.head) {
7725                 /* Otherwise traverse passed in connector list and get encoders
7726                  * for them. */
7727                 for (ro = 0; ro < set->num_connectors; ro++) {
7728                         if (set->connectors[ro] == &connector->base) {
7729                                 connector->new_encoder = connector->encoder;
7730                                 break;
7731                         }
7732                 }
7733
7734                 /* If we disable the crtc, disable all its connectors. Also, if
7735                  * the connector is on the changing crtc but not on the new
7736                  * connector list, disable it. */
7737                 if ((!set->fb || ro == set->num_connectors) &&
7738                     connector->base.encoder &&
7739                     connector->base.encoder->crtc == set->crtc) {
7740                         connector->new_encoder = NULL;
7741
7742                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7743                                 connector->base.base.id,
7744                                 drm_get_connector_name(&connector->base));
7745                 }
7746
7747
7748                 if (&connector->new_encoder->base != connector->base.encoder) {
7749                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7750                         config->mode_changed = true;
7751                 }
7752
7753                 /* Disable all disconnected encoders. */
7754                 if (connector->base.status == connector_status_disconnected)
7755                         connector->new_encoder = NULL;
7756         }
7757         /* connector->new_encoder is now updated for all connectors. */
7758
7759         /* Update crtc of enabled connectors. */
7760         count = 0;
7761         list_for_each_entry(connector, &dev->mode_config.connector_list,
7762                             base.head) {
7763                 if (!connector->new_encoder)
7764                         continue;
7765
7766                 new_crtc = connector->new_encoder->base.crtc;
7767
7768                 for (ro = 0; ro < set->num_connectors; ro++) {
7769                         if (set->connectors[ro] == &connector->base)
7770                                 new_crtc = set->crtc;
7771                 }
7772
7773                 /* Make sure the new CRTC will work with the encoder */
7774                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7775                                            new_crtc)) {
7776                         return -EINVAL;
7777                 }
7778                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7779
7780                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7781                         connector->base.base.id,
7782                         drm_get_connector_name(&connector->base),
7783                         new_crtc->base.id);
7784         }
7785
7786         /* Check for any encoders that needs to be disabled. */
7787         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7788                             base.head) {
7789                 list_for_each_entry(connector,
7790                                     &dev->mode_config.connector_list,
7791                                     base.head) {
7792                         if (connector->new_encoder == encoder) {
7793                                 WARN_ON(!connector->new_encoder->new_crtc);
7794
7795                                 goto next_encoder;
7796                         }
7797                 }
7798                 encoder->new_crtc = NULL;
7799 next_encoder:
7800                 /* Only now check for crtc changes so we don't miss encoders
7801                  * that will be disabled. */
7802                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7803                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7804                         config->mode_changed = true;
7805                 }
7806         }
7807         /* Now we've also updated encoder->new_crtc for all encoders. */
7808
7809         return 0;
7810 }
7811
7812 static int intel_crtc_set_config(struct drm_mode_set *set)
7813 {
7814         struct drm_device *dev;
7815         struct drm_mode_set save_set;
7816         struct intel_set_config *config;
7817         int ret;
7818
7819         BUG_ON(!set);
7820         BUG_ON(!set->crtc);
7821         BUG_ON(!set->crtc->helper_private);
7822
7823         if (!set->mode)
7824                 set->fb = NULL;
7825
7826         /* The fb helper likes to play gross jokes with ->mode_set_config.
7827          * Unfortunately the crtc helper doesn't do much at all for this case,
7828          * so we have to cope with this madness until the fb helper is fixed up. */
7829         if (set->fb && set->num_connectors == 0)
7830                 return 0;
7831
7832         if (set->fb) {
7833                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7834                                 set->crtc->base.id, set->fb->base.id,
7835                                 (int)set->num_connectors, set->x, set->y);
7836         } else {
7837                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7838         }
7839
7840         dev = set->crtc->dev;
7841
7842         ret = -ENOMEM;
7843         config = kzalloc(sizeof(*config), GFP_KERNEL);
7844         if (!config)
7845                 goto out_config;
7846
7847         ret = intel_set_config_save_state(dev, config);
7848         if (ret)
7849                 goto out_config;
7850
7851         save_set.crtc = set->crtc;
7852         save_set.mode = &set->crtc->mode;
7853         save_set.x = set->crtc->x;
7854         save_set.y = set->crtc->y;
7855         save_set.fb = set->crtc->fb;
7856
7857         /* Compute whether we need a full modeset, only an fb base update or no
7858          * change at all. In the future we might also check whether only the
7859          * mode changed, e.g. for LVDS where we only change the panel fitter in
7860          * such cases. */
7861         intel_set_config_compute_mode_changes(set, config);
7862
7863         ret = intel_modeset_stage_output_state(dev, set, config);
7864         if (ret)
7865                 goto fail;
7866
7867         if (config->mode_changed) {
7868                 if (set->mode) {
7869                         DRM_DEBUG_KMS("attempting to set mode from"
7870                                         " userspace\n");
7871                         drm_mode_debug_printmodeline(set->mode);
7872                 }
7873
7874                 if (!intel_set_mode(set->crtc, set->mode,
7875                                     set->x, set->y, set->fb)) {
7876                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7877                                   set->crtc->base.id);
7878                         ret = -EINVAL;
7879                         goto fail;
7880                 }
7881         } else if (config->fb_changed) {
7882                 ret = intel_pipe_set_base(set->crtc,
7883                                           set->x, set->y, set->fb);
7884         }
7885
7886         intel_set_config_free(config);
7887
7888         return 0;
7889
7890 fail:
7891         intel_set_config_restore_state(dev, config);
7892
7893         /* Try to restore the config */
7894         if (config->mode_changed &&
7895             !intel_set_mode(save_set.crtc, save_set.mode,
7896                             save_set.x, save_set.y, save_set.fb))
7897                 DRM_ERROR("failed to restore config after modeset failure\n");
7898
7899 out_config:
7900         intel_set_config_free(config);
7901         return ret;
7902 }
7903
7904 static const struct drm_crtc_funcs intel_crtc_funcs = {
7905         .cursor_set = intel_crtc_cursor_set,
7906         .cursor_move = intel_crtc_cursor_move,
7907         .gamma_set = intel_crtc_gamma_set,
7908         .set_config = intel_crtc_set_config,
7909         .destroy = intel_crtc_destroy,
7910         .page_flip = intel_crtc_page_flip,
7911 };
7912
7913 static void intel_cpu_pll_init(struct drm_device *dev)
7914 {
7915         if (IS_HASWELL(dev))
7916                 intel_ddi_pll_init(dev);
7917 }
7918
7919 static void intel_pch_pll_init(struct drm_device *dev)
7920 {
7921         drm_i915_private_t *dev_priv = dev->dev_private;
7922         int i;
7923
7924         if (dev_priv->num_pch_pll == 0) {
7925                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7926                 return;
7927         }
7928
7929         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7930                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7931                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7932                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7933         }
7934 }
7935
7936 static void intel_crtc_init(struct drm_device *dev, int pipe)
7937 {
7938         drm_i915_private_t *dev_priv = dev->dev_private;
7939         struct intel_crtc *intel_crtc;
7940         int i;
7941
7942         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7943         if (intel_crtc == NULL)
7944                 return;
7945
7946         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7947
7948         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7949         for (i = 0; i < 256; i++) {
7950                 intel_crtc->lut_r[i] = i;
7951                 intel_crtc->lut_g[i] = i;
7952                 intel_crtc->lut_b[i] = i;
7953         }
7954
7955         /* Swap pipes & planes for FBC on pre-965 */
7956         intel_crtc->pipe = pipe;
7957         intel_crtc->plane = pipe;
7958         intel_crtc->cpu_transcoder = pipe;
7959         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7960                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7961                 intel_crtc->plane = !pipe;
7962         }
7963
7964         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7965                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7966         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7967         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7968
7969         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7970
7971         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7972 }
7973
7974 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7975                                 struct drm_file *file)
7976 {
7977         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7978         struct drm_mode_object *drmmode_obj;
7979         struct intel_crtc *crtc;
7980
7981         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7982                 return -ENODEV;
7983
7984         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7985                         DRM_MODE_OBJECT_CRTC);
7986
7987         if (!drmmode_obj) {
7988                 DRM_ERROR("no such CRTC id\n");
7989                 return -EINVAL;
7990         }
7991
7992         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7993         pipe_from_crtc_id->pipe = crtc->pipe;
7994
7995         return 0;
7996 }
7997
7998 static int intel_encoder_clones(struct intel_encoder *encoder)
7999 {
8000         struct drm_device *dev = encoder->base.dev;
8001         struct intel_encoder *source_encoder;
8002         int index_mask = 0;
8003         int entry = 0;
8004
8005         list_for_each_entry(source_encoder,
8006                             &dev->mode_config.encoder_list, base.head) {
8007
8008                 if (encoder == source_encoder)
8009                         index_mask |= (1 << entry);
8010
8011                 /* Intel hw has only one MUX where enocoders could be cloned. */
8012                 if (encoder->cloneable && source_encoder->cloneable)
8013                         index_mask |= (1 << entry);
8014
8015                 entry++;
8016         }
8017
8018         return index_mask;
8019 }
8020
8021 static bool has_edp_a(struct drm_device *dev)
8022 {
8023         struct drm_i915_private *dev_priv = dev->dev_private;
8024
8025         if (!IS_MOBILE(dev))
8026                 return false;
8027
8028         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8029                 return false;
8030
8031         if (IS_GEN5(dev) &&
8032             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8033                 return false;
8034
8035         return true;
8036 }
8037
8038 static void intel_setup_outputs(struct drm_device *dev)
8039 {
8040         struct drm_i915_private *dev_priv = dev->dev_private;
8041         struct intel_encoder *encoder;
8042         bool dpd_is_edp = false;
8043         bool has_lvds;
8044
8045         has_lvds = intel_lvds_init(dev);
8046         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8047                 /* disable the panel fitter on everything but LVDS */
8048                 I915_WRITE(PFIT_CONTROL, 0);
8049         }
8050
8051         if (HAS_PCH_SPLIT(dev)) {
8052                 dpd_is_edp = intel_dpd_is_edp(dev);
8053
8054                 if (has_edp_a(dev))
8055                         intel_dp_init(dev, DP_A, PORT_A);
8056
8057                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8058                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8059         }
8060
8061         intel_crt_init(dev);
8062
8063         if (IS_HASWELL(dev)) {
8064                 int found;
8065
8066                 /* Haswell uses DDI functions to detect digital outputs */
8067                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8068                 /* DDI A only supports eDP */
8069                 if (found)
8070                         intel_ddi_init(dev, PORT_A);
8071
8072                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8073                  * register */
8074                 found = I915_READ(SFUSE_STRAP);
8075
8076                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8077                         intel_ddi_init(dev, PORT_B);
8078                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8079                         intel_ddi_init(dev, PORT_C);
8080                 if (found & SFUSE_STRAP_DDID_DETECTED)
8081                         intel_ddi_init(dev, PORT_D);
8082         } else if (HAS_PCH_SPLIT(dev)) {
8083                 int found;
8084
8085                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8086                         /* PCH SDVOB multiplex with HDMIB */
8087                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8088                         if (!found)
8089                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8090                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8091                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8092                 }
8093
8094                 if (I915_READ(HDMIC) & PORT_DETECTED)
8095                         intel_hdmi_init(dev, HDMIC, PORT_C);
8096
8097                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8098                         intel_hdmi_init(dev, HDMID, PORT_D);
8099
8100                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8101                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8102
8103                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8104                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8105         } else if (IS_VALLEYVIEW(dev)) {
8106                 int found;
8107
8108                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8109                 if (I915_READ(DP_C) & DP_DETECTED)
8110                         intel_dp_init(dev, DP_C, PORT_C);
8111
8112                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8113                         /* SDVOB multiplex with HDMIB */
8114                         found = intel_sdvo_init(dev, SDVOB, true);
8115                         if (!found)
8116                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8117                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8118                                 intel_dp_init(dev, DP_B, PORT_B);
8119                 }
8120
8121                 if (I915_READ(SDVOC) & PORT_DETECTED)
8122                         intel_hdmi_init(dev, SDVOC, PORT_C);
8123
8124         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8125                 bool found = false;
8126
8127                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8128                         DRM_DEBUG_KMS("probing SDVOB\n");
8129                         found = intel_sdvo_init(dev, SDVOB, true);
8130                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8131                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8132                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8133                         }
8134
8135                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8136                                 DRM_DEBUG_KMS("probing DP_B\n");
8137                                 intel_dp_init(dev, DP_B, PORT_B);
8138                         }
8139                 }
8140
8141                 /* Before G4X SDVOC doesn't have its own detect register */
8142
8143                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8144                         DRM_DEBUG_KMS("probing SDVOC\n");
8145                         found = intel_sdvo_init(dev, SDVOC, false);
8146                 }
8147
8148                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8149
8150                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8151                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8152                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8153                         }
8154                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8155                                 DRM_DEBUG_KMS("probing DP_C\n");
8156                                 intel_dp_init(dev, DP_C, PORT_C);
8157                         }
8158                 }
8159
8160                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8161                     (I915_READ(DP_D) & DP_DETECTED)) {
8162                         DRM_DEBUG_KMS("probing DP_D\n");
8163                         intel_dp_init(dev, DP_D, PORT_D);
8164                 }
8165         } else if (IS_GEN2(dev))
8166                 intel_dvo_init(dev);
8167
8168         if (SUPPORTS_TV(dev))
8169                 intel_tv_init(dev);
8170
8171         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8172                 encoder->base.possible_crtcs = encoder->crtc_mask;
8173                 encoder->base.possible_clones =
8174                         intel_encoder_clones(encoder);
8175         }
8176
8177         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8178                 ironlake_init_pch_refclk(dev);
8179 }
8180
8181 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8182 {
8183         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8184
8185         drm_framebuffer_cleanup(fb);
8186         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8187
8188         kfree(intel_fb);
8189 }
8190
8191 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8192                                                 struct drm_file *file,
8193                                                 unsigned int *handle)
8194 {
8195         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8196         struct drm_i915_gem_object *obj = intel_fb->obj;
8197
8198         return drm_gem_handle_create(file, &obj->base, handle);
8199 }
8200
8201 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8202         .destroy = intel_user_framebuffer_destroy,
8203         .create_handle = intel_user_framebuffer_create_handle,
8204 };
8205
8206 int intel_framebuffer_init(struct drm_device *dev,
8207                            struct intel_framebuffer *intel_fb,
8208                            struct drm_mode_fb_cmd2 *mode_cmd,
8209                            struct drm_i915_gem_object *obj)
8210 {
8211         int ret;
8212
8213         if (obj->tiling_mode == I915_TILING_Y)
8214                 return -EINVAL;
8215
8216         if (mode_cmd->pitches[0] & 63)
8217                 return -EINVAL;
8218
8219         switch (mode_cmd->pixel_format) {
8220         case DRM_FORMAT_RGB332:
8221         case DRM_FORMAT_RGB565:
8222         case DRM_FORMAT_XRGB8888:
8223         case DRM_FORMAT_XBGR8888:
8224         case DRM_FORMAT_ARGB8888:
8225         case DRM_FORMAT_XRGB2101010:
8226         case DRM_FORMAT_ARGB2101010:
8227                 /* RGB formats are common across chipsets */
8228                 break;
8229         case DRM_FORMAT_YUYV:
8230         case DRM_FORMAT_UYVY:
8231         case DRM_FORMAT_YVYU:
8232         case DRM_FORMAT_VYUY:
8233                 break;
8234         default:
8235                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8236                                 mode_cmd->pixel_format);
8237                 return -EINVAL;
8238         }
8239
8240         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8241         if (ret) {
8242                 DRM_ERROR("framebuffer init failed %d\n", ret);
8243                 return ret;
8244         }
8245
8246         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8247         intel_fb->obj = obj;
8248         return 0;
8249 }
8250
8251 static struct drm_framebuffer *
8252 intel_user_framebuffer_create(struct drm_device *dev,
8253                               struct drm_file *filp,
8254                               struct drm_mode_fb_cmd2 *mode_cmd)
8255 {
8256         struct drm_i915_gem_object *obj;
8257
8258         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8259                                                 mode_cmd->handles[0]));
8260         if (&obj->base == NULL)
8261                 return ERR_PTR(-ENOENT);
8262
8263         return intel_framebuffer_create(dev, mode_cmd, obj);
8264 }
8265
8266 static const struct drm_mode_config_funcs intel_mode_funcs = {
8267         .fb_create = intel_user_framebuffer_create,
8268         .output_poll_changed = intel_fb_output_poll_changed,
8269 };
8270
8271 /* Set up chip specific display functions */
8272 static void intel_init_display(struct drm_device *dev)
8273 {
8274         struct drm_i915_private *dev_priv = dev->dev_private;
8275
8276         /* We always want a DPMS function */
8277         if (IS_HASWELL(dev)) {
8278                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8279                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8280                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8281                 dev_priv->display.off = haswell_crtc_off;
8282                 dev_priv->display.update_plane = ironlake_update_plane;
8283         } else if (HAS_PCH_SPLIT(dev)) {
8284                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8285                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8286                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8287                 dev_priv->display.off = ironlake_crtc_off;
8288                 dev_priv->display.update_plane = ironlake_update_plane;
8289         } else {
8290                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8291                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8292                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8293                 dev_priv->display.off = i9xx_crtc_off;
8294                 dev_priv->display.update_plane = i9xx_update_plane;
8295         }
8296
8297         /* Returns the core display clock speed */
8298         if (IS_VALLEYVIEW(dev))
8299                 dev_priv->display.get_display_clock_speed =
8300                         valleyview_get_display_clock_speed;
8301         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8302                 dev_priv->display.get_display_clock_speed =
8303                         i945_get_display_clock_speed;
8304         else if (IS_I915G(dev))
8305                 dev_priv->display.get_display_clock_speed =
8306                         i915_get_display_clock_speed;
8307         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8308                 dev_priv->display.get_display_clock_speed =
8309                         i9xx_misc_get_display_clock_speed;
8310         else if (IS_I915GM(dev))
8311                 dev_priv->display.get_display_clock_speed =
8312                         i915gm_get_display_clock_speed;
8313         else if (IS_I865G(dev))
8314                 dev_priv->display.get_display_clock_speed =
8315                         i865_get_display_clock_speed;
8316         else if (IS_I85X(dev))
8317                 dev_priv->display.get_display_clock_speed =
8318                         i855_get_display_clock_speed;
8319         else /* 852, 830 */
8320                 dev_priv->display.get_display_clock_speed =
8321                         i830_get_display_clock_speed;
8322
8323         if (HAS_PCH_SPLIT(dev)) {
8324                 if (IS_GEN5(dev)) {
8325                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8326                         dev_priv->display.write_eld = ironlake_write_eld;
8327                 } else if (IS_GEN6(dev)) {
8328                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8329                         dev_priv->display.write_eld = ironlake_write_eld;
8330                 } else if (IS_IVYBRIDGE(dev)) {
8331                         /* FIXME: detect B0+ stepping and use auto training */
8332                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8333                         dev_priv->display.write_eld = ironlake_write_eld;
8334                 } else if (IS_HASWELL(dev)) {
8335                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8336                         dev_priv->display.write_eld = haswell_write_eld;
8337                 } else
8338                         dev_priv->display.update_wm = NULL;
8339         } else if (IS_G4X(dev)) {
8340                 dev_priv->display.write_eld = g4x_write_eld;
8341         }
8342
8343         /* Default just returns -ENODEV to indicate unsupported */
8344         dev_priv->display.queue_flip = intel_default_queue_flip;
8345
8346         switch (INTEL_INFO(dev)->gen) {
8347         case 2:
8348                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8349                 break;
8350
8351         case 3:
8352                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8353                 break;
8354
8355         case 4:
8356         case 5:
8357                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8358                 break;
8359
8360         case 6:
8361                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8362                 break;
8363         case 7:
8364                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8365                 break;
8366         }
8367 }
8368
8369 /*
8370  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8371  * resume, or other times.  This quirk makes sure that's the case for
8372  * affected systems.
8373  */
8374 static void quirk_pipea_force(struct drm_device *dev)
8375 {
8376         struct drm_i915_private *dev_priv = dev->dev_private;
8377
8378         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8379         DRM_INFO("applying pipe a force quirk\n");
8380 }
8381
8382 /*
8383  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8384  */
8385 static void quirk_ssc_force_disable(struct drm_device *dev)
8386 {
8387         struct drm_i915_private *dev_priv = dev->dev_private;
8388         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8389         DRM_INFO("applying lvds SSC disable quirk\n");
8390 }
8391
8392 /*
8393  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8394  * brightness value
8395  */
8396 static void quirk_invert_brightness(struct drm_device *dev)
8397 {
8398         struct drm_i915_private *dev_priv = dev->dev_private;
8399         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8400         DRM_INFO("applying inverted panel brightness quirk\n");
8401 }
8402
8403 struct intel_quirk {
8404         int device;
8405         int subsystem_vendor;
8406         int subsystem_device;
8407         void (*hook)(struct drm_device *dev);
8408 };
8409
8410 static struct intel_quirk intel_quirks[] = {
8411         /* HP Mini needs pipe A force quirk (LP: #322104) */
8412         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8413
8414         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8415         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8416
8417         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8418         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8419
8420         /* 830/845 need to leave pipe A & dpll A up */
8421         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8422         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8423
8424         /* Lenovo U160 cannot use SSC on LVDS */
8425         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8426
8427         /* Sony Vaio Y cannot use SSC on LVDS */
8428         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8429
8430         /* Acer Aspire 5734Z must invert backlight brightness */
8431         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8432 };
8433
8434 static void intel_init_quirks(struct drm_device *dev)
8435 {
8436         struct pci_dev *d = dev->pdev;
8437         int i;
8438
8439         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8440                 struct intel_quirk *q = &intel_quirks[i];
8441
8442                 if (d->device == q->device &&
8443                     (d->subsystem_vendor == q->subsystem_vendor ||
8444                      q->subsystem_vendor == PCI_ANY_ID) &&
8445                     (d->subsystem_device == q->subsystem_device ||
8446                      q->subsystem_device == PCI_ANY_ID))
8447                         q->hook(dev);
8448         }
8449 }
8450
8451 /* Disable the VGA plane that we never use */
8452 static void i915_disable_vga(struct drm_device *dev)
8453 {
8454         struct drm_i915_private *dev_priv = dev->dev_private;
8455         u8 sr1;
8456         u32 vga_reg;
8457
8458         if (HAS_PCH_SPLIT(dev))
8459                 vga_reg = CPU_VGACNTRL;
8460         else
8461                 vga_reg = VGACNTRL;
8462
8463         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8464         outb(SR01, VGA_SR_INDEX);
8465         sr1 = inb(VGA_SR_DATA);
8466         outb(sr1 | 1<<5, VGA_SR_DATA);
8467         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8468         udelay(300);
8469
8470         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8471         POSTING_READ(vga_reg);
8472 }
8473
8474 void intel_modeset_init_hw(struct drm_device *dev)
8475 {
8476         /* We attempt to init the necessary power wells early in the initialization
8477          * time, so the subsystems that expect power to be enabled can work.
8478          */
8479         intel_init_power_wells(dev);
8480
8481         intel_prepare_ddi(dev);
8482
8483         intel_init_clock_gating(dev);
8484
8485         mutex_lock(&dev->struct_mutex);
8486         intel_enable_gt_powersave(dev);
8487         mutex_unlock(&dev->struct_mutex);
8488 }
8489
8490 void intel_modeset_init(struct drm_device *dev)
8491 {
8492         struct drm_i915_private *dev_priv = dev->dev_private;
8493         int i, ret;
8494
8495         drm_mode_config_init(dev);
8496
8497         dev->mode_config.min_width = 0;
8498         dev->mode_config.min_height = 0;
8499
8500         dev->mode_config.preferred_depth = 24;
8501         dev->mode_config.prefer_shadow = 1;
8502
8503         dev->mode_config.funcs = &intel_mode_funcs;
8504
8505         intel_init_quirks(dev);
8506
8507         intel_init_pm(dev);
8508
8509         intel_init_display(dev);
8510
8511         if (IS_GEN2(dev)) {
8512                 dev->mode_config.max_width = 2048;
8513                 dev->mode_config.max_height = 2048;
8514         } else if (IS_GEN3(dev)) {
8515                 dev->mode_config.max_width = 4096;
8516                 dev->mode_config.max_height = 4096;
8517         } else {
8518                 dev->mode_config.max_width = 8192;
8519                 dev->mode_config.max_height = 8192;
8520         }
8521         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8522
8523         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8524                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8525
8526         for (i = 0; i < dev_priv->num_pipe; i++) {
8527                 intel_crtc_init(dev, i);
8528                 ret = intel_plane_init(dev, i);
8529                 if (ret)
8530                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8531         }
8532
8533         intel_cpu_pll_init(dev);
8534         intel_pch_pll_init(dev);
8535
8536         /* Just disable it once at startup */
8537         i915_disable_vga(dev);
8538         intel_setup_outputs(dev);
8539 }
8540
8541 static void
8542 intel_connector_break_all_links(struct intel_connector *connector)
8543 {
8544         connector->base.dpms = DRM_MODE_DPMS_OFF;
8545         connector->base.encoder = NULL;
8546         connector->encoder->connectors_active = false;
8547         connector->encoder->base.crtc = NULL;
8548 }
8549
8550 static void intel_enable_pipe_a(struct drm_device *dev)
8551 {
8552         struct intel_connector *connector;
8553         struct drm_connector *crt = NULL;
8554         struct intel_load_detect_pipe load_detect_temp;
8555
8556         /* We can't just switch on the pipe A, we need to set things up with a
8557          * proper mode and output configuration. As a gross hack, enable pipe A
8558          * by enabling the load detect pipe once. */
8559         list_for_each_entry(connector,
8560                             &dev->mode_config.connector_list,
8561                             base.head) {
8562                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8563                         crt = &connector->base;
8564                         break;
8565                 }
8566         }
8567
8568         if (!crt)
8569                 return;
8570
8571         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8572                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8573
8574
8575 }
8576
8577 static bool
8578 intel_check_plane_mapping(struct intel_crtc *crtc)
8579 {
8580         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8581         u32 reg, val;
8582
8583         if (dev_priv->num_pipe == 1)
8584                 return true;
8585
8586         reg = DSPCNTR(!crtc->plane);
8587         val = I915_READ(reg);
8588
8589         if ((val & DISPLAY_PLANE_ENABLE) &&
8590             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8591                 return false;
8592
8593         return true;
8594 }
8595
8596 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8597 {
8598         struct drm_device *dev = crtc->base.dev;
8599         struct drm_i915_private *dev_priv = dev->dev_private;
8600         u32 reg;
8601
8602         /* Clear any frame start delays used for debugging left by the BIOS */
8603         reg = PIPECONF(crtc->cpu_transcoder);
8604         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8605
8606         /* We need to sanitize the plane -> pipe mapping first because this will
8607          * disable the crtc (and hence change the state) if it is wrong. Note
8608          * that gen4+ has a fixed plane -> pipe mapping.  */
8609         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8610                 struct intel_connector *connector;
8611                 bool plane;
8612
8613                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8614                               crtc->base.base.id);
8615
8616                 /* Pipe has the wrong plane attached and the plane is active.
8617                  * Temporarily change the plane mapping and disable everything
8618                  * ...  */
8619                 plane = crtc->plane;
8620                 crtc->plane = !plane;
8621                 dev_priv->display.crtc_disable(&crtc->base);
8622                 crtc->plane = plane;
8623
8624                 /* ... and break all links. */
8625                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8626                                     base.head) {
8627                         if (connector->encoder->base.crtc != &crtc->base)
8628                                 continue;
8629
8630                         intel_connector_break_all_links(connector);
8631                 }
8632
8633                 WARN_ON(crtc->active);
8634                 crtc->base.enabled = false;
8635         }
8636
8637         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8638             crtc->pipe == PIPE_A && !crtc->active) {
8639                 /* BIOS forgot to enable pipe A, this mostly happens after
8640                  * resume. Force-enable the pipe to fix this, the update_dpms
8641                  * call below we restore the pipe to the right state, but leave
8642                  * the required bits on. */
8643                 intel_enable_pipe_a(dev);
8644         }
8645
8646         /* Adjust the state of the output pipe according to whether we
8647          * have active connectors/encoders. */
8648         intel_crtc_update_dpms(&crtc->base);
8649
8650         if (crtc->active != crtc->base.enabled) {
8651                 struct intel_encoder *encoder;
8652
8653                 /* This can happen either due to bugs in the get_hw_state
8654                  * functions or because the pipe is force-enabled due to the
8655                  * pipe A quirk. */
8656                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8657                               crtc->base.base.id,
8658                               crtc->base.enabled ? "enabled" : "disabled",
8659                               crtc->active ? "enabled" : "disabled");
8660
8661                 crtc->base.enabled = crtc->active;
8662
8663                 /* Because we only establish the connector -> encoder ->
8664                  * crtc links if something is active, this means the
8665                  * crtc is now deactivated. Break the links. connector
8666                  * -> encoder links are only establish when things are
8667                  *  actually up, hence no need to break them. */
8668                 WARN_ON(crtc->active);
8669
8670                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8671                         WARN_ON(encoder->connectors_active);
8672                         encoder->base.crtc = NULL;
8673                 }
8674         }
8675 }
8676
8677 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8678 {
8679         struct intel_connector *connector;
8680         struct drm_device *dev = encoder->base.dev;
8681
8682         /* We need to check both for a crtc link (meaning that the
8683          * encoder is active and trying to read from a pipe) and the
8684          * pipe itself being active. */
8685         bool has_active_crtc = encoder->base.crtc &&
8686                 to_intel_crtc(encoder->base.crtc)->active;
8687
8688         if (encoder->connectors_active && !has_active_crtc) {
8689                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8690                               encoder->base.base.id,
8691                               drm_get_encoder_name(&encoder->base));
8692
8693                 /* Connector is active, but has no active pipe. This is
8694                  * fallout from our resume register restoring. Disable
8695                  * the encoder manually again. */
8696                 if (encoder->base.crtc) {
8697                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8698                                       encoder->base.base.id,
8699                                       drm_get_encoder_name(&encoder->base));
8700                         encoder->disable(encoder);
8701                 }
8702
8703                 /* Inconsistent output/port/pipe state happens presumably due to
8704                  * a bug in one of the get_hw_state functions. Or someplace else
8705                  * in our code, like the register restore mess on resume. Clamp
8706                  * things to off as a safer default. */
8707                 list_for_each_entry(connector,
8708                                     &dev->mode_config.connector_list,
8709                                     base.head) {
8710                         if (connector->encoder != encoder)
8711                                 continue;
8712
8713                         intel_connector_break_all_links(connector);
8714                 }
8715         }
8716         /* Enabled encoders without active connectors will be fixed in
8717          * the crtc fixup. */
8718 }
8719
8720 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8721  * and i915 state tracking structures. */
8722 void intel_modeset_setup_hw_state(struct drm_device *dev)
8723 {
8724         struct drm_i915_private *dev_priv = dev->dev_private;
8725         enum pipe pipe;
8726         u32 tmp;
8727         struct intel_crtc *crtc;
8728         struct intel_encoder *encoder;
8729         struct intel_connector *connector;
8730
8731         if (IS_HASWELL(dev)) {
8732                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8733
8734                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8735                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8736                         case TRANS_DDI_EDP_INPUT_A_ON:
8737                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8738                                 pipe = PIPE_A;
8739                                 break;
8740                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8741                                 pipe = PIPE_B;
8742                                 break;
8743                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8744                                 pipe = PIPE_C;
8745                                 break;
8746                         }
8747
8748                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8749                         crtc->cpu_transcoder = TRANSCODER_EDP;
8750
8751                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8752                                       pipe_name(pipe));
8753                 }
8754         }
8755
8756         for_each_pipe(pipe) {
8757                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8758
8759                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8760                 if (tmp & PIPECONF_ENABLE)
8761                         crtc->active = true;
8762                 else
8763                         crtc->active = false;
8764
8765                 crtc->base.enabled = crtc->active;
8766
8767                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8768                               crtc->base.base.id,
8769                               crtc->active ? "enabled" : "disabled");
8770         }
8771
8772         if (IS_HASWELL(dev))
8773                 intel_ddi_setup_hw_pll_state(dev);
8774
8775         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8776                             base.head) {
8777                 pipe = 0;
8778
8779                 if (encoder->get_hw_state(encoder, &pipe)) {
8780                         encoder->base.crtc =
8781                                 dev_priv->pipe_to_crtc_mapping[pipe];
8782                 } else {
8783                         encoder->base.crtc = NULL;
8784                 }
8785
8786                 encoder->connectors_active = false;
8787                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8788                               encoder->base.base.id,
8789                               drm_get_encoder_name(&encoder->base),
8790                               encoder->base.crtc ? "enabled" : "disabled",
8791                               pipe);
8792         }
8793
8794         list_for_each_entry(connector, &dev->mode_config.connector_list,
8795                             base.head) {
8796                 if (connector->get_hw_state(connector)) {
8797                         connector->base.dpms = DRM_MODE_DPMS_ON;
8798                         connector->encoder->connectors_active = true;
8799                         connector->base.encoder = &connector->encoder->base;
8800                 } else {
8801                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8802                         connector->base.encoder = NULL;
8803                 }
8804                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8805                               connector->base.base.id,
8806                               drm_get_connector_name(&connector->base),
8807                               connector->base.encoder ? "enabled" : "disabled");
8808         }
8809
8810         /* HW state is read out, now we need to sanitize this mess. */
8811         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8812                             base.head) {
8813                 intel_sanitize_encoder(encoder);
8814         }
8815
8816         for_each_pipe(pipe) {
8817                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8818                 intel_sanitize_crtc(crtc);
8819         }
8820
8821         intel_modeset_update_staged_output_state(dev);
8822
8823         intel_modeset_check_state(dev);
8824
8825         drm_mode_config_reset(dev);
8826 }
8827
8828 void intel_modeset_gem_init(struct drm_device *dev)
8829 {
8830         intel_modeset_init_hw(dev);
8831
8832         intel_setup_overlay(dev);
8833
8834         intel_modeset_setup_hw_state(dev);
8835 }
8836
8837 void intel_modeset_cleanup(struct drm_device *dev)
8838 {
8839         struct drm_i915_private *dev_priv = dev->dev_private;
8840         struct drm_crtc *crtc;
8841         struct intel_crtc *intel_crtc;
8842
8843         drm_kms_helper_poll_fini(dev);
8844         mutex_lock(&dev->struct_mutex);
8845
8846         intel_unregister_dsm_handler();
8847
8848
8849         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8850                 /* Skip inactive CRTCs */
8851                 if (!crtc->fb)
8852                         continue;
8853
8854                 intel_crtc = to_intel_crtc(crtc);
8855                 intel_increase_pllclock(crtc);
8856         }
8857
8858         intel_disable_fbc(dev);
8859
8860         intel_disable_gt_powersave(dev);
8861
8862         ironlake_teardown_rc6(dev);
8863
8864         if (IS_VALLEYVIEW(dev))
8865                 vlv_init_dpio(dev);
8866
8867         mutex_unlock(&dev->struct_mutex);
8868
8869         /* Disable the irq before mode object teardown, for the irq might
8870          * enqueue unpin/hotplug work. */
8871         drm_irq_uninstall(dev);
8872         cancel_work_sync(&dev_priv->hotplug_work);
8873         cancel_work_sync(&dev_priv->rps.work);
8874
8875         /* flush any delayed tasks or pending work */
8876         flush_scheduled_work();
8877
8878         drm_mode_config_cleanup(dev);
8879 }
8880
8881 /*
8882  * Return which encoder is currently attached for connector.
8883  */
8884 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8885 {
8886         return &intel_attached_encoder(connector)->base;
8887 }
8888
8889 void intel_connector_attach_encoder(struct intel_connector *connector,
8890                                     struct intel_encoder *encoder)
8891 {
8892         connector->encoder = encoder;
8893         drm_mode_connector_attach_encoder(&connector->base,
8894                                           &encoder->base);
8895 }
8896
8897 /*
8898  * set vga decode state - true == enable VGA decode
8899  */
8900 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8901 {
8902         struct drm_i915_private *dev_priv = dev->dev_private;
8903         u16 gmch_ctrl;
8904
8905         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8906         if (state)
8907                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8908         else
8909                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8910         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8911         return 0;
8912 }
8913
8914 #ifdef CONFIG_DEBUG_FS
8915 #include <linux/seq_file.h>
8916
8917 struct intel_display_error_state {
8918         struct intel_cursor_error_state {
8919                 u32 control;
8920                 u32 position;
8921                 u32 base;
8922                 u32 size;
8923         } cursor[I915_MAX_PIPES];
8924
8925         struct intel_pipe_error_state {
8926                 u32 conf;
8927                 u32 source;
8928
8929                 u32 htotal;
8930                 u32 hblank;
8931                 u32 hsync;
8932                 u32 vtotal;
8933                 u32 vblank;
8934                 u32 vsync;
8935         } pipe[I915_MAX_PIPES];
8936
8937         struct intel_plane_error_state {
8938                 u32 control;
8939                 u32 stride;
8940                 u32 size;
8941                 u32 pos;
8942                 u32 addr;
8943                 u32 surface;
8944                 u32 tile_offset;
8945         } plane[I915_MAX_PIPES];
8946 };
8947
8948 struct intel_display_error_state *
8949 intel_display_capture_error_state(struct drm_device *dev)
8950 {
8951         drm_i915_private_t *dev_priv = dev->dev_private;
8952         struct intel_display_error_state *error;
8953         enum transcoder cpu_transcoder;
8954         int i;
8955
8956         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8957         if (error == NULL)
8958                 return NULL;
8959
8960         for_each_pipe(i) {
8961                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8962
8963                 error->cursor[i].control = I915_READ(CURCNTR(i));
8964                 error->cursor[i].position = I915_READ(CURPOS(i));
8965                 error->cursor[i].base = I915_READ(CURBASE(i));
8966
8967                 error->plane[i].control = I915_READ(DSPCNTR(i));
8968                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8969                 error->plane[i].size = I915_READ(DSPSIZE(i));
8970                 error->plane[i].pos = I915_READ(DSPPOS(i));
8971                 error->plane[i].addr = I915_READ(DSPADDR(i));
8972                 if (INTEL_INFO(dev)->gen >= 4) {
8973                         error->plane[i].surface = I915_READ(DSPSURF(i));
8974                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8975                 }
8976
8977                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
8978                 error->pipe[i].source = I915_READ(PIPESRC(i));
8979                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8980                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8981                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8982                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8983                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8984                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
8985         }
8986
8987         return error;
8988 }
8989
8990 void
8991 intel_display_print_error_state(struct seq_file *m,
8992                                 struct drm_device *dev,
8993                                 struct intel_display_error_state *error)
8994 {
8995         drm_i915_private_t *dev_priv = dev->dev_private;
8996         int i;
8997
8998         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8999         for_each_pipe(i) {
9000                 seq_printf(m, "Pipe [%d]:\n", i);
9001                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9002                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9003                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9004                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9005                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9006                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9007                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9008                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9009
9010                 seq_printf(m, "Plane [%d]:\n", i);
9011                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9012                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9013                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9014                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9015                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9016                 if (INTEL_INFO(dev)->gen >= 4) {
9017                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9018                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9019                 }
9020
9021                 seq_printf(m, "Cursor [%d]:\n", i);
9022                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9023                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9024                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9025         }
9026 }
9027 #endif