Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  *
1433  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434  */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* No really, not for ILK+ */
1441         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445                 assert_panel_unlocked(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val |= DPLL_VCO_ENABLE;
1450
1451         /* We do this three times for luck */
1452         I915_WRITE(reg, val);
1453         POSTING_READ(reg);
1454         udelay(150); /* wait for warmup */
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         udelay(150); /* wait for warmup */
1458         I915_WRITE(reg, val);
1459         POSTING_READ(reg);
1460         udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464  * intel_disable_pll - disable a PLL
1465  * @dev_priv: i915 private structure
1466  * @pipe: pipe PLL to disable
1467  *
1468  * Disable the PLL for @pipe, making sure the pipe is off first.
1469  *
1470  * Note!  This is for pre-ILK only.
1471  */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* Don't disable pipe A or pipe A PLLs if needed */
1478         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479                 return;
1480
1481         /* Make sure the pipe isn't still relying on us */
1482         assert_pipe_disabled(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val &= ~DPLL_VCO_ENABLE;
1487         I915_WRITE(reg, val);
1488         POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495         unsigned long flags;
1496
1497         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499                                 100)) {
1500                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501                 goto out_unlock;
1502         }
1503
1504         I915_WRITE(SBI_ADDR,
1505                         (reg << 16));
1506         I915_WRITE(SBI_DATA,
1507                         value);
1508         I915_WRITE(SBI_CTL_STAT,
1509                         SBI_BUSY |
1510                         SBI_CTL_OP_CRWR);
1511
1512         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513                                 100)) {
1514                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515                 goto out_unlock;
1516         }
1517
1518 out_unlock:
1519         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525         unsigned long flags;
1526         u32 value = 0;
1527
1528         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530                                 100)) {
1531                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532                 goto out_unlock;
1533         }
1534
1535         I915_WRITE(SBI_ADDR,
1536                         (reg << 16));
1537         I915_WRITE(SBI_CTL_STAT,
1538                         SBI_BUSY |
1539                         SBI_CTL_OP_CRRD);
1540
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544                 goto out_unlock;
1545         }
1546
1547         value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551         return value;
1552 }
1553
1554 /**
1555  * intel_enable_pch_pll - enable PCH PLL
1556  * @dev_priv: i915 private structure
1557  * @pipe: pipe PLL to enable
1558  *
1559  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560  * drives the transcoder clock.
1561  */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565         struct intel_pch_pll *pll;
1566         int reg;
1567         u32 val;
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(dev_priv->info->gen < 5);
1571         pll = intel_crtc->pch_pll;
1572         if (pll == NULL)
1573                 return;
1574
1575         if (WARN_ON(pll->refcount == 0))
1576                 return;
1577
1578         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579                       pll->pll_reg, pll->active, pll->on,
1580                       intel_crtc->base.base.id);
1581
1582         /* PCH refclock must be enabled first */
1583         assert_pch_refclk_enabled(dev_priv);
1584
1585         if (pll->active++ && pll->on) {
1586                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587                 return;
1588         }
1589
1590         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592         reg = pll->pll_reg;
1593         val = I915_READ(reg);
1594         val |= DPLL_VCO_ENABLE;
1595         I915_WRITE(reg, val);
1596         POSTING_READ(reg);
1597         udelay(200);
1598
1599         pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606         int reg;
1607         u32 val;
1608
1609         /* PCH only available on ILK+ */
1610         BUG_ON(dev_priv->info->gen < 5);
1611         if (pll == NULL)
1612                return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         if (WARN_ON(pll->active == 0)) {
1622                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623                 return;
1624         }
1625
1626         if (--pll->active) {
1627                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628                 return;
1629         }
1630
1631         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633         /* Make sure transcoder isn't still depending on us */
1634         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636         reg = pll->pll_reg;
1637         val = I915_READ(reg);
1638         val &= ~DPLL_VCO_ENABLE;
1639         I915_WRITE(reg, val);
1640         POSTING_READ(reg);
1641         udelay(200);
1642
1643         pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647                                     enum pipe pipe)
1648 {
1649         int reg;
1650         u32 val, pipeconf_val;
1651         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653         /* PCH only available on ILK+ */
1654         BUG_ON(dev_priv->info->gen < 5);
1655
1656         /* Make sure PCH DPLL is enabled */
1657         assert_pch_pll_enabled(dev_priv,
1658                                to_intel_crtc(crtc)->pch_pll,
1659                                to_intel_crtc(crtc));
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667                 return;
1668         }
1669         reg = TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv->dev)) {
1674                 /*
1675                  * make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg.
1677                  */
1678                 val &= ~PIPE_BPC_MASK;
1679                 val |= pipeconf_val & PIPE_BPC_MASK;
1680         }
1681
1682         val &= ~TRANS_INTERLACE_MASK;
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684                 if (HAS_PCH_IBX(dev_priv->dev) &&
1685                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686                         val |= TRANS_LEGACY_INTERLACED_ILK;
1687                 else
1688                         val |= TRANS_INTERLACED;
1689         else
1690                 val |= TRANS_PROGRESSIVE;
1691
1692         I915_WRITE(reg, val | TRANS_ENABLE);
1693         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698                                      enum pipe pipe)
1699 {
1700         int reg;
1701         u32 val;
1702
1703         /* FDI relies on the transcoder */
1704         assert_fdi_tx_disabled(dev_priv, pipe);
1705         assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707         /* Ports must be off as well */
1708         assert_pch_ports_disabled(dev_priv, pipe);
1709
1710         reg = TRANSCONF(pipe);
1711         val = I915_READ(reg);
1712         val &= ~TRANS_ENABLE;
1713         I915_WRITE(reg, val);
1714         /* wait for PCH transcoder off, transcoder state */
1715         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720  * intel_enable_pipe - enable a pipe, asserting requirements
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe to enable
1723  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724  *
1725  * Enable @pipe, making sure that various hardware specific requirements
1726  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727  *
1728  * @pipe should be %PIPE_A or %PIPE_B.
1729  *
1730  * Will wait until the pipe is actually running (i.e. first vblank) before
1731  * returning.
1732  */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734                               bool pch_port)
1735 {
1736         int reg;
1737         u32 val;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751                 }
1752                 /* FIXME: assert CPU port conditions for SNB+ */
1753         }
1754
1755         reg = PIPECONF(pipe);
1756         val = I915_READ(reg);
1757         if (val & PIPECONF_ENABLE)
1758                 return;
1759
1760         I915_WRITE(reg, val | PIPECONF_ENABLE);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_pipe - disable a pipe, asserting requirements
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe to disable
1768  *
1769  * Disable @pipe, making sure that various hardware specific requirements
1770  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771  *
1772  * @pipe should be %PIPE_A or %PIPE_B.
1773  *
1774  * Will wait until the pipe has shut down before returning.
1775  */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777                                enum pipe pipe)
1778 {
1779         int reg;
1780         u32 val;
1781
1782         /*
1783          * Make sure planes won't keep trying to pump pixels to us,
1784          * or we might hang the display.
1785          */
1786         assert_planes_disabled(dev_priv, pipe);
1787
1788         /* Don't disable pipe A or pipe A PLLs if needed */
1789         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790                 return;
1791
1792         reg = PIPECONF(pipe);
1793         val = I915_READ(reg);
1794         if ((val & PIPECONF_ENABLE) == 0)
1795                 return;
1796
1797         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802  * Plane regs are double buffered, going from enabled->disabled needs a
1803  * trigger in order to latch.  The display address reg provides this.
1804  */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806                                       enum plane plane)
1807 {
1808         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813  * intel_enable_plane - enable a display plane on a given pipe
1814  * @dev_priv: i915 private structure
1815  * @plane: plane to enable
1816  * @pipe: pipe being fed
1817  *
1818  * Enable @plane on @pipe, making sure that @pipe is running first.
1819  */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane, enum pipe pipe)
1822 {
1823         int reg;
1824         u32 val;
1825
1826         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827         assert_pipe_enabled(dev_priv, pipe);
1828
1829         reg = DSPCNTR(plane);
1830         val = I915_READ(reg);
1831         if (val & DISPLAY_PLANE_ENABLE)
1832                 return;
1833
1834         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835         intel_flush_display_plane(dev_priv, plane);
1836         intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840  * intel_disable_plane - disable a display plane
1841  * @dev_priv: i915 private structure
1842  * @plane: plane to disable
1843  * @pipe: pipe consuming the data
1844  *
1845  * Disable @plane; should be an independent operation.
1846  */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848                                 enum plane plane, enum pipe pipe)
1849 {
1850         int reg;
1851         u32 val;
1852
1853         reg = DSPCNTR(plane);
1854         val = I915_READ(reg);
1855         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856                 return;
1857
1858         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859         intel_flush_display_plane(dev_priv, plane);
1860         intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864                            enum pipe pipe, int reg, u32 port_sel)
1865 {
1866         u32 val = I915_READ(reg);
1867         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869                 I915_WRITE(reg, val & ~DP_PORT_EN);
1870         }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874                              enum pipe pipe, int reg)
1875 {
1876         u32 val = I915_READ(reg);
1877         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879                               reg, pipe);
1880                 I915_WRITE(reg, val & ~PORT_ENABLE);
1881         }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886                                     enum pipe pipe)
1887 {
1888         u32 reg, val;
1889
1890         val = I915_READ(PCH_PP_CONTROL);
1891         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897         reg = PCH_ADPA;
1898         val = I915_READ(reg);
1899         if (adpa_pipe_enabled(dev_priv, pipe, val))
1900                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902         reg = PCH_LVDS;
1903         val = I915_READ(reg);
1904         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907                 POSTING_READ(reg);
1908                 udelay(100);
1909         }
1910
1911         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913         disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918                            struct drm_i915_gem_object *obj,
1919                            struct intel_ring_buffer *pipelined)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         u32 alignment;
1923         int ret;
1924
1925         switch (obj->tiling_mode) {
1926         case I915_TILING_NONE:
1927                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928                         alignment = 128 * 1024;
1929                 else if (INTEL_INFO(dev)->gen >= 4)
1930                         alignment = 4 * 1024;
1931                 else
1932                         alignment = 64 * 1024;
1933                 break;
1934         case I915_TILING_X:
1935                 /* pin() will align the object as required by fence */
1936                 alignment = 0;
1937                 break;
1938         case I915_TILING_Y:
1939                 /* FIXME: Is this true? */
1940                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941                 return -EINVAL;
1942         default:
1943                 BUG();
1944         }
1945
1946         dev_priv->mm.interruptible = false;
1947         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948         if (ret)
1949                 goto err_interruptible;
1950
1951         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952          * fence, whereas 965+ only requires a fence if using
1953          * framebuffer compression.  For simplicity, we always install
1954          * a fence as the cost is not that onerous.
1955          */
1956         ret = i915_gem_object_get_fence(obj);
1957         if (ret)
1958                 goto err_unpin;
1959
1960         i915_gem_object_pin_fence(obj);
1961
1962         dev_priv->mm.interruptible = true;
1963         return 0;
1964
1965 err_unpin:
1966         i915_gem_object_unpin(obj);
1967 err_interruptible:
1968         dev_priv->mm.interruptible = true;
1969         return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974         i915_gem_object_unpin_fence(obj);
1975         i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979  * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981                                                         unsigned int bpp,
1982                                                         unsigned int pitch)
1983 {
1984         int tile_rows, tiles;
1985
1986         tile_rows = *y / 8;
1987         *y %= 8;
1988         tiles = *x / (512/bpp);
1989         *x %= 512/bpp;
1990
1991         return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->bits_per_pixel) {
2024         case 8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case 16:
2028                 if (fb->depth == 15)
2029                         dspcntr |= DISPPLANE_15_16BPP;
2030                 else
2031                         dspcntr |= DISPPLANE_16BPP;
2032                 break;
2033         case 24:
2034         case 32:
2035                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036                 break;
2037         default:
2038                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039                 return -EINVAL;
2040         }
2041         if (INTEL_INFO(dev)->gen >= 4) {
2042                 if (obj->tiling_mode != I915_TILING_NONE)
2043                         dspcntr |= DISPPLANE_TILED;
2044                 else
2045                         dspcntr &= ~DISPPLANE_TILED;
2046         }
2047
2048         I915_WRITE(reg, dspcntr);
2049
2050         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052         if (INTEL_INFO(dev)->gen >= 4) {
2053                 intel_crtc->dspaddr_offset =
2054                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055                                                            fb->bits_per_pixel / 8,
2056                                                            fb->pitches[0]);
2057                 linear_offset -= intel_crtc->dspaddr_offset;
2058         } else {
2059                 intel_crtc->dspaddr_offset = linear_offset;
2060         }
2061
2062         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065         if (INTEL_INFO(dev)->gen >= 4) {
2066                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072         POSTING_READ(reg);
2073
2074         return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078                                  struct drm_framebuffer *fb, int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long linear_offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093         case 2:
2094                 break;
2095         default:
2096                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097                 return -EINVAL;
2098         }
2099
2100         intel_fb = to_intel_framebuffer(fb);
2101         obj = intel_fb->obj;
2102
2103         reg = DSPCNTR(plane);
2104         dspcntr = I915_READ(reg);
2105         /* Mask out pixel format bits in case we change it */
2106         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107         switch (fb->bits_per_pixel) {
2108         case 8:
2109                 dspcntr |= DISPPLANE_8BPP;
2110                 break;
2111         case 16:
2112                 if (fb->depth != 16)
2113                         return -EINVAL;
2114
2115                 dspcntr |= DISPPLANE_16BPP;
2116                 break;
2117         case 24:
2118         case 32:
2119                 if (fb->depth == 24)
2120                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121                 else if (fb->depth == 30)
2122                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123                 else
2124                         return -EINVAL;
2125                 break;
2126         default:
2127                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128                 return -EINVAL;
2129         }
2130
2131         if (obj->tiling_mode != I915_TILING_NONE)
2132                 dspcntr |= DISPPLANE_TILED;
2133         else
2134                 dspcntr &= ~DISPPLANE_TILED;
2135
2136         /* must disable */
2137         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139         I915_WRITE(reg, dspcntr);
2140
2141         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142         intel_crtc->dspaddr_offset =
2143                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144                                                    fb->bits_per_pixel / 8,
2145                                                    fb->pitches[0]);
2146         linear_offset -= intel_crtc->dspaddr_offset;
2147
2148         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151         I915_MODIFY_DISPBASE(DSPSURF(plane),
2152                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2153         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154         I915_WRITE(DSPLINOFF(plane), linear_offset);
2155         POSTING_READ(reg);
2156
2157         return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163                            int x, int y, enum mode_set_atomic state)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         if (dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170         intel_increase_pllclock(crtc);
2171
2172         return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180         bool was_interruptible = dev_priv->mm.interruptible;
2181         int ret;
2182
2183         wait_event(dev_priv->pending_flip_queue,
2184                    atomic_read(&dev_priv->mm.wedged) ||
2185                    atomic_read(&obj->pending_flip) == 0);
2186
2187         /* Big Hammer, we also need to ensure that any pending
2188          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189          * current scanout is retired before unpinning the old
2190          * framebuffer.
2191          *
2192          * This should only fail upon a hung GPU, in which case we
2193          * can safely continue.
2194          */
2195         dev_priv->mm.interruptible = false;
2196         ret = i915_gem_object_finish_gpu(obj);
2197         dev_priv->mm.interruptible = was_interruptible;
2198
2199         return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_master_private *master_priv;
2209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210         struct drm_framebuffer *old_fb;
2211         int ret;
2212
2213         /* no fb bound */
2214         if (!fb) {
2215                 DRM_ERROR("No FB bound\n");
2216                 return 0;
2217         }
2218
2219         if(intel_crtc->plane > dev_priv->num_pipe) {
2220                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221                                 intel_crtc->plane,
2222                                 dev_priv->num_pipe);
2223                 return -EINVAL;
2224         }
2225
2226         mutex_lock(&dev->struct_mutex);
2227         ret = intel_pin_and_fence_fb_obj(dev,
2228                                          to_intel_framebuffer(fb)->obj,
2229                                          NULL);
2230         if (ret != 0) {
2231                 mutex_unlock(&dev->struct_mutex);
2232                 DRM_ERROR("pin & fence failed\n");
2233                 return ret;
2234         }
2235
2236         if (crtc->fb)
2237                 intel_finish_fb(crtc->fb);
2238
2239         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2240         if (ret) {
2241                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2242                 mutex_unlock(&dev->struct_mutex);
2243                 DRM_ERROR("failed to update base address\n");
2244                 return ret;
2245         }
2246
2247         old_fb = crtc->fb;
2248         crtc->fb = fb;
2249
2250         if (old_fb) {
2251                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2252                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2253         }
2254
2255         intel_update_fbc(dev);
2256         mutex_unlock(&dev->struct_mutex);
2257
2258         if (!dev->primary->master)
2259                 return 0;
2260
2261         master_priv = dev->primary->master->driver_priv;
2262         if (!master_priv->sarea_priv)
2263                 return 0;
2264
2265         if (intel_crtc->pipe) {
2266                 master_priv->sarea_priv->pipeB_x = x;
2267                 master_priv->sarea_priv->pipeB_y = y;
2268         } else {
2269                 master_priv->sarea_priv->pipeA_x = x;
2270                 master_priv->sarea_priv->pipeA_y = y;
2271         }
2272
2273         return 0;
2274 }
2275
2276 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         u32 dpa_ctl;
2281
2282         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2283         dpa_ctl = I915_READ(DP_A);
2284         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2285
2286         if (clock < 200000) {
2287                 u32 temp;
2288                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2289                 /* workaround for 160Mhz:
2290                    1) program 0x4600c bits 15:0 = 0x8124
2291                    2) program 0x46010 bit 0 = 1
2292                    3) program 0x46034 bit 24 = 1
2293                    4) program 0x64000 bit 14 = 1
2294                    */
2295                 temp = I915_READ(0x4600c);
2296                 temp &= 0xffff0000;
2297                 I915_WRITE(0x4600c, temp | 0x8124);
2298
2299                 temp = I915_READ(0x46010);
2300                 I915_WRITE(0x46010, temp | 1);
2301
2302                 temp = I915_READ(0x46034);
2303                 I915_WRITE(0x46034, temp | (1 << 24));
2304         } else {
2305                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2306         }
2307         I915_WRITE(DP_A, dpa_ctl);
2308
2309         POSTING_READ(DP_A);
2310         udelay(500);
2311 }
2312
2313 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2314 {
2315         struct drm_device *dev = crtc->dev;
2316         struct drm_i915_private *dev_priv = dev->dev_private;
2317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318         int pipe = intel_crtc->pipe;
2319         u32 reg, temp;
2320
2321         /* enable normal train */
2322         reg = FDI_TX_CTL(pipe);
2323         temp = I915_READ(reg);
2324         if (IS_IVYBRIDGE(dev)) {
2325                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2326                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2327         } else {
2328                 temp &= ~FDI_LINK_TRAIN_NONE;
2329                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2330         }
2331         I915_WRITE(reg, temp);
2332
2333         reg = FDI_RX_CTL(pipe);
2334         temp = I915_READ(reg);
2335         if (HAS_PCH_CPT(dev)) {
2336                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2337                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2338         } else {
2339                 temp &= ~FDI_LINK_TRAIN_NONE;
2340                 temp |= FDI_LINK_TRAIN_NONE;
2341         }
2342         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2343
2344         /* wait one idle pattern time */
2345         POSTING_READ(reg);
2346         udelay(1000);
2347
2348         /* IVB wants error correction enabled */
2349         if (IS_IVYBRIDGE(dev))
2350                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2351                            FDI_FE_ERRC_ENABLE);
2352 }
2353
2354 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2355 {
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         u32 flags = I915_READ(SOUTH_CHICKEN1);
2358
2359         flags |= FDI_PHASE_SYNC_OVR(pipe);
2360         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2361         flags |= FDI_PHASE_SYNC_EN(pipe);
2362         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2363         POSTING_READ(SOUTH_CHICKEN1);
2364 }
2365
2366 /* The FDI link training functions for ILK/Ibexpeak. */
2367 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2368 {
2369         struct drm_device *dev = crtc->dev;
2370         struct drm_i915_private *dev_priv = dev->dev_private;
2371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372         int pipe = intel_crtc->pipe;
2373         int plane = intel_crtc->plane;
2374         u32 reg, temp, tries;
2375
2376         /* FDI needs bits from pipe & plane first */
2377         assert_pipe_enabled(dev_priv, pipe);
2378         assert_plane_enabled(dev_priv, plane);
2379
2380         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2381            for train result */
2382         reg = FDI_RX_IMR(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_RX_SYMBOL_LOCK;
2385         temp &= ~FDI_RX_BIT_LOCK;
2386         I915_WRITE(reg, temp);
2387         I915_READ(reg);
2388         udelay(150);
2389
2390         /* enable CPU FDI TX and PCH FDI RX */
2391         reg = FDI_TX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         temp &= ~(7 << 19);
2394         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2395         temp &= ~FDI_LINK_TRAIN_NONE;
2396         temp |= FDI_LINK_TRAIN_PATTERN_1;
2397         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2398
2399         reg = FDI_RX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         temp &= ~FDI_LINK_TRAIN_NONE;
2402         temp |= FDI_LINK_TRAIN_PATTERN_1;
2403         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404
2405         POSTING_READ(reg);
2406         udelay(150);
2407
2408         /* Ironlake workaround, enable clock pointer after FDI enable*/
2409         if (HAS_PCH_IBX(dev)) {
2410                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2411                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2412                            FDI_RX_PHASE_SYNC_POINTER_EN);
2413         }
2414
2415         reg = FDI_RX_IIR(pipe);
2416         for (tries = 0; tries < 5; tries++) {
2417                 temp = I915_READ(reg);
2418                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419
2420                 if ((temp & FDI_RX_BIT_LOCK)) {
2421                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2422                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2423                         break;
2424                 }
2425         }
2426         if (tries == 5)
2427                 DRM_ERROR("FDI train 1 fail!\n");
2428
2429         /* Train 2 */
2430         reg = FDI_TX_CTL(pipe);
2431         temp = I915_READ(reg);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_2;
2434         I915_WRITE(reg, temp);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_2;
2440         I915_WRITE(reg, temp);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         reg = FDI_RX_IIR(pipe);
2446         for (tries = 0; tries < 5; tries++) {
2447                 temp = I915_READ(reg);
2448                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450                 if (temp & FDI_RX_SYMBOL_LOCK) {
2451                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2452                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2453                         break;
2454                 }
2455         }
2456         if (tries == 5)
2457                 DRM_ERROR("FDI train 2 fail!\n");
2458
2459         DRM_DEBUG_KMS("FDI train done\n");
2460
2461 }
2462
2463 static const int snb_b_fdi_train_param[] = {
2464         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2465         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2466         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2467         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2468 };
2469
2470 /* The FDI link training functions for SNB/Cougarpoint. */
2471 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2472 {
2473         struct drm_device *dev = crtc->dev;
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476         int pipe = intel_crtc->pipe;
2477         u32 reg, temp, i, retry;
2478
2479         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480            for train result */
2481         reg = FDI_RX_IMR(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_RX_SYMBOL_LOCK;
2484         temp &= ~FDI_RX_BIT_LOCK;
2485         I915_WRITE(reg, temp);
2486
2487         POSTING_READ(reg);
2488         udelay(150);
2489
2490         /* enable CPU FDI TX and PCH FDI RX */
2491         reg = FDI_TX_CTL(pipe);
2492         temp = I915_READ(reg);
2493         temp &= ~(7 << 19);
2494         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2495         temp &= ~FDI_LINK_TRAIN_NONE;
2496         temp |= FDI_LINK_TRAIN_PATTERN_1;
2497         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498         /* SNB-B */
2499         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2500         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2501
2502         reg = FDI_RX_CTL(pipe);
2503         temp = I915_READ(reg);
2504         if (HAS_PCH_CPT(dev)) {
2505                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507         } else {
2508                 temp &= ~FDI_LINK_TRAIN_NONE;
2509                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510         }
2511         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2512
2513         POSTING_READ(reg);
2514         udelay(150);
2515
2516         if (HAS_PCH_CPT(dev))
2517                 cpt_phase_pointer_enable(dev, pipe);
2518
2519         for (i = 0; i < 4; i++) {
2520                 reg = FDI_TX_CTL(pipe);
2521                 temp = I915_READ(reg);
2522                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523                 temp |= snb_b_fdi_train_param[i];
2524                 I915_WRITE(reg, temp);
2525
2526                 POSTING_READ(reg);
2527                 udelay(500);
2528
2529                 for (retry = 0; retry < 5; retry++) {
2530                         reg = FDI_RX_IIR(pipe);
2531                         temp = I915_READ(reg);
2532                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533                         if (temp & FDI_RX_BIT_LOCK) {
2534                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2535                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2536                                 break;
2537                         }
2538                         udelay(50);
2539                 }
2540                 if (retry < 5)
2541                         break;
2542         }
2543         if (i == 4)
2544                 DRM_ERROR("FDI train 1 fail!\n");
2545
2546         /* Train 2 */
2547         reg = FDI_TX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         temp &= ~FDI_LINK_TRAIN_NONE;
2550         temp |= FDI_LINK_TRAIN_PATTERN_2;
2551         if (IS_GEN6(dev)) {
2552                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553                 /* SNB-B */
2554                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2555         }
2556         I915_WRITE(reg, temp);
2557
2558         reg = FDI_RX_CTL(pipe);
2559         temp = I915_READ(reg);
2560         if (HAS_PCH_CPT(dev)) {
2561                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2563         } else {
2564                 temp &= ~FDI_LINK_TRAIN_NONE;
2565                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566         }
2567         I915_WRITE(reg, temp);
2568
2569         POSTING_READ(reg);
2570         udelay(150);
2571
2572         for (i = 0; i < 4; i++) {
2573                 reg = FDI_TX_CTL(pipe);
2574                 temp = I915_READ(reg);
2575                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576                 temp |= snb_b_fdi_train_param[i];
2577                 I915_WRITE(reg, temp);
2578
2579                 POSTING_READ(reg);
2580                 udelay(500);
2581
2582                 for (retry = 0; retry < 5; retry++) {
2583                         reg = FDI_RX_IIR(pipe);
2584                         temp = I915_READ(reg);
2585                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586                         if (temp & FDI_RX_SYMBOL_LOCK) {
2587                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2588                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2589                                 break;
2590                         }
2591                         udelay(50);
2592                 }
2593                 if (retry < 5)
2594                         break;
2595         }
2596         if (i == 4)
2597                 DRM_ERROR("FDI train 2 fail!\n");
2598
2599         DRM_DEBUG_KMS("FDI train done.\n");
2600 }
2601
2602 /* Manual link training for Ivy Bridge A0 parts */
2603 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2604 {
2605         struct drm_device *dev = crtc->dev;
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608         int pipe = intel_crtc->pipe;
2609         u32 reg, temp, i;
2610
2611         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612            for train result */
2613         reg = FDI_RX_IMR(pipe);
2614         temp = I915_READ(reg);
2615         temp &= ~FDI_RX_SYMBOL_LOCK;
2616         temp &= ~FDI_RX_BIT_LOCK;
2617         I915_WRITE(reg, temp);
2618
2619         POSTING_READ(reg);
2620         udelay(150);
2621
2622         /* enable CPU FDI TX and PCH FDI RX */
2623         reg = FDI_TX_CTL(pipe);
2624         temp = I915_READ(reg);
2625         temp &= ~(7 << 19);
2626         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2628         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2629         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2631         temp |= FDI_COMPOSITE_SYNC;
2632         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2633
2634         reg = FDI_RX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_AUTO;
2637         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2639         temp |= FDI_COMPOSITE_SYNC;
2640         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642         POSTING_READ(reg);
2643         udelay(150);
2644
2645         if (HAS_PCH_CPT(dev))
2646                 cpt_phase_pointer_enable(dev, pipe);
2647
2648         for (i = 0; i < 4; i++) {
2649                 reg = FDI_TX_CTL(pipe);
2650                 temp = I915_READ(reg);
2651                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652                 temp |= snb_b_fdi_train_param[i];
2653                 I915_WRITE(reg, temp);
2654
2655                 POSTING_READ(reg);
2656                 udelay(500);
2657
2658                 reg = FDI_RX_IIR(pipe);
2659                 temp = I915_READ(reg);
2660                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662                 if (temp & FDI_RX_BIT_LOCK ||
2663                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2666                         break;
2667                 }
2668         }
2669         if (i == 4)
2670                 DRM_ERROR("FDI train 1 fail!\n");
2671
2672         /* Train 2 */
2673         reg = FDI_TX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2677         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2679         I915_WRITE(reg, temp);
2680
2681         reg = FDI_RX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685         I915_WRITE(reg, temp);
2686
2687         POSTING_READ(reg);
2688         udelay(150);
2689
2690         for (i = 0; i < 4; i++) {
2691                 reg = FDI_TX_CTL(pipe);
2692                 temp = I915_READ(reg);
2693                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694                 temp |= snb_b_fdi_train_param[i];
2695                 I915_WRITE(reg, temp);
2696
2697                 POSTING_READ(reg);
2698                 udelay(500);
2699
2700                 reg = FDI_RX_IIR(pipe);
2701                 temp = I915_READ(reg);
2702                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704                 if (temp & FDI_RX_SYMBOL_LOCK) {
2705                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2706                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2707                         break;
2708                 }
2709         }
2710         if (i == 4)
2711                 DRM_ERROR("FDI train 2 fail!\n");
2712
2713         DRM_DEBUG_KMS("FDI train done.\n");
2714 }
2715
2716 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2717 {
2718         struct drm_device *dev = intel_crtc->base.dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         int pipe = intel_crtc->pipe;
2721         u32 reg, temp;
2722
2723         /* Write the TU size bits so error detection works */
2724         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2725                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2726
2727         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2728         reg = FDI_RX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         temp &= ~((0x7 << 19) | (0x7 << 16));
2731         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2732         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2733         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734
2735         POSTING_READ(reg);
2736         udelay(200);
2737
2738         /* Switch from Rawclk to PCDclk */
2739         temp = I915_READ(reg);
2740         I915_WRITE(reg, temp | FDI_PCDCLK);
2741
2742         POSTING_READ(reg);
2743         udelay(200);
2744
2745         /* On Haswell, the PLL configuration for ports and pipes is handled
2746          * separately, as part of DDI setup */
2747         if (!IS_HASWELL(dev)) {
2748                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2749                 reg = FDI_TX_CTL(pipe);
2750                 temp = I915_READ(reg);
2751                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2752                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2753
2754                         POSTING_READ(reg);
2755                         udelay(100);
2756                 }
2757         }
2758 }
2759
2760 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2761 {
2762         struct drm_device *dev = intel_crtc->base.dev;
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         int pipe = intel_crtc->pipe;
2765         u32 reg, temp;
2766
2767         /* Switch from PCDclk to Rawclk */
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2771
2772         /* Disable CPU FDI TX PLL */
2773         reg = FDI_TX_CTL(pipe);
2774         temp = I915_READ(reg);
2775         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2776
2777         POSTING_READ(reg);
2778         udelay(100);
2779
2780         reg = FDI_RX_CTL(pipe);
2781         temp = I915_READ(reg);
2782         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2783
2784         /* Wait for the clocks to turn off. */
2785         POSTING_READ(reg);
2786         udelay(100);
2787 }
2788
2789 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2790 {
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         u32 flags = I915_READ(SOUTH_CHICKEN1);
2793
2794         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2795         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2796         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2797         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2798         POSTING_READ(SOUTH_CHICKEN1);
2799 }
2800 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2801 {
2802         struct drm_device *dev = crtc->dev;
2803         struct drm_i915_private *dev_priv = dev->dev_private;
2804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805         int pipe = intel_crtc->pipe;
2806         u32 reg, temp;
2807
2808         /* disable CPU FDI tx and PCH FDI rx */
2809         reg = FDI_TX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2812         POSTING_READ(reg);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~(0x7 << 16);
2817         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(100);
2822
2823         /* Ironlake workaround, disable clock pointer after downing FDI */
2824         if (HAS_PCH_IBX(dev)) {
2825                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2826                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2827                            I915_READ(FDI_RX_CHICKEN(pipe) &
2828                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2829         } else if (HAS_PCH_CPT(dev)) {
2830                 cpt_phase_pointer_disable(dev, pipe);
2831         }
2832
2833         /* still set train pattern 1 */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~FDI_LINK_TRAIN_NONE;
2837         temp |= FDI_LINK_TRAIN_PATTERN_1;
2838         I915_WRITE(reg, temp);
2839
2840         reg = FDI_RX_CTL(pipe);
2841         temp = I915_READ(reg);
2842         if (HAS_PCH_CPT(dev)) {
2843                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845         } else {
2846                 temp &= ~FDI_LINK_TRAIN_NONE;
2847                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848         }
2849         /* BPC in FDI rx is consistent with that in PIPECONF */
2850         temp &= ~(0x07 << 16);
2851         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2852         I915_WRITE(reg, temp);
2853
2854         POSTING_READ(reg);
2855         udelay(100);
2856 }
2857
2858 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859 {
2860         struct drm_device *dev = crtc->dev;
2861
2862         if (crtc->fb == NULL)
2863                 return;
2864
2865         mutex_lock(&dev->struct_mutex);
2866         intel_finish_fb(crtc->fb);
2867         mutex_unlock(&dev->struct_mutex);
2868 }
2869
2870 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2871 {
2872         struct drm_device *dev = crtc->dev;
2873         struct intel_encoder *intel_encoder;
2874
2875         /*
2876          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2877          * must be driven by its own crtc; no sharing is possible.
2878          */
2879         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2880
2881                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2882                  * CPU handles all others */
2883                 if (IS_HASWELL(dev)) {
2884                         /* It is still unclear how this will work on PPT, so throw up a warning */
2885                         WARN_ON(!HAS_PCH_LPT(dev));
2886
2887                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2888                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2889                                 return true;
2890                         } else {
2891                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2892                                               intel_encoder->type);
2893                                 return false;
2894                         }
2895                 }
2896
2897                 switch (intel_encoder->type) {
2898                 case INTEL_OUTPUT_EDP:
2899                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2900                                 return false;
2901                         continue;
2902                 }
2903         }
2904
2905         return true;
2906 }
2907
2908 /* Program iCLKIP clock to the desired frequency */
2909 static void lpt_program_iclkip(struct drm_crtc *crtc)
2910 {
2911         struct drm_device *dev = crtc->dev;
2912         struct drm_i915_private *dev_priv = dev->dev_private;
2913         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2914         u32 temp;
2915
2916         /* It is necessary to ungate the pixclk gate prior to programming
2917          * the divisors, and gate it back when it is done.
2918          */
2919         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2920
2921         /* Disable SSCCTL */
2922         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2923                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2924                                         SBI_SSCCTL_DISABLE);
2925
2926         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927         if (crtc->mode.clock == 20000) {
2928                 auxdiv = 1;
2929                 divsel = 0x41;
2930                 phaseinc = 0x20;
2931         } else {
2932                 /* The iCLK virtual clock root frequency is in MHz,
2933                  * but the crtc->mode.clock in in KHz. To get the divisors,
2934                  * it is necessary to divide one by another, so we
2935                  * convert the virtual clock precision to KHz here for higher
2936                  * precision.
2937                  */
2938                 u32 iclk_virtual_root_freq = 172800 * 1000;
2939                 u32 iclk_pi_range = 64;
2940                 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943                 msb_divisor_value = desired_divisor / iclk_pi_range;
2944                 pi_value = desired_divisor % iclk_pi_range;
2945
2946                 auxdiv = 0;
2947                 divsel = msb_divisor_value - 2;
2948                 phaseinc = pi_value;
2949         }
2950
2951         /* This should not happen with any sane values */
2952         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958                         crtc->mode.clock,
2959                         auxdiv,
2960                         divsel,
2961                         phasedir,
2962                         phaseinc);
2963
2964         /* Program SSCDIVINTPHASE6 */
2965         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2966         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2972
2973         intel_sbi_write(dev_priv,
2974                         SBI_SSCDIVINTPHASE6,
2975                         temp);
2976
2977         /* Program SSCAUXDIV */
2978         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2979         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2980         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2981         intel_sbi_write(dev_priv,
2982                         SBI_SSCAUXDIV6,
2983                         temp);
2984
2985
2986         /* Enable modulator and associated divider */
2987         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2988         temp &= ~SBI_SSCCTL_DISABLE;
2989         intel_sbi_write(dev_priv,
2990                         SBI_SSCCTL6,
2991                         temp);
2992
2993         /* Wait for initialization time */
2994         udelay(24);
2995
2996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997 }
2998
2999 /*
3000  * Enable PCH resources required for PCH ports:
3001  *   - PCH PLLs
3002  *   - FDI training & RX/TX
3003  *   - update transcoder timings
3004  *   - DP transcoding bits
3005  *   - transcoder
3006  */
3007 static void ironlake_pch_enable(struct drm_crtc *crtc)
3008 {
3009         struct drm_device *dev = crtc->dev;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012         int pipe = intel_crtc->pipe;
3013         u32 reg, temp;
3014
3015         assert_transcoder_disabled(dev_priv, pipe);
3016
3017         /* For PCH output, training FDI link */
3018         dev_priv->display.fdi_link_train(crtc);
3019
3020         intel_enable_pch_pll(intel_crtc);
3021
3022         if (HAS_PCH_LPT(dev)) {
3023                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3024                 lpt_program_iclkip(crtc);
3025         } else if (HAS_PCH_CPT(dev)) {
3026                 u32 sel;
3027
3028                 temp = I915_READ(PCH_DPLL_SEL);
3029                 switch (pipe) {
3030                 default:
3031                 case 0:
3032                         temp |= TRANSA_DPLL_ENABLE;
3033                         sel = TRANSA_DPLLB_SEL;
3034                         break;
3035                 case 1:
3036                         temp |= TRANSB_DPLL_ENABLE;
3037                         sel = TRANSB_DPLLB_SEL;
3038                         break;
3039                 case 2:
3040                         temp |= TRANSC_DPLL_ENABLE;
3041                         sel = TRANSC_DPLLB_SEL;
3042                         break;
3043                 }
3044                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045                         temp |= sel;
3046                 else
3047                         temp &= ~sel;
3048                 I915_WRITE(PCH_DPLL_SEL, temp);
3049         }
3050
3051         /* set transcoder timing, panel must allow it */
3052         assert_panel_unlocked(dev_priv, pipe);
3053         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3056
3057         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3060         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3061
3062         if (!IS_HASWELL(dev))
3063                 intel_fdi_normal_train(crtc);
3064
3065         /* For PCH DP, enable TRANS_DP_CTL */
3066         if (HAS_PCH_CPT(dev) &&
3067             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3068              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3069                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3070                 reg = TRANS_DP_CTL(pipe);
3071                 temp = I915_READ(reg);
3072                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3073                           TRANS_DP_SYNC_MASK |
3074                           TRANS_DP_BPC_MASK);
3075                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3076                          TRANS_DP_ENH_FRAMING);
3077                 temp |= bpc << 9; /* same format but at 11:9 */
3078
3079                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3080                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3081                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3082                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3083
3084                 switch (intel_trans_dp_port_sel(crtc)) {
3085                 case PCH_DP_B:
3086                         temp |= TRANS_DP_PORT_SEL_B;
3087                         break;
3088                 case PCH_DP_C:
3089                         temp |= TRANS_DP_PORT_SEL_C;
3090                         break;
3091                 case PCH_DP_D:
3092                         temp |= TRANS_DP_PORT_SEL_D;
3093                         break;
3094                 default:
3095                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3096                         temp |= TRANS_DP_PORT_SEL_B;
3097                         break;
3098                 }
3099
3100                 I915_WRITE(reg, temp);
3101         }
3102
3103         intel_enable_transcoder(dev_priv, pipe);
3104 }
3105
3106 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3107 {
3108         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3109
3110         if (pll == NULL)
3111                 return;
3112
3113         if (pll->refcount == 0) {
3114                 WARN(1, "bad PCH PLL refcount\n");
3115                 return;
3116         }
3117
3118         --pll->refcount;
3119         intel_crtc->pch_pll = NULL;
3120 }
3121
3122 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3123 {
3124         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3125         struct intel_pch_pll *pll;
3126         int i;
3127
3128         pll = intel_crtc->pch_pll;
3129         if (pll) {
3130                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3131                               intel_crtc->base.base.id, pll->pll_reg);
3132                 goto prepare;
3133         }
3134
3135         if (HAS_PCH_IBX(dev_priv->dev)) {
3136                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3137                 i = intel_crtc->pipe;
3138                 pll = &dev_priv->pch_plls[i];
3139
3140                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3141                               intel_crtc->base.base.id, pll->pll_reg);
3142
3143                 goto found;
3144         }
3145
3146         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147                 pll = &dev_priv->pch_plls[i];
3148
3149                 /* Only want to check enabled timings first */
3150                 if (pll->refcount == 0)
3151                         continue;
3152
3153                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3154                     fp == I915_READ(pll->fp0_reg)) {
3155                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3156                                       intel_crtc->base.base.id,
3157                                       pll->pll_reg, pll->refcount, pll->active);
3158
3159                         goto found;
3160                 }
3161         }
3162
3163         /* Ok no matching timings, maybe there's a free one? */
3164         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3165                 pll = &dev_priv->pch_plls[i];
3166                 if (pll->refcount == 0) {
3167                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3168                                       intel_crtc->base.base.id, pll->pll_reg);
3169                         goto found;
3170                 }
3171         }
3172
3173         return NULL;
3174
3175 found:
3176         intel_crtc->pch_pll = pll;
3177         pll->refcount++;
3178         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3179 prepare: /* separate function? */
3180         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3181
3182         /* Wait for the clocks to stabilize before rewriting the regs */
3183         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3184         POSTING_READ(pll->pll_reg);
3185         udelay(150);
3186
3187         I915_WRITE(pll->fp0_reg, fp);
3188         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3189         pll->on = false;
3190         return pll;
3191 }
3192
3193 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3197         u32 temp;
3198
3199         temp = I915_READ(dslreg);
3200         udelay(500);
3201         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3202                 /* Without this, mode sets may fail silently on FDI */
3203                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3204                 udelay(250);
3205                 I915_WRITE(tc2reg, 0);
3206                 if (wait_for(I915_READ(dslreg) != temp, 5))
3207                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3208         }
3209 }
3210
3211 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3212 {
3213         struct drm_device *dev = crtc->dev;
3214         struct drm_i915_private *dev_priv = dev->dev_private;
3215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3216         struct intel_encoder *encoder;
3217         int pipe = intel_crtc->pipe;
3218         int plane = intel_crtc->plane;
3219         u32 temp;
3220         bool is_pch_port;
3221
3222         WARN_ON(!crtc->enabled);
3223
3224         /* XXX: For compatability with the crtc helper code, call the encoder's
3225          * enable function unconditionally for now. */
3226         if (intel_crtc->active)
3227                 goto encoders;
3228
3229         intel_crtc->active = true;
3230         intel_update_watermarks(dev);
3231
3232         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233                 temp = I915_READ(PCH_LVDS);
3234                 if ((temp & LVDS_PORT_EN) == 0)
3235                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236         }
3237
3238         is_pch_port = intel_crtc_driving_pch(crtc);
3239
3240         if (is_pch_port)
3241                 ironlake_fdi_pll_enable(intel_crtc);
3242         else
3243                 ironlake_fdi_disable(crtc);
3244
3245         /* Enable panel fitting for LVDS */
3246         if (dev_priv->pch_pf_size &&
3247             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3248                 /* Force use of hard-coded filter coefficients
3249                  * as some pre-programmed values are broken,
3250                  * e.g. x201.
3251                  */
3252                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3254                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3255         }
3256
3257         /*
3258          * On ILK+ LUT must be loaded before the pipe is running but with
3259          * clocks enabled
3260          */
3261         intel_crtc_load_lut(crtc);
3262
3263         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3264         intel_enable_plane(dev_priv, plane, pipe);
3265
3266         if (is_pch_port)
3267                 ironlake_pch_enable(crtc);
3268
3269         mutex_lock(&dev->struct_mutex);
3270         intel_update_fbc(dev);
3271         mutex_unlock(&dev->struct_mutex);
3272
3273         intel_crtc_update_cursor(crtc, true);
3274
3275 encoders:
3276         for_each_encoder_on_crtc(dev, crtc, encoder)
3277                 encoder->enable(encoder);
3278
3279         if (HAS_PCH_CPT(dev))
3280                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3281 }
3282
3283 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3284 {
3285         struct drm_device *dev = crtc->dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3288         struct intel_encoder *encoder;
3289         int pipe = intel_crtc->pipe;
3290         int plane = intel_crtc->plane;
3291         u32 reg, temp;
3292
3293         /* XXX: For compatability with the crtc helper code, call the encoder's
3294          * disable function unconditionally for now. */
3295         for_each_encoder_on_crtc(dev, crtc, encoder)
3296                 encoder->disable(encoder);
3297
3298         if (!intel_crtc->active)
3299                 return;
3300
3301         intel_crtc_wait_for_pending_flips(crtc);
3302         drm_vblank_off(dev, pipe);
3303         intel_crtc_update_cursor(crtc, false);
3304
3305         intel_disable_plane(dev_priv, plane, pipe);
3306
3307         if (dev_priv->cfb_plane == plane)
3308                 intel_disable_fbc(dev);
3309
3310         intel_disable_pipe(dev_priv, pipe);
3311
3312         /* Disable PF */
3313         I915_WRITE(PF_CTL(pipe), 0);
3314         I915_WRITE(PF_WIN_SZ(pipe), 0);
3315
3316         ironlake_fdi_disable(crtc);
3317
3318         /* This is a horrible layering violation; we should be doing this in
3319          * the connector/encoder ->prepare instead, but we don't always have
3320          * enough information there about the config to know whether it will
3321          * actually be necessary or just cause undesired flicker.
3322          */
3323         intel_disable_pch_ports(dev_priv, pipe);
3324
3325         intel_disable_transcoder(dev_priv, pipe);
3326
3327         if (HAS_PCH_CPT(dev)) {
3328                 /* disable TRANS_DP_CTL */
3329                 reg = TRANS_DP_CTL(pipe);
3330                 temp = I915_READ(reg);
3331                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3332                 temp |= TRANS_DP_PORT_SEL_NONE;
3333                 I915_WRITE(reg, temp);
3334
3335                 /* disable DPLL_SEL */
3336                 temp = I915_READ(PCH_DPLL_SEL);
3337                 switch (pipe) {
3338                 case 0:
3339                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3340                         break;
3341                 case 1:
3342                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3343                         break;
3344                 case 2:
3345                         /* C shares PLL A or B */
3346                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3347                         break;
3348                 default:
3349                         BUG(); /* wtf */
3350                 }
3351                 I915_WRITE(PCH_DPLL_SEL, temp);
3352         }
3353
3354         /* disable PCH DPLL */
3355         intel_disable_pch_pll(intel_crtc);
3356
3357         ironlake_fdi_pll_disable(intel_crtc);
3358
3359         intel_crtc->active = false;
3360         intel_update_watermarks(dev);
3361
3362         mutex_lock(&dev->struct_mutex);
3363         intel_update_fbc(dev);
3364         mutex_unlock(&dev->struct_mutex);
3365 }
3366
3367 static void ironlake_crtc_off(struct drm_crtc *crtc)
3368 {
3369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370         intel_put_pch_pll(intel_crtc);
3371 }
3372
3373 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3374 {
3375         if (!enable && intel_crtc->overlay) {
3376                 struct drm_device *dev = intel_crtc->base.dev;
3377                 struct drm_i915_private *dev_priv = dev->dev_private;
3378
3379                 mutex_lock(&dev->struct_mutex);
3380                 dev_priv->mm.interruptible = false;
3381                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382                 dev_priv->mm.interruptible = true;
3383                 mutex_unlock(&dev->struct_mutex);
3384         }
3385
3386         /* Let userspace switch the overlay on again. In most cases userspace
3387          * has to recompute where to put it anyway.
3388          */
3389 }
3390
3391 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         struct intel_encoder *encoder;
3397         int pipe = intel_crtc->pipe;
3398         int plane = intel_crtc->plane;
3399
3400         WARN_ON(!crtc->enabled);
3401
3402         /* XXX: For compatability with the crtc helper code, call the encoder's
3403          * enable function unconditionally for now. */
3404         if (intel_crtc->active)
3405                 goto encoders;
3406
3407         intel_crtc->active = true;
3408         intel_update_watermarks(dev);
3409
3410         intel_enable_pll(dev_priv, pipe);
3411         intel_enable_pipe(dev_priv, pipe, false);
3412         intel_enable_plane(dev_priv, plane, pipe);
3413
3414         intel_crtc_load_lut(crtc);
3415         intel_update_fbc(dev);
3416
3417         /* Give the overlay scaler a chance to enable if it's on this pipe */
3418         intel_crtc_dpms_overlay(intel_crtc, true);
3419         intel_crtc_update_cursor(crtc, true);
3420
3421 encoders:
3422         for_each_encoder_on_crtc(dev, crtc, encoder)
3423                 encoder->enable(encoder);
3424 }
3425
3426 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3427 {
3428         struct drm_device *dev = crtc->dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3431         struct intel_encoder *encoder;
3432         int pipe = intel_crtc->pipe;
3433         int plane = intel_crtc->plane;
3434
3435         /* XXX: For compatability with the crtc helper code, call the encoder's
3436          * disable function unconditionally for now. */
3437         for_each_encoder_on_crtc(dev, crtc, encoder)
3438                 encoder->disable(encoder);
3439
3440         if (!intel_crtc->active)
3441                 return;
3442
3443         /* Give the overlay scaler a chance to disable if it's on this pipe */
3444         intel_crtc_wait_for_pending_flips(crtc);
3445         drm_vblank_off(dev, pipe);
3446         intel_crtc_dpms_overlay(intel_crtc, false);
3447         intel_crtc_update_cursor(crtc, false);
3448
3449         if (dev_priv->cfb_plane == plane)
3450                 intel_disable_fbc(dev);
3451
3452         intel_disable_plane(dev_priv, plane, pipe);
3453         intel_disable_pipe(dev_priv, pipe);
3454         intel_disable_pll(dev_priv, pipe);
3455
3456         intel_crtc->active = false;
3457         intel_update_fbc(dev);
3458         intel_update_watermarks(dev);
3459 }
3460
3461 static void i9xx_crtc_off(struct drm_crtc *crtc)
3462 {
3463 }
3464
3465 /**
3466  * Sets the power management mode of the pipe and plane.
3467  */
3468 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3469 {
3470         struct drm_device *dev = crtc->dev;
3471         struct drm_i915_private *dev_priv = dev->dev_private;
3472         struct drm_i915_master_private *master_priv;
3473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3474         struct intel_encoder *intel_encoder;
3475         int pipe = intel_crtc->pipe;
3476         bool enabled, enable = false;
3477
3478         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3479                 enable |= intel_encoder->connectors_active;
3480
3481         if (enable)
3482                 dev_priv->display.crtc_enable(crtc);
3483         else
3484                 dev_priv->display.crtc_disable(crtc);
3485
3486         if (!dev->primary->master)
3487                 return;
3488
3489         master_priv = dev->primary->master->driver_priv;
3490         if (!master_priv->sarea_priv)
3491                 return;
3492
3493         enabled = crtc->enabled && enable;
3494
3495         switch (pipe) {
3496         case 0:
3497                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3499                 break;
3500         case 1:
3501                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3503                 break;
3504         default:
3505                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3506                 break;
3507         }
3508 }
3509
3510 static void intel_crtc_disable(struct drm_crtc *crtc)
3511 {
3512         struct drm_device *dev = crtc->dev;
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514
3515         /* crtc->disable is only called when we have no encoders, hence this
3516          * will disable the pipe. */
3517         intel_crtc_update_dpms(crtc);
3518         dev_priv->display.off(crtc);
3519
3520         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3522
3523         if (crtc->fb) {
3524                 mutex_lock(&dev->struct_mutex);
3525                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3526                 mutex_unlock(&dev->struct_mutex);
3527         }
3528 }
3529
3530 void intel_encoder_disable(struct drm_encoder *encoder)
3531 {
3532         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3533
3534         intel_encoder->disable(intel_encoder);
3535 }
3536
3537 void intel_encoder_destroy(struct drm_encoder *encoder)
3538 {
3539         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3540
3541         drm_encoder_cleanup(encoder);
3542         kfree(intel_encoder);
3543 }
3544
3545 /* Simple dpms helper for encodres with just one connector, no cloning and only
3546  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547  * state of the entire output pipe. */
3548 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3549 {
3550         if (mode == DRM_MODE_DPMS_ON) {
3551                 encoder->connectors_active = true;
3552
3553                 intel_crtc_update_dpms(encoder->base.crtc);
3554         } else {
3555                 encoder->connectors_active = false;
3556
3557                 intel_crtc_update_dpms(encoder->base.crtc);
3558         }
3559 }
3560
3561 /* Cross check the actual hw state with our own modeset state tracking (and it's
3562  * internal consistency). */
3563 void intel_connector_check_state(struct intel_connector *connector)
3564 {
3565         if (connector->get_hw_state(connector)) {
3566                 struct intel_encoder *encoder = connector->encoder;
3567                 struct drm_crtc *crtc;
3568                 bool encoder_enabled;
3569                 enum pipe pipe;
3570
3571                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3572                               connector->base.base.id,
3573                               drm_get_connector_name(&connector->base));
3574
3575                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3576                      "wrong connector dpms state\n");
3577                 WARN(connector->base.encoder != &encoder->base,
3578                      "active connector not linked to encoder\n");
3579                 WARN(!encoder->connectors_active,
3580                      "encoder->connectors_active not set\n");
3581
3582                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3583                 WARN(!encoder_enabled, "encoder not enabled\n");
3584                 if (WARN_ON(!encoder->base.crtc))
3585                         return;
3586
3587                 crtc = encoder->base.crtc;
3588
3589                 WARN(!crtc->enabled, "crtc not enabled\n");
3590                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3591                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3592                      "encoder active on the wrong pipe\n");
3593         }
3594 }
3595
3596 /* Even simpler default implementation, if there's really no special case to
3597  * consider. */
3598 void intel_connector_dpms(struct drm_connector *connector, int mode)
3599 {
3600         struct intel_encoder *encoder = intel_attached_encoder(connector);
3601
3602         /* All the simple cases only support two dpms states. */
3603         if (mode != DRM_MODE_DPMS_ON)
3604                 mode = DRM_MODE_DPMS_OFF;
3605
3606         if (mode == connector->dpms)
3607                 return;
3608
3609         connector->dpms = mode;
3610
3611         /* Only need to change hw state when actually enabled */
3612         if (encoder->base.crtc)
3613                 intel_encoder_dpms(encoder, mode);
3614         else
3615                 encoder->connectors_active = false;
3616
3617         intel_connector_check_state(to_intel_connector(connector));
3618 }
3619
3620 /* Simple connector->get_hw_state implementation for encoders that support only
3621  * one connector and no cloning and hence the encoder state determines the state
3622  * of the connector. */
3623 bool intel_connector_get_hw_state(struct intel_connector *connector)
3624 {
3625         enum pipe pipe = 0;
3626         struct intel_encoder *encoder = connector->encoder;
3627
3628         return encoder->get_hw_state(encoder, &pipe);
3629 }
3630
3631 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3632                                   const struct drm_display_mode *mode,
3633                                   struct drm_display_mode *adjusted_mode)
3634 {
3635         struct drm_device *dev = crtc->dev;
3636
3637         if (HAS_PCH_SPLIT(dev)) {
3638                 /* FDI link clock is fixed at 2.7G */
3639                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3640                         return false;
3641         }
3642
3643         /* All interlaced capable intel hw wants timings in frames. Note though
3644          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3645          * timings, so we need to be careful not to clobber these.*/
3646         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3647                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3648
3649         return true;
3650 }
3651
3652 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3653 {
3654         return 400000; /* FIXME */
3655 }
3656
3657 static int i945_get_display_clock_speed(struct drm_device *dev)
3658 {
3659         return 400000;
3660 }
3661
3662 static int i915_get_display_clock_speed(struct drm_device *dev)
3663 {
3664         return 333000;
3665 }
3666
3667 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3668 {
3669         return 200000;
3670 }
3671
3672 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3673 {
3674         u16 gcfgc = 0;
3675
3676         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3677
3678         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3679                 return 133000;
3680         else {
3681                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3682                 case GC_DISPLAY_CLOCK_333_MHZ:
3683                         return 333000;
3684                 default:
3685                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3686                         return 190000;
3687                 }
3688         }
3689 }
3690
3691 static int i865_get_display_clock_speed(struct drm_device *dev)
3692 {
3693         return 266000;
3694 }
3695
3696 static int i855_get_display_clock_speed(struct drm_device *dev)
3697 {
3698         u16 hpllcc = 0;
3699         /* Assume that the hardware is in the high speed state.  This
3700          * should be the default.
3701          */
3702         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3703         case GC_CLOCK_133_200:
3704         case GC_CLOCK_100_200:
3705                 return 200000;
3706         case GC_CLOCK_166_250:
3707                 return 250000;
3708         case GC_CLOCK_100_133:
3709                 return 133000;
3710         }
3711
3712         /* Shouldn't happen */
3713         return 0;
3714 }
3715
3716 static int i830_get_display_clock_speed(struct drm_device *dev)
3717 {
3718         return 133000;
3719 }
3720
3721 struct fdi_m_n {
3722         u32        tu;
3723         u32        gmch_m;
3724         u32        gmch_n;
3725         u32        link_m;
3726         u32        link_n;
3727 };
3728
3729 static void
3730 fdi_reduce_ratio(u32 *num, u32 *den)
3731 {
3732         while (*num > 0xffffff || *den > 0xffffff) {
3733                 *num >>= 1;
3734                 *den >>= 1;
3735         }
3736 }
3737
3738 static void
3739 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3740                      int link_clock, struct fdi_m_n *m_n)
3741 {
3742         m_n->tu = 64; /* default size */
3743
3744         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3745         m_n->gmch_m = bits_per_pixel * pixel_clock;
3746         m_n->gmch_n = link_clock * nlanes * 8;
3747         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3748
3749         m_n->link_m = pixel_clock;
3750         m_n->link_n = link_clock;
3751         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3752 }
3753
3754 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3755 {
3756         if (i915_panel_use_ssc >= 0)
3757                 return i915_panel_use_ssc != 0;
3758         return dev_priv->lvds_use_ssc
3759                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3760 }
3761
3762 /**
3763  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3764  * @crtc: CRTC structure
3765  * @mode: requested mode
3766  *
3767  * A pipe may be connected to one or more outputs.  Based on the depth of the
3768  * attached framebuffer, choose a good color depth to use on the pipe.
3769  *
3770  * If possible, match the pipe depth to the fb depth.  In some cases, this
3771  * isn't ideal, because the connected output supports a lesser or restricted
3772  * set of depths.  Resolve that here:
3773  *    LVDS typically supports only 6bpc, so clamp down in that case
3774  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3775  *    Displays may support a restricted set as well, check EDID and clamp as
3776  *      appropriate.
3777  *    DP may want to dither down to 6bpc to fit larger modes
3778  *
3779  * RETURNS:
3780  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3781  * true if they don't match).
3782  */
3783 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3784                                          struct drm_framebuffer *fb,
3785                                          unsigned int *pipe_bpp,
3786                                          struct drm_display_mode *mode)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_i915_private *dev_priv = dev->dev_private;
3790         struct drm_connector *connector;
3791         struct intel_encoder *intel_encoder;
3792         unsigned int display_bpc = UINT_MAX, bpc;
3793
3794         /* Walk the encoders & connectors on this crtc, get min bpc */
3795         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3796
3797                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3798                         unsigned int lvds_bpc;
3799
3800                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3801                             LVDS_A3_POWER_UP)
3802                                 lvds_bpc = 8;
3803                         else
3804                                 lvds_bpc = 6;
3805
3806                         if (lvds_bpc < display_bpc) {
3807                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3808                                 display_bpc = lvds_bpc;
3809                         }
3810                         continue;
3811                 }
3812
3813                 /* Not one of the known troublemakers, check the EDID */
3814                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3815                                     head) {
3816                         if (connector->encoder != &intel_encoder->base)
3817                                 continue;
3818
3819                         /* Don't use an invalid EDID bpc value */
3820                         if (connector->display_info.bpc &&
3821                             connector->display_info.bpc < display_bpc) {
3822                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3823                                 display_bpc = connector->display_info.bpc;
3824                         }
3825                 }
3826
3827                 /*
3828                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3829                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3830                  */
3831                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3832                         if (display_bpc > 8 && display_bpc < 12) {
3833                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3834                                 display_bpc = 12;
3835                         } else {
3836                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3837                                 display_bpc = 8;
3838                         }
3839                 }
3840         }
3841
3842         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3843                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3844                 display_bpc = 6;
3845         }
3846
3847         /*
3848          * We could just drive the pipe at the highest bpc all the time and
3849          * enable dithering as needed, but that costs bandwidth.  So choose
3850          * the minimum value that expresses the full color range of the fb but
3851          * also stays within the max display bpc discovered above.
3852          */
3853
3854         switch (fb->depth) {
3855         case 8:
3856                 bpc = 8; /* since we go through a colormap */
3857                 break;
3858         case 15:
3859         case 16:
3860                 bpc = 6; /* min is 18bpp */
3861                 break;
3862         case 24:
3863                 bpc = 8;
3864                 break;
3865         case 30:
3866                 bpc = 10;
3867                 break;
3868         case 48:
3869                 bpc = 12;
3870                 break;
3871         default:
3872                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3873                 bpc = min((unsigned int)8, display_bpc);
3874                 break;
3875         }
3876
3877         display_bpc = min(display_bpc, bpc);
3878
3879         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3880                       bpc, display_bpc);
3881
3882         *pipe_bpp = display_bpc * 3;
3883
3884         return display_bpc != bpc;
3885 }
3886
3887 static int vlv_get_refclk(struct drm_crtc *crtc)
3888 {
3889         struct drm_device *dev = crtc->dev;
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891         int refclk = 27000; /* for DP & HDMI */
3892
3893         return 100000; /* only one validated so far */
3894
3895         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3896                 refclk = 96000;
3897         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3898                 if (intel_panel_use_ssc(dev_priv))
3899                         refclk = 100000;
3900                 else
3901                         refclk = 96000;
3902         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3903                 refclk = 100000;
3904         }
3905
3906         return refclk;
3907 }
3908
3909 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3910 {
3911         struct drm_device *dev = crtc->dev;
3912         struct drm_i915_private *dev_priv = dev->dev_private;
3913         int refclk;
3914
3915         if (IS_VALLEYVIEW(dev)) {
3916                 refclk = vlv_get_refclk(crtc);
3917         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3918             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3919                 refclk = dev_priv->lvds_ssc_freq * 1000;
3920                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3921                               refclk / 1000);
3922         } else if (!IS_GEN2(dev)) {
3923                 refclk = 96000;
3924         } else {
3925                 refclk = 48000;
3926         }
3927
3928         return refclk;
3929 }
3930
3931 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3932                                       intel_clock_t *clock)
3933 {
3934         /* SDVO TV has fixed PLL values depend on its clock range,
3935            this mirrors vbios setting. */
3936         if (adjusted_mode->clock >= 100000
3937             && adjusted_mode->clock < 140500) {
3938                 clock->p1 = 2;
3939                 clock->p2 = 10;
3940                 clock->n = 3;
3941                 clock->m1 = 16;
3942                 clock->m2 = 8;
3943         } else if (adjusted_mode->clock >= 140500
3944                    && adjusted_mode->clock <= 200000) {
3945                 clock->p1 = 1;
3946                 clock->p2 = 10;
3947                 clock->n = 6;
3948                 clock->m1 = 12;
3949                 clock->m2 = 8;
3950         }
3951 }
3952
3953 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3954                                      intel_clock_t *clock,
3955                                      intel_clock_t *reduced_clock)
3956 {
3957         struct drm_device *dev = crtc->dev;
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960         int pipe = intel_crtc->pipe;
3961         u32 fp, fp2 = 0;
3962
3963         if (IS_PINEVIEW(dev)) {
3964                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3965                 if (reduced_clock)
3966                         fp2 = (1 << reduced_clock->n) << 16 |
3967                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3968         } else {
3969                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3970                 if (reduced_clock)
3971                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3972                                 reduced_clock->m2;
3973         }
3974
3975         I915_WRITE(FP0(pipe), fp);
3976
3977         intel_crtc->lowfreq_avail = false;
3978         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3979             reduced_clock && i915_powersave) {
3980                 I915_WRITE(FP1(pipe), fp2);
3981                 intel_crtc->lowfreq_avail = true;
3982         } else {
3983                 I915_WRITE(FP1(pipe), fp);
3984         }
3985 }
3986
3987 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3988                               struct drm_display_mode *adjusted_mode)
3989 {
3990         struct drm_device *dev = crtc->dev;
3991         struct drm_i915_private *dev_priv = dev->dev_private;
3992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993         int pipe = intel_crtc->pipe;
3994         u32 temp;
3995
3996         temp = I915_READ(LVDS);
3997         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3998         if (pipe == 1) {
3999                 temp |= LVDS_PIPEB_SELECT;
4000         } else {
4001                 temp &= ~LVDS_PIPEB_SELECT;
4002         }
4003         /* set the corresponsding LVDS_BORDER bit */
4004         temp |= dev_priv->lvds_border_bits;
4005         /* Set the B0-B3 data pairs corresponding to whether we're going to
4006          * set the DPLLs for dual-channel mode or not.
4007          */
4008         if (clock->p2 == 7)
4009                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4010         else
4011                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4012
4013         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4014          * appropriately here, but we need to look more thoroughly into how
4015          * panels behave in the two modes.
4016          */
4017         /* set the dithering flag on LVDS as needed */
4018         if (INTEL_INFO(dev)->gen >= 4) {
4019                 if (dev_priv->lvds_dither)
4020                         temp |= LVDS_ENABLE_DITHER;
4021                 else
4022                         temp &= ~LVDS_ENABLE_DITHER;
4023         }
4024         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4025         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4026                 temp |= LVDS_HSYNC_POLARITY;
4027         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4028                 temp |= LVDS_VSYNC_POLARITY;
4029         I915_WRITE(LVDS, temp);
4030 }
4031
4032 static void vlv_update_pll(struct drm_crtc *crtc,
4033                            struct drm_display_mode *mode,
4034                            struct drm_display_mode *adjusted_mode,
4035                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4036                            int refclk, int num_connectors)
4037 {
4038         struct drm_device *dev = crtc->dev;
4039         struct drm_i915_private *dev_priv = dev->dev_private;
4040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4041         int pipe = intel_crtc->pipe;
4042         u32 dpll, mdiv, pdiv;
4043         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4044         bool is_hdmi;
4045
4046         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4047
4048         bestn = clock->n;
4049         bestm1 = clock->m1;
4050         bestm2 = clock->m2;
4051         bestp1 = clock->p1;
4052         bestp2 = clock->p2;
4053
4054         /* Enable DPIO clock input */
4055         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4056                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4057         I915_WRITE(DPLL(pipe), dpll);
4058         POSTING_READ(DPLL(pipe));
4059
4060         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4061         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4062         mdiv |= ((bestn << DPIO_N_SHIFT));
4063         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4064         mdiv |= (1 << DPIO_K_SHIFT);
4065         mdiv |= DPIO_ENABLE_CALIBRATION;
4066         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4067
4068         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4069
4070         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4071                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4072                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4073         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4074
4075         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4076
4077         dpll |= DPLL_VCO_ENABLE;
4078         I915_WRITE(DPLL(pipe), dpll);
4079         POSTING_READ(DPLL(pipe));
4080         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4081                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4082
4083         if (is_hdmi) {
4084                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4085
4086                 if (temp > 1)
4087                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4088                 else
4089                         temp = 0;
4090
4091                 I915_WRITE(DPLL_MD(pipe), temp);
4092                 POSTING_READ(DPLL_MD(pipe));
4093         }
4094
4095         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4096 }
4097
4098 static void i9xx_update_pll(struct drm_crtc *crtc,
4099                             struct drm_display_mode *mode,
4100                             struct drm_display_mode *adjusted_mode,
4101                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4102                             int num_connectors)
4103 {
4104         struct drm_device *dev = crtc->dev;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107         int pipe = intel_crtc->pipe;
4108         u32 dpll;
4109         bool is_sdvo;
4110
4111         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4112                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4113
4114         dpll = DPLL_VGA_MODE_DIS;
4115
4116         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4117                 dpll |= DPLLB_MODE_LVDS;
4118         else
4119                 dpll |= DPLLB_MODE_DAC_SERIAL;
4120         if (is_sdvo) {
4121                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4122                 if (pixel_multiplier > 1) {
4123                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4124                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4125                 }
4126                 dpll |= DPLL_DVO_HIGH_SPEED;
4127         }
4128         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4129                 dpll |= DPLL_DVO_HIGH_SPEED;
4130
4131         /* compute bitmask from p1 value */
4132         if (IS_PINEVIEW(dev))
4133                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4134         else {
4135                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4136                 if (IS_G4X(dev) && reduced_clock)
4137                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4138         }
4139         switch (clock->p2) {
4140         case 5:
4141                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4142                 break;
4143         case 7:
4144                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4145                 break;
4146         case 10:
4147                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4148                 break;
4149         case 14:
4150                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4151                 break;
4152         }
4153         if (INTEL_INFO(dev)->gen >= 4)
4154                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4155
4156         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4157                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4158         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4159                 /* XXX: just matching BIOS for now */
4160                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4161                 dpll |= 3;
4162         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4163                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4164                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4165         else
4166                 dpll |= PLL_REF_INPUT_DREFCLK;
4167
4168         dpll |= DPLL_VCO_ENABLE;
4169         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4170         POSTING_READ(DPLL(pipe));
4171         udelay(150);
4172
4173         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4174          * This is an exception to the general rule that mode_set doesn't turn
4175          * things on.
4176          */
4177         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4178                 intel_update_lvds(crtc, clock, adjusted_mode);
4179
4180         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4181                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4182
4183         I915_WRITE(DPLL(pipe), dpll);
4184
4185         /* Wait for the clocks to stabilize. */
4186         POSTING_READ(DPLL(pipe));
4187         udelay(150);
4188
4189         if (INTEL_INFO(dev)->gen >= 4) {
4190                 u32 temp = 0;
4191                 if (is_sdvo) {
4192                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4193                         if (temp > 1)
4194                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4195                         else
4196                                 temp = 0;
4197                 }
4198                 I915_WRITE(DPLL_MD(pipe), temp);
4199         } else {
4200                 /* The pixel multiplier can only be updated once the
4201                  * DPLL is enabled and the clocks are stable.
4202                  *
4203                  * So write it again.
4204                  */
4205                 I915_WRITE(DPLL(pipe), dpll);
4206         }
4207 }
4208
4209 static void i8xx_update_pll(struct drm_crtc *crtc,
4210                             struct drm_display_mode *adjusted_mode,
4211                             intel_clock_t *clock,
4212                             int num_connectors)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         int pipe = intel_crtc->pipe;
4218         u32 dpll;
4219
4220         dpll = DPLL_VGA_MODE_DIS;
4221
4222         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4223                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4224         } else {
4225                 if (clock->p1 == 2)
4226                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4227                 else
4228                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4229                 if (clock->p2 == 4)
4230                         dpll |= PLL_P2_DIVIDE_BY_4;
4231         }
4232
4233         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4234                 /* XXX: just matching BIOS for now */
4235                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4236                 dpll |= 3;
4237         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4238                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4239                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4240         else
4241                 dpll |= PLL_REF_INPUT_DREFCLK;
4242
4243         dpll |= DPLL_VCO_ENABLE;
4244         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4245         POSTING_READ(DPLL(pipe));
4246         udelay(150);
4247
4248         I915_WRITE(DPLL(pipe), dpll);
4249
4250         /* Wait for the clocks to stabilize. */
4251         POSTING_READ(DPLL(pipe));
4252         udelay(150);
4253
4254         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4255          * This is an exception to the general rule that mode_set doesn't turn
4256          * things on.
4257          */
4258         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4259                 intel_update_lvds(crtc, clock, adjusted_mode);
4260
4261         /* The pixel multiplier can only be updated once the
4262          * DPLL is enabled and the clocks are stable.
4263          *
4264          * So write it again.
4265          */
4266         I915_WRITE(DPLL(pipe), dpll);
4267 }
4268
4269 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4270                               struct drm_display_mode *mode,
4271                               struct drm_display_mode *adjusted_mode,
4272                               int x, int y,
4273                               struct drm_framebuffer *fb)
4274 {
4275         struct drm_device *dev = crtc->dev;
4276         struct drm_i915_private *dev_priv = dev->dev_private;
4277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278         int pipe = intel_crtc->pipe;
4279         int plane = intel_crtc->plane;
4280         int refclk, num_connectors = 0;
4281         intel_clock_t clock, reduced_clock;
4282         u32 dspcntr, pipeconf, vsyncshift;
4283         bool ok, has_reduced_clock = false, is_sdvo = false;
4284         bool is_lvds = false, is_tv = false, is_dp = false;
4285         struct intel_encoder *encoder;
4286         const intel_limit_t *limit;
4287         int ret;
4288
4289         for_each_encoder_on_crtc(dev, crtc, encoder) {
4290                 switch (encoder->type) {
4291                 case INTEL_OUTPUT_LVDS:
4292                         is_lvds = true;
4293                         break;
4294                 case INTEL_OUTPUT_SDVO:
4295                 case INTEL_OUTPUT_HDMI:
4296                         is_sdvo = true;
4297                         if (encoder->needs_tv_clock)
4298                                 is_tv = true;
4299                         break;
4300                 case INTEL_OUTPUT_TVOUT:
4301                         is_tv = true;
4302                         break;
4303                 case INTEL_OUTPUT_DISPLAYPORT:
4304                         is_dp = true;
4305                         break;
4306                 }
4307
4308                 num_connectors++;
4309         }
4310
4311         refclk = i9xx_get_refclk(crtc, num_connectors);
4312
4313         /*
4314          * Returns a set of divisors for the desired target clock with the given
4315          * refclk, or FALSE.  The returned values represent the clock equation:
4316          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4317          */
4318         limit = intel_limit(crtc, refclk);
4319         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4320                              &clock);
4321         if (!ok) {
4322                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4323                 return -EINVAL;
4324         }
4325
4326         /* Ensure that the cursor is valid for the new mode before changing... */
4327         intel_crtc_update_cursor(crtc, true);
4328
4329         if (is_lvds && dev_priv->lvds_downclock_avail) {
4330                 /*
4331                  * Ensure we match the reduced clock's P to the target clock.
4332                  * If the clocks don't match, we can't switch the display clock
4333                  * by using the FP0/FP1. In such case we will disable the LVDS
4334                  * downclock feature.
4335                 */
4336                 has_reduced_clock = limit->find_pll(limit, crtc,
4337                                                     dev_priv->lvds_downclock,
4338                                                     refclk,
4339                                                     &clock,
4340                                                     &reduced_clock);
4341         }
4342
4343         if (is_sdvo && is_tv)
4344                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4345
4346         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4347                                  &reduced_clock : NULL);
4348
4349         if (IS_GEN2(dev))
4350                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4351         else if (IS_VALLEYVIEW(dev))
4352                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4353                                refclk, num_connectors);
4354         else
4355                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4356                                 has_reduced_clock ? &reduced_clock : NULL,
4357                                 num_connectors);
4358
4359         /* setup pipeconf */
4360         pipeconf = I915_READ(PIPECONF(pipe));
4361
4362         /* Set up the display plane register */
4363         dspcntr = DISPPLANE_GAMMA_ENABLE;
4364
4365         if (pipe == 0)
4366                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4367         else
4368                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4369
4370         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4371                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4372                  * core speed.
4373                  *
4374                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4375                  * pipe == 0 check?
4376                  */
4377                 if (mode->clock >
4378                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4379                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4380                 else
4381                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4382         }
4383
4384         /* default to 8bpc */
4385         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4386         if (is_dp) {
4387                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4388                         pipeconf |= PIPECONF_BPP_6 |
4389                                     PIPECONF_DITHER_EN |
4390                                     PIPECONF_DITHER_TYPE_SP;
4391                 }
4392         }
4393
4394         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4395         drm_mode_debug_printmodeline(mode);
4396
4397         if (HAS_PIPE_CXSR(dev)) {
4398                 if (intel_crtc->lowfreq_avail) {
4399                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4400                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4401                 } else {
4402                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4403                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4404                 }
4405         }
4406
4407         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4408         if (!IS_GEN2(dev) &&
4409             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4410                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4411                 /* the chip adds 2 halflines automatically */
4412                 adjusted_mode->crtc_vtotal -= 1;
4413                 adjusted_mode->crtc_vblank_end -= 1;
4414                 vsyncshift = adjusted_mode->crtc_hsync_start
4415                              - adjusted_mode->crtc_htotal/2;
4416         } else {
4417                 pipeconf |= PIPECONF_PROGRESSIVE;
4418                 vsyncshift = 0;
4419         }
4420
4421         if (!IS_GEN3(dev))
4422                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4423
4424         I915_WRITE(HTOTAL(pipe),
4425                    (adjusted_mode->crtc_hdisplay - 1) |
4426                    ((adjusted_mode->crtc_htotal - 1) << 16));
4427         I915_WRITE(HBLANK(pipe),
4428                    (adjusted_mode->crtc_hblank_start - 1) |
4429                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4430         I915_WRITE(HSYNC(pipe),
4431                    (adjusted_mode->crtc_hsync_start - 1) |
4432                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4433
4434         I915_WRITE(VTOTAL(pipe),
4435                    (adjusted_mode->crtc_vdisplay - 1) |
4436                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4437         I915_WRITE(VBLANK(pipe),
4438                    (adjusted_mode->crtc_vblank_start - 1) |
4439                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4440         I915_WRITE(VSYNC(pipe),
4441                    (adjusted_mode->crtc_vsync_start - 1) |
4442                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4443
4444         /* pipesrc and dspsize control the size that is scaled from,
4445          * which should always be the user's requested size.
4446          */
4447         I915_WRITE(DSPSIZE(plane),
4448                    ((mode->vdisplay - 1) << 16) |
4449                    (mode->hdisplay - 1));
4450         I915_WRITE(DSPPOS(plane), 0);
4451         I915_WRITE(PIPESRC(pipe),
4452                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4453
4454         I915_WRITE(PIPECONF(pipe), pipeconf);
4455         POSTING_READ(PIPECONF(pipe));
4456         intel_enable_pipe(dev_priv, pipe, false);
4457
4458         intel_wait_for_vblank(dev, pipe);
4459
4460         I915_WRITE(DSPCNTR(plane), dspcntr);
4461         POSTING_READ(DSPCNTR(plane));
4462
4463         ret = intel_pipe_set_base(crtc, x, y, fb);
4464
4465         intel_update_watermarks(dev);
4466
4467         return ret;
4468 }
4469
4470 /*
4471  * Initialize reference clocks when the driver loads
4472  */
4473 void ironlake_init_pch_refclk(struct drm_device *dev)
4474 {
4475         struct drm_i915_private *dev_priv = dev->dev_private;
4476         struct drm_mode_config *mode_config = &dev->mode_config;
4477         struct intel_encoder *encoder;
4478         u32 temp;
4479         bool has_lvds = false;
4480         bool has_cpu_edp = false;
4481         bool has_pch_edp = false;
4482         bool has_panel = false;
4483         bool has_ck505 = false;
4484         bool can_ssc = false;
4485
4486         /* We need to take the global config into account */
4487         list_for_each_entry(encoder, &mode_config->encoder_list,
4488                             base.head) {
4489                 switch (encoder->type) {
4490                 case INTEL_OUTPUT_LVDS:
4491                         has_panel = true;
4492                         has_lvds = true;
4493                         break;
4494                 case INTEL_OUTPUT_EDP:
4495                         has_panel = true;
4496                         if (intel_encoder_is_pch_edp(&encoder->base))
4497                                 has_pch_edp = true;
4498                         else
4499                                 has_cpu_edp = true;
4500                         break;
4501                 }
4502         }
4503
4504         if (HAS_PCH_IBX(dev)) {
4505                 has_ck505 = dev_priv->display_clock_mode;
4506                 can_ssc = has_ck505;
4507         } else {
4508                 has_ck505 = false;
4509                 can_ssc = true;
4510         }
4511
4512         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4513                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4514                       has_ck505);
4515
4516         /* Ironlake: try to setup display ref clock before DPLL
4517          * enabling. This is only under driver's control after
4518          * PCH B stepping, previous chipset stepping should be
4519          * ignoring this setting.
4520          */
4521         temp = I915_READ(PCH_DREF_CONTROL);
4522         /* Always enable nonspread source */
4523         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4524
4525         if (has_ck505)
4526                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4527         else
4528                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4529
4530         if (has_panel) {
4531                 temp &= ~DREF_SSC_SOURCE_MASK;
4532                 temp |= DREF_SSC_SOURCE_ENABLE;
4533
4534                 /* SSC must be turned on before enabling the CPU output  */
4535                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4536                         DRM_DEBUG_KMS("Using SSC on panel\n");
4537                         temp |= DREF_SSC1_ENABLE;
4538                 } else
4539                         temp &= ~DREF_SSC1_ENABLE;
4540
4541                 /* Get SSC going before enabling the outputs */
4542                 I915_WRITE(PCH_DREF_CONTROL, temp);
4543                 POSTING_READ(PCH_DREF_CONTROL);
4544                 udelay(200);
4545
4546                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4547
4548                 /* Enable CPU source on CPU attached eDP */
4549                 if (has_cpu_edp) {
4550                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4551                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4552                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4553                         }
4554                         else
4555                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4556                 } else
4557                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4558
4559                 I915_WRITE(PCH_DREF_CONTROL, temp);
4560                 POSTING_READ(PCH_DREF_CONTROL);
4561                 udelay(200);
4562         } else {
4563                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4564
4565                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4566
4567                 /* Turn off CPU output */
4568                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4569
4570                 I915_WRITE(PCH_DREF_CONTROL, temp);
4571                 POSTING_READ(PCH_DREF_CONTROL);
4572                 udelay(200);
4573
4574                 /* Turn off the SSC source */
4575                 temp &= ~DREF_SSC_SOURCE_MASK;
4576                 temp |= DREF_SSC_SOURCE_DISABLE;
4577
4578                 /* Turn off SSC1 */
4579                 temp &= ~ DREF_SSC1_ENABLE;
4580
4581                 I915_WRITE(PCH_DREF_CONTROL, temp);
4582                 POSTING_READ(PCH_DREF_CONTROL);
4583                 udelay(200);
4584         }
4585 }
4586
4587 static int ironlake_get_refclk(struct drm_crtc *crtc)
4588 {
4589         struct drm_device *dev = crtc->dev;
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_encoder *encoder;
4592         struct intel_encoder *edp_encoder = NULL;
4593         int num_connectors = 0;
4594         bool is_lvds = false;
4595
4596         for_each_encoder_on_crtc(dev, crtc, encoder) {
4597                 switch (encoder->type) {
4598                 case INTEL_OUTPUT_LVDS:
4599                         is_lvds = true;
4600                         break;
4601                 case INTEL_OUTPUT_EDP:
4602                         edp_encoder = encoder;
4603                         break;
4604                 }
4605                 num_connectors++;
4606         }
4607
4608         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4609                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4610                               dev_priv->lvds_ssc_freq);
4611                 return dev_priv->lvds_ssc_freq * 1000;
4612         }
4613
4614         return 120000;
4615 }
4616
4617 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4618                                   struct drm_display_mode *mode,
4619                                   struct drm_display_mode *adjusted_mode,
4620                                   int x, int y,
4621                                   struct drm_framebuffer *fb)
4622 {
4623         struct drm_device *dev = crtc->dev;
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         int pipe = intel_crtc->pipe;
4627         int plane = intel_crtc->plane;
4628         int refclk, num_connectors = 0;
4629         intel_clock_t clock, reduced_clock;
4630         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4631         bool ok, has_reduced_clock = false, is_sdvo = false;
4632         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4633         struct intel_encoder *encoder, *edp_encoder = NULL;
4634         const intel_limit_t *limit;
4635         int ret;
4636         struct fdi_m_n m_n = {0};
4637         u32 temp;
4638         int target_clock, pixel_multiplier, lane, link_bw, factor;
4639         unsigned int pipe_bpp;
4640         bool dither;
4641         bool is_cpu_edp = false, is_pch_edp = false;
4642
4643         for_each_encoder_on_crtc(dev, crtc, encoder) {
4644                 switch (encoder->type) {
4645                 case INTEL_OUTPUT_LVDS:
4646                         is_lvds = true;
4647                         break;
4648                 case INTEL_OUTPUT_SDVO:
4649                 case INTEL_OUTPUT_HDMI:
4650                         is_sdvo = true;
4651                         if (encoder->needs_tv_clock)
4652                                 is_tv = true;
4653                         break;
4654                 case INTEL_OUTPUT_TVOUT:
4655                         is_tv = true;
4656                         break;
4657                 case INTEL_OUTPUT_ANALOG:
4658                         is_crt = true;
4659                         break;
4660                 case INTEL_OUTPUT_DISPLAYPORT:
4661                         is_dp = true;
4662                         break;
4663                 case INTEL_OUTPUT_EDP:
4664                         is_dp = true;
4665                         if (intel_encoder_is_pch_edp(&encoder->base))
4666                                 is_pch_edp = true;
4667                         else
4668                                 is_cpu_edp = true;
4669                         edp_encoder = encoder;
4670                         break;
4671                 }
4672
4673                 num_connectors++;
4674         }
4675
4676         refclk = ironlake_get_refclk(crtc);
4677
4678         /*
4679          * Returns a set of divisors for the desired target clock with the given
4680          * refclk, or FALSE.  The returned values represent the clock equation:
4681          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4682          */
4683         limit = intel_limit(crtc, refclk);
4684         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4685                              &clock);
4686         if (!ok) {
4687                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4688                 return -EINVAL;
4689         }
4690
4691         /* Ensure that the cursor is valid for the new mode before changing... */
4692         intel_crtc_update_cursor(crtc, true);
4693
4694         if (is_lvds && dev_priv->lvds_downclock_avail) {
4695                 /*
4696                  * Ensure we match the reduced clock's P to the target clock.
4697                  * If the clocks don't match, we can't switch the display clock
4698                  * by using the FP0/FP1. In such case we will disable the LVDS
4699                  * downclock feature.
4700                 */
4701                 has_reduced_clock = limit->find_pll(limit, crtc,
4702                                                     dev_priv->lvds_downclock,
4703                                                     refclk,
4704                                                     &clock,
4705                                                     &reduced_clock);
4706         }
4707
4708         if (is_sdvo && is_tv)
4709                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4710
4711
4712         /* FDI link */
4713         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4714         lane = 0;
4715         /* CPU eDP doesn't require FDI link, so just set DP M/N
4716            according to current link config */
4717         if (is_cpu_edp) {
4718                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4719         } else {
4720                 /* FDI is a binary signal running at ~2.7GHz, encoding
4721                  * each output octet as 10 bits. The actual frequency
4722                  * is stored as a divider into a 100MHz clock, and the
4723                  * mode pixel clock is stored in units of 1KHz.
4724                  * Hence the bw of each lane in terms of the mode signal
4725                  * is:
4726                  */
4727                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4728         }
4729
4730         /* [e]DP over FDI requires target mode clock instead of link clock. */
4731         if (edp_encoder)
4732                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4733         else if (is_dp)
4734                 target_clock = mode->clock;
4735         else
4736                 target_clock = adjusted_mode->clock;
4737
4738         /* determine panel color depth */
4739         temp = I915_READ(PIPECONF(pipe));
4740         temp &= ~PIPE_BPC_MASK;
4741         dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
4742         switch (pipe_bpp) {
4743         case 18:
4744                 temp |= PIPE_6BPC;
4745                 break;
4746         case 24:
4747                 temp |= PIPE_8BPC;
4748                 break;
4749         case 30:
4750                 temp |= PIPE_10BPC;
4751                 break;
4752         case 36:
4753                 temp |= PIPE_12BPC;
4754                 break;
4755         default:
4756                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4757                         pipe_bpp);
4758                 temp |= PIPE_8BPC;
4759                 pipe_bpp = 24;
4760                 break;
4761         }
4762
4763         intel_crtc->bpp = pipe_bpp;
4764         I915_WRITE(PIPECONF(pipe), temp);
4765
4766         if (!lane) {
4767                 /*
4768                  * Account for spread spectrum to avoid
4769                  * oversubscribing the link. Max center spread
4770                  * is 2.5%; use 5% for safety's sake.
4771                  */
4772                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4773                 lane = bps / (link_bw * 8) + 1;
4774         }
4775
4776         intel_crtc->fdi_lanes = lane;
4777
4778         if (pixel_multiplier > 1)
4779                 link_bw *= pixel_multiplier;
4780         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4781                              &m_n);
4782
4783         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4784         if (has_reduced_clock)
4785                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4786                         reduced_clock.m2;
4787
4788         /* Enable autotuning of the PLL clock (if permissible) */
4789         factor = 21;
4790         if (is_lvds) {
4791                 if ((intel_panel_use_ssc(dev_priv) &&
4792                      dev_priv->lvds_ssc_freq == 100) ||
4793                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4794                         factor = 25;
4795         } else if (is_sdvo && is_tv)
4796                 factor = 20;
4797
4798         if (clock.m < factor * clock.n)
4799                 fp |= FP_CB_TUNE;
4800
4801         dpll = 0;
4802
4803         if (is_lvds)
4804                 dpll |= DPLLB_MODE_LVDS;
4805         else
4806                 dpll |= DPLLB_MODE_DAC_SERIAL;
4807         if (is_sdvo) {
4808                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4809                 if (pixel_multiplier > 1) {
4810                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4811                 }
4812                 dpll |= DPLL_DVO_HIGH_SPEED;
4813         }
4814         if (is_dp && !is_cpu_edp)
4815                 dpll |= DPLL_DVO_HIGH_SPEED;
4816
4817         /* compute bitmask from p1 value */
4818         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4819         /* also FPA1 */
4820         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4821
4822         switch (clock.p2) {
4823         case 5:
4824                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4825                 break;
4826         case 7:
4827                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4828                 break;
4829         case 10:
4830                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4831                 break;
4832         case 14:
4833                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4834                 break;
4835         }
4836
4837         if (is_sdvo && is_tv)
4838                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4839         else if (is_tv)
4840                 /* XXX: just matching BIOS for now */
4841                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4842                 dpll |= 3;
4843         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4844                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4845         else
4846                 dpll |= PLL_REF_INPUT_DREFCLK;
4847
4848         /* setup pipeconf */
4849         pipeconf = I915_READ(PIPECONF(pipe));
4850
4851         /* Set up the display plane register */
4852         dspcntr = DISPPLANE_GAMMA_ENABLE;
4853
4854         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4855         drm_mode_debug_printmodeline(mode);
4856
4857         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4858          * pre-Haswell/LPT generation */
4859         if (HAS_PCH_LPT(dev)) {
4860                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4861                                 pipe);
4862         } else if (!is_cpu_edp) {
4863                 struct intel_pch_pll *pll;
4864
4865                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4866                 if (pll == NULL) {
4867                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4868                                          pipe);
4869                         return -EINVAL;
4870                 }
4871         } else
4872                 intel_put_pch_pll(intel_crtc);
4873
4874         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4875          * This is an exception to the general rule that mode_set doesn't turn
4876          * things on.
4877          */
4878         if (is_lvds) {
4879                 temp = I915_READ(PCH_LVDS);
4880                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4881                 if (HAS_PCH_CPT(dev)) {
4882                         temp &= ~PORT_TRANS_SEL_MASK;
4883                         temp |= PORT_TRANS_SEL_CPT(pipe);
4884                 } else {
4885                         if (pipe == 1)
4886                                 temp |= LVDS_PIPEB_SELECT;
4887                         else
4888                                 temp &= ~LVDS_PIPEB_SELECT;
4889                 }
4890
4891                 /* set the corresponsding LVDS_BORDER bit */
4892                 temp |= dev_priv->lvds_border_bits;
4893                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4894                  * set the DPLLs for dual-channel mode or not.
4895                  */
4896                 if (clock.p2 == 7)
4897                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4898                 else
4899                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4900
4901                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4902                  * appropriately here, but we need to look more thoroughly into how
4903                  * panels behave in the two modes.
4904                  */
4905                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4906                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4907                         temp |= LVDS_HSYNC_POLARITY;
4908                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4909                         temp |= LVDS_VSYNC_POLARITY;
4910                 I915_WRITE(PCH_LVDS, temp);
4911         }
4912
4913         pipeconf &= ~PIPECONF_DITHER_EN;
4914         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4915         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4916                 pipeconf |= PIPECONF_DITHER_EN;
4917                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4918         }
4919         if (is_dp && !is_cpu_edp) {
4920                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4921         } else {
4922                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4923                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4924                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4925                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4926                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4927         }
4928
4929         if (intel_crtc->pch_pll) {
4930                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4931
4932                 /* Wait for the clocks to stabilize. */
4933                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4934                 udelay(150);
4935
4936                 /* The pixel multiplier can only be updated once the
4937                  * DPLL is enabled and the clocks are stable.
4938                  *
4939                  * So write it again.
4940                  */
4941                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4942         }
4943
4944         intel_crtc->lowfreq_avail = false;
4945         if (intel_crtc->pch_pll) {
4946                 if (is_lvds && has_reduced_clock && i915_powersave) {
4947                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4948                         intel_crtc->lowfreq_avail = true;
4949                 } else {
4950                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4951                 }
4952         }
4953
4954         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4955         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4956                 pipeconf |= PIPECONF_INTERLACED_ILK;
4957                 /* the chip adds 2 halflines automatically */
4958                 adjusted_mode->crtc_vtotal -= 1;
4959                 adjusted_mode->crtc_vblank_end -= 1;
4960                 I915_WRITE(VSYNCSHIFT(pipe),
4961                            adjusted_mode->crtc_hsync_start
4962                            - adjusted_mode->crtc_htotal/2);
4963         } else {
4964                 pipeconf |= PIPECONF_PROGRESSIVE;
4965                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4966         }
4967
4968         I915_WRITE(HTOTAL(pipe),
4969                    (adjusted_mode->crtc_hdisplay - 1) |
4970                    ((adjusted_mode->crtc_htotal - 1) << 16));
4971         I915_WRITE(HBLANK(pipe),
4972                    (adjusted_mode->crtc_hblank_start - 1) |
4973                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4974         I915_WRITE(HSYNC(pipe),
4975                    (adjusted_mode->crtc_hsync_start - 1) |
4976                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4977
4978         I915_WRITE(VTOTAL(pipe),
4979                    (adjusted_mode->crtc_vdisplay - 1) |
4980                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4981         I915_WRITE(VBLANK(pipe),
4982                    (adjusted_mode->crtc_vblank_start - 1) |
4983                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4984         I915_WRITE(VSYNC(pipe),
4985                    (adjusted_mode->crtc_vsync_start - 1) |
4986                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4987
4988         /* pipesrc controls the size that is scaled from, which should
4989          * always be the user's requested size.
4990          */
4991         I915_WRITE(PIPESRC(pipe),
4992                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4993
4994         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4995         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4996         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4997         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4998
4999         if (is_cpu_edp)
5000                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5001
5002         I915_WRITE(PIPECONF(pipe), pipeconf);
5003         POSTING_READ(PIPECONF(pipe));
5004
5005         intel_wait_for_vblank(dev, pipe);
5006
5007         I915_WRITE(DSPCNTR(plane), dspcntr);
5008         POSTING_READ(DSPCNTR(plane));
5009
5010         ret = intel_pipe_set_base(crtc, x, y, fb);
5011
5012         intel_update_watermarks(dev);
5013
5014         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5015
5016         return ret;
5017 }
5018
5019 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5020                                struct drm_display_mode *mode,
5021                                struct drm_display_mode *adjusted_mode,
5022                                int x, int y,
5023                                struct drm_framebuffer *fb)
5024 {
5025         struct drm_device *dev = crtc->dev;
5026         struct drm_i915_private *dev_priv = dev->dev_private;
5027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028         int pipe = intel_crtc->pipe;
5029         int ret;
5030
5031         drm_vblank_pre_modeset(dev, pipe);
5032
5033         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5034                                               x, y, fb);
5035         drm_vblank_post_modeset(dev, pipe);
5036
5037         return ret;
5038 }
5039
5040 static bool intel_eld_uptodate(struct drm_connector *connector,
5041                                int reg_eldv, uint32_t bits_eldv,
5042                                int reg_elda, uint32_t bits_elda,
5043                                int reg_edid)
5044 {
5045         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5046         uint8_t *eld = connector->eld;
5047         uint32_t i;
5048
5049         i = I915_READ(reg_eldv);
5050         i &= bits_eldv;
5051
5052         if (!eld[0])
5053                 return !i;
5054
5055         if (!i)
5056                 return false;
5057
5058         i = I915_READ(reg_elda);
5059         i &= ~bits_elda;
5060         I915_WRITE(reg_elda, i);
5061
5062         for (i = 0; i < eld[2]; i++)
5063                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5064                         return false;
5065
5066         return true;
5067 }
5068
5069 static void g4x_write_eld(struct drm_connector *connector,
5070                           struct drm_crtc *crtc)
5071 {
5072         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073         uint8_t *eld = connector->eld;
5074         uint32_t eldv;
5075         uint32_t len;
5076         uint32_t i;
5077
5078         i = I915_READ(G4X_AUD_VID_DID);
5079
5080         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5081                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5082         else
5083                 eldv = G4X_ELDV_DEVCTG;
5084
5085         if (intel_eld_uptodate(connector,
5086                                G4X_AUD_CNTL_ST, eldv,
5087                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5088                                G4X_HDMIW_HDMIEDID))
5089                 return;
5090
5091         i = I915_READ(G4X_AUD_CNTL_ST);
5092         i &= ~(eldv | G4X_ELD_ADDR);
5093         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5094         I915_WRITE(G4X_AUD_CNTL_ST, i);
5095
5096         if (!eld[0])
5097                 return;
5098
5099         len = min_t(uint8_t, eld[2], len);
5100         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5101         for (i = 0; i < len; i++)
5102                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5103
5104         i = I915_READ(G4X_AUD_CNTL_ST);
5105         i |= eldv;
5106         I915_WRITE(G4X_AUD_CNTL_ST, i);
5107 }
5108
5109 static void haswell_write_eld(struct drm_connector *connector,
5110                                      struct drm_crtc *crtc)
5111 {
5112         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5113         uint8_t *eld = connector->eld;
5114         struct drm_device *dev = crtc->dev;
5115         uint32_t eldv;
5116         uint32_t i;
5117         int len;
5118         int pipe = to_intel_crtc(crtc)->pipe;
5119         int tmp;
5120
5121         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5122         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5123         int aud_config = HSW_AUD_CFG(pipe);
5124         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5125
5126
5127         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5128
5129         /* Audio output enable */
5130         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5131         tmp = I915_READ(aud_cntrl_st2);
5132         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5133         I915_WRITE(aud_cntrl_st2, tmp);
5134
5135         /* Wait for 1 vertical blank */
5136         intel_wait_for_vblank(dev, pipe);
5137
5138         /* Set ELD valid state */
5139         tmp = I915_READ(aud_cntrl_st2);
5140         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5141         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5142         I915_WRITE(aud_cntrl_st2, tmp);
5143         tmp = I915_READ(aud_cntrl_st2);
5144         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5145
5146         /* Enable HDMI mode */
5147         tmp = I915_READ(aud_config);
5148         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5149         /* clear N_programing_enable and N_value_index */
5150         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5151         I915_WRITE(aud_config, tmp);
5152
5153         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5154
5155         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5156
5157         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5158                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5159                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5160                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5161         } else
5162                 I915_WRITE(aud_config, 0);
5163
5164         if (intel_eld_uptodate(connector,
5165                                aud_cntrl_st2, eldv,
5166                                aud_cntl_st, IBX_ELD_ADDRESS,
5167                                hdmiw_hdmiedid))
5168                 return;
5169
5170         i = I915_READ(aud_cntrl_st2);
5171         i &= ~eldv;
5172         I915_WRITE(aud_cntrl_st2, i);
5173
5174         if (!eld[0])
5175                 return;
5176
5177         i = I915_READ(aud_cntl_st);
5178         i &= ~IBX_ELD_ADDRESS;
5179         I915_WRITE(aud_cntl_st, i);
5180         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5181         DRM_DEBUG_DRIVER("port num:%d\n", i);
5182
5183         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5184         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5185         for (i = 0; i < len; i++)
5186                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5187
5188         i = I915_READ(aud_cntrl_st2);
5189         i |= eldv;
5190         I915_WRITE(aud_cntrl_st2, i);
5191
5192 }
5193
5194 static void ironlake_write_eld(struct drm_connector *connector,
5195                                      struct drm_crtc *crtc)
5196 {
5197         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5198         uint8_t *eld = connector->eld;
5199         uint32_t eldv;
5200         uint32_t i;
5201         int len;
5202         int hdmiw_hdmiedid;
5203         int aud_config;
5204         int aud_cntl_st;
5205         int aud_cntrl_st2;
5206         int pipe = to_intel_crtc(crtc)->pipe;
5207
5208         if (HAS_PCH_IBX(connector->dev)) {
5209                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5210                 aud_config = IBX_AUD_CFG(pipe);
5211                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5212                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5213         } else {
5214                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5215                 aud_config = CPT_AUD_CFG(pipe);
5216                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5217                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5218         }
5219
5220         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5221
5222         i = I915_READ(aud_cntl_st);
5223         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5224         if (!i) {
5225                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5226                 /* operate blindly on all ports */
5227                 eldv = IBX_ELD_VALIDB;
5228                 eldv |= IBX_ELD_VALIDB << 4;
5229                 eldv |= IBX_ELD_VALIDB << 8;
5230         } else {
5231                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5232                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5233         }
5234
5235         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5236                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5237                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5238                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5239         } else
5240                 I915_WRITE(aud_config, 0);
5241
5242         if (intel_eld_uptodate(connector,
5243                                aud_cntrl_st2, eldv,
5244                                aud_cntl_st, IBX_ELD_ADDRESS,
5245                                hdmiw_hdmiedid))
5246                 return;
5247
5248         i = I915_READ(aud_cntrl_st2);
5249         i &= ~eldv;
5250         I915_WRITE(aud_cntrl_st2, i);
5251
5252         if (!eld[0])
5253                 return;
5254
5255         i = I915_READ(aud_cntl_st);
5256         i &= ~IBX_ELD_ADDRESS;
5257         I915_WRITE(aud_cntl_st, i);
5258
5259         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5260         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5261         for (i = 0; i < len; i++)
5262                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5263
5264         i = I915_READ(aud_cntrl_st2);
5265         i |= eldv;
5266         I915_WRITE(aud_cntrl_st2, i);
5267 }
5268
5269 void intel_write_eld(struct drm_encoder *encoder,
5270                      struct drm_display_mode *mode)
5271 {
5272         struct drm_crtc *crtc = encoder->crtc;
5273         struct drm_connector *connector;
5274         struct drm_device *dev = encoder->dev;
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276
5277         connector = drm_select_eld(encoder, mode);
5278         if (!connector)
5279                 return;
5280
5281         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5282                          connector->base.id,
5283                          drm_get_connector_name(connector),
5284                          connector->encoder->base.id,
5285                          drm_get_encoder_name(connector->encoder));
5286
5287         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5288
5289         if (dev_priv->display.write_eld)
5290                 dev_priv->display.write_eld(connector, crtc);
5291 }
5292
5293 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5294 void intel_crtc_load_lut(struct drm_crtc *crtc)
5295 {
5296         struct drm_device *dev = crtc->dev;
5297         struct drm_i915_private *dev_priv = dev->dev_private;
5298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5299         int palreg = PALETTE(intel_crtc->pipe);
5300         int i;
5301
5302         /* The clocks have to be on to load the palette. */
5303         if (!crtc->enabled || !intel_crtc->active)
5304                 return;
5305
5306         /* use legacy palette for Ironlake */
5307         if (HAS_PCH_SPLIT(dev))
5308                 palreg = LGC_PALETTE(intel_crtc->pipe);
5309
5310         for (i = 0; i < 256; i++) {
5311                 I915_WRITE(palreg + 4 * i,
5312                            (intel_crtc->lut_r[i] << 16) |
5313                            (intel_crtc->lut_g[i] << 8) |
5314                            intel_crtc->lut_b[i]);
5315         }
5316 }
5317
5318 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5319 {
5320         struct drm_device *dev = crtc->dev;
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323         bool visible = base != 0;
5324         u32 cntl;
5325
5326         if (intel_crtc->cursor_visible == visible)
5327                 return;
5328
5329         cntl = I915_READ(_CURACNTR);
5330         if (visible) {
5331                 /* On these chipsets we can only modify the base whilst
5332                  * the cursor is disabled.
5333                  */
5334                 I915_WRITE(_CURABASE, base);
5335
5336                 cntl &= ~(CURSOR_FORMAT_MASK);
5337                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5338                 cntl |= CURSOR_ENABLE |
5339                         CURSOR_GAMMA_ENABLE |
5340                         CURSOR_FORMAT_ARGB;
5341         } else
5342                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5343         I915_WRITE(_CURACNTR, cntl);
5344
5345         intel_crtc->cursor_visible = visible;
5346 }
5347
5348 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5349 {
5350         struct drm_device *dev = crtc->dev;
5351         struct drm_i915_private *dev_priv = dev->dev_private;
5352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353         int pipe = intel_crtc->pipe;
5354         bool visible = base != 0;
5355
5356         if (intel_crtc->cursor_visible != visible) {
5357                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5358                 if (base) {
5359                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5360                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5361                         cntl |= pipe << 28; /* Connect to correct pipe */
5362                 } else {
5363                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5364                         cntl |= CURSOR_MODE_DISABLE;
5365                 }
5366                 I915_WRITE(CURCNTR(pipe), cntl);
5367
5368                 intel_crtc->cursor_visible = visible;
5369         }
5370         /* and commit changes on next vblank */
5371         I915_WRITE(CURBASE(pipe), base);
5372 }
5373
5374 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5375 {
5376         struct drm_device *dev = crtc->dev;
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379         int pipe = intel_crtc->pipe;
5380         bool visible = base != 0;
5381
5382         if (intel_crtc->cursor_visible != visible) {
5383                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5384                 if (base) {
5385                         cntl &= ~CURSOR_MODE;
5386                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5387                 } else {
5388                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5389                         cntl |= CURSOR_MODE_DISABLE;
5390                 }
5391                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5392
5393                 intel_crtc->cursor_visible = visible;
5394         }
5395         /* and commit changes on next vblank */
5396         I915_WRITE(CURBASE_IVB(pipe), base);
5397 }
5398
5399 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5400 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5401                                      bool on)
5402 {
5403         struct drm_device *dev = crtc->dev;
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406         int pipe = intel_crtc->pipe;
5407         int x = intel_crtc->cursor_x;
5408         int y = intel_crtc->cursor_y;
5409         u32 base, pos;
5410         bool visible;
5411
5412         pos = 0;
5413
5414         if (on && crtc->enabled && crtc->fb) {
5415                 base = intel_crtc->cursor_addr;
5416                 if (x > (int) crtc->fb->width)
5417                         base = 0;
5418
5419                 if (y > (int) crtc->fb->height)
5420                         base = 0;
5421         } else
5422                 base = 0;
5423
5424         if (x < 0) {
5425                 if (x + intel_crtc->cursor_width < 0)
5426                         base = 0;
5427
5428                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5429                 x = -x;
5430         }
5431         pos |= x << CURSOR_X_SHIFT;
5432
5433         if (y < 0) {
5434                 if (y + intel_crtc->cursor_height < 0)
5435                         base = 0;
5436
5437                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5438                 y = -y;
5439         }
5440         pos |= y << CURSOR_Y_SHIFT;
5441
5442         visible = base != 0;
5443         if (!visible && !intel_crtc->cursor_visible)
5444                 return;
5445
5446         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5447                 I915_WRITE(CURPOS_IVB(pipe), pos);
5448                 ivb_update_cursor(crtc, base);
5449         } else {
5450                 I915_WRITE(CURPOS(pipe), pos);
5451                 if (IS_845G(dev) || IS_I865G(dev))
5452                         i845_update_cursor(crtc, base);
5453                 else
5454                         i9xx_update_cursor(crtc, base);
5455         }
5456 }
5457
5458 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5459                                  struct drm_file *file,
5460                                  uint32_t handle,
5461                                  uint32_t width, uint32_t height)
5462 {
5463         struct drm_device *dev = crtc->dev;
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5466         struct drm_i915_gem_object *obj;
5467         uint32_t addr;
5468         int ret;
5469
5470         /* if we want to turn off the cursor ignore width and height */
5471         if (!handle) {
5472                 DRM_DEBUG_KMS("cursor off\n");
5473                 addr = 0;
5474                 obj = NULL;
5475                 mutex_lock(&dev->struct_mutex);
5476                 goto finish;
5477         }
5478
5479         /* Currently we only support 64x64 cursors */
5480         if (width != 64 || height != 64) {
5481                 DRM_ERROR("we currently only support 64x64 cursors\n");
5482                 return -EINVAL;
5483         }
5484
5485         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5486         if (&obj->base == NULL)
5487                 return -ENOENT;
5488
5489         if (obj->base.size < width * height * 4) {
5490                 DRM_ERROR("buffer is to small\n");
5491                 ret = -ENOMEM;
5492                 goto fail;
5493         }
5494
5495         /* we only need to pin inside GTT if cursor is non-phy */
5496         mutex_lock(&dev->struct_mutex);
5497         if (!dev_priv->info->cursor_needs_physical) {
5498                 if (obj->tiling_mode) {
5499                         DRM_ERROR("cursor cannot be tiled\n");
5500                         ret = -EINVAL;
5501                         goto fail_locked;
5502                 }
5503
5504                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5505                 if (ret) {
5506                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5507                         goto fail_locked;
5508                 }
5509
5510                 ret = i915_gem_object_put_fence(obj);
5511                 if (ret) {
5512                         DRM_ERROR("failed to release fence for cursor");
5513                         goto fail_unpin;
5514                 }
5515
5516                 addr = obj->gtt_offset;
5517         } else {
5518                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5519                 ret = i915_gem_attach_phys_object(dev, obj,
5520                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5521                                                   align);
5522                 if (ret) {
5523                         DRM_ERROR("failed to attach phys object\n");
5524                         goto fail_locked;
5525                 }
5526                 addr = obj->phys_obj->handle->busaddr;
5527         }
5528
5529         if (IS_GEN2(dev))
5530                 I915_WRITE(CURSIZE, (height << 12) | width);
5531
5532  finish:
5533         if (intel_crtc->cursor_bo) {
5534                 if (dev_priv->info->cursor_needs_physical) {
5535                         if (intel_crtc->cursor_bo != obj)
5536                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5537                 } else
5538                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5539                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5540         }
5541
5542         mutex_unlock(&dev->struct_mutex);
5543
5544         intel_crtc->cursor_addr = addr;
5545         intel_crtc->cursor_bo = obj;
5546         intel_crtc->cursor_width = width;
5547         intel_crtc->cursor_height = height;
5548
5549         intel_crtc_update_cursor(crtc, true);
5550
5551         return 0;
5552 fail_unpin:
5553         i915_gem_object_unpin(obj);
5554 fail_locked:
5555         mutex_unlock(&dev->struct_mutex);
5556 fail:
5557         drm_gem_object_unreference_unlocked(&obj->base);
5558         return ret;
5559 }
5560
5561 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5562 {
5563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5564
5565         intel_crtc->cursor_x = x;
5566         intel_crtc->cursor_y = y;
5567
5568         intel_crtc_update_cursor(crtc, true);
5569
5570         return 0;
5571 }
5572
5573 /** Sets the color ramps on behalf of RandR */
5574 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5575                                  u16 blue, int regno)
5576 {
5577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5578
5579         intel_crtc->lut_r[regno] = red >> 8;
5580         intel_crtc->lut_g[regno] = green >> 8;
5581         intel_crtc->lut_b[regno] = blue >> 8;
5582 }
5583
5584 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5585                              u16 *blue, int regno)
5586 {
5587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588
5589         *red = intel_crtc->lut_r[regno] << 8;
5590         *green = intel_crtc->lut_g[regno] << 8;
5591         *blue = intel_crtc->lut_b[regno] << 8;
5592 }
5593
5594 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5595                                  u16 *blue, uint32_t start, uint32_t size)
5596 {
5597         int end = (start + size > 256) ? 256 : start + size, i;
5598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5599
5600         for (i = start; i < end; i++) {
5601                 intel_crtc->lut_r[i] = red[i] >> 8;
5602                 intel_crtc->lut_g[i] = green[i] >> 8;
5603                 intel_crtc->lut_b[i] = blue[i] >> 8;
5604         }
5605
5606         intel_crtc_load_lut(crtc);
5607 }
5608
5609 /**
5610  * Get a pipe with a simple mode set on it for doing load-based monitor
5611  * detection.
5612  *
5613  * It will be up to the load-detect code to adjust the pipe as appropriate for
5614  * its requirements.  The pipe will be connected to no other encoders.
5615  *
5616  * Currently this code will only succeed if there is a pipe with no encoders
5617  * configured for it.  In the future, it could choose to temporarily disable
5618  * some outputs to free up a pipe for its use.
5619  *
5620  * \return crtc, or NULL if no pipes are available.
5621  */
5622
5623 /* VESA 640x480x72Hz mode to set on the pipe */
5624 static struct drm_display_mode load_detect_mode = {
5625         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5626                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5627 };
5628
5629 static struct drm_framebuffer *
5630 intel_framebuffer_create(struct drm_device *dev,
5631                          struct drm_mode_fb_cmd2 *mode_cmd,
5632                          struct drm_i915_gem_object *obj)
5633 {
5634         struct intel_framebuffer *intel_fb;
5635         int ret;
5636
5637         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5638         if (!intel_fb) {
5639                 drm_gem_object_unreference_unlocked(&obj->base);
5640                 return ERR_PTR(-ENOMEM);
5641         }
5642
5643         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5644         if (ret) {
5645                 drm_gem_object_unreference_unlocked(&obj->base);
5646                 kfree(intel_fb);
5647                 return ERR_PTR(ret);
5648         }
5649
5650         return &intel_fb->base;
5651 }
5652
5653 static u32
5654 intel_framebuffer_pitch_for_width(int width, int bpp)
5655 {
5656         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5657         return ALIGN(pitch, 64);
5658 }
5659
5660 static u32
5661 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5662 {
5663         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5664         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5665 }
5666
5667 static struct drm_framebuffer *
5668 intel_framebuffer_create_for_mode(struct drm_device *dev,
5669                                   struct drm_display_mode *mode,
5670                                   int depth, int bpp)
5671 {
5672         struct drm_i915_gem_object *obj;
5673         struct drm_mode_fb_cmd2 mode_cmd;
5674
5675         obj = i915_gem_alloc_object(dev,
5676                                     intel_framebuffer_size_for_mode(mode, bpp));
5677         if (obj == NULL)
5678                 return ERR_PTR(-ENOMEM);
5679
5680         mode_cmd.width = mode->hdisplay;
5681         mode_cmd.height = mode->vdisplay;
5682         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5683                                                                 bpp);
5684         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5685
5686         return intel_framebuffer_create(dev, &mode_cmd, obj);
5687 }
5688
5689 static struct drm_framebuffer *
5690 mode_fits_in_fbdev(struct drm_device *dev,
5691                    struct drm_display_mode *mode)
5692 {
5693         struct drm_i915_private *dev_priv = dev->dev_private;
5694         struct drm_i915_gem_object *obj;
5695         struct drm_framebuffer *fb;
5696
5697         if (dev_priv->fbdev == NULL)
5698                 return NULL;
5699
5700         obj = dev_priv->fbdev->ifb.obj;
5701         if (obj == NULL)
5702                 return NULL;
5703
5704         fb = &dev_priv->fbdev->ifb.base;
5705         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5706                                                                fb->bits_per_pixel))
5707                 return NULL;
5708
5709         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5710                 return NULL;
5711
5712         return fb;
5713 }
5714
5715 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5716                                 struct drm_display_mode *mode,
5717                                 struct intel_load_detect_pipe *old)
5718 {
5719         struct intel_crtc *intel_crtc;
5720         struct intel_encoder *intel_encoder =
5721                 intel_attached_encoder(connector);
5722         struct drm_crtc *possible_crtc;
5723         struct drm_encoder *encoder = &intel_encoder->base;
5724         struct drm_crtc *crtc = NULL;
5725         struct drm_device *dev = encoder->dev;
5726         struct drm_framebuffer *fb;
5727         int i = -1;
5728
5729         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5730                       connector->base.id, drm_get_connector_name(connector),
5731                       encoder->base.id, drm_get_encoder_name(encoder));
5732
5733         /*
5734          * Algorithm gets a little messy:
5735          *
5736          *   - if the connector already has an assigned crtc, use it (but make
5737          *     sure it's on first)
5738          *
5739          *   - try to find the first unused crtc that can drive this connector,
5740          *     and use that if we find one
5741          */
5742
5743         /* See if we already have a CRTC for this connector */
5744         if (encoder->crtc) {
5745                 crtc = encoder->crtc;
5746
5747                 old->dpms_mode = connector->dpms;
5748                 old->load_detect_temp = false;
5749
5750                 /* Make sure the crtc and connector are running */
5751                 if (connector->dpms != DRM_MODE_DPMS_ON)
5752                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5753
5754                 return true;
5755         }
5756
5757         /* Find an unused one (if possible) */
5758         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5759                 i++;
5760                 if (!(encoder->possible_crtcs & (1 << i)))
5761                         continue;
5762                 if (!possible_crtc->enabled) {
5763                         crtc = possible_crtc;
5764                         break;
5765                 }
5766         }
5767
5768         /*
5769          * If we didn't find an unused CRTC, don't use any.
5770          */
5771         if (!crtc) {
5772                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5773                 return false;
5774         }
5775
5776         encoder->crtc = crtc;
5777         connector->encoder = encoder;
5778
5779         intel_crtc = to_intel_crtc(crtc);
5780         old->dpms_mode = connector->dpms;
5781         old->load_detect_temp = true;
5782         old->release_fb = NULL;
5783
5784         if (!mode)
5785                 mode = &load_detect_mode;
5786
5787         /* We need a framebuffer large enough to accommodate all accesses
5788          * that the plane may generate whilst we perform load detection.
5789          * We can not rely on the fbcon either being present (we get called
5790          * during its initialisation to detect all boot displays, or it may
5791          * not even exist) or that it is large enough to satisfy the
5792          * requested mode.
5793          */
5794         fb = mode_fits_in_fbdev(dev, mode);
5795         if (fb == NULL) {
5796                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5797                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5798                 old->release_fb = fb;
5799         } else
5800                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5801         if (IS_ERR(fb)) {
5802                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5803                 goto fail;
5804         }
5805
5806         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
5807                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5808                 if (old->release_fb)
5809                         old->release_fb->funcs->destroy(old->release_fb);
5810                 goto fail;
5811         }
5812
5813         /* let the connector get through one full cycle before testing */
5814         intel_wait_for_vblank(dev, intel_crtc->pipe);
5815
5816         return true;
5817 fail:
5818         connector->encoder = NULL;
5819         encoder->crtc = NULL;
5820         return false;
5821 }
5822
5823 void intel_release_load_detect_pipe(struct drm_connector *connector,
5824                                     struct intel_load_detect_pipe *old)
5825 {
5826         struct intel_encoder *intel_encoder =
5827                 intel_attached_encoder(connector);
5828         struct drm_encoder *encoder = &intel_encoder->base;
5829         struct drm_device *dev = encoder->dev;
5830
5831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5832                       connector->base.id, drm_get_connector_name(connector),
5833                       encoder->base.id, drm_get_encoder_name(encoder));
5834
5835         if (old->load_detect_temp) {
5836                 connector->encoder = NULL;
5837                 encoder->crtc = NULL;
5838                 drm_helper_disable_unused_functions(dev);
5839
5840                 if (old->release_fb)
5841                         old->release_fb->funcs->destroy(old->release_fb);
5842
5843                 return;
5844         }
5845
5846         /* Switch crtc and encoder back off if necessary */
5847         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5848                 connector->funcs->dpms(connector, old->dpms_mode);
5849 }
5850
5851 /* Returns the clock of the currently programmed mode of the given pipe. */
5852 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5853 {
5854         struct drm_i915_private *dev_priv = dev->dev_private;
5855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856         int pipe = intel_crtc->pipe;
5857         u32 dpll = I915_READ(DPLL(pipe));
5858         u32 fp;
5859         intel_clock_t clock;
5860
5861         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5862                 fp = I915_READ(FP0(pipe));
5863         else
5864                 fp = I915_READ(FP1(pipe));
5865
5866         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5867         if (IS_PINEVIEW(dev)) {
5868                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5869                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5870         } else {
5871                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5872                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5873         }
5874
5875         if (!IS_GEN2(dev)) {
5876                 if (IS_PINEVIEW(dev))
5877                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5878                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5879                 else
5880                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5881                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5882
5883                 switch (dpll & DPLL_MODE_MASK) {
5884                 case DPLLB_MODE_DAC_SERIAL:
5885                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5886                                 5 : 10;
5887                         break;
5888                 case DPLLB_MODE_LVDS:
5889                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5890                                 7 : 14;
5891                         break;
5892                 default:
5893                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5894                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5895                         return 0;
5896                 }
5897
5898                 /* XXX: Handle the 100Mhz refclk */
5899                 intel_clock(dev, 96000, &clock);
5900         } else {
5901                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5902
5903                 if (is_lvds) {
5904                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5905                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5906                         clock.p2 = 14;
5907
5908                         if ((dpll & PLL_REF_INPUT_MASK) ==
5909                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5910                                 /* XXX: might not be 66MHz */
5911                                 intel_clock(dev, 66000, &clock);
5912                         } else
5913                                 intel_clock(dev, 48000, &clock);
5914                 } else {
5915                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5916                                 clock.p1 = 2;
5917                         else {
5918                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5919                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5920                         }
5921                         if (dpll & PLL_P2_DIVIDE_BY_4)
5922                                 clock.p2 = 4;
5923                         else
5924                                 clock.p2 = 2;
5925
5926                         intel_clock(dev, 48000, &clock);
5927                 }
5928         }
5929
5930         /* XXX: It would be nice to validate the clocks, but we can't reuse
5931          * i830PllIsValid() because it relies on the xf86_config connector
5932          * configuration being accurate, which it isn't necessarily.
5933          */
5934
5935         return clock.dot;
5936 }
5937
5938 /** Returns the currently programmed mode of the given pipe. */
5939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5940                                              struct drm_crtc *crtc)
5941 {
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944         int pipe = intel_crtc->pipe;
5945         struct drm_display_mode *mode;
5946         int htot = I915_READ(HTOTAL(pipe));
5947         int hsync = I915_READ(HSYNC(pipe));
5948         int vtot = I915_READ(VTOTAL(pipe));
5949         int vsync = I915_READ(VSYNC(pipe));
5950
5951         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5952         if (!mode)
5953                 return NULL;
5954
5955         mode->clock = intel_crtc_clock_get(dev, crtc);
5956         mode->hdisplay = (htot & 0xffff) + 1;
5957         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5958         mode->hsync_start = (hsync & 0xffff) + 1;
5959         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5960         mode->vdisplay = (vtot & 0xffff) + 1;
5961         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5962         mode->vsync_start = (vsync & 0xffff) + 1;
5963         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5964
5965         drm_mode_set_name(mode);
5966
5967         return mode;
5968 }
5969
5970 static void intel_increase_pllclock(struct drm_crtc *crtc)
5971 {
5972         struct drm_device *dev = crtc->dev;
5973         drm_i915_private_t *dev_priv = dev->dev_private;
5974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5975         int pipe = intel_crtc->pipe;
5976         int dpll_reg = DPLL(pipe);
5977         int dpll;
5978
5979         if (HAS_PCH_SPLIT(dev))
5980                 return;
5981
5982         if (!dev_priv->lvds_downclock_avail)
5983                 return;
5984
5985         dpll = I915_READ(dpll_reg);
5986         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5987                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5988
5989                 assert_panel_unlocked(dev_priv, pipe);
5990
5991                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5992                 I915_WRITE(dpll_reg, dpll);
5993                 intel_wait_for_vblank(dev, pipe);
5994
5995                 dpll = I915_READ(dpll_reg);
5996                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5997                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5998         }
5999 }
6000
6001 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6002 {
6003         struct drm_device *dev = crtc->dev;
6004         drm_i915_private_t *dev_priv = dev->dev_private;
6005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6006
6007         if (HAS_PCH_SPLIT(dev))
6008                 return;
6009
6010         if (!dev_priv->lvds_downclock_avail)
6011                 return;
6012
6013         /*
6014          * Since this is called by a timer, we should never get here in
6015          * the manual case.
6016          */
6017         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6018                 int pipe = intel_crtc->pipe;
6019                 int dpll_reg = DPLL(pipe);
6020                 int dpll;
6021
6022                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6023
6024                 assert_panel_unlocked(dev_priv, pipe);
6025
6026                 dpll = I915_READ(dpll_reg);
6027                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6028                 I915_WRITE(dpll_reg, dpll);
6029                 intel_wait_for_vblank(dev, pipe);
6030                 dpll = I915_READ(dpll_reg);
6031                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6032                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6033         }
6034
6035 }
6036
6037 void intel_mark_busy(struct drm_device *dev)
6038 {
6039         i915_update_gfx_val(dev->dev_private);
6040 }
6041
6042 void intel_mark_idle(struct drm_device *dev)
6043 {
6044 }
6045
6046 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6047 {
6048         struct drm_device *dev = obj->base.dev;
6049         struct drm_crtc *crtc;
6050
6051         if (!i915_powersave)
6052                 return;
6053
6054         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6055                 if (!crtc->fb)
6056                         continue;
6057
6058                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6059                         intel_increase_pllclock(crtc);
6060         }
6061 }
6062
6063 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6064 {
6065         struct drm_device *dev = obj->base.dev;
6066         struct drm_crtc *crtc;
6067
6068         if (!i915_powersave)
6069                 return;
6070
6071         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6072                 if (!crtc->fb)
6073                         continue;
6074
6075                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6076                         intel_decrease_pllclock(crtc);
6077         }
6078 }
6079
6080 static void intel_crtc_destroy(struct drm_crtc *crtc)
6081 {
6082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083         struct drm_device *dev = crtc->dev;
6084         struct intel_unpin_work *work;
6085         unsigned long flags;
6086
6087         spin_lock_irqsave(&dev->event_lock, flags);
6088         work = intel_crtc->unpin_work;
6089         intel_crtc->unpin_work = NULL;
6090         spin_unlock_irqrestore(&dev->event_lock, flags);
6091
6092         if (work) {
6093                 cancel_work_sync(&work->work);
6094                 kfree(work);
6095         }
6096
6097         drm_crtc_cleanup(crtc);
6098
6099         kfree(intel_crtc);
6100 }
6101
6102 static void intel_unpin_work_fn(struct work_struct *__work)
6103 {
6104         struct intel_unpin_work *work =
6105                 container_of(__work, struct intel_unpin_work, work);
6106
6107         mutex_lock(&work->dev->struct_mutex);
6108         intel_unpin_fb_obj(work->old_fb_obj);
6109         drm_gem_object_unreference(&work->pending_flip_obj->base);
6110         drm_gem_object_unreference(&work->old_fb_obj->base);
6111
6112         intel_update_fbc(work->dev);
6113         mutex_unlock(&work->dev->struct_mutex);
6114         kfree(work);
6115 }
6116
6117 static void do_intel_finish_page_flip(struct drm_device *dev,
6118                                       struct drm_crtc *crtc)
6119 {
6120         drm_i915_private_t *dev_priv = dev->dev_private;
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122         struct intel_unpin_work *work;
6123         struct drm_i915_gem_object *obj;
6124         struct drm_pending_vblank_event *e;
6125         struct timeval tnow, tvbl;
6126         unsigned long flags;
6127
6128         /* Ignore early vblank irqs */
6129         if (intel_crtc == NULL)
6130                 return;
6131
6132         do_gettimeofday(&tnow);
6133
6134         spin_lock_irqsave(&dev->event_lock, flags);
6135         work = intel_crtc->unpin_work;
6136         if (work == NULL || !work->pending) {
6137                 spin_unlock_irqrestore(&dev->event_lock, flags);
6138                 return;
6139         }
6140
6141         intel_crtc->unpin_work = NULL;
6142
6143         if (work->event) {
6144                 e = work->event;
6145                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6146
6147                 /* Called before vblank count and timestamps have
6148                  * been updated for the vblank interval of flip
6149                  * completion? Need to increment vblank count and
6150                  * add one videorefresh duration to returned timestamp
6151                  * to account for this. We assume this happened if we
6152                  * get called over 0.9 frame durations after the last
6153                  * timestamped vblank.
6154                  *
6155                  * This calculation can not be used with vrefresh rates
6156                  * below 5Hz (10Hz to be on the safe side) without
6157                  * promoting to 64 integers.
6158                  */
6159                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6160                     9 * crtc->framedur_ns) {
6161                         e->event.sequence++;
6162                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6163                                              crtc->framedur_ns);
6164                 }
6165
6166                 e->event.tv_sec = tvbl.tv_sec;
6167                 e->event.tv_usec = tvbl.tv_usec;
6168
6169                 list_add_tail(&e->base.link,
6170                               &e->base.file_priv->event_list);
6171                 wake_up_interruptible(&e->base.file_priv->event_wait);
6172         }
6173
6174         drm_vblank_put(dev, intel_crtc->pipe);
6175
6176         spin_unlock_irqrestore(&dev->event_lock, flags);
6177
6178         obj = work->old_fb_obj;
6179
6180         atomic_clear_mask(1 << intel_crtc->plane,
6181                           &obj->pending_flip.counter);
6182         if (atomic_read(&obj->pending_flip) == 0)
6183                 wake_up(&dev_priv->pending_flip_queue);
6184
6185         schedule_work(&work->work);
6186
6187         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6188 }
6189
6190 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6191 {
6192         drm_i915_private_t *dev_priv = dev->dev_private;
6193         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6194
6195         do_intel_finish_page_flip(dev, crtc);
6196 }
6197
6198 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6199 {
6200         drm_i915_private_t *dev_priv = dev->dev_private;
6201         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6202
6203         do_intel_finish_page_flip(dev, crtc);
6204 }
6205
6206 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6207 {
6208         drm_i915_private_t *dev_priv = dev->dev_private;
6209         struct intel_crtc *intel_crtc =
6210                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6211         unsigned long flags;
6212
6213         spin_lock_irqsave(&dev->event_lock, flags);
6214         if (intel_crtc->unpin_work) {
6215                 if ((++intel_crtc->unpin_work->pending) > 1)
6216                         DRM_ERROR("Prepared flip multiple times\n");
6217         } else {
6218                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6219         }
6220         spin_unlock_irqrestore(&dev->event_lock, flags);
6221 }
6222
6223 static int intel_gen2_queue_flip(struct drm_device *dev,
6224                                  struct drm_crtc *crtc,
6225                                  struct drm_framebuffer *fb,
6226                                  struct drm_i915_gem_object *obj)
6227 {
6228         struct drm_i915_private *dev_priv = dev->dev_private;
6229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230         u32 flip_mask;
6231         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6232         int ret;
6233
6234         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6235         if (ret)
6236                 goto err;
6237
6238         ret = intel_ring_begin(ring, 6);
6239         if (ret)
6240                 goto err_unpin;
6241
6242         /* Can't queue multiple flips, so wait for the previous
6243          * one to finish before executing the next.
6244          */
6245         if (intel_crtc->plane)
6246                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6247         else
6248                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6249         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250         intel_ring_emit(ring, MI_NOOP);
6251         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6252                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253         intel_ring_emit(ring, fb->pitches[0]);
6254         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6255         intel_ring_emit(ring, 0); /* aux display base address, unused */
6256         intel_ring_advance(ring);
6257         return 0;
6258
6259 err_unpin:
6260         intel_unpin_fb_obj(obj);
6261 err:
6262         return ret;
6263 }
6264
6265 static int intel_gen3_queue_flip(struct drm_device *dev,
6266                                  struct drm_crtc *crtc,
6267                                  struct drm_framebuffer *fb,
6268                                  struct drm_i915_gem_object *obj)
6269 {
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272         u32 flip_mask;
6273         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6274         int ret;
6275
6276         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6277         if (ret)
6278                 goto err;
6279
6280         ret = intel_ring_begin(ring, 6);
6281         if (ret)
6282                 goto err_unpin;
6283
6284         if (intel_crtc->plane)
6285                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6286         else
6287                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6288         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6289         intel_ring_emit(ring, MI_NOOP);
6290         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6291                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292         intel_ring_emit(ring, fb->pitches[0]);
6293         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6294         intel_ring_emit(ring, MI_NOOP);
6295
6296         intel_ring_advance(ring);
6297         return 0;
6298
6299 err_unpin:
6300         intel_unpin_fb_obj(obj);
6301 err:
6302         return ret;
6303 }
6304
6305 static int intel_gen4_queue_flip(struct drm_device *dev,
6306                                  struct drm_crtc *crtc,
6307                                  struct drm_framebuffer *fb,
6308                                  struct drm_i915_gem_object *obj)
6309 {
6310         struct drm_i915_private *dev_priv = dev->dev_private;
6311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312         uint32_t pf, pipesrc;
6313         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6314         int ret;
6315
6316         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6317         if (ret)
6318                 goto err;
6319
6320         ret = intel_ring_begin(ring, 4);
6321         if (ret)
6322                 goto err_unpin;
6323
6324         /* i965+ uses the linear or tiled offsets from the
6325          * Display Registers (which do not change across a page-flip)
6326          * so we need only reprogram the base address.
6327          */
6328         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6329                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6330         intel_ring_emit(ring, fb->pitches[0]);
6331         intel_ring_emit(ring,
6332                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6333                         obj->tiling_mode);
6334
6335         /* XXX Enabling the panel-fitter across page-flip is so far
6336          * untested on non-native modes, so ignore it for now.
6337          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6338          */
6339         pf = 0;
6340         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6341         intel_ring_emit(ring, pf | pipesrc);
6342         intel_ring_advance(ring);
6343         return 0;
6344
6345 err_unpin:
6346         intel_unpin_fb_obj(obj);
6347 err:
6348         return ret;
6349 }
6350
6351 static int intel_gen6_queue_flip(struct drm_device *dev,
6352                                  struct drm_crtc *crtc,
6353                                  struct drm_framebuffer *fb,
6354                                  struct drm_i915_gem_object *obj)
6355 {
6356         struct drm_i915_private *dev_priv = dev->dev_private;
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6359         uint32_t pf, pipesrc;
6360         int ret;
6361
6362         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6363         if (ret)
6364                 goto err;
6365
6366         ret = intel_ring_begin(ring, 4);
6367         if (ret)
6368                 goto err_unpin;
6369
6370         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6371                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6372         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6373         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6374
6375         /* Contrary to the suggestions in the documentation,
6376          * "Enable Panel Fitter" does not seem to be required when page
6377          * flipping with a non-native mode, and worse causes a normal
6378          * modeset to fail.
6379          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6380          */
6381         pf = 0;
6382         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6383         intel_ring_emit(ring, pf | pipesrc);
6384         intel_ring_advance(ring);
6385         return 0;
6386
6387 err_unpin:
6388         intel_unpin_fb_obj(obj);
6389 err:
6390         return ret;
6391 }
6392
6393 /*
6394  * On gen7 we currently use the blit ring because (in early silicon at least)
6395  * the render ring doesn't give us interrpts for page flip completion, which
6396  * means clients will hang after the first flip is queued.  Fortunately the
6397  * blit ring generates interrupts properly, so use it instead.
6398  */
6399 static int intel_gen7_queue_flip(struct drm_device *dev,
6400                                  struct drm_crtc *crtc,
6401                                  struct drm_framebuffer *fb,
6402                                  struct drm_i915_gem_object *obj)
6403 {
6404         struct drm_i915_private *dev_priv = dev->dev_private;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6407         uint32_t plane_bit = 0;
6408         int ret;
6409
6410         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6411         if (ret)
6412                 goto err;
6413
6414         switch(intel_crtc->plane) {
6415         case PLANE_A:
6416                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6417                 break;
6418         case PLANE_B:
6419                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6420                 break;
6421         case PLANE_C:
6422                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6423                 break;
6424         default:
6425                 WARN_ONCE(1, "unknown plane in flip command\n");
6426                 ret = -ENODEV;
6427                 goto err_unpin;
6428         }
6429
6430         ret = intel_ring_begin(ring, 4);
6431         if (ret)
6432                 goto err_unpin;
6433
6434         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6435         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6436         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6437         intel_ring_emit(ring, (MI_NOOP));
6438         intel_ring_advance(ring);
6439         return 0;
6440
6441 err_unpin:
6442         intel_unpin_fb_obj(obj);
6443 err:
6444         return ret;
6445 }
6446
6447 static int intel_default_queue_flip(struct drm_device *dev,
6448                                     struct drm_crtc *crtc,
6449                                     struct drm_framebuffer *fb,
6450                                     struct drm_i915_gem_object *obj)
6451 {
6452         return -ENODEV;
6453 }
6454
6455 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6456                                 struct drm_framebuffer *fb,
6457                                 struct drm_pending_vblank_event *event)
6458 {
6459         struct drm_device *dev = crtc->dev;
6460         struct drm_i915_private *dev_priv = dev->dev_private;
6461         struct intel_framebuffer *intel_fb;
6462         struct drm_i915_gem_object *obj;
6463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464         struct intel_unpin_work *work;
6465         unsigned long flags;
6466         int ret;
6467
6468         /* Can't change pixel format via MI display flips. */
6469         if (fb->pixel_format != crtc->fb->pixel_format)
6470                 return -EINVAL;
6471
6472         /*
6473          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6474          * Note that pitch changes could also affect these register.
6475          */
6476         if (INTEL_INFO(dev)->gen > 3 &&
6477             (fb->offsets[0] != crtc->fb->offsets[0] ||
6478              fb->pitches[0] != crtc->fb->pitches[0]))
6479                 return -EINVAL;
6480
6481         work = kzalloc(sizeof *work, GFP_KERNEL);
6482         if (work == NULL)
6483                 return -ENOMEM;
6484
6485         work->event = event;
6486         work->dev = crtc->dev;
6487         intel_fb = to_intel_framebuffer(crtc->fb);
6488         work->old_fb_obj = intel_fb->obj;
6489         INIT_WORK(&work->work, intel_unpin_work_fn);
6490
6491         ret = drm_vblank_get(dev, intel_crtc->pipe);
6492         if (ret)
6493                 goto free_work;
6494
6495         /* We borrow the event spin lock for protecting unpin_work */
6496         spin_lock_irqsave(&dev->event_lock, flags);
6497         if (intel_crtc->unpin_work) {
6498                 spin_unlock_irqrestore(&dev->event_lock, flags);
6499                 kfree(work);
6500                 drm_vblank_put(dev, intel_crtc->pipe);
6501
6502                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6503                 return -EBUSY;
6504         }
6505         intel_crtc->unpin_work = work;
6506         spin_unlock_irqrestore(&dev->event_lock, flags);
6507
6508         intel_fb = to_intel_framebuffer(fb);
6509         obj = intel_fb->obj;
6510
6511         ret = i915_mutex_lock_interruptible(dev);
6512         if (ret)
6513                 goto cleanup;
6514
6515         /* Reference the objects for the scheduled work. */
6516         drm_gem_object_reference(&work->old_fb_obj->base);
6517         drm_gem_object_reference(&obj->base);
6518
6519         crtc->fb = fb;
6520
6521         work->pending_flip_obj = obj;
6522
6523         work->enable_stall_check = true;
6524
6525         /* Block clients from rendering to the new back buffer until
6526          * the flip occurs and the object is no longer visible.
6527          */
6528         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6529
6530         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6531         if (ret)
6532                 goto cleanup_pending;
6533
6534         intel_disable_fbc(dev);
6535         intel_mark_fb_busy(obj);
6536         mutex_unlock(&dev->struct_mutex);
6537
6538         trace_i915_flip_request(intel_crtc->plane, obj);
6539
6540         return 0;
6541
6542 cleanup_pending:
6543         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6544         drm_gem_object_unreference(&work->old_fb_obj->base);
6545         drm_gem_object_unreference(&obj->base);
6546         mutex_unlock(&dev->struct_mutex);
6547
6548 cleanup:
6549         spin_lock_irqsave(&dev->event_lock, flags);
6550         intel_crtc->unpin_work = NULL;
6551         spin_unlock_irqrestore(&dev->event_lock, flags);
6552
6553         drm_vblank_put(dev, intel_crtc->pipe);
6554 free_work:
6555         kfree(work);
6556
6557         return ret;
6558 }
6559
6560 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6561         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6562         .load_lut = intel_crtc_load_lut,
6563         .disable = intel_crtc_disable,
6564 };
6565
6566 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6567 {
6568         struct intel_encoder *other_encoder;
6569         struct drm_crtc *crtc = &encoder->new_crtc->base;
6570
6571         if (WARN_ON(!crtc))
6572                 return false;
6573
6574         list_for_each_entry(other_encoder,
6575                             &crtc->dev->mode_config.encoder_list,
6576                             base.head) {
6577
6578                 if (&other_encoder->new_crtc->base != crtc ||
6579                     encoder == other_encoder)
6580                         continue;
6581                 else
6582                         return true;
6583         }
6584
6585         return false;
6586 }
6587
6588 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6589                                   struct drm_crtc *crtc)
6590 {
6591         struct drm_device *dev;
6592         struct drm_crtc *tmp;
6593         int crtc_mask = 1;
6594
6595         WARN(!crtc, "checking null crtc?\n");
6596
6597         dev = crtc->dev;
6598
6599         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6600                 if (tmp == crtc)
6601                         break;
6602                 crtc_mask <<= 1;
6603         }
6604
6605         if (encoder->possible_crtcs & crtc_mask)
6606                 return true;
6607         return false;
6608 }
6609
6610 static void
6611 intel_crtc_prepare_encoders(struct drm_device *dev)
6612 {
6613         struct intel_encoder *encoder;
6614
6615         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6616                 /* Disable unused encoders */
6617                 if (encoder->base.crtc == NULL)
6618                         encoder->disable(encoder);
6619         }
6620 }
6621
6622 /**
6623  * intel_modeset_update_staged_output_state
6624  *
6625  * Updates the staged output configuration state, e.g. after we've read out the
6626  * current hw state.
6627  */
6628 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6629 {
6630         struct intel_encoder *encoder;
6631         struct intel_connector *connector;
6632
6633         list_for_each_entry(connector, &dev->mode_config.connector_list,
6634                             base.head) {
6635                 connector->new_encoder =
6636                         to_intel_encoder(connector->base.encoder);
6637         }
6638
6639         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6640                             base.head) {
6641                 encoder->new_crtc =
6642                         to_intel_crtc(encoder->base.crtc);
6643         }
6644 }
6645
6646 /**
6647  * intel_modeset_commit_output_state
6648  *
6649  * This function copies the stage display pipe configuration to the real one.
6650  */
6651 static void intel_modeset_commit_output_state(struct drm_device *dev)
6652 {
6653         struct intel_encoder *encoder;
6654         struct intel_connector *connector;
6655
6656         list_for_each_entry(connector, &dev->mode_config.connector_list,
6657                             base.head) {
6658                 connector->base.encoder = &connector->new_encoder->base;
6659         }
6660
6661         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6662                             base.head) {
6663                 encoder->base.crtc = &encoder->new_crtc->base;
6664         }
6665 }
6666
6667 static struct drm_display_mode *
6668 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6669                             struct drm_display_mode *mode)
6670 {
6671         struct drm_device *dev = crtc->dev;
6672         struct drm_display_mode *adjusted_mode;
6673         struct drm_encoder_helper_funcs *encoder_funcs;
6674         struct intel_encoder *encoder;
6675
6676         adjusted_mode = drm_mode_duplicate(dev, mode);
6677         if (!adjusted_mode)
6678                 return ERR_PTR(-ENOMEM);
6679
6680         /* Pass our mode to the connectors and the CRTC to give them a chance to
6681          * adjust it according to limitations or connector properties, and also
6682          * a chance to reject the mode entirely.
6683          */
6684         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6685                             base.head) {
6686
6687                 if (&encoder->new_crtc->base != crtc)
6688                         continue;
6689                 encoder_funcs = encoder->base.helper_private;
6690                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6691                                                 adjusted_mode))) {
6692                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6693                         goto fail;
6694                 }
6695         }
6696
6697         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6698                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6699                 goto fail;
6700         }
6701         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6702
6703         return adjusted_mode;
6704 fail:
6705         drm_mode_destroy(dev, adjusted_mode);
6706         return ERR_PTR(-EINVAL);
6707 }
6708
6709 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
6710  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
6711 static void
6712 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
6713                              unsigned *prepare_pipes, unsigned *disable_pipes)
6714 {
6715         struct intel_crtc *intel_crtc;
6716         struct drm_device *dev = crtc->dev;
6717         struct intel_encoder *encoder;
6718         struct intel_connector *connector;
6719         struct drm_crtc *tmp_crtc;
6720
6721         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
6722
6723         /* Check which crtcs have changed outputs connected to them, these need
6724          * to be part of the prepare_pipes mask. We don't (yet) support global
6725          * modeset across multiple crtcs, so modeset_pipes will only have one
6726          * bit set at most. */
6727         list_for_each_entry(connector, &dev->mode_config.connector_list,
6728                             base.head) {
6729                 if (connector->base.encoder == &connector->new_encoder->base)
6730                         continue;
6731
6732                 if (connector->base.encoder) {
6733                         tmp_crtc = connector->base.encoder->crtc;
6734
6735                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6736                 }
6737
6738                 if (connector->new_encoder)
6739                         *prepare_pipes |=
6740                                 1 << connector->new_encoder->new_crtc->pipe;
6741         }
6742
6743         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6744                             base.head) {
6745                 if (encoder->base.crtc == &encoder->new_crtc->base)
6746                         continue;
6747
6748                 if (encoder->base.crtc) {
6749                         tmp_crtc = encoder->base.crtc;
6750
6751                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
6752                 }
6753
6754                 if (encoder->new_crtc)
6755                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
6756         }
6757
6758         /* Check for any pipes that will be fully disabled ... */
6759         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
6760                             base.head) {
6761                 bool used = false;
6762
6763                 /* Don't try to disable disabled crtcs. */
6764                 if (!intel_crtc->base.enabled)
6765                         continue;
6766
6767                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6768                                     base.head) {
6769                         if (encoder->new_crtc == intel_crtc)
6770                                 used = true;
6771                 }
6772
6773                 if (!used)
6774                         *disable_pipes |= 1 << intel_crtc->pipe;
6775         }
6776
6777
6778         /* set_mode is also used to update properties on life display pipes. */
6779         intel_crtc = to_intel_crtc(crtc);
6780         if (crtc->enabled)
6781                 *prepare_pipes |= 1 << intel_crtc->pipe;
6782
6783         /* We only support modeset on one single crtc, hence we need to do that
6784          * only for the passed in crtc iff we change anything else than just
6785          * disable crtcs.
6786          *
6787          * This is actually not true, to be fully compatible with the old crtc
6788          * helper we automatically disable _any_ output (i.e. doesn't need to be
6789          * connected to the crtc we're modesetting on) if it's disconnected.
6790          * Which is a rather nutty api (since changed the output configuration
6791          * without userspace's explicit request can lead to confusion), but
6792          * alas. Hence we currently need to modeset on all pipes we prepare. */
6793         if (*prepare_pipes)
6794                 *modeset_pipes = *prepare_pipes;
6795
6796         /* ... and mask these out. */
6797         *modeset_pipes &= ~(*disable_pipes);
6798         *prepare_pipes &= ~(*disable_pipes);
6799 }
6800
6801 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
6802         list_for_each_entry((intel_crtc), \
6803                             &(dev)->mode_config.crtc_list, \
6804                             base.head) \
6805                 if (mask & (1 <<(intel_crtc)->pipe)) \
6806
6807 bool intel_set_mode(struct drm_crtc *crtc,
6808                     struct drm_display_mode *mode,
6809                     int x, int y, struct drm_framebuffer *fb)
6810 {
6811         struct drm_device *dev = crtc->dev;
6812         drm_i915_private_t *dev_priv = dev->dev_private;
6813         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6814         struct drm_encoder_helper_funcs *encoder_funcs;
6815         struct drm_encoder *encoder;
6816         struct intel_crtc *intel_crtc;
6817         unsigned disable_pipes, prepare_pipes, modeset_pipes;
6818         bool ret = true;
6819
6820         intel_modeset_affected_pipes(crtc, &modeset_pipes,
6821                                      &prepare_pipes, &disable_pipes);
6822
6823         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
6824                       modeset_pipes, prepare_pipes, disable_pipes);
6825
6826         intel_modeset_commit_output_state(dev);
6827
6828         crtc->enabled = drm_helper_crtc_in_use(crtc);
6829
6830         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
6831                 drm_helper_disable_unused_functions(dev);
6832
6833         saved_hwmode = crtc->hwmode;
6834         saved_mode = crtc->mode;
6835
6836         /* Hack: Because we don't (yet) support global modeset on multiple
6837          * crtcs, we don't keep track of the new mode for more than one crtc.
6838          * Hence simply check whether any bit is set in modeset_pipes in all the
6839          * pieces of code that are not yet converted to deal with mutliple crtcs
6840          * changing their mode at the same time. */
6841         adjusted_mode = NULL;
6842         if (modeset_pipes) {
6843                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
6844                 if (IS_ERR(adjusted_mode)) {
6845                         return false;
6846                 }
6847
6848                 intel_crtc_prepare_encoders(dev);
6849         }
6850
6851         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
6852                 dev_priv->display.crtc_disable(&intel_crtc->base);
6853
6854         if (modeset_pipes) {
6855                 crtc->mode = *mode;
6856                 crtc->x = x;
6857                 crtc->y = y;
6858         }
6859
6860         /* Set up the DPLL and any encoders state that needs to adjust or depend
6861          * on the DPLL.
6862          */
6863         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
6864                 ret = !intel_crtc_mode_set(&intel_crtc->base,
6865                                            mode, adjusted_mode,
6866                                            x, y, fb);
6867                 if (!ret)
6868                     goto done;
6869
6870                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6871
6872                         if (encoder->crtc != &intel_crtc->base)
6873                                 continue;
6874
6875                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6876                                 encoder->base.id, drm_get_encoder_name(encoder),
6877                                 mode->base.id, mode->name);
6878                         encoder_funcs = encoder->helper_private;
6879                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6880                 }
6881         }
6882
6883         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6884         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
6885                 dev_priv->display.crtc_enable(&intel_crtc->base);
6886
6887         if (modeset_pipes) {
6888                 /* Store real post-adjustment hardware mode. */
6889                 crtc->hwmode = *adjusted_mode;
6890
6891                 /* Calculate and store various constants which
6892                  * are later needed by vblank and swap-completion
6893                  * timestamping. They are derived from true hwmode.
6894                  */
6895                 drm_calc_timestamping_constants(crtc);
6896         }
6897
6898         /* FIXME: add subpixel order */
6899 done:
6900         drm_mode_destroy(dev, adjusted_mode);
6901         if (!ret && crtc->enabled) {
6902                 crtc->hwmode = saved_hwmode;
6903                 crtc->mode = saved_mode;
6904         }
6905
6906         return ret;
6907 }
6908
6909 #undef for_each_intel_crtc_masked
6910
6911 static void intel_set_config_free(struct intel_set_config *config)
6912 {
6913         if (!config)
6914                 return;
6915
6916         kfree(config->save_connector_encoders);
6917         kfree(config->save_encoder_crtcs);
6918         kfree(config);
6919 }
6920
6921 static int intel_set_config_save_state(struct drm_device *dev,
6922                                        struct intel_set_config *config)
6923 {
6924         struct drm_encoder *encoder;
6925         struct drm_connector *connector;
6926         int count;
6927
6928         config->save_encoder_crtcs =
6929                 kcalloc(dev->mode_config.num_encoder,
6930                         sizeof(struct drm_crtc *), GFP_KERNEL);
6931         if (!config->save_encoder_crtcs)
6932                 return -ENOMEM;
6933
6934         config->save_connector_encoders =
6935                 kcalloc(dev->mode_config.num_connector,
6936                         sizeof(struct drm_encoder *), GFP_KERNEL);
6937         if (!config->save_connector_encoders)
6938                 return -ENOMEM;
6939
6940         /* Copy data. Note that driver private data is not affected.
6941          * Should anything bad happen only the expected state is
6942          * restored, not the drivers personal bookkeeping.
6943          */
6944         count = 0;
6945         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6946                 config->save_encoder_crtcs[count++] = encoder->crtc;
6947         }
6948
6949         count = 0;
6950         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6951                 config->save_connector_encoders[count++] = connector->encoder;
6952         }
6953
6954         return 0;
6955 }
6956
6957 static void intel_set_config_restore_state(struct drm_device *dev,
6958                                            struct intel_set_config *config)
6959 {
6960         struct intel_encoder *encoder;
6961         struct intel_connector *connector;
6962         int count;
6963
6964         count = 0;
6965         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6966                 encoder->new_crtc =
6967                         to_intel_crtc(config->save_encoder_crtcs[count++]);
6968         }
6969
6970         count = 0;
6971         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
6972                 connector->new_encoder =
6973                         to_intel_encoder(config->save_connector_encoders[count++]);
6974         }
6975 }
6976
6977 static void
6978 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
6979                                       struct intel_set_config *config)
6980 {
6981
6982         /* We should be able to check here if the fb has the same properties
6983          * and then just flip_or_move it */
6984         if (set->crtc->fb != set->fb) {
6985                 /* If we have no fb then treat it as a full mode set */
6986                 if (set->crtc->fb == NULL) {
6987                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6988                         config->mode_changed = true;
6989                 } else if (set->fb == NULL) {
6990                         config->mode_changed = true;
6991                 } else if (set->fb->depth != set->crtc->fb->depth) {
6992                         config->mode_changed = true;
6993                 } else if (set->fb->bits_per_pixel !=
6994                            set->crtc->fb->bits_per_pixel) {
6995                         config->mode_changed = true;
6996                 } else
6997                         config->fb_changed = true;
6998         }
6999
7000         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7001                 config->fb_changed = true;
7002
7003         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7004                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7005                 drm_mode_debug_printmodeline(&set->crtc->mode);
7006                 drm_mode_debug_printmodeline(set->mode);
7007                 config->mode_changed = true;
7008         }
7009 }
7010
7011 static int
7012 intel_modeset_stage_output_state(struct drm_device *dev,
7013                                  struct drm_mode_set *set,
7014                                  struct intel_set_config *config)
7015 {
7016         struct drm_crtc *new_crtc;
7017         struct intel_connector *connector;
7018         struct intel_encoder *encoder;
7019         int count, ro;
7020
7021         /* The upper layers ensure that we either disabl a crtc or have a list
7022          * of connectors. For paranoia, double-check this. */
7023         WARN_ON(!set->fb && (set->num_connectors != 0));
7024         WARN_ON(set->fb && (set->num_connectors == 0));
7025
7026         count = 0;
7027         list_for_each_entry(connector, &dev->mode_config.connector_list,
7028                             base.head) {
7029                 /* Otherwise traverse passed in connector list and get encoders
7030                  * for them. */
7031                 for (ro = 0; ro < set->num_connectors; ro++) {
7032                         if (set->connectors[ro] == &connector->base) {
7033                                 connector->new_encoder = connector->encoder;
7034                                 break;
7035                         }
7036                 }
7037
7038                 /* If we disable the crtc, disable all its connectors. Also, if
7039                  * the connector is on the changing crtc but not on the new
7040                  * connector list, disable it. */
7041                 if ((!set->fb || ro == set->num_connectors) &&
7042                     connector->base.encoder &&
7043                     connector->base.encoder->crtc == set->crtc) {
7044                         connector->new_encoder = NULL;
7045
7046                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7047                                 connector->base.base.id,
7048                                 drm_get_connector_name(&connector->base));
7049                 }
7050
7051
7052                 if (&connector->new_encoder->base != connector->base.encoder) {
7053                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7054                         config->mode_changed = true;
7055                 }
7056
7057                 /* Disable all disconnected encoders. */
7058                 if (connector->base.status == connector_status_disconnected)
7059                         connector->new_encoder = NULL;
7060         }
7061         /* connector->new_encoder is now updated for all connectors. */
7062
7063         /* Update crtc of enabled connectors. */
7064         count = 0;
7065         list_for_each_entry(connector, &dev->mode_config.connector_list,
7066                             base.head) {
7067                 if (!connector->new_encoder)
7068                         continue;
7069
7070                 new_crtc = connector->new_encoder->base.crtc;
7071
7072                 for (ro = 0; ro < set->num_connectors; ro++) {
7073                         if (set->connectors[ro] == &connector->base)
7074                                 new_crtc = set->crtc;
7075                 }
7076
7077                 /* Make sure the new CRTC will work with the encoder */
7078                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7079                                            new_crtc)) {
7080                         return -EINVAL;
7081                 }
7082                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7083
7084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7085                         connector->base.base.id,
7086                         drm_get_connector_name(&connector->base),
7087                         new_crtc->base.id);
7088         }
7089
7090         /* Check for any encoders that needs to be disabled. */
7091         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7092                             base.head) {
7093                 list_for_each_entry(connector,
7094                                     &dev->mode_config.connector_list,
7095                                     base.head) {
7096                         if (connector->new_encoder == encoder) {
7097                                 WARN_ON(!connector->new_encoder->new_crtc);
7098
7099                                 goto next_encoder;
7100                         }
7101                 }
7102                 encoder->new_crtc = NULL;
7103 next_encoder:
7104                 /* Only now check for crtc changes so we don't miss encoders
7105                  * that will be disabled. */
7106                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7107                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7108                         config->mode_changed = true;
7109                 }
7110         }
7111         /* Now we've also updated encoder->new_crtc for all encoders. */
7112
7113         return 0;
7114 }
7115
7116 static int intel_crtc_set_config(struct drm_mode_set *set)
7117 {
7118         struct drm_device *dev;
7119         struct drm_mode_set save_set;
7120         struct intel_set_config *config;
7121         int ret;
7122         int i;
7123
7124         BUG_ON(!set);
7125         BUG_ON(!set->crtc);
7126         BUG_ON(!set->crtc->helper_private);
7127
7128         if (!set->mode)
7129                 set->fb = NULL;
7130
7131         /* The fb helper likes to play gross jokes with ->mode_set_config.
7132          * Unfortunately the crtc helper doesn't do much at all for this case,
7133          * so we have to cope with this madness until the fb helper is fixed up. */
7134         if (set->fb && set->num_connectors == 0)
7135                 return 0;
7136
7137         if (set->fb) {
7138                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7139                                 set->crtc->base.id, set->fb->base.id,
7140                                 (int)set->num_connectors, set->x, set->y);
7141         } else {
7142                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7143         }
7144
7145         dev = set->crtc->dev;
7146
7147         ret = -ENOMEM;
7148         config = kzalloc(sizeof(*config), GFP_KERNEL);
7149         if (!config)
7150                 goto out_config;
7151
7152         ret = intel_set_config_save_state(dev, config);
7153         if (ret)
7154                 goto out_config;
7155
7156         save_set.crtc = set->crtc;
7157         save_set.mode = &set->crtc->mode;
7158         save_set.x = set->crtc->x;
7159         save_set.y = set->crtc->y;
7160         save_set.fb = set->crtc->fb;
7161
7162         /* Compute whether we need a full modeset, only an fb base update or no
7163          * change at all. In the future we might also check whether only the
7164          * mode changed, e.g. for LVDS where we only change the panel fitter in
7165          * such cases. */
7166         intel_set_config_compute_mode_changes(set, config);
7167
7168         ret = intel_modeset_stage_output_state(dev, set, config);
7169         if (ret)
7170                 goto fail;
7171
7172         if (config->mode_changed) {
7173                 if (set->mode) {
7174                         DRM_DEBUG_KMS("attempting to set mode from"
7175                                         " userspace\n");
7176                         drm_mode_debug_printmodeline(set->mode);
7177                 }
7178
7179                 if (!intel_set_mode(set->crtc, set->mode,
7180                                     set->x, set->y, set->fb)) {
7181                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7182                                   set->crtc->base.id);
7183                         ret = -EINVAL;
7184                         goto fail;
7185                 }
7186
7187                 if (set->crtc->enabled) {
7188                         DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7189                         for (i = 0; i < set->num_connectors; i++) {
7190                                 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7191                                               drm_get_connector_name(set->connectors[i]));
7192                                 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7193                         }
7194                 }
7195         } else if (config->fb_changed) {
7196                 ret = intel_pipe_set_base(set->crtc,
7197                                           set->x, set->y, set->fb);
7198         }
7199
7200         intel_set_config_free(config);
7201
7202         return 0;
7203
7204 fail:
7205         intel_set_config_restore_state(dev, config);
7206
7207         /* Try to restore the config */
7208         if (config->mode_changed &&
7209             !intel_set_mode(save_set.crtc, save_set.mode,
7210                             save_set.x, save_set.y, save_set.fb))
7211                 DRM_ERROR("failed to restore config after modeset failure\n");
7212
7213 out_config:
7214         intel_set_config_free(config);
7215         return ret;
7216 }
7217
7218 static const struct drm_crtc_funcs intel_crtc_funcs = {
7219         .cursor_set = intel_crtc_cursor_set,
7220         .cursor_move = intel_crtc_cursor_move,
7221         .gamma_set = intel_crtc_gamma_set,
7222         .set_config = intel_crtc_set_config,
7223         .destroy = intel_crtc_destroy,
7224         .page_flip = intel_crtc_page_flip,
7225 };
7226
7227 static void intel_pch_pll_init(struct drm_device *dev)
7228 {
7229         drm_i915_private_t *dev_priv = dev->dev_private;
7230         int i;
7231
7232         if (dev_priv->num_pch_pll == 0) {
7233                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7234                 return;
7235         }
7236
7237         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7238                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7239                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7240                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7241         }
7242 }
7243
7244 static void intel_crtc_init(struct drm_device *dev, int pipe)
7245 {
7246         drm_i915_private_t *dev_priv = dev->dev_private;
7247         struct intel_crtc *intel_crtc;
7248         int i;
7249
7250         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7251         if (intel_crtc == NULL)
7252                 return;
7253
7254         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7255
7256         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7257         for (i = 0; i < 256; i++) {
7258                 intel_crtc->lut_r[i] = i;
7259                 intel_crtc->lut_g[i] = i;
7260                 intel_crtc->lut_b[i] = i;
7261         }
7262
7263         /* Swap pipes & planes for FBC on pre-965 */
7264         intel_crtc->pipe = pipe;
7265         intel_crtc->plane = pipe;
7266         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7267                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7268                 intel_crtc->plane = !pipe;
7269         }
7270
7271         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7272                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7273         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7274         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7275
7276         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7277
7278         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7279 }
7280
7281 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7282                                 struct drm_file *file)
7283 {
7284         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7285         struct drm_mode_object *drmmode_obj;
7286         struct intel_crtc *crtc;
7287
7288         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7289                 return -ENODEV;
7290
7291         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7292                         DRM_MODE_OBJECT_CRTC);
7293
7294         if (!drmmode_obj) {
7295                 DRM_ERROR("no such CRTC id\n");
7296                 return -EINVAL;
7297         }
7298
7299         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7300         pipe_from_crtc_id->pipe = crtc->pipe;
7301
7302         return 0;
7303 }
7304
7305 static int intel_encoder_clones(struct intel_encoder *encoder)
7306 {
7307         struct drm_device *dev = encoder->base.dev;
7308         struct intel_encoder *source_encoder;
7309         int index_mask = 0;
7310         int entry = 0;
7311
7312         list_for_each_entry(source_encoder,
7313                             &dev->mode_config.encoder_list, base.head) {
7314
7315                 if (encoder == source_encoder)
7316                         index_mask |= (1 << entry);
7317
7318                 /* Intel hw has only one MUX where enocoders could be cloned. */
7319                 if (encoder->cloneable && source_encoder->cloneable)
7320                         index_mask |= (1 << entry);
7321
7322                 entry++;
7323         }
7324
7325         return index_mask;
7326 }
7327
7328 static bool has_edp_a(struct drm_device *dev)
7329 {
7330         struct drm_i915_private *dev_priv = dev->dev_private;
7331
7332         if (!IS_MOBILE(dev))
7333                 return false;
7334
7335         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7336                 return false;
7337
7338         if (IS_GEN5(dev) &&
7339             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7340                 return false;
7341
7342         return true;
7343 }
7344
7345 static void intel_setup_outputs(struct drm_device *dev)
7346 {
7347         struct drm_i915_private *dev_priv = dev->dev_private;
7348         struct intel_encoder *encoder;
7349         bool dpd_is_edp = false;
7350         bool has_lvds;
7351
7352         has_lvds = intel_lvds_init(dev);
7353         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7354                 /* disable the panel fitter on everything but LVDS */
7355                 I915_WRITE(PFIT_CONTROL, 0);
7356         }
7357
7358         if (HAS_PCH_SPLIT(dev)) {
7359                 dpd_is_edp = intel_dpd_is_edp(dev);
7360
7361                 if (has_edp_a(dev))
7362                         intel_dp_init(dev, DP_A, PORT_A);
7363
7364                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7365                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7366         }
7367
7368         intel_crt_init(dev);
7369
7370         if (IS_HASWELL(dev)) {
7371                 int found;
7372
7373                 /* Haswell uses DDI functions to detect digital outputs */
7374                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7375                 /* DDI A only supports eDP */
7376                 if (found)
7377                         intel_ddi_init(dev, PORT_A);
7378
7379                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7380                  * register */
7381                 found = I915_READ(SFUSE_STRAP);
7382
7383                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7384                         intel_ddi_init(dev, PORT_B);
7385                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7386                         intel_ddi_init(dev, PORT_C);
7387                 if (found & SFUSE_STRAP_DDID_DETECTED)
7388                         intel_ddi_init(dev, PORT_D);
7389         } else if (HAS_PCH_SPLIT(dev)) {
7390                 int found;
7391
7392                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7393                         /* PCH SDVOB multiplex with HDMIB */
7394                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7395                         if (!found)
7396                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7397                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7398                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7399                 }
7400
7401                 if (I915_READ(HDMIC) & PORT_DETECTED)
7402                         intel_hdmi_init(dev, HDMIC, PORT_C);
7403
7404                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7405                         intel_hdmi_init(dev, HDMID, PORT_D);
7406
7407                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7408                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7409
7410                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7411                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7412         } else if (IS_VALLEYVIEW(dev)) {
7413                 int found;
7414
7415                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7416                         /* SDVOB multiplex with HDMIB */
7417                         found = intel_sdvo_init(dev, SDVOB, true);
7418                         if (!found)
7419                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7420                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7421                                 intel_dp_init(dev, DP_B, PORT_B);
7422                 }
7423
7424                 if (I915_READ(SDVOC) & PORT_DETECTED)
7425                         intel_hdmi_init(dev, SDVOC, PORT_C);
7426
7427                 /* Shares lanes with HDMI on SDVOC */
7428                 if (I915_READ(DP_C) & DP_DETECTED)
7429                         intel_dp_init(dev, DP_C, PORT_C);
7430         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7431                 bool found = false;
7432
7433                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7434                         DRM_DEBUG_KMS("probing SDVOB\n");
7435                         found = intel_sdvo_init(dev, SDVOB, true);
7436                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7437                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7438                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7439                         }
7440
7441                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7442                                 DRM_DEBUG_KMS("probing DP_B\n");
7443                                 intel_dp_init(dev, DP_B, PORT_B);
7444                         }
7445                 }
7446
7447                 /* Before G4X SDVOC doesn't have its own detect register */
7448
7449                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7450                         DRM_DEBUG_KMS("probing SDVOC\n");
7451                         found = intel_sdvo_init(dev, SDVOC, false);
7452                 }
7453
7454                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7455
7456                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7457                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7458                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7459                         }
7460                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7461                                 DRM_DEBUG_KMS("probing DP_C\n");
7462                                 intel_dp_init(dev, DP_C, PORT_C);
7463                         }
7464                 }
7465
7466                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7467                     (I915_READ(DP_D) & DP_DETECTED)) {
7468                         DRM_DEBUG_KMS("probing DP_D\n");
7469                         intel_dp_init(dev, DP_D, PORT_D);
7470                 }
7471         } else if (IS_GEN2(dev))
7472                 intel_dvo_init(dev);
7473
7474         if (SUPPORTS_TV(dev))
7475                 intel_tv_init(dev);
7476
7477         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7478                 encoder->base.possible_crtcs = encoder->crtc_mask;
7479                 encoder->base.possible_clones =
7480                         intel_encoder_clones(encoder);
7481         }
7482
7483         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7484                 ironlake_init_pch_refclk(dev);
7485 }
7486
7487 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7488 {
7489         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7490
7491         drm_framebuffer_cleanup(fb);
7492         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7493
7494         kfree(intel_fb);
7495 }
7496
7497 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7498                                                 struct drm_file *file,
7499                                                 unsigned int *handle)
7500 {
7501         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7502         struct drm_i915_gem_object *obj = intel_fb->obj;
7503
7504         return drm_gem_handle_create(file, &obj->base, handle);
7505 }
7506
7507 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7508         .destroy = intel_user_framebuffer_destroy,
7509         .create_handle = intel_user_framebuffer_create_handle,
7510 };
7511
7512 int intel_framebuffer_init(struct drm_device *dev,
7513                            struct intel_framebuffer *intel_fb,
7514                            struct drm_mode_fb_cmd2 *mode_cmd,
7515                            struct drm_i915_gem_object *obj)
7516 {
7517         int ret;
7518
7519         if (obj->tiling_mode == I915_TILING_Y)
7520                 return -EINVAL;
7521
7522         if (mode_cmd->pitches[0] & 63)
7523                 return -EINVAL;
7524
7525         switch (mode_cmd->pixel_format) {
7526         case DRM_FORMAT_RGB332:
7527         case DRM_FORMAT_RGB565:
7528         case DRM_FORMAT_XRGB8888:
7529         case DRM_FORMAT_XBGR8888:
7530         case DRM_FORMAT_ARGB8888:
7531         case DRM_FORMAT_XRGB2101010:
7532         case DRM_FORMAT_ARGB2101010:
7533                 /* RGB formats are common across chipsets */
7534                 break;
7535         case DRM_FORMAT_YUYV:
7536         case DRM_FORMAT_UYVY:
7537         case DRM_FORMAT_YVYU:
7538         case DRM_FORMAT_VYUY:
7539                 break;
7540         default:
7541                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7542                                 mode_cmd->pixel_format);
7543                 return -EINVAL;
7544         }
7545
7546         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7547         if (ret) {
7548                 DRM_ERROR("framebuffer init failed %d\n", ret);
7549                 return ret;
7550         }
7551
7552         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7553         intel_fb->obj = obj;
7554         return 0;
7555 }
7556
7557 static struct drm_framebuffer *
7558 intel_user_framebuffer_create(struct drm_device *dev,
7559                               struct drm_file *filp,
7560                               struct drm_mode_fb_cmd2 *mode_cmd)
7561 {
7562         struct drm_i915_gem_object *obj;
7563
7564         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7565                                                 mode_cmd->handles[0]));
7566         if (&obj->base == NULL)
7567                 return ERR_PTR(-ENOENT);
7568
7569         return intel_framebuffer_create(dev, mode_cmd, obj);
7570 }
7571
7572 static const struct drm_mode_config_funcs intel_mode_funcs = {
7573         .fb_create = intel_user_framebuffer_create,
7574         .output_poll_changed = intel_fb_output_poll_changed,
7575 };
7576
7577 /* Set up chip specific display functions */
7578 static void intel_init_display(struct drm_device *dev)
7579 {
7580         struct drm_i915_private *dev_priv = dev->dev_private;
7581
7582         /* We always want a DPMS function */
7583         if (HAS_PCH_SPLIT(dev)) {
7584                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7585                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7586                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7587                 dev_priv->display.off = ironlake_crtc_off;
7588                 dev_priv->display.update_plane = ironlake_update_plane;
7589         } else {
7590                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7591                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7592                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7593                 dev_priv->display.off = i9xx_crtc_off;
7594                 dev_priv->display.update_plane = i9xx_update_plane;
7595         }
7596
7597         /* Returns the core display clock speed */
7598         if (IS_VALLEYVIEW(dev))
7599                 dev_priv->display.get_display_clock_speed =
7600                         valleyview_get_display_clock_speed;
7601         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7602                 dev_priv->display.get_display_clock_speed =
7603                         i945_get_display_clock_speed;
7604         else if (IS_I915G(dev))
7605                 dev_priv->display.get_display_clock_speed =
7606                         i915_get_display_clock_speed;
7607         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7608                 dev_priv->display.get_display_clock_speed =
7609                         i9xx_misc_get_display_clock_speed;
7610         else if (IS_I915GM(dev))
7611                 dev_priv->display.get_display_clock_speed =
7612                         i915gm_get_display_clock_speed;
7613         else if (IS_I865G(dev))
7614                 dev_priv->display.get_display_clock_speed =
7615                         i865_get_display_clock_speed;
7616         else if (IS_I85X(dev))
7617                 dev_priv->display.get_display_clock_speed =
7618                         i855_get_display_clock_speed;
7619         else /* 852, 830 */
7620                 dev_priv->display.get_display_clock_speed =
7621                         i830_get_display_clock_speed;
7622
7623         if (HAS_PCH_SPLIT(dev)) {
7624                 if (IS_GEN5(dev)) {
7625                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7626                         dev_priv->display.write_eld = ironlake_write_eld;
7627                 } else if (IS_GEN6(dev)) {
7628                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7629                         dev_priv->display.write_eld = ironlake_write_eld;
7630                 } else if (IS_IVYBRIDGE(dev)) {
7631                         /* FIXME: detect B0+ stepping and use auto training */
7632                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7633                         dev_priv->display.write_eld = ironlake_write_eld;
7634                 } else if (IS_HASWELL(dev)) {
7635                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7636                         dev_priv->display.write_eld = haswell_write_eld;
7637                 } else
7638                         dev_priv->display.update_wm = NULL;
7639         } else if (IS_G4X(dev)) {
7640                 dev_priv->display.write_eld = g4x_write_eld;
7641         }
7642
7643         /* Default just returns -ENODEV to indicate unsupported */
7644         dev_priv->display.queue_flip = intel_default_queue_flip;
7645
7646         switch (INTEL_INFO(dev)->gen) {
7647         case 2:
7648                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7649                 break;
7650
7651         case 3:
7652                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7653                 break;
7654
7655         case 4:
7656         case 5:
7657                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7658                 break;
7659
7660         case 6:
7661                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7662                 break;
7663         case 7:
7664                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7665                 break;
7666         }
7667 }
7668
7669 /*
7670  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7671  * resume, or other times.  This quirk makes sure that's the case for
7672  * affected systems.
7673  */
7674 static void quirk_pipea_force(struct drm_device *dev)
7675 {
7676         struct drm_i915_private *dev_priv = dev->dev_private;
7677
7678         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7679         DRM_INFO("applying pipe a force quirk\n");
7680 }
7681
7682 /*
7683  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7684  */
7685 static void quirk_ssc_force_disable(struct drm_device *dev)
7686 {
7687         struct drm_i915_private *dev_priv = dev->dev_private;
7688         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7689         DRM_INFO("applying lvds SSC disable quirk\n");
7690 }
7691
7692 /*
7693  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7694  * brightness value
7695  */
7696 static void quirk_invert_brightness(struct drm_device *dev)
7697 {
7698         struct drm_i915_private *dev_priv = dev->dev_private;
7699         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7700         DRM_INFO("applying inverted panel brightness quirk\n");
7701 }
7702
7703 struct intel_quirk {
7704         int device;
7705         int subsystem_vendor;
7706         int subsystem_device;
7707         void (*hook)(struct drm_device *dev);
7708 };
7709
7710 static struct intel_quirk intel_quirks[] = {
7711         /* HP Mini needs pipe A force quirk (LP: #322104) */
7712         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7713
7714         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7715         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7716
7717         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7718         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7719
7720         /* 855 & before need to leave pipe A & dpll A up */
7721         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7722         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7723         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7724
7725         /* Lenovo U160 cannot use SSC on LVDS */
7726         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7727
7728         /* Sony Vaio Y cannot use SSC on LVDS */
7729         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7730
7731         /* Acer Aspire 5734Z must invert backlight brightness */
7732         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7733 };
7734
7735 static void intel_init_quirks(struct drm_device *dev)
7736 {
7737         struct pci_dev *d = dev->pdev;
7738         int i;
7739
7740         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7741                 struct intel_quirk *q = &intel_quirks[i];
7742
7743                 if (d->device == q->device &&
7744                     (d->subsystem_vendor == q->subsystem_vendor ||
7745                      q->subsystem_vendor == PCI_ANY_ID) &&
7746                     (d->subsystem_device == q->subsystem_device ||
7747                      q->subsystem_device == PCI_ANY_ID))
7748                         q->hook(dev);
7749         }
7750 }
7751
7752 /* Disable the VGA plane that we never use */
7753 static void i915_disable_vga(struct drm_device *dev)
7754 {
7755         struct drm_i915_private *dev_priv = dev->dev_private;
7756         u8 sr1;
7757         u32 vga_reg;
7758
7759         if (HAS_PCH_SPLIT(dev))
7760                 vga_reg = CPU_VGACNTRL;
7761         else
7762                 vga_reg = VGACNTRL;
7763
7764         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7765         outb(SR01, VGA_SR_INDEX);
7766         sr1 = inb(VGA_SR_DATA);
7767         outb(sr1 | 1<<5, VGA_SR_DATA);
7768         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7769         udelay(300);
7770
7771         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7772         POSTING_READ(vga_reg);
7773 }
7774
7775 void intel_modeset_init_hw(struct drm_device *dev)
7776 {
7777         /* We attempt to init the necessary power wells early in the initialization
7778          * time, so the subsystems that expect power to be enabled can work.
7779          */
7780         intel_init_power_wells(dev);
7781
7782         intel_prepare_ddi(dev);
7783
7784         intel_init_clock_gating(dev);
7785
7786         mutex_lock(&dev->struct_mutex);
7787         intel_enable_gt_powersave(dev);
7788         mutex_unlock(&dev->struct_mutex);
7789 }
7790
7791 void intel_modeset_init(struct drm_device *dev)
7792 {
7793         struct drm_i915_private *dev_priv = dev->dev_private;
7794         int i, ret;
7795
7796         drm_mode_config_init(dev);
7797
7798         dev->mode_config.min_width = 0;
7799         dev->mode_config.min_height = 0;
7800
7801         dev->mode_config.preferred_depth = 24;
7802         dev->mode_config.prefer_shadow = 1;
7803
7804         dev->mode_config.funcs = &intel_mode_funcs;
7805
7806         intel_init_quirks(dev);
7807
7808         intel_init_pm(dev);
7809
7810         intel_init_display(dev);
7811
7812         if (IS_GEN2(dev)) {
7813                 dev->mode_config.max_width = 2048;
7814                 dev->mode_config.max_height = 2048;
7815         } else if (IS_GEN3(dev)) {
7816                 dev->mode_config.max_width = 4096;
7817                 dev->mode_config.max_height = 4096;
7818         } else {
7819                 dev->mode_config.max_width = 8192;
7820                 dev->mode_config.max_height = 8192;
7821         }
7822         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7823
7824         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7825                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7826
7827         for (i = 0; i < dev_priv->num_pipe; i++) {
7828                 intel_crtc_init(dev, i);
7829                 ret = intel_plane_init(dev, i);
7830                 if (ret)
7831                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7832         }
7833
7834         intel_pch_pll_init(dev);
7835
7836         /* Just disable it once at startup */
7837         i915_disable_vga(dev);
7838         intel_setup_outputs(dev);
7839 }
7840
7841 static void
7842 intel_connector_break_all_links(struct intel_connector *connector)
7843 {
7844         connector->base.dpms = DRM_MODE_DPMS_OFF;
7845         connector->base.encoder = NULL;
7846         connector->encoder->connectors_active = false;
7847         connector->encoder->base.crtc = NULL;
7848 }
7849
7850 static void intel_enable_pipe_a(struct drm_device *dev)
7851 {
7852         struct intel_connector *connector;
7853         struct drm_connector *crt = NULL;
7854         struct intel_load_detect_pipe load_detect_temp;
7855
7856         /* We can't just switch on the pipe A, we need to set things up with a
7857          * proper mode and output configuration. As a gross hack, enable pipe A
7858          * by enabling the load detect pipe once. */
7859         list_for_each_entry(connector,
7860                             &dev->mode_config.connector_list,
7861                             base.head) {
7862                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7863                         crt = &connector->base;
7864                         break;
7865                 }
7866         }
7867
7868         if (!crt)
7869                 return;
7870
7871         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7872                 intel_release_load_detect_pipe(crt, &load_detect_temp);
7873
7874
7875 }
7876
7877 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7878 {
7879         struct drm_device *dev = crtc->base.dev;
7880         struct drm_i915_private *dev_priv = dev->dev_private;
7881         u32 reg, val;
7882
7883         /* Clear any frame start delays used for debugging left by the BIOS */
7884         reg = PIPECONF(crtc->pipe);
7885         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7886
7887         /* We need to sanitize the plane -> pipe mapping first because this will
7888          * disable the crtc (and hence change the state) if it is wrong. */
7889         if (!HAS_PCH_SPLIT(dev)) {
7890                 struct intel_connector *connector;
7891                 bool plane;
7892
7893                 reg = DSPCNTR(crtc->plane);
7894                 val = I915_READ(reg);
7895
7896                 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7897                     (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7898                         goto ok;
7899
7900                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7901                               crtc->base.base.id);
7902
7903                 /* Pipe has the wrong plane attached and the plane is active.
7904                  * Temporarily change the plane mapping and disable everything
7905                  * ...  */
7906                 plane = crtc->plane;
7907                 crtc->plane = !plane;
7908                 dev_priv->display.crtc_disable(&crtc->base);
7909                 crtc->plane = plane;
7910
7911                 /* ... and break all links. */
7912                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7913                                     base.head) {
7914                         if (connector->encoder->base.crtc != &crtc->base)
7915                                 continue;
7916
7917                         intel_connector_break_all_links(connector);
7918                 }
7919
7920                 WARN_ON(crtc->active);
7921                 crtc->base.enabled = false;
7922         }
7923 ok:
7924
7925         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7926             crtc->pipe == PIPE_A && !crtc->active) {
7927                 /* BIOS forgot to enable pipe A, this mostly happens after
7928                  * resume. Force-enable the pipe to fix this, the update_dpms
7929                  * call below we restore the pipe to the right state, but leave
7930                  * the required bits on. */
7931                 intel_enable_pipe_a(dev);
7932         }
7933
7934         /* Adjust the state of the output pipe according to whether we
7935          * have active connectors/encoders. */
7936         intel_crtc_update_dpms(&crtc->base);
7937
7938         if (crtc->active != crtc->base.enabled) {
7939                 struct intel_encoder *encoder;
7940
7941                 /* This can happen either due to bugs in the get_hw_state
7942                  * functions or because the pipe is force-enabled due to the
7943                  * pipe A quirk. */
7944                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7945                               crtc->base.base.id,
7946                               crtc->base.enabled ? "enabled" : "disabled",
7947                               crtc->active ? "enabled" : "disabled");
7948
7949                 crtc->base.enabled = crtc->active;
7950
7951                 /* Because we only establish the connector -> encoder ->
7952                  * crtc links if something is active, this means the
7953                  * crtc is now deactivated. Break the links. connector
7954                  * -> encoder links are only establish when things are
7955                  *  actually up, hence no need to break them. */
7956                 WARN_ON(crtc->active);
7957
7958                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7959                         WARN_ON(encoder->connectors_active);
7960                         encoder->base.crtc = NULL;
7961                 }
7962         }
7963 }
7964
7965 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7966 {
7967         struct intel_connector *connector;
7968         struct drm_device *dev = encoder->base.dev;
7969
7970         /* We need to check both for a crtc link (meaning that the
7971          * encoder is active and trying to read from a pipe) and the
7972          * pipe itself being active. */
7973         bool has_active_crtc = encoder->base.crtc &&
7974                 to_intel_crtc(encoder->base.crtc)->active;
7975
7976         if (encoder->connectors_active && !has_active_crtc) {
7977                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7978                               encoder->base.base.id,
7979                               drm_get_encoder_name(&encoder->base));
7980
7981                 /* Connector is active, but has no active pipe. This is
7982                  * fallout from our resume register restoring. Disable
7983                  * the encoder manually again. */
7984                 if (encoder->base.crtc) {
7985                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7986                                       encoder->base.base.id,
7987                                       drm_get_encoder_name(&encoder->base));
7988                         encoder->disable(encoder);
7989                 }
7990
7991                 /* Inconsistent output/port/pipe state happens presumably due to
7992                  * a bug in one of the get_hw_state functions. Or someplace else
7993                  * in our code, like the register restore mess on resume. Clamp
7994                  * things to off as a safer default. */
7995                 list_for_each_entry(connector,
7996                                     &dev->mode_config.connector_list,
7997                                     base.head) {
7998                         if (connector->encoder != encoder)
7999                                 continue;
8000
8001                         intel_connector_break_all_links(connector);
8002                 }
8003         }
8004         /* Enabled encoders without active connectors will be fixed in
8005          * the crtc fixup. */
8006 }
8007
8008 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8009  * and i915 state tracking structures. */
8010 void intel_modeset_setup_hw_state(struct drm_device *dev)
8011 {
8012         struct drm_i915_private *dev_priv = dev->dev_private;
8013         enum pipe pipe;
8014         u32 tmp;
8015         struct intel_crtc *crtc;
8016         struct intel_encoder *encoder;
8017         struct intel_connector *connector;
8018
8019         for_each_pipe(pipe) {
8020                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8021
8022                 tmp = I915_READ(PIPECONF(pipe));
8023                 if (tmp & PIPECONF_ENABLE)
8024                         crtc->active = true;
8025                 else
8026                         crtc->active = false;
8027
8028                 crtc->base.enabled = crtc->active;
8029
8030                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8031                               crtc->base.base.id,
8032                               crtc->active ? "enabled" : "disabled");
8033         }
8034
8035         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8036                             base.head) {
8037                 pipe = 0;
8038
8039                 if (encoder->get_hw_state(encoder, &pipe)) {
8040                         encoder->base.crtc =
8041                                 dev_priv->pipe_to_crtc_mapping[pipe];
8042                 } else {
8043                         encoder->base.crtc = NULL;
8044                 }
8045
8046                 encoder->connectors_active = false;
8047                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8048                               encoder->base.base.id,
8049                               drm_get_encoder_name(&encoder->base),
8050                               encoder->base.crtc ? "enabled" : "disabled",
8051                               pipe);
8052         }
8053
8054         list_for_each_entry(connector, &dev->mode_config.connector_list,
8055                             base.head) {
8056                 if (connector->get_hw_state(connector)) {
8057                         connector->base.dpms = DRM_MODE_DPMS_ON;
8058                         connector->encoder->connectors_active = true;
8059                         connector->base.encoder = &connector->encoder->base;
8060                 } else {
8061                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8062                         connector->base.encoder = NULL;
8063                 }
8064                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8065                               connector->base.base.id,
8066                               drm_get_connector_name(&connector->base),
8067                               connector->base.encoder ? "enabled" : "disabled");
8068         }
8069
8070         /* HW state is read out, now we need to sanitize this mess. */
8071         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8072                             base.head) {
8073                 intel_sanitize_encoder(encoder);
8074         }
8075
8076         for_each_pipe(pipe) {
8077                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8078                 intel_sanitize_crtc(crtc);
8079         }
8080
8081         intel_modeset_update_staged_output_state(dev);
8082 }
8083
8084 void intel_modeset_gem_init(struct drm_device *dev)
8085 {
8086         intel_modeset_init_hw(dev);
8087
8088         intel_setup_overlay(dev);
8089
8090         intel_modeset_setup_hw_state(dev);
8091 }
8092
8093 void intel_modeset_cleanup(struct drm_device *dev)
8094 {
8095         struct drm_i915_private *dev_priv = dev->dev_private;
8096         struct drm_crtc *crtc;
8097         struct intel_crtc *intel_crtc;
8098
8099         drm_kms_helper_poll_fini(dev);
8100         mutex_lock(&dev->struct_mutex);
8101
8102         intel_unregister_dsm_handler();
8103
8104
8105         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8106                 /* Skip inactive CRTCs */
8107                 if (!crtc->fb)
8108                         continue;
8109
8110                 intel_crtc = to_intel_crtc(crtc);
8111                 intel_increase_pllclock(crtc);
8112         }
8113
8114         intel_disable_fbc(dev);
8115
8116         intel_disable_gt_powersave(dev);
8117
8118         ironlake_teardown_rc6(dev);
8119
8120         if (IS_VALLEYVIEW(dev))
8121                 vlv_init_dpio(dev);
8122
8123         mutex_unlock(&dev->struct_mutex);
8124
8125         /* Disable the irq before mode object teardown, for the irq might
8126          * enqueue unpin/hotplug work. */
8127         drm_irq_uninstall(dev);
8128         cancel_work_sync(&dev_priv->hotplug_work);
8129         cancel_work_sync(&dev_priv->rps.work);
8130
8131         /* flush any delayed tasks or pending work */
8132         flush_scheduled_work();
8133
8134         drm_mode_config_cleanup(dev);
8135 }
8136
8137 /*
8138  * Return which encoder is currently attached for connector.
8139  */
8140 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8141 {
8142         return &intel_attached_encoder(connector)->base;
8143 }
8144
8145 void intel_connector_attach_encoder(struct intel_connector *connector,
8146                                     struct intel_encoder *encoder)
8147 {
8148         connector->encoder = encoder;
8149         drm_mode_connector_attach_encoder(&connector->base,
8150                                           &encoder->base);
8151 }
8152
8153 /*
8154  * set vga decode state - true == enable VGA decode
8155  */
8156 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8157 {
8158         struct drm_i915_private *dev_priv = dev->dev_private;
8159         u16 gmch_ctrl;
8160
8161         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8162         if (state)
8163                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8164         else
8165                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8166         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8167         return 0;
8168 }
8169
8170 #ifdef CONFIG_DEBUG_FS
8171 #include <linux/seq_file.h>
8172
8173 struct intel_display_error_state {
8174         struct intel_cursor_error_state {
8175                 u32 control;
8176                 u32 position;
8177                 u32 base;
8178                 u32 size;
8179         } cursor[I915_MAX_PIPES];
8180
8181         struct intel_pipe_error_state {
8182                 u32 conf;
8183                 u32 source;
8184
8185                 u32 htotal;
8186                 u32 hblank;
8187                 u32 hsync;
8188                 u32 vtotal;
8189                 u32 vblank;
8190                 u32 vsync;
8191         } pipe[I915_MAX_PIPES];
8192
8193         struct intel_plane_error_state {
8194                 u32 control;
8195                 u32 stride;
8196                 u32 size;
8197                 u32 pos;
8198                 u32 addr;
8199                 u32 surface;
8200                 u32 tile_offset;
8201         } plane[I915_MAX_PIPES];
8202 };
8203
8204 struct intel_display_error_state *
8205 intel_display_capture_error_state(struct drm_device *dev)
8206 {
8207         drm_i915_private_t *dev_priv = dev->dev_private;
8208         struct intel_display_error_state *error;
8209         int i;
8210
8211         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8212         if (error == NULL)
8213                 return NULL;
8214
8215         for_each_pipe(i) {
8216                 error->cursor[i].control = I915_READ(CURCNTR(i));
8217                 error->cursor[i].position = I915_READ(CURPOS(i));
8218                 error->cursor[i].base = I915_READ(CURBASE(i));
8219
8220                 error->plane[i].control = I915_READ(DSPCNTR(i));
8221                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8222                 error->plane[i].size = I915_READ(DSPSIZE(i));
8223                 error->plane[i].pos = I915_READ(DSPPOS(i));
8224                 error->plane[i].addr = I915_READ(DSPADDR(i));
8225                 if (INTEL_INFO(dev)->gen >= 4) {
8226                         error->plane[i].surface = I915_READ(DSPSURF(i));
8227                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8228                 }
8229
8230                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8231                 error->pipe[i].source = I915_READ(PIPESRC(i));
8232                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8233                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8234                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8235                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8236                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8237                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8238         }
8239
8240         return error;
8241 }
8242
8243 void
8244 intel_display_print_error_state(struct seq_file *m,
8245                                 struct drm_device *dev,
8246                                 struct intel_display_error_state *error)
8247 {
8248         drm_i915_private_t *dev_priv = dev->dev_private;
8249         int i;
8250
8251         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8252         for_each_pipe(i) {
8253                 seq_printf(m, "Pipe [%d]:\n", i);
8254                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8255                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8256                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8257                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8258                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8259                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8260                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8261                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8262
8263                 seq_printf(m, "Plane [%d]:\n", i);
8264                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8265                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8266                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8267                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8268                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8269                 if (INTEL_INFO(dev)->gen >= 4) {
8270                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8271                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8272                 }
8273
8274                 seq_printf(m, "Cursor [%d]:\n", i);
8275                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8276                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8277                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8278         }
8279 }
8280 #endif