Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  *
1433  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434  */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* No really, not for ILK+ */
1441         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443         /* PLL is protected by panel, make sure we can write it */
1444         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445                 assert_panel_unlocked(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val |= DPLL_VCO_ENABLE;
1450
1451         /* We do this three times for luck */
1452         I915_WRITE(reg, val);
1453         POSTING_READ(reg);
1454         udelay(150); /* wait for warmup */
1455         I915_WRITE(reg, val);
1456         POSTING_READ(reg);
1457         udelay(150); /* wait for warmup */
1458         I915_WRITE(reg, val);
1459         POSTING_READ(reg);
1460         udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464  * intel_disable_pll - disable a PLL
1465  * @dev_priv: i915 private structure
1466  * @pipe: pipe PLL to disable
1467  *
1468  * Disable the PLL for @pipe, making sure the pipe is off first.
1469  *
1470  * Note!  This is for pre-ILK only.
1471  */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474         int reg;
1475         u32 val;
1476
1477         /* Don't disable pipe A or pipe A PLLs if needed */
1478         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479                 return;
1480
1481         /* Make sure the pipe isn't still relying on us */
1482         assert_pipe_disabled(dev_priv, pipe);
1483
1484         reg = DPLL(pipe);
1485         val = I915_READ(reg);
1486         val &= ~DPLL_VCO_ENABLE;
1487         I915_WRITE(reg, val);
1488         POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495         unsigned long flags;
1496
1497         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499                                 100)) {
1500                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501                 goto out_unlock;
1502         }
1503
1504         I915_WRITE(SBI_ADDR,
1505                         (reg << 16));
1506         I915_WRITE(SBI_DATA,
1507                         value);
1508         I915_WRITE(SBI_CTL_STAT,
1509                         SBI_BUSY |
1510                         SBI_CTL_OP_CRWR);
1511
1512         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513                                 100)) {
1514                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515                 goto out_unlock;
1516         }
1517
1518 out_unlock:
1519         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525         unsigned long flags;
1526         u32 value = 0;
1527
1528         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530                                 100)) {
1531                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532                 goto out_unlock;
1533         }
1534
1535         I915_WRITE(SBI_ADDR,
1536                         (reg << 16));
1537         I915_WRITE(SBI_CTL_STAT,
1538                         SBI_BUSY |
1539                         SBI_CTL_OP_CRRD);
1540
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544                 goto out_unlock;
1545         }
1546
1547         value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551         return value;
1552 }
1553
1554 /**
1555  * intel_enable_pch_pll - enable PCH PLL
1556  * @dev_priv: i915 private structure
1557  * @pipe: pipe PLL to enable
1558  *
1559  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560  * drives the transcoder clock.
1561  */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565         struct intel_pch_pll *pll;
1566         int reg;
1567         u32 val;
1568
1569         /* PCH PLLs only available on ILK, SNB and IVB */
1570         BUG_ON(dev_priv->info->gen < 5);
1571         pll = intel_crtc->pch_pll;
1572         if (pll == NULL)
1573                 return;
1574
1575         if (WARN_ON(pll->refcount == 0))
1576                 return;
1577
1578         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579                       pll->pll_reg, pll->active, pll->on,
1580                       intel_crtc->base.base.id);
1581
1582         /* PCH refclock must be enabled first */
1583         assert_pch_refclk_enabled(dev_priv);
1584
1585         if (pll->active++ && pll->on) {
1586                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587                 return;
1588         }
1589
1590         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592         reg = pll->pll_reg;
1593         val = I915_READ(reg);
1594         val |= DPLL_VCO_ENABLE;
1595         I915_WRITE(reg, val);
1596         POSTING_READ(reg);
1597         udelay(200);
1598
1599         pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606         int reg;
1607         u32 val;
1608
1609         /* PCH only available on ILK+ */
1610         BUG_ON(dev_priv->info->gen < 5);
1611         if (pll == NULL)
1612                return;
1613
1614         if (WARN_ON(pll->refcount == 0))
1615                 return;
1616
1617         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618                       pll->pll_reg, pll->active, pll->on,
1619                       intel_crtc->base.base.id);
1620
1621         if (WARN_ON(pll->active == 0)) {
1622                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623                 return;
1624         }
1625
1626         if (--pll->active) {
1627                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628                 return;
1629         }
1630
1631         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633         /* Make sure transcoder isn't still depending on us */
1634         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636         reg = pll->pll_reg;
1637         val = I915_READ(reg);
1638         val &= ~DPLL_VCO_ENABLE;
1639         I915_WRITE(reg, val);
1640         POSTING_READ(reg);
1641         udelay(200);
1642
1643         pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647                                     enum pipe pipe)
1648 {
1649         int reg;
1650         u32 val, pipeconf_val;
1651         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653         /* PCH only available on ILK+ */
1654         BUG_ON(dev_priv->info->gen < 5);
1655
1656         /* Make sure PCH DPLL is enabled */
1657         assert_pch_pll_enabled(dev_priv,
1658                                to_intel_crtc(crtc)->pch_pll,
1659                                to_intel_crtc(crtc));
1660
1661         /* FDI must be feeding us bits for PCH ports */
1662         assert_fdi_tx_enabled(dev_priv, pipe);
1663         assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667                 return;
1668         }
1669         reg = TRANSCONF(pipe);
1670         val = I915_READ(reg);
1671         pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673         if (HAS_PCH_IBX(dev_priv->dev)) {
1674                 /*
1675                  * make the BPC in transcoder be consistent with
1676                  * that in pipeconf reg.
1677                  */
1678                 val &= ~PIPE_BPC_MASK;
1679                 val |= pipeconf_val & PIPE_BPC_MASK;
1680         }
1681
1682         val &= ~TRANS_INTERLACE_MASK;
1683         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684                 if (HAS_PCH_IBX(dev_priv->dev) &&
1685                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686                         val |= TRANS_LEGACY_INTERLACED_ILK;
1687                 else
1688                         val |= TRANS_INTERLACED;
1689         else
1690                 val |= TRANS_PROGRESSIVE;
1691
1692         I915_WRITE(reg, val | TRANS_ENABLE);
1693         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698                                      enum pipe pipe)
1699 {
1700         int reg;
1701         u32 val;
1702
1703         /* FDI relies on the transcoder */
1704         assert_fdi_tx_disabled(dev_priv, pipe);
1705         assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707         /* Ports must be off as well */
1708         assert_pch_ports_disabled(dev_priv, pipe);
1709
1710         reg = TRANSCONF(pipe);
1711         val = I915_READ(reg);
1712         val &= ~TRANS_ENABLE;
1713         I915_WRITE(reg, val);
1714         /* wait for PCH transcoder off, transcoder state */
1715         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720  * intel_enable_pipe - enable a pipe, asserting requirements
1721  * @dev_priv: i915 private structure
1722  * @pipe: pipe to enable
1723  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724  *
1725  * Enable @pipe, making sure that various hardware specific requirements
1726  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727  *
1728  * @pipe should be %PIPE_A or %PIPE_B.
1729  *
1730  * Will wait until the pipe is actually running (i.e. first vblank) before
1731  * returning.
1732  */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734                               bool pch_port)
1735 {
1736         int reg;
1737         u32 val;
1738
1739         /*
1740          * A pipe without a PLL won't actually be able to drive bits from
1741          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1742          * need the check.
1743          */
1744         if (!HAS_PCH_SPLIT(dev_priv->dev))
1745                 assert_pll_enabled(dev_priv, pipe);
1746         else {
1747                 if (pch_port) {
1748                         /* if driving the PCH, we need FDI enabled */
1749                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751                 }
1752                 /* FIXME: assert CPU port conditions for SNB+ */
1753         }
1754
1755         reg = PIPECONF(pipe);
1756         val = I915_READ(reg);
1757         if (val & PIPECONF_ENABLE)
1758                 return;
1759
1760         I915_WRITE(reg, val | PIPECONF_ENABLE);
1761         intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765  * intel_disable_pipe - disable a pipe, asserting requirements
1766  * @dev_priv: i915 private structure
1767  * @pipe: pipe to disable
1768  *
1769  * Disable @pipe, making sure that various hardware specific requirements
1770  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771  *
1772  * @pipe should be %PIPE_A or %PIPE_B.
1773  *
1774  * Will wait until the pipe has shut down before returning.
1775  */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777                                enum pipe pipe)
1778 {
1779         int reg;
1780         u32 val;
1781
1782         /*
1783          * Make sure planes won't keep trying to pump pixels to us,
1784          * or we might hang the display.
1785          */
1786         assert_planes_disabled(dev_priv, pipe);
1787
1788         /* Don't disable pipe A or pipe A PLLs if needed */
1789         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790                 return;
1791
1792         reg = PIPECONF(pipe);
1793         val = I915_READ(reg);
1794         if ((val & PIPECONF_ENABLE) == 0)
1795                 return;
1796
1797         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802  * Plane regs are double buffered, going from enabled->disabled needs a
1803  * trigger in order to latch.  The display address reg provides this.
1804  */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806                                       enum plane plane)
1807 {
1808         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813  * intel_enable_plane - enable a display plane on a given pipe
1814  * @dev_priv: i915 private structure
1815  * @plane: plane to enable
1816  * @pipe: pipe being fed
1817  *
1818  * Enable @plane on @pipe, making sure that @pipe is running first.
1819  */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane, enum pipe pipe)
1822 {
1823         int reg;
1824         u32 val;
1825
1826         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827         assert_pipe_enabled(dev_priv, pipe);
1828
1829         reg = DSPCNTR(plane);
1830         val = I915_READ(reg);
1831         if (val & DISPLAY_PLANE_ENABLE)
1832                 return;
1833
1834         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835         intel_flush_display_plane(dev_priv, plane);
1836         intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840  * intel_disable_plane - disable a display plane
1841  * @dev_priv: i915 private structure
1842  * @plane: plane to disable
1843  * @pipe: pipe consuming the data
1844  *
1845  * Disable @plane; should be an independent operation.
1846  */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848                                 enum plane plane, enum pipe pipe)
1849 {
1850         int reg;
1851         u32 val;
1852
1853         reg = DSPCNTR(plane);
1854         val = I915_READ(reg);
1855         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856                 return;
1857
1858         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859         intel_flush_display_plane(dev_priv, plane);
1860         intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864                            enum pipe pipe, int reg, u32 port_sel)
1865 {
1866         u32 val = I915_READ(reg);
1867         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869                 I915_WRITE(reg, val & ~DP_PORT_EN);
1870         }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874                              enum pipe pipe, int reg)
1875 {
1876         u32 val = I915_READ(reg);
1877         if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879                               reg, pipe);
1880                 I915_WRITE(reg, val & ~PORT_ENABLE);
1881         }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886                                     enum pipe pipe)
1887 {
1888         u32 reg, val;
1889
1890         val = I915_READ(PCH_PP_CONTROL);
1891         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897         reg = PCH_ADPA;
1898         val = I915_READ(reg);
1899         if (adpa_pipe_enabled(dev_priv, pipe, val))
1900                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902         reg = PCH_LVDS;
1903         val = I915_READ(reg);
1904         if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907                 POSTING_READ(reg);
1908                 udelay(100);
1909         }
1910
1911         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913         disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918                            struct drm_i915_gem_object *obj,
1919                            struct intel_ring_buffer *pipelined)
1920 {
1921         struct drm_i915_private *dev_priv = dev->dev_private;
1922         u32 alignment;
1923         int ret;
1924
1925         switch (obj->tiling_mode) {
1926         case I915_TILING_NONE:
1927                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928                         alignment = 128 * 1024;
1929                 else if (INTEL_INFO(dev)->gen >= 4)
1930                         alignment = 4 * 1024;
1931                 else
1932                         alignment = 64 * 1024;
1933                 break;
1934         case I915_TILING_X:
1935                 /* pin() will align the object as required by fence */
1936                 alignment = 0;
1937                 break;
1938         case I915_TILING_Y:
1939                 /* FIXME: Is this true? */
1940                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941                 return -EINVAL;
1942         default:
1943                 BUG();
1944         }
1945
1946         dev_priv->mm.interruptible = false;
1947         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948         if (ret)
1949                 goto err_interruptible;
1950
1951         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952          * fence, whereas 965+ only requires a fence if using
1953          * framebuffer compression.  For simplicity, we always install
1954          * a fence as the cost is not that onerous.
1955          */
1956         ret = i915_gem_object_get_fence(obj);
1957         if (ret)
1958                 goto err_unpin;
1959
1960         i915_gem_object_pin_fence(obj);
1961
1962         dev_priv->mm.interruptible = true;
1963         return 0;
1964
1965 err_unpin:
1966         i915_gem_object_unpin(obj);
1967 err_interruptible:
1968         dev_priv->mm.interruptible = true;
1969         return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974         i915_gem_object_unpin_fence(obj);
1975         i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979  * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981                                                         unsigned int bpp,
1982                                                         unsigned int pitch)
1983 {
1984         int tile_rows, tiles;
1985
1986         tile_rows = *y / 8;
1987         *y %= 8;
1988         tiles = *x / (512/bpp);
1989         *x %= 512/bpp;
1990
1991         return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995                              int x, int y)
1996 {
1997         struct drm_device *dev = crtc->dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000         struct intel_framebuffer *intel_fb;
2001         struct drm_i915_gem_object *obj;
2002         int plane = intel_crtc->plane;
2003         unsigned long linear_offset;
2004         u32 dspcntr;
2005         u32 reg;
2006
2007         switch (plane) {
2008         case 0:
2009         case 1:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->bits_per_pixel) {
2024         case 8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case 16:
2028                 if (fb->depth == 15)
2029                         dspcntr |= DISPPLANE_15_16BPP;
2030                 else
2031                         dspcntr |= DISPPLANE_16BPP;
2032                 break;
2033         case 24:
2034         case 32:
2035                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036                 break;
2037         default:
2038                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039                 return -EINVAL;
2040         }
2041         if (INTEL_INFO(dev)->gen >= 4) {
2042                 if (obj->tiling_mode != I915_TILING_NONE)
2043                         dspcntr |= DISPPLANE_TILED;
2044                 else
2045                         dspcntr &= ~DISPPLANE_TILED;
2046         }
2047
2048         I915_WRITE(reg, dspcntr);
2049
2050         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052         if (INTEL_INFO(dev)->gen >= 4) {
2053                 intel_crtc->dspaddr_offset =
2054                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055                                                            fb->bits_per_pixel / 8,
2056                                                            fb->pitches[0]);
2057                 linear_offset -= intel_crtc->dspaddr_offset;
2058         } else {
2059                 intel_crtc->dspaddr_offset = linear_offset;
2060         }
2061
2062         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065         if (INTEL_INFO(dev)->gen >= 4) {
2066                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2068                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070         } else
2071                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072         POSTING_READ(reg);
2073
2074         return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078                                  struct drm_framebuffer *fb, int x, int y)
2079 {
2080         struct drm_device *dev = crtc->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083         struct intel_framebuffer *intel_fb;
2084         struct drm_i915_gem_object *obj;
2085         int plane = intel_crtc->plane;
2086         unsigned long linear_offset;
2087         u32 dspcntr;
2088         u32 reg;
2089
2090         switch (plane) {
2091         case 0:
2092         case 1:
2093         case 2:
2094                 break;
2095         default:
2096                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097                 return -EINVAL;
2098         }
2099
2100         intel_fb = to_intel_framebuffer(fb);
2101         obj = intel_fb->obj;
2102
2103         reg = DSPCNTR(plane);
2104         dspcntr = I915_READ(reg);
2105         /* Mask out pixel format bits in case we change it */
2106         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107         switch (fb->bits_per_pixel) {
2108         case 8:
2109                 dspcntr |= DISPPLANE_8BPP;
2110                 break;
2111         case 16:
2112                 if (fb->depth != 16)
2113                         return -EINVAL;
2114
2115                 dspcntr |= DISPPLANE_16BPP;
2116                 break;
2117         case 24:
2118         case 32:
2119                 if (fb->depth == 24)
2120                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121                 else if (fb->depth == 30)
2122                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123                 else
2124                         return -EINVAL;
2125                 break;
2126         default:
2127                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128                 return -EINVAL;
2129         }
2130
2131         if (obj->tiling_mode != I915_TILING_NONE)
2132                 dspcntr |= DISPPLANE_TILED;
2133         else
2134                 dspcntr &= ~DISPPLANE_TILED;
2135
2136         /* must disable */
2137         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139         I915_WRITE(reg, dspcntr);
2140
2141         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142         intel_crtc->dspaddr_offset =
2143                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144                                                    fb->bits_per_pixel / 8,
2145                                                    fb->pitches[0]);
2146         linear_offset -= intel_crtc->dspaddr_offset;
2147
2148         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151         I915_MODIFY_DISPBASE(DSPSURF(plane),
2152                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2153         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154         I915_WRITE(DSPLINOFF(plane), linear_offset);
2155         POSTING_READ(reg);
2156
2157         return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163                            int x, int y, enum mode_set_atomic state)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168         if (dev_priv->display.disable_fbc)
2169                 dev_priv->display.disable_fbc(dev);
2170         intel_increase_pllclock(crtc);
2171
2172         return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180         bool was_interruptible = dev_priv->mm.interruptible;
2181         int ret;
2182
2183         wait_event(dev_priv->pending_flip_queue,
2184                    atomic_read(&dev_priv->mm.wedged) ||
2185                    atomic_read(&obj->pending_flip) == 0);
2186
2187         /* Big Hammer, we also need to ensure that any pending
2188          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189          * current scanout is retired before unpinning the old
2190          * framebuffer.
2191          *
2192          * This should only fail upon a hung GPU, in which case we
2193          * can safely continue.
2194          */
2195         dev_priv->mm.interruptible = false;
2196         ret = i915_gem_object_finish_gpu(obj);
2197         dev_priv->mm.interruptible = was_interruptible;
2198
2199         return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204                     struct drm_framebuffer *old_fb)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_i915_master_private *master_priv;
2209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210         int ret;
2211
2212         /* no fb bound */
2213         if (!crtc->fb) {
2214                 DRM_ERROR("No FB bound\n");
2215                 return 0;
2216         }
2217
2218         if(intel_crtc->plane > dev_priv->num_pipe) {
2219                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220                                 intel_crtc->plane,
2221                                 dev_priv->num_pipe);
2222                 return -EINVAL;
2223         }
2224
2225         mutex_lock(&dev->struct_mutex);
2226         ret = intel_pin_and_fence_fb_obj(dev,
2227                                          to_intel_framebuffer(crtc->fb)->obj,
2228                                          NULL);
2229         if (ret != 0) {
2230                 mutex_unlock(&dev->struct_mutex);
2231                 DRM_ERROR("pin & fence failed\n");
2232                 return ret;
2233         }
2234
2235         if (old_fb)
2236                 intel_finish_fb(old_fb);
2237
2238         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239         if (ret) {
2240                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241                 mutex_unlock(&dev->struct_mutex);
2242                 DRM_ERROR("failed to update base address\n");
2243                 return ret;
2244         }
2245
2246         if (old_fb) {
2247                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249         }
2250
2251         intel_update_fbc(dev);
2252         mutex_unlock(&dev->struct_mutex);
2253
2254         if (!dev->primary->master)
2255                 return 0;
2256
2257         master_priv = dev->primary->master->driver_priv;
2258         if (!master_priv->sarea_priv)
2259                 return 0;
2260
2261         if (intel_crtc->pipe) {
2262                 master_priv->sarea_priv->pipeB_x = x;
2263                 master_priv->sarea_priv->pipeB_y = y;
2264         } else {
2265                 master_priv->sarea_priv->pipeA_x = x;
2266                 master_priv->sarea_priv->pipeA_y = y;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274         struct drm_device *dev = crtc->dev;
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         u32 dpa_ctl;
2277
2278         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279         dpa_ctl = I915_READ(DP_A);
2280         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282         if (clock < 200000) {
2283                 u32 temp;
2284                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285                 /* workaround for 160Mhz:
2286                    1) program 0x4600c bits 15:0 = 0x8124
2287                    2) program 0x46010 bit 0 = 1
2288                    3) program 0x46034 bit 24 = 1
2289                    4) program 0x64000 bit 14 = 1
2290                    */
2291                 temp = I915_READ(0x4600c);
2292                 temp &= 0xffff0000;
2293                 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295                 temp = I915_READ(0x46010);
2296                 I915_WRITE(0x46010, temp | 1);
2297
2298                 temp = I915_READ(0x46034);
2299                 I915_WRITE(0x46034, temp | (1 << 24));
2300         } else {
2301                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302         }
2303         I915_WRITE(DP_A, dpa_ctl);
2304
2305         POSTING_READ(DP_A);
2306         udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311         struct drm_device *dev = crtc->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314         int pipe = intel_crtc->pipe;
2315         u32 reg, temp;
2316
2317         /* enable normal train */
2318         reg = FDI_TX_CTL(pipe);
2319         temp = I915_READ(reg);
2320         if (IS_IVYBRIDGE(dev)) {
2321                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323         } else {
2324                 temp &= ~FDI_LINK_TRAIN_NONE;
2325                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326         }
2327         I915_WRITE(reg, temp);
2328
2329         reg = FDI_RX_CTL(pipe);
2330         temp = I915_READ(reg);
2331         if (HAS_PCH_CPT(dev)) {
2332                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334         } else {
2335                 temp &= ~FDI_LINK_TRAIN_NONE;
2336                 temp |= FDI_LINK_TRAIN_NONE;
2337         }
2338         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340         /* wait one idle pattern time */
2341         POSTING_READ(reg);
2342         udelay(1000);
2343
2344         /* IVB wants error correction enabled */
2345         if (IS_IVYBRIDGE(dev))
2346                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347                            FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355         flags |= FDI_PHASE_SYNC_OVR(pipe);
2356         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357         flags |= FDI_PHASE_SYNC_EN(pipe);
2358         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359         POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365         struct drm_device *dev = crtc->dev;
2366         struct drm_i915_private *dev_priv = dev->dev_private;
2367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368         int pipe = intel_crtc->pipe;
2369         int plane = intel_crtc->plane;
2370         u32 reg, temp, tries;
2371
2372         /* FDI needs bits from pipe & plane first */
2373         assert_pipe_enabled(dev_priv, pipe);
2374         assert_plane_enabled(dev_priv, plane);
2375
2376         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377            for train result */
2378         reg = FDI_RX_IMR(pipe);
2379         temp = I915_READ(reg);
2380         temp &= ~FDI_RX_SYMBOL_LOCK;
2381         temp &= ~FDI_RX_BIT_LOCK;
2382         I915_WRITE(reg, temp);
2383         I915_READ(reg);
2384         udelay(150);
2385
2386         /* enable CPU FDI TX and PCH FDI RX */
2387         reg = FDI_TX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~(7 << 19);
2390         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395         reg = FDI_RX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         temp &= ~FDI_LINK_TRAIN_NONE;
2398         temp |= FDI_LINK_TRAIN_PATTERN_1;
2399         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401         POSTING_READ(reg);
2402         udelay(150);
2403
2404         /* Ironlake workaround, enable clock pointer after FDI enable*/
2405         if (HAS_PCH_IBX(dev)) {
2406                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408                            FDI_RX_PHASE_SYNC_POINTER_EN);
2409         }
2410
2411         reg = FDI_RX_IIR(pipe);
2412         for (tries = 0; tries < 5; tries++) {
2413                 temp = I915_READ(reg);
2414                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416                 if ((temp & FDI_RX_BIT_LOCK)) {
2417                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2418                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419                         break;
2420                 }
2421         }
2422         if (tries == 5)
2423                 DRM_ERROR("FDI train 1 fail!\n");
2424
2425         /* Train 2 */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_LINK_TRAIN_NONE;
2429         temp |= FDI_LINK_TRAIN_PATTERN_2;
2430         I915_WRITE(reg, temp);
2431
2432         reg = FDI_RX_CTL(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_LINK_TRAIN_NONE;
2435         temp |= FDI_LINK_TRAIN_PATTERN_2;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         reg = FDI_RX_IIR(pipe);
2442         for (tries = 0; tries < 5; tries++) {
2443                 temp = I915_READ(reg);
2444                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446                 if (temp & FDI_RX_SYMBOL_LOCK) {
2447                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2449                         break;
2450                 }
2451         }
2452         if (tries == 5)
2453                 DRM_ERROR("FDI train 2 fail!\n");
2454
2455         DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469         struct drm_device *dev = crtc->dev;
2470         struct drm_i915_private *dev_priv = dev->dev_private;
2471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472         int pipe = intel_crtc->pipe;
2473         u32 reg, temp, i, retry;
2474
2475         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476            for train result */
2477         reg = FDI_RX_IMR(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_RX_SYMBOL_LOCK;
2480         temp &= ~FDI_RX_BIT_LOCK;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494         /* SNB-B */
2495         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498         reg = FDI_RX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         if (HAS_PCH_CPT(dev)) {
2501                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503         } else {
2504                 temp &= ~FDI_LINK_TRAIN_NONE;
2505                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506         }
2507         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509         POSTING_READ(reg);
2510         udelay(150);
2511
2512         if (HAS_PCH_CPT(dev))
2513                 cpt_phase_pointer_enable(dev, pipe);
2514
2515         for (i = 0; i < 4; i++) {
2516                 reg = FDI_TX_CTL(pipe);
2517                 temp = I915_READ(reg);
2518                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519                 temp |= snb_b_fdi_train_param[i];
2520                 I915_WRITE(reg, temp);
2521
2522                 POSTING_READ(reg);
2523                 udelay(500);
2524
2525                 for (retry = 0; retry < 5; retry++) {
2526                         reg = FDI_RX_IIR(pipe);
2527                         temp = I915_READ(reg);
2528                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529                         if (temp & FDI_RX_BIT_LOCK) {
2530                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532                                 break;
2533                         }
2534                         udelay(50);
2535                 }
2536                 if (retry < 5)
2537                         break;
2538         }
2539         if (i == 4)
2540                 DRM_ERROR("FDI train 1 fail!\n");
2541
2542         /* Train 2 */
2543         reg = FDI_TX_CTL(pipe);
2544         temp = I915_READ(reg);
2545         temp &= ~FDI_LINK_TRAIN_NONE;
2546         temp |= FDI_LINK_TRAIN_PATTERN_2;
2547         if (IS_GEN6(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549                 /* SNB-B */
2550                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551         }
2552         I915_WRITE(reg, temp);
2553
2554         reg = FDI_RX_CTL(pipe);
2555         temp = I915_READ(reg);
2556         if (HAS_PCH_CPT(dev)) {
2557                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559         } else {
2560                 temp &= ~FDI_LINK_TRAIN_NONE;
2561                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562         }
2563         I915_WRITE(reg, temp);
2564
2565         POSTING_READ(reg);
2566         udelay(150);
2567
2568         for (i = 0; i < 4; i++) {
2569                 reg = FDI_TX_CTL(pipe);
2570                 temp = I915_READ(reg);
2571                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572                 temp |= snb_b_fdi_train_param[i];
2573                 I915_WRITE(reg, temp);
2574
2575                 POSTING_READ(reg);
2576                 udelay(500);
2577
2578                 for (retry = 0; retry < 5; retry++) {
2579                         reg = FDI_RX_IIR(pipe);
2580                         temp = I915_READ(reg);
2581                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582                         if (temp & FDI_RX_SYMBOL_LOCK) {
2583                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585                                 break;
2586                         }
2587                         udelay(50);
2588                 }
2589                 if (retry < 5)
2590                         break;
2591         }
2592         if (i == 4)
2593                 DRM_ERROR("FDI train 2 fail!\n");
2594
2595         DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601         struct drm_device *dev = crtc->dev;
2602         struct drm_i915_private *dev_priv = dev->dev_private;
2603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604         int pipe = intel_crtc->pipe;
2605         u32 reg, temp, i;
2606
2607         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608            for train result */
2609         reg = FDI_RX_IMR(pipe);
2610         temp = I915_READ(reg);
2611         temp &= ~FDI_RX_SYMBOL_LOCK;
2612         temp &= ~FDI_RX_BIT_LOCK;
2613         I915_WRITE(reg, temp);
2614
2615         POSTING_READ(reg);
2616         udelay(150);
2617
2618         /* enable CPU FDI TX and PCH FDI RX */
2619         reg = FDI_TX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~(7 << 19);
2622         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627         temp |= FDI_COMPOSITE_SYNC;
2628         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630         reg = FDI_RX_CTL(pipe);
2631         temp = I915_READ(reg);
2632         temp &= ~FDI_LINK_TRAIN_AUTO;
2633         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635         temp |= FDI_COMPOSITE_SYNC;
2636         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         if (HAS_PCH_CPT(dev))
2642                 cpt_phase_pointer_enable(dev, pipe);
2643
2644         for (i = 0; i < 4; i++) {
2645                 reg = FDI_TX_CTL(pipe);
2646                 temp = I915_READ(reg);
2647                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648                 temp |= snb_b_fdi_train_param[i];
2649                 I915_WRITE(reg, temp);
2650
2651                 POSTING_READ(reg);
2652                 udelay(500);
2653
2654                 reg = FDI_RX_IIR(pipe);
2655                 temp = I915_READ(reg);
2656                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658                 if (temp & FDI_RX_BIT_LOCK ||
2659                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2662                         break;
2663                 }
2664         }
2665         if (i == 4)
2666                 DRM_ERROR("FDI train 1 fail!\n");
2667
2668         /* Train 2 */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675         I915_WRITE(reg, temp);
2676
2677         reg = FDI_RX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681         I915_WRITE(reg, temp);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_SYMBOL_LOCK) {
2701                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2703                         break;
2704                 }
2705         }
2706         if (i == 4)
2707                 DRM_ERROR("FDI train 2 fail!\n");
2708
2709         DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2713 {
2714         struct drm_device *dev = intel_crtc->base.dev;
2715         struct drm_i915_private *dev_priv = dev->dev_private;
2716         int pipe = intel_crtc->pipe;
2717         u32 reg, temp;
2718
2719         /* Write the TU size bits so error detection works */
2720         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2722
2723         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         temp &= ~((0x7 << 19) | (0x7 << 16));
2727         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731         POSTING_READ(reg);
2732         udelay(200);
2733
2734         /* Switch from Rawclk to PCDclk */
2735         temp = I915_READ(reg);
2736         I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738         POSTING_READ(reg);
2739         udelay(200);
2740
2741         /* On Haswell, the PLL configuration for ports and pipes is handled
2742          * separately, as part of DDI setup */
2743         if (!IS_HASWELL(dev)) {
2744                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745                 reg = FDI_TX_CTL(pipe);
2746                 temp = I915_READ(reg);
2747                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749
2750                         POSTING_READ(reg);
2751                         udelay(100);
2752                 }
2753         }
2754 }
2755
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757 {
2758         struct drm_device *dev = intel_crtc->base.dev;
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         int pipe = intel_crtc->pipe;
2761         u32 reg, temp;
2762
2763         /* Switch from PCDclk to Rawclk */
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768         /* Disable CPU FDI TX PLL */
2769         reg = FDI_TX_CTL(pipe);
2770         temp = I915_READ(reg);
2771         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773         POSTING_READ(reg);
2774         udelay(100);
2775
2776         reg = FDI_RX_CTL(pipe);
2777         temp = I915_READ(reg);
2778         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780         /* Wait for the clocks to turn off. */
2781         POSTING_READ(reg);
2782         udelay(100);
2783 }
2784
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786 {
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794         POSTING_READ(SOUTH_CHICKEN1);
2795 }
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797 {
2798         struct drm_device *dev = crtc->dev;
2799         struct drm_i915_private *dev_priv = dev->dev_private;
2800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801         int pipe = intel_crtc->pipe;
2802         u32 reg, temp;
2803
2804         /* disable CPU FDI tx and PCH FDI rx */
2805         reg = FDI_TX_CTL(pipe);
2806         temp = I915_READ(reg);
2807         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808         POSTING_READ(reg);
2809
2810         reg = FDI_RX_CTL(pipe);
2811         temp = I915_READ(reg);
2812         temp &= ~(0x7 << 16);
2813         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816         POSTING_READ(reg);
2817         udelay(100);
2818
2819         /* Ironlake workaround, disable clock pointer after downing FDI */
2820         if (HAS_PCH_IBX(dev)) {
2821                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823                            I915_READ(FDI_RX_CHICKEN(pipe) &
2824                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825         } else if (HAS_PCH_CPT(dev)) {
2826                 cpt_phase_pointer_disable(dev, pipe);
2827         }
2828
2829         /* still set train pattern 1 */
2830         reg = FDI_TX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~FDI_LINK_TRAIN_NONE;
2833         temp |= FDI_LINK_TRAIN_PATTERN_1;
2834         I915_WRITE(reg, temp);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         if (HAS_PCH_CPT(dev)) {
2839                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841         } else {
2842                 temp &= ~FDI_LINK_TRAIN_NONE;
2843                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844         }
2845         /* BPC in FDI rx is consistent with that in PIPECONF */
2846         temp &= ~(0x07 << 16);
2847         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848         I915_WRITE(reg, temp);
2849
2850         POSTING_READ(reg);
2851         udelay(100);
2852 }
2853
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->dev;
2857
2858         if (crtc->fb == NULL)
2859                 return;
2860
2861         mutex_lock(&dev->struct_mutex);
2862         intel_finish_fb(crtc->fb);
2863         mutex_unlock(&dev->struct_mutex);
2864 }
2865
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 {
2868         struct drm_device *dev = crtc->dev;
2869         struct intel_encoder *intel_encoder;
2870
2871         /*
2872          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873          * must be driven by its own crtc; no sharing is possible.
2874          */
2875         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2876
2877                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878                  * CPU handles all others */
2879                 if (IS_HASWELL(dev)) {
2880                         /* It is still unclear how this will work on PPT, so throw up a warning */
2881                         WARN_ON(!HAS_PCH_LPT(dev));
2882
2883                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885                                 return true;
2886                         } else {
2887                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888                                               intel_encoder->type);
2889                                 return false;
2890                         }
2891                 }
2892
2893                 switch (intel_encoder->type) {
2894                 case INTEL_OUTPUT_EDP:
2895                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2896                                 return false;
2897                         continue;
2898                 }
2899         }
2900
2901         return true;
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907         struct drm_device *dev = crtc->dev;
2908         struct drm_i915_private *dev_priv = dev->dev_private;
2909         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910         u32 temp;
2911
2912         /* It is necessary to ungate the pixclk gate prior to programming
2913          * the divisors, and gate it back when it is done.
2914          */
2915         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917         /* Disable SSCCTL */
2918         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920                                         SBI_SSCCTL_DISABLE);
2921
2922         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923         if (crtc->mode.clock == 20000) {
2924                 auxdiv = 1;
2925                 divsel = 0x41;
2926                 phaseinc = 0x20;
2927         } else {
2928                 /* The iCLK virtual clock root frequency is in MHz,
2929                  * but the crtc->mode.clock in in KHz. To get the divisors,
2930                  * it is necessary to divide one by another, so we
2931                  * convert the virtual clock precision to KHz here for higher
2932                  * precision.
2933                  */
2934                 u32 iclk_virtual_root_freq = 172800 * 1000;
2935                 u32 iclk_pi_range = 64;
2936                 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939                 msb_divisor_value = desired_divisor / iclk_pi_range;
2940                 pi_value = desired_divisor % iclk_pi_range;
2941
2942                 auxdiv = 0;
2943                 divsel = msb_divisor_value - 2;
2944                 phaseinc = pi_value;
2945         }
2946
2947         /* This should not happen with any sane values */
2948         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954                         crtc->mode.clock,
2955                         auxdiv,
2956                         divsel,
2957                         phasedir,
2958                         phaseinc);
2959
2960         /* Program SSCDIVINTPHASE6 */
2961         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969         intel_sbi_write(dev_priv,
2970                         SBI_SSCDIVINTPHASE6,
2971                         temp);
2972
2973         /* Program SSCAUXDIV */
2974         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977         intel_sbi_write(dev_priv,
2978                         SBI_SSCAUXDIV6,
2979                         temp);
2980
2981
2982         /* Enable modulator and associated divider */
2983         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984         temp &= ~SBI_SSCCTL_DISABLE;
2985         intel_sbi_write(dev_priv,
2986                         SBI_SSCCTL6,
2987                         temp);
2988
2989         /* Wait for initialization time */
2990         udelay(24);
2991
2992         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993 }
2994
2995 /*
2996  * Enable PCH resources required for PCH ports:
2997  *   - PCH PLLs
2998  *   - FDI training & RX/TX
2999  *   - update transcoder timings
3000  *   - DP transcoding bits
3001  *   - transcoder
3002  */
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3004 {
3005         struct drm_device *dev = crtc->dev;
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008         int pipe = intel_crtc->pipe;
3009         u32 reg, temp;
3010
3011         assert_transcoder_disabled(dev_priv, pipe);
3012
3013         /* For PCH output, training FDI link */
3014         dev_priv->display.fdi_link_train(crtc);
3015
3016         intel_enable_pch_pll(intel_crtc);
3017
3018         if (HAS_PCH_LPT(dev)) {
3019                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020                 lpt_program_iclkip(crtc);
3021         } else if (HAS_PCH_CPT(dev)) {
3022                 u32 sel;
3023
3024                 temp = I915_READ(PCH_DPLL_SEL);
3025                 switch (pipe) {
3026                 default:
3027                 case 0:
3028                         temp |= TRANSA_DPLL_ENABLE;
3029                         sel = TRANSA_DPLLB_SEL;
3030                         break;
3031                 case 1:
3032                         temp |= TRANSB_DPLL_ENABLE;
3033                         sel = TRANSB_DPLLB_SEL;
3034                         break;
3035                 case 2:
3036                         temp |= TRANSC_DPLL_ENABLE;
3037                         sel = TRANSC_DPLLB_SEL;
3038                         break;
3039                 }
3040                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041                         temp |= sel;
3042                 else
3043                         temp &= ~sel;
3044                 I915_WRITE(PCH_DPLL_SEL, temp);
3045         }
3046
3047         /* set transcoder timing, panel must allow it */
3048         assert_panel_unlocked(dev_priv, pipe);
3049         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3052
3053         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3056         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3057
3058         if (!IS_HASWELL(dev))
3059                 intel_fdi_normal_train(crtc);
3060
3061         /* For PCH DP, enable TRANS_DP_CTL */
3062         if (HAS_PCH_CPT(dev) &&
3063             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066                 reg = TRANS_DP_CTL(pipe);
3067                 temp = I915_READ(reg);
3068                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069                           TRANS_DP_SYNC_MASK |
3070                           TRANS_DP_BPC_MASK);
3071                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072                          TRANS_DP_ENH_FRAMING);
3073                 temp |= bpc << 9; /* same format but at 11:9 */
3074
3075                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3079
3080                 switch (intel_trans_dp_port_sel(crtc)) {
3081                 case PCH_DP_B:
3082                         temp |= TRANS_DP_PORT_SEL_B;
3083                         break;
3084                 case PCH_DP_C:
3085                         temp |= TRANS_DP_PORT_SEL_C;
3086                         break;
3087                 case PCH_DP_D:
3088                         temp |= TRANS_DP_PORT_SEL_D;
3089                         break;
3090                 default:
3091                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092                         temp |= TRANS_DP_PORT_SEL_B;
3093                         break;
3094                 }
3095
3096                 I915_WRITE(reg, temp);
3097         }
3098
3099         intel_enable_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103 {
3104         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106         if (pll == NULL)
3107                 return;
3108
3109         if (pll->refcount == 0) {
3110                 WARN(1, "bad PCH PLL refcount\n");
3111                 return;
3112         }
3113
3114         --pll->refcount;
3115         intel_crtc->pch_pll = NULL;
3116 }
3117
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119 {
3120         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121         struct intel_pch_pll *pll;
3122         int i;
3123
3124         pll = intel_crtc->pch_pll;
3125         if (pll) {
3126                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127                               intel_crtc->base.base.id, pll->pll_reg);
3128                 goto prepare;
3129         }
3130
3131         if (HAS_PCH_IBX(dev_priv->dev)) {
3132                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133                 i = intel_crtc->pipe;
3134                 pll = &dev_priv->pch_plls[i];
3135
3136                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137                               intel_crtc->base.base.id, pll->pll_reg);
3138
3139                 goto found;
3140         }
3141
3142         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143                 pll = &dev_priv->pch_plls[i];
3144
3145                 /* Only want to check enabled timings first */
3146                 if (pll->refcount == 0)
3147                         continue;
3148
3149                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150                     fp == I915_READ(pll->fp0_reg)) {
3151                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152                                       intel_crtc->base.base.id,
3153                                       pll->pll_reg, pll->refcount, pll->active);
3154
3155                         goto found;
3156                 }
3157         }
3158
3159         /* Ok no matching timings, maybe there's a free one? */
3160         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161                 pll = &dev_priv->pch_plls[i];
3162                 if (pll->refcount == 0) {
3163                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164                                       intel_crtc->base.base.id, pll->pll_reg);
3165                         goto found;
3166                 }
3167         }
3168
3169         return NULL;
3170
3171 found:
3172         intel_crtc->pch_pll = pll;
3173         pll->refcount++;
3174         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3177
3178         /* Wait for the clocks to stabilize before rewriting the regs */
3179         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180         POSTING_READ(pll->pll_reg);
3181         udelay(150);
3182
3183         I915_WRITE(pll->fp0_reg, fp);
3184         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3185         pll->on = false;
3186         return pll;
3187 }
3188
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193         u32 temp;
3194
3195         temp = I915_READ(dslreg);
3196         udelay(500);
3197         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198                 /* Without this, mode sets may fail silently on FDI */
3199                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200                 udelay(250);
3201                 I915_WRITE(tc2reg, 0);
3202                 if (wait_for(I915_READ(dslreg) != temp, 5))
3203                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204         }
3205 }
3206
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208 {
3209         struct drm_device *dev = crtc->dev;
3210         struct drm_i915_private *dev_priv = dev->dev_private;
3211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212         struct intel_encoder *encoder;
3213         int pipe = intel_crtc->pipe;
3214         int plane = intel_crtc->plane;
3215         u32 temp;
3216         bool is_pch_port;
3217
3218         WARN_ON(!crtc->enabled);
3219
3220         /* XXX: For compatability with the crtc helper code, call the encoder's
3221          * enable function unconditionally for now. */
3222         if (intel_crtc->active)
3223                 goto encoders;
3224
3225         intel_crtc->active = true;
3226         intel_update_watermarks(dev);
3227
3228         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3229                 temp = I915_READ(PCH_LVDS);
3230                 if ((temp & LVDS_PORT_EN) == 0)
3231                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3232         }
3233
3234         is_pch_port = intel_crtc_driving_pch(crtc);
3235
3236         if (is_pch_port)
3237                 ironlake_fdi_pll_enable(intel_crtc);
3238         else
3239                 ironlake_fdi_disable(crtc);
3240
3241         /* Enable panel fitting for LVDS */
3242         if (dev_priv->pch_pf_size &&
3243             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3244                 /* Force use of hard-coded filter coefficients
3245                  * as some pre-programmed values are broken,
3246                  * e.g. x201.
3247                  */
3248                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3249                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3250                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3251         }
3252
3253         /*
3254          * On ILK+ LUT must be loaded before the pipe is running but with
3255          * clocks enabled
3256          */
3257         intel_crtc_load_lut(crtc);
3258
3259         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3260         intel_enable_plane(dev_priv, plane, pipe);
3261
3262         if (is_pch_port)
3263                 ironlake_pch_enable(crtc);
3264
3265         mutex_lock(&dev->struct_mutex);
3266         intel_update_fbc(dev);
3267         mutex_unlock(&dev->struct_mutex);
3268
3269         intel_crtc_update_cursor(crtc, true);
3270
3271 encoders:
3272         for_each_encoder_on_crtc(dev, crtc, encoder)
3273                 encoder->enable(encoder);
3274
3275         if (HAS_PCH_CPT(dev))
3276                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3277 }
3278
3279 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3280 {
3281         struct drm_device *dev = crtc->dev;
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284         struct intel_encoder *encoder;
3285         int pipe = intel_crtc->pipe;
3286         int plane = intel_crtc->plane;
3287         u32 reg, temp;
3288
3289         /* XXX: For compatability with the crtc helper code, call the encoder's
3290          * disable function unconditionally for now. */
3291         for_each_encoder_on_crtc(dev, crtc, encoder)
3292                 encoder->disable(encoder);
3293
3294         if (!intel_crtc->active)
3295                 return;
3296
3297         intel_crtc_wait_for_pending_flips(crtc);
3298         drm_vblank_off(dev, pipe);
3299         intel_crtc_update_cursor(crtc, false);
3300
3301         intel_disable_plane(dev_priv, plane, pipe);
3302
3303         if (dev_priv->cfb_plane == plane)
3304                 intel_disable_fbc(dev);
3305
3306         intel_disable_pipe(dev_priv, pipe);
3307
3308         /* Disable PF */
3309         I915_WRITE(PF_CTL(pipe), 0);
3310         I915_WRITE(PF_WIN_SZ(pipe), 0);
3311
3312         ironlake_fdi_disable(crtc);
3313
3314         /* This is a horrible layering violation; we should be doing this in
3315          * the connector/encoder ->prepare instead, but we don't always have
3316          * enough information there about the config to know whether it will
3317          * actually be necessary or just cause undesired flicker.
3318          */
3319         intel_disable_pch_ports(dev_priv, pipe);
3320
3321         intel_disable_transcoder(dev_priv, pipe);
3322
3323         if (HAS_PCH_CPT(dev)) {
3324                 /* disable TRANS_DP_CTL */
3325                 reg = TRANS_DP_CTL(pipe);
3326                 temp = I915_READ(reg);
3327                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3328                 temp |= TRANS_DP_PORT_SEL_NONE;
3329                 I915_WRITE(reg, temp);
3330
3331                 /* disable DPLL_SEL */
3332                 temp = I915_READ(PCH_DPLL_SEL);
3333                 switch (pipe) {
3334                 case 0:
3335                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3336                         break;
3337                 case 1:
3338                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3339                         break;
3340                 case 2:
3341                         /* C shares PLL A or B */
3342                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3343                         break;
3344                 default:
3345                         BUG(); /* wtf */
3346                 }
3347                 I915_WRITE(PCH_DPLL_SEL, temp);
3348         }
3349
3350         /* disable PCH DPLL */
3351         intel_disable_pch_pll(intel_crtc);
3352
3353         ironlake_fdi_pll_disable(intel_crtc);
3354
3355         intel_crtc->active = false;
3356         intel_update_watermarks(dev);
3357
3358         mutex_lock(&dev->struct_mutex);
3359         intel_update_fbc(dev);
3360         mutex_unlock(&dev->struct_mutex);
3361 }
3362
3363 static void ironlake_crtc_off(struct drm_crtc *crtc)
3364 {
3365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366         intel_put_pch_pll(intel_crtc);
3367 }
3368
3369 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3370 {
3371         if (!enable && intel_crtc->overlay) {
3372                 struct drm_device *dev = intel_crtc->base.dev;
3373                 struct drm_i915_private *dev_priv = dev->dev_private;
3374
3375                 mutex_lock(&dev->struct_mutex);
3376                 dev_priv->mm.interruptible = false;
3377                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3378                 dev_priv->mm.interruptible = true;
3379                 mutex_unlock(&dev->struct_mutex);
3380         }
3381
3382         /* Let userspace switch the overlay on again. In most cases userspace
3383          * has to recompute where to put it anyway.
3384          */
3385 }
3386
3387 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3388 {
3389         struct drm_device *dev = crtc->dev;
3390         struct drm_i915_private *dev_priv = dev->dev_private;
3391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392         struct intel_encoder *encoder;
3393         int pipe = intel_crtc->pipe;
3394         int plane = intel_crtc->plane;
3395
3396         WARN_ON(!crtc->enabled);
3397
3398         /* XXX: For compatability with the crtc helper code, call the encoder's
3399          * enable function unconditionally for now. */
3400         if (intel_crtc->active)
3401                 goto encoders;
3402
3403         intel_crtc->active = true;
3404         intel_update_watermarks(dev);
3405
3406         intel_enable_pll(dev_priv, pipe);
3407         intel_enable_pipe(dev_priv, pipe, false);
3408         intel_enable_plane(dev_priv, plane, pipe);
3409
3410         intel_crtc_load_lut(crtc);
3411         intel_update_fbc(dev);
3412
3413         /* Give the overlay scaler a chance to enable if it's on this pipe */
3414         intel_crtc_dpms_overlay(intel_crtc, true);
3415         intel_crtc_update_cursor(crtc, true);
3416
3417 encoders:
3418         for_each_encoder_on_crtc(dev, crtc, encoder)
3419                 encoder->enable(encoder);
3420 }
3421
3422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3423 {
3424         struct drm_device *dev = crtc->dev;
3425         struct drm_i915_private *dev_priv = dev->dev_private;
3426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427         struct intel_encoder *encoder;
3428         int pipe = intel_crtc->pipe;
3429         int plane = intel_crtc->plane;
3430
3431         /* XXX: For compatability with the crtc helper code, call the encoder's
3432          * disable function unconditionally for now. */
3433         for_each_encoder_on_crtc(dev, crtc, encoder)
3434                 encoder->disable(encoder);
3435
3436         if (!intel_crtc->active)
3437                 return;
3438
3439         /* Give the overlay scaler a chance to disable if it's on this pipe */
3440         intel_crtc_wait_for_pending_flips(crtc);
3441         drm_vblank_off(dev, pipe);
3442         intel_crtc_dpms_overlay(intel_crtc, false);
3443         intel_crtc_update_cursor(crtc, false);
3444
3445         if (dev_priv->cfb_plane == plane)
3446                 intel_disable_fbc(dev);
3447
3448         intel_disable_plane(dev_priv, plane, pipe);
3449         intel_disable_pipe(dev_priv, pipe);
3450         intel_disable_pll(dev_priv, pipe);
3451
3452         intel_crtc->active = false;
3453         intel_update_fbc(dev);
3454         intel_update_watermarks(dev);
3455 }
3456
3457 static void i9xx_crtc_off(struct drm_crtc *crtc)
3458 {
3459 }
3460
3461 /**
3462  * Sets the power management mode of the pipe and plane.
3463  */
3464 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3465 {
3466         struct drm_device *dev = crtc->dev;
3467         struct drm_i915_private *dev_priv = dev->dev_private;
3468         struct drm_i915_master_private *master_priv;
3469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3470         struct intel_encoder *intel_encoder;
3471         int pipe = intel_crtc->pipe;
3472         bool enabled, enable = false;
3473         int mode;
3474
3475         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3476                 enable |= intel_encoder->connectors_active;
3477
3478         mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
3479
3480         if (intel_crtc->dpms_mode == mode)
3481                 return;
3482
3483         intel_crtc->dpms_mode = mode;
3484
3485         if (enable)
3486                 dev_priv->display.crtc_enable(crtc);
3487         else
3488                 dev_priv->display.crtc_disable(crtc);
3489
3490         if (!dev->primary->master)
3491                 return;
3492
3493         master_priv = dev->primary->master->driver_priv;
3494         if (!master_priv->sarea_priv)
3495                 return;
3496
3497         enabled = crtc->enabled && enable;
3498
3499         switch (pipe) {
3500         case 0:
3501                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3502                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3503                 break;
3504         case 1:
3505                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3506                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3507                 break;
3508         default:
3509                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3510                 break;
3511         }
3512 }
3513
3514 static void intel_crtc_disable(struct drm_crtc *crtc)
3515 {
3516         struct drm_device *dev = crtc->dev;
3517         struct drm_i915_private *dev_priv = dev->dev_private;
3518
3519         /* crtc->disable is only called when we have no encoders, hence this
3520          * will disable the pipe. */
3521         intel_crtc_update_dpms(crtc);
3522         dev_priv->display.off(crtc);
3523
3524         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3525         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3526
3527         if (crtc->fb) {
3528                 mutex_lock(&dev->struct_mutex);
3529                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3530                 mutex_unlock(&dev->struct_mutex);
3531         }
3532 }
3533
3534 void intel_encoder_disable(struct drm_encoder *encoder)
3535 {
3536         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3537
3538         intel_encoder->disable(intel_encoder);
3539 }
3540
3541 void intel_encoder_destroy(struct drm_encoder *encoder)
3542 {
3543         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3544
3545         drm_encoder_cleanup(encoder);
3546         kfree(intel_encoder);
3547 }
3548
3549 /* Simple dpms helper for encodres with just one connector, no cloning and only
3550  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3551  * state of the entire output pipe. */
3552 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3553 {
3554         if (mode == DRM_MODE_DPMS_ON) {
3555                 encoder->connectors_active = true;
3556
3557                 intel_crtc_update_dpms(encoder->base.crtc);
3558         } else {
3559                 encoder->connectors_active = false;
3560
3561                 intel_crtc_update_dpms(encoder->base.crtc);
3562         }
3563 }
3564
3565 /* Even simpler default implementation, if there's really no special case to
3566  * consider. */
3567 void intel_connector_dpms(struct drm_connector *connector, int mode)
3568 {
3569         struct intel_encoder *encoder = intel_attached_encoder(connector);
3570
3571         /* All the simple cases only support two dpms states. */
3572         if (mode != DRM_MODE_DPMS_ON)
3573                 mode = DRM_MODE_DPMS_OFF;
3574
3575         if (mode == connector->dpms)
3576                 return;
3577
3578         connector->dpms = mode;
3579
3580         /* Only need to change hw state when actually enabled */
3581         if (encoder->base.crtc)
3582                 intel_encoder_dpms(encoder, mode);
3583         else
3584                 encoder->connectors_active = false;
3585 }
3586
3587 /* Simple connector->get_hw_state implementation for encoders that support only
3588  * one connector and no cloning and hence the encoder state determines the state
3589  * of the connector. */
3590 bool intel_connector_get_hw_state(struct intel_connector *connector)
3591 {
3592         enum pipe pipe = 0;
3593         struct intel_encoder *encoder = connector->encoder;
3594
3595         return encoder->get_hw_state(encoder, &pipe);
3596 }
3597
3598 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3599                                   const struct drm_display_mode *mode,
3600                                   struct drm_display_mode *adjusted_mode)
3601 {
3602         struct drm_device *dev = crtc->dev;
3603
3604         if (HAS_PCH_SPLIT(dev)) {
3605                 /* FDI link clock is fixed at 2.7G */
3606                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3607                         return false;
3608         }
3609
3610         /* All interlaced capable intel hw wants timings in frames. Note though
3611          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3612          * timings, so we need to be careful not to clobber these.*/
3613         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3614                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3615
3616         return true;
3617 }
3618
3619 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3620 {
3621         return 400000; /* FIXME */
3622 }
3623
3624 static int i945_get_display_clock_speed(struct drm_device *dev)
3625 {
3626         return 400000;
3627 }
3628
3629 static int i915_get_display_clock_speed(struct drm_device *dev)
3630 {
3631         return 333000;
3632 }
3633
3634 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3635 {
3636         return 200000;
3637 }
3638
3639 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3640 {
3641         u16 gcfgc = 0;
3642
3643         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3644
3645         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3646                 return 133000;
3647         else {
3648                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3649                 case GC_DISPLAY_CLOCK_333_MHZ:
3650                         return 333000;
3651                 default:
3652                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3653                         return 190000;
3654                 }
3655         }
3656 }
3657
3658 static int i865_get_display_clock_speed(struct drm_device *dev)
3659 {
3660         return 266000;
3661 }
3662
3663 static int i855_get_display_clock_speed(struct drm_device *dev)
3664 {
3665         u16 hpllcc = 0;
3666         /* Assume that the hardware is in the high speed state.  This
3667          * should be the default.
3668          */
3669         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3670         case GC_CLOCK_133_200:
3671         case GC_CLOCK_100_200:
3672                 return 200000;
3673         case GC_CLOCK_166_250:
3674                 return 250000;
3675         case GC_CLOCK_100_133:
3676                 return 133000;
3677         }
3678
3679         /* Shouldn't happen */
3680         return 0;
3681 }
3682
3683 static int i830_get_display_clock_speed(struct drm_device *dev)
3684 {
3685         return 133000;
3686 }
3687
3688 struct fdi_m_n {
3689         u32        tu;
3690         u32        gmch_m;
3691         u32        gmch_n;
3692         u32        link_m;
3693         u32        link_n;
3694 };
3695
3696 static void
3697 fdi_reduce_ratio(u32 *num, u32 *den)
3698 {
3699         while (*num > 0xffffff || *den > 0xffffff) {
3700                 *num >>= 1;
3701                 *den >>= 1;
3702         }
3703 }
3704
3705 static void
3706 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3707                      int link_clock, struct fdi_m_n *m_n)
3708 {
3709         m_n->tu = 64; /* default size */
3710
3711         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3712         m_n->gmch_m = bits_per_pixel * pixel_clock;
3713         m_n->gmch_n = link_clock * nlanes * 8;
3714         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3715
3716         m_n->link_m = pixel_clock;
3717         m_n->link_n = link_clock;
3718         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3719 }
3720
3721 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3722 {
3723         if (i915_panel_use_ssc >= 0)
3724                 return i915_panel_use_ssc != 0;
3725         return dev_priv->lvds_use_ssc
3726                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3727 }
3728
3729 /**
3730  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3731  * @crtc: CRTC structure
3732  * @mode: requested mode
3733  *
3734  * A pipe may be connected to one or more outputs.  Based on the depth of the
3735  * attached framebuffer, choose a good color depth to use on the pipe.
3736  *
3737  * If possible, match the pipe depth to the fb depth.  In some cases, this
3738  * isn't ideal, because the connected output supports a lesser or restricted
3739  * set of depths.  Resolve that here:
3740  *    LVDS typically supports only 6bpc, so clamp down in that case
3741  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3742  *    Displays may support a restricted set as well, check EDID and clamp as
3743  *      appropriate.
3744  *    DP may want to dither down to 6bpc to fit larger modes
3745  *
3746  * RETURNS:
3747  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3748  * true if they don't match).
3749  */
3750 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3751                                          unsigned int *pipe_bpp,
3752                                          struct drm_display_mode *mode)
3753 {
3754         struct drm_device *dev = crtc->dev;
3755         struct drm_i915_private *dev_priv = dev->dev_private;
3756         struct drm_connector *connector;
3757         struct intel_encoder *intel_encoder;
3758         unsigned int display_bpc = UINT_MAX, bpc;
3759
3760         /* Walk the encoders & connectors on this crtc, get min bpc */
3761         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3762
3763                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3764                         unsigned int lvds_bpc;
3765
3766                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3767                             LVDS_A3_POWER_UP)
3768                                 lvds_bpc = 8;
3769                         else
3770                                 lvds_bpc = 6;
3771
3772                         if (lvds_bpc < display_bpc) {
3773                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3774                                 display_bpc = lvds_bpc;
3775                         }
3776                         continue;
3777                 }
3778
3779                 /* Not one of the known troublemakers, check the EDID */
3780                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3781                                     head) {
3782                         if (connector->encoder != &intel_encoder->base)
3783                                 continue;
3784
3785                         /* Don't use an invalid EDID bpc value */
3786                         if (connector->display_info.bpc &&
3787                             connector->display_info.bpc < display_bpc) {
3788                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3789                                 display_bpc = connector->display_info.bpc;
3790                         }
3791                 }
3792
3793                 /*
3794                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3795                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3796                  */
3797                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3798                         if (display_bpc > 8 && display_bpc < 12) {
3799                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3800                                 display_bpc = 12;
3801                         } else {
3802                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3803                                 display_bpc = 8;
3804                         }
3805                 }
3806         }
3807
3808         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3809                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3810                 display_bpc = 6;
3811         }
3812
3813         /*
3814          * We could just drive the pipe at the highest bpc all the time and
3815          * enable dithering as needed, but that costs bandwidth.  So choose
3816          * the minimum value that expresses the full color range of the fb but
3817          * also stays within the max display bpc discovered above.
3818          */
3819
3820         switch (crtc->fb->depth) {
3821         case 8:
3822                 bpc = 8; /* since we go through a colormap */
3823                 break;
3824         case 15:
3825         case 16:
3826                 bpc = 6; /* min is 18bpp */
3827                 break;
3828         case 24:
3829                 bpc = 8;
3830                 break;
3831         case 30:
3832                 bpc = 10;
3833                 break;
3834         case 48:
3835                 bpc = 12;
3836                 break;
3837         default:
3838                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3839                 bpc = min((unsigned int)8, display_bpc);
3840                 break;
3841         }
3842
3843         display_bpc = min(display_bpc, bpc);
3844
3845         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3846                       bpc, display_bpc);
3847
3848         *pipe_bpp = display_bpc * 3;
3849
3850         return display_bpc != bpc;
3851 }
3852
3853 static int vlv_get_refclk(struct drm_crtc *crtc)
3854 {
3855         struct drm_device *dev = crtc->dev;
3856         struct drm_i915_private *dev_priv = dev->dev_private;
3857         int refclk = 27000; /* for DP & HDMI */
3858
3859         return 100000; /* only one validated so far */
3860
3861         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3862                 refclk = 96000;
3863         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3864                 if (intel_panel_use_ssc(dev_priv))
3865                         refclk = 100000;
3866                 else
3867                         refclk = 96000;
3868         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3869                 refclk = 100000;
3870         }
3871
3872         return refclk;
3873 }
3874
3875 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3876 {
3877         struct drm_device *dev = crtc->dev;
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879         int refclk;
3880
3881         if (IS_VALLEYVIEW(dev)) {
3882                 refclk = vlv_get_refclk(crtc);
3883         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3884             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3885                 refclk = dev_priv->lvds_ssc_freq * 1000;
3886                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3887                               refclk / 1000);
3888         } else if (!IS_GEN2(dev)) {
3889                 refclk = 96000;
3890         } else {
3891                 refclk = 48000;
3892         }
3893
3894         return refclk;
3895 }
3896
3897 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3898                                       intel_clock_t *clock)
3899 {
3900         /* SDVO TV has fixed PLL values depend on its clock range,
3901            this mirrors vbios setting. */
3902         if (adjusted_mode->clock >= 100000
3903             && adjusted_mode->clock < 140500) {
3904                 clock->p1 = 2;
3905                 clock->p2 = 10;
3906                 clock->n = 3;
3907                 clock->m1 = 16;
3908                 clock->m2 = 8;
3909         } else if (adjusted_mode->clock >= 140500
3910                    && adjusted_mode->clock <= 200000) {
3911                 clock->p1 = 1;
3912                 clock->p2 = 10;
3913                 clock->n = 6;
3914                 clock->m1 = 12;
3915                 clock->m2 = 8;
3916         }
3917 }
3918
3919 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3920                                      intel_clock_t *clock,
3921                                      intel_clock_t *reduced_clock)
3922 {
3923         struct drm_device *dev = crtc->dev;
3924         struct drm_i915_private *dev_priv = dev->dev_private;
3925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3926         int pipe = intel_crtc->pipe;
3927         u32 fp, fp2 = 0;
3928
3929         if (IS_PINEVIEW(dev)) {
3930                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3931                 if (reduced_clock)
3932                         fp2 = (1 << reduced_clock->n) << 16 |
3933                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3934         } else {
3935                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3936                 if (reduced_clock)
3937                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3938                                 reduced_clock->m2;
3939         }
3940
3941         I915_WRITE(FP0(pipe), fp);
3942
3943         intel_crtc->lowfreq_avail = false;
3944         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3945             reduced_clock && i915_powersave) {
3946                 I915_WRITE(FP1(pipe), fp2);
3947                 intel_crtc->lowfreq_avail = true;
3948         } else {
3949                 I915_WRITE(FP1(pipe), fp);
3950         }
3951 }
3952
3953 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3954                               struct drm_display_mode *adjusted_mode)
3955 {
3956         struct drm_device *dev = crtc->dev;
3957         struct drm_i915_private *dev_priv = dev->dev_private;
3958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3959         int pipe = intel_crtc->pipe;
3960         u32 temp;
3961
3962         temp = I915_READ(LVDS);
3963         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3964         if (pipe == 1) {
3965                 temp |= LVDS_PIPEB_SELECT;
3966         } else {
3967                 temp &= ~LVDS_PIPEB_SELECT;
3968         }
3969         /* set the corresponsding LVDS_BORDER bit */
3970         temp |= dev_priv->lvds_border_bits;
3971         /* Set the B0-B3 data pairs corresponding to whether we're going to
3972          * set the DPLLs for dual-channel mode or not.
3973          */
3974         if (clock->p2 == 7)
3975                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3976         else
3977                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3978
3979         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3980          * appropriately here, but we need to look more thoroughly into how
3981          * panels behave in the two modes.
3982          */
3983         /* set the dithering flag on LVDS as needed */
3984         if (INTEL_INFO(dev)->gen >= 4) {
3985                 if (dev_priv->lvds_dither)
3986                         temp |= LVDS_ENABLE_DITHER;
3987                 else
3988                         temp &= ~LVDS_ENABLE_DITHER;
3989         }
3990         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3991         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3992                 temp |= LVDS_HSYNC_POLARITY;
3993         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3994                 temp |= LVDS_VSYNC_POLARITY;
3995         I915_WRITE(LVDS, temp);
3996 }
3997
3998 static void vlv_update_pll(struct drm_crtc *crtc,
3999                            struct drm_display_mode *mode,
4000                            struct drm_display_mode *adjusted_mode,
4001                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4002                            int refclk, int num_connectors)
4003 {
4004         struct drm_device *dev = crtc->dev;
4005         struct drm_i915_private *dev_priv = dev->dev_private;
4006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4007         int pipe = intel_crtc->pipe;
4008         u32 dpll, mdiv, pdiv;
4009         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4010         bool is_hdmi;
4011
4012         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4013
4014         bestn = clock->n;
4015         bestm1 = clock->m1;
4016         bestm2 = clock->m2;
4017         bestp1 = clock->p1;
4018         bestp2 = clock->p2;
4019
4020         /* Enable DPIO clock input */
4021         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4022                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4023         I915_WRITE(DPLL(pipe), dpll);
4024         POSTING_READ(DPLL(pipe));
4025
4026         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4027         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4028         mdiv |= ((bestn << DPIO_N_SHIFT));
4029         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4030         mdiv |= (1 << DPIO_K_SHIFT);
4031         mdiv |= DPIO_ENABLE_CALIBRATION;
4032         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4033
4034         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4035
4036         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4037                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4038                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4039         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4040
4041         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4042
4043         dpll |= DPLL_VCO_ENABLE;
4044         I915_WRITE(DPLL(pipe), dpll);
4045         POSTING_READ(DPLL(pipe));
4046         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4047                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4048
4049         if (is_hdmi) {
4050                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4051
4052                 if (temp > 1)
4053                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4054                 else
4055                         temp = 0;
4056
4057                 I915_WRITE(DPLL_MD(pipe), temp);
4058                 POSTING_READ(DPLL_MD(pipe));
4059         }
4060
4061         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4062 }
4063
4064 static void i9xx_update_pll(struct drm_crtc *crtc,
4065                             struct drm_display_mode *mode,
4066                             struct drm_display_mode *adjusted_mode,
4067                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4068                             int num_connectors)
4069 {
4070         struct drm_device *dev = crtc->dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4073         int pipe = intel_crtc->pipe;
4074         u32 dpll;
4075         bool is_sdvo;
4076
4077         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4078                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4079
4080         dpll = DPLL_VGA_MODE_DIS;
4081
4082         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4083                 dpll |= DPLLB_MODE_LVDS;
4084         else
4085                 dpll |= DPLLB_MODE_DAC_SERIAL;
4086         if (is_sdvo) {
4087                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4088                 if (pixel_multiplier > 1) {
4089                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4090                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4091                 }
4092                 dpll |= DPLL_DVO_HIGH_SPEED;
4093         }
4094         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4095                 dpll |= DPLL_DVO_HIGH_SPEED;
4096
4097         /* compute bitmask from p1 value */
4098         if (IS_PINEVIEW(dev))
4099                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4100         else {
4101                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4102                 if (IS_G4X(dev) && reduced_clock)
4103                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4104         }
4105         switch (clock->p2) {
4106         case 5:
4107                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4108                 break;
4109         case 7:
4110                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4111                 break;
4112         case 10:
4113                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4114                 break;
4115         case 14:
4116                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4117                 break;
4118         }
4119         if (INTEL_INFO(dev)->gen >= 4)
4120                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4121
4122         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4123                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4124         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4125                 /* XXX: just matching BIOS for now */
4126                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4127                 dpll |= 3;
4128         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4129                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4130                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4131         else
4132                 dpll |= PLL_REF_INPUT_DREFCLK;
4133
4134         dpll |= DPLL_VCO_ENABLE;
4135         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4136         POSTING_READ(DPLL(pipe));
4137         udelay(150);
4138
4139         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4140          * This is an exception to the general rule that mode_set doesn't turn
4141          * things on.
4142          */
4143         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4144                 intel_update_lvds(crtc, clock, adjusted_mode);
4145
4146         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4147                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4148
4149         I915_WRITE(DPLL(pipe), dpll);
4150
4151         /* Wait for the clocks to stabilize. */
4152         POSTING_READ(DPLL(pipe));
4153         udelay(150);
4154
4155         if (INTEL_INFO(dev)->gen >= 4) {
4156                 u32 temp = 0;
4157                 if (is_sdvo) {
4158                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4159                         if (temp > 1)
4160                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4161                         else
4162                                 temp = 0;
4163                 }
4164                 I915_WRITE(DPLL_MD(pipe), temp);
4165         } else {
4166                 /* The pixel multiplier can only be updated once the
4167                  * DPLL is enabled and the clocks are stable.
4168                  *
4169                  * So write it again.
4170                  */
4171                 I915_WRITE(DPLL(pipe), dpll);
4172         }
4173 }
4174
4175 static void i8xx_update_pll(struct drm_crtc *crtc,
4176                             struct drm_display_mode *adjusted_mode,
4177                             intel_clock_t *clock,
4178                             int num_connectors)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct drm_i915_private *dev_priv = dev->dev_private;
4182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183         int pipe = intel_crtc->pipe;
4184         u32 dpll;
4185
4186         dpll = DPLL_VGA_MODE_DIS;
4187
4188         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4189                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4190         } else {
4191                 if (clock->p1 == 2)
4192                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4193                 else
4194                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4195                 if (clock->p2 == 4)
4196                         dpll |= PLL_P2_DIVIDE_BY_4;
4197         }
4198
4199         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4200                 /* XXX: just matching BIOS for now */
4201                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4202                 dpll |= 3;
4203         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4204                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4205                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4206         else
4207                 dpll |= PLL_REF_INPUT_DREFCLK;
4208
4209         dpll |= DPLL_VCO_ENABLE;
4210         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4211         POSTING_READ(DPLL(pipe));
4212         udelay(150);
4213
4214         I915_WRITE(DPLL(pipe), dpll);
4215
4216         /* Wait for the clocks to stabilize. */
4217         POSTING_READ(DPLL(pipe));
4218         udelay(150);
4219
4220         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4221          * This is an exception to the general rule that mode_set doesn't turn
4222          * things on.
4223          */
4224         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4225                 intel_update_lvds(crtc, clock, adjusted_mode);
4226
4227         /* The pixel multiplier can only be updated once the
4228          * DPLL is enabled and the clocks are stable.
4229          *
4230          * So write it again.
4231          */
4232         I915_WRITE(DPLL(pipe), dpll);
4233 }
4234
4235 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4236                               struct drm_display_mode *mode,
4237                               struct drm_display_mode *adjusted_mode,
4238                               int x, int y,
4239                               struct drm_framebuffer *old_fb)
4240 {
4241         struct drm_device *dev = crtc->dev;
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244         int pipe = intel_crtc->pipe;
4245         int plane = intel_crtc->plane;
4246         int refclk, num_connectors = 0;
4247         intel_clock_t clock, reduced_clock;
4248         u32 dspcntr, pipeconf, vsyncshift;
4249         bool ok, has_reduced_clock = false, is_sdvo = false;
4250         bool is_lvds = false, is_tv = false, is_dp = false;
4251         struct intel_encoder *encoder;
4252         const intel_limit_t *limit;
4253         int ret;
4254
4255         for_each_encoder_on_crtc(dev, crtc, encoder) {
4256                 switch (encoder->type) {
4257                 case INTEL_OUTPUT_LVDS:
4258                         is_lvds = true;
4259                         break;
4260                 case INTEL_OUTPUT_SDVO:
4261                 case INTEL_OUTPUT_HDMI:
4262                         is_sdvo = true;
4263                         if (encoder->needs_tv_clock)
4264                                 is_tv = true;
4265                         break;
4266                 case INTEL_OUTPUT_TVOUT:
4267                         is_tv = true;
4268                         break;
4269                 case INTEL_OUTPUT_DISPLAYPORT:
4270                         is_dp = true;
4271                         break;
4272                 }
4273
4274                 num_connectors++;
4275         }
4276
4277         refclk = i9xx_get_refclk(crtc, num_connectors);
4278
4279         /*
4280          * Returns a set of divisors for the desired target clock with the given
4281          * refclk, or FALSE.  The returned values represent the clock equation:
4282          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4283          */
4284         limit = intel_limit(crtc, refclk);
4285         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4286                              &clock);
4287         if (!ok) {
4288                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4289                 return -EINVAL;
4290         }
4291
4292         /* Ensure that the cursor is valid for the new mode before changing... */
4293         intel_crtc_update_cursor(crtc, true);
4294
4295         if (is_lvds && dev_priv->lvds_downclock_avail) {
4296                 /*
4297                  * Ensure we match the reduced clock's P to the target clock.
4298                  * If the clocks don't match, we can't switch the display clock
4299                  * by using the FP0/FP1. In such case we will disable the LVDS
4300                  * downclock feature.
4301                 */
4302                 has_reduced_clock = limit->find_pll(limit, crtc,
4303                                                     dev_priv->lvds_downclock,
4304                                                     refclk,
4305                                                     &clock,
4306                                                     &reduced_clock);
4307         }
4308
4309         if (is_sdvo && is_tv)
4310                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4311
4312         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4313                                  &reduced_clock : NULL);
4314
4315         if (IS_GEN2(dev))
4316                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4317         else if (IS_VALLEYVIEW(dev))
4318                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4319                                refclk, num_connectors);
4320         else
4321                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4322                                 has_reduced_clock ? &reduced_clock : NULL,
4323                                 num_connectors);
4324
4325         /* setup pipeconf */
4326         pipeconf = I915_READ(PIPECONF(pipe));
4327
4328         /* Set up the display plane register */
4329         dspcntr = DISPPLANE_GAMMA_ENABLE;
4330
4331         if (pipe == 0)
4332                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4333         else
4334                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4335
4336         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4337                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4338                  * core speed.
4339                  *
4340                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4341                  * pipe == 0 check?
4342                  */
4343                 if (mode->clock >
4344                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4345                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4346                 else
4347                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4348         }
4349
4350         /* default to 8bpc */
4351         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4352         if (is_dp) {
4353                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4354                         pipeconf |= PIPECONF_BPP_6 |
4355                                     PIPECONF_DITHER_EN |
4356                                     PIPECONF_DITHER_TYPE_SP;
4357                 }
4358         }
4359
4360         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4361         drm_mode_debug_printmodeline(mode);
4362
4363         if (HAS_PIPE_CXSR(dev)) {
4364                 if (intel_crtc->lowfreq_avail) {
4365                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4366                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4367                 } else {
4368                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4369                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4370                 }
4371         }
4372
4373         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4374         if (!IS_GEN2(dev) &&
4375             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4376                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4377                 /* the chip adds 2 halflines automatically */
4378                 adjusted_mode->crtc_vtotal -= 1;
4379                 adjusted_mode->crtc_vblank_end -= 1;
4380                 vsyncshift = adjusted_mode->crtc_hsync_start
4381                              - adjusted_mode->crtc_htotal/2;
4382         } else {
4383                 pipeconf |= PIPECONF_PROGRESSIVE;
4384                 vsyncshift = 0;
4385         }
4386
4387         if (!IS_GEN3(dev))
4388                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4389
4390         I915_WRITE(HTOTAL(pipe),
4391                    (adjusted_mode->crtc_hdisplay - 1) |
4392                    ((adjusted_mode->crtc_htotal - 1) << 16));
4393         I915_WRITE(HBLANK(pipe),
4394                    (adjusted_mode->crtc_hblank_start - 1) |
4395                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4396         I915_WRITE(HSYNC(pipe),
4397                    (adjusted_mode->crtc_hsync_start - 1) |
4398                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4399
4400         I915_WRITE(VTOTAL(pipe),
4401                    (adjusted_mode->crtc_vdisplay - 1) |
4402                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4403         I915_WRITE(VBLANK(pipe),
4404                    (adjusted_mode->crtc_vblank_start - 1) |
4405                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4406         I915_WRITE(VSYNC(pipe),
4407                    (adjusted_mode->crtc_vsync_start - 1) |
4408                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4409
4410         /* pipesrc and dspsize control the size that is scaled from,
4411          * which should always be the user's requested size.
4412          */
4413         I915_WRITE(DSPSIZE(plane),
4414                    ((mode->vdisplay - 1) << 16) |
4415                    (mode->hdisplay - 1));
4416         I915_WRITE(DSPPOS(plane), 0);
4417         I915_WRITE(PIPESRC(pipe),
4418                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4419
4420         I915_WRITE(PIPECONF(pipe), pipeconf);
4421         POSTING_READ(PIPECONF(pipe));
4422         intel_enable_pipe(dev_priv, pipe, false);
4423
4424         intel_wait_for_vblank(dev, pipe);
4425
4426         I915_WRITE(DSPCNTR(plane), dspcntr);
4427         POSTING_READ(DSPCNTR(plane));
4428
4429         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4430
4431         intel_update_watermarks(dev);
4432
4433         return ret;
4434 }
4435
4436 /*
4437  * Initialize reference clocks when the driver loads
4438  */
4439 void ironlake_init_pch_refclk(struct drm_device *dev)
4440 {
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         struct drm_mode_config *mode_config = &dev->mode_config;
4443         struct intel_encoder *encoder;
4444         u32 temp;
4445         bool has_lvds = false;
4446         bool has_cpu_edp = false;
4447         bool has_pch_edp = false;
4448         bool has_panel = false;
4449         bool has_ck505 = false;
4450         bool can_ssc = false;
4451
4452         /* We need to take the global config into account */
4453         list_for_each_entry(encoder, &mode_config->encoder_list,
4454                             base.head) {
4455                 switch (encoder->type) {
4456                 case INTEL_OUTPUT_LVDS:
4457                         has_panel = true;
4458                         has_lvds = true;
4459                         break;
4460                 case INTEL_OUTPUT_EDP:
4461                         has_panel = true;
4462                         if (intel_encoder_is_pch_edp(&encoder->base))
4463                                 has_pch_edp = true;
4464                         else
4465                                 has_cpu_edp = true;
4466                         break;
4467                 }
4468         }
4469
4470         if (HAS_PCH_IBX(dev)) {
4471                 has_ck505 = dev_priv->display_clock_mode;
4472                 can_ssc = has_ck505;
4473         } else {
4474                 has_ck505 = false;
4475                 can_ssc = true;
4476         }
4477
4478         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4479                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4480                       has_ck505);
4481
4482         /* Ironlake: try to setup display ref clock before DPLL
4483          * enabling. This is only under driver's control after
4484          * PCH B stepping, previous chipset stepping should be
4485          * ignoring this setting.
4486          */
4487         temp = I915_READ(PCH_DREF_CONTROL);
4488         /* Always enable nonspread source */
4489         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4490
4491         if (has_ck505)
4492                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4493         else
4494                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4495
4496         if (has_panel) {
4497                 temp &= ~DREF_SSC_SOURCE_MASK;
4498                 temp |= DREF_SSC_SOURCE_ENABLE;
4499
4500                 /* SSC must be turned on before enabling the CPU output  */
4501                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4502                         DRM_DEBUG_KMS("Using SSC on panel\n");
4503                         temp |= DREF_SSC1_ENABLE;
4504                 } else
4505                         temp &= ~DREF_SSC1_ENABLE;
4506
4507                 /* Get SSC going before enabling the outputs */
4508                 I915_WRITE(PCH_DREF_CONTROL, temp);
4509                 POSTING_READ(PCH_DREF_CONTROL);
4510                 udelay(200);
4511
4512                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4513
4514                 /* Enable CPU source on CPU attached eDP */
4515                 if (has_cpu_edp) {
4516                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4517                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4518                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4519                         }
4520                         else
4521                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4522                 } else
4523                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4524
4525                 I915_WRITE(PCH_DREF_CONTROL, temp);
4526                 POSTING_READ(PCH_DREF_CONTROL);
4527                 udelay(200);
4528         } else {
4529                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4530
4531                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4532
4533                 /* Turn off CPU output */
4534                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4535
4536                 I915_WRITE(PCH_DREF_CONTROL, temp);
4537                 POSTING_READ(PCH_DREF_CONTROL);
4538                 udelay(200);
4539
4540                 /* Turn off the SSC source */
4541                 temp &= ~DREF_SSC_SOURCE_MASK;
4542                 temp |= DREF_SSC_SOURCE_DISABLE;
4543
4544                 /* Turn off SSC1 */
4545                 temp &= ~ DREF_SSC1_ENABLE;
4546
4547                 I915_WRITE(PCH_DREF_CONTROL, temp);
4548                 POSTING_READ(PCH_DREF_CONTROL);
4549                 udelay(200);
4550         }
4551 }
4552
4553 static int ironlake_get_refclk(struct drm_crtc *crtc)
4554 {
4555         struct drm_device *dev = crtc->dev;
4556         struct drm_i915_private *dev_priv = dev->dev_private;
4557         struct intel_encoder *encoder;
4558         struct intel_encoder *edp_encoder = NULL;
4559         int num_connectors = 0;
4560         bool is_lvds = false;
4561
4562         for_each_encoder_on_crtc(dev, crtc, encoder) {
4563                 switch (encoder->type) {
4564                 case INTEL_OUTPUT_LVDS:
4565                         is_lvds = true;
4566                         break;
4567                 case INTEL_OUTPUT_EDP:
4568                         edp_encoder = encoder;
4569                         break;
4570                 }
4571                 num_connectors++;
4572         }
4573
4574         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4575                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4576                               dev_priv->lvds_ssc_freq);
4577                 return dev_priv->lvds_ssc_freq * 1000;
4578         }
4579
4580         return 120000;
4581 }
4582
4583 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4584                                   struct drm_display_mode *mode,
4585                                   struct drm_display_mode *adjusted_mode,
4586                                   int x, int y,
4587                                   struct drm_framebuffer *old_fb)
4588 {
4589         struct drm_device *dev = crtc->dev;
4590         struct drm_i915_private *dev_priv = dev->dev_private;
4591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592         int pipe = intel_crtc->pipe;
4593         int plane = intel_crtc->plane;
4594         int refclk, num_connectors = 0;
4595         intel_clock_t clock, reduced_clock;
4596         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4597         bool ok, has_reduced_clock = false, is_sdvo = false;
4598         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4599         struct intel_encoder *encoder, *edp_encoder = NULL;
4600         const intel_limit_t *limit;
4601         int ret;
4602         struct fdi_m_n m_n = {0};
4603         u32 temp;
4604         int target_clock, pixel_multiplier, lane, link_bw, factor;
4605         unsigned int pipe_bpp;
4606         bool dither;
4607         bool is_cpu_edp = false, is_pch_edp = false;
4608
4609         for_each_encoder_on_crtc(dev, crtc, encoder) {
4610                 switch (encoder->type) {
4611                 case INTEL_OUTPUT_LVDS:
4612                         is_lvds = true;
4613                         break;
4614                 case INTEL_OUTPUT_SDVO:
4615                 case INTEL_OUTPUT_HDMI:
4616                         is_sdvo = true;
4617                         if (encoder->needs_tv_clock)
4618                                 is_tv = true;
4619                         break;
4620                 case INTEL_OUTPUT_TVOUT:
4621                         is_tv = true;
4622                         break;
4623                 case INTEL_OUTPUT_ANALOG:
4624                         is_crt = true;
4625                         break;
4626                 case INTEL_OUTPUT_DISPLAYPORT:
4627                         is_dp = true;
4628                         break;
4629                 case INTEL_OUTPUT_EDP:
4630                         is_dp = true;
4631                         if (intel_encoder_is_pch_edp(&encoder->base))
4632                                 is_pch_edp = true;
4633                         else
4634                                 is_cpu_edp = true;
4635                         edp_encoder = encoder;
4636                         break;
4637                 }
4638
4639                 num_connectors++;
4640         }
4641
4642         refclk = ironlake_get_refclk(crtc);
4643
4644         /*
4645          * Returns a set of divisors for the desired target clock with the given
4646          * refclk, or FALSE.  The returned values represent the clock equation:
4647          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4648          */
4649         limit = intel_limit(crtc, refclk);
4650         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4651                              &clock);
4652         if (!ok) {
4653                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4654                 return -EINVAL;
4655         }
4656
4657         /* Ensure that the cursor is valid for the new mode before changing... */
4658         intel_crtc_update_cursor(crtc, true);
4659
4660         if (is_lvds && dev_priv->lvds_downclock_avail) {
4661                 /*
4662                  * Ensure we match the reduced clock's P to the target clock.
4663                  * If the clocks don't match, we can't switch the display clock
4664                  * by using the FP0/FP1. In such case we will disable the LVDS
4665                  * downclock feature.
4666                 */
4667                 has_reduced_clock = limit->find_pll(limit, crtc,
4668                                                     dev_priv->lvds_downclock,
4669                                                     refclk,
4670                                                     &clock,
4671                                                     &reduced_clock);
4672         }
4673
4674         if (is_sdvo && is_tv)
4675                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4676
4677
4678         /* FDI link */
4679         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4680         lane = 0;
4681         /* CPU eDP doesn't require FDI link, so just set DP M/N
4682            according to current link config */
4683         if (is_cpu_edp) {
4684                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4685         } else {
4686                 /* FDI is a binary signal running at ~2.7GHz, encoding
4687                  * each output octet as 10 bits. The actual frequency
4688                  * is stored as a divider into a 100MHz clock, and the
4689                  * mode pixel clock is stored in units of 1KHz.
4690                  * Hence the bw of each lane in terms of the mode signal
4691                  * is:
4692                  */
4693                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4694         }
4695
4696         /* [e]DP over FDI requires target mode clock instead of link clock. */
4697         if (edp_encoder)
4698                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4699         else if (is_dp)
4700                 target_clock = mode->clock;
4701         else
4702                 target_clock = adjusted_mode->clock;
4703
4704         /* determine panel color depth */
4705         temp = I915_READ(PIPECONF(pipe));
4706         temp &= ~PIPE_BPC_MASK;
4707         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4708         switch (pipe_bpp) {
4709         case 18:
4710                 temp |= PIPE_6BPC;
4711                 break;
4712         case 24:
4713                 temp |= PIPE_8BPC;
4714                 break;
4715         case 30:
4716                 temp |= PIPE_10BPC;
4717                 break;
4718         case 36:
4719                 temp |= PIPE_12BPC;
4720                 break;
4721         default:
4722                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4723                         pipe_bpp);
4724                 temp |= PIPE_8BPC;
4725                 pipe_bpp = 24;
4726                 break;
4727         }
4728
4729         intel_crtc->bpp = pipe_bpp;
4730         I915_WRITE(PIPECONF(pipe), temp);
4731
4732         if (!lane) {
4733                 /*
4734                  * Account for spread spectrum to avoid
4735                  * oversubscribing the link. Max center spread
4736                  * is 2.5%; use 5% for safety's sake.
4737                  */
4738                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4739                 lane = bps / (link_bw * 8) + 1;
4740         }
4741
4742         intel_crtc->fdi_lanes = lane;
4743
4744         if (pixel_multiplier > 1)
4745                 link_bw *= pixel_multiplier;
4746         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4747                              &m_n);
4748
4749         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4750         if (has_reduced_clock)
4751                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4752                         reduced_clock.m2;
4753
4754         /* Enable autotuning of the PLL clock (if permissible) */
4755         factor = 21;
4756         if (is_lvds) {
4757                 if ((intel_panel_use_ssc(dev_priv) &&
4758                      dev_priv->lvds_ssc_freq == 100) ||
4759                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4760                         factor = 25;
4761         } else if (is_sdvo && is_tv)
4762                 factor = 20;
4763
4764         if (clock.m < factor * clock.n)
4765                 fp |= FP_CB_TUNE;
4766
4767         dpll = 0;
4768
4769         if (is_lvds)
4770                 dpll |= DPLLB_MODE_LVDS;
4771         else
4772                 dpll |= DPLLB_MODE_DAC_SERIAL;
4773         if (is_sdvo) {
4774                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4775                 if (pixel_multiplier > 1) {
4776                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4777                 }
4778                 dpll |= DPLL_DVO_HIGH_SPEED;
4779         }
4780         if (is_dp && !is_cpu_edp)
4781                 dpll |= DPLL_DVO_HIGH_SPEED;
4782
4783         /* compute bitmask from p1 value */
4784         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4785         /* also FPA1 */
4786         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4787
4788         switch (clock.p2) {
4789         case 5:
4790                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4791                 break;
4792         case 7:
4793                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4794                 break;
4795         case 10:
4796                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4797                 break;
4798         case 14:
4799                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4800                 break;
4801         }
4802
4803         if (is_sdvo && is_tv)
4804                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4805         else if (is_tv)
4806                 /* XXX: just matching BIOS for now */
4807                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4808                 dpll |= 3;
4809         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4810                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4811         else
4812                 dpll |= PLL_REF_INPUT_DREFCLK;
4813
4814         /* setup pipeconf */
4815         pipeconf = I915_READ(PIPECONF(pipe));
4816
4817         /* Set up the display plane register */
4818         dspcntr = DISPPLANE_GAMMA_ENABLE;
4819
4820         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4821         drm_mode_debug_printmodeline(mode);
4822
4823         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4824          * pre-Haswell/LPT generation */
4825         if (HAS_PCH_LPT(dev)) {
4826                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4827                                 pipe);
4828         } else if (!is_cpu_edp) {
4829                 struct intel_pch_pll *pll;
4830
4831                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4832                 if (pll == NULL) {
4833                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4834                                          pipe);
4835                         return -EINVAL;
4836                 }
4837         } else
4838                 intel_put_pch_pll(intel_crtc);
4839
4840         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4841          * This is an exception to the general rule that mode_set doesn't turn
4842          * things on.
4843          */
4844         if (is_lvds) {
4845                 temp = I915_READ(PCH_LVDS);
4846                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4847                 if (HAS_PCH_CPT(dev)) {
4848                         temp &= ~PORT_TRANS_SEL_MASK;
4849                         temp |= PORT_TRANS_SEL_CPT(pipe);
4850                 } else {
4851                         if (pipe == 1)
4852                                 temp |= LVDS_PIPEB_SELECT;
4853                         else
4854                                 temp &= ~LVDS_PIPEB_SELECT;
4855                 }
4856
4857                 /* set the corresponsding LVDS_BORDER bit */
4858                 temp |= dev_priv->lvds_border_bits;
4859                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4860                  * set the DPLLs for dual-channel mode or not.
4861                  */
4862                 if (clock.p2 == 7)
4863                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4864                 else
4865                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4866
4867                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4868                  * appropriately here, but we need to look more thoroughly into how
4869                  * panels behave in the two modes.
4870                  */
4871                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4872                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4873                         temp |= LVDS_HSYNC_POLARITY;
4874                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4875                         temp |= LVDS_VSYNC_POLARITY;
4876                 I915_WRITE(PCH_LVDS, temp);
4877         }
4878
4879         pipeconf &= ~PIPECONF_DITHER_EN;
4880         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4881         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4882                 pipeconf |= PIPECONF_DITHER_EN;
4883                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4884         }
4885         if (is_dp && !is_cpu_edp) {
4886                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4887         } else {
4888                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4889                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4890                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4891                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4892                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4893         }
4894
4895         if (intel_crtc->pch_pll) {
4896                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4897
4898                 /* Wait for the clocks to stabilize. */
4899                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4900                 udelay(150);
4901
4902                 /* The pixel multiplier can only be updated once the
4903                  * DPLL is enabled and the clocks are stable.
4904                  *
4905                  * So write it again.
4906                  */
4907                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4908         }
4909
4910         intel_crtc->lowfreq_avail = false;
4911         if (intel_crtc->pch_pll) {
4912                 if (is_lvds && has_reduced_clock && i915_powersave) {
4913                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4914                         intel_crtc->lowfreq_avail = true;
4915                 } else {
4916                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4917                 }
4918         }
4919
4920         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4921         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4922                 pipeconf |= PIPECONF_INTERLACED_ILK;
4923                 /* the chip adds 2 halflines automatically */
4924                 adjusted_mode->crtc_vtotal -= 1;
4925                 adjusted_mode->crtc_vblank_end -= 1;
4926                 I915_WRITE(VSYNCSHIFT(pipe),
4927                            adjusted_mode->crtc_hsync_start
4928                            - adjusted_mode->crtc_htotal/2);
4929         } else {
4930                 pipeconf |= PIPECONF_PROGRESSIVE;
4931                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4932         }
4933
4934         I915_WRITE(HTOTAL(pipe),
4935                    (adjusted_mode->crtc_hdisplay - 1) |
4936                    ((adjusted_mode->crtc_htotal - 1) << 16));
4937         I915_WRITE(HBLANK(pipe),
4938                    (adjusted_mode->crtc_hblank_start - 1) |
4939                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4940         I915_WRITE(HSYNC(pipe),
4941                    (adjusted_mode->crtc_hsync_start - 1) |
4942                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4943
4944         I915_WRITE(VTOTAL(pipe),
4945                    (adjusted_mode->crtc_vdisplay - 1) |
4946                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4947         I915_WRITE(VBLANK(pipe),
4948                    (adjusted_mode->crtc_vblank_start - 1) |
4949                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4950         I915_WRITE(VSYNC(pipe),
4951                    (adjusted_mode->crtc_vsync_start - 1) |
4952                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4953
4954         /* pipesrc controls the size that is scaled from, which should
4955          * always be the user's requested size.
4956          */
4957         I915_WRITE(PIPESRC(pipe),
4958                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4959
4960         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4961         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4962         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4963         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4964
4965         if (is_cpu_edp)
4966                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4967
4968         I915_WRITE(PIPECONF(pipe), pipeconf);
4969         POSTING_READ(PIPECONF(pipe));
4970
4971         intel_wait_for_vblank(dev, pipe);
4972
4973         I915_WRITE(DSPCNTR(plane), dspcntr);
4974         POSTING_READ(DSPCNTR(plane));
4975
4976         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4977
4978         intel_update_watermarks(dev);
4979
4980         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4981
4982         return ret;
4983 }
4984
4985 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4986                                struct drm_display_mode *mode,
4987                                struct drm_display_mode *adjusted_mode,
4988                                int x, int y,
4989                                struct drm_framebuffer *old_fb)
4990 {
4991         struct drm_device *dev = crtc->dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4994         int pipe = intel_crtc->pipe;
4995         int ret;
4996
4997         drm_vblank_pre_modeset(dev, pipe);
4998
4999         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5000                                               x, y, old_fb);
5001         drm_vblank_post_modeset(dev, pipe);
5002
5003         if (ret)
5004                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5005         else
5006                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5007
5008         return ret;
5009 }
5010
5011 static bool intel_eld_uptodate(struct drm_connector *connector,
5012                                int reg_eldv, uint32_t bits_eldv,
5013                                int reg_elda, uint32_t bits_elda,
5014                                int reg_edid)
5015 {
5016         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5017         uint8_t *eld = connector->eld;
5018         uint32_t i;
5019
5020         i = I915_READ(reg_eldv);
5021         i &= bits_eldv;
5022
5023         if (!eld[0])
5024                 return !i;
5025
5026         if (!i)
5027                 return false;
5028
5029         i = I915_READ(reg_elda);
5030         i &= ~bits_elda;
5031         I915_WRITE(reg_elda, i);
5032
5033         for (i = 0; i < eld[2]; i++)
5034                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5035                         return false;
5036
5037         return true;
5038 }
5039
5040 static void g4x_write_eld(struct drm_connector *connector,
5041                           struct drm_crtc *crtc)
5042 {
5043         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5044         uint8_t *eld = connector->eld;
5045         uint32_t eldv;
5046         uint32_t len;
5047         uint32_t i;
5048
5049         i = I915_READ(G4X_AUD_VID_DID);
5050
5051         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5052                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5053         else
5054                 eldv = G4X_ELDV_DEVCTG;
5055
5056         if (intel_eld_uptodate(connector,
5057                                G4X_AUD_CNTL_ST, eldv,
5058                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5059                                G4X_HDMIW_HDMIEDID))
5060                 return;
5061
5062         i = I915_READ(G4X_AUD_CNTL_ST);
5063         i &= ~(eldv | G4X_ELD_ADDR);
5064         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5065         I915_WRITE(G4X_AUD_CNTL_ST, i);
5066
5067         if (!eld[0])
5068                 return;
5069
5070         len = min_t(uint8_t, eld[2], len);
5071         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5072         for (i = 0; i < len; i++)
5073                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5074
5075         i = I915_READ(G4X_AUD_CNTL_ST);
5076         i |= eldv;
5077         I915_WRITE(G4X_AUD_CNTL_ST, i);
5078 }
5079
5080 static void haswell_write_eld(struct drm_connector *connector,
5081                                      struct drm_crtc *crtc)
5082 {
5083         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5084         uint8_t *eld = connector->eld;
5085         struct drm_device *dev = crtc->dev;
5086         uint32_t eldv;
5087         uint32_t i;
5088         int len;
5089         int pipe = to_intel_crtc(crtc)->pipe;
5090         int tmp;
5091
5092         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5093         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5094         int aud_config = HSW_AUD_CFG(pipe);
5095         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5096
5097
5098         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5099
5100         /* Audio output enable */
5101         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5102         tmp = I915_READ(aud_cntrl_st2);
5103         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5104         I915_WRITE(aud_cntrl_st2, tmp);
5105
5106         /* Wait for 1 vertical blank */
5107         intel_wait_for_vblank(dev, pipe);
5108
5109         /* Set ELD valid state */
5110         tmp = I915_READ(aud_cntrl_st2);
5111         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5112         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5113         I915_WRITE(aud_cntrl_st2, tmp);
5114         tmp = I915_READ(aud_cntrl_st2);
5115         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5116
5117         /* Enable HDMI mode */
5118         tmp = I915_READ(aud_config);
5119         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5120         /* clear N_programing_enable and N_value_index */
5121         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5122         I915_WRITE(aud_config, tmp);
5123
5124         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5125
5126         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5127
5128         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5129                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5130                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5131                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5132         } else
5133                 I915_WRITE(aud_config, 0);
5134
5135         if (intel_eld_uptodate(connector,
5136                                aud_cntrl_st2, eldv,
5137                                aud_cntl_st, IBX_ELD_ADDRESS,
5138                                hdmiw_hdmiedid))
5139                 return;
5140
5141         i = I915_READ(aud_cntrl_st2);
5142         i &= ~eldv;
5143         I915_WRITE(aud_cntrl_st2, i);
5144
5145         if (!eld[0])
5146                 return;
5147
5148         i = I915_READ(aud_cntl_st);
5149         i &= ~IBX_ELD_ADDRESS;
5150         I915_WRITE(aud_cntl_st, i);
5151         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5152         DRM_DEBUG_DRIVER("port num:%d\n", i);
5153
5154         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5155         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5156         for (i = 0; i < len; i++)
5157                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5158
5159         i = I915_READ(aud_cntrl_st2);
5160         i |= eldv;
5161         I915_WRITE(aud_cntrl_st2, i);
5162
5163 }
5164
5165 static void ironlake_write_eld(struct drm_connector *connector,
5166                                      struct drm_crtc *crtc)
5167 {
5168         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5169         uint8_t *eld = connector->eld;
5170         uint32_t eldv;
5171         uint32_t i;
5172         int len;
5173         int hdmiw_hdmiedid;
5174         int aud_config;
5175         int aud_cntl_st;
5176         int aud_cntrl_st2;
5177         int pipe = to_intel_crtc(crtc)->pipe;
5178
5179         if (HAS_PCH_IBX(connector->dev)) {
5180                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5181                 aud_config = IBX_AUD_CFG(pipe);
5182                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5183                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5184         } else {
5185                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5186                 aud_config = CPT_AUD_CFG(pipe);
5187                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5188                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5189         }
5190
5191         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5192
5193         i = I915_READ(aud_cntl_st);
5194         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5195         if (!i) {
5196                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5197                 /* operate blindly on all ports */
5198                 eldv = IBX_ELD_VALIDB;
5199                 eldv |= IBX_ELD_VALIDB << 4;
5200                 eldv |= IBX_ELD_VALIDB << 8;
5201         } else {
5202                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5203                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5204         }
5205
5206         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5207                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5208                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5209                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5210         } else
5211                 I915_WRITE(aud_config, 0);
5212
5213         if (intel_eld_uptodate(connector,
5214                                aud_cntrl_st2, eldv,
5215                                aud_cntl_st, IBX_ELD_ADDRESS,
5216                                hdmiw_hdmiedid))
5217                 return;
5218
5219         i = I915_READ(aud_cntrl_st2);
5220         i &= ~eldv;
5221         I915_WRITE(aud_cntrl_st2, i);
5222
5223         if (!eld[0])
5224                 return;
5225
5226         i = I915_READ(aud_cntl_st);
5227         i &= ~IBX_ELD_ADDRESS;
5228         I915_WRITE(aud_cntl_st, i);
5229
5230         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5231         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5232         for (i = 0; i < len; i++)
5233                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5234
5235         i = I915_READ(aud_cntrl_st2);
5236         i |= eldv;
5237         I915_WRITE(aud_cntrl_st2, i);
5238 }
5239
5240 void intel_write_eld(struct drm_encoder *encoder,
5241                      struct drm_display_mode *mode)
5242 {
5243         struct drm_crtc *crtc = encoder->crtc;
5244         struct drm_connector *connector;
5245         struct drm_device *dev = encoder->dev;
5246         struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248         connector = drm_select_eld(encoder, mode);
5249         if (!connector)
5250                 return;
5251
5252         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5253                          connector->base.id,
5254                          drm_get_connector_name(connector),
5255                          connector->encoder->base.id,
5256                          drm_get_encoder_name(connector->encoder));
5257
5258         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5259
5260         if (dev_priv->display.write_eld)
5261                 dev_priv->display.write_eld(connector, crtc);
5262 }
5263
5264 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5265 void intel_crtc_load_lut(struct drm_crtc *crtc)
5266 {
5267         struct drm_device *dev = crtc->dev;
5268         struct drm_i915_private *dev_priv = dev->dev_private;
5269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5270         int palreg = PALETTE(intel_crtc->pipe);
5271         int i;
5272
5273         /* The clocks have to be on to load the palette. */
5274         if (!crtc->enabled || !intel_crtc->active)
5275                 return;
5276
5277         /* use legacy palette for Ironlake */
5278         if (HAS_PCH_SPLIT(dev))
5279                 palreg = LGC_PALETTE(intel_crtc->pipe);
5280
5281         for (i = 0; i < 256; i++) {
5282                 I915_WRITE(palreg + 4 * i,
5283                            (intel_crtc->lut_r[i] << 16) |
5284                            (intel_crtc->lut_g[i] << 8) |
5285                            intel_crtc->lut_b[i]);
5286         }
5287 }
5288
5289 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5290 {
5291         struct drm_device *dev = crtc->dev;
5292         struct drm_i915_private *dev_priv = dev->dev_private;
5293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294         bool visible = base != 0;
5295         u32 cntl;
5296
5297         if (intel_crtc->cursor_visible == visible)
5298                 return;
5299
5300         cntl = I915_READ(_CURACNTR);
5301         if (visible) {
5302                 /* On these chipsets we can only modify the base whilst
5303                  * the cursor is disabled.
5304                  */
5305                 I915_WRITE(_CURABASE, base);
5306
5307                 cntl &= ~(CURSOR_FORMAT_MASK);
5308                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5309                 cntl |= CURSOR_ENABLE |
5310                         CURSOR_GAMMA_ENABLE |
5311                         CURSOR_FORMAT_ARGB;
5312         } else
5313                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5314         I915_WRITE(_CURACNTR, cntl);
5315
5316         intel_crtc->cursor_visible = visible;
5317 }
5318
5319 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5320 {
5321         struct drm_device *dev = crtc->dev;
5322         struct drm_i915_private *dev_priv = dev->dev_private;
5323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5324         int pipe = intel_crtc->pipe;
5325         bool visible = base != 0;
5326
5327         if (intel_crtc->cursor_visible != visible) {
5328                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5329                 if (base) {
5330                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5331                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5332                         cntl |= pipe << 28; /* Connect to correct pipe */
5333                 } else {
5334                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5335                         cntl |= CURSOR_MODE_DISABLE;
5336                 }
5337                 I915_WRITE(CURCNTR(pipe), cntl);
5338
5339                 intel_crtc->cursor_visible = visible;
5340         }
5341         /* and commit changes on next vblank */
5342         I915_WRITE(CURBASE(pipe), base);
5343 }
5344
5345 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5346 {
5347         struct drm_device *dev = crtc->dev;
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350         int pipe = intel_crtc->pipe;
5351         bool visible = base != 0;
5352
5353         if (intel_crtc->cursor_visible != visible) {
5354                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5355                 if (base) {
5356                         cntl &= ~CURSOR_MODE;
5357                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5358                 } else {
5359                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5360                         cntl |= CURSOR_MODE_DISABLE;
5361                 }
5362                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5363
5364                 intel_crtc->cursor_visible = visible;
5365         }
5366         /* and commit changes on next vblank */
5367         I915_WRITE(CURBASE_IVB(pipe), base);
5368 }
5369
5370 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5371 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5372                                      bool on)
5373 {
5374         struct drm_device *dev = crtc->dev;
5375         struct drm_i915_private *dev_priv = dev->dev_private;
5376         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377         int pipe = intel_crtc->pipe;
5378         int x = intel_crtc->cursor_x;
5379         int y = intel_crtc->cursor_y;
5380         u32 base, pos;
5381         bool visible;
5382
5383         pos = 0;
5384
5385         if (on && crtc->enabled && crtc->fb) {
5386                 base = intel_crtc->cursor_addr;
5387                 if (x > (int) crtc->fb->width)
5388                         base = 0;
5389
5390                 if (y > (int) crtc->fb->height)
5391                         base = 0;
5392         } else
5393                 base = 0;
5394
5395         if (x < 0) {
5396                 if (x + intel_crtc->cursor_width < 0)
5397                         base = 0;
5398
5399                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5400                 x = -x;
5401         }
5402         pos |= x << CURSOR_X_SHIFT;
5403
5404         if (y < 0) {
5405                 if (y + intel_crtc->cursor_height < 0)
5406                         base = 0;
5407
5408                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5409                 y = -y;
5410         }
5411         pos |= y << CURSOR_Y_SHIFT;
5412
5413         visible = base != 0;
5414         if (!visible && !intel_crtc->cursor_visible)
5415                 return;
5416
5417         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5418                 I915_WRITE(CURPOS_IVB(pipe), pos);
5419                 ivb_update_cursor(crtc, base);
5420         } else {
5421                 I915_WRITE(CURPOS(pipe), pos);
5422                 if (IS_845G(dev) || IS_I865G(dev))
5423                         i845_update_cursor(crtc, base);
5424                 else
5425                         i9xx_update_cursor(crtc, base);
5426         }
5427 }
5428
5429 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5430                                  struct drm_file *file,
5431                                  uint32_t handle,
5432                                  uint32_t width, uint32_t height)
5433 {
5434         struct drm_device *dev = crtc->dev;
5435         struct drm_i915_private *dev_priv = dev->dev_private;
5436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5437         struct drm_i915_gem_object *obj;
5438         uint32_t addr;
5439         int ret;
5440
5441         DRM_DEBUG_KMS("\n");
5442
5443         /* if we want to turn off the cursor ignore width and height */
5444         if (!handle) {
5445                 DRM_DEBUG_KMS("cursor off\n");
5446                 addr = 0;
5447                 obj = NULL;
5448                 mutex_lock(&dev->struct_mutex);
5449                 goto finish;
5450         }
5451
5452         /* Currently we only support 64x64 cursors */
5453         if (width != 64 || height != 64) {
5454                 DRM_ERROR("we currently only support 64x64 cursors\n");
5455                 return -EINVAL;
5456         }
5457
5458         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5459         if (&obj->base == NULL)
5460                 return -ENOENT;
5461
5462         if (obj->base.size < width * height * 4) {
5463                 DRM_ERROR("buffer is to small\n");
5464                 ret = -ENOMEM;
5465                 goto fail;
5466         }
5467
5468         /* we only need to pin inside GTT if cursor is non-phy */
5469         mutex_lock(&dev->struct_mutex);
5470         if (!dev_priv->info->cursor_needs_physical) {
5471                 if (obj->tiling_mode) {
5472                         DRM_ERROR("cursor cannot be tiled\n");
5473                         ret = -EINVAL;
5474                         goto fail_locked;
5475                 }
5476
5477                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5478                 if (ret) {
5479                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5480                         goto fail_locked;
5481                 }
5482
5483                 ret = i915_gem_object_put_fence(obj);
5484                 if (ret) {
5485                         DRM_ERROR("failed to release fence for cursor");
5486                         goto fail_unpin;
5487                 }
5488
5489                 addr = obj->gtt_offset;
5490         } else {
5491                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5492                 ret = i915_gem_attach_phys_object(dev, obj,
5493                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5494                                                   align);
5495                 if (ret) {
5496                         DRM_ERROR("failed to attach phys object\n");
5497                         goto fail_locked;
5498                 }
5499                 addr = obj->phys_obj->handle->busaddr;
5500         }
5501
5502         if (IS_GEN2(dev))
5503                 I915_WRITE(CURSIZE, (height << 12) | width);
5504
5505  finish:
5506         if (intel_crtc->cursor_bo) {
5507                 if (dev_priv->info->cursor_needs_physical) {
5508                         if (intel_crtc->cursor_bo != obj)
5509                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5510                 } else
5511                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5512                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5513         }
5514
5515         mutex_unlock(&dev->struct_mutex);
5516
5517         intel_crtc->cursor_addr = addr;
5518         intel_crtc->cursor_bo = obj;
5519         intel_crtc->cursor_width = width;
5520         intel_crtc->cursor_height = height;
5521
5522         intel_crtc_update_cursor(crtc, true);
5523
5524         return 0;
5525 fail_unpin:
5526         i915_gem_object_unpin(obj);
5527 fail_locked:
5528         mutex_unlock(&dev->struct_mutex);
5529 fail:
5530         drm_gem_object_unreference_unlocked(&obj->base);
5531         return ret;
5532 }
5533
5534 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5535 {
5536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5537
5538         intel_crtc->cursor_x = x;
5539         intel_crtc->cursor_y = y;
5540
5541         intel_crtc_update_cursor(crtc, true);
5542
5543         return 0;
5544 }
5545
5546 /** Sets the color ramps on behalf of RandR */
5547 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5548                                  u16 blue, int regno)
5549 {
5550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5551
5552         intel_crtc->lut_r[regno] = red >> 8;
5553         intel_crtc->lut_g[regno] = green >> 8;
5554         intel_crtc->lut_b[regno] = blue >> 8;
5555 }
5556
5557 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5558                              u16 *blue, int regno)
5559 {
5560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561
5562         *red = intel_crtc->lut_r[regno] << 8;
5563         *green = intel_crtc->lut_g[regno] << 8;
5564         *blue = intel_crtc->lut_b[regno] << 8;
5565 }
5566
5567 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5568                                  u16 *blue, uint32_t start, uint32_t size)
5569 {
5570         int end = (start + size > 256) ? 256 : start + size, i;
5571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5572
5573         for (i = start; i < end; i++) {
5574                 intel_crtc->lut_r[i] = red[i] >> 8;
5575                 intel_crtc->lut_g[i] = green[i] >> 8;
5576                 intel_crtc->lut_b[i] = blue[i] >> 8;
5577         }
5578
5579         intel_crtc_load_lut(crtc);
5580 }
5581
5582 /**
5583  * Get a pipe with a simple mode set on it for doing load-based monitor
5584  * detection.
5585  *
5586  * It will be up to the load-detect code to adjust the pipe as appropriate for
5587  * its requirements.  The pipe will be connected to no other encoders.
5588  *
5589  * Currently this code will only succeed if there is a pipe with no encoders
5590  * configured for it.  In the future, it could choose to temporarily disable
5591  * some outputs to free up a pipe for its use.
5592  *
5593  * \return crtc, or NULL if no pipes are available.
5594  */
5595
5596 /* VESA 640x480x72Hz mode to set on the pipe */
5597 static struct drm_display_mode load_detect_mode = {
5598         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5599                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5600 };
5601
5602 static struct drm_framebuffer *
5603 intel_framebuffer_create(struct drm_device *dev,
5604                          struct drm_mode_fb_cmd2 *mode_cmd,
5605                          struct drm_i915_gem_object *obj)
5606 {
5607         struct intel_framebuffer *intel_fb;
5608         int ret;
5609
5610         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5611         if (!intel_fb) {
5612                 drm_gem_object_unreference_unlocked(&obj->base);
5613                 return ERR_PTR(-ENOMEM);
5614         }
5615
5616         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5617         if (ret) {
5618                 drm_gem_object_unreference_unlocked(&obj->base);
5619                 kfree(intel_fb);
5620                 return ERR_PTR(ret);
5621         }
5622
5623         return &intel_fb->base;
5624 }
5625
5626 static u32
5627 intel_framebuffer_pitch_for_width(int width, int bpp)
5628 {
5629         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5630         return ALIGN(pitch, 64);
5631 }
5632
5633 static u32
5634 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5635 {
5636         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5637         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5638 }
5639
5640 static struct drm_framebuffer *
5641 intel_framebuffer_create_for_mode(struct drm_device *dev,
5642                                   struct drm_display_mode *mode,
5643                                   int depth, int bpp)
5644 {
5645         struct drm_i915_gem_object *obj;
5646         struct drm_mode_fb_cmd2 mode_cmd;
5647
5648         obj = i915_gem_alloc_object(dev,
5649                                     intel_framebuffer_size_for_mode(mode, bpp));
5650         if (obj == NULL)
5651                 return ERR_PTR(-ENOMEM);
5652
5653         mode_cmd.width = mode->hdisplay;
5654         mode_cmd.height = mode->vdisplay;
5655         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5656                                                                 bpp);
5657         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5658
5659         return intel_framebuffer_create(dev, &mode_cmd, obj);
5660 }
5661
5662 static struct drm_framebuffer *
5663 mode_fits_in_fbdev(struct drm_device *dev,
5664                    struct drm_display_mode *mode)
5665 {
5666         struct drm_i915_private *dev_priv = dev->dev_private;
5667         struct drm_i915_gem_object *obj;
5668         struct drm_framebuffer *fb;
5669
5670         if (dev_priv->fbdev == NULL)
5671                 return NULL;
5672
5673         obj = dev_priv->fbdev->ifb.obj;
5674         if (obj == NULL)
5675                 return NULL;
5676
5677         fb = &dev_priv->fbdev->ifb.base;
5678         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5679                                                                fb->bits_per_pixel))
5680                 return NULL;
5681
5682         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5683                 return NULL;
5684
5685         return fb;
5686 }
5687
5688 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5689                                 struct drm_display_mode *mode,
5690                                 struct intel_load_detect_pipe *old)
5691 {
5692         struct intel_crtc *intel_crtc;
5693         struct intel_encoder *intel_encoder =
5694                 intel_attached_encoder(connector);
5695         struct drm_crtc *possible_crtc;
5696         struct drm_encoder *encoder = &intel_encoder->base;
5697         struct drm_crtc *crtc = NULL;
5698         struct drm_device *dev = encoder->dev;
5699         struct drm_framebuffer *old_fb;
5700         int i = -1;
5701
5702         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5703                       connector->base.id, drm_get_connector_name(connector),
5704                       encoder->base.id, drm_get_encoder_name(encoder));
5705
5706         /*
5707          * Algorithm gets a little messy:
5708          *
5709          *   - if the connector already has an assigned crtc, use it (but make
5710          *     sure it's on first)
5711          *
5712          *   - try to find the first unused crtc that can drive this connector,
5713          *     and use that if we find one
5714          */
5715
5716         /* See if we already have a CRTC for this connector */
5717         if (encoder->crtc) {
5718                 crtc = encoder->crtc;
5719
5720                 old->dpms_mode = connector->dpms;
5721                 old->load_detect_temp = false;
5722
5723                 /* Make sure the crtc and connector are running */
5724                 if (connector->dpms != DRM_MODE_DPMS_ON)
5725                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5726
5727                 return true;
5728         }
5729
5730         /* Find an unused one (if possible) */
5731         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5732                 i++;
5733                 if (!(encoder->possible_crtcs & (1 << i)))
5734                         continue;
5735                 if (!possible_crtc->enabled) {
5736                         crtc = possible_crtc;
5737                         break;
5738                 }
5739         }
5740
5741         /*
5742          * If we didn't find an unused CRTC, don't use any.
5743          */
5744         if (!crtc) {
5745                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5746                 return false;
5747         }
5748
5749         encoder->crtc = crtc;
5750         connector->encoder = encoder;
5751
5752         intel_crtc = to_intel_crtc(crtc);
5753         old->dpms_mode = connector->dpms;
5754         old->load_detect_temp = true;
5755         old->release_fb = NULL;
5756
5757         if (!mode)
5758                 mode = &load_detect_mode;
5759
5760         old_fb = crtc->fb;
5761
5762         /* We need a framebuffer large enough to accommodate all accesses
5763          * that the plane may generate whilst we perform load detection.
5764          * We can not rely on the fbcon either being present (we get called
5765          * during its initialisation to detect all boot displays, or it may
5766          * not even exist) or that it is large enough to satisfy the
5767          * requested mode.
5768          */
5769         crtc->fb = mode_fits_in_fbdev(dev, mode);
5770         if (crtc->fb == NULL) {
5771                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5772                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5773                 old->release_fb = crtc->fb;
5774         } else
5775                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5776         if (IS_ERR(crtc->fb)) {
5777                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5778                 goto fail;
5779         }
5780
5781         if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
5782                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5783                 if (old->release_fb)
5784                         old->release_fb->funcs->destroy(old->release_fb);
5785                 goto fail;
5786         }
5787
5788         /* let the connector get through one full cycle before testing */
5789         intel_wait_for_vblank(dev, intel_crtc->pipe);
5790
5791         return true;
5792 fail:
5793         connector->encoder = NULL;
5794         encoder->crtc = NULL;
5795         crtc->fb = old_fb;
5796         return false;
5797 }
5798
5799 void intel_release_load_detect_pipe(struct drm_connector *connector,
5800                                     struct intel_load_detect_pipe *old)
5801 {
5802         struct intel_encoder *intel_encoder =
5803                 intel_attached_encoder(connector);
5804         struct drm_encoder *encoder = &intel_encoder->base;
5805         struct drm_device *dev = encoder->dev;
5806
5807         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5808                       connector->base.id, drm_get_connector_name(connector),
5809                       encoder->base.id, drm_get_encoder_name(encoder));
5810
5811         if (old->load_detect_temp) {
5812                 connector->encoder = NULL;
5813                 encoder->crtc = NULL;
5814                 drm_helper_disable_unused_functions(dev);
5815
5816                 if (old->release_fb)
5817                         old->release_fb->funcs->destroy(old->release_fb);
5818
5819                 return;
5820         }
5821
5822         /* Switch crtc and encoder back off if necessary */
5823         if (old->dpms_mode != DRM_MODE_DPMS_ON)
5824                 connector->funcs->dpms(connector, old->dpms_mode);
5825 }
5826
5827 /* Returns the clock of the currently programmed mode of the given pipe. */
5828 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5829 {
5830         struct drm_i915_private *dev_priv = dev->dev_private;
5831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5832         int pipe = intel_crtc->pipe;
5833         u32 dpll = I915_READ(DPLL(pipe));
5834         u32 fp;
5835         intel_clock_t clock;
5836
5837         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5838                 fp = I915_READ(FP0(pipe));
5839         else
5840                 fp = I915_READ(FP1(pipe));
5841
5842         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5843         if (IS_PINEVIEW(dev)) {
5844                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5845                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5846         } else {
5847                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5848                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5849         }
5850
5851         if (!IS_GEN2(dev)) {
5852                 if (IS_PINEVIEW(dev))
5853                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5854                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5855                 else
5856                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5857                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5858
5859                 switch (dpll & DPLL_MODE_MASK) {
5860                 case DPLLB_MODE_DAC_SERIAL:
5861                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5862                                 5 : 10;
5863                         break;
5864                 case DPLLB_MODE_LVDS:
5865                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5866                                 7 : 14;
5867                         break;
5868                 default:
5869                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5870                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5871                         return 0;
5872                 }
5873
5874                 /* XXX: Handle the 100Mhz refclk */
5875                 intel_clock(dev, 96000, &clock);
5876         } else {
5877                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5878
5879                 if (is_lvds) {
5880                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5881                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5882                         clock.p2 = 14;
5883
5884                         if ((dpll & PLL_REF_INPUT_MASK) ==
5885                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5886                                 /* XXX: might not be 66MHz */
5887                                 intel_clock(dev, 66000, &clock);
5888                         } else
5889                                 intel_clock(dev, 48000, &clock);
5890                 } else {
5891                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5892                                 clock.p1 = 2;
5893                         else {
5894                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5895                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5896                         }
5897                         if (dpll & PLL_P2_DIVIDE_BY_4)
5898                                 clock.p2 = 4;
5899                         else
5900                                 clock.p2 = 2;
5901
5902                         intel_clock(dev, 48000, &clock);
5903                 }
5904         }
5905
5906         /* XXX: It would be nice to validate the clocks, but we can't reuse
5907          * i830PllIsValid() because it relies on the xf86_config connector
5908          * configuration being accurate, which it isn't necessarily.
5909          */
5910
5911         return clock.dot;
5912 }
5913
5914 /** Returns the currently programmed mode of the given pipe. */
5915 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5916                                              struct drm_crtc *crtc)
5917 {
5918         struct drm_i915_private *dev_priv = dev->dev_private;
5919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5920         int pipe = intel_crtc->pipe;
5921         struct drm_display_mode *mode;
5922         int htot = I915_READ(HTOTAL(pipe));
5923         int hsync = I915_READ(HSYNC(pipe));
5924         int vtot = I915_READ(VTOTAL(pipe));
5925         int vsync = I915_READ(VSYNC(pipe));
5926
5927         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5928         if (!mode)
5929                 return NULL;
5930
5931         mode->clock = intel_crtc_clock_get(dev, crtc);
5932         mode->hdisplay = (htot & 0xffff) + 1;
5933         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5934         mode->hsync_start = (hsync & 0xffff) + 1;
5935         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5936         mode->vdisplay = (vtot & 0xffff) + 1;
5937         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5938         mode->vsync_start = (vsync & 0xffff) + 1;
5939         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5940
5941         drm_mode_set_name(mode);
5942
5943         return mode;
5944 }
5945
5946 static void intel_increase_pllclock(struct drm_crtc *crtc)
5947 {
5948         struct drm_device *dev = crtc->dev;
5949         drm_i915_private_t *dev_priv = dev->dev_private;
5950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5951         int pipe = intel_crtc->pipe;
5952         int dpll_reg = DPLL(pipe);
5953         int dpll;
5954
5955         if (HAS_PCH_SPLIT(dev))
5956                 return;
5957
5958         if (!dev_priv->lvds_downclock_avail)
5959                 return;
5960
5961         dpll = I915_READ(dpll_reg);
5962         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5963                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5964
5965                 assert_panel_unlocked(dev_priv, pipe);
5966
5967                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5968                 I915_WRITE(dpll_reg, dpll);
5969                 intel_wait_for_vblank(dev, pipe);
5970
5971                 dpll = I915_READ(dpll_reg);
5972                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5973                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5974         }
5975 }
5976
5977 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5978 {
5979         struct drm_device *dev = crtc->dev;
5980         drm_i915_private_t *dev_priv = dev->dev_private;
5981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982
5983         if (HAS_PCH_SPLIT(dev))
5984                 return;
5985
5986         if (!dev_priv->lvds_downclock_avail)
5987                 return;
5988
5989         /*
5990          * Since this is called by a timer, we should never get here in
5991          * the manual case.
5992          */
5993         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5994                 int pipe = intel_crtc->pipe;
5995                 int dpll_reg = DPLL(pipe);
5996                 int dpll;
5997
5998                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5999
6000                 assert_panel_unlocked(dev_priv, pipe);
6001
6002                 dpll = I915_READ(dpll_reg);
6003                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6004                 I915_WRITE(dpll_reg, dpll);
6005                 intel_wait_for_vblank(dev, pipe);
6006                 dpll = I915_READ(dpll_reg);
6007                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6008                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6009         }
6010
6011 }
6012
6013 void intel_mark_busy(struct drm_device *dev)
6014 {
6015         i915_update_gfx_val(dev->dev_private);
6016 }
6017
6018 void intel_mark_idle(struct drm_device *dev)
6019 {
6020 }
6021
6022 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6023 {
6024         struct drm_device *dev = obj->base.dev;
6025         struct drm_crtc *crtc;
6026
6027         if (!i915_powersave)
6028                 return;
6029
6030         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6031                 if (!crtc->fb)
6032                         continue;
6033
6034                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6035                         intel_increase_pllclock(crtc);
6036         }
6037 }
6038
6039 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6040 {
6041         struct drm_device *dev = obj->base.dev;
6042         struct drm_crtc *crtc;
6043
6044         if (!i915_powersave)
6045                 return;
6046
6047         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6048                 if (!crtc->fb)
6049                         continue;
6050
6051                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6052                         intel_decrease_pllclock(crtc);
6053         }
6054 }
6055
6056 static void intel_crtc_destroy(struct drm_crtc *crtc)
6057 {
6058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059         struct drm_device *dev = crtc->dev;
6060         struct intel_unpin_work *work;
6061         unsigned long flags;
6062
6063         spin_lock_irqsave(&dev->event_lock, flags);
6064         work = intel_crtc->unpin_work;
6065         intel_crtc->unpin_work = NULL;
6066         spin_unlock_irqrestore(&dev->event_lock, flags);
6067
6068         if (work) {
6069                 cancel_work_sync(&work->work);
6070                 kfree(work);
6071         }
6072
6073         drm_crtc_cleanup(crtc);
6074
6075         kfree(intel_crtc);
6076 }
6077
6078 static void intel_unpin_work_fn(struct work_struct *__work)
6079 {
6080         struct intel_unpin_work *work =
6081                 container_of(__work, struct intel_unpin_work, work);
6082
6083         mutex_lock(&work->dev->struct_mutex);
6084         intel_unpin_fb_obj(work->old_fb_obj);
6085         drm_gem_object_unreference(&work->pending_flip_obj->base);
6086         drm_gem_object_unreference(&work->old_fb_obj->base);
6087
6088         intel_update_fbc(work->dev);
6089         mutex_unlock(&work->dev->struct_mutex);
6090         kfree(work);
6091 }
6092
6093 static void do_intel_finish_page_flip(struct drm_device *dev,
6094                                       struct drm_crtc *crtc)
6095 {
6096         drm_i915_private_t *dev_priv = dev->dev_private;
6097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6098         struct intel_unpin_work *work;
6099         struct drm_i915_gem_object *obj;
6100         struct drm_pending_vblank_event *e;
6101         struct timeval tnow, tvbl;
6102         unsigned long flags;
6103
6104         /* Ignore early vblank irqs */
6105         if (intel_crtc == NULL)
6106                 return;
6107
6108         do_gettimeofday(&tnow);
6109
6110         spin_lock_irqsave(&dev->event_lock, flags);
6111         work = intel_crtc->unpin_work;
6112         if (work == NULL || !work->pending) {
6113                 spin_unlock_irqrestore(&dev->event_lock, flags);
6114                 return;
6115         }
6116
6117         intel_crtc->unpin_work = NULL;
6118
6119         if (work->event) {
6120                 e = work->event;
6121                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6122
6123                 /* Called before vblank count and timestamps have
6124                  * been updated for the vblank interval of flip
6125                  * completion? Need to increment vblank count and
6126                  * add one videorefresh duration to returned timestamp
6127                  * to account for this. We assume this happened if we
6128                  * get called over 0.9 frame durations after the last
6129                  * timestamped vblank.
6130                  *
6131                  * This calculation can not be used with vrefresh rates
6132                  * below 5Hz (10Hz to be on the safe side) without
6133                  * promoting to 64 integers.
6134                  */
6135                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6136                     9 * crtc->framedur_ns) {
6137                         e->event.sequence++;
6138                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6139                                              crtc->framedur_ns);
6140                 }
6141
6142                 e->event.tv_sec = tvbl.tv_sec;
6143                 e->event.tv_usec = tvbl.tv_usec;
6144
6145                 list_add_tail(&e->base.link,
6146                               &e->base.file_priv->event_list);
6147                 wake_up_interruptible(&e->base.file_priv->event_wait);
6148         }
6149
6150         drm_vblank_put(dev, intel_crtc->pipe);
6151
6152         spin_unlock_irqrestore(&dev->event_lock, flags);
6153
6154         obj = work->old_fb_obj;
6155
6156         atomic_clear_mask(1 << intel_crtc->plane,
6157                           &obj->pending_flip.counter);
6158         if (atomic_read(&obj->pending_flip) == 0)
6159                 wake_up(&dev_priv->pending_flip_queue);
6160
6161         schedule_work(&work->work);
6162
6163         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6164 }
6165
6166 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6167 {
6168         drm_i915_private_t *dev_priv = dev->dev_private;
6169         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6170
6171         do_intel_finish_page_flip(dev, crtc);
6172 }
6173
6174 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6175 {
6176         drm_i915_private_t *dev_priv = dev->dev_private;
6177         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6178
6179         do_intel_finish_page_flip(dev, crtc);
6180 }
6181
6182 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6183 {
6184         drm_i915_private_t *dev_priv = dev->dev_private;
6185         struct intel_crtc *intel_crtc =
6186                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6187         unsigned long flags;
6188
6189         spin_lock_irqsave(&dev->event_lock, flags);
6190         if (intel_crtc->unpin_work) {
6191                 if ((++intel_crtc->unpin_work->pending) > 1)
6192                         DRM_ERROR("Prepared flip multiple times\n");
6193         } else {
6194                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6195         }
6196         spin_unlock_irqrestore(&dev->event_lock, flags);
6197 }
6198
6199 static int intel_gen2_queue_flip(struct drm_device *dev,
6200                                  struct drm_crtc *crtc,
6201                                  struct drm_framebuffer *fb,
6202                                  struct drm_i915_gem_object *obj)
6203 {
6204         struct drm_i915_private *dev_priv = dev->dev_private;
6205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6206         u32 flip_mask;
6207         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6208         int ret;
6209
6210         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6211         if (ret)
6212                 goto err;
6213
6214         ret = intel_ring_begin(ring, 6);
6215         if (ret)
6216                 goto err_unpin;
6217
6218         /* Can't queue multiple flips, so wait for the previous
6219          * one to finish before executing the next.
6220          */
6221         if (intel_crtc->plane)
6222                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6223         else
6224                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6225         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6226         intel_ring_emit(ring, MI_NOOP);
6227         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6228                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6229         intel_ring_emit(ring, fb->pitches[0]);
6230         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6231         intel_ring_emit(ring, 0); /* aux display base address, unused */
6232         intel_ring_advance(ring);
6233         return 0;
6234
6235 err_unpin:
6236         intel_unpin_fb_obj(obj);
6237 err:
6238         return ret;
6239 }
6240
6241 static int intel_gen3_queue_flip(struct drm_device *dev,
6242                                  struct drm_crtc *crtc,
6243                                  struct drm_framebuffer *fb,
6244                                  struct drm_i915_gem_object *obj)
6245 {
6246         struct drm_i915_private *dev_priv = dev->dev_private;
6247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248         u32 flip_mask;
6249         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6250         int ret;
6251
6252         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6253         if (ret)
6254                 goto err;
6255
6256         ret = intel_ring_begin(ring, 6);
6257         if (ret)
6258                 goto err_unpin;
6259
6260         if (intel_crtc->plane)
6261                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6262         else
6263                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6264         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6265         intel_ring_emit(ring, MI_NOOP);
6266         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6267                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6268         intel_ring_emit(ring, fb->pitches[0]);
6269         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6270         intel_ring_emit(ring, MI_NOOP);
6271
6272         intel_ring_advance(ring);
6273         return 0;
6274
6275 err_unpin:
6276         intel_unpin_fb_obj(obj);
6277 err:
6278         return ret;
6279 }
6280
6281 static int intel_gen4_queue_flip(struct drm_device *dev,
6282                                  struct drm_crtc *crtc,
6283                                  struct drm_framebuffer *fb,
6284                                  struct drm_i915_gem_object *obj)
6285 {
6286         struct drm_i915_private *dev_priv = dev->dev_private;
6287         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288         uint32_t pf, pipesrc;
6289         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6290         int ret;
6291
6292         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6293         if (ret)
6294                 goto err;
6295
6296         ret = intel_ring_begin(ring, 4);
6297         if (ret)
6298                 goto err_unpin;
6299
6300         /* i965+ uses the linear or tiled offsets from the
6301          * Display Registers (which do not change across a page-flip)
6302          * so we need only reprogram the base address.
6303          */
6304         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6305                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6306         intel_ring_emit(ring, fb->pitches[0]);
6307         intel_ring_emit(ring,
6308                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6309                         obj->tiling_mode);
6310
6311         /* XXX Enabling the panel-fitter across page-flip is so far
6312          * untested on non-native modes, so ignore it for now.
6313          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6314          */
6315         pf = 0;
6316         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6317         intel_ring_emit(ring, pf | pipesrc);
6318         intel_ring_advance(ring);
6319         return 0;
6320
6321 err_unpin:
6322         intel_unpin_fb_obj(obj);
6323 err:
6324         return ret;
6325 }
6326
6327 static int intel_gen6_queue_flip(struct drm_device *dev,
6328                                  struct drm_crtc *crtc,
6329                                  struct drm_framebuffer *fb,
6330                                  struct drm_i915_gem_object *obj)
6331 {
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6335         uint32_t pf, pipesrc;
6336         int ret;
6337
6338         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6339         if (ret)
6340                 goto err;
6341
6342         ret = intel_ring_begin(ring, 4);
6343         if (ret)
6344                 goto err_unpin;
6345
6346         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6347                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6348         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6349         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6350
6351         /* Contrary to the suggestions in the documentation,
6352          * "Enable Panel Fitter" does not seem to be required when page
6353          * flipping with a non-native mode, and worse causes a normal
6354          * modeset to fail.
6355          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6356          */
6357         pf = 0;
6358         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6359         intel_ring_emit(ring, pf | pipesrc);
6360         intel_ring_advance(ring);
6361         return 0;
6362
6363 err_unpin:
6364         intel_unpin_fb_obj(obj);
6365 err:
6366         return ret;
6367 }
6368
6369 /*
6370  * On gen7 we currently use the blit ring because (in early silicon at least)
6371  * the render ring doesn't give us interrpts for page flip completion, which
6372  * means clients will hang after the first flip is queued.  Fortunately the
6373  * blit ring generates interrupts properly, so use it instead.
6374  */
6375 static int intel_gen7_queue_flip(struct drm_device *dev,
6376                                  struct drm_crtc *crtc,
6377                                  struct drm_framebuffer *fb,
6378                                  struct drm_i915_gem_object *obj)
6379 {
6380         struct drm_i915_private *dev_priv = dev->dev_private;
6381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6383         uint32_t plane_bit = 0;
6384         int ret;
6385
6386         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6387         if (ret)
6388                 goto err;
6389
6390         switch(intel_crtc->plane) {
6391         case PLANE_A:
6392                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6393                 break;
6394         case PLANE_B:
6395                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6396                 break;
6397         case PLANE_C:
6398                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6399                 break;
6400         default:
6401                 WARN_ONCE(1, "unknown plane in flip command\n");
6402                 ret = -ENODEV;
6403                 goto err_unpin;
6404         }
6405
6406         ret = intel_ring_begin(ring, 4);
6407         if (ret)
6408                 goto err_unpin;
6409
6410         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6411         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6412         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6413         intel_ring_emit(ring, (MI_NOOP));
6414         intel_ring_advance(ring);
6415         return 0;
6416
6417 err_unpin:
6418         intel_unpin_fb_obj(obj);
6419 err:
6420         return ret;
6421 }
6422
6423 static int intel_default_queue_flip(struct drm_device *dev,
6424                                     struct drm_crtc *crtc,
6425                                     struct drm_framebuffer *fb,
6426                                     struct drm_i915_gem_object *obj)
6427 {
6428         return -ENODEV;
6429 }
6430
6431 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6432                                 struct drm_framebuffer *fb,
6433                                 struct drm_pending_vblank_event *event)
6434 {
6435         struct drm_device *dev = crtc->dev;
6436         struct drm_i915_private *dev_priv = dev->dev_private;
6437         struct intel_framebuffer *intel_fb;
6438         struct drm_i915_gem_object *obj;
6439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6440         struct intel_unpin_work *work;
6441         unsigned long flags;
6442         int ret;
6443
6444         /* Can't change pixel format via MI display flips. */
6445         if (fb->pixel_format != crtc->fb->pixel_format)
6446                 return -EINVAL;
6447
6448         /*
6449          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6450          * Note that pitch changes could also affect these register.
6451          */
6452         if (INTEL_INFO(dev)->gen > 3 &&
6453             (fb->offsets[0] != crtc->fb->offsets[0] ||
6454              fb->pitches[0] != crtc->fb->pitches[0]))
6455                 return -EINVAL;
6456
6457         work = kzalloc(sizeof *work, GFP_KERNEL);
6458         if (work == NULL)
6459                 return -ENOMEM;
6460
6461         work->event = event;
6462         work->dev = crtc->dev;
6463         intel_fb = to_intel_framebuffer(crtc->fb);
6464         work->old_fb_obj = intel_fb->obj;
6465         INIT_WORK(&work->work, intel_unpin_work_fn);
6466
6467         ret = drm_vblank_get(dev, intel_crtc->pipe);
6468         if (ret)
6469                 goto free_work;
6470
6471         /* We borrow the event spin lock for protecting unpin_work */
6472         spin_lock_irqsave(&dev->event_lock, flags);
6473         if (intel_crtc->unpin_work) {
6474                 spin_unlock_irqrestore(&dev->event_lock, flags);
6475                 kfree(work);
6476                 drm_vblank_put(dev, intel_crtc->pipe);
6477
6478                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6479                 return -EBUSY;
6480         }
6481         intel_crtc->unpin_work = work;
6482         spin_unlock_irqrestore(&dev->event_lock, flags);
6483
6484         intel_fb = to_intel_framebuffer(fb);
6485         obj = intel_fb->obj;
6486
6487         ret = i915_mutex_lock_interruptible(dev);
6488         if (ret)
6489                 goto cleanup;
6490
6491         /* Reference the objects for the scheduled work. */
6492         drm_gem_object_reference(&work->old_fb_obj->base);
6493         drm_gem_object_reference(&obj->base);
6494
6495         crtc->fb = fb;
6496
6497         work->pending_flip_obj = obj;
6498
6499         work->enable_stall_check = true;
6500
6501         /* Block clients from rendering to the new back buffer until
6502          * the flip occurs and the object is no longer visible.
6503          */
6504         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6505
6506         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6507         if (ret)
6508                 goto cleanup_pending;
6509
6510         intel_disable_fbc(dev);
6511         intel_mark_fb_busy(obj);
6512         mutex_unlock(&dev->struct_mutex);
6513
6514         trace_i915_flip_request(intel_crtc->plane, obj);
6515
6516         return 0;
6517
6518 cleanup_pending:
6519         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6520         drm_gem_object_unreference(&work->old_fb_obj->base);
6521         drm_gem_object_unreference(&obj->base);
6522         mutex_unlock(&dev->struct_mutex);
6523
6524 cleanup:
6525         spin_lock_irqsave(&dev->event_lock, flags);
6526         intel_crtc->unpin_work = NULL;
6527         spin_unlock_irqrestore(&dev->event_lock, flags);
6528
6529         drm_vblank_put(dev, intel_crtc->pipe);
6530 free_work:
6531         kfree(work);
6532
6533         return ret;
6534 }
6535
6536 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6537         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6538         .load_lut = intel_crtc_load_lut,
6539         .disable = intel_crtc_disable,
6540 };
6541
6542 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6543                                   struct drm_crtc *crtc)
6544 {
6545         struct drm_device *dev;
6546         struct drm_crtc *tmp;
6547         int crtc_mask = 1;
6548
6549         WARN(!crtc, "checking null crtc?\n");
6550
6551         dev = crtc->dev;
6552
6553         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6554                 if (tmp == crtc)
6555                         break;
6556                 crtc_mask <<= 1;
6557         }
6558
6559         if (encoder->possible_crtcs & crtc_mask)
6560                 return true;
6561         return false;
6562 }
6563
6564 static int
6565 intel_crtc_helper_disable(struct drm_crtc *crtc)
6566 {
6567         struct drm_device *dev = crtc->dev;
6568         struct drm_connector *connector;
6569         struct drm_encoder *encoder;
6570
6571         /* Decouple all encoders and their attached connectors from this crtc */
6572         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6573                 if (encoder->crtc != crtc)
6574                         continue;
6575
6576                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6577                         if (connector->encoder != encoder)
6578                                 continue;
6579
6580                         connector->encoder = NULL;
6581                 }
6582         }
6583
6584         drm_helper_disable_unused_functions(dev);
6585         return 0;
6586 }
6587
6588 static void
6589 intel_crtc_prepare_encoders(struct drm_device *dev)
6590 {
6591         struct intel_encoder *encoder;
6592
6593         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6594                 /* Disable unused encoders */
6595                 if (encoder->base.crtc == NULL)
6596                         encoder->disable(encoder);
6597         }
6598 }
6599
6600 bool intel_set_mode(struct drm_crtc *crtc,
6601                     struct drm_display_mode *mode,
6602                     int x, int y, struct drm_framebuffer *old_fb)
6603 {
6604         struct drm_device *dev = crtc->dev;
6605         drm_i915_private_t *dev_priv = dev->dev_private;
6606         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6607         struct drm_encoder_helper_funcs *encoder_funcs;
6608         int saved_x, saved_y;
6609         struct drm_encoder *encoder;
6610         bool ret = true;
6611
6612         crtc->enabled = drm_helper_crtc_in_use(crtc);
6613         if (!crtc->enabled)
6614                 return true;
6615
6616         adjusted_mode = drm_mode_duplicate(dev, mode);
6617         if (!adjusted_mode)
6618                 return false;
6619
6620         saved_hwmode = crtc->hwmode;
6621         saved_mode = crtc->mode;
6622         saved_x = crtc->x;
6623         saved_y = crtc->y;
6624
6625         /* Update crtc values up front so the driver can rely on them for mode
6626          * setting.
6627          */
6628         crtc->mode = *mode;
6629         crtc->x = x;
6630         crtc->y = y;
6631
6632         /* Pass our mode to the connectors and the CRTC to give them a chance to
6633          * adjust it according to limitations or connector properties, and also
6634          * a chance to reject the mode entirely.
6635          */
6636         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6637
6638                 if (encoder->crtc != crtc)
6639                         continue;
6640                 encoder_funcs = encoder->helper_private;
6641                 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6642                                                       adjusted_mode))) {
6643                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6644                         goto done;
6645                 }
6646         }
6647
6648         if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6649                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6650                 goto done;
6651         }
6652         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6653
6654         intel_crtc_prepare_encoders(dev);
6655
6656         dev_priv->display.crtc_disable(crtc);
6657
6658         /* Set up the DPLL and any encoders state that needs to adjust or depend
6659          * on the DPLL.
6660          */
6661         ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
6662         if (!ret)
6663             goto done;
6664
6665         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6666
6667                 if (encoder->crtc != crtc)
6668                         continue;
6669
6670                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6671                         encoder->base.id, drm_get_encoder_name(encoder),
6672                         mode->base.id, mode->name);
6673                 encoder_funcs = encoder->helper_private;
6674                 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6675         }
6676
6677         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6678         dev_priv->display.crtc_enable(crtc);
6679
6680         /* Store real post-adjustment hardware mode. */
6681         crtc->hwmode = *adjusted_mode;
6682
6683         /* Calculate and store various constants which
6684          * are later needed by vblank and swap-completion
6685          * timestamping. They are derived from true hwmode.
6686          */
6687         drm_calc_timestamping_constants(crtc);
6688
6689         /* FIXME: add subpixel order */
6690 done:
6691         drm_mode_destroy(dev, adjusted_mode);
6692         if (!ret) {
6693                 crtc->hwmode = saved_hwmode;
6694                 crtc->mode = saved_mode;
6695                 crtc->x = saved_x;
6696                 crtc->y = saved_y;
6697         }
6698
6699         return ret;
6700 }
6701
6702 static int intel_crtc_set_config(struct drm_mode_set *set)
6703 {
6704         struct drm_device *dev;
6705         struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6706         struct drm_encoder *save_encoders, *new_encoder, *encoder;
6707         struct drm_framebuffer *old_fb = NULL;
6708         bool mode_changed = false; /* if true do a full mode set */
6709         bool fb_changed = false; /* if true and !mode_changed just do a flip */
6710         struct drm_connector *save_connectors, *connector;
6711         int count = 0, ro;
6712         struct drm_mode_set save_set;
6713         int ret;
6714         int i;
6715
6716         DRM_DEBUG_KMS("\n");
6717
6718         if (!set)
6719                 return -EINVAL;
6720
6721         if (!set->crtc)
6722                 return -EINVAL;
6723
6724         if (!set->crtc->helper_private)
6725                 return -EINVAL;
6726
6727         if (!set->mode)
6728                 set->fb = NULL;
6729
6730         if (set->fb) {
6731                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6732                                 set->crtc->base.id, set->fb->base.id,
6733                                 (int)set->num_connectors, set->x, set->y);
6734         } else {
6735                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6736                 return intel_crtc_helper_disable(set->crtc);
6737         }
6738
6739         dev = set->crtc->dev;
6740
6741         /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6742          * connector data. */
6743         save_crtcs = kzalloc(dev->mode_config.num_crtc *
6744                              sizeof(struct drm_crtc), GFP_KERNEL);
6745         if (!save_crtcs)
6746                 return -ENOMEM;
6747
6748         save_encoders = kzalloc(dev->mode_config.num_encoder *
6749                                 sizeof(struct drm_encoder), GFP_KERNEL);
6750         if (!save_encoders) {
6751                 kfree(save_crtcs);
6752                 return -ENOMEM;
6753         }
6754
6755         save_connectors = kzalloc(dev->mode_config.num_connector *
6756                                 sizeof(struct drm_connector), GFP_KERNEL);
6757         if (!save_connectors) {
6758                 kfree(save_crtcs);
6759                 kfree(save_encoders);
6760                 return -ENOMEM;
6761         }
6762
6763         /* Copy data. Note that driver private data is not affected.
6764          * Should anything bad happen only the expected state is
6765          * restored, not the drivers personal bookkeeping.
6766          */
6767         count = 0;
6768         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6769                 save_crtcs[count++] = *crtc;
6770         }
6771
6772         count = 0;
6773         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6774                 save_encoders[count++] = *encoder;
6775         }
6776
6777         count = 0;
6778         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6779                 save_connectors[count++] = *connector;
6780         }
6781
6782         save_set.crtc = set->crtc;
6783         save_set.mode = &set->crtc->mode;
6784         save_set.x = set->crtc->x;
6785         save_set.y = set->crtc->y;
6786         save_set.fb = set->crtc->fb;
6787
6788         /* We should be able to check here if the fb has the same properties
6789          * and then just flip_or_move it */
6790         if (set->crtc->fb != set->fb) {
6791                 /* If we have no fb then treat it as a full mode set */
6792                 if (set->crtc->fb == NULL) {
6793                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6794                         mode_changed = true;
6795                 } else if (set->fb == NULL) {
6796                         mode_changed = true;
6797                 } else if (set->fb->depth != set->crtc->fb->depth) {
6798                         mode_changed = true;
6799                 } else if (set->fb->bits_per_pixel !=
6800                            set->crtc->fb->bits_per_pixel) {
6801                         mode_changed = true;
6802                 } else
6803                         fb_changed = true;
6804         }
6805
6806         if (set->x != set->crtc->x || set->y != set->crtc->y)
6807                 fb_changed = true;
6808
6809         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6810                 DRM_DEBUG_KMS("modes are different, full mode set\n");
6811                 drm_mode_debug_printmodeline(&set->crtc->mode);
6812                 drm_mode_debug_printmodeline(set->mode);
6813                 mode_changed = true;
6814         }
6815
6816         /* a) traverse passed in connector list and get encoders for them */
6817         count = 0;
6818         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6819                 new_encoder = connector->encoder;
6820                 for (ro = 0; ro < set->num_connectors; ro++) {
6821                         if (set->connectors[ro] == connector) {
6822                                 new_encoder =
6823                                         &intel_attached_encoder(connector)->base;
6824                                 break;
6825                         }
6826                 }
6827
6828                 if (new_encoder != connector->encoder) {
6829                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6830                         mode_changed = true;
6831                         /* If the encoder is reused for another connector, then
6832                          * the appropriate crtc will be set later.
6833                          */
6834                         if (connector->encoder)
6835                                 connector->encoder->crtc = NULL;
6836                         connector->encoder = new_encoder;
6837                 }
6838         }
6839
6840         count = 0;
6841         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6842                 if (!connector->encoder)
6843                         continue;
6844
6845                 if (connector->encoder->crtc == set->crtc)
6846                         new_crtc = NULL;
6847                 else
6848                         new_crtc = connector->encoder->crtc;
6849
6850                 for (ro = 0; ro < set->num_connectors; ro++) {
6851                         if (set->connectors[ro] == connector)
6852                                 new_crtc = set->crtc;
6853                 }
6854
6855                 /* Make sure the new CRTC will work with the encoder */
6856                 if (new_crtc &&
6857                     !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6858                         ret = -EINVAL;
6859                         goto fail;
6860                 }
6861                 if (new_crtc != connector->encoder->crtc) {
6862                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6863                         mode_changed = true;
6864                         connector->encoder->crtc = new_crtc;
6865                 }
6866                 if (new_crtc) {
6867                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6868                                 connector->base.id, drm_get_connector_name(connector),
6869                                 new_crtc->base.id);
6870                 } else {
6871                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6872                                 connector->base.id, drm_get_connector_name(connector));
6873                 }
6874         }
6875
6876         if (mode_changed) {
6877                 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6878                 if (set->crtc->enabled) {
6879                         DRM_DEBUG_KMS("attempting to set mode from"
6880                                         " userspace\n");
6881                         drm_mode_debug_printmodeline(set->mode);
6882                         old_fb = set->crtc->fb;
6883                         set->crtc->fb = set->fb;
6884                         if (!intel_set_mode(set->crtc, set->mode,
6885                                             set->x, set->y, old_fb)) {
6886                                 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6887                                           set->crtc->base.id);
6888                                 set->crtc->fb = old_fb;
6889                                 ret = -EINVAL;
6890                                 goto fail;
6891                         }
6892                         DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6893                         for (i = 0; i < set->num_connectors; i++) {
6894                                 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6895                                               drm_get_connector_name(set->connectors[i]));
6896                                 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6897                         }
6898                 }
6899                 drm_helper_disable_unused_functions(dev);
6900         } else if (fb_changed) {
6901                 set->crtc->x = set->x;
6902                 set->crtc->y = set->y;
6903
6904                 old_fb = set->crtc->fb;
6905                 if (set->crtc->fb != set->fb)
6906                         set->crtc->fb = set->fb;
6907                 ret = intel_pipe_set_base(set->crtc,
6908                                           set->x, set->y, old_fb);
6909                 if (ret != 0) {
6910                         set->crtc->fb = old_fb;
6911                         goto fail;
6912                 }
6913         }
6914
6915         kfree(save_connectors);
6916         kfree(save_encoders);
6917         kfree(save_crtcs);
6918         return 0;
6919
6920 fail:
6921         /* Restore all previous data. */
6922         count = 0;
6923         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6924                 *crtc = save_crtcs[count++];
6925         }
6926
6927         count = 0;
6928         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6929                 *encoder = save_encoders[count++];
6930         }
6931
6932         count = 0;
6933         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6934                 *connector = save_connectors[count++];
6935         }
6936
6937         /* Try to restore the config */
6938         if (mode_changed &&
6939             !intel_set_mode(save_set.crtc, save_set.mode,
6940                             save_set.x, save_set.y, save_set.fb))
6941                 DRM_ERROR("failed to restore config after modeset failure\n");
6942
6943         kfree(save_connectors);
6944         kfree(save_encoders);
6945         kfree(save_crtcs);
6946         return ret;
6947 }
6948
6949 static const struct drm_crtc_funcs intel_crtc_funcs = {
6950         .cursor_set = intel_crtc_cursor_set,
6951         .cursor_move = intel_crtc_cursor_move,
6952         .gamma_set = intel_crtc_gamma_set,
6953         .set_config = intel_crtc_set_config,
6954         .destroy = intel_crtc_destroy,
6955         .page_flip = intel_crtc_page_flip,
6956 };
6957
6958 static void intel_pch_pll_init(struct drm_device *dev)
6959 {
6960         drm_i915_private_t *dev_priv = dev->dev_private;
6961         int i;
6962
6963         if (dev_priv->num_pch_pll == 0) {
6964                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6965                 return;
6966         }
6967
6968         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6969                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6970                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6971                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6972         }
6973 }
6974
6975 static void intel_crtc_init(struct drm_device *dev, int pipe)
6976 {
6977         drm_i915_private_t *dev_priv = dev->dev_private;
6978         struct intel_crtc *intel_crtc;
6979         int i;
6980
6981         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6982         if (intel_crtc == NULL)
6983                 return;
6984
6985         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6986
6987         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6988         for (i = 0; i < 256; i++) {
6989                 intel_crtc->lut_r[i] = i;
6990                 intel_crtc->lut_g[i] = i;
6991                 intel_crtc->lut_b[i] = i;
6992         }
6993
6994         /* Swap pipes & planes for FBC on pre-965 */
6995         intel_crtc->pipe = pipe;
6996         intel_crtc->plane = pipe;
6997         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6998                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6999                 intel_crtc->plane = !pipe;
7000         }
7001
7002         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7003                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7004         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7005         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7006
7007         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7008
7009         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7010 }
7011
7012 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7013                                 struct drm_file *file)
7014 {
7015         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7016         struct drm_mode_object *drmmode_obj;
7017         struct intel_crtc *crtc;
7018
7019         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7020                 return -ENODEV;
7021
7022         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7023                         DRM_MODE_OBJECT_CRTC);
7024
7025         if (!drmmode_obj) {
7026                 DRM_ERROR("no such CRTC id\n");
7027                 return -EINVAL;
7028         }
7029
7030         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7031         pipe_from_crtc_id->pipe = crtc->pipe;
7032
7033         return 0;
7034 }
7035
7036 static int intel_encoder_clones(struct intel_encoder *encoder)
7037 {
7038         struct drm_device *dev = encoder->base.dev;
7039         struct intel_encoder *source_encoder;
7040         int index_mask = 0;
7041         int entry = 0;
7042
7043         list_for_each_entry(source_encoder,
7044                             &dev->mode_config.encoder_list, base.head) {
7045
7046                 if (encoder == source_encoder)
7047                         index_mask |= (1 << entry);
7048
7049                 /* Intel hw has only one MUX where enocoders could be cloned. */
7050                 if (encoder->cloneable && source_encoder->cloneable)
7051                         index_mask |= (1 << entry);
7052
7053                 entry++;
7054         }
7055
7056         return index_mask;
7057 }
7058
7059 static bool has_edp_a(struct drm_device *dev)
7060 {
7061         struct drm_i915_private *dev_priv = dev->dev_private;
7062
7063         if (!IS_MOBILE(dev))
7064                 return false;
7065
7066         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7067                 return false;
7068
7069         if (IS_GEN5(dev) &&
7070             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7071                 return false;
7072
7073         return true;
7074 }
7075
7076 static void intel_setup_outputs(struct drm_device *dev)
7077 {
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         struct intel_encoder *encoder;
7080         bool dpd_is_edp = false;
7081         bool has_lvds;
7082
7083         has_lvds = intel_lvds_init(dev);
7084         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7085                 /* disable the panel fitter on everything but LVDS */
7086                 I915_WRITE(PFIT_CONTROL, 0);
7087         }
7088
7089         if (HAS_PCH_SPLIT(dev)) {
7090                 dpd_is_edp = intel_dpd_is_edp(dev);
7091
7092                 if (has_edp_a(dev))
7093                         intel_dp_init(dev, DP_A, PORT_A);
7094
7095                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7096                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7097         }
7098
7099         intel_crt_init(dev);
7100
7101         if (IS_HASWELL(dev)) {
7102                 int found;
7103
7104                 /* Haswell uses DDI functions to detect digital outputs */
7105                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7106                 /* DDI A only supports eDP */
7107                 if (found)
7108                         intel_ddi_init(dev, PORT_A);
7109
7110                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7111                  * register */
7112                 found = I915_READ(SFUSE_STRAP);
7113
7114                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7115                         intel_ddi_init(dev, PORT_B);
7116                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7117                         intel_ddi_init(dev, PORT_C);
7118                 if (found & SFUSE_STRAP_DDID_DETECTED)
7119                         intel_ddi_init(dev, PORT_D);
7120         } else if (HAS_PCH_SPLIT(dev)) {
7121                 int found;
7122
7123                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7124                         /* PCH SDVOB multiplex with HDMIB */
7125                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7126                         if (!found)
7127                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7128                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7129                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7130                 }
7131
7132                 if (I915_READ(HDMIC) & PORT_DETECTED)
7133                         intel_hdmi_init(dev, HDMIC, PORT_C);
7134
7135                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7136                         intel_hdmi_init(dev, HDMID, PORT_D);
7137
7138                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7139                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7140
7141                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7142                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7143         } else if (IS_VALLEYVIEW(dev)) {
7144                 int found;
7145
7146                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7147                         /* SDVOB multiplex with HDMIB */
7148                         found = intel_sdvo_init(dev, SDVOB, true);
7149                         if (!found)
7150                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7151                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7152                                 intel_dp_init(dev, DP_B, PORT_B);
7153                 }
7154
7155                 if (I915_READ(SDVOC) & PORT_DETECTED)
7156                         intel_hdmi_init(dev, SDVOC, PORT_C);
7157
7158                 /* Shares lanes with HDMI on SDVOC */
7159                 if (I915_READ(DP_C) & DP_DETECTED)
7160                         intel_dp_init(dev, DP_C, PORT_C);
7161         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7162                 bool found = false;
7163
7164                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7165                         DRM_DEBUG_KMS("probing SDVOB\n");
7166                         found = intel_sdvo_init(dev, SDVOB, true);
7167                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7168                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7169                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7170                         }
7171
7172                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7173                                 DRM_DEBUG_KMS("probing DP_B\n");
7174                                 intel_dp_init(dev, DP_B, PORT_B);
7175                         }
7176                 }
7177
7178                 /* Before G4X SDVOC doesn't have its own detect register */
7179
7180                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7181                         DRM_DEBUG_KMS("probing SDVOC\n");
7182                         found = intel_sdvo_init(dev, SDVOC, false);
7183                 }
7184
7185                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7186
7187                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7188                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7189                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7190                         }
7191                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7192                                 DRM_DEBUG_KMS("probing DP_C\n");
7193                                 intel_dp_init(dev, DP_C, PORT_C);
7194                         }
7195                 }
7196
7197                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7198                     (I915_READ(DP_D) & DP_DETECTED)) {
7199                         DRM_DEBUG_KMS("probing DP_D\n");
7200                         intel_dp_init(dev, DP_D, PORT_D);
7201                 }
7202         } else if (IS_GEN2(dev))
7203                 intel_dvo_init(dev);
7204
7205         if (SUPPORTS_TV(dev))
7206                 intel_tv_init(dev);
7207
7208         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7209                 encoder->base.possible_crtcs = encoder->crtc_mask;
7210                 encoder->base.possible_clones =
7211                         intel_encoder_clones(encoder);
7212         }
7213
7214         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7215                 ironlake_init_pch_refclk(dev);
7216 }
7217
7218 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7219 {
7220         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7221
7222         drm_framebuffer_cleanup(fb);
7223         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7224
7225         kfree(intel_fb);
7226 }
7227
7228 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7229                                                 struct drm_file *file,
7230                                                 unsigned int *handle)
7231 {
7232         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7233         struct drm_i915_gem_object *obj = intel_fb->obj;
7234
7235         return drm_gem_handle_create(file, &obj->base, handle);
7236 }
7237
7238 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7239         .destroy = intel_user_framebuffer_destroy,
7240         .create_handle = intel_user_framebuffer_create_handle,
7241 };
7242
7243 int intel_framebuffer_init(struct drm_device *dev,
7244                            struct intel_framebuffer *intel_fb,
7245                            struct drm_mode_fb_cmd2 *mode_cmd,
7246                            struct drm_i915_gem_object *obj)
7247 {
7248         int ret;
7249
7250         if (obj->tiling_mode == I915_TILING_Y)
7251                 return -EINVAL;
7252
7253         if (mode_cmd->pitches[0] & 63)
7254                 return -EINVAL;
7255
7256         switch (mode_cmd->pixel_format) {
7257         case DRM_FORMAT_RGB332:
7258         case DRM_FORMAT_RGB565:
7259         case DRM_FORMAT_XRGB8888:
7260         case DRM_FORMAT_XBGR8888:
7261         case DRM_FORMAT_ARGB8888:
7262         case DRM_FORMAT_XRGB2101010:
7263         case DRM_FORMAT_ARGB2101010:
7264                 /* RGB formats are common across chipsets */
7265                 break;
7266         case DRM_FORMAT_YUYV:
7267         case DRM_FORMAT_UYVY:
7268         case DRM_FORMAT_YVYU:
7269         case DRM_FORMAT_VYUY:
7270                 break;
7271         default:
7272                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7273                                 mode_cmd->pixel_format);
7274                 return -EINVAL;
7275         }
7276
7277         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7278         if (ret) {
7279                 DRM_ERROR("framebuffer init failed %d\n", ret);
7280                 return ret;
7281         }
7282
7283         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7284         intel_fb->obj = obj;
7285         return 0;
7286 }
7287
7288 static struct drm_framebuffer *
7289 intel_user_framebuffer_create(struct drm_device *dev,
7290                               struct drm_file *filp,
7291                               struct drm_mode_fb_cmd2 *mode_cmd)
7292 {
7293         struct drm_i915_gem_object *obj;
7294
7295         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7296                                                 mode_cmd->handles[0]));
7297         if (&obj->base == NULL)
7298                 return ERR_PTR(-ENOENT);
7299
7300         return intel_framebuffer_create(dev, mode_cmd, obj);
7301 }
7302
7303 static const struct drm_mode_config_funcs intel_mode_funcs = {
7304         .fb_create = intel_user_framebuffer_create,
7305         .output_poll_changed = intel_fb_output_poll_changed,
7306 };
7307
7308 /* Set up chip specific display functions */
7309 static void intel_init_display(struct drm_device *dev)
7310 {
7311         struct drm_i915_private *dev_priv = dev->dev_private;
7312
7313         /* We always want a DPMS function */
7314         if (HAS_PCH_SPLIT(dev)) {
7315                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7316                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7317                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7318                 dev_priv->display.off = ironlake_crtc_off;
7319                 dev_priv->display.update_plane = ironlake_update_plane;
7320         } else {
7321                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7322                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7323                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7324                 dev_priv->display.off = i9xx_crtc_off;
7325                 dev_priv->display.update_plane = i9xx_update_plane;
7326         }
7327
7328         /* Returns the core display clock speed */
7329         if (IS_VALLEYVIEW(dev))
7330                 dev_priv->display.get_display_clock_speed =
7331                         valleyview_get_display_clock_speed;
7332         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7333                 dev_priv->display.get_display_clock_speed =
7334                         i945_get_display_clock_speed;
7335         else if (IS_I915G(dev))
7336                 dev_priv->display.get_display_clock_speed =
7337                         i915_get_display_clock_speed;
7338         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7339                 dev_priv->display.get_display_clock_speed =
7340                         i9xx_misc_get_display_clock_speed;
7341         else if (IS_I915GM(dev))
7342                 dev_priv->display.get_display_clock_speed =
7343                         i915gm_get_display_clock_speed;
7344         else if (IS_I865G(dev))
7345                 dev_priv->display.get_display_clock_speed =
7346                         i865_get_display_clock_speed;
7347         else if (IS_I85X(dev))
7348                 dev_priv->display.get_display_clock_speed =
7349                         i855_get_display_clock_speed;
7350         else /* 852, 830 */
7351                 dev_priv->display.get_display_clock_speed =
7352                         i830_get_display_clock_speed;
7353
7354         if (HAS_PCH_SPLIT(dev)) {
7355                 if (IS_GEN5(dev)) {
7356                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7357                         dev_priv->display.write_eld = ironlake_write_eld;
7358                 } else if (IS_GEN6(dev)) {
7359                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7360                         dev_priv->display.write_eld = ironlake_write_eld;
7361                 } else if (IS_IVYBRIDGE(dev)) {
7362                         /* FIXME: detect B0+ stepping and use auto training */
7363                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7364                         dev_priv->display.write_eld = ironlake_write_eld;
7365                 } else if (IS_HASWELL(dev)) {
7366                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7367                         dev_priv->display.write_eld = haswell_write_eld;
7368                 } else
7369                         dev_priv->display.update_wm = NULL;
7370         } else if (IS_G4X(dev)) {
7371                 dev_priv->display.write_eld = g4x_write_eld;
7372         }
7373
7374         /* Default just returns -ENODEV to indicate unsupported */
7375         dev_priv->display.queue_flip = intel_default_queue_flip;
7376
7377         switch (INTEL_INFO(dev)->gen) {
7378         case 2:
7379                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7380                 break;
7381
7382         case 3:
7383                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7384                 break;
7385
7386         case 4:
7387         case 5:
7388                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7389                 break;
7390
7391         case 6:
7392                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7393                 break;
7394         case 7:
7395                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7396                 break;
7397         }
7398 }
7399
7400 /*
7401  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7402  * resume, or other times.  This quirk makes sure that's the case for
7403  * affected systems.
7404  */
7405 static void quirk_pipea_force(struct drm_device *dev)
7406 {
7407         struct drm_i915_private *dev_priv = dev->dev_private;
7408
7409         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7410         DRM_INFO("applying pipe a force quirk\n");
7411 }
7412
7413 /*
7414  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7415  */
7416 static void quirk_ssc_force_disable(struct drm_device *dev)
7417 {
7418         struct drm_i915_private *dev_priv = dev->dev_private;
7419         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7420         DRM_INFO("applying lvds SSC disable quirk\n");
7421 }
7422
7423 /*
7424  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7425  * brightness value
7426  */
7427 static void quirk_invert_brightness(struct drm_device *dev)
7428 {
7429         struct drm_i915_private *dev_priv = dev->dev_private;
7430         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7431         DRM_INFO("applying inverted panel brightness quirk\n");
7432 }
7433
7434 struct intel_quirk {
7435         int device;
7436         int subsystem_vendor;
7437         int subsystem_device;
7438         void (*hook)(struct drm_device *dev);
7439 };
7440
7441 static struct intel_quirk intel_quirks[] = {
7442         /* HP Mini needs pipe A force quirk (LP: #322104) */
7443         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7444
7445         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7446         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7447
7448         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7449         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7450
7451         /* 855 & before need to leave pipe A & dpll A up */
7452         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7453         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7454         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7455
7456         /* Lenovo U160 cannot use SSC on LVDS */
7457         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7458
7459         /* Sony Vaio Y cannot use SSC on LVDS */
7460         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7461
7462         /* Acer Aspire 5734Z must invert backlight brightness */
7463         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7464 };
7465
7466 static void intel_init_quirks(struct drm_device *dev)
7467 {
7468         struct pci_dev *d = dev->pdev;
7469         int i;
7470
7471         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7472                 struct intel_quirk *q = &intel_quirks[i];
7473
7474                 if (d->device == q->device &&
7475                     (d->subsystem_vendor == q->subsystem_vendor ||
7476                      q->subsystem_vendor == PCI_ANY_ID) &&
7477                     (d->subsystem_device == q->subsystem_device ||
7478                      q->subsystem_device == PCI_ANY_ID))
7479                         q->hook(dev);
7480         }
7481 }
7482
7483 /* Disable the VGA plane that we never use */
7484 static void i915_disable_vga(struct drm_device *dev)
7485 {
7486         struct drm_i915_private *dev_priv = dev->dev_private;
7487         u8 sr1;
7488         u32 vga_reg;
7489
7490         if (HAS_PCH_SPLIT(dev))
7491                 vga_reg = CPU_VGACNTRL;
7492         else
7493                 vga_reg = VGACNTRL;
7494
7495         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7496         outb(SR01, VGA_SR_INDEX);
7497         sr1 = inb(VGA_SR_DATA);
7498         outb(sr1 | 1<<5, VGA_SR_DATA);
7499         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7500         udelay(300);
7501
7502         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7503         POSTING_READ(vga_reg);
7504 }
7505
7506 void intel_modeset_init_hw(struct drm_device *dev)
7507 {
7508         /* We attempt to init the necessary power wells early in the initialization
7509          * time, so the subsystems that expect power to be enabled can work.
7510          */
7511         intel_init_power_wells(dev);
7512
7513         intel_prepare_ddi(dev);
7514
7515         intel_init_clock_gating(dev);
7516
7517         mutex_lock(&dev->struct_mutex);
7518         intel_enable_gt_powersave(dev);
7519         mutex_unlock(&dev->struct_mutex);
7520 }
7521
7522 void intel_modeset_init(struct drm_device *dev)
7523 {
7524         struct drm_i915_private *dev_priv = dev->dev_private;
7525         int i, ret;
7526
7527         drm_mode_config_init(dev);
7528
7529         dev->mode_config.min_width = 0;
7530         dev->mode_config.min_height = 0;
7531
7532         dev->mode_config.preferred_depth = 24;
7533         dev->mode_config.prefer_shadow = 1;
7534
7535         dev->mode_config.funcs = &intel_mode_funcs;
7536
7537         intel_init_quirks(dev);
7538
7539         intel_init_pm(dev);
7540
7541         intel_init_display(dev);
7542
7543         if (IS_GEN2(dev)) {
7544                 dev->mode_config.max_width = 2048;
7545                 dev->mode_config.max_height = 2048;
7546         } else if (IS_GEN3(dev)) {
7547                 dev->mode_config.max_width = 4096;
7548                 dev->mode_config.max_height = 4096;
7549         } else {
7550                 dev->mode_config.max_width = 8192;
7551                 dev->mode_config.max_height = 8192;
7552         }
7553         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7554
7555         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7556                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7557
7558         for (i = 0; i < dev_priv->num_pipe; i++) {
7559                 intel_crtc_init(dev, i);
7560                 ret = intel_plane_init(dev, i);
7561                 if (ret)
7562                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7563         }
7564
7565         intel_pch_pll_init(dev);
7566
7567         /* Just disable it once at startup */
7568         i915_disable_vga(dev);
7569         intel_setup_outputs(dev);
7570 }
7571
7572 static void
7573 intel_connector_break_all_links(struct intel_connector *connector)
7574 {
7575         connector->base.dpms = DRM_MODE_DPMS_OFF;
7576         connector->base.encoder = NULL;
7577         connector->encoder->connectors_active = false;
7578         connector->encoder->base.crtc = NULL;
7579 }
7580
7581 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7582 {
7583         struct drm_device *dev = crtc->base.dev;
7584         struct drm_i915_private *dev_priv = dev->dev_private;
7585         u32 reg, val;
7586
7587         /* Clear the dpms state for compatibility with code still using that
7588          * deprecated state variable. */
7589         crtc->dpms_mode = -1;
7590
7591         /* Clear any frame start delays used for debugging left by the BIOS */
7592         reg = PIPECONF(crtc->pipe);
7593         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7594
7595         /* We need to sanitize the plane -> pipe mapping first because this will
7596          * disable the crtc (and hence change the state) if it is wrong. */
7597         if (!HAS_PCH_SPLIT(dev)) {
7598                 struct intel_connector *connector;
7599                 bool plane;
7600
7601                 reg = DSPCNTR(crtc->plane);
7602                 val = I915_READ(reg);
7603
7604                 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7605                     (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7606                         goto ok;
7607
7608                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7609                               crtc->base.base.id);
7610
7611                 /* Pipe has the wrong plane attached and the plane is active.
7612                  * Temporarily change the plane mapping and disable everything
7613                  * ...  */
7614                 plane = crtc->plane;
7615                 crtc->plane = !plane;
7616                 dev_priv->display.crtc_disable(&crtc->base);
7617                 crtc->plane = plane;
7618
7619                 /* ... and break all links. */
7620                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621                                     base.head) {
7622                         if (connector->encoder->base.crtc != &crtc->base)
7623                                 continue;
7624
7625                         intel_connector_break_all_links(connector);
7626                 }
7627
7628                 WARN_ON(crtc->active);
7629                 crtc->base.enabled = false;
7630         }
7631 ok:
7632
7633         /* Adjust the state of the output pipe according to whether we
7634          * have active connectors/encoders. */
7635         intel_crtc_update_dpms(&crtc->base);
7636
7637         if (crtc->active != crtc->base.enabled) {
7638                 struct intel_encoder *encoder;
7639
7640                 /* This can happen either due to bugs in the get_hw_state
7641                  * functions or because the pipe is force-enabled due to the
7642                  * pipe A quirk. */
7643                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7644                               crtc->base.base.id,
7645                               crtc->base.enabled ? "enabled" : "disabled",
7646                               crtc->active ? "enabled" : "disabled");
7647
7648                 crtc->base.enabled = crtc->active;
7649
7650                 /* Because we only establish the connector -> encoder ->
7651                  * crtc links if something is active, this means the
7652                  * crtc is now deactivated. Break the links. connector
7653                  * -> encoder links are only establish when things are
7654                  *  actually up, hence no need to break them. */
7655                 WARN_ON(crtc->active);
7656
7657                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7658                         WARN_ON(encoder->connectors_active);
7659                         encoder->base.crtc = NULL;
7660                 }
7661         }
7662 }
7663
7664 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7665 {
7666         struct intel_connector *connector;
7667         struct drm_device *dev = encoder->base.dev;
7668
7669         /* We need to check both for a crtc link (meaning that the
7670          * encoder is active and trying to read from a pipe) and the
7671          * pipe itself being active. */
7672         bool has_active_crtc = encoder->base.crtc &&
7673                 to_intel_crtc(encoder->base.crtc)->active;
7674
7675         if (encoder->connectors_active && !has_active_crtc) {
7676                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7677                               encoder->base.base.id,
7678                               drm_get_encoder_name(&encoder->base));
7679
7680                 /* Connector is active, but has no active pipe. This is
7681                  * fallout from our resume register restoring. Disable
7682                  * the encoder manually again. */
7683                 if (encoder->base.crtc) {
7684                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7685                                       encoder->base.base.id,
7686                                       drm_get_encoder_name(&encoder->base));
7687                         encoder->disable(encoder);
7688                 }
7689
7690                 /* Inconsistent output/port/pipe state happens presumably due to
7691                  * a bug in one of the get_hw_state functions. Or someplace else
7692                  * in our code, like the register restore mess on resume. Clamp
7693                  * things to off as a safer default. */
7694                 list_for_each_entry(connector,
7695                                     &dev->mode_config.connector_list,
7696                                     base.head) {
7697                         if (connector->encoder != encoder)
7698                                 continue;
7699
7700                         intel_connector_break_all_links(connector);
7701                 }
7702         }
7703         /* Enabled encoders without active connectors will be fixed in
7704          * the crtc fixup. */
7705 }
7706
7707 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7708  * and i915 state tracking structures. */
7709 void intel_modeset_setup_hw_state(struct drm_device *dev)
7710 {
7711         struct drm_i915_private *dev_priv = dev->dev_private;
7712         enum pipe pipe;
7713         u32 tmp;
7714         struct intel_crtc *crtc;
7715         struct intel_encoder *encoder;
7716         struct intel_connector *connector;
7717
7718         for_each_pipe(pipe) {
7719                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7720
7721                 tmp = I915_READ(PIPECONF(pipe));
7722                 if (tmp & PIPECONF_ENABLE)
7723                         crtc->active = true;
7724                 else
7725                         crtc->active = false;
7726
7727                 crtc->base.enabled = crtc->active;
7728
7729                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7730                               crtc->base.base.id,
7731                               crtc->active ? "enabled" : "disabled");
7732         }
7733
7734         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7735                             base.head) {
7736                 pipe = 0;
7737
7738                 if (encoder->get_hw_state(encoder, &pipe)) {
7739                         encoder->base.crtc =
7740                                 dev_priv->pipe_to_crtc_mapping[pipe];
7741                 } else {
7742                         encoder->base.crtc = NULL;
7743                 }
7744
7745                 encoder->connectors_active = false;
7746                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7747                               encoder->base.base.id,
7748                               drm_get_encoder_name(&encoder->base),
7749                               encoder->base.crtc ? "enabled" : "disabled",
7750                               pipe);
7751         }
7752
7753         list_for_each_entry(connector, &dev->mode_config.connector_list,
7754                             base.head) {
7755                 if (connector->get_hw_state(connector)) {
7756                         connector->base.dpms = DRM_MODE_DPMS_ON;
7757                         connector->encoder->connectors_active = true;
7758                         connector->base.encoder = &connector->encoder->base;
7759                 } else {
7760                         connector->base.dpms = DRM_MODE_DPMS_OFF;
7761                         connector->base.encoder = NULL;
7762                 }
7763                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7764                               connector->base.base.id,
7765                               drm_get_connector_name(&connector->base),
7766                               connector->base.encoder ? "enabled" : "disabled");
7767         }
7768
7769         /* HW state is read out, now we need to sanitize this mess. */
7770         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7771                             base.head) {
7772                 intel_sanitize_encoder(encoder);
7773         }
7774
7775         for_each_pipe(pipe) {
7776                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7777                 intel_sanitize_crtc(crtc);
7778         }
7779 }
7780
7781 void intel_modeset_gem_init(struct drm_device *dev)
7782 {
7783         intel_modeset_init_hw(dev);
7784
7785         intel_setup_overlay(dev);
7786
7787         intel_modeset_setup_hw_state(dev);
7788 }
7789
7790 void intel_modeset_cleanup(struct drm_device *dev)
7791 {
7792         struct drm_i915_private *dev_priv = dev->dev_private;
7793         struct drm_crtc *crtc;
7794         struct intel_crtc *intel_crtc;
7795
7796         drm_kms_helper_poll_fini(dev);
7797         mutex_lock(&dev->struct_mutex);
7798
7799         intel_unregister_dsm_handler();
7800
7801
7802         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7803                 /* Skip inactive CRTCs */
7804                 if (!crtc->fb)
7805                         continue;
7806
7807                 intel_crtc = to_intel_crtc(crtc);
7808                 intel_increase_pllclock(crtc);
7809         }
7810
7811         intel_disable_fbc(dev);
7812
7813         intel_disable_gt_powersave(dev);
7814
7815         ironlake_teardown_rc6(dev);
7816
7817         if (IS_VALLEYVIEW(dev))
7818                 vlv_init_dpio(dev);
7819
7820         mutex_unlock(&dev->struct_mutex);
7821
7822         /* Disable the irq before mode object teardown, for the irq might
7823          * enqueue unpin/hotplug work. */
7824         drm_irq_uninstall(dev);
7825         cancel_work_sync(&dev_priv->hotplug_work);
7826         cancel_work_sync(&dev_priv->rps.work);
7827
7828         /* flush any delayed tasks or pending work */
7829         flush_scheduled_work();
7830
7831         drm_mode_config_cleanup(dev);
7832 }
7833
7834 /*
7835  * Return which encoder is currently attached for connector.
7836  */
7837 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7838 {
7839         return &intel_attached_encoder(connector)->base;
7840 }
7841
7842 void intel_connector_attach_encoder(struct intel_connector *connector,
7843                                     struct intel_encoder *encoder)
7844 {
7845         connector->encoder = encoder;
7846         drm_mode_connector_attach_encoder(&connector->base,
7847                                           &encoder->base);
7848 }
7849
7850 /*
7851  * set vga decode state - true == enable VGA decode
7852  */
7853 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7854 {
7855         struct drm_i915_private *dev_priv = dev->dev_private;
7856         u16 gmch_ctrl;
7857
7858         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7859         if (state)
7860                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7861         else
7862                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7863         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7864         return 0;
7865 }
7866
7867 #ifdef CONFIG_DEBUG_FS
7868 #include <linux/seq_file.h>
7869
7870 struct intel_display_error_state {
7871         struct intel_cursor_error_state {
7872                 u32 control;
7873                 u32 position;
7874                 u32 base;
7875                 u32 size;
7876         } cursor[I915_MAX_PIPES];
7877
7878         struct intel_pipe_error_state {
7879                 u32 conf;
7880                 u32 source;
7881
7882                 u32 htotal;
7883                 u32 hblank;
7884                 u32 hsync;
7885                 u32 vtotal;
7886                 u32 vblank;
7887                 u32 vsync;
7888         } pipe[I915_MAX_PIPES];
7889
7890         struct intel_plane_error_state {
7891                 u32 control;
7892                 u32 stride;
7893                 u32 size;
7894                 u32 pos;
7895                 u32 addr;
7896                 u32 surface;
7897                 u32 tile_offset;
7898         } plane[I915_MAX_PIPES];
7899 };
7900
7901 struct intel_display_error_state *
7902 intel_display_capture_error_state(struct drm_device *dev)
7903 {
7904         drm_i915_private_t *dev_priv = dev->dev_private;
7905         struct intel_display_error_state *error;
7906         int i;
7907
7908         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7909         if (error == NULL)
7910                 return NULL;
7911
7912         for_each_pipe(i) {
7913                 error->cursor[i].control = I915_READ(CURCNTR(i));
7914                 error->cursor[i].position = I915_READ(CURPOS(i));
7915                 error->cursor[i].base = I915_READ(CURBASE(i));
7916
7917                 error->plane[i].control = I915_READ(DSPCNTR(i));
7918                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7919                 error->plane[i].size = I915_READ(DSPSIZE(i));
7920                 error->plane[i].pos = I915_READ(DSPPOS(i));
7921                 error->plane[i].addr = I915_READ(DSPADDR(i));
7922                 if (INTEL_INFO(dev)->gen >= 4) {
7923                         error->plane[i].surface = I915_READ(DSPSURF(i));
7924                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7925                 }
7926
7927                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7928                 error->pipe[i].source = I915_READ(PIPESRC(i));
7929                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7930                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7931                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7932                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7933                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7934                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7935         }
7936
7937         return error;
7938 }
7939
7940 void
7941 intel_display_print_error_state(struct seq_file *m,
7942                                 struct drm_device *dev,
7943                                 struct intel_display_error_state *error)
7944 {
7945         drm_i915_private_t *dev_priv = dev->dev_private;
7946         int i;
7947
7948         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7949         for_each_pipe(i) {
7950                 seq_printf(m, "Pipe [%d]:\n", i);
7951                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7952                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7953                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7954                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7955                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7956                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7957                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7958                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7959
7960                 seq_printf(m, "Plane [%d]:\n", i);
7961                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7962                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7963                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7964                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7965                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7966                 if (INTEL_INFO(dev)->gen >= 4) {
7967                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7968                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7969                 }
7970
7971                 seq_printf(m, "Cursor [%d]:\n", i);
7972                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7973                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7974                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7975         }
7976 }
7977 #endif