Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum transcoder cpu_transcoder)
1722 {
1723         u32 val, pipeconf_val;
1724
1725         /* PCH only available on ILK+ */
1726         BUG_ON(dev_priv->info->gen < 5);
1727
1728         /* FDI must be feeding us bits for PCH ports */
1729         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1731
1732         /* Workaround: set timing override bit. */
1733         val = I915_READ(_TRANSA_CHICKEN2);
1734         val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
1735         I915_WRITE(_TRANSA_CHICKEN2, val);
1736
1737         val = TRANS_ENABLE;
1738         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1739
1740         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1741             PIPECONF_INTERLACED_ILK)
1742                 val |= TRANS_INTERLACED;
1743         else
1744                 val |= TRANS_PROGRESSIVE;
1745
1746         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1747         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1748                 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 }
1750
1751 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1752                                             enum pipe pipe)
1753 {
1754         int reg;
1755         u32 val;
1756
1757         /* FDI relies on the transcoder */
1758         assert_fdi_tx_disabled(dev_priv, pipe);
1759         assert_fdi_rx_disabled(dev_priv, pipe);
1760
1761         /* Ports must be off as well */
1762         assert_pch_ports_disabled(dev_priv, pipe);
1763
1764         reg = TRANSCONF(pipe);
1765         val = I915_READ(reg);
1766         val &= ~TRANS_ENABLE;
1767         I915_WRITE(reg, val);
1768         /* wait for PCH transcoder off, transcoder state */
1769         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1770                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1771 }
1772
1773 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1774                                        enum transcoder cpu_transcoder)
1775 {
1776         u32 val;
1777
1778         /* FDI relies on the transcoder */
1779         assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
1780         assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
1781
1782         val = I915_READ(_TRANSACONF);
1783         val &= ~TRANS_ENABLE;
1784         I915_WRITE(_TRANSACONF, val);
1785         /* wait for PCH transcoder off, transcoder state */
1786         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1787                 DRM_ERROR("Failed to disable PCH transcoder\n");
1788
1789         /* Workaround: clear timing override bit. */
1790         val = I915_READ(_TRANSA_CHICKEN2);
1791         val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
1792         I915_WRITE(_TRANSA_CHICKEN2, val);
1793 }
1794
1795 /**
1796  * intel_enable_pipe - enable a pipe, asserting requirements
1797  * @dev_priv: i915 private structure
1798  * @pipe: pipe to enable
1799  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1800  *
1801  * Enable @pipe, making sure that various hardware specific requirements
1802  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1803  *
1804  * @pipe should be %PIPE_A or %PIPE_B.
1805  *
1806  * Will wait until the pipe is actually running (i.e. first vblank) before
1807  * returning.
1808  */
1809 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1810                               bool pch_port)
1811 {
1812         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1813                                                                       pipe);
1814         int reg;
1815         u32 val;
1816
1817         /*
1818          * A pipe without a PLL won't actually be able to drive bits from
1819          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1820          * need the check.
1821          */
1822         if (!HAS_PCH_SPLIT(dev_priv->dev))
1823                 assert_pll_enabled(dev_priv, pipe);
1824         else {
1825                 if (pch_port) {
1826                         /* if driving the PCH, we need FDI enabled */
1827                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1828                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1829                 }
1830                 /* FIXME: assert CPU port conditions for SNB+ */
1831         }
1832
1833         reg = PIPECONF(cpu_transcoder);
1834         val = I915_READ(reg);
1835         if (val & PIPECONF_ENABLE)
1836                 return;
1837
1838         I915_WRITE(reg, val | PIPECONF_ENABLE);
1839         intel_wait_for_vblank(dev_priv->dev, pipe);
1840 }
1841
1842 /**
1843  * intel_disable_pipe - disable a pipe, asserting requirements
1844  * @dev_priv: i915 private structure
1845  * @pipe: pipe to disable
1846  *
1847  * Disable @pipe, making sure that various hardware specific requirements
1848  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1849  *
1850  * @pipe should be %PIPE_A or %PIPE_B.
1851  *
1852  * Will wait until the pipe has shut down before returning.
1853  */
1854 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1855                                enum pipe pipe)
1856 {
1857         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1858                                                                       pipe);
1859         int reg;
1860         u32 val;
1861
1862         /*
1863          * Make sure planes won't keep trying to pump pixels to us,
1864          * or we might hang the display.
1865          */
1866         assert_planes_disabled(dev_priv, pipe);
1867
1868         /* Don't disable pipe A or pipe A PLLs if needed */
1869         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1870                 return;
1871
1872         reg = PIPECONF(cpu_transcoder);
1873         val = I915_READ(reg);
1874         if ((val & PIPECONF_ENABLE) == 0)
1875                 return;
1876
1877         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1878         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1879 }
1880
1881 /*
1882  * Plane regs are double buffered, going from enabled->disabled needs a
1883  * trigger in order to latch.  The display address reg provides this.
1884  */
1885 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1886                                       enum plane plane)
1887 {
1888         if (dev_priv->info->gen >= 4)
1889                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1890         else
1891                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1892 }
1893
1894 /**
1895  * intel_enable_plane - enable a display plane on a given pipe
1896  * @dev_priv: i915 private structure
1897  * @plane: plane to enable
1898  * @pipe: pipe being fed
1899  *
1900  * Enable @plane on @pipe, making sure that @pipe is running first.
1901  */
1902 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1903                                enum plane plane, enum pipe pipe)
1904 {
1905         int reg;
1906         u32 val;
1907
1908         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1909         assert_pipe_enabled(dev_priv, pipe);
1910
1911         reg = DSPCNTR(plane);
1912         val = I915_READ(reg);
1913         if (val & DISPLAY_PLANE_ENABLE)
1914                 return;
1915
1916         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1917         intel_flush_display_plane(dev_priv, plane);
1918         intel_wait_for_vblank(dev_priv->dev, pipe);
1919 }
1920
1921 /**
1922  * intel_disable_plane - disable a display plane
1923  * @dev_priv: i915 private structure
1924  * @plane: plane to disable
1925  * @pipe: pipe consuming the data
1926  *
1927  * Disable @plane; should be an independent operation.
1928  */
1929 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1930                                 enum plane plane, enum pipe pipe)
1931 {
1932         int reg;
1933         u32 val;
1934
1935         reg = DSPCNTR(plane);
1936         val = I915_READ(reg);
1937         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1938                 return;
1939
1940         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1941         intel_flush_display_plane(dev_priv, plane);
1942         intel_wait_for_vblank(dev_priv->dev, pipe);
1943 }
1944
1945 int
1946 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1947                            struct drm_i915_gem_object *obj,
1948                            struct intel_ring_buffer *pipelined)
1949 {
1950         struct drm_i915_private *dev_priv = dev->dev_private;
1951         u32 alignment;
1952         int ret;
1953
1954         switch (obj->tiling_mode) {
1955         case I915_TILING_NONE:
1956                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1957                         alignment = 128 * 1024;
1958                 else if (INTEL_INFO(dev)->gen >= 4)
1959                         alignment = 4 * 1024;
1960                 else
1961                         alignment = 64 * 1024;
1962                 break;
1963         case I915_TILING_X:
1964                 /* pin() will align the object as required by fence */
1965                 alignment = 0;
1966                 break;
1967         case I915_TILING_Y:
1968                 /* FIXME: Is this true? */
1969                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1970                 return -EINVAL;
1971         default:
1972                 BUG();
1973         }
1974
1975         dev_priv->mm.interruptible = false;
1976         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1977         if (ret)
1978                 goto err_interruptible;
1979
1980         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1981          * fence, whereas 965+ only requires a fence if using
1982          * framebuffer compression.  For simplicity, we always install
1983          * a fence as the cost is not that onerous.
1984          */
1985         ret = i915_gem_object_get_fence(obj);
1986         if (ret)
1987                 goto err_unpin;
1988
1989         i915_gem_object_pin_fence(obj);
1990
1991         dev_priv->mm.interruptible = true;
1992         return 0;
1993
1994 err_unpin:
1995         i915_gem_object_unpin(obj);
1996 err_interruptible:
1997         dev_priv->mm.interruptible = true;
1998         return ret;
1999 }
2000
2001 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2002 {
2003         i915_gem_object_unpin_fence(obj);
2004         i915_gem_object_unpin(obj);
2005 }
2006
2007 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2008  * is assumed to be a power-of-two. */
2009 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2010                                                unsigned int bpp,
2011                                                unsigned int pitch)
2012 {
2013         int tile_rows, tiles;
2014
2015         tile_rows = *y / 8;
2016         *y %= 8;
2017         tiles = *x / (512/bpp);
2018         *x %= 512/bpp;
2019
2020         return tile_rows * pitch * 8 + tiles * 4096;
2021 }
2022
2023 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2024                              int x, int y)
2025 {
2026         struct drm_device *dev = crtc->dev;
2027         struct drm_i915_private *dev_priv = dev->dev_private;
2028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2029         struct intel_framebuffer *intel_fb;
2030         struct drm_i915_gem_object *obj;
2031         int plane = intel_crtc->plane;
2032         unsigned long linear_offset;
2033         u32 dspcntr;
2034         u32 reg;
2035
2036         switch (plane) {
2037         case 0:
2038         case 1:
2039                 break;
2040         default:
2041                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2042                 return -EINVAL;
2043         }
2044
2045         intel_fb = to_intel_framebuffer(fb);
2046         obj = intel_fb->obj;
2047
2048         reg = DSPCNTR(plane);
2049         dspcntr = I915_READ(reg);
2050         /* Mask out pixel format bits in case we change it */
2051         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2052         switch (fb->pixel_format) {
2053         case DRM_FORMAT_C8:
2054                 dspcntr |= DISPPLANE_8BPP;
2055                 break;
2056         case DRM_FORMAT_XRGB1555:
2057         case DRM_FORMAT_ARGB1555:
2058                 dspcntr |= DISPPLANE_BGRX555;
2059                 break;
2060         case DRM_FORMAT_RGB565:
2061                 dspcntr |= DISPPLANE_BGRX565;
2062                 break;
2063         case DRM_FORMAT_XRGB8888:
2064         case DRM_FORMAT_ARGB8888:
2065                 dspcntr |= DISPPLANE_BGRX888;
2066                 break;
2067         case DRM_FORMAT_XBGR8888:
2068         case DRM_FORMAT_ABGR8888:
2069                 dspcntr |= DISPPLANE_RGBX888;
2070                 break;
2071         case DRM_FORMAT_XRGB2101010:
2072         case DRM_FORMAT_ARGB2101010:
2073                 dspcntr |= DISPPLANE_BGRX101010;
2074                 break;
2075         case DRM_FORMAT_XBGR2101010:
2076         case DRM_FORMAT_ABGR2101010:
2077                 dspcntr |= DISPPLANE_RGBX101010;
2078                 break;
2079         default:
2080                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2081                 return -EINVAL;
2082         }
2083
2084         if (INTEL_INFO(dev)->gen >= 4) {
2085                 if (obj->tiling_mode != I915_TILING_NONE)
2086                         dspcntr |= DISPPLANE_TILED;
2087                 else
2088                         dspcntr &= ~DISPPLANE_TILED;
2089         }
2090
2091         I915_WRITE(reg, dspcntr);
2092
2093         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2094
2095         if (INTEL_INFO(dev)->gen >= 4) {
2096                 intel_crtc->dspaddr_offset =
2097                         intel_gen4_compute_offset_xtiled(&x, &y,
2098                                                          fb->bits_per_pixel / 8,
2099                                                          fb->pitches[0]);
2100                 linear_offset -= intel_crtc->dspaddr_offset;
2101         } else {
2102                 intel_crtc->dspaddr_offset = linear_offset;
2103         }
2104
2105         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2106                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2107         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2108         if (INTEL_INFO(dev)->gen >= 4) {
2109                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2110                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2111                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2112                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2113         } else
2114                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2115         POSTING_READ(reg);
2116
2117         return 0;
2118 }
2119
2120 static int ironlake_update_plane(struct drm_crtc *crtc,
2121                                  struct drm_framebuffer *fb, int x, int y)
2122 {
2123         struct drm_device *dev = crtc->dev;
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126         struct intel_framebuffer *intel_fb;
2127         struct drm_i915_gem_object *obj;
2128         int plane = intel_crtc->plane;
2129         unsigned long linear_offset;
2130         u32 dspcntr;
2131         u32 reg;
2132
2133         switch (plane) {
2134         case 0:
2135         case 1:
2136         case 2:
2137                 break;
2138         default:
2139                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2140                 return -EINVAL;
2141         }
2142
2143         intel_fb = to_intel_framebuffer(fb);
2144         obj = intel_fb->obj;
2145
2146         reg = DSPCNTR(plane);
2147         dspcntr = I915_READ(reg);
2148         /* Mask out pixel format bits in case we change it */
2149         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2150         switch (fb->pixel_format) {
2151         case DRM_FORMAT_C8:
2152                 dspcntr |= DISPPLANE_8BPP;
2153                 break;
2154         case DRM_FORMAT_RGB565:
2155                 dspcntr |= DISPPLANE_BGRX565;
2156                 break;
2157         case DRM_FORMAT_XRGB8888:
2158         case DRM_FORMAT_ARGB8888:
2159                 dspcntr |= DISPPLANE_BGRX888;
2160                 break;
2161         case DRM_FORMAT_XBGR8888:
2162         case DRM_FORMAT_ABGR8888:
2163                 dspcntr |= DISPPLANE_RGBX888;
2164                 break;
2165         case DRM_FORMAT_XRGB2101010:
2166         case DRM_FORMAT_ARGB2101010:
2167                 dspcntr |= DISPPLANE_BGRX101010;
2168                 break;
2169         case DRM_FORMAT_XBGR2101010:
2170         case DRM_FORMAT_ABGR2101010:
2171                 dspcntr |= DISPPLANE_RGBX101010;
2172                 break;
2173         default:
2174                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2175                 return -EINVAL;
2176         }
2177
2178         if (obj->tiling_mode != I915_TILING_NONE)
2179                 dspcntr |= DISPPLANE_TILED;
2180         else
2181                 dspcntr &= ~DISPPLANE_TILED;
2182
2183         /* must disable */
2184         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2185
2186         I915_WRITE(reg, dspcntr);
2187
2188         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2189         intel_crtc->dspaddr_offset =
2190                 intel_gen4_compute_offset_xtiled(&x, &y,
2191                                                  fb->bits_per_pixel / 8,
2192                                                  fb->pitches[0]);
2193         linear_offset -= intel_crtc->dspaddr_offset;
2194
2195         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2196                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2197         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2198         I915_MODIFY_DISPBASE(DSPSURF(plane),
2199                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2200         if (IS_HASWELL(dev)) {
2201                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2202         } else {
2203                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2204                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2205         }
2206         POSTING_READ(reg);
2207
2208         return 0;
2209 }
2210
2211 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2212 static int
2213 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2214                            int x, int y, enum mode_set_atomic state)
2215 {
2216         struct drm_device *dev = crtc->dev;
2217         struct drm_i915_private *dev_priv = dev->dev_private;
2218
2219         if (dev_priv->display.disable_fbc)
2220                 dev_priv->display.disable_fbc(dev);
2221         intel_increase_pllclock(crtc);
2222
2223         return dev_priv->display.update_plane(crtc, fb, x, y);
2224 }
2225
2226 static int
2227 intel_finish_fb(struct drm_framebuffer *old_fb)
2228 {
2229         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2230         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2231         bool was_interruptible = dev_priv->mm.interruptible;
2232         int ret;
2233
2234         wait_event(dev_priv->pending_flip_queue,
2235                    atomic_read(&dev_priv->mm.wedged) ||
2236                    atomic_read(&obj->pending_flip) == 0);
2237
2238         /* Big Hammer, we also need to ensure that any pending
2239          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2240          * current scanout is retired before unpinning the old
2241          * framebuffer.
2242          *
2243          * This should only fail upon a hung GPU, in which case we
2244          * can safely continue.
2245          */
2246         dev_priv->mm.interruptible = false;
2247         ret = i915_gem_object_finish_gpu(obj);
2248         dev_priv->mm.interruptible = was_interruptible;
2249
2250         return ret;
2251 }
2252
2253 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2254 {
2255         struct drm_device *dev = crtc->dev;
2256         struct drm_i915_master_private *master_priv;
2257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2258
2259         if (!dev->primary->master)
2260                 return;
2261
2262         master_priv = dev->primary->master->driver_priv;
2263         if (!master_priv->sarea_priv)
2264                 return;
2265
2266         switch (intel_crtc->pipe) {
2267         case 0:
2268                 master_priv->sarea_priv->pipeA_x = x;
2269                 master_priv->sarea_priv->pipeA_y = y;
2270                 break;
2271         case 1:
2272                 master_priv->sarea_priv->pipeB_x = x;
2273                 master_priv->sarea_priv->pipeB_y = y;
2274                 break;
2275         default:
2276                 break;
2277         }
2278 }
2279
2280 static int
2281 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2282                     struct drm_framebuffer *fb)
2283 {
2284         struct drm_device *dev = crtc->dev;
2285         struct drm_i915_private *dev_priv = dev->dev_private;
2286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287         struct drm_framebuffer *old_fb;
2288         int ret;
2289
2290         /* no fb bound */
2291         if (!fb) {
2292                 DRM_ERROR("No FB bound\n");
2293                 return 0;
2294         }
2295
2296         if(intel_crtc->plane > dev_priv->num_pipe) {
2297                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2298                                 intel_crtc->plane,
2299                                 dev_priv->num_pipe);
2300                 return -EINVAL;
2301         }
2302
2303         mutex_lock(&dev->struct_mutex);
2304         ret = intel_pin_and_fence_fb_obj(dev,
2305                                          to_intel_framebuffer(fb)->obj,
2306                                          NULL);
2307         if (ret != 0) {
2308                 mutex_unlock(&dev->struct_mutex);
2309                 DRM_ERROR("pin & fence failed\n");
2310                 return ret;
2311         }
2312
2313         if (crtc->fb)
2314                 intel_finish_fb(crtc->fb);
2315
2316         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2317         if (ret) {
2318                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("failed to update base address\n");
2321                 return ret;
2322         }
2323
2324         old_fb = crtc->fb;
2325         crtc->fb = fb;
2326         crtc->x = x;
2327         crtc->y = y;
2328
2329         if (old_fb) {
2330                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2331                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2332         }
2333
2334         intel_update_fbc(dev);
2335         mutex_unlock(&dev->struct_mutex);
2336
2337         intel_crtc_update_sarea_pos(crtc, x, y);
2338
2339         return 0;
2340 }
2341
2342 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2343 {
2344         struct drm_device *dev = crtc->dev;
2345         struct drm_i915_private *dev_priv = dev->dev_private;
2346         u32 dpa_ctl;
2347
2348         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2349         dpa_ctl = I915_READ(DP_A);
2350         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2351
2352         if (clock < 200000) {
2353                 u32 temp;
2354                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2355                 /* workaround for 160Mhz:
2356                    1) program 0x4600c bits 15:0 = 0x8124
2357                    2) program 0x46010 bit 0 = 1
2358                    3) program 0x46034 bit 24 = 1
2359                    4) program 0x64000 bit 14 = 1
2360                    */
2361                 temp = I915_READ(0x4600c);
2362                 temp &= 0xffff0000;
2363                 I915_WRITE(0x4600c, temp | 0x8124);
2364
2365                 temp = I915_READ(0x46010);
2366                 I915_WRITE(0x46010, temp | 1);
2367
2368                 temp = I915_READ(0x46034);
2369                 I915_WRITE(0x46034, temp | (1 << 24));
2370         } else {
2371                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2372         }
2373         I915_WRITE(DP_A, dpa_ctl);
2374
2375         POSTING_READ(DP_A);
2376         udelay(500);
2377 }
2378
2379 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2380 {
2381         struct drm_device *dev = crtc->dev;
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2384         int pipe = intel_crtc->pipe;
2385         u32 reg, temp;
2386
2387         /* enable normal train */
2388         reg = FDI_TX_CTL(pipe);
2389         temp = I915_READ(reg);
2390         if (IS_IVYBRIDGE(dev)) {
2391                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2392                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2393         } else {
2394                 temp &= ~FDI_LINK_TRAIN_NONE;
2395                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2396         }
2397         I915_WRITE(reg, temp);
2398
2399         reg = FDI_RX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         if (HAS_PCH_CPT(dev)) {
2402                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2403                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2404         } else {
2405                 temp &= ~FDI_LINK_TRAIN_NONE;
2406                 temp |= FDI_LINK_TRAIN_NONE;
2407         }
2408         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2409
2410         /* wait one idle pattern time */
2411         POSTING_READ(reg);
2412         udelay(1000);
2413
2414         /* IVB wants error correction enabled */
2415         if (IS_IVYBRIDGE(dev))
2416                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2417                            FDI_FE_ERRC_ENABLE);
2418 }
2419
2420 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2421 {
2422         struct drm_i915_private *dev_priv = dev->dev_private;
2423         u32 flags = I915_READ(SOUTH_CHICKEN1);
2424
2425         flags |= FDI_PHASE_SYNC_OVR(pipe);
2426         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2427         flags |= FDI_PHASE_SYNC_EN(pipe);
2428         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2429         POSTING_READ(SOUTH_CHICKEN1);
2430 }
2431
2432 static void ivb_modeset_global_resources(struct drm_device *dev)
2433 {
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *pipe_B_crtc =
2436                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2437         struct intel_crtc *pipe_C_crtc =
2438                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2439         uint32_t temp;
2440
2441         /* When everything is off disable fdi C so that we could enable fdi B
2442          * with all lanes. XXX: This misses the case where a pipe is not using
2443          * any pch resources and so doesn't need any fdi lanes. */
2444         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2445                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447
2448                 temp = I915_READ(SOUTH_CHICKEN1);
2449                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451                 I915_WRITE(SOUTH_CHICKEN1, temp);
2452         }
2453 }
2454
2455 /* The FDI link training functions for ILK/Ibexpeak. */
2456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457 {
2458         struct drm_device *dev = crtc->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461         int pipe = intel_crtc->pipe;
2462         int plane = intel_crtc->plane;
2463         u32 reg, temp, tries;
2464
2465         /* FDI needs bits from pipe & plane first */
2466         assert_pipe_enabled(dev_priv, pipe);
2467         assert_plane_enabled(dev_priv, plane);
2468
2469         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470            for train result */
2471         reg = FDI_RX_IMR(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_RX_SYMBOL_LOCK;
2474         temp &= ~FDI_RX_BIT_LOCK;
2475         I915_WRITE(reg, temp);
2476         I915_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~(7 << 19);
2483         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2487
2488         reg = FDI_RX_CTL(pipe);
2489         temp = I915_READ(reg);
2490         temp &= ~FDI_LINK_TRAIN_NONE;
2491         temp |= FDI_LINK_TRAIN_PATTERN_1;
2492         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494         POSTING_READ(reg);
2495         udelay(150);
2496
2497         /* Ironlake workaround, enable clock pointer after FDI enable*/
2498         if (HAS_PCH_IBX(dev)) {
2499                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501                            FDI_RX_PHASE_SYNC_POINTER_EN);
2502         }
2503
2504         reg = FDI_RX_IIR(pipe);
2505         for (tries = 0; tries < 5; tries++) {
2506                 temp = I915_READ(reg);
2507                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2508
2509                 if ((temp & FDI_RX_BIT_LOCK)) {
2510                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2511                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2512                         break;
2513                 }
2514         }
2515         if (tries == 5)
2516                 DRM_ERROR("FDI train 1 fail!\n");
2517
2518         /* Train 2 */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_LINK_TRAIN_NONE;
2522         temp |= FDI_LINK_TRAIN_PATTERN_2;
2523         I915_WRITE(reg, temp);
2524
2525         reg = FDI_RX_CTL(pipe);
2526         temp = I915_READ(reg);
2527         temp &= ~FDI_LINK_TRAIN_NONE;
2528         temp |= FDI_LINK_TRAIN_PATTERN_2;
2529         I915_WRITE(reg, temp);
2530
2531         POSTING_READ(reg);
2532         udelay(150);
2533
2534         reg = FDI_RX_IIR(pipe);
2535         for (tries = 0; tries < 5; tries++) {
2536                 temp = I915_READ(reg);
2537                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2538
2539                 if (temp & FDI_RX_SYMBOL_LOCK) {
2540                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2541                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2542                         break;
2543                 }
2544         }
2545         if (tries == 5)
2546                 DRM_ERROR("FDI train 2 fail!\n");
2547
2548         DRM_DEBUG_KMS("FDI train done\n");
2549
2550 }
2551
2552 static const int snb_b_fdi_train_param[] = {
2553         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2554         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2555         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2556         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2557 };
2558
2559 /* The FDI link training functions for SNB/Cougarpoint. */
2560 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2561 {
2562         struct drm_device *dev = crtc->dev;
2563         struct drm_i915_private *dev_priv = dev->dev_private;
2564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2565         int pipe = intel_crtc->pipe;
2566         u32 reg, temp, i, retry;
2567
2568         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2569            for train result */
2570         reg = FDI_RX_IMR(pipe);
2571         temp = I915_READ(reg);
2572         temp &= ~FDI_RX_SYMBOL_LOCK;
2573         temp &= ~FDI_RX_BIT_LOCK;
2574         I915_WRITE(reg, temp);
2575
2576         POSTING_READ(reg);
2577         udelay(150);
2578
2579         /* enable CPU FDI TX and PCH FDI RX */
2580         reg = FDI_TX_CTL(pipe);
2581         temp = I915_READ(reg);
2582         temp &= ~(7 << 19);
2583         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_1;
2586         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587         /* SNB-B */
2588         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2589         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2590
2591         I915_WRITE(FDI_RX_MISC(pipe),
2592                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2593
2594         reg = FDI_RX_CTL(pipe);
2595         temp = I915_READ(reg);
2596         if (HAS_PCH_CPT(dev)) {
2597                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2599         } else {
2600                 temp &= ~FDI_LINK_TRAIN_NONE;
2601                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2602         }
2603         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2604
2605         POSTING_READ(reg);
2606         udelay(150);
2607
2608         if (HAS_PCH_CPT(dev))
2609                 cpt_phase_pointer_enable(dev, pipe);
2610
2611         for (i = 0; i < 4; i++) {
2612                 reg = FDI_TX_CTL(pipe);
2613                 temp = I915_READ(reg);
2614                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615                 temp |= snb_b_fdi_train_param[i];
2616                 I915_WRITE(reg, temp);
2617
2618                 POSTING_READ(reg);
2619                 udelay(500);
2620
2621                 for (retry = 0; retry < 5; retry++) {
2622                         reg = FDI_RX_IIR(pipe);
2623                         temp = I915_READ(reg);
2624                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2625                         if (temp & FDI_RX_BIT_LOCK) {
2626                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2628                                 break;
2629                         }
2630                         udelay(50);
2631                 }
2632                 if (retry < 5)
2633                         break;
2634         }
2635         if (i == 4)
2636                 DRM_ERROR("FDI train 1 fail!\n");
2637
2638         /* Train 2 */
2639         reg = FDI_TX_CTL(pipe);
2640         temp = I915_READ(reg);
2641         temp &= ~FDI_LINK_TRAIN_NONE;
2642         temp |= FDI_LINK_TRAIN_PATTERN_2;
2643         if (IS_GEN6(dev)) {
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 /* SNB-B */
2646                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2647         }
2648         I915_WRITE(reg, temp);
2649
2650         reg = FDI_RX_CTL(pipe);
2651         temp = I915_READ(reg);
2652         if (HAS_PCH_CPT(dev)) {
2653                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2655         } else {
2656                 temp &= ~FDI_LINK_TRAIN_NONE;
2657                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2658         }
2659         I915_WRITE(reg, temp);
2660
2661         POSTING_READ(reg);
2662         udelay(150);
2663
2664         for (i = 0; i < 4; i++) {
2665                 reg = FDI_TX_CTL(pipe);
2666                 temp = I915_READ(reg);
2667                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668                 temp |= snb_b_fdi_train_param[i];
2669                 I915_WRITE(reg, temp);
2670
2671                 POSTING_READ(reg);
2672                 udelay(500);
2673
2674                 for (retry = 0; retry < 5; retry++) {
2675                         reg = FDI_RX_IIR(pipe);
2676                         temp = I915_READ(reg);
2677                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2678                         if (temp & FDI_RX_SYMBOL_LOCK) {
2679                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2680                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2681                                 break;
2682                         }
2683                         udelay(50);
2684                 }
2685                 if (retry < 5)
2686                         break;
2687         }
2688         if (i == 4)
2689                 DRM_ERROR("FDI train 2 fail!\n");
2690
2691         DRM_DEBUG_KMS("FDI train done.\n");
2692 }
2693
2694 /* Manual link training for Ivy Bridge A0 parts */
2695 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2696 {
2697         struct drm_device *dev = crtc->dev;
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2700         int pipe = intel_crtc->pipe;
2701         u32 reg, temp, i;
2702
2703         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2704            for train result */
2705         reg = FDI_RX_IMR(pipe);
2706         temp = I915_READ(reg);
2707         temp &= ~FDI_RX_SYMBOL_LOCK;
2708         temp &= ~FDI_RX_BIT_LOCK;
2709         I915_WRITE(reg, temp);
2710
2711         POSTING_READ(reg);
2712         udelay(150);
2713
2714         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2715                       I915_READ(FDI_RX_IIR(pipe)));
2716
2717         /* enable CPU FDI TX and PCH FDI RX */
2718         reg = FDI_TX_CTL(pipe);
2719         temp = I915_READ(reg);
2720         temp &= ~(7 << 19);
2721         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2722         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2723         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2724         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2726         temp |= FDI_COMPOSITE_SYNC;
2727         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2728
2729         I915_WRITE(FDI_RX_MISC(pipe),
2730                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2731
2732         reg = FDI_RX_CTL(pipe);
2733         temp = I915_READ(reg);
2734         temp &= ~FDI_LINK_TRAIN_AUTO;
2735         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2737         temp |= FDI_COMPOSITE_SYNC;
2738         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2739
2740         POSTING_READ(reg);
2741         udelay(150);
2742
2743         if (HAS_PCH_CPT(dev))
2744                 cpt_phase_pointer_enable(dev, pipe);
2745
2746         for (i = 0; i < 4; i++) {
2747                 reg = FDI_TX_CTL(pipe);
2748                 temp = I915_READ(reg);
2749                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750                 temp |= snb_b_fdi_train_param[i];
2751                 I915_WRITE(reg, temp);
2752
2753                 POSTING_READ(reg);
2754                 udelay(500);
2755
2756                 reg = FDI_RX_IIR(pipe);
2757                 temp = I915_READ(reg);
2758                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2759
2760                 if (temp & FDI_RX_BIT_LOCK ||
2761                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2762                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2763                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2764                         break;
2765                 }
2766         }
2767         if (i == 4)
2768                 DRM_ERROR("FDI train 1 fail!\n");
2769
2770         /* Train 2 */
2771         reg = FDI_TX_CTL(pipe);
2772         temp = I915_READ(reg);
2773         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2776         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2777         I915_WRITE(reg, temp);
2778
2779         reg = FDI_RX_CTL(pipe);
2780         temp = I915_READ(reg);
2781         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2782         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2783         I915_WRITE(reg, temp);
2784
2785         POSTING_READ(reg);
2786         udelay(150);
2787
2788         for (i = 0; i < 4; i++) {
2789                 reg = FDI_TX_CTL(pipe);
2790                 temp = I915_READ(reg);
2791                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2792                 temp |= snb_b_fdi_train_param[i];
2793                 I915_WRITE(reg, temp);
2794
2795                 POSTING_READ(reg);
2796                 udelay(500);
2797
2798                 reg = FDI_RX_IIR(pipe);
2799                 temp = I915_READ(reg);
2800                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2801
2802                 if (temp & FDI_RX_SYMBOL_LOCK) {
2803                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2804                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2805                         break;
2806                 }
2807         }
2808         if (i == 4)
2809                 DRM_ERROR("FDI train 2 fail!\n");
2810
2811         DRM_DEBUG_KMS("FDI train done.\n");
2812 }
2813
2814 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2815 {
2816         struct drm_device *dev = intel_crtc->base.dev;
2817         struct drm_i915_private *dev_priv = dev->dev_private;
2818         int pipe = intel_crtc->pipe;
2819         u32 reg, temp;
2820
2821
2822         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2823         reg = FDI_RX_CTL(pipe);
2824         temp = I915_READ(reg);
2825         temp &= ~((0x7 << 19) | (0x7 << 16));
2826         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2827         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2829
2830         POSTING_READ(reg);
2831         udelay(200);
2832
2833         /* Switch from Rawclk to PCDclk */
2834         temp = I915_READ(reg);
2835         I915_WRITE(reg, temp | FDI_PCDCLK);
2836
2837         POSTING_READ(reg);
2838         udelay(200);
2839
2840         /* On Haswell, the PLL configuration for ports and pipes is handled
2841          * separately, as part of DDI setup */
2842         if (!IS_HASWELL(dev)) {
2843                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2844                 reg = FDI_TX_CTL(pipe);
2845                 temp = I915_READ(reg);
2846                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2847                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2848
2849                         POSTING_READ(reg);
2850                         udelay(100);
2851                 }
2852         }
2853 }
2854
2855 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2856 {
2857         struct drm_device *dev = intel_crtc->base.dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859         int pipe = intel_crtc->pipe;
2860         u32 reg, temp;
2861
2862         /* Switch from PCDclk to Rawclk */
2863         reg = FDI_RX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2866
2867         /* Disable CPU FDI TX PLL */
2868         reg = FDI_TX_CTL(pipe);
2869         temp = I915_READ(reg);
2870         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2871
2872         POSTING_READ(reg);
2873         udelay(100);
2874
2875         reg = FDI_RX_CTL(pipe);
2876         temp = I915_READ(reg);
2877         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2878
2879         /* Wait for the clocks to turn off. */
2880         POSTING_READ(reg);
2881         udelay(100);
2882 }
2883
2884 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2885 {
2886         struct drm_i915_private *dev_priv = dev->dev_private;
2887         u32 flags = I915_READ(SOUTH_CHICKEN1);
2888
2889         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2890         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2891         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2892         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2893         POSTING_READ(SOUTH_CHICKEN1);
2894 }
2895 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900         int pipe = intel_crtc->pipe;
2901         u32 reg, temp;
2902
2903         /* disable CPU FDI tx and PCH FDI rx */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2907         POSTING_READ(reg);
2908
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         temp &= ~(0x7 << 16);
2912         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2913         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2914
2915         POSTING_READ(reg);
2916         udelay(100);
2917
2918         /* Ironlake workaround, disable clock pointer after downing FDI */
2919         if (HAS_PCH_IBX(dev)) {
2920                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2921                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2922                            I915_READ(FDI_RX_CHICKEN(pipe) &
2923                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2924         } else if (HAS_PCH_CPT(dev)) {
2925                 cpt_phase_pointer_disable(dev, pipe);
2926         }
2927
2928         /* still set train pattern 1 */
2929         reg = FDI_TX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_LINK_TRAIN_NONE;
2932         temp |= FDI_LINK_TRAIN_PATTERN_1;
2933         I915_WRITE(reg, temp);
2934
2935         reg = FDI_RX_CTL(pipe);
2936         temp = I915_READ(reg);
2937         if (HAS_PCH_CPT(dev)) {
2938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940         } else {
2941                 temp &= ~FDI_LINK_TRAIN_NONE;
2942                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943         }
2944         /* BPC in FDI rx is consistent with that in PIPECONF */
2945         temp &= ~(0x07 << 16);
2946         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947         I915_WRITE(reg, temp);
2948
2949         POSTING_READ(reg);
2950         udelay(100);
2951 }
2952
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954 {
2955         struct drm_device *dev = crtc->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         unsigned long flags;
2958         bool pending;
2959
2960         if (atomic_read(&dev_priv->mm.wedged))
2961                 return false;
2962
2963         spin_lock_irqsave(&dev->event_lock, flags);
2964         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965         spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967         return pending;
2968 }
2969
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974
2975         if (crtc->fb == NULL)
2976                 return;
2977
2978         wait_event(dev_priv->pending_flip_queue,
2979                    !intel_crtc_has_pending_flip(crtc));
2980
2981         mutex_lock(&dev->struct_mutex);
2982         intel_finish_fb(crtc->fb);
2983         mutex_unlock(&dev->struct_mutex);
2984 }
2985
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct intel_encoder *intel_encoder;
2990
2991         /*
2992          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993          * must be driven by its own crtc; no sharing is possible.
2994          */
2995         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2996                 switch (intel_encoder->type) {
2997                 case INTEL_OUTPUT_EDP:
2998                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2999                                 return false;
3000                         continue;
3001                 }
3002         }
3003
3004         return true;
3005 }
3006
3007 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008 {
3009         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010 }
3011
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc *crtc)
3014 {
3015         struct drm_device *dev = crtc->dev;
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018         u32 temp;
3019
3020         /* It is necessary to ungate the pixclk gate prior to programming
3021          * the divisors, and gate it back when it is done.
3022          */
3023         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025         /* Disable SSCCTL */
3026         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028                                         SBI_SSCCTL_DISABLE);
3029
3030         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031         if (crtc->mode.clock == 20000) {
3032                 auxdiv = 1;
3033                 divsel = 0x41;
3034                 phaseinc = 0x20;
3035         } else {
3036                 /* The iCLK virtual clock root frequency is in MHz,
3037                  * but the crtc->mode.clock in in KHz. To get the divisors,
3038                  * it is necessary to divide one by another, so we
3039                  * convert the virtual clock precision to KHz here for higher
3040                  * precision.
3041                  */
3042                 u32 iclk_virtual_root_freq = 172800 * 1000;
3043                 u32 iclk_pi_range = 64;
3044                 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047                 msb_divisor_value = desired_divisor / iclk_pi_range;
3048                 pi_value = desired_divisor % iclk_pi_range;
3049
3050                 auxdiv = 0;
3051                 divsel = msb_divisor_value - 2;
3052                 phaseinc = pi_value;
3053         }
3054
3055         /* This should not happen with any sane values */
3056         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062                         crtc->mode.clock,
3063                         auxdiv,
3064                         divsel,
3065                         phasedir,
3066                         phaseinc);
3067
3068         /* Program SSCDIVINTPHASE6 */
3069         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077         intel_sbi_write(dev_priv,
3078                         SBI_SSCDIVINTPHASE6,
3079                         temp);
3080
3081         /* Program SSCAUXDIV */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085         intel_sbi_write(dev_priv,
3086                         SBI_SSCAUXDIV6,
3087                         temp);
3088
3089
3090         /* Enable modulator and associated divider */
3091         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092         temp &= ~SBI_SSCCTL_DISABLE;
3093         intel_sbi_write(dev_priv,
3094                         SBI_SSCCTL6,
3095                         temp);
3096
3097         /* Wait for initialization time */
3098         udelay(24);
3099
3100         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101 }
3102
3103 /*
3104  * Enable PCH resources required for PCH ports:
3105  *   - PCH PLLs
3106  *   - FDI training & RX/TX
3107  *   - update transcoder timings
3108  *   - DP transcoding bits
3109  *   - transcoder
3110  */
3111 static void ironlake_pch_enable(struct drm_crtc *crtc)
3112 {
3113         struct drm_device *dev = crtc->dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116         int pipe = intel_crtc->pipe;
3117         u32 reg, temp;
3118
3119         assert_transcoder_disabled(dev_priv, pipe);
3120
3121         /* Write the TU size bits before fdi link training, so that error
3122          * detection works. */
3123         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
3126         /* For PCH output, training FDI link */
3127         dev_priv->display.fdi_link_train(crtc);
3128
3129         /* XXX: pch pll's can be enabled any time before we enable the PCH
3130          * transcoder, and we actually should do this to not upset any PCH
3131          * transcoder that already use the clock when we share it.
3132          *
3133          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134          * unconditionally resets the pll - we need that to have the right LVDS
3135          * enable sequence. */
3136         ironlake_enable_pch_pll(intel_crtc);
3137
3138         if (HAS_PCH_CPT(dev)) {
3139                 u32 sel;
3140
3141                 temp = I915_READ(PCH_DPLL_SEL);
3142                 switch (pipe) {
3143                 default:
3144                 case 0:
3145                         temp |= TRANSA_DPLL_ENABLE;
3146                         sel = TRANSA_DPLLB_SEL;
3147                         break;
3148                 case 1:
3149                         temp |= TRANSB_DPLL_ENABLE;
3150                         sel = TRANSB_DPLLB_SEL;
3151                         break;
3152                 case 2:
3153                         temp |= TRANSC_DPLL_ENABLE;
3154                         sel = TRANSC_DPLLB_SEL;
3155                         break;
3156                 }
3157                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158                         temp |= sel;
3159                 else
3160                         temp &= ~sel;
3161                 I915_WRITE(PCH_DPLL_SEL, temp);
3162         }
3163
3164         /* set transcoder timing, panel must allow it */
3165         assert_panel_unlocked(dev_priv, pipe);
3166         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3169
3170         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3173         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3174
3175         intel_fdi_normal_train(crtc);
3176
3177         /* For PCH DP, enable TRANS_DP_CTL */
3178         if (HAS_PCH_CPT(dev) &&
3179             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3181                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3185                           TRANS_DP_SYNC_MASK |
3186                           TRANS_DP_BPC_MASK);
3187                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188                          TRANS_DP_ENH_FRAMING);
3189                 temp |= bpc << 9; /* same format but at 11:9 */
3190
3191                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3192                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3193                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3194                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3195
3196                 switch (intel_trans_dp_port_sel(crtc)) {
3197                 case PCH_DP_B:
3198                         temp |= TRANS_DP_PORT_SEL_B;
3199                         break;
3200                 case PCH_DP_C:
3201                         temp |= TRANS_DP_PORT_SEL_C;
3202                         break;
3203                 case PCH_DP_D:
3204                         temp |= TRANS_DP_PORT_SEL_D;
3205                         break;
3206                 default:
3207                         BUG();
3208                 }
3209
3210                 I915_WRITE(reg, temp);
3211         }
3212
3213         ironlake_enable_pch_transcoder(dev_priv, pipe);
3214 }
3215
3216 static void lpt_pch_enable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         int pipe = intel_crtc->pipe;
3222         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3223
3224         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3225
3226         /* Write the TU size bits before fdi link training, so that error
3227          * detection works. */
3228         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3229                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3230
3231         /* For PCH output, training FDI link */
3232         dev_priv->display.fdi_link_train(crtc);
3233
3234         lpt_program_iclkip(crtc);
3235
3236         /* Set transcoder timing. */
3237         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3238         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3239         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3240
3241         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3242         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3243         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3244         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3245
3246         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3247 }
3248
3249 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3250 {
3251         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3252
3253         if (pll == NULL)
3254                 return;
3255
3256         if (pll->refcount == 0) {
3257                 WARN(1, "bad PCH PLL refcount\n");
3258                 return;
3259         }
3260
3261         --pll->refcount;
3262         intel_crtc->pch_pll = NULL;
3263 }
3264
3265 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3266 {
3267         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3268         struct intel_pch_pll *pll;
3269         int i;
3270
3271         pll = intel_crtc->pch_pll;
3272         if (pll) {
3273                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3274                               intel_crtc->base.base.id, pll->pll_reg);
3275                 goto prepare;
3276         }
3277
3278         if (HAS_PCH_IBX(dev_priv->dev)) {
3279                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3280                 i = intel_crtc->pipe;
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3284                               intel_crtc->base.base.id, pll->pll_reg);
3285
3286                 goto found;
3287         }
3288
3289         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3290                 pll = &dev_priv->pch_plls[i];
3291
3292                 /* Only want to check enabled timings first */
3293                 if (pll->refcount == 0)
3294                         continue;
3295
3296                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3297                     fp == I915_READ(pll->fp0_reg)) {
3298                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3299                                       intel_crtc->base.base.id,
3300                                       pll->pll_reg, pll->refcount, pll->active);
3301
3302                         goto found;
3303                 }
3304         }
3305
3306         /* Ok no matching timings, maybe there's a free one? */
3307         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3308                 pll = &dev_priv->pch_plls[i];
3309                 if (pll->refcount == 0) {
3310                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3311                                       intel_crtc->base.base.id, pll->pll_reg);
3312                         goto found;
3313                 }
3314         }
3315
3316         return NULL;
3317
3318 found:
3319         intel_crtc->pch_pll = pll;
3320         pll->refcount++;
3321         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3322 prepare: /* separate function? */
3323         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3324
3325         /* Wait for the clocks to stabilize before rewriting the regs */
3326         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3327         POSTING_READ(pll->pll_reg);
3328         udelay(150);
3329
3330         I915_WRITE(pll->fp0_reg, fp);
3331         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3332         pll->on = false;
3333         return pll;
3334 }
3335
3336 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3337 {
3338         struct drm_i915_private *dev_priv = dev->dev_private;
3339         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3340         u32 temp;
3341
3342         temp = I915_READ(dslreg);
3343         udelay(500);
3344         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3345                 /* Without this, mode sets may fail silently on FDI */
3346                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3347                 udelay(250);
3348                 I915_WRITE(tc2reg, 0);
3349                 if (wait_for(I915_READ(dslreg) != temp, 5))
3350                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3351         }
3352 }
3353
3354 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3355 {
3356         struct drm_device *dev = crtc->dev;
3357         struct drm_i915_private *dev_priv = dev->dev_private;
3358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359         struct intel_encoder *encoder;
3360         int pipe = intel_crtc->pipe;
3361         int plane = intel_crtc->plane;
3362         u32 temp;
3363         bool is_pch_port;
3364
3365         WARN_ON(!crtc->enabled);
3366
3367         if (intel_crtc->active)
3368                 return;
3369
3370         intel_crtc->active = true;
3371         intel_update_watermarks(dev);
3372
3373         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3374                 temp = I915_READ(PCH_LVDS);
3375                 if ((temp & LVDS_PORT_EN) == 0)
3376                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3377         }
3378
3379         is_pch_port = ironlake_crtc_driving_pch(crtc);
3380
3381         if (is_pch_port) {
3382                 /* Note: FDI PLL enabling _must_ be done before we enable the
3383                  * cpu pipes, hence this is separate from all the other fdi/pch
3384                  * enabling. */
3385                 ironlake_fdi_pll_enable(intel_crtc);
3386         } else {
3387                 assert_fdi_tx_disabled(dev_priv, pipe);
3388                 assert_fdi_rx_disabled(dev_priv, pipe);
3389         }
3390
3391         for_each_encoder_on_crtc(dev, crtc, encoder)
3392                 if (encoder->pre_enable)
3393                         encoder->pre_enable(encoder);
3394
3395         /* Enable panel fitting for LVDS */
3396         if (dev_priv->pch_pf_size &&
3397             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3398                 /* Force use of hard-coded filter coefficients
3399                  * as some pre-programmed values are broken,
3400                  * e.g. x201.
3401                  */
3402                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3403                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3404                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3405         }
3406
3407         /*
3408          * On ILK+ LUT must be loaded before the pipe is running but with
3409          * clocks enabled
3410          */
3411         intel_crtc_load_lut(crtc);
3412
3413         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3414         intel_enable_plane(dev_priv, plane, pipe);
3415
3416         if (is_pch_port)
3417                 ironlake_pch_enable(crtc);
3418
3419         mutex_lock(&dev->struct_mutex);
3420         intel_update_fbc(dev);
3421         mutex_unlock(&dev->struct_mutex);
3422
3423         intel_crtc_update_cursor(crtc, true);
3424
3425         for_each_encoder_on_crtc(dev, crtc, encoder)
3426                 encoder->enable(encoder);
3427
3428         if (HAS_PCH_CPT(dev))
3429                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3430
3431         /*
3432          * There seems to be a race in PCH platform hw (at least on some
3433          * outputs) where an enabled pipe still completes any pageflip right
3434          * away (as if the pipe is off) instead of waiting for vblank. As soon
3435          * as the first vblank happend, everything works as expected. Hence just
3436          * wait for one vblank before returning to avoid strange things
3437          * happening.
3438          */
3439         intel_wait_for_vblank(dev, intel_crtc->pipe);
3440 }
3441
3442 static void haswell_crtc_enable(struct drm_crtc *crtc)
3443 {
3444         struct drm_device *dev = crtc->dev;
3445         struct drm_i915_private *dev_priv = dev->dev_private;
3446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447         struct intel_encoder *encoder;
3448         int pipe = intel_crtc->pipe;
3449         int plane = intel_crtc->plane;
3450         bool is_pch_port;
3451
3452         WARN_ON(!crtc->enabled);
3453
3454         if (intel_crtc->active)
3455                 return;
3456
3457         intel_crtc->active = true;
3458         intel_update_watermarks(dev);
3459
3460         is_pch_port = haswell_crtc_driving_pch(crtc);
3461
3462         if (is_pch_port)
3463                 ironlake_fdi_pll_enable(intel_crtc);
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 if (encoder->pre_enable)
3467                         encoder->pre_enable(encoder);
3468
3469         intel_ddi_enable_pipe_clock(intel_crtc);
3470
3471         /* Enable panel fitting for eDP */
3472         if (dev_priv->pch_pf_size && HAS_eDP) {
3473                 /* Force use of hard-coded filter coefficients
3474                  * as some pre-programmed values are broken,
3475                  * e.g. x201.
3476                  */
3477                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3478                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3479                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3480         }
3481
3482         /*
3483          * On ILK+ LUT must be loaded before the pipe is running but with
3484          * clocks enabled
3485          */
3486         intel_crtc_load_lut(crtc);
3487
3488         intel_ddi_set_pipe_settings(crtc);
3489         intel_ddi_enable_pipe_func(crtc);
3490
3491         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3492         intel_enable_plane(dev_priv, plane, pipe);
3493
3494         if (is_pch_port)
3495                 lpt_pch_enable(crtc);
3496
3497         mutex_lock(&dev->struct_mutex);
3498         intel_update_fbc(dev);
3499         mutex_unlock(&dev->struct_mutex);
3500
3501         intel_crtc_update_cursor(crtc, true);
3502
3503         for_each_encoder_on_crtc(dev, crtc, encoder)
3504                 encoder->enable(encoder);
3505
3506         /*
3507          * There seems to be a race in PCH platform hw (at least on some
3508          * outputs) where an enabled pipe still completes any pageflip right
3509          * away (as if the pipe is off) instead of waiting for vblank. As soon
3510          * as the first vblank happend, everything works as expected. Hence just
3511          * wait for one vblank before returning to avoid strange things
3512          * happening.
3513          */
3514         intel_wait_for_vblank(dev, intel_crtc->pipe);
3515 }
3516
3517 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         struct intel_encoder *encoder;
3523         int pipe = intel_crtc->pipe;
3524         int plane = intel_crtc->plane;
3525         u32 reg, temp;
3526
3527
3528         if (!intel_crtc->active)
3529                 return;
3530
3531         for_each_encoder_on_crtc(dev, crtc, encoder)
3532                 encoder->disable(encoder);
3533
3534         intel_crtc_wait_for_pending_flips(crtc);
3535         drm_vblank_off(dev, pipe);
3536         intel_crtc_update_cursor(crtc, false);
3537
3538         intel_disable_plane(dev_priv, plane, pipe);
3539
3540         if (dev_priv->cfb_plane == plane)
3541                 intel_disable_fbc(dev);
3542
3543         intel_disable_pipe(dev_priv, pipe);
3544
3545         /* Disable PF */
3546         I915_WRITE(PF_CTL(pipe), 0);
3547         I915_WRITE(PF_WIN_SZ(pipe), 0);
3548
3549         for_each_encoder_on_crtc(dev, crtc, encoder)
3550                 if (encoder->post_disable)
3551                         encoder->post_disable(encoder);
3552
3553         ironlake_fdi_disable(crtc);
3554
3555         ironlake_disable_pch_transcoder(dev_priv, pipe);
3556
3557         if (HAS_PCH_CPT(dev)) {
3558                 /* disable TRANS_DP_CTL */
3559                 reg = TRANS_DP_CTL(pipe);
3560                 temp = I915_READ(reg);
3561                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3562                 temp |= TRANS_DP_PORT_SEL_NONE;
3563                 I915_WRITE(reg, temp);
3564
3565                 /* disable DPLL_SEL */
3566                 temp = I915_READ(PCH_DPLL_SEL);
3567                 switch (pipe) {
3568                 case 0:
3569                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3570                         break;
3571                 case 1:
3572                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3573                         break;
3574                 case 2:
3575                         /* C shares PLL A or B */
3576                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3577                         break;
3578                 default:
3579                         BUG(); /* wtf */
3580                 }
3581                 I915_WRITE(PCH_DPLL_SEL, temp);
3582         }
3583
3584         /* disable PCH DPLL */
3585         intel_disable_pch_pll(intel_crtc);
3586
3587         ironlake_fdi_pll_disable(intel_crtc);
3588
3589         intel_crtc->active = false;
3590         intel_update_watermarks(dev);
3591
3592         mutex_lock(&dev->struct_mutex);
3593         intel_update_fbc(dev);
3594         mutex_unlock(&dev->struct_mutex);
3595 }
3596
3597 static void haswell_crtc_disable(struct drm_crtc *crtc)
3598 {
3599         struct drm_device *dev = crtc->dev;
3600         struct drm_i915_private *dev_priv = dev->dev_private;
3601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602         struct intel_encoder *encoder;
3603         int pipe = intel_crtc->pipe;
3604         int plane = intel_crtc->plane;
3605         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3606         bool is_pch_port;
3607
3608         if (!intel_crtc->active)
3609                 return;
3610
3611         is_pch_port = haswell_crtc_driving_pch(crtc);
3612
3613         for_each_encoder_on_crtc(dev, crtc, encoder)
3614                 encoder->disable(encoder);
3615
3616         intel_crtc_wait_for_pending_flips(crtc);
3617         drm_vblank_off(dev, pipe);
3618         intel_crtc_update_cursor(crtc, false);
3619
3620         intel_disable_plane(dev_priv, plane, pipe);
3621
3622         if (dev_priv->cfb_plane == plane)
3623                 intel_disable_fbc(dev);
3624
3625         intel_disable_pipe(dev_priv, pipe);
3626
3627         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3628
3629         /* Disable PF */
3630         I915_WRITE(PF_CTL(pipe), 0);
3631         I915_WRITE(PF_WIN_SZ(pipe), 0);
3632
3633         intel_ddi_disable_pipe_clock(intel_crtc);
3634
3635         for_each_encoder_on_crtc(dev, crtc, encoder)
3636                 if (encoder->post_disable)
3637                         encoder->post_disable(encoder);
3638
3639         if (is_pch_port) {
3640                 ironlake_fdi_disable(crtc);
3641                 lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
3642                 intel_disable_pch_pll(intel_crtc);
3643                 ironlake_fdi_pll_disable(intel_crtc);
3644         }
3645
3646         intel_crtc->active = false;
3647         intel_update_watermarks(dev);
3648
3649         mutex_lock(&dev->struct_mutex);
3650         intel_update_fbc(dev);
3651         mutex_unlock(&dev->struct_mutex);
3652 }
3653
3654 static void ironlake_crtc_off(struct drm_crtc *crtc)
3655 {
3656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657         intel_put_pch_pll(intel_crtc);
3658 }
3659
3660 static void haswell_crtc_off(struct drm_crtc *crtc)
3661 {
3662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663
3664         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3665          * start using it. */
3666         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3667
3668         intel_ddi_put_crtc_pll(crtc);
3669 }
3670
3671 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3672 {
3673         if (!enable && intel_crtc->overlay) {
3674                 struct drm_device *dev = intel_crtc->base.dev;
3675                 struct drm_i915_private *dev_priv = dev->dev_private;
3676
3677                 mutex_lock(&dev->struct_mutex);
3678                 dev_priv->mm.interruptible = false;
3679                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3680                 dev_priv->mm.interruptible = true;
3681                 mutex_unlock(&dev->struct_mutex);
3682         }
3683
3684         /* Let userspace switch the overlay on again. In most cases userspace
3685          * has to recompute where to put it anyway.
3686          */
3687 }
3688
3689 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3690 {
3691         struct drm_device *dev = crtc->dev;
3692         struct drm_i915_private *dev_priv = dev->dev_private;
3693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3694         struct intel_encoder *encoder;
3695         int pipe = intel_crtc->pipe;
3696         int plane = intel_crtc->plane;
3697
3698         WARN_ON(!crtc->enabled);
3699
3700         if (intel_crtc->active)
3701                 return;
3702
3703         intel_crtc->active = true;
3704         intel_update_watermarks(dev);
3705
3706         intel_enable_pll(dev_priv, pipe);
3707         intel_enable_pipe(dev_priv, pipe, false);
3708         intel_enable_plane(dev_priv, plane, pipe);
3709
3710         intel_crtc_load_lut(crtc);
3711         intel_update_fbc(dev);
3712
3713         /* Give the overlay scaler a chance to enable if it's on this pipe */
3714         intel_crtc_dpms_overlay(intel_crtc, true);
3715         intel_crtc_update_cursor(crtc, true);
3716
3717         for_each_encoder_on_crtc(dev, crtc, encoder)
3718                 encoder->enable(encoder);
3719 }
3720
3721 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3722 {
3723         struct drm_device *dev = crtc->dev;
3724         struct drm_i915_private *dev_priv = dev->dev_private;
3725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726         struct intel_encoder *encoder;
3727         int pipe = intel_crtc->pipe;
3728         int plane = intel_crtc->plane;
3729
3730
3731         if (!intel_crtc->active)
3732                 return;
3733
3734         for_each_encoder_on_crtc(dev, crtc, encoder)
3735                 encoder->disable(encoder);
3736
3737         /* Give the overlay scaler a chance to disable if it's on this pipe */
3738         intel_crtc_wait_for_pending_flips(crtc);
3739         drm_vblank_off(dev, pipe);
3740         intel_crtc_dpms_overlay(intel_crtc, false);
3741         intel_crtc_update_cursor(crtc, false);
3742
3743         if (dev_priv->cfb_plane == plane)
3744                 intel_disable_fbc(dev);
3745
3746         intel_disable_plane(dev_priv, plane, pipe);
3747         intel_disable_pipe(dev_priv, pipe);
3748         intel_disable_pll(dev_priv, pipe);
3749
3750         intel_crtc->active = false;
3751         intel_update_fbc(dev);
3752         intel_update_watermarks(dev);
3753 }
3754
3755 static void i9xx_crtc_off(struct drm_crtc *crtc)
3756 {
3757 }
3758
3759 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3760                                     bool enabled)
3761 {
3762         struct drm_device *dev = crtc->dev;
3763         struct drm_i915_master_private *master_priv;
3764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765         int pipe = intel_crtc->pipe;
3766
3767         if (!dev->primary->master)
3768                 return;
3769
3770         master_priv = dev->primary->master->driver_priv;
3771         if (!master_priv->sarea_priv)
3772                 return;
3773
3774         switch (pipe) {
3775         case 0:
3776                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3777                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3778                 break;
3779         case 1:
3780                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3781                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3782                 break;
3783         default:
3784                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3785                 break;
3786         }
3787 }
3788
3789 /**
3790  * Sets the power management mode of the pipe and plane.
3791  */
3792 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795         struct drm_i915_private *dev_priv = dev->dev_private;
3796         struct intel_encoder *intel_encoder;
3797         bool enable = false;
3798
3799         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3800                 enable |= intel_encoder->connectors_active;
3801
3802         if (enable)
3803                 dev_priv->display.crtc_enable(crtc);
3804         else
3805                 dev_priv->display.crtc_disable(crtc);
3806
3807         intel_crtc_update_sarea(crtc, enable);
3808 }
3809
3810 static void intel_crtc_noop(struct drm_crtc *crtc)
3811 {
3812 }
3813
3814 static void intel_crtc_disable(struct drm_crtc *crtc)
3815 {
3816         struct drm_device *dev = crtc->dev;
3817         struct drm_connector *connector;
3818         struct drm_i915_private *dev_priv = dev->dev_private;
3819
3820         /* crtc should still be enabled when we disable it. */
3821         WARN_ON(!crtc->enabled);
3822
3823         dev_priv->display.crtc_disable(crtc);
3824         intel_crtc_update_sarea(crtc, false);
3825         dev_priv->display.off(crtc);
3826
3827         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3828         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3829
3830         if (crtc->fb) {
3831                 mutex_lock(&dev->struct_mutex);
3832                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3833                 mutex_unlock(&dev->struct_mutex);
3834                 crtc->fb = NULL;
3835         }
3836
3837         /* Update computed state. */
3838         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3839                 if (!connector->encoder || !connector->encoder->crtc)
3840                         continue;
3841
3842                 if (connector->encoder->crtc != crtc)
3843                         continue;
3844
3845                 connector->dpms = DRM_MODE_DPMS_OFF;
3846                 to_intel_encoder(connector->encoder)->connectors_active = false;
3847         }
3848 }
3849
3850 void intel_modeset_disable(struct drm_device *dev)
3851 {
3852         struct drm_crtc *crtc;
3853
3854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3855                 if (crtc->enabled)
3856                         intel_crtc_disable(crtc);
3857         }
3858 }
3859
3860 void intel_encoder_noop(struct drm_encoder *encoder)
3861 {
3862 }
3863
3864 void intel_encoder_destroy(struct drm_encoder *encoder)
3865 {
3866         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3867
3868         drm_encoder_cleanup(encoder);
3869         kfree(intel_encoder);
3870 }
3871
3872 /* Simple dpms helper for encodres with just one connector, no cloning and only
3873  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3874  * state of the entire output pipe. */
3875 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3876 {
3877         if (mode == DRM_MODE_DPMS_ON) {
3878                 encoder->connectors_active = true;
3879
3880                 intel_crtc_update_dpms(encoder->base.crtc);
3881         } else {
3882                 encoder->connectors_active = false;
3883
3884                 intel_crtc_update_dpms(encoder->base.crtc);
3885         }
3886 }
3887
3888 /* Cross check the actual hw state with our own modeset state tracking (and it's
3889  * internal consistency). */
3890 static void intel_connector_check_state(struct intel_connector *connector)
3891 {
3892         if (connector->get_hw_state(connector)) {
3893                 struct intel_encoder *encoder = connector->encoder;
3894                 struct drm_crtc *crtc;
3895                 bool encoder_enabled;
3896                 enum pipe pipe;
3897
3898                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3899                               connector->base.base.id,
3900                               drm_get_connector_name(&connector->base));
3901
3902                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3903                      "wrong connector dpms state\n");
3904                 WARN(connector->base.encoder != &encoder->base,
3905                      "active connector not linked to encoder\n");
3906                 WARN(!encoder->connectors_active,
3907                      "encoder->connectors_active not set\n");
3908
3909                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3910                 WARN(!encoder_enabled, "encoder not enabled\n");
3911                 if (WARN_ON(!encoder->base.crtc))
3912                         return;
3913
3914                 crtc = encoder->base.crtc;
3915
3916                 WARN(!crtc->enabled, "crtc not enabled\n");
3917                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3918                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3919                      "encoder active on the wrong pipe\n");
3920         }
3921 }
3922
3923 /* Even simpler default implementation, if there's really no special case to
3924  * consider. */
3925 void intel_connector_dpms(struct drm_connector *connector, int mode)
3926 {
3927         struct intel_encoder *encoder = intel_attached_encoder(connector);
3928
3929         /* All the simple cases only support two dpms states. */
3930         if (mode != DRM_MODE_DPMS_ON)
3931                 mode = DRM_MODE_DPMS_OFF;
3932
3933         if (mode == connector->dpms)
3934                 return;
3935
3936         connector->dpms = mode;
3937
3938         /* Only need to change hw state when actually enabled */
3939         if (encoder->base.crtc)
3940                 intel_encoder_dpms(encoder, mode);
3941         else
3942                 WARN_ON(encoder->connectors_active != false);
3943
3944         intel_modeset_check_state(connector->dev);
3945 }
3946
3947 /* Simple connector->get_hw_state implementation for encoders that support only
3948  * one connector and no cloning and hence the encoder state determines the state
3949  * of the connector. */
3950 bool intel_connector_get_hw_state(struct intel_connector *connector)
3951 {
3952         enum pipe pipe = 0;
3953         struct intel_encoder *encoder = connector->encoder;
3954
3955         return encoder->get_hw_state(encoder, &pipe);
3956 }
3957
3958 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3959                                   const struct drm_display_mode *mode,
3960                                   struct drm_display_mode *adjusted_mode)
3961 {
3962         struct drm_device *dev = crtc->dev;
3963
3964         if (HAS_PCH_SPLIT(dev)) {
3965                 /* FDI link clock is fixed at 2.7G */
3966                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3967                         return false;
3968         }
3969
3970         /* All interlaced capable intel hw wants timings in frames. Note though
3971          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3972          * timings, so we need to be careful not to clobber these.*/
3973         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3974                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3975
3976         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3977          * with a hsync front porch of 0.
3978          */
3979         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3980                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3981                 return false;
3982
3983         return true;
3984 }
3985
3986 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3987 {
3988         return 400000; /* FIXME */
3989 }
3990
3991 static int i945_get_display_clock_speed(struct drm_device *dev)
3992 {
3993         return 400000;
3994 }
3995
3996 static int i915_get_display_clock_speed(struct drm_device *dev)
3997 {
3998         return 333000;
3999 }
4000
4001 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4002 {
4003         return 200000;
4004 }
4005
4006 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4007 {
4008         u16 gcfgc = 0;
4009
4010         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4011
4012         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4013                 return 133000;
4014         else {
4015                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4016                 case GC_DISPLAY_CLOCK_333_MHZ:
4017                         return 333000;
4018                 default:
4019                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4020                         return 190000;
4021                 }
4022         }
4023 }
4024
4025 static int i865_get_display_clock_speed(struct drm_device *dev)
4026 {
4027         return 266000;
4028 }
4029
4030 static int i855_get_display_clock_speed(struct drm_device *dev)
4031 {
4032         u16 hpllcc = 0;
4033         /* Assume that the hardware is in the high speed state.  This
4034          * should be the default.
4035          */
4036         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4037         case GC_CLOCK_133_200:
4038         case GC_CLOCK_100_200:
4039                 return 200000;
4040         case GC_CLOCK_166_250:
4041                 return 250000;
4042         case GC_CLOCK_100_133:
4043                 return 133000;
4044         }
4045
4046         /* Shouldn't happen */
4047         return 0;
4048 }
4049
4050 static int i830_get_display_clock_speed(struct drm_device *dev)
4051 {
4052         return 133000;
4053 }
4054
4055 struct fdi_m_n {
4056         u32        tu;
4057         u32        gmch_m;
4058         u32        gmch_n;
4059         u32        link_m;
4060         u32        link_n;
4061 };
4062
4063 static void
4064 fdi_reduce_ratio(u32 *num, u32 *den)
4065 {
4066         while (*num > 0xffffff || *den > 0xffffff) {
4067                 *num >>= 1;
4068                 *den >>= 1;
4069         }
4070 }
4071
4072 static void
4073 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4074                      int link_clock, struct fdi_m_n *m_n)
4075 {
4076         m_n->tu = 64; /* default size */
4077
4078         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4079         m_n->gmch_m = bits_per_pixel * pixel_clock;
4080         m_n->gmch_n = link_clock * nlanes * 8;
4081         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4082
4083         m_n->link_m = pixel_clock;
4084         m_n->link_n = link_clock;
4085         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4086 }
4087
4088 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4089 {
4090         if (i915_panel_use_ssc >= 0)
4091                 return i915_panel_use_ssc != 0;
4092         return dev_priv->lvds_use_ssc
4093                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4094 }
4095
4096 /**
4097  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4098  * @crtc: CRTC structure
4099  * @mode: requested mode
4100  *
4101  * A pipe may be connected to one or more outputs.  Based on the depth of the
4102  * attached framebuffer, choose a good color depth to use on the pipe.
4103  *
4104  * If possible, match the pipe depth to the fb depth.  In some cases, this
4105  * isn't ideal, because the connected output supports a lesser or restricted
4106  * set of depths.  Resolve that here:
4107  *    LVDS typically supports only 6bpc, so clamp down in that case
4108  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4109  *    Displays may support a restricted set as well, check EDID and clamp as
4110  *      appropriate.
4111  *    DP may want to dither down to 6bpc to fit larger modes
4112  *
4113  * RETURNS:
4114  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4115  * true if they don't match).
4116  */
4117 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4118                                          struct drm_framebuffer *fb,
4119                                          unsigned int *pipe_bpp,
4120                                          struct drm_display_mode *mode)
4121 {
4122         struct drm_device *dev = crtc->dev;
4123         struct drm_i915_private *dev_priv = dev->dev_private;
4124         struct drm_connector *connector;
4125         struct intel_encoder *intel_encoder;
4126         unsigned int display_bpc = UINT_MAX, bpc;
4127
4128         /* Walk the encoders & connectors on this crtc, get min bpc */
4129         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4130
4131                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4132                         unsigned int lvds_bpc;
4133
4134                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4135                             LVDS_A3_POWER_UP)
4136                                 lvds_bpc = 8;
4137                         else
4138                                 lvds_bpc = 6;
4139
4140                         if (lvds_bpc < display_bpc) {
4141                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4142                                 display_bpc = lvds_bpc;
4143                         }
4144                         continue;
4145                 }
4146
4147                 /* Not one of the known troublemakers, check the EDID */
4148                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4149                                     head) {
4150                         if (connector->encoder != &intel_encoder->base)
4151                                 continue;
4152
4153                         /* Don't use an invalid EDID bpc value */
4154                         if (connector->display_info.bpc &&
4155                             connector->display_info.bpc < display_bpc) {
4156                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4157                                 display_bpc = connector->display_info.bpc;
4158                         }
4159                 }
4160
4161                 /*
4162                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4163                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4164                  */
4165                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4166                         if (display_bpc > 8 && display_bpc < 12) {
4167                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4168                                 display_bpc = 12;
4169                         } else {
4170                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4171                                 display_bpc = 8;
4172                         }
4173                 }
4174         }
4175
4176         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4177                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4178                 display_bpc = 6;
4179         }
4180
4181         /*
4182          * We could just drive the pipe at the highest bpc all the time and
4183          * enable dithering as needed, but that costs bandwidth.  So choose
4184          * the minimum value that expresses the full color range of the fb but
4185          * also stays within the max display bpc discovered above.
4186          */
4187
4188         switch (fb->depth) {
4189         case 8:
4190                 bpc = 8; /* since we go through a colormap */
4191                 break;
4192         case 15:
4193         case 16:
4194                 bpc = 6; /* min is 18bpp */
4195                 break;
4196         case 24:
4197                 bpc = 8;
4198                 break;
4199         case 30:
4200                 bpc = 10;
4201                 break;
4202         case 48:
4203                 bpc = 12;
4204                 break;
4205         default:
4206                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4207                 bpc = min((unsigned int)8, display_bpc);
4208                 break;
4209         }
4210
4211         display_bpc = min(display_bpc, bpc);
4212
4213         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4214                       bpc, display_bpc);
4215
4216         *pipe_bpp = display_bpc * 3;
4217
4218         return display_bpc != bpc;
4219 }
4220
4221 static int vlv_get_refclk(struct drm_crtc *crtc)
4222 {
4223         struct drm_device *dev = crtc->dev;
4224         struct drm_i915_private *dev_priv = dev->dev_private;
4225         int refclk = 27000; /* for DP & HDMI */
4226
4227         return 100000; /* only one validated so far */
4228
4229         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4230                 refclk = 96000;
4231         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4232                 if (intel_panel_use_ssc(dev_priv))
4233                         refclk = 100000;
4234                 else
4235                         refclk = 96000;
4236         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4237                 refclk = 100000;
4238         }
4239
4240         return refclk;
4241 }
4242
4243 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4244 {
4245         struct drm_device *dev = crtc->dev;
4246         struct drm_i915_private *dev_priv = dev->dev_private;
4247         int refclk;
4248
4249         if (IS_VALLEYVIEW(dev)) {
4250                 refclk = vlv_get_refclk(crtc);
4251         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4252             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4253                 refclk = dev_priv->lvds_ssc_freq * 1000;
4254                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4255                               refclk / 1000);
4256         } else if (!IS_GEN2(dev)) {
4257                 refclk = 96000;
4258         } else {
4259                 refclk = 48000;
4260         }
4261
4262         return refclk;
4263 }
4264
4265 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4266                                       intel_clock_t *clock)
4267 {
4268         /* SDVO TV has fixed PLL values depend on its clock range,
4269            this mirrors vbios setting. */
4270         if (adjusted_mode->clock >= 100000
4271             && adjusted_mode->clock < 140500) {
4272                 clock->p1 = 2;
4273                 clock->p2 = 10;
4274                 clock->n = 3;
4275                 clock->m1 = 16;
4276                 clock->m2 = 8;
4277         } else if (adjusted_mode->clock >= 140500
4278                    && adjusted_mode->clock <= 200000) {
4279                 clock->p1 = 1;
4280                 clock->p2 = 10;
4281                 clock->n = 6;
4282                 clock->m1 = 12;
4283                 clock->m2 = 8;
4284         }
4285 }
4286
4287 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4288                                      intel_clock_t *clock,
4289                                      intel_clock_t *reduced_clock)
4290 {
4291         struct drm_device *dev = crtc->dev;
4292         struct drm_i915_private *dev_priv = dev->dev_private;
4293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294         int pipe = intel_crtc->pipe;
4295         u32 fp, fp2 = 0;
4296
4297         if (IS_PINEVIEW(dev)) {
4298                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4299                 if (reduced_clock)
4300                         fp2 = (1 << reduced_clock->n) << 16 |
4301                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4302         } else {
4303                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4304                 if (reduced_clock)
4305                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4306                                 reduced_clock->m2;
4307         }
4308
4309         I915_WRITE(FP0(pipe), fp);
4310
4311         intel_crtc->lowfreq_avail = false;
4312         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4313             reduced_clock && i915_powersave) {
4314                 I915_WRITE(FP1(pipe), fp2);
4315                 intel_crtc->lowfreq_avail = true;
4316         } else {
4317                 I915_WRITE(FP1(pipe), fp);
4318         }
4319 }
4320
4321 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4322                               struct drm_display_mode *adjusted_mode)
4323 {
4324         struct drm_device *dev = crtc->dev;
4325         struct drm_i915_private *dev_priv = dev->dev_private;
4326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4327         int pipe = intel_crtc->pipe;
4328         u32 temp;
4329
4330         temp = I915_READ(LVDS);
4331         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4332         if (pipe == 1) {
4333                 temp |= LVDS_PIPEB_SELECT;
4334         } else {
4335                 temp &= ~LVDS_PIPEB_SELECT;
4336         }
4337         /* set the corresponsding LVDS_BORDER bit */
4338         temp |= dev_priv->lvds_border_bits;
4339         /* Set the B0-B3 data pairs corresponding to whether we're going to
4340          * set the DPLLs for dual-channel mode or not.
4341          */
4342         if (clock->p2 == 7)
4343                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4344         else
4345                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4346
4347         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4348          * appropriately here, but we need to look more thoroughly into how
4349          * panels behave in the two modes.
4350          */
4351         /* set the dithering flag on LVDS as needed */
4352         if (INTEL_INFO(dev)->gen >= 4) {
4353                 if (dev_priv->lvds_dither)
4354                         temp |= LVDS_ENABLE_DITHER;
4355                 else
4356                         temp &= ~LVDS_ENABLE_DITHER;
4357         }
4358         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4359         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4360                 temp |= LVDS_HSYNC_POLARITY;
4361         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4362                 temp |= LVDS_VSYNC_POLARITY;
4363         I915_WRITE(LVDS, temp);
4364 }
4365
4366 static void vlv_update_pll(struct drm_crtc *crtc,
4367                            struct drm_display_mode *mode,
4368                            struct drm_display_mode *adjusted_mode,
4369                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4370                            int num_connectors)
4371 {
4372         struct drm_device *dev = crtc->dev;
4373         struct drm_i915_private *dev_priv = dev->dev_private;
4374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4375         int pipe = intel_crtc->pipe;
4376         u32 dpll, mdiv, pdiv;
4377         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4378         bool is_sdvo;
4379         u32 temp;
4380
4381         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4382                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4383
4384         dpll = DPLL_VGA_MODE_DIS;
4385         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4386         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4387         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4388
4389         I915_WRITE(DPLL(pipe), dpll);
4390         POSTING_READ(DPLL(pipe));
4391
4392         bestn = clock->n;
4393         bestm1 = clock->m1;
4394         bestm2 = clock->m2;
4395         bestp1 = clock->p1;
4396         bestp2 = clock->p2;
4397
4398         /*
4399          * In Valleyview PLL and program lane counter registers are exposed
4400          * through DPIO interface
4401          */
4402         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4403         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4404         mdiv |= ((bestn << DPIO_N_SHIFT));
4405         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4406         mdiv |= (1 << DPIO_K_SHIFT);
4407         mdiv |= DPIO_ENABLE_CALIBRATION;
4408         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4409
4410         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4411
4412         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4413                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4414                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4415                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4416         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4417
4418         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4419
4420         dpll |= DPLL_VCO_ENABLE;
4421         I915_WRITE(DPLL(pipe), dpll);
4422         POSTING_READ(DPLL(pipe));
4423         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4424                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4425
4426         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4427
4428         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4429                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4430
4431         I915_WRITE(DPLL(pipe), dpll);
4432
4433         /* Wait for the clocks to stabilize. */
4434         POSTING_READ(DPLL(pipe));
4435         udelay(150);
4436
4437         temp = 0;
4438         if (is_sdvo) {
4439                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4440                 if (temp > 1)
4441                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4442                 else
4443                         temp = 0;
4444         }
4445         I915_WRITE(DPLL_MD(pipe), temp);
4446         POSTING_READ(DPLL_MD(pipe));
4447
4448         /* Now program lane control registers */
4449         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4450                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4451         {
4452                 temp = 0x1000C4;
4453                 if(pipe == 1)
4454                         temp |= (1 << 21);
4455                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4456         }
4457         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4458         {
4459                 temp = 0x1000C4;
4460                 if(pipe == 1)
4461                         temp |= (1 << 21);
4462                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4463         }
4464 }
4465
4466 static void i9xx_update_pll(struct drm_crtc *crtc,
4467                             struct drm_display_mode *mode,
4468                             struct drm_display_mode *adjusted_mode,
4469                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4470                             int num_connectors)
4471 {
4472         struct drm_device *dev = crtc->dev;
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475         int pipe = intel_crtc->pipe;
4476         u32 dpll;
4477         bool is_sdvo;
4478
4479         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4480
4481         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4482                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4483
4484         dpll = DPLL_VGA_MODE_DIS;
4485
4486         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4487                 dpll |= DPLLB_MODE_LVDS;
4488         else
4489                 dpll |= DPLLB_MODE_DAC_SERIAL;
4490         if (is_sdvo) {
4491                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4492                 if (pixel_multiplier > 1) {
4493                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4494                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4495                 }
4496                 dpll |= DPLL_DVO_HIGH_SPEED;
4497         }
4498         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4499                 dpll |= DPLL_DVO_HIGH_SPEED;
4500
4501         /* compute bitmask from p1 value */
4502         if (IS_PINEVIEW(dev))
4503                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4504         else {
4505                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4506                 if (IS_G4X(dev) && reduced_clock)
4507                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4508         }
4509         switch (clock->p2) {
4510         case 5:
4511                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4512                 break;
4513         case 7:
4514                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4515                 break;
4516         case 10:
4517                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4518                 break;
4519         case 14:
4520                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4521                 break;
4522         }
4523         if (INTEL_INFO(dev)->gen >= 4)
4524                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4525
4526         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4527                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4528         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4529                 /* XXX: just matching BIOS for now */
4530                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4531                 dpll |= 3;
4532         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4533                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4534                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4535         else
4536                 dpll |= PLL_REF_INPUT_DREFCLK;
4537
4538         dpll |= DPLL_VCO_ENABLE;
4539         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4540         POSTING_READ(DPLL(pipe));
4541         udelay(150);
4542
4543         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4544          * This is an exception to the general rule that mode_set doesn't turn
4545          * things on.
4546          */
4547         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4548                 intel_update_lvds(crtc, clock, adjusted_mode);
4549
4550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4551                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4552
4553         I915_WRITE(DPLL(pipe), dpll);
4554
4555         /* Wait for the clocks to stabilize. */
4556         POSTING_READ(DPLL(pipe));
4557         udelay(150);
4558
4559         if (INTEL_INFO(dev)->gen >= 4) {
4560                 u32 temp = 0;
4561                 if (is_sdvo) {
4562                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4563                         if (temp > 1)
4564                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4565                         else
4566                                 temp = 0;
4567                 }
4568                 I915_WRITE(DPLL_MD(pipe), temp);
4569         } else {
4570                 /* The pixel multiplier can only be updated once the
4571                  * DPLL is enabled and the clocks are stable.
4572                  *
4573                  * So write it again.
4574                  */
4575                 I915_WRITE(DPLL(pipe), dpll);
4576         }
4577 }
4578
4579 static void i8xx_update_pll(struct drm_crtc *crtc,
4580                             struct drm_display_mode *adjusted_mode,
4581                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4582                             int num_connectors)
4583 {
4584         struct drm_device *dev = crtc->dev;
4585         struct drm_i915_private *dev_priv = dev->dev_private;
4586         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4587         int pipe = intel_crtc->pipe;
4588         u32 dpll;
4589
4590         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4591
4592         dpll = DPLL_VGA_MODE_DIS;
4593
4594         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4595                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596         } else {
4597                 if (clock->p1 == 2)
4598                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4599                 else
4600                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4601                 if (clock->p2 == 4)
4602                         dpll |= PLL_P2_DIVIDE_BY_4;
4603         }
4604
4605         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4606                 /* XXX: just matching BIOS for now */
4607                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4608                 dpll |= 3;
4609         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4610                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4611                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4612         else
4613                 dpll |= PLL_REF_INPUT_DREFCLK;
4614
4615         dpll |= DPLL_VCO_ENABLE;
4616         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4617         POSTING_READ(DPLL(pipe));
4618         udelay(150);
4619
4620         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4621          * This is an exception to the general rule that mode_set doesn't turn
4622          * things on.
4623          */
4624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4625                 intel_update_lvds(crtc, clock, adjusted_mode);
4626
4627         I915_WRITE(DPLL(pipe), dpll);
4628
4629         /* Wait for the clocks to stabilize. */
4630         POSTING_READ(DPLL(pipe));
4631         udelay(150);
4632
4633         /* The pixel multiplier can only be updated once the
4634          * DPLL is enabled and the clocks are stable.
4635          *
4636          * So write it again.
4637          */
4638         I915_WRITE(DPLL(pipe), dpll);
4639 }
4640
4641 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4642                                    struct drm_display_mode *mode,
4643                                    struct drm_display_mode *adjusted_mode)
4644 {
4645         struct drm_device *dev = intel_crtc->base.dev;
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647         enum pipe pipe = intel_crtc->pipe;
4648         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4649         uint32_t vsyncshift;
4650
4651         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4652                 /* the chip adds 2 halflines automatically */
4653                 adjusted_mode->crtc_vtotal -= 1;
4654                 adjusted_mode->crtc_vblank_end -= 1;
4655                 vsyncshift = adjusted_mode->crtc_hsync_start
4656                              - adjusted_mode->crtc_htotal / 2;
4657         } else {
4658                 vsyncshift = 0;
4659         }
4660
4661         if (INTEL_INFO(dev)->gen > 3)
4662                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4663
4664         I915_WRITE(HTOTAL(cpu_transcoder),
4665                    (adjusted_mode->crtc_hdisplay - 1) |
4666                    ((adjusted_mode->crtc_htotal - 1) << 16));
4667         I915_WRITE(HBLANK(cpu_transcoder),
4668                    (adjusted_mode->crtc_hblank_start - 1) |
4669                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4670         I915_WRITE(HSYNC(cpu_transcoder),
4671                    (adjusted_mode->crtc_hsync_start - 1) |
4672                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4673
4674         I915_WRITE(VTOTAL(cpu_transcoder),
4675                    (adjusted_mode->crtc_vdisplay - 1) |
4676                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4677         I915_WRITE(VBLANK(cpu_transcoder),
4678                    (adjusted_mode->crtc_vblank_start - 1) |
4679                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4680         I915_WRITE(VSYNC(cpu_transcoder),
4681                    (adjusted_mode->crtc_vsync_start - 1) |
4682                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4683
4684         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4685          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4686          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4687          * bits. */
4688         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4689             (pipe == PIPE_B || pipe == PIPE_C))
4690                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4691
4692         /* pipesrc controls the size that is scaled from, which should
4693          * always be the user's requested size.
4694          */
4695         I915_WRITE(PIPESRC(pipe),
4696                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4697 }
4698
4699 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4700                               struct drm_display_mode *mode,
4701                               struct drm_display_mode *adjusted_mode,
4702                               int x, int y,
4703                               struct drm_framebuffer *fb)
4704 {
4705         struct drm_device *dev = crtc->dev;
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708         int pipe = intel_crtc->pipe;
4709         int plane = intel_crtc->plane;
4710         int refclk, num_connectors = 0;
4711         intel_clock_t clock, reduced_clock;
4712         u32 dspcntr, pipeconf;
4713         bool ok, has_reduced_clock = false, is_sdvo = false;
4714         bool is_lvds = false, is_tv = false, is_dp = false;
4715         struct intel_encoder *encoder;
4716         const intel_limit_t *limit;
4717         int ret;
4718
4719         for_each_encoder_on_crtc(dev, crtc, encoder) {
4720                 switch (encoder->type) {
4721                 case INTEL_OUTPUT_LVDS:
4722                         is_lvds = true;
4723                         break;
4724                 case INTEL_OUTPUT_SDVO:
4725                 case INTEL_OUTPUT_HDMI:
4726                         is_sdvo = true;
4727                         if (encoder->needs_tv_clock)
4728                                 is_tv = true;
4729                         break;
4730                 case INTEL_OUTPUT_TVOUT:
4731                         is_tv = true;
4732                         break;
4733                 case INTEL_OUTPUT_DISPLAYPORT:
4734                         is_dp = true;
4735                         break;
4736                 }
4737
4738                 num_connectors++;
4739         }
4740
4741         refclk = i9xx_get_refclk(crtc, num_connectors);
4742
4743         /*
4744          * Returns a set of divisors for the desired target clock with the given
4745          * refclk, or FALSE.  The returned values represent the clock equation:
4746          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4747          */
4748         limit = intel_limit(crtc, refclk);
4749         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4750                              &clock);
4751         if (!ok) {
4752                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4753                 return -EINVAL;
4754         }
4755
4756         /* Ensure that the cursor is valid for the new mode before changing... */
4757         intel_crtc_update_cursor(crtc, true);
4758
4759         if (is_lvds && dev_priv->lvds_downclock_avail) {
4760                 /*
4761                  * Ensure we match the reduced clock's P to the target clock.
4762                  * If the clocks don't match, we can't switch the display clock
4763                  * by using the FP0/FP1. In such case we will disable the LVDS
4764                  * downclock feature.
4765                 */
4766                 has_reduced_clock = limit->find_pll(limit, crtc,
4767                                                     dev_priv->lvds_downclock,
4768                                                     refclk,
4769                                                     &clock,
4770                                                     &reduced_clock);
4771         }
4772
4773         if (is_sdvo && is_tv)
4774                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4775
4776         if (IS_GEN2(dev))
4777                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4778                                 has_reduced_clock ? &reduced_clock : NULL,
4779                                 num_connectors);
4780         else if (IS_VALLEYVIEW(dev))
4781                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4782                                 has_reduced_clock ? &reduced_clock : NULL,
4783                                 num_connectors);
4784         else
4785                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4786                                 has_reduced_clock ? &reduced_clock : NULL,
4787                                 num_connectors);
4788
4789         /* setup pipeconf */
4790         pipeconf = I915_READ(PIPECONF(pipe));
4791
4792         /* Set up the display plane register */
4793         dspcntr = DISPPLANE_GAMMA_ENABLE;
4794
4795         if (pipe == 0)
4796                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4797         else
4798                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4799
4800         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4801                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4802                  * core speed.
4803                  *
4804                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4805                  * pipe == 0 check?
4806                  */
4807                 if (mode->clock >
4808                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4809                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4810                 else
4811                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4812         }
4813
4814         /* default to 8bpc */
4815         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4816         if (is_dp) {
4817                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4818                         pipeconf |= PIPECONF_BPP_6 |
4819                                     PIPECONF_DITHER_EN |
4820                                     PIPECONF_DITHER_TYPE_SP;
4821                 }
4822         }
4823
4824         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4825                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4826                         pipeconf |= PIPECONF_BPP_6 |
4827                                         PIPECONF_ENABLE |
4828                                         I965_PIPECONF_ACTIVE;
4829                 }
4830         }
4831
4832         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4833         drm_mode_debug_printmodeline(mode);
4834
4835         if (HAS_PIPE_CXSR(dev)) {
4836                 if (intel_crtc->lowfreq_avail) {
4837                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4838                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4839                 } else {
4840                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4841                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4842                 }
4843         }
4844
4845         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4846         if (!IS_GEN2(dev) &&
4847             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4848                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4849         else
4850                 pipeconf |= PIPECONF_PROGRESSIVE;
4851
4852         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4853
4854         /* pipesrc and dspsize control the size that is scaled from,
4855          * which should always be the user's requested size.
4856          */
4857         I915_WRITE(DSPSIZE(plane),
4858                    ((mode->vdisplay - 1) << 16) |
4859                    (mode->hdisplay - 1));
4860         I915_WRITE(DSPPOS(plane), 0);
4861
4862         I915_WRITE(PIPECONF(pipe), pipeconf);
4863         POSTING_READ(PIPECONF(pipe));
4864         intel_enable_pipe(dev_priv, pipe, false);
4865
4866         intel_wait_for_vblank(dev, pipe);
4867
4868         I915_WRITE(DSPCNTR(plane), dspcntr);
4869         POSTING_READ(DSPCNTR(plane));
4870
4871         ret = intel_pipe_set_base(crtc, x, y, fb);
4872
4873         intel_update_watermarks(dev);
4874
4875         return ret;
4876 }
4877
4878 /*
4879  * Initialize reference clocks when the driver loads
4880  */
4881 void ironlake_init_pch_refclk(struct drm_device *dev)
4882 {
4883         struct drm_i915_private *dev_priv = dev->dev_private;
4884         struct drm_mode_config *mode_config = &dev->mode_config;
4885         struct intel_encoder *encoder;
4886         u32 temp;
4887         bool has_lvds = false;
4888         bool has_cpu_edp = false;
4889         bool has_pch_edp = false;
4890         bool has_panel = false;
4891         bool has_ck505 = false;
4892         bool can_ssc = false;
4893
4894         /* We need to take the global config into account */
4895         list_for_each_entry(encoder, &mode_config->encoder_list,
4896                             base.head) {
4897                 switch (encoder->type) {
4898                 case INTEL_OUTPUT_LVDS:
4899                         has_panel = true;
4900                         has_lvds = true;
4901                         break;
4902                 case INTEL_OUTPUT_EDP:
4903                         has_panel = true;
4904                         if (intel_encoder_is_pch_edp(&encoder->base))
4905                                 has_pch_edp = true;
4906                         else
4907                                 has_cpu_edp = true;
4908                         break;
4909                 }
4910         }
4911
4912         if (HAS_PCH_IBX(dev)) {
4913                 has_ck505 = dev_priv->display_clock_mode;
4914                 can_ssc = has_ck505;
4915         } else {
4916                 has_ck505 = false;
4917                 can_ssc = true;
4918         }
4919
4920         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4921                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4922                       has_ck505);
4923
4924         /* Ironlake: try to setup display ref clock before DPLL
4925          * enabling. This is only under driver's control after
4926          * PCH B stepping, previous chipset stepping should be
4927          * ignoring this setting.
4928          */
4929         temp = I915_READ(PCH_DREF_CONTROL);
4930         /* Always enable nonspread source */
4931         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4932
4933         if (has_ck505)
4934                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4935         else
4936                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4937
4938         if (has_panel) {
4939                 temp &= ~DREF_SSC_SOURCE_MASK;
4940                 temp |= DREF_SSC_SOURCE_ENABLE;
4941
4942                 /* SSC must be turned on before enabling the CPU output  */
4943                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4944                         DRM_DEBUG_KMS("Using SSC on panel\n");
4945                         temp |= DREF_SSC1_ENABLE;
4946                 } else
4947                         temp &= ~DREF_SSC1_ENABLE;
4948
4949                 /* Get SSC going before enabling the outputs */
4950                 I915_WRITE(PCH_DREF_CONTROL, temp);
4951                 POSTING_READ(PCH_DREF_CONTROL);
4952                 udelay(200);
4953
4954                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4955
4956                 /* Enable CPU source on CPU attached eDP */
4957                 if (has_cpu_edp) {
4958                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4959                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4960                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4961                         }
4962                         else
4963                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4964                 } else
4965                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4966
4967                 I915_WRITE(PCH_DREF_CONTROL, temp);
4968                 POSTING_READ(PCH_DREF_CONTROL);
4969                 udelay(200);
4970         } else {
4971                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4972
4973                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4974
4975                 /* Turn off CPU output */
4976                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4977
4978                 I915_WRITE(PCH_DREF_CONTROL, temp);
4979                 POSTING_READ(PCH_DREF_CONTROL);
4980                 udelay(200);
4981
4982                 /* Turn off the SSC source */
4983                 temp &= ~DREF_SSC_SOURCE_MASK;
4984                 temp |= DREF_SSC_SOURCE_DISABLE;
4985
4986                 /* Turn off SSC1 */
4987                 temp &= ~ DREF_SSC1_ENABLE;
4988
4989                 I915_WRITE(PCH_DREF_CONTROL, temp);
4990                 POSTING_READ(PCH_DREF_CONTROL);
4991                 udelay(200);
4992         }
4993 }
4994
4995 static int ironlake_get_refclk(struct drm_crtc *crtc)
4996 {
4997         struct drm_device *dev = crtc->dev;
4998         struct drm_i915_private *dev_priv = dev->dev_private;
4999         struct intel_encoder *encoder;
5000         struct intel_encoder *edp_encoder = NULL;
5001         int num_connectors = 0;
5002         bool is_lvds = false;
5003
5004         for_each_encoder_on_crtc(dev, crtc, encoder) {
5005                 switch (encoder->type) {
5006                 case INTEL_OUTPUT_LVDS:
5007                         is_lvds = true;
5008                         break;
5009                 case INTEL_OUTPUT_EDP:
5010                         edp_encoder = encoder;
5011                         break;
5012                 }
5013                 num_connectors++;
5014         }
5015
5016         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5017                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5018                               dev_priv->lvds_ssc_freq);
5019                 return dev_priv->lvds_ssc_freq * 1000;
5020         }
5021
5022         return 120000;
5023 }
5024
5025 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5026                                   struct drm_display_mode *adjusted_mode,
5027                                   bool dither)
5028 {
5029         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031         int pipe = intel_crtc->pipe;
5032         uint32_t val;
5033
5034         val = I915_READ(PIPECONF(pipe));
5035
5036         val &= ~PIPE_BPC_MASK;
5037         switch (intel_crtc->bpp) {
5038         case 18:
5039                 val |= PIPE_6BPC;
5040                 break;
5041         case 24:
5042                 val |= PIPE_8BPC;
5043                 break;
5044         case 30:
5045                 val |= PIPE_10BPC;
5046                 break;
5047         case 36:
5048                 val |= PIPE_12BPC;
5049                 break;
5050         default:
5051                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5052                 BUG();
5053         }
5054
5055         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5056         if (dither)
5057                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5058
5059         val &= ~PIPECONF_INTERLACE_MASK;
5060         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5061                 val |= PIPECONF_INTERLACED_ILK;
5062         else
5063                 val |= PIPECONF_PROGRESSIVE;
5064
5065         I915_WRITE(PIPECONF(pipe), val);
5066         POSTING_READ(PIPECONF(pipe));
5067 }
5068
5069 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5070                                  struct drm_display_mode *adjusted_mode,
5071                                  bool dither)
5072 {
5073         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5075         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5076         uint32_t val;
5077
5078         val = I915_READ(PIPECONF(cpu_transcoder));
5079
5080         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5081         if (dither)
5082                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5083
5084         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5085         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5086                 val |= PIPECONF_INTERLACED_ILK;
5087         else
5088                 val |= PIPECONF_PROGRESSIVE;
5089
5090         I915_WRITE(PIPECONF(cpu_transcoder), val);
5091         POSTING_READ(PIPECONF(cpu_transcoder));
5092 }
5093
5094 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5095                                     struct drm_display_mode *adjusted_mode,
5096                                     intel_clock_t *clock,
5097                                     bool *has_reduced_clock,
5098                                     intel_clock_t *reduced_clock)
5099 {
5100         struct drm_device *dev = crtc->dev;
5101         struct drm_i915_private *dev_priv = dev->dev_private;
5102         struct intel_encoder *intel_encoder;
5103         int refclk;
5104         const intel_limit_t *limit;
5105         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5106
5107         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5108                 switch (intel_encoder->type) {
5109                 case INTEL_OUTPUT_LVDS:
5110                         is_lvds = true;
5111                         break;
5112                 case INTEL_OUTPUT_SDVO:
5113                 case INTEL_OUTPUT_HDMI:
5114                         is_sdvo = true;
5115                         if (intel_encoder->needs_tv_clock)
5116                                 is_tv = true;
5117                         break;
5118                 case INTEL_OUTPUT_TVOUT:
5119                         is_tv = true;
5120                         break;
5121                 }
5122         }
5123
5124         refclk = ironlake_get_refclk(crtc);
5125
5126         /*
5127          * Returns a set of divisors for the desired target clock with the given
5128          * refclk, or FALSE.  The returned values represent the clock equation:
5129          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5130          */
5131         limit = intel_limit(crtc, refclk);
5132         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5133                               clock);
5134         if (!ret)
5135                 return false;
5136
5137         if (is_lvds && dev_priv->lvds_downclock_avail) {
5138                 /*
5139                  * Ensure we match the reduced clock's P to the target clock.
5140                  * If the clocks don't match, we can't switch the display clock
5141                  * by using the FP0/FP1. In such case we will disable the LVDS
5142                  * downclock feature.
5143                 */
5144                 *has_reduced_clock = limit->find_pll(limit, crtc,
5145                                                      dev_priv->lvds_downclock,
5146                                                      refclk,
5147                                                      clock,
5148                                                      reduced_clock);
5149         }
5150
5151         if (is_sdvo && is_tv)
5152                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5153
5154         return true;
5155 }
5156
5157 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5158 {
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160         uint32_t temp;
5161
5162         temp = I915_READ(SOUTH_CHICKEN1);
5163         if (temp & FDI_BC_BIFURCATION_SELECT)
5164                 return;
5165
5166         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5167         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5168
5169         temp |= FDI_BC_BIFURCATION_SELECT;
5170         DRM_DEBUG_KMS("enabling fdi C rx\n");
5171         I915_WRITE(SOUTH_CHICKEN1, temp);
5172         POSTING_READ(SOUTH_CHICKEN1);
5173 }
5174
5175 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5176 {
5177         struct drm_device *dev = intel_crtc->base.dev;
5178         struct drm_i915_private *dev_priv = dev->dev_private;
5179         struct intel_crtc *pipe_B_crtc =
5180                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5181
5182         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5183                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5184         if (intel_crtc->fdi_lanes > 4) {
5185                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5186                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5187                 /* Clamp lanes to avoid programming the hw with bogus values. */
5188                 intel_crtc->fdi_lanes = 4;
5189
5190                 return false;
5191         }
5192
5193         if (dev_priv->num_pipe == 2)
5194                 return true;
5195
5196         switch (intel_crtc->pipe) {
5197         case PIPE_A:
5198                 return true;
5199         case PIPE_B:
5200                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5201                     intel_crtc->fdi_lanes > 2) {
5202                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5203                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5204                         /* Clamp lanes to avoid programming the hw with bogus values. */
5205                         intel_crtc->fdi_lanes = 2;
5206
5207                         return false;
5208                 }
5209
5210                 if (intel_crtc->fdi_lanes > 2)
5211                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5212                 else
5213                         cpt_enable_fdi_bc_bifurcation(dev);
5214
5215                 return true;
5216         case PIPE_C:
5217                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5218                         if (intel_crtc->fdi_lanes > 2) {
5219                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5220                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5221                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5222                                 intel_crtc->fdi_lanes = 2;
5223
5224                                 return false;
5225                         }
5226                 } else {
5227                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5228                         return false;
5229                 }
5230
5231                 cpt_enable_fdi_bc_bifurcation(dev);
5232
5233                 return true;
5234         default:
5235                 BUG();
5236         }
5237 }
5238
5239 static void ironlake_set_m_n(struct drm_crtc *crtc,
5240                              struct drm_display_mode *mode,
5241                              struct drm_display_mode *adjusted_mode)
5242 {
5243         struct drm_device *dev = crtc->dev;
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5247         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5248         struct fdi_m_n m_n = {0};
5249         int target_clock, pixel_multiplier, lane, link_bw;
5250         bool is_dp = false, is_cpu_edp = false;
5251
5252         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5253                 switch (intel_encoder->type) {
5254                 case INTEL_OUTPUT_DISPLAYPORT:
5255                         is_dp = true;
5256                         break;
5257                 case INTEL_OUTPUT_EDP:
5258                         is_dp = true;
5259                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5260                                 is_cpu_edp = true;
5261                         edp_encoder = intel_encoder;
5262                         break;
5263                 }
5264         }
5265
5266         /* FDI link */
5267         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5268         lane = 0;
5269         /* CPU eDP doesn't require FDI link, so just set DP M/N
5270            according to current link config */
5271         if (is_cpu_edp) {
5272                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5273         } else {
5274                 /* FDI is a binary signal running at ~2.7GHz, encoding
5275                  * each output octet as 10 bits. The actual frequency
5276                  * is stored as a divider into a 100MHz clock, and the
5277                  * mode pixel clock is stored in units of 1KHz.
5278                  * Hence the bw of each lane in terms of the mode signal
5279                  * is:
5280                  */
5281                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5282         }
5283
5284         /* [e]DP over FDI requires target mode clock instead of link clock. */
5285         if (edp_encoder)
5286                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5287         else if (is_dp)
5288                 target_clock = mode->clock;
5289         else
5290                 target_clock = adjusted_mode->clock;
5291
5292         if (!lane) {
5293                 /*
5294                  * Account for spread spectrum to avoid
5295                  * oversubscribing the link. Max center spread
5296                  * is 2.5%; use 5% for safety's sake.
5297                  */
5298                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5299                 lane = bps / (link_bw * 8) + 1;
5300         }
5301
5302         intel_crtc->fdi_lanes = lane;
5303
5304         if (pixel_multiplier > 1)
5305                 link_bw *= pixel_multiplier;
5306         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5307                              &m_n);
5308
5309         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5310         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5311         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5312         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5313 }
5314
5315 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5316                                       struct drm_display_mode *adjusted_mode,
5317                                       intel_clock_t *clock, u32 fp)
5318 {
5319         struct drm_crtc *crtc = &intel_crtc->base;
5320         struct drm_device *dev = crtc->dev;
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322         struct intel_encoder *intel_encoder;
5323         uint32_t dpll;
5324         int factor, pixel_multiplier, num_connectors = 0;
5325         bool is_lvds = false, is_sdvo = false, is_tv = false;
5326         bool is_dp = false, is_cpu_edp = false;
5327
5328         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5329                 switch (intel_encoder->type) {
5330                 case INTEL_OUTPUT_LVDS:
5331                         is_lvds = true;
5332                         break;
5333                 case INTEL_OUTPUT_SDVO:
5334                 case INTEL_OUTPUT_HDMI:
5335                         is_sdvo = true;
5336                         if (intel_encoder->needs_tv_clock)
5337                                 is_tv = true;
5338                         break;
5339                 case INTEL_OUTPUT_TVOUT:
5340                         is_tv = true;
5341                         break;
5342                 case INTEL_OUTPUT_DISPLAYPORT:
5343                         is_dp = true;
5344                         break;
5345                 case INTEL_OUTPUT_EDP:
5346                         is_dp = true;
5347                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5348                                 is_cpu_edp = true;
5349                         break;
5350                 }
5351
5352                 num_connectors++;
5353         }
5354
5355         /* Enable autotuning of the PLL clock (if permissible) */
5356         factor = 21;
5357         if (is_lvds) {
5358                 if ((intel_panel_use_ssc(dev_priv) &&
5359                      dev_priv->lvds_ssc_freq == 100) ||
5360                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5361                         factor = 25;
5362         } else if (is_sdvo && is_tv)
5363                 factor = 20;
5364
5365         if (clock->m < factor * clock->n)
5366                 fp |= FP_CB_TUNE;
5367
5368         dpll = 0;
5369
5370         if (is_lvds)
5371                 dpll |= DPLLB_MODE_LVDS;
5372         else
5373                 dpll |= DPLLB_MODE_DAC_SERIAL;
5374         if (is_sdvo) {
5375                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5376                 if (pixel_multiplier > 1) {
5377                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5378                 }
5379                 dpll |= DPLL_DVO_HIGH_SPEED;
5380         }
5381         if (is_dp && !is_cpu_edp)
5382                 dpll |= DPLL_DVO_HIGH_SPEED;
5383
5384         /* compute bitmask from p1 value */
5385         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5386         /* also FPA1 */
5387         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5388
5389         switch (clock->p2) {
5390         case 5:
5391                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5392                 break;
5393         case 7:
5394                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5395                 break;
5396         case 10:
5397                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5398                 break;
5399         case 14:
5400                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5401                 break;
5402         }
5403
5404         if (is_sdvo && is_tv)
5405                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5406         else if (is_tv)
5407                 /* XXX: just matching BIOS for now */
5408                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5409                 dpll |= 3;
5410         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5411                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5412         else
5413                 dpll |= PLL_REF_INPUT_DREFCLK;
5414
5415         return dpll;
5416 }
5417
5418 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5419                                   struct drm_display_mode *mode,
5420                                   struct drm_display_mode *adjusted_mode,
5421                                   int x, int y,
5422                                   struct drm_framebuffer *fb)
5423 {
5424         struct drm_device *dev = crtc->dev;
5425         struct drm_i915_private *dev_priv = dev->dev_private;
5426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427         int pipe = intel_crtc->pipe;
5428         int plane = intel_crtc->plane;
5429         int num_connectors = 0;
5430         intel_clock_t clock, reduced_clock;
5431         u32 dpll, fp = 0, fp2 = 0;
5432         bool ok, has_reduced_clock = false;
5433         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5434         struct intel_encoder *encoder;
5435         u32 temp;
5436         int ret;
5437         bool dither, fdi_config_ok;
5438
5439         for_each_encoder_on_crtc(dev, crtc, encoder) {
5440                 switch (encoder->type) {
5441                 case INTEL_OUTPUT_LVDS:
5442                         is_lvds = true;
5443                         break;
5444                 case INTEL_OUTPUT_DISPLAYPORT:
5445                         is_dp = true;
5446                         break;
5447                 case INTEL_OUTPUT_EDP:
5448                         is_dp = true;
5449                         if (!intel_encoder_is_pch_edp(&encoder->base))
5450                                 is_cpu_edp = true;
5451                         break;
5452                 }
5453
5454                 num_connectors++;
5455         }
5456
5457         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5458              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5459
5460         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5461                                      &has_reduced_clock, &reduced_clock);
5462         if (!ok) {
5463                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5464                 return -EINVAL;
5465         }
5466
5467         /* Ensure that the cursor is valid for the new mode before changing... */
5468         intel_crtc_update_cursor(crtc, true);
5469
5470         /* determine panel color depth */
5471         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5472                                               adjusted_mode);
5473         if (is_lvds && dev_priv->lvds_dither)
5474                 dither = true;
5475
5476         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5477         if (has_reduced_clock)
5478                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5479                         reduced_clock.m2;
5480
5481         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5482
5483         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5484         drm_mode_debug_printmodeline(mode);
5485
5486         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5487         if (!is_cpu_edp) {
5488                 struct intel_pch_pll *pll;
5489
5490                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5491                 if (pll == NULL) {
5492                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5493                                          pipe);
5494                         return -EINVAL;
5495                 }
5496         } else
5497                 intel_put_pch_pll(intel_crtc);
5498
5499         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5500          * This is an exception to the general rule that mode_set doesn't turn
5501          * things on.
5502          */
5503         if (is_lvds) {
5504                 temp = I915_READ(PCH_LVDS);
5505                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5506                 if (HAS_PCH_CPT(dev)) {
5507                         temp &= ~PORT_TRANS_SEL_MASK;
5508                         temp |= PORT_TRANS_SEL_CPT(pipe);
5509                 } else {
5510                         if (pipe == 1)
5511                                 temp |= LVDS_PIPEB_SELECT;
5512                         else
5513                                 temp &= ~LVDS_PIPEB_SELECT;
5514                 }
5515
5516                 /* set the corresponsding LVDS_BORDER bit */
5517                 temp |= dev_priv->lvds_border_bits;
5518                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5519                  * set the DPLLs for dual-channel mode or not.
5520                  */
5521                 if (clock.p2 == 7)
5522                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5523                 else
5524                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5525
5526                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5527                  * appropriately here, but we need to look more thoroughly into how
5528                  * panels behave in the two modes.
5529                  */
5530                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5531                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5532                         temp |= LVDS_HSYNC_POLARITY;
5533                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5534                         temp |= LVDS_VSYNC_POLARITY;
5535                 I915_WRITE(PCH_LVDS, temp);
5536         }
5537
5538         if (is_dp && !is_cpu_edp) {
5539                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5540         } else {
5541                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5542                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5543                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5544                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5545                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5546         }
5547
5548         if (intel_crtc->pch_pll) {
5549                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5550
5551                 /* Wait for the clocks to stabilize. */
5552                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5553                 udelay(150);
5554
5555                 /* The pixel multiplier can only be updated once the
5556                  * DPLL is enabled and the clocks are stable.
5557                  *
5558                  * So write it again.
5559                  */
5560                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5561         }
5562
5563         intel_crtc->lowfreq_avail = false;
5564         if (intel_crtc->pch_pll) {
5565                 if (is_lvds && has_reduced_clock && i915_powersave) {
5566                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5567                         intel_crtc->lowfreq_avail = true;
5568                 } else {
5569                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5570                 }
5571         }
5572
5573         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5574
5575         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5576          * ironlake_check_fdi_lanes. */
5577         ironlake_set_m_n(crtc, mode, adjusted_mode);
5578
5579         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5580
5581         if (is_cpu_edp)
5582                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5583
5584         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5585
5586         intel_wait_for_vblank(dev, pipe);
5587
5588         /* Set up the display plane register */
5589         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5590         POSTING_READ(DSPCNTR(plane));
5591
5592         ret = intel_pipe_set_base(crtc, x, y, fb);
5593
5594         intel_update_watermarks(dev);
5595
5596         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5597
5598         return fdi_config_ok ? ret : -EINVAL;
5599 }
5600
5601 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5602                                  struct drm_display_mode *mode,
5603                                  struct drm_display_mode *adjusted_mode,
5604                                  int x, int y,
5605                                  struct drm_framebuffer *fb)
5606 {
5607         struct drm_device *dev = crtc->dev;
5608         struct drm_i915_private *dev_priv = dev->dev_private;
5609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5610         int pipe = intel_crtc->pipe;
5611         int plane = intel_crtc->plane;
5612         int num_connectors = 0;
5613         intel_clock_t clock, reduced_clock;
5614         u32 dpll = 0, fp = 0, fp2 = 0;
5615         bool ok, has_reduced_clock = false;
5616         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5617         struct intel_encoder *encoder;
5618         u32 temp;
5619         int ret;
5620         bool dither;
5621
5622         for_each_encoder_on_crtc(dev, crtc, encoder) {
5623                 switch (encoder->type) {
5624                 case INTEL_OUTPUT_LVDS:
5625                         is_lvds = true;
5626                         break;
5627                 case INTEL_OUTPUT_DISPLAYPORT:
5628                         is_dp = true;
5629                         break;
5630                 case INTEL_OUTPUT_EDP:
5631                         is_dp = true;
5632                         if (!intel_encoder_is_pch_edp(&encoder->base))
5633                                 is_cpu_edp = true;
5634                         break;
5635                 }
5636
5637                 num_connectors++;
5638         }
5639
5640         if (is_cpu_edp)
5641                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5642         else
5643                 intel_crtc->cpu_transcoder = pipe;
5644
5645         /* We are not sure yet this won't happen. */
5646         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5647              INTEL_PCH_TYPE(dev));
5648
5649         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5650              num_connectors, pipe_name(pipe));
5651
5652         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5653                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5654
5655         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5656
5657         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5658                 return -EINVAL;
5659
5660         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5661                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5662                                              &has_reduced_clock,
5663                                              &reduced_clock);
5664                 if (!ok) {
5665                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5666                         return -EINVAL;
5667                 }
5668         }
5669
5670         /* Ensure that the cursor is valid for the new mode before changing... */
5671         intel_crtc_update_cursor(crtc, true);
5672
5673         /* determine panel color depth */
5674         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5675                                               adjusted_mode);
5676         if (is_lvds && dev_priv->lvds_dither)
5677                 dither = true;
5678
5679         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5680         drm_mode_debug_printmodeline(mode);
5681
5682         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5683                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5684                 if (has_reduced_clock)
5685                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5686                               reduced_clock.m2;
5687
5688                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5689                                              fp);
5690
5691                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5692                  * own on pre-Haswell/LPT generation */
5693                 if (!is_cpu_edp) {
5694                         struct intel_pch_pll *pll;
5695
5696                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5697                         if (pll == NULL) {
5698                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5699                                                  pipe);
5700                                 return -EINVAL;
5701                         }
5702                 } else
5703                         intel_put_pch_pll(intel_crtc);
5704
5705                 /* The LVDS pin pair needs to be on before the DPLLs are
5706                  * enabled.  This is an exception to the general rule that
5707                  * mode_set doesn't turn things on.
5708                  */
5709                 if (is_lvds) {
5710                         temp = I915_READ(PCH_LVDS);
5711                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5712                         if (HAS_PCH_CPT(dev)) {
5713                                 temp &= ~PORT_TRANS_SEL_MASK;
5714                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5715                         } else {
5716                                 if (pipe == 1)
5717                                         temp |= LVDS_PIPEB_SELECT;
5718                                 else
5719                                         temp &= ~LVDS_PIPEB_SELECT;
5720                         }
5721
5722                         /* set the corresponsding LVDS_BORDER bit */
5723                         temp |= dev_priv->lvds_border_bits;
5724                         /* Set the B0-B3 data pairs corresponding to whether
5725                          * we're going to set the DPLLs for dual-channel mode or
5726                          * not.
5727                          */
5728                         if (clock.p2 == 7)
5729                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5730                         else
5731                                 temp &= ~(LVDS_B0B3_POWER_UP |
5732                                           LVDS_CLKB_POWER_UP);
5733
5734                         /* It would be nice to set 24 vs 18-bit mode
5735                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5736                          * look more thoroughly into how panels behave in the
5737                          * two modes.
5738                          */
5739                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5740                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5741                                 temp |= LVDS_HSYNC_POLARITY;
5742                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5743                                 temp |= LVDS_VSYNC_POLARITY;
5744                         I915_WRITE(PCH_LVDS, temp);
5745                 }
5746         }
5747
5748         if (is_dp && !is_cpu_edp) {
5749                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5750         } else {
5751                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5752                         /* For non-DP output, clear any trans DP clock recovery
5753                          * setting.*/
5754                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5755                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5756                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5757                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5758                 }
5759         }
5760
5761         intel_crtc->lowfreq_avail = false;
5762         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5763                 if (intel_crtc->pch_pll) {
5764                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5765
5766                         /* Wait for the clocks to stabilize. */
5767                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5768                         udelay(150);
5769
5770                         /* The pixel multiplier can only be updated once the
5771                          * DPLL is enabled and the clocks are stable.
5772                          *
5773                          * So write it again.
5774                          */
5775                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5776                 }
5777
5778                 if (intel_crtc->pch_pll) {
5779                         if (is_lvds && has_reduced_clock && i915_powersave) {
5780                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5781                                 intel_crtc->lowfreq_avail = true;
5782                         } else {
5783                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5784                         }
5785                 }
5786         }
5787
5788         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5789
5790         if (!is_dp || is_cpu_edp)
5791                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5792
5793         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5794                 if (is_cpu_edp)
5795                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5796
5797         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5798
5799         /* Set up the display plane register */
5800         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5801         POSTING_READ(DSPCNTR(plane));
5802
5803         ret = intel_pipe_set_base(crtc, x, y, fb);
5804
5805         intel_update_watermarks(dev);
5806
5807         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5808
5809         return ret;
5810 }
5811
5812 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5813                                struct drm_display_mode *mode,
5814                                struct drm_display_mode *adjusted_mode,
5815                                int x, int y,
5816                                struct drm_framebuffer *fb)
5817 {
5818         struct drm_device *dev = crtc->dev;
5819         struct drm_i915_private *dev_priv = dev->dev_private;
5820         struct drm_encoder_helper_funcs *encoder_funcs;
5821         struct intel_encoder *encoder;
5822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5823         int pipe = intel_crtc->pipe;
5824         int ret;
5825
5826         drm_vblank_pre_modeset(dev, pipe);
5827
5828         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5829                                               x, y, fb);
5830         drm_vblank_post_modeset(dev, pipe);
5831
5832         if (ret != 0)
5833                 return ret;
5834
5835         for_each_encoder_on_crtc(dev, crtc, encoder) {
5836                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5837                         encoder->base.base.id,
5838                         drm_get_encoder_name(&encoder->base),
5839                         mode->base.id, mode->name);
5840                 encoder_funcs = encoder->base.helper_private;
5841                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5842         }
5843
5844         return 0;
5845 }
5846
5847 static bool intel_eld_uptodate(struct drm_connector *connector,
5848                                int reg_eldv, uint32_t bits_eldv,
5849                                int reg_elda, uint32_t bits_elda,
5850                                int reg_edid)
5851 {
5852         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5853         uint8_t *eld = connector->eld;
5854         uint32_t i;
5855
5856         i = I915_READ(reg_eldv);
5857         i &= bits_eldv;
5858
5859         if (!eld[0])
5860                 return !i;
5861
5862         if (!i)
5863                 return false;
5864
5865         i = I915_READ(reg_elda);
5866         i &= ~bits_elda;
5867         I915_WRITE(reg_elda, i);
5868
5869         for (i = 0; i < eld[2]; i++)
5870                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5871                         return false;
5872
5873         return true;
5874 }
5875
5876 static void g4x_write_eld(struct drm_connector *connector,
5877                           struct drm_crtc *crtc)
5878 {
5879         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5880         uint8_t *eld = connector->eld;
5881         uint32_t eldv;
5882         uint32_t len;
5883         uint32_t i;
5884
5885         i = I915_READ(G4X_AUD_VID_DID);
5886
5887         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5888                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5889         else
5890                 eldv = G4X_ELDV_DEVCTG;
5891
5892         if (intel_eld_uptodate(connector,
5893                                G4X_AUD_CNTL_ST, eldv,
5894                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5895                                G4X_HDMIW_HDMIEDID))
5896                 return;
5897
5898         i = I915_READ(G4X_AUD_CNTL_ST);
5899         i &= ~(eldv | G4X_ELD_ADDR);
5900         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5901         I915_WRITE(G4X_AUD_CNTL_ST, i);
5902
5903         if (!eld[0])
5904                 return;
5905
5906         len = min_t(uint8_t, eld[2], len);
5907         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5908         for (i = 0; i < len; i++)
5909                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5910
5911         i = I915_READ(G4X_AUD_CNTL_ST);
5912         i |= eldv;
5913         I915_WRITE(G4X_AUD_CNTL_ST, i);
5914 }
5915
5916 static void haswell_write_eld(struct drm_connector *connector,
5917                                      struct drm_crtc *crtc)
5918 {
5919         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5920         uint8_t *eld = connector->eld;
5921         struct drm_device *dev = crtc->dev;
5922         uint32_t eldv;
5923         uint32_t i;
5924         int len;
5925         int pipe = to_intel_crtc(crtc)->pipe;
5926         int tmp;
5927
5928         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5929         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5930         int aud_config = HSW_AUD_CFG(pipe);
5931         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5932
5933
5934         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5935
5936         /* Audio output enable */
5937         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5938         tmp = I915_READ(aud_cntrl_st2);
5939         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5940         I915_WRITE(aud_cntrl_st2, tmp);
5941
5942         /* Wait for 1 vertical blank */
5943         intel_wait_for_vblank(dev, pipe);
5944
5945         /* Set ELD valid state */
5946         tmp = I915_READ(aud_cntrl_st2);
5947         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5948         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5949         I915_WRITE(aud_cntrl_st2, tmp);
5950         tmp = I915_READ(aud_cntrl_st2);
5951         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5952
5953         /* Enable HDMI mode */
5954         tmp = I915_READ(aud_config);
5955         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5956         /* clear N_programing_enable and N_value_index */
5957         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5958         I915_WRITE(aud_config, tmp);
5959
5960         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5961
5962         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5963
5964         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5965                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5966                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5967                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5968         } else
5969                 I915_WRITE(aud_config, 0);
5970
5971         if (intel_eld_uptodate(connector,
5972                                aud_cntrl_st2, eldv,
5973                                aud_cntl_st, IBX_ELD_ADDRESS,
5974                                hdmiw_hdmiedid))
5975                 return;
5976
5977         i = I915_READ(aud_cntrl_st2);
5978         i &= ~eldv;
5979         I915_WRITE(aud_cntrl_st2, i);
5980
5981         if (!eld[0])
5982                 return;
5983
5984         i = I915_READ(aud_cntl_st);
5985         i &= ~IBX_ELD_ADDRESS;
5986         I915_WRITE(aud_cntl_st, i);
5987         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5988         DRM_DEBUG_DRIVER("port num:%d\n", i);
5989
5990         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5991         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5992         for (i = 0; i < len; i++)
5993                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5994
5995         i = I915_READ(aud_cntrl_st2);
5996         i |= eldv;
5997         I915_WRITE(aud_cntrl_st2, i);
5998
5999 }
6000
6001 static void ironlake_write_eld(struct drm_connector *connector,
6002                                      struct drm_crtc *crtc)
6003 {
6004         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6005         uint8_t *eld = connector->eld;
6006         uint32_t eldv;
6007         uint32_t i;
6008         int len;
6009         int hdmiw_hdmiedid;
6010         int aud_config;
6011         int aud_cntl_st;
6012         int aud_cntrl_st2;
6013         int pipe = to_intel_crtc(crtc)->pipe;
6014
6015         if (HAS_PCH_IBX(connector->dev)) {
6016                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6017                 aud_config = IBX_AUD_CFG(pipe);
6018                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6019                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6020         } else {
6021                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6022                 aud_config = CPT_AUD_CFG(pipe);
6023                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6024                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6025         }
6026
6027         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6028
6029         i = I915_READ(aud_cntl_st);
6030         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6031         if (!i) {
6032                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6033                 /* operate blindly on all ports */
6034                 eldv = IBX_ELD_VALIDB;
6035                 eldv |= IBX_ELD_VALIDB << 4;
6036                 eldv |= IBX_ELD_VALIDB << 8;
6037         } else {
6038                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6039                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6040         }
6041
6042         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6043                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6044                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6045                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6046         } else
6047                 I915_WRITE(aud_config, 0);
6048
6049         if (intel_eld_uptodate(connector,
6050                                aud_cntrl_st2, eldv,
6051                                aud_cntl_st, IBX_ELD_ADDRESS,
6052                                hdmiw_hdmiedid))
6053                 return;
6054
6055         i = I915_READ(aud_cntrl_st2);
6056         i &= ~eldv;
6057         I915_WRITE(aud_cntrl_st2, i);
6058
6059         if (!eld[0])
6060                 return;
6061
6062         i = I915_READ(aud_cntl_st);
6063         i &= ~IBX_ELD_ADDRESS;
6064         I915_WRITE(aud_cntl_st, i);
6065
6066         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6067         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6068         for (i = 0; i < len; i++)
6069                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6070
6071         i = I915_READ(aud_cntrl_st2);
6072         i |= eldv;
6073         I915_WRITE(aud_cntrl_st2, i);
6074 }
6075
6076 void intel_write_eld(struct drm_encoder *encoder,
6077                      struct drm_display_mode *mode)
6078 {
6079         struct drm_crtc *crtc = encoder->crtc;
6080         struct drm_connector *connector;
6081         struct drm_device *dev = encoder->dev;
6082         struct drm_i915_private *dev_priv = dev->dev_private;
6083
6084         connector = drm_select_eld(encoder, mode);
6085         if (!connector)
6086                 return;
6087
6088         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6089                          connector->base.id,
6090                          drm_get_connector_name(connector),
6091                          connector->encoder->base.id,
6092                          drm_get_encoder_name(connector->encoder));
6093
6094         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6095
6096         if (dev_priv->display.write_eld)
6097                 dev_priv->display.write_eld(connector, crtc);
6098 }
6099
6100 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6101 void intel_crtc_load_lut(struct drm_crtc *crtc)
6102 {
6103         struct drm_device *dev = crtc->dev;
6104         struct drm_i915_private *dev_priv = dev->dev_private;
6105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6106         int palreg = PALETTE(intel_crtc->pipe);
6107         int i;
6108
6109         /* The clocks have to be on to load the palette. */
6110         if (!crtc->enabled || !intel_crtc->active)
6111                 return;
6112
6113         /* use legacy palette for Ironlake */
6114         if (HAS_PCH_SPLIT(dev))
6115                 palreg = LGC_PALETTE(intel_crtc->pipe);
6116
6117         for (i = 0; i < 256; i++) {
6118                 I915_WRITE(palreg + 4 * i,
6119                            (intel_crtc->lut_r[i] << 16) |
6120                            (intel_crtc->lut_g[i] << 8) |
6121                            intel_crtc->lut_b[i]);
6122         }
6123 }
6124
6125 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6126 {
6127         struct drm_device *dev = crtc->dev;
6128         struct drm_i915_private *dev_priv = dev->dev_private;
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130         bool visible = base != 0;
6131         u32 cntl;
6132
6133         if (intel_crtc->cursor_visible == visible)
6134                 return;
6135
6136         cntl = I915_READ(_CURACNTR);
6137         if (visible) {
6138                 /* On these chipsets we can only modify the base whilst
6139                  * the cursor is disabled.
6140                  */
6141                 I915_WRITE(_CURABASE, base);
6142
6143                 cntl &= ~(CURSOR_FORMAT_MASK);
6144                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6145                 cntl |= CURSOR_ENABLE |
6146                         CURSOR_GAMMA_ENABLE |
6147                         CURSOR_FORMAT_ARGB;
6148         } else
6149                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6150         I915_WRITE(_CURACNTR, cntl);
6151
6152         intel_crtc->cursor_visible = visible;
6153 }
6154
6155 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6156 {
6157         struct drm_device *dev = crtc->dev;
6158         struct drm_i915_private *dev_priv = dev->dev_private;
6159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160         int pipe = intel_crtc->pipe;
6161         bool visible = base != 0;
6162
6163         if (intel_crtc->cursor_visible != visible) {
6164                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6165                 if (base) {
6166                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6167                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6168                         cntl |= pipe << 28; /* Connect to correct pipe */
6169                 } else {
6170                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6171                         cntl |= CURSOR_MODE_DISABLE;
6172                 }
6173                 I915_WRITE(CURCNTR(pipe), cntl);
6174
6175                 intel_crtc->cursor_visible = visible;
6176         }
6177         /* and commit changes on next vblank */
6178         I915_WRITE(CURBASE(pipe), base);
6179 }
6180
6181 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6182 {
6183         struct drm_device *dev = crtc->dev;
6184         struct drm_i915_private *dev_priv = dev->dev_private;
6185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186         int pipe = intel_crtc->pipe;
6187         bool visible = base != 0;
6188
6189         if (intel_crtc->cursor_visible != visible) {
6190                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6191                 if (base) {
6192                         cntl &= ~CURSOR_MODE;
6193                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6194                 } else {
6195                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6196                         cntl |= CURSOR_MODE_DISABLE;
6197                 }
6198                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6199
6200                 intel_crtc->cursor_visible = visible;
6201         }
6202         /* and commit changes on next vblank */
6203         I915_WRITE(CURBASE_IVB(pipe), base);
6204 }
6205
6206 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6207 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6208                                      bool on)
6209 {
6210         struct drm_device *dev = crtc->dev;
6211         struct drm_i915_private *dev_priv = dev->dev_private;
6212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213         int pipe = intel_crtc->pipe;
6214         int x = intel_crtc->cursor_x;
6215         int y = intel_crtc->cursor_y;
6216         u32 base, pos;
6217         bool visible;
6218
6219         pos = 0;
6220
6221         if (on && crtc->enabled && crtc->fb) {
6222                 base = intel_crtc->cursor_addr;
6223                 if (x > (int) crtc->fb->width)
6224                         base = 0;
6225
6226                 if (y > (int) crtc->fb->height)
6227                         base = 0;
6228         } else
6229                 base = 0;
6230
6231         if (x < 0) {
6232                 if (x + intel_crtc->cursor_width < 0)
6233                         base = 0;
6234
6235                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6236                 x = -x;
6237         }
6238         pos |= x << CURSOR_X_SHIFT;
6239
6240         if (y < 0) {
6241                 if (y + intel_crtc->cursor_height < 0)
6242                         base = 0;
6243
6244                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6245                 y = -y;
6246         }
6247         pos |= y << CURSOR_Y_SHIFT;
6248
6249         visible = base != 0;
6250         if (!visible && !intel_crtc->cursor_visible)
6251                 return;
6252
6253         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6254                 I915_WRITE(CURPOS_IVB(pipe), pos);
6255                 ivb_update_cursor(crtc, base);
6256         } else {
6257                 I915_WRITE(CURPOS(pipe), pos);
6258                 if (IS_845G(dev) || IS_I865G(dev))
6259                         i845_update_cursor(crtc, base);
6260                 else
6261                         i9xx_update_cursor(crtc, base);
6262         }
6263 }
6264
6265 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6266                                  struct drm_file *file,
6267                                  uint32_t handle,
6268                                  uint32_t width, uint32_t height)
6269 {
6270         struct drm_device *dev = crtc->dev;
6271         struct drm_i915_private *dev_priv = dev->dev_private;
6272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273         struct drm_i915_gem_object *obj;
6274         uint32_t addr;
6275         int ret;
6276
6277         /* if we want to turn off the cursor ignore width and height */
6278         if (!handle) {
6279                 DRM_DEBUG_KMS("cursor off\n");
6280                 addr = 0;
6281                 obj = NULL;
6282                 mutex_lock(&dev->struct_mutex);
6283                 goto finish;
6284         }
6285
6286         /* Currently we only support 64x64 cursors */
6287         if (width != 64 || height != 64) {
6288                 DRM_ERROR("we currently only support 64x64 cursors\n");
6289                 return -EINVAL;
6290         }
6291
6292         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6293         if (&obj->base == NULL)
6294                 return -ENOENT;
6295
6296         if (obj->base.size < width * height * 4) {
6297                 DRM_ERROR("buffer is to small\n");
6298                 ret = -ENOMEM;
6299                 goto fail;
6300         }
6301
6302         /* we only need to pin inside GTT if cursor is non-phy */
6303         mutex_lock(&dev->struct_mutex);
6304         if (!dev_priv->info->cursor_needs_physical) {
6305                 if (obj->tiling_mode) {
6306                         DRM_ERROR("cursor cannot be tiled\n");
6307                         ret = -EINVAL;
6308                         goto fail_locked;
6309                 }
6310
6311                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6312                 if (ret) {
6313                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6314                         goto fail_locked;
6315                 }
6316
6317                 ret = i915_gem_object_put_fence(obj);
6318                 if (ret) {
6319                         DRM_ERROR("failed to release fence for cursor");
6320                         goto fail_unpin;
6321                 }
6322
6323                 addr = obj->gtt_offset;
6324         } else {
6325                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6326                 ret = i915_gem_attach_phys_object(dev, obj,
6327                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6328                                                   align);
6329                 if (ret) {
6330                         DRM_ERROR("failed to attach phys object\n");
6331                         goto fail_locked;
6332                 }
6333                 addr = obj->phys_obj->handle->busaddr;
6334         }
6335
6336         if (IS_GEN2(dev))
6337                 I915_WRITE(CURSIZE, (height << 12) | width);
6338
6339  finish:
6340         if (intel_crtc->cursor_bo) {
6341                 if (dev_priv->info->cursor_needs_physical) {
6342                         if (intel_crtc->cursor_bo != obj)
6343                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6344                 } else
6345                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6346                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6347         }
6348
6349         mutex_unlock(&dev->struct_mutex);
6350
6351         intel_crtc->cursor_addr = addr;
6352         intel_crtc->cursor_bo = obj;
6353         intel_crtc->cursor_width = width;
6354         intel_crtc->cursor_height = height;
6355
6356         intel_crtc_update_cursor(crtc, true);
6357
6358         return 0;
6359 fail_unpin:
6360         i915_gem_object_unpin(obj);
6361 fail_locked:
6362         mutex_unlock(&dev->struct_mutex);
6363 fail:
6364         drm_gem_object_unreference_unlocked(&obj->base);
6365         return ret;
6366 }
6367
6368 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6369 {
6370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371
6372         intel_crtc->cursor_x = x;
6373         intel_crtc->cursor_y = y;
6374
6375         intel_crtc_update_cursor(crtc, true);
6376
6377         return 0;
6378 }
6379
6380 /** Sets the color ramps on behalf of RandR */
6381 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6382                                  u16 blue, int regno)
6383 {
6384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385
6386         intel_crtc->lut_r[regno] = red >> 8;
6387         intel_crtc->lut_g[regno] = green >> 8;
6388         intel_crtc->lut_b[regno] = blue >> 8;
6389 }
6390
6391 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6392                              u16 *blue, int regno)
6393 {
6394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395
6396         *red = intel_crtc->lut_r[regno] << 8;
6397         *green = intel_crtc->lut_g[regno] << 8;
6398         *blue = intel_crtc->lut_b[regno] << 8;
6399 }
6400
6401 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6402                                  u16 *blue, uint32_t start, uint32_t size)
6403 {
6404         int end = (start + size > 256) ? 256 : start + size, i;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406
6407         for (i = start; i < end; i++) {
6408                 intel_crtc->lut_r[i] = red[i] >> 8;
6409                 intel_crtc->lut_g[i] = green[i] >> 8;
6410                 intel_crtc->lut_b[i] = blue[i] >> 8;
6411         }
6412
6413         intel_crtc_load_lut(crtc);
6414 }
6415
6416 /**
6417  * Get a pipe with a simple mode set on it for doing load-based monitor
6418  * detection.
6419  *
6420  * It will be up to the load-detect code to adjust the pipe as appropriate for
6421  * its requirements.  The pipe will be connected to no other encoders.
6422  *
6423  * Currently this code will only succeed if there is a pipe with no encoders
6424  * configured for it.  In the future, it could choose to temporarily disable
6425  * some outputs to free up a pipe for its use.
6426  *
6427  * \return crtc, or NULL if no pipes are available.
6428  */
6429
6430 /* VESA 640x480x72Hz mode to set on the pipe */
6431 static struct drm_display_mode load_detect_mode = {
6432         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6433                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6434 };
6435
6436 static struct drm_framebuffer *
6437 intel_framebuffer_create(struct drm_device *dev,
6438                          struct drm_mode_fb_cmd2 *mode_cmd,
6439                          struct drm_i915_gem_object *obj)
6440 {
6441         struct intel_framebuffer *intel_fb;
6442         int ret;
6443
6444         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6445         if (!intel_fb) {
6446                 drm_gem_object_unreference_unlocked(&obj->base);
6447                 return ERR_PTR(-ENOMEM);
6448         }
6449
6450         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6451         if (ret) {
6452                 drm_gem_object_unreference_unlocked(&obj->base);
6453                 kfree(intel_fb);
6454                 return ERR_PTR(ret);
6455         }
6456
6457         return &intel_fb->base;
6458 }
6459
6460 static u32
6461 intel_framebuffer_pitch_for_width(int width, int bpp)
6462 {
6463         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6464         return ALIGN(pitch, 64);
6465 }
6466
6467 static u32
6468 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6469 {
6470         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6471         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6472 }
6473
6474 static struct drm_framebuffer *
6475 intel_framebuffer_create_for_mode(struct drm_device *dev,
6476                                   struct drm_display_mode *mode,
6477                                   int depth, int bpp)
6478 {
6479         struct drm_i915_gem_object *obj;
6480         struct drm_mode_fb_cmd2 mode_cmd;
6481
6482         obj = i915_gem_alloc_object(dev,
6483                                     intel_framebuffer_size_for_mode(mode, bpp));
6484         if (obj == NULL)
6485                 return ERR_PTR(-ENOMEM);
6486
6487         mode_cmd.width = mode->hdisplay;
6488         mode_cmd.height = mode->vdisplay;
6489         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6490                                                                 bpp);
6491         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6492
6493         return intel_framebuffer_create(dev, &mode_cmd, obj);
6494 }
6495
6496 static struct drm_framebuffer *
6497 mode_fits_in_fbdev(struct drm_device *dev,
6498                    struct drm_display_mode *mode)
6499 {
6500         struct drm_i915_private *dev_priv = dev->dev_private;
6501         struct drm_i915_gem_object *obj;
6502         struct drm_framebuffer *fb;
6503
6504         if (dev_priv->fbdev == NULL)
6505                 return NULL;
6506
6507         obj = dev_priv->fbdev->ifb.obj;
6508         if (obj == NULL)
6509                 return NULL;
6510
6511         fb = &dev_priv->fbdev->ifb.base;
6512         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6513                                                                fb->bits_per_pixel))
6514                 return NULL;
6515
6516         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6517                 return NULL;
6518
6519         return fb;
6520 }
6521
6522 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6523                                 struct drm_display_mode *mode,
6524                                 struct intel_load_detect_pipe *old)
6525 {
6526         struct intel_crtc *intel_crtc;
6527         struct intel_encoder *intel_encoder =
6528                 intel_attached_encoder(connector);
6529         struct drm_crtc *possible_crtc;
6530         struct drm_encoder *encoder = &intel_encoder->base;
6531         struct drm_crtc *crtc = NULL;
6532         struct drm_device *dev = encoder->dev;
6533         struct drm_framebuffer *fb;
6534         int i = -1;
6535
6536         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6537                       connector->base.id, drm_get_connector_name(connector),
6538                       encoder->base.id, drm_get_encoder_name(encoder));
6539
6540         /*
6541          * Algorithm gets a little messy:
6542          *
6543          *   - if the connector already has an assigned crtc, use it (but make
6544          *     sure it's on first)
6545          *
6546          *   - try to find the first unused crtc that can drive this connector,
6547          *     and use that if we find one
6548          */
6549
6550         /* See if we already have a CRTC for this connector */
6551         if (encoder->crtc) {
6552                 crtc = encoder->crtc;
6553
6554                 old->dpms_mode = connector->dpms;
6555                 old->load_detect_temp = false;
6556
6557                 /* Make sure the crtc and connector are running */
6558                 if (connector->dpms != DRM_MODE_DPMS_ON)
6559                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6560
6561                 return true;
6562         }
6563
6564         /* Find an unused one (if possible) */
6565         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6566                 i++;
6567                 if (!(encoder->possible_crtcs & (1 << i)))
6568                         continue;
6569                 if (!possible_crtc->enabled) {
6570                         crtc = possible_crtc;
6571                         break;
6572                 }
6573         }
6574
6575         /*
6576          * If we didn't find an unused CRTC, don't use any.
6577          */
6578         if (!crtc) {
6579                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6580                 return false;
6581         }
6582
6583         intel_encoder->new_crtc = to_intel_crtc(crtc);
6584         to_intel_connector(connector)->new_encoder = intel_encoder;
6585
6586         intel_crtc = to_intel_crtc(crtc);
6587         old->dpms_mode = connector->dpms;
6588         old->load_detect_temp = true;
6589         old->release_fb = NULL;
6590
6591         if (!mode)
6592                 mode = &load_detect_mode;
6593
6594         /* We need a framebuffer large enough to accommodate all accesses
6595          * that the plane may generate whilst we perform load detection.
6596          * We can not rely on the fbcon either being present (we get called
6597          * during its initialisation to detect all boot displays, or it may
6598          * not even exist) or that it is large enough to satisfy the
6599          * requested mode.
6600          */
6601         fb = mode_fits_in_fbdev(dev, mode);
6602         if (fb == NULL) {
6603                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6604                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6605                 old->release_fb = fb;
6606         } else
6607                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6608         if (IS_ERR(fb)) {
6609                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6610                 goto fail;
6611         }
6612
6613         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6614                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6615                 if (old->release_fb)
6616                         old->release_fb->funcs->destroy(old->release_fb);
6617                 goto fail;
6618         }
6619
6620         /* let the connector get through one full cycle before testing */
6621         intel_wait_for_vblank(dev, intel_crtc->pipe);
6622
6623         return true;
6624 fail:
6625         connector->encoder = NULL;
6626         encoder->crtc = NULL;
6627         return false;
6628 }
6629
6630 void intel_release_load_detect_pipe(struct drm_connector *connector,
6631                                     struct intel_load_detect_pipe *old)
6632 {
6633         struct intel_encoder *intel_encoder =
6634                 intel_attached_encoder(connector);
6635         struct drm_encoder *encoder = &intel_encoder->base;
6636
6637         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6638                       connector->base.id, drm_get_connector_name(connector),
6639                       encoder->base.id, drm_get_encoder_name(encoder));
6640
6641         if (old->load_detect_temp) {
6642                 struct drm_crtc *crtc = encoder->crtc;
6643
6644                 to_intel_connector(connector)->new_encoder = NULL;
6645                 intel_encoder->new_crtc = NULL;
6646                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6647
6648                 if (old->release_fb)
6649                         old->release_fb->funcs->destroy(old->release_fb);
6650
6651                 return;
6652         }
6653
6654         /* Switch crtc and encoder back off if necessary */
6655         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6656                 connector->funcs->dpms(connector, old->dpms_mode);
6657 }
6658
6659 /* Returns the clock of the currently programmed mode of the given pipe. */
6660 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6661 {
6662         struct drm_i915_private *dev_priv = dev->dev_private;
6663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664         int pipe = intel_crtc->pipe;
6665         u32 dpll = I915_READ(DPLL(pipe));
6666         u32 fp;
6667         intel_clock_t clock;
6668
6669         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6670                 fp = I915_READ(FP0(pipe));
6671         else
6672                 fp = I915_READ(FP1(pipe));
6673
6674         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6675         if (IS_PINEVIEW(dev)) {
6676                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6677                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6678         } else {
6679                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6680                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6681         }
6682
6683         if (!IS_GEN2(dev)) {
6684                 if (IS_PINEVIEW(dev))
6685                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6686                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6687                 else
6688                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6689                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6690
6691                 switch (dpll & DPLL_MODE_MASK) {
6692                 case DPLLB_MODE_DAC_SERIAL:
6693                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6694                                 5 : 10;
6695                         break;
6696                 case DPLLB_MODE_LVDS:
6697                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6698                                 7 : 14;
6699                         break;
6700                 default:
6701                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6702                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6703                         return 0;
6704                 }
6705
6706                 /* XXX: Handle the 100Mhz refclk */
6707                 intel_clock(dev, 96000, &clock);
6708         } else {
6709                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6710
6711                 if (is_lvds) {
6712                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6713                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6714                         clock.p2 = 14;
6715
6716                         if ((dpll & PLL_REF_INPUT_MASK) ==
6717                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6718                                 /* XXX: might not be 66MHz */
6719                                 intel_clock(dev, 66000, &clock);
6720                         } else
6721                                 intel_clock(dev, 48000, &clock);
6722                 } else {
6723                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6724                                 clock.p1 = 2;
6725                         else {
6726                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6727                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6728                         }
6729                         if (dpll & PLL_P2_DIVIDE_BY_4)
6730                                 clock.p2 = 4;
6731                         else
6732                                 clock.p2 = 2;
6733
6734                         intel_clock(dev, 48000, &clock);
6735                 }
6736         }
6737
6738         /* XXX: It would be nice to validate the clocks, but we can't reuse
6739          * i830PllIsValid() because it relies on the xf86_config connector
6740          * configuration being accurate, which it isn't necessarily.
6741          */
6742
6743         return clock.dot;
6744 }
6745
6746 /** Returns the currently programmed mode of the given pipe. */
6747 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6748                                              struct drm_crtc *crtc)
6749 {
6750         struct drm_i915_private *dev_priv = dev->dev_private;
6751         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6752         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6753         struct drm_display_mode *mode;
6754         int htot = I915_READ(HTOTAL(cpu_transcoder));
6755         int hsync = I915_READ(HSYNC(cpu_transcoder));
6756         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6757         int vsync = I915_READ(VSYNC(cpu_transcoder));
6758
6759         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6760         if (!mode)
6761                 return NULL;
6762
6763         mode->clock = intel_crtc_clock_get(dev, crtc);
6764         mode->hdisplay = (htot & 0xffff) + 1;
6765         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6766         mode->hsync_start = (hsync & 0xffff) + 1;
6767         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6768         mode->vdisplay = (vtot & 0xffff) + 1;
6769         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6770         mode->vsync_start = (vsync & 0xffff) + 1;
6771         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6772
6773         drm_mode_set_name(mode);
6774
6775         return mode;
6776 }
6777
6778 static void intel_increase_pllclock(struct drm_crtc *crtc)
6779 {
6780         struct drm_device *dev = crtc->dev;
6781         drm_i915_private_t *dev_priv = dev->dev_private;
6782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6783         int pipe = intel_crtc->pipe;
6784         int dpll_reg = DPLL(pipe);
6785         int dpll;
6786
6787         if (HAS_PCH_SPLIT(dev))
6788                 return;
6789
6790         if (!dev_priv->lvds_downclock_avail)
6791                 return;
6792
6793         dpll = I915_READ(dpll_reg);
6794         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6795                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6796
6797                 assert_panel_unlocked(dev_priv, pipe);
6798
6799                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6800                 I915_WRITE(dpll_reg, dpll);
6801                 intel_wait_for_vblank(dev, pipe);
6802
6803                 dpll = I915_READ(dpll_reg);
6804                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6805                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6806         }
6807 }
6808
6809 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6810 {
6811         struct drm_device *dev = crtc->dev;
6812         drm_i915_private_t *dev_priv = dev->dev_private;
6813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814
6815         if (HAS_PCH_SPLIT(dev))
6816                 return;
6817
6818         if (!dev_priv->lvds_downclock_avail)
6819                 return;
6820
6821         /*
6822          * Since this is called by a timer, we should never get here in
6823          * the manual case.
6824          */
6825         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6826                 int pipe = intel_crtc->pipe;
6827                 int dpll_reg = DPLL(pipe);
6828                 int dpll;
6829
6830                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6831
6832                 assert_panel_unlocked(dev_priv, pipe);
6833
6834                 dpll = I915_READ(dpll_reg);
6835                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6836                 I915_WRITE(dpll_reg, dpll);
6837                 intel_wait_for_vblank(dev, pipe);
6838                 dpll = I915_READ(dpll_reg);
6839                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6840                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6841         }
6842
6843 }
6844
6845 void intel_mark_busy(struct drm_device *dev)
6846 {
6847         i915_update_gfx_val(dev->dev_private);
6848 }
6849
6850 void intel_mark_idle(struct drm_device *dev)
6851 {
6852 }
6853
6854 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6855 {
6856         struct drm_device *dev = obj->base.dev;
6857         struct drm_crtc *crtc;
6858
6859         if (!i915_powersave)
6860                 return;
6861
6862         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6863                 if (!crtc->fb)
6864                         continue;
6865
6866                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6867                         intel_increase_pllclock(crtc);
6868         }
6869 }
6870
6871 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6872 {
6873         struct drm_device *dev = obj->base.dev;
6874         struct drm_crtc *crtc;
6875
6876         if (!i915_powersave)
6877                 return;
6878
6879         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6880                 if (!crtc->fb)
6881                         continue;
6882
6883                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6884                         intel_decrease_pllclock(crtc);
6885         }
6886 }
6887
6888 static void intel_crtc_destroy(struct drm_crtc *crtc)
6889 {
6890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6891         struct drm_device *dev = crtc->dev;
6892         struct intel_unpin_work *work;
6893         unsigned long flags;
6894
6895         spin_lock_irqsave(&dev->event_lock, flags);
6896         work = intel_crtc->unpin_work;
6897         intel_crtc->unpin_work = NULL;
6898         spin_unlock_irqrestore(&dev->event_lock, flags);
6899
6900         if (work) {
6901                 cancel_work_sync(&work->work);
6902                 kfree(work);
6903         }
6904
6905         drm_crtc_cleanup(crtc);
6906
6907         kfree(intel_crtc);
6908 }
6909
6910 static void intel_unpin_work_fn(struct work_struct *__work)
6911 {
6912         struct intel_unpin_work *work =
6913                 container_of(__work, struct intel_unpin_work, work);
6914
6915         mutex_lock(&work->dev->struct_mutex);
6916         intel_unpin_fb_obj(work->old_fb_obj);
6917         drm_gem_object_unreference(&work->pending_flip_obj->base);
6918         drm_gem_object_unreference(&work->old_fb_obj->base);
6919
6920         intel_update_fbc(work->dev);
6921         mutex_unlock(&work->dev->struct_mutex);
6922         kfree(work);
6923 }
6924
6925 static void do_intel_finish_page_flip(struct drm_device *dev,
6926                                       struct drm_crtc *crtc)
6927 {
6928         drm_i915_private_t *dev_priv = dev->dev_private;
6929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6930         struct intel_unpin_work *work;
6931         struct drm_i915_gem_object *obj;
6932         struct drm_pending_vblank_event *e;
6933         struct timeval tvbl;
6934         unsigned long flags;
6935
6936         /* Ignore early vblank irqs */
6937         if (intel_crtc == NULL)
6938                 return;
6939
6940         spin_lock_irqsave(&dev->event_lock, flags);
6941         work = intel_crtc->unpin_work;
6942         if (work == NULL || !work->pending) {
6943                 spin_unlock_irqrestore(&dev->event_lock, flags);
6944                 return;
6945         }
6946
6947         intel_crtc->unpin_work = NULL;
6948
6949         if (work->event) {
6950                 e = work->event;
6951                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6952
6953                 e->event.tv_sec = tvbl.tv_sec;
6954                 e->event.tv_usec = tvbl.tv_usec;
6955
6956                 list_add_tail(&e->base.link,
6957                               &e->base.file_priv->event_list);
6958                 wake_up_interruptible(&e->base.file_priv->event_wait);
6959         }
6960
6961         drm_vblank_put(dev, intel_crtc->pipe);
6962
6963         spin_unlock_irqrestore(&dev->event_lock, flags);
6964
6965         obj = work->old_fb_obj;
6966
6967         atomic_clear_mask(1 << intel_crtc->plane,
6968                           &obj->pending_flip.counter);
6969
6970         wake_up(&dev_priv->pending_flip_queue);
6971         schedule_work(&work->work);
6972
6973         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6974 }
6975
6976 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6977 {
6978         drm_i915_private_t *dev_priv = dev->dev_private;
6979         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6980
6981         do_intel_finish_page_flip(dev, crtc);
6982 }
6983
6984 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6985 {
6986         drm_i915_private_t *dev_priv = dev->dev_private;
6987         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6988
6989         do_intel_finish_page_flip(dev, crtc);
6990 }
6991
6992 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6993 {
6994         drm_i915_private_t *dev_priv = dev->dev_private;
6995         struct intel_crtc *intel_crtc =
6996                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6997         unsigned long flags;
6998
6999         spin_lock_irqsave(&dev->event_lock, flags);
7000         if (intel_crtc->unpin_work) {
7001                 if ((++intel_crtc->unpin_work->pending) > 1)
7002                         DRM_ERROR("Prepared flip multiple times\n");
7003         } else {
7004                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7005         }
7006         spin_unlock_irqrestore(&dev->event_lock, flags);
7007 }
7008
7009 static int intel_gen2_queue_flip(struct drm_device *dev,
7010                                  struct drm_crtc *crtc,
7011                                  struct drm_framebuffer *fb,
7012                                  struct drm_i915_gem_object *obj)
7013 {
7014         struct drm_i915_private *dev_priv = dev->dev_private;
7015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7016         u32 flip_mask;
7017         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7018         int ret;
7019
7020         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7021         if (ret)
7022                 goto err;
7023
7024         ret = intel_ring_begin(ring, 6);
7025         if (ret)
7026                 goto err_unpin;
7027
7028         /* Can't queue multiple flips, so wait for the previous
7029          * one to finish before executing the next.
7030          */
7031         if (intel_crtc->plane)
7032                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7033         else
7034                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7035         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7036         intel_ring_emit(ring, MI_NOOP);
7037         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7038                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7039         intel_ring_emit(ring, fb->pitches[0]);
7040         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7041         intel_ring_emit(ring, 0); /* aux display base address, unused */
7042         intel_ring_advance(ring);
7043         return 0;
7044
7045 err_unpin:
7046         intel_unpin_fb_obj(obj);
7047 err:
7048         return ret;
7049 }
7050
7051 static int intel_gen3_queue_flip(struct drm_device *dev,
7052                                  struct drm_crtc *crtc,
7053                                  struct drm_framebuffer *fb,
7054                                  struct drm_i915_gem_object *obj)
7055 {
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058         u32 flip_mask;
7059         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7060         int ret;
7061
7062         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7063         if (ret)
7064                 goto err;
7065
7066         ret = intel_ring_begin(ring, 6);
7067         if (ret)
7068                 goto err_unpin;
7069
7070         if (intel_crtc->plane)
7071                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7072         else
7073                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7074         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7075         intel_ring_emit(ring, MI_NOOP);
7076         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7077                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7078         intel_ring_emit(ring, fb->pitches[0]);
7079         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7080         intel_ring_emit(ring, MI_NOOP);
7081
7082         intel_ring_advance(ring);
7083         return 0;
7084
7085 err_unpin:
7086         intel_unpin_fb_obj(obj);
7087 err:
7088         return ret;
7089 }
7090
7091 static int intel_gen4_queue_flip(struct drm_device *dev,
7092                                  struct drm_crtc *crtc,
7093                                  struct drm_framebuffer *fb,
7094                                  struct drm_i915_gem_object *obj)
7095 {
7096         struct drm_i915_private *dev_priv = dev->dev_private;
7097         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098         uint32_t pf, pipesrc;
7099         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7100         int ret;
7101
7102         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7103         if (ret)
7104                 goto err;
7105
7106         ret = intel_ring_begin(ring, 4);
7107         if (ret)
7108                 goto err_unpin;
7109
7110         /* i965+ uses the linear or tiled offsets from the
7111          * Display Registers (which do not change across a page-flip)
7112          * so we need only reprogram the base address.
7113          */
7114         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7115                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7116         intel_ring_emit(ring, fb->pitches[0]);
7117         intel_ring_emit(ring,
7118                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7119                         obj->tiling_mode);
7120
7121         /* XXX Enabling the panel-fitter across page-flip is so far
7122          * untested on non-native modes, so ignore it for now.
7123          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7124          */
7125         pf = 0;
7126         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7127         intel_ring_emit(ring, pf | pipesrc);
7128         intel_ring_advance(ring);
7129         return 0;
7130
7131 err_unpin:
7132         intel_unpin_fb_obj(obj);
7133 err:
7134         return ret;
7135 }
7136
7137 static int intel_gen6_queue_flip(struct drm_device *dev,
7138                                  struct drm_crtc *crtc,
7139                                  struct drm_framebuffer *fb,
7140                                  struct drm_i915_gem_object *obj)
7141 {
7142         struct drm_i915_private *dev_priv = dev->dev_private;
7143         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7144         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7145         uint32_t pf, pipesrc;
7146         int ret;
7147
7148         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7149         if (ret)
7150                 goto err;
7151
7152         ret = intel_ring_begin(ring, 4);
7153         if (ret)
7154                 goto err_unpin;
7155
7156         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7157                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7158         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7159         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7160
7161         /* Contrary to the suggestions in the documentation,
7162          * "Enable Panel Fitter" does not seem to be required when page
7163          * flipping with a non-native mode, and worse causes a normal
7164          * modeset to fail.
7165          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7166          */
7167         pf = 0;
7168         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7169         intel_ring_emit(ring, pf | pipesrc);
7170         intel_ring_advance(ring);
7171         return 0;
7172
7173 err_unpin:
7174         intel_unpin_fb_obj(obj);
7175 err:
7176         return ret;
7177 }
7178
7179 /*
7180  * On gen7 we currently use the blit ring because (in early silicon at least)
7181  * the render ring doesn't give us interrpts for page flip completion, which
7182  * means clients will hang after the first flip is queued.  Fortunately the
7183  * blit ring generates interrupts properly, so use it instead.
7184  */
7185 static int intel_gen7_queue_flip(struct drm_device *dev,
7186                                  struct drm_crtc *crtc,
7187                                  struct drm_framebuffer *fb,
7188                                  struct drm_i915_gem_object *obj)
7189 {
7190         struct drm_i915_private *dev_priv = dev->dev_private;
7191         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7192         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7193         uint32_t plane_bit = 0;
7194         int ret;
7195
7196         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7197         if (ret)
7198                 goto err;
7199
7200         switch(intel_crtc->plane) {
7201         case PLANE_A:
7202                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7203                 break;
7204         case PLANE_B:
7205                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7206                 break;
7207         case PLANE_C:
7208                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7209                 break;
7210         default:
7211                 WARN_ONCE(1, "unknown plane in flip command\n");
7212                 ret = -ENODEV;
7213                 goto err_unpin;
7214         }
7215
7216         ret = intel_ring_begin(ring, 4);
7217         if (ret)
7218                 goto err_unpin;
7219
7220         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7221         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7222         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7223         intel_ring_emit(ring, (MI_NOOP));
7224         intel_ring_advance(ring);
7225         return 0;
7226
7227 err_unpin:
7228         intel_unpin_fb_obj(obj);
7229 err:
7230         return ret;
7231 }
7232
7233 static int intel_default_queue_flip(struct drm_device *dev,
7234                                     struct drm_crtc *crtc,
7235                                     struct drm_framebuffer *fb,
7236                                     struct drm_i915_gem_object *obj)
7237 {
7238         return -ENODEV;
7239 }
7240
7241 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7242                                 struct drm_framebuffer *fb,
7243                                 struct drm_pending_vblank_event *event)
7244 {
7245         struct drm_device *dev = crtc->dev;
7246         struct drm_i915_private *dev_priv = dev->dev_private;
7247         struct intel_framebuffer *intel_fb;
7248         struct drm_i915_gem_object *obj;
7249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7250         struct intel_unpin_work *work;
7251         unsigned long flags;
7252         int ret;
7253
7254         /* Can't change pixel format via MI display flips. */
7255         if (fb->pixel_format != crtc->fb->pixel_format)
7256                 return -EINVAL;
7257
7258         /*
7259          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7260          * Note that pitch changes could also affect these register.
7261          */
7262         if (INTEL_INFO(dev)->gen > 3 &&
7263             (fb->offsets[0] != crtc->fb->offsets[0] ||
7264              fb->pitches[0] != crtc->fb->pitches[0]))
7265                 return -EINVAL;
7266
7267         work = kzalloc(sizeof *work, GFP_KERNEL);
7268         if (work == NULL)
7269                 return -ENOMEM;
7270
7271         work->event = event;
7272         work->dev = crtc->dev;
7273         intel_fb = to_intel_framebuffer(crtc->fb);
7274         work->old_fb_obj = intel_fb->obj;
7275         INIT_WORK(&work->work, intel_unpin_work_fn);
7276
7277         ret = drm_vblank_get(dev, intel_crtc->pipe);
7278         if (ret)
7279                 goto free_work;
7280
7281         /* We borrow the event spin lock for protecting unpin_work */
7282         spin_lock_irqsave(&dev->event_lock, flags);
7283         if (intel_crtc->unpin_work) {
7284                 spin_unlock_irqrestore(&dev->event_lock, flags);
7285                 kfree(work);
7286                 drm_vblank_put(dev, intel_crtc->pipe);
7287
7288                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7289                 return -EBUSY;
7290         }
7291         intel_crtc->unpin_work = work;
7292         spin_unlock_irqrestore(&dev->event_lock, flags);
7293
7294         intel_fb = to_intel_framebuffer(fb);
7295         obj = intel_fb->obj;
7296
7297         ret = i915_mutex_lock_interruptible(dev);
7298         if (ret)
7299                 goto cleanup;
7300
7301         /* Reference the objects for the scheduled work. */
7302         drm_gem_object_reference(&work->old_fb_obj->base);
7303         drm_gem_object_reference(&obj->base);
7304
7305         crtc->fb = fb;
7306
7307         work->pending_flip_obj = obj;
7308
7309         work->enable_stall_check = true;
7310
7311         /* Block clients from rendering to the new back buffer until
7312          * the flip occurs and the object is no longer visible.
7313          */
7314         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7315
7316         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7317         if (ret)
7318                 goto cleanup_pending;
7319
7320         intel_disable_fbc(dev);
7321         intel_mark_fb_busy(obj);
7322         mutex_unlock(&dev->struct_mutex);
7323
7324         trace_i915_flip_request(intel_crtc->plane, obj);
7325
7326         return 0;
7327
7328 cleanup_pending:
7329         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7330         drm_gem_object_unreference(&work->old_fb_obj->base);
7331         drm_gem_object_unreference(&obj->base);
7332         mutex_unlock(&dev->struct_mutex);
7333
7334 cleanup:
7335         spin_lock_irqsave(&dev->event_lock, flags);
7336         intel_crtc->unpin_work = NULL;
7337         spin_unlock_irqrestore(&dev->event_lock, flags);
7338
7339         drm_vblank_put(dev, intel_crtc->pipe);
7340 free_work:
7341         kfree(work);
7342
7343         return ret;
7344 }
7345
7346 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7347         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7348         .load_lut = intel_crtc_load_lut,
7349         .disable = intel_crtc_noop,
7350 };
7351
7352 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7353 {
7354         struct intel_encoder *other_encoder;
7355         struct drm_crtc *crtc = &encoder->new_crtc->base;
7356
7357         if (WARN_ON(!crtc))
7358                 return false;
7359
7360         list_for_each_entry(other_encoder,
7361                             &crtc->dev->mode_config.encoder_list,
7362                             base.head) {
7363
7364                 if (&other_encoder->new_crtc->base != crtc ||
7365                     encoder == other_encoder)
7366                         continue;
7367                 else
7368                         return true;
7369         }
7370
7371         return false;
7372 }
7373
7374 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7375                                   struct drm_crtc *crtc)
7376 {
7377         struct drm_device *dev;
7378         struct drm_crtc *tmp;
7379         int crtc_mask = 1;
7380
7381         WARN(!crtc, "checking null crtc?\n");
7382
7383         dev = crtc->dev;
7384
7385         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7386                 if (tmp == crtc)
7387                         break;
7388                 crtc_mask <<= 1;
7389         }
7390
7391         if (encoder->possible_crtcs & crtc_mask)
7392                 return true;
7393         return false;
7394 }
7395
7396 /**
7397  * intel_modeset_update_staged_output_state
7398  *
7399  * Updates the staged output configuration state, e.g. after we've read out the
7400  * current hw state.
7401  */
7402 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7403 {
7404         struct intel_encoder *encoder;
7405         struct intel_connector *connector;
7406
7407         list_for_each_entry(connector, &dev->mode_config.connector_list,
7408                             base.head) {
7409                 connector->new_encoder =
7410                         to_intel_encoder(connector->base.encoder);
7411         }
7412
7413         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7414                             base.head) {
7415                 encoder->new_crtc =
7416                         to_intel_crtc(encoder->base.crtc);
7417         }
7418 }
7419
7420 /**
7421  * intel_modeset_commit_output_state
7422  *
7423  * This function copies the stage display pipe configuration to the real one.
7424  */
7425 static void intel_modeset_commit_output_state(struct drm_device *dev)
7426 {
7427         struct intel_encoder *encoder;
7428         struct intel_connector *connector;
7429
7430         list_for_each_entry(connector, &dev->mode_config.connector_list,
7431                             base.head) {
7432                 connector->base.encoder = &connector->new_encoder->base;
7433         }
7434
7435         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7436                             base.head) {
7437                 encoder->base.crtc = &encoder->new_crtc->base;
7438         }
7439 }
7440
7441 static struct drm_display_mode *
7442 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7443                             struct drm_display_mode *mode)
7444 {
7445         struct drm_device *dev = crtc->dev;
7446         struct drm_display_mode *adjusted_mode;
7447         struct drm_encoder_helper_funcs *encoder_funcs;
7448         struct intel_encoder *encoder;
7449
7450         adjusted_mode = drm_mode_duplicate(dev, mode);
7451         if (!adjusted_mode)
7452                 return ERR_PTR(-ENOMEM);
7453
7454         /* Pass our mode to the connectors and the CRTC to give them a chance to
7455          * adjust it according to limitations or connector properties, and also
7456          * a chance to reject the mode entirely.
7457          */
7458         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7459                             base.head) {
7460
7461                 if (&encoder->new_crtc->base != crtc)
7462                         continue;
7463                 encoder_funcs = encoder->base.helper_private;
7464                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7465                                                 adjusted_mode))) {
7466                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7467                         goto fail;
7468                 }
7469         }
7470
7471         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7472                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7473                 goto fail;
7474         }
7475         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7476
7477         return adjusted_mode;
7478 fail:
7479         drm_mode_destroy(dev, adjusted_mode);
7480         return ERR_PTR(-EINVAL);
7481 }
7482
7483 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7484  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7485 static void
7486 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7487                              unsigned *prepare_pipes, unsigned *disable_pipes)
7488 {
7489         struct intel_crtc *intel_crtc;
7490         struct drm_device *dev = crtc->dev;
7491         struct intel_encoder *encoder;
7492         struct intel_connector *connector;
7493         struct drm_crtc *tmp_crtc;
7494
7495         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7496
7497         /* Check which crtcs have changed outputs connected to them, these need
7498          * to be part of the prepare_pipes mask. We don't (yet) support global
7499          * modeset across multiple crtcs, so modeset_pipes will only have one
7500          * bit set at most. */
7501         list_for_each_entry(connector, &dev->mode_config.connector_list,
7502                             base.head) {
7503                 if (connector->base.encoder == &connector->new_encoder->base)
7504                         continue;
7505
7506                 if (connector->base.encoder) {
7507                         tmp_crtc = connector->base.encoder->crtc;
7508
7509                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7510                 }
7511
7512                 if (connector->new_encoder)
7513                         *prepare_pipes |=
7514                                 1 << connector->new_encoder->new_crtc->pipe;
7515         }
7516
7517         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7518                             base.head) {
7519                 if (encoder->base.crtc == &encoder->new_crtc->base)
7520                         continue;
7521
7522                 if (encoder->base.crtc) {
7523                         tmp_crtc = encoder->base.crtc;
7524
7525                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7526                 }
7527
7528                 if (encoder->new_crtc)
7529                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7530         }
7531
7532         /* Check for any pipes that will be fully disabled ... */
7533         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7534                             base.head) {
7535                 bool used = false;
7536
7537                 /* Don't try to disable disabled crtcs. */
7538                 if (!intel_crtc->base.enabled)
7539                         continue;
7540
7541                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7542                                     base.head) {
7543                         if (encoder->new_crtc == intel_crtc)
7544                                 used = true;
7545                 }
7546
7547                 if (!used)
7548                         *disable_pipes |= 1 << intel_crtc->pipe;
7549         }
7550
7551
7552         /* set_mode is also used to update properties on life display pipes. */
7553         intel_crtc = to_intel_crtc(crtc);
7554         if (crtc->enabled)
7555                 *prepare_pipes |= 1 << intel_crtc->pipe;
7556
7557         /* We only support modeset on one single crtc, hence we need to do that
7558          * only for the passed in crtc iff we change anything else than just
7559          * disable crtcs.
7560          *
7561          * This is actually not true, to be fully compatible with the old crtc
7562          * helper we automatically disable _any_ output (i.e. doesn't need to be
7563          * connected to the crtc we're modesetting on) if it's disconnected.
7564          * Which is a rather nutty api (since changed the output configuration
7565          * without userspace's explicit request can lead to confusion), but
7566          * alas. Hence we currently need to modeset on all pipes we prepare. */
7567         if (*prepare_pipes)
7568                 *modeset_pipes = *prepare_pipes;
7569
7570         /* ... and mask these out. */
7571         *modeset_pipes &= ~(*disable_pipes);
7572         *prepare_pipes &= ~(*disable_pipes);
7573 }
7574
7575 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7576 {
7577         struct drm_encoder *encoder;
7578         struct drm_device *dev = crtc->dev;
7579
7580         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7581                 if (encoder->crtc == crtc)
7582                         return true;
7583
7584         return false;
7585 }
7586
7587 static void
7588 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7589 {
7590         struct intel_encoder *intel_encoder;
7591         struct intel_crtc *intel_crtc;
7592         struct drm_connector *connector;
7593
7594         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7595                             base.head) {
7596                 if (!intel_encoder->base.crtc)
7597                         continue;
7598
7599                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7600
7601                 if (prepare_pipes & (1 << intel_crtc->pipe))
7602                         intel_encoder->connectors_active = false;
7603         }
7604
7605         intel_modeset_commit_output_state(dev);
7606
7607         /* Update computed state. */
7608         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7609                             base.head) {
7610                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7611         }
7612
7613         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7614                 if (!connector->encoder || !connector->encoder->crtc)
7615                         continue;
7616
7617                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7618
7619                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7620                         struct drm_property *dpms_property =
7621                                 dev->mode_config.dpms_property;
7622
7623                         connector->dpms = DRM_MODE_DPMS_ON;
7624                         drm_connector_property_set_value(connector,
7625                                                          dpms_property,
7626                                                          DRM_MODE_DPMS_ON);
7627
7628                         intel_encoder = to_intel_encoder(connector->encoder);
7629                         intel_encoder->connectors_active = true;
7630                 }
7631         }
7632
7633 }
7634
7635 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7636         list_for_each_entry((intel_crtc), \
7637                             &(dev)->mode_config.crtc_list, \
7638                             base.head) \
7639                 if (mask & (1 <<(intel_crtc)->pipe)) \
7640
7641 void
7642 intel_modeset_check_state(struct drm_device *dev)
7643 {
7644         struct intel_crtc *crtc;
7645         struct intel_encoder *encoder;
7646         struct intel_connector *connector;
7647
7648         list_for_each_entry(connector, &dev->mode_config.connector_list,
7649                             base.head) {
7650                 /* This also checks the encoder/connector hw state with the
7651                  * ->get_hw_state callbacks. */
7652                 intel_connector_check_state(connector);
7653
7654                 WARN(&connector->new_encoder->base != connector->base.encoder,
7655                      "connector's staged encoder doesn't match current encoder\n");
7656         }
7657
7658         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7659                             base.head) {
7660                 bool enabled = false;
7661                 bool active = false;
7662                 enum pipe pipe, tracked_pipe;
7663
7664                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7665                               encoder->base.base.id,
7666                               drm_get_encoder_name(&encoder->base));
7667
7668                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7669                      "encoder's stage crtc doesn't match current crtc\n");
7670                 WARN(encoder->connectors_active && !encoder->base.crtc,
7671                      "encoder's active_connectors set, but no crtc\n");
7672
7673                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674                                     base.head) {
7675                         if (connector->base.encoder != &encoder->base)
7676                                 continue;
7677                         enabled = true;
7678                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7679                                 active = true;
7680                 }
7681                 WARN(!!encoder->base.crtc != enabled,
7682                      "encoder's enabled state mismatch "
7683                      "(expected %i, found %i)\n",
7684                      !!encoder->base.crtc, enabled);
7685                 WARN(active && !encoder->base.crtc,
7686                      "active encoder with no crtc\n");
7687
7688                 WARN(encoder->connectors_active != active,
7689                      "encoder's computed active state doesn't match tracked active state "
7690                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7691
7692                 active = encoder->get_hw_state(encoder, &pipe);
7693                 WARN(active != encoder->connectors_active,
7694                      "encoder's hw state doesn't match sw tracking "
7695                      "(expected %i, found %i)\n",
7696                      encoder->connectors_active, active);
7697
7698                 if (!encoder->base.crtc)
7699                         continue;
7700
7701                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7702                 WARN(active && pipe != tracked_pipe,
7703                      "active encoder's pipe doesn't match"
7704                      "(expected %i, found %i)\n",
7705                      tracked_pipe, pipe);
7706
7707         }
7708
7709         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7710                             base.head) {
7711                 bool enabled = false;
7712                 bool active = false;
7713
7714                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7715                               crtc->base.base.id);
7716
7717                 WARN(crtc->active && !crtc->base.enabled,
7718                      "active crtc, but not enabled in sw tracking\n");
7719
7720                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7721                                     base.head) {
7722                         if (encoder->base.crtc != &crtc->base)
7723                                 continue;
7724                         enabled = true;
7725                         if (encoder->connectors_active)
7726                                 active = true;
7727                 }
7728                 WARN(active != crtc->active,
7729                      "crtc's computed active state doesn't match tracked active state "
7730                      "(expected %i, found %i)\n", active, crtc->active);
7731                 WARN(enabled != crtc->base.enabled,
7732                      "crtc's computed enabled state doesn't match tracked enabled state "
7733                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7734
7735                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7736         }
7737 }
7738
7739 bool intel_set_mode(struct drm_crtc *crtc,
7740                     struct drm_display_mode *mode,
7741                     int x, int y, struct drm_framebuffer *fb)
7742 {
7743         struct drm_device *dev = crtc->dev;
7744         drm_i915_private_t *dev_priv = dev->dev_private;
7745         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7746         struct intel_crtc *intel_crtc;
7747         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7748         bool ret = true;
7749
7750         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7751                                      &prepare_pipes, &disable_pipes);
7752
7753         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7754                       modeset_pipes, prepare_pipes, disable_pipes);
7755
7756         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7757                 intel_crtc_disable(&intel_crtc->base);
7758
7759         saved_hwmode = crtc->hwmode;
7760         saved_mode = crtc->mode;
7761
7762         /* Hack: Because we don't (yet) support global modeset on multiple
7763          * crtcs, we don't keep track of the new mode for more than one crtc.
7764          * Hence simply check whether any bit is set in modeset_pipes in all the
7765          * pieces of code that are not yet converted to deal with mutliple crtcs
7766          * changing their mode at the same time. */
7767         adjusted_mode = NULL;
7768         if (modeset_pipes) {
7769                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7770                 if (IS_ERR(adjusted_mode)) {
7771                         return false;
7772                 }
7773         }
7774
7775         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7776                 if (intel_crtc->base.enabled)
7777                         dev_priv->display.crtc_disable(&intel_crtc->base);
7778         }
7779
7780         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7781          * to set it here already despite that we pass it down the callchain.
7782          */
7783         if (modeset_pipes)
7784                 crtc->mode = *mode;
7785
7786         /* Only after disabling all output pipelines that will be changed can we
7787          * update the the output configuration. */
7788         intel_modeset_update_state(dev, prepare_pipes);
7789
7790         if (dev_priv->display.modeset_global_resources)
7791                 dev_priv->display.modeset_global_resources(dev);
7792
7793         /* Set up the DPLL and any encoders state that needs to adjust or depend
7794          * on the DPLL.
7795          */
7796         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7797                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7798                                            mode, adjusted_mode,
7799                                            x, y, fb);
7800                 if (!ret)
7801                     goto done;
7802         }
7803
7804         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7805         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7806                 dev_priv->display.crtc_enable(&intel_crtc->base);
7807
7808         if (modeset_pipes) {
7809                 /* Store real post-adjustment hardware mode. */
7810                 crtc->hwmode = *adjusted_mode;
7811
7812                 /* Calculate and store various constants which
7813                  * are later needed by vblank and swap-completion
7814                  * timestamping. They are derived from true hwmode.
7815                  */
7816                 drm_calc_timestamping_constants(crtc);
7817         }
7818
7819         /* FIXME: add subpixel order */
7820 done:
7821         drm_mode_destroy(dev, adjusted_mode);
7822         if (!ret && crtc->enabled) {
7823                 crtc->hwmode = saved_hwmode;
7824                 crtc->mode = saved_mode;
7825         } else {
7826                 intel_modeset_check_state(dev);
7827         }
7828
7829         return ret;
7830 }
7831
7832 #undef for_each_intel_crtc_masked
7833
7834 static void intel_set_config_free(struct intel_set_config *config)
7835 {
7836         if (!config)
7837                 return;
7838
7839         kfree(config->save_connector_encoders);
7840         kfree(config->save_encoder_crtcs);
7841         kfree(config);
7842 }
7843
7844 static int intel_set_config_save_state(struct drm_device *dev,
7845                                        struct intel_set_config *config)
7846 {
7847         struct drm_encoder *encoder;
7848         struct drm_connector *connector;
7849         int count;
7850
7851         config->save_encoder_crtcs =
7852                 kcalloc(dev->mode_config.num_encoder,
7853                         sizeof(struct drm_crtc *), GFP_KERNEL);
7854         if (!config->save_encoder_crtcs)
7855                 return -ENOMEM;
7856
7857         config->save_connector_encoders =
7858                 kcalloc(dev->mode_config.num_connector,
7859                         sizeof(struct drm_encoder *), GFP_KERNEL);
7860         if (!config->save_connector_encoders)
7861                 return -ENOMEM;
7862
7863         /* Copy data. Note that driver private data is not affected.
7864          * Should anything bad happen only the expected state is
7865          * restored, not the drivers personal bookkeeping.
7866          */
7867         count = 0;
7868         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7869                 config->save_encoder_crtcs[count++] = encoder->crtc;
7870         }
7871
7872         count = 0;
7873         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7874                 config->save_connector_encoders[count++] = connector->encoder;
7875         }
7876
7877         return 0;
7878 }
7879
7880 static void intel_set_config_restore_state(struct drm_device *dev,
7881                                            struct intel_set_config *config)
7882 {
7883         struct intel_encoder *encoder;
7884         struct intel_connector *connector;
7885         int count;
7886
7887         count = 0;
7888         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7889                 encoder->new_crtc =
7890                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7891         }
7892
7893         count = 0;
7894         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7895                 connector->new_encoder =
7896                         to_intel_encoder(config->save_connector_encoders[count++]);
7897         }
7898 }
7899
7900 static void
7901 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7902                                       struct intel_set_config *config)
7903 {
7904
7905         /* We should be able to check here if the fb has the same properties
7906          * and then just flip_or_move it */
7907         if (set->crtc->fb != set->fb) {
7908                 /* If we have no fb then treat it as a full mode set */
7909                 if (set->crtc->fb == NULL) {
7910                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7911                         config->mode_changed = true;
7912                 } else if (set->fb == NULL) {
7913                         config->mode_changed = true;
7914                 } else if (set->fb->depth != set->crtc->fb->depth) {
7915                         config->mode_changed = true;
7916                 } else if (set->fb->bits_per_pixel !=
7917                            set->crtc->fb->bits_per_pixel) {
7918                         config->mode_changed = true;
7919                 } else
7920                         config->fb_changed = true;
7921         }
7922
7923         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7924                 config->fb_changed = true;
7925
7926         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7927                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7928                 drm_mode_debug_printmodeline(&set->crtc->mode);
7929                 drm_mode_debug_printmodeline(set->mode);
7930                 config->mode_changed = true;
7931         }
7932 }
7933
7934 static int
7935 intel_modeset_stage_output_state(struct drm_device *dev,
7936                                  struct drm_mode_set *set,
7937                                  struct intel_set_config *config)
7938 {
7939         struct drm_crtc *new_crtc;
7940         struct intel_connector *connector;
7941         struct intel_encoder *encoder;
7942         int count, ro;
7943
7944         /* The upper layers ensure that we either disabl a crtc or have a list
7945          * of connectors. For paranoia, double-check this. */
7946         WARN_ON(!set->fb && (set->num_connectors != 0));
7947         WARN_ON(set->fb && (set->num_connectors == 0));
7948
7949         count = 0;
7950         list_for_each_entry(connector, &dev->mode_config.connector_list,
7951                             base.head) {
7952                 /* Otherwise traverse passed in connector list and get encoders
7953                  * for them. */
7954                 for (ro = 0; ro < set->num_connectors; ro++) {
7955                         if (set->connectors[ro] == &connector->base) {
7956                                 connector->new_encoder = connector->encoder;
7957                                 break;
7958                         }
7959                 }
7960
7961                 /* If we disable the crtc, disable all its connectors. Also, if
7962                  * the connector is on the changing crtc but not on the new
7963                  * connector list, disable it. */
7964                 if ((!set->fb || ro == set->num_connectors) &&
7965                     connector->base.encoder &&
7966                     connector->base.encoder->crtc == set->crtc) {
7967                         connector->new_encoder = NULL;
7968
7969                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7970                                 connector->base.base.id,
7971                                 drm_get_connector_name(&connector->base));
7972                 }
7973
7974
7975                 if (&connector->new_encoder->base != connector->base.encoder) {
7976                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7977                         config->mode_changed = true;
7978                 }
7979
7980                 /* Disable all disconnected encoders. */
7981                 if (connector->base.status == connector_status_disconnected)
7982                         connector->new_encoder = NULL;
7983         }
7984         /* connector->new_encoder is now updated for all connectors. */
7985
7986         /* Update crtc of enabled connectors. */
7987         count = 0;
7988         list_for_each_entry(connector, &dev->mode_config.connector_list,
7989                             base.head) {
7990                 if (!connector->new_encoder)
7991                         continue;
7992
7993                 new_crtc = connector->new_encoder->base.crtc;
7994
7995                 for (ro = 0; ro < set->num_connectors; ro++) {
7996                         if (set->connectors[ro] == &connector->base)
7997                                 new_crtc = set->crtc;
7998                 }
7999
8000                 /* Make sure the new CRTC will work with the encoder */
8001                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8002                                            new_crtc)) {
8003                         return -EINVAL;
8004                 }
8005                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8006
8007                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8008                         connector->base.base.id,
8009                         drm_get_connector_name(&connector->base),
8010                         new_crtc->base.id);
8011         }
8012
8013         /* Check for any encoders that needs to be disabled. */
8014         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8015                             base.head) {
8016                 list_for_each_entry(connector,
8017                                     &dev->mode_config.connector_list,
8018                                     base.head) {
8019                         if (connector->new_encoder == encoder) {
8020                                 WARN_ON(!connector->new_encoder->new_crtc);
8021
8022                                 goto next_encoder;
8023                         }
8024                 }
8025                 encoder->new_crtc = NULL;
8026 next_encoder:
8027                 /* Only now check for crtc changes so we don't miss encoders
8028                  * that will be disabled. */
8029                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8030                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8031                         config->mode_changed = true;
8032                 }
8033         }
8034         /* Now we've also updated encoder->new_crtc for all encoders. */
8035
8036         return 0;
8037 }
8038
8039 static int intel_crtc_set_config(struct drm_mode_set *set)
8040 {
8041         struct drm_device *dev;
8042         struct drm_mode_set save_set;
8043         struct intel_set_config *config;
8044         int ret;
8045
8046         BUG_ON(!set);
8047         BUG_ON(!set->crtc);
8048         BUG_ON(!set->crtc->helper_private);
8049
8050         if (!set->mode)
8051                 set->fb = NULL;
8052
8053         /* The fb helper likes to play gross jokes with ->mode_set_config.
8054          * Unfortunately the crtc helper doesn't do much at all for this case,
8055          * so we have to cope with this madness until the fb helper is fixed up. */
8056         if (set->fb && set->num_connectors == 0)
8057                 return 0;
8058
8059         if (set->fb) {
8060                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8061                                 set->crtc->base.id, set->fb->base.id,
8062                                 (int)set->num_connectors, set->x, set->y);
8063         } else {
8064                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8065         }
8066
8067         dev = set->crtc->dev;
8068
8069         ret = -ENOMEM;
8070         config = kzalloc(sizeof(*config), GFP_KERNEL);
8071         if (!config)
8072                 goto out_config;
8073
8074         ret = intel_set_config_save_state(dev, config);
8075         if (ret)
8076                 goto out_config;
8077
8078         save_set.crtc = set->crtc;
8079         save_set.mode = &set->crtc->mode;
8080         save_set.x = set->crtc->x;
8081         save_set.y = set->crtc->y;
8082         save_set.fb = set->crtc->fb;
8083
8084         /* Compute whether we need a full modeset, only an fb base update or no
8085          * change at all. In the future we might also check whether only the
8086          * mode changed, e.g. for LVDS where we only change the panel fitter in
8087          * such cases. */
8088         intel_set_config_compute_mode_changes(set, config);
8089
8090         ret = intel_modeset_stage_output_state(dev, set, config);
8091         if (ret)
8092                 goto fail;
8093
8094         if (config->mode_changed) {
8095                 if (set->mode) {
8096                         DRM_DEBUG_KMS("attempting to set mode from"
8097                                         " userspace\n");
8098                         drm_mode_debug_printmodeline(set->mode);
8099                 }
8100
8101                 if (!intel_set_mode(set->crtc, set->mode,
8102                                     set->x, set->y, set->fb)) {
8103                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8104                                   set->crtc->base.id);
8105                         ret = -EINVAL;
8106                         goto fail;
8107                 }
8108         } else if (config->fb_changed) {
8109                 ret = intel_pipe_set_base(set->crtc,
8110                                           set->x, set->y, set->fb);
8111         }
8112
8113         intel_set_config_free(config);
8114
8115         return 0;
8116
8117 fail:
8118         intel_set_config_restore_state(dev, config);
8119
8120         /* Try to restore the config */
8121         if (config->mode_changed &&
8122             !intel_set_mode(save_set.crtc, save_set.mode,
8123                             save_set.x, save_set.y, save_set.fb))
8124                 DRM_ERROR("failed to restore config after modeset failure\n");
8125
8126 out_config:
8127         intel_set_config_free(config);
8128         return ret;
8129 }
8130
8131 static const struct drm_crtc_funcs intel_crtc_funcs = {
8132         .cursor_set = intel_crtc_cursor_set,
8133         .cursor_move = intel_crtc_cursor_move,
8134         .gamma_set = intel_crtc_gamma_set,
8135         .set_config = intel_crtc_set_config,
8136         .destroy = intel_crtc_destroy,
8137         .page_flip = intel_crtc_page_flip,
8138 };
8139
8140 static void intel_cpu_pll_init(struct drm_device *dev)
8141 {
8142         if (IS_HASWELL(dev))
8143                 intel_ddi_pll_init(dev);
8144 }
8145
8146 static void intel_pch_pll_init(struct drm_device *dev)
8147 {
8148         drm_i915_private_t *dev_priv = dev->dev_private;
8149         int i;
8150
8151         if (dev_priv->num_pch_pll == 0) {
8152                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8153                 return;
8154         }
8155
8156         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8157                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8158                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8159                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8160         }
8161 }
8162
8163 static void intel_crtc_init(struct drm_device *dev, int pipe)
8164 {
8165         drm_i915_private_t *dev_priv = dev->dev_private;
8166         struct intel_crtc *intel_crtc;
8167         int i;
8168
8169         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8170         if (intel_crtc == NULL)
8171                 return;
8172
8173         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8174
8175         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8176         for (i = 0; i < 256; i++) {
8177                 intel_crtc->lut_r[i] = i;
8178                 intel_crtc->lut_g[i] = i;
8179                 intel_crtc->lut_b[i] = i;
8180         }
8181
8182         /* Swap pipes & planes for FBC on pre-965 */
8183         intel_crtc->pipe = pipe;
8184         intel_crtc->plane = pipe;
8185         intel_crtc->cpu_transcoder = pipe;
8186         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8187                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8188                 intel_crtc->plane = !pipe;
8189         }
8190
8191         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8192                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8193         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8194         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8195
8196         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8197
8198         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8199 }
8200
8201 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8202                                 struct drm_file *file)
8203 {
8204         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8205         struct drm_mode_object *drmmode_obj;
8206         struct intel_crtc *crtc;
8207
8208         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8209                 return -ENODEV;
8210
8211         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8212                         DRM_MODE_OBJECT_CRTC);
8213
8214         if (!drmmode_obj) {
8215                 DRM_ERROR("no such CRTC id\n");
8216                 return -EINVAL;
8217         }
8218
8219         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8220         pipe_from_crtc_id->pipe = crtc->pipe;
8221
8222         return 0;
8223 }
8224
8225 static int intel_encoder_clones(struct intel_encoder *encoder)
8226 {
8227         struct drm_device *dev = encoder->base.dev;
8228         struct intel_encoder *source_encoder;
8229         int index_mask = 0;
8230         int entry = 0;
8231
8232         list_for_each_entry(source_encoder,
8233                             &dev->mode_config.encoder_list, base.head) {
8234
8235                 if (encoder == source_encoder)
8236                         index_mask |= (1 << entry);
8237
8238                 /* Intel hw has only one MUX where enocoders could be cloned. */
8239                 if (encoder->cloneable && source_encoder->cloneable)
8240                         index_mask |= (1 << entry);
8241
8242                 entry++;
8243         }
8244
8245         return index_mask;
8246 }
8247
8248 static bool has_edp_a(struct drm_device *dev)
8249 {
8250         struct drm_i915_private *dev_priv = dev->dev_private;
8251
8252         if (!IS_MOBILE(dev))
8253                 return false;
8254
8255         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8256                 return false;
8257
8258         if (IS_GEN5(dev) &&
8259             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8260                 return false;
8261
8262         return true;
8263 }
8264
8265 static void intel_setup_outputs(struct drm_device *dev)
8266 {
8267         struct drm_i915_private *dev_priv = dev->dev_private;
8268         struct intel_encoder *encoder;
8269         bool dpd_is_edp = false;
8270         bool has_lvds;
8271
8272         has_lvds = intel_lvds_init(dev);
8273         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8274                 /* disable the panel fitter on everything but LVDS */
8275                 I915_WRITE(PFIT_CONTROL, 0);
8276         }
8277
8278         if (HAS_PCH_SPLIT(dev)) {
8279                 dpd_is_edp = intel_dpd_is_edp(dev);
8280
8281                 if (has_edp_a(dev))
8282                         intel_dp_init(dev, DP_A, PORT_A);
8283
8284                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8285                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8286         }
8287
8288         intel_crt_init(dev);
8289
8290         if (IS_HASWELL(dev)) {
8291                 int found;
8292
8293                 /* Haswell uses DDI functions to detect digital outputs */
8294                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8295                 /* DDI A only supports eDP */
8296                 if (found)
8297                         intel_ddi_init(dev, PORT_A);
8298
8299                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8300                  * register */
8301                 found = I915_READ(SFUSE_STRAP);
8302
8303                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8304                         intel_ddi_init(dev, PORT_B);
8305                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8306                         intel_ddi_init(dev, PORT_C);
8307                 if (found & SFUSE_STRAP_DDID_DETECTED)
8308                         intel_ddi_init(dev, PORT_D);
8309         } else if (HAS_PCH_SPLIT(dev)) {
8310                 int found;
8311
8312                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8313                         /* PCH SDVOB multiplex with HDMIB */
8314                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8315                         if (!found)
8316                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8317                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8318                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8319                 }
8320
8321                 if (I915_READ(HDMIC) & PORT_DETECTED)
8322                         intel_hdmi_init(dev, HDMIC, PORT_C);
8323
8324                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8325                         intel_hdmi_init(dev, HDMID, PORT_D);
8326
8327                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8328                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8329
8330                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8331                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8332         } else if (IS_VALLEYVIEW(dev)) {
8333                 int found;
8334
8335                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8336                 if (I915_READ(DP_C) & DP_DETECTED)
8337                         intel_dp_init(dev, DP_C, PORT_C);
8338
8339                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8340                         /* SDVOB multiplex with HDMIB */
8341                         found = intel_sdvo_init(dev, SDVOB, true);
8342                         if (!found)
8343                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8344                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8345                                 intel_dp_init(dev, DP_B, PORT_B);
8346                 }
8347
8348                 if (I915_READ(SDVOC) & PORT_DETECTED)
8349                         intel_hdmi_init(dev, SDVOC, PORT_C);
8350
8351         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8352                 bool found = false;
8353
8354                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8355                         DRM_DEBUG_KMS("probing SDVOB\n");
8356                         found = intel_sdvo_init(dev, SDVOB, true);
8357                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8358                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8359                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8360                         }
8361
8362                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8363                                 DRM_DEBUG_KMS("probing DP_B\n");
8364                                 intel_dp_init(dev, DP_B, PORT_B);
8365                         }
8366                 }
8367
8368                 /* Before G4X SDVOC doesn't have its own detect register */
8369
8370                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8371                         DRM_DEBUG_KMS("probing SDVOC\n");
8372                         found = intel_sdvo_init(dev, SDVOC, false);
8373                 }
8374
8375                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8376
8377                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8378                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8379                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8380                         }
8381                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8382                                 DRM_DEBUG_KMS("probing DP_C\n");
8383                                 intel_dp_init(dev, DP_C, PORT_C);
8384                         }
8385                 }
8386
8387                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8388                     (I915_READ(DP_D) & DP_DETECTED)) {
8389                         DRM_DEBUG_KMS("probing DP_D\n");
8390                         intel_dp_init(dev, DP_D, PORT_D);
8391                 }
8392         } else if (IS_GEN2(dev))
8393                 intel_dvo_init(dev);
8394
8395         if (SUPPORTS_TV(dev))
8396                 intel_tv_init(dev);
8397
8398         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8399                 encoder->base.possible_crtcs = encoder->crtc_mask;
8400                 encoder->base.possible_clones =
8401                         intel_encoder_clones(encoder);
8402         }
8403
8404         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8405                 ironlake_init_pch_refclk(dev);
8406 }
8407
8408 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8409 {
8410         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8411
8412         drm_framebuffer_cleanup(fb);
8413         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8414
8415         kfree(intel_fb);
8416 }
8417
8418 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8419                                                 struct drm_file *file,
8420                                                 unsigned int *handle)
8421 {
8422         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8423         struct drm_i915_gem_object *obj = intel_fb->obj;
8424
8425         return drm_gem_handle_create(file, &obj->base, handle);
8426 }
8427
8428 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8429         .destroy = intel_user_framebuffer_destroy,
8430         .create_handle = intel_user_framebuffer_create_handle,
8431 };
8432
8433 int intel_framebuffer_init(struct drm_device *dev,
8434                            struct intel_framebuffer *intel_fb,
8435                            struct drm_mode_fb_cmd2 *mode_cmd,
8436                            struct drm_i915_gem_object *obj)
8437 {
8438         int ret;
8439
8440         if (obj->tiling_mode == I915_TILING_Y)
8441                 return -EINVAL;
8442
8443         if (mode_cmd->pitches[0] & 63)
8444                 return -EINVAL;
8445
8446         /* FIXME <= Gen4 stride limits are bit unclear */
8447         if (mode_cmd->pitches[0] > 32768)
8448                 return -EINVAL;
8449
8450         if (obj->tiling_mode != I915_TILING_NONE &&
8451             mode_cmd->pitches[0] != obj->stride)
8452                 return -EINVAL;
8453
8454         /* Reject formats not supported by any plane early. */
8455         switch (mode_cmd->pixel_format) {
8456         case DRM_FORMAT_C8:
8457         case DRM_FORMAT_RGB565:
8458         case DRM_FORMAT_XRGB8888:
8459         case DRM_FORMAT_ARGB8888:
8460                 break;
8461         case DRM_FORMAT_XRGB1555:
8462         case DRM_FORMAT_ARGB1555:
8463                 if (INTEL_INFO(dev)->gen > 3)
8464                         return -EINVAL;
8465                 break;
8466         case DRM_FORMAT_XBGR8888:
8467         case DRM_FORMAT_ABGR8888:
8468         case DRM_FORMAT_XRGB2101010:
8469         case DRM_FORMAT_ARGB2101010:
8470         case DRM_FORMAT_XBGR2101010:
8471         case DRM_FORMAT_ABGR2101010:
8472                 if (INTEL_INFO(dev)->gen < 4)
8473                         return -EINVAL;
8474                 break;
8475         case DRM_FORMAT_YUYV:
8476         case DRM_FORMAT_UYVY:
8477         case DRM_FORMAT_YVYU:
8478         case DRM_FORMAT_VYUY:
8479                 if (INTEL_INFO(dev)->gen < 6)
8480                         return -EINVAL;
8481                 break;
8482         default:
8483                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8484                 return -EINVAL;
8485         }
8486
8487         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8488         if (mode_cmd->offsets[0] != 0)
8489                 return -EINVAL;
8490
8491         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8492         if (ret) {
8493                 DRM_ERROR("framebuffer init failed %d\n", ret);
8494                 return ret;
8495         }
8496
8497         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8498         intel_fb->obj = obj;
8499         return 0;
8500 }
8501
8502 static struct drm_framebuffer *
8503 intel_user_framebuffer_create(struct drm_device *dev,
8504                               struct drm_file *filp,
8505                               struct drm_mode_fb_cmd2 *mode_cmd)
8506 {
8507         struct drm_i915_gem_object *obj;
8508
8509         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8510                                                 mode_cmd->handles[0]));
8511         if (&obj->base == NULL)
8512                 return ERR_PTR(-ENOENT);
8513
8514         return intel_framebuffer_create(dev, mode_cmd, obj);
8515 }
8516
8517 static const struct drm_mode_config_funcs intel_mode_funcs = {
8518         .fb_create = intel_user_framebuffer_create,
8519         .output_poll_changed = intel_fb_output_poll_changed,
8520 };
8521
8522 /* Set up chip specific display functions */
8523 static void intel_init_display(struct drm_device *dev)
8524 {
8525         struct drm_i915_private *dev_priv = dev->dev_private;
8526
8527         /* We always want a DPMS function */
8528         if (IS_HASWELL(dev)) {
8529                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8530                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8531                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8532                 dev_priv->display.off = haswell_crtc_off;
8533                 dev_priv->display.update_plane = ironlake_update_plane;
8534         } else if (HAS_PCH_SPLIT(dev)) {
8535                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8536                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8537                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8538                 dev_priv->display.off = ironlake_crtc_off;
8539                 dev_priv->display.update_plane = ironlake_update_plane;
8540         } else {
8541                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8542                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8543                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8544                 dev_priv->display.off = i9xx_crtc_off;
8545                 dev_priv->display.update_plane = i9xx_update_plane;
8546         }
8547
8548         /* Returns the core display clock speed */
8549         if (IS_VALLEYVIEW(dev))
8550                 dev_priv->display.get_display_clock_speed =
8551                         valleyview_get_display_clock_speed;
8552         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8553                 dev_priv->display.get_display_clock_speed =
8554                         i945_get_display_clock_speed;
8555         else if (IS_I915G(dev))
8556                 dev_priv->display.get_display_clock_speed =
8557                         i915_get_display_clock_speed;
8558         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8559                 dev_priv->display.get_display_clock_speed =
8560                         i9xx_misc_get_display_clock_speed;
8561         else if (IS_I915GM(dev))
8562                 dev_priv->display.get_display_clock_speed =
8563                         i915gm_get_display_clock_speed;
8564         else if (IS_I865G(dev))
8565                 dev_priv->display.get_display_clock_speed =
8566                         i865_get_display_clock_speed;
8567         else if (IS_I85X(dev))
8568                 dev_priv->display.get_display_clock_speed =
8569                         i855_get_display_clock_speed;
8570         else /* 852, 830 */
8571                 dev_priv->display.get_display_clock_speed =
8572                         i830_get_display_clock_speed;
8573
8574         if (HAS_PCH_SPLIT(dev)) {
8575                 if (IS_GEN5(dev)) {
8576                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8577                         dev_priv->display.write_eld = ironlake_write_eld;
8578                 } else if (IS_GEN6(dev)) {
8579                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8580                         dev_priv->display.write_eld = ironlake_write_eld;
8581                 } else if (IS_IVYBRIDGE(dev)) {
8582                         /* FIXME: detect B0+ stepping and use auto training */
8583                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8584                         dev_priv->display.write_eld = ironlake_write_eld;
8585                         dev_priv->display.modeset_global_resources =
8586                                 ivb_modeset_global_resources;
8587                 } else if (IS_HASWELL(dev)) {
8588                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8589                         dev_priv->display.write_eld = haswell_write_eld;
8590                 } else
8591                         dev_priv->display.update_wm = NULL;
8592         } else if (IS_G4X(dev)) {
8593                 dev_priv->display.write_eld = g4x_write_eld;
8594         }
8595
8596         /* Default just returns -ENODEV to indicate unsupported */
8597         dev_priv->display.queue_flip = intel_default_queue_flip;
8598
8599         switch (INTEL_INFO(dev)->gen) {
8600         case 2:
8601                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8602                 break;
8603
8604         case 3:
8605                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8606                 break;
8607
8608         case 4:
8609         case 5:
8610                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8611                 break;
8612
8613         case 6:
8614                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8615                 break;
8616         case 7:
8617                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8618                 break;
8619         }
8620 }
8621
8622 /*
8623  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8624  * resume, or other times.  This quirk makes sure that's the case for
8625  * affected systems.
8626  */
8627 static void quirk_pipea_force(struct drm_device *dev)
8628 {
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630
8631         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8632         DRM_INFO("applying pipe a force quirk\n");
8633 }
8634
8635 /*
8636  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8637  */
8638 static void quirk_ssc_force_disable(struct drm_device *dev)
8639 {
8640         struct drm_i915_private *dev_priv = dev->dev_private;
8641         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8642         DRM_INFO("applying lvds SSC disable quirk\n");
8643 }
8644
8645 /*
8646  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8647  * brightness value
8648  */
8649 static void quirk_invert_brightness(struct drm_device *dev)
8650 {
8651         struct drm_i915_private *dev_priv = dev->dev_private;
8652         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8653         DRM_INFO("applying inverted panel brightness quirk\n");
8654 }
8655
8656 struct intel_quirk {
8657         int device;
8658         int subsystem_vendor;
8659         int subsystem_device;
8660         void (*hook)(struct drm_device *dev);
8661 };
8662
8663 static struct intel_quirk intel_quirks[] = {
8664         /* HP Mini needs pipe A force quirk (LP: #322104) */
8665         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8666
8667         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8668         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8669
8670         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8671         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8672
8673         /* 830/845 need to leave pipe A & dpll A up */
8674         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8675         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8676
8677         /* Lenovo U160 cannot use SSC on LVDS */
8678         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8679
8680         /* Sony Vaio Y cannot use SSC on LVDS */
8681         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8682
8683         /* Acer Aspire 5734Z must invert backlight brightness */
8684         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8685 };
8686
8687 static void intel_init_quirks(struct drm_device *dev)
8688 {
8689         struct pci_dev *d = dev->pdev;
8690         int i;
8691
8692         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8693                 struct intel_quirk *q = &intel_quirks[i];
8694
8695                 if (d->device == q->device &&
8696                     (d->subsystem_vendor == q->subsystem_vendor ||
8697                      q->subsystem_vendor == PCI_ANY_ID) &&
8698                     (d->subsystem_device == q->subsystem_device ||
8699                      q->subsystem_device == PCI_ANY_ID))
8700                         q->hook(dev);
8701         }
8702 }
8703
8704 /* Disable the VGA plane that we never use */
8705 static void i915_disable_vga(struct drm_device *dev)
8706 {
8707         struct drm_i915_private *dev_priv = dev->dev_private;
8708         u8 sr1;
8709         u32 vga_reg;
8710
8711         if (HAS_PCH_SPLIT(dev))
8712                 vga_reg = CPU_VGACNTRL;
8713         else
8714                 vga_reg = VGACNTRL;
8715
8716         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8717         outb(SR01, VGA_SR_INDEX);
8718         sr1 = inb(VGA_SR_DATA);
8719         outb(sr1 | 1<<5, VGA_SR_DATA);
8720         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8721         udelay(300);
8722
8723         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8724         POSTING_READ(vga_reg);
8725 }
8726
8727 void intel_modeset_init_hw(struct drm_device *dev)
8728 {
8729         /* We attempt to init the necessary power wells early in the initialization
8730          * time, so the subsystems that expect power to be enabled can work.
8731          */
8732         intel_init_power_wells(dev);
8733
8734         intel_prepare_ddi(dev);
8735
8736         intel_init_clock_gating(dev);
8737
8738         mutex_lock(&dev->struct_mutex);
8739         intel_enable_gt_powersave(dev);
8740         mutex_unlock(&dev->struct_mutex);
8741 }
8742
8743 void intel_modeset_init(struct drm_device *dev)
8744 {
8745         struct drm_i915_private *dev_priv = dev->dev_private;
8746         int i, ret;
8747
8748         drm_mode_config_init(dev);
8749
8750         dev->mode_config.min_width = 0;
8751         dev->mode_config.min_height = 0;
8752
8753         dev->mode_config.preferred_depth = 24;
8754         dev->mode_config.prefer_shadow = 1;
8755
8756         dev->mode_config.funcs = &intel_mode_funcs;
8757
8758         intel_init_quirks(dev);
8759
8760         intel_init_pm(dev);
8761
8762         intel_init_display(dev);
8763
8764         if (IS_GEN2(dev)) {
8765                 dev->mode_config.max_width = 2048;
8766                 dev->mode_config.max_height = 2048;
8767         } else if (IS_GEN3(dev)) {
8768                 dev->mode_config.max_width = 4096;
8769                 dev->mode_config.max_height = 4096;
8770         } else {
8771                 dev->mode_config.max_width = 8192;
8772                 dev->mode_config.max_height = 8192;
8773         }
8774         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8775
8776         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8777                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8778
8779         for (i = 0; i < dev_priv->num_pipe; i++) {
8780                 intel_crtc_init(dev, i);
8781                 ret = intel_plane_init(dev, i);
8782                 if (ret)
8783                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8784         }
8785
8786         intel_cpu_pll_init(dev);
8787         intel_pch_pll_init(dev);
8788
8789         /* Just disable it once at startup */
8790         i915_disable_vga(dev);
8791         intel_setup_outputs(dev);
8792 }
8793
8794 static void
8795 intel_connector_break_all_links(struct intel_connector *connector)
8796 {
8797         connector->base.dpms = DRM_MODE_DPMS_OFF;
8798         connector->base.encoder = NULL;
8799         connector->encoder->connectors_active = false;
8800         connector->encoder->base.crtc = NULL;
8801 }
8802
8803 static void intel_enable_pipe_a(struct drm_device *dev)
8804 {
8805         struct intel_connector *connector;
8806         struct drm_connector *crt = NULL;
8807         struct intel_load_detect_pipe load_detect_temp;
8808
8809         /* We can't just switch on the pipe A, we need to set things up with a
8810          * proper mode and output configuration. As a gross hack, enable pipe A
8811          * by enabling the load detect pipe once. */
8812         list_for_each_entry(connector,
8813                             &dev->mode_config.connector_list,
8814                             base.head) {
8815                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8816                         crt = &connector->base;
8817                         break;
8818                 }
8819         }
8820
8821         if (!crt)
8822                 return;
8823
8824         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8825                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8826
8827
8828 }
8829
8830 static bool
8831 intel_check_plane_mapping(struct intel_crtc *crtc)
8832 {
8833         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8834         u32 reg, val;
8835
8836         if (dev_priv->num_pipe == 1)
8837                 return true;
8838
8839         reg = DSPCNTR(!crtc->plane);
8840         val = I915_READ(reg);
8841
8842         if ((val & DISPLAY_PLANE_ENABLE) &&
8843             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8844                 return false;
8845
8846         return true;
8847 }
8848
8849 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8850 {
8851         struct drm_device *dev = crtc->base.dev;
8852         struct drm_i915_private *dev_priv = dev->dev_private;
8853         u32 reg;
8854
8855         /* Clear any frame start delays used for debugging left by the BIOS */
8856         reg = PIPECONF(crtc->cpu_transcoder);
8857         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8858
8859         /* We need to sanitize the plane -> pipe mapping first because this will
8860          * disable the crtc (and hence change the state) if it is wrong. Note
8861          * that gen4+ has a fixed plane -> pipe mapping.  */
8862         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8863                 struct intel_connector *connector;
8864                 bool plane;
8865
8866                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8867                               crtc->base.base.id);
8868
8869                 /* Pipe has the wrong plane attached and the plane is active.
8870                  * Temporarily change the plane mapping and disable everything
8871                  * ...  */
8872                 plane = crtc->plane;
8873                 crtc->plane = !plane;
8874                 dev_priv->display.crtc_disable(&crtc->base);
8875                 crtc->plane = plane;
8876
8877                 /* ... and break all links. */
8878                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8879                                     base.head) {
8880                         if (connector->encoder->base.crtc != &crtc->base)
8881                                 continue;
8882
8883                         intel_connector_break_all_links(connector);
8884                 }
8885
8886                 WARN_ON(crtc->active);
8887                 crtc->base.enabled = false;
8888         }
8889
8890         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8891             crtc->pipe == PIPE_A && !crtc->active) {
8892                 /* BIOS forgot to enable pipe A, this mostly happens after
8893                  * resume. Force-enable the pipe to fix this, the update_dpms
8894                  * call below we restore the pipe to the right state, but leave
8895                  * the required bits on. */
8896                 intel_enable_pipe_a(dev);
8897         }
8898
8899         /* Adjust the state of the output pipe according to whether we
8900          * have active connectors/encoders. */
8901         intel_crtc_update_dpms(&crtc->base);
8902
8903         if (crtc->active != crtc->base.enabled) {
8904                 struct intel_encoder *encoder;
8905
8906                 /* This can happen either due to bugs in the get_hw_state
8907                  * functions or because the pipe is force-enabled due to the
8908                  * pipe A quirk. */
8909                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8910                               crtc->base.base.id,
8911                               crtc->base.enabled ? "enabled" : "disabled",
8912                               crtc->active ? "enabled" : "disabled");
8913
8914                 crtc->base.enabled = crtc->active;
8915
8916                 /* Because we only establish the connector -> encoder ->
8917                  * crtc links if something is active, this means the
8918                  * crtc is now deactivated. Break the links. connector
8919                  * -> encoder links are only establish when things are
8920                  *  actually up, hence no need to break them. */
8921                 WARN_ON(crtc->active);
8922
8923                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8924                         WARN_ON(encoder->connectors_active);
8925                         encoder->base.crtc = NULL;
8926                 }
8927         }
8928 }
8929
8930 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8931 {
8932         struct intel_connector *connector;
8933         struct drm_device *dev = encoder->base.dev;
8934
8935         /* We need to check both for a crtc link (meaning that the
8936          * encoder is active and trying to read from a pipe) and the
8937          * pipe itself being active. */
8938         bool has_active_crtc = encoder->base.crtc &&
8939                 to_intel_crtc(encoder->base.crtc)->active;
8940
8941         if (encoder->connectors_active && !has_active_crtc) {
8942                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8943                               encoder->base.base.id,
8944                               drm_get_encoder_name(&encoder->base));
8945
8946                 /* Connector is active, but has no active pipe. This is
8947                  * fallout from our resume register restoring. Disable
8948                  * the encoder manually again. */
8949                 if (encoder->base.crtc) {
8950                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8951                                       encoder->base.base.id,
8952                                       drm_get_encoder_name(&encoder->base));
8953                         encoder->disable(encoder);
8954                 }
8955
8956                 /* Inconsistent output/port/pipe state happens presumably due to
8957                  * a bug in one of the get_hw_state functions. Or someplace else
8958                  * in our code, like the register restore mess on resume. Clamp
8959                  * things to off as a safer default. */
8960                 list_for_each_entry(connector,
8961                                     &dev->mode_config.connector_list,
8962                                     base.head) {
8963                         if (connector->encoder != encoder)
8964                                 continue;
8965
8966                         intel_connector_break_all_links(connector);
8967                 }
8968         }
8969         /* Enabled encoders without active connectors will be fixed in
8970          * the crtc fixup. */
8971 }
8972
8973 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8974  * and i915 state tracking structures. */
8975 void intel_modeset_setup_hw_state(struct drm_device *dev)
8976 {
8977         struct drm_i915_private *dev_priv = dev->dev_private;
8978         enum pipe pipe;
8979         u32 tmp;
8980         struct intel_crtc *crtc;
8981         struct intel_encoder *encoder;
8982         struct intel_connector *connector;
8983
8984         if (IS_HASWELL(dev)) {
8985                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8986
8987                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8988                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8989                         case TRANS_DDI_EDP_INPUT_A_ON:
8990                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8991                                 pipe = PIPE_A;
8992                                 break;
8993                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8994                                 pipe = PIPE_B;
8995                                 break;
8996                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8997                                 pipe = PIPE_C;
8998                                 break;
8999                         }
9000
9001                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9002                         crtc->cpu_transcoder = TRANSCODER_EDP;
9003
9004                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9005                                       pipe_name(pipe));
9006                 }
9007         }
9008
9009         for_each_pipe(pipe) {
9010                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9011
9012                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9013                 if (tmp & PIPECONF_ENABLE)
9014                         crtc->active = true;
9015                 else
9016                         crtc->active = false;
9017
9018                 crtc->base.enabled = crtc->active;
9019
9020                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9021                               crtc->base.base.id,
9022                               crtc->active ? "enabled" : "disabled");
9023         }
9024
9025         if (IS_HASWELL(dev))
9026                 intel_ddi_setup_hw_pll_state(dev);
9027
9028         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9029                             base.head) {
9030                 pipe = 0;
9031
9032                 if (encoder->get_hw_state(encoder, &pipe)) {
9033                         encoder->base.crtc =
9034                                 dev_priv->pipe_to_crtc_mapping[pipe];
9035                 } else {
9036                         encoder->base.crtc = NULL;
9037                 }
9038
9039                 encoder->connectors_active = false;
9040                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9041                               encoder->base.base.id,
9042                               drm_get_encoder_name(&encoder->base),
9043                               encoder->base.crtc ? "enabled" : "disabled",
9044                               pipe);
9045         }
9046
9047         list_for_each_entry(connector, &dev->mode_config.connector_list,
9048                             base.head) {
9049                 if (connector->get_hw_state(connector)) {
9050                         connector->base.dpms = DRM_MODE_DPMS_ON;
9051                         connector->encoder->connectors_active = true;
9052                         connector->base.encoder = &connector->encoder->base;
9053                 } else {
9054                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9055                         connector->base.encoder = NULL;
9056                 }
9057                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9058                               connector->base.base.id,
9059                               drm_get_connector_name(&connector->base),
9060                               connector->base.encoder ? "enabled" : "disabled");
9061         }
9062
9063         /* HW state is read out, now we need to sanitize this mess. */
9064         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9065                             base.head) {
9066                 intel_sanitize_encoder(encoder);
9067         }
9068
9069         for_each_pipe(pipe) {
9070                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9071                 intel_sanitize_crtc(crtc);
9072         }
9073
9074         intel_modeset_update_staged_output_state(dev);
9075
9076         intel_modeset_check_state(dev);
9077
9078         drm_mode_config_reset(dev);
9079 }
9080
9081 void intel_modeset_gem_init(struct drm_device *dev)
9082 {
9083         intel_modeset_init_hw(dev);
9084
9085         intel_setup_overlay(dev);
9086
9087         intel_modeset_setup_hw_state(dev);
9088 }
9089
9090 void intel_modeset_cleanup(struct drm_device *dev)
9091 {
9092         struct drm_i915_private *dev_priv = dev->dev_private;
9093         struct drm_crtc *crtc;
9094         struct intel_crtc *intel_crtc;
9095
9096         drm_kms_helper_poll_fini(dev);
9097         mutex_lock(&dev->struct_mutex);
9098
9099         intel_unregister_dsm_handler();
9100
9101
9102         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9103                 /* Skip inactive CRTCs */
9104                 if (!crtc->fb)
9105                         continue;
9106
9107                 intel_crtc = to_intel_crtc(crtc);
9108                 intel_increase_pllclock(crtc);
9109         }
9110
9111         intel_disable_fbc(dev);
9112
9113         intel_disable_gt_powersave(dev);
9114
9115         ironlake_teardown_rc6(dev);
9116
9117         if (IS_VALLEYVIEW(dev))
9118                 vlv_init_dpio(dev);
9119
9120         mutex_unlock(&dev->struct_mutex);
9121
9122         /* Disable the irq before mode object teardown, for the irq might
9123          * enqueue unpin/hotplug work. */
9124         drm_irq_uninstall(dev);
9125         cancel_work_sync(&dev_priv->hotplug_work);
9126         cancel_work_sync(&dev_priv->rps.work);
9127
9128         /* flush any delayed tasks or pending work */
9129         flush_scheduled_work();
9130
9131         drm_mode_config_cleanup(dev);
9132 }
9133
9134 /*
9135  * Return which encoder is currently attached for connector.
9136  */
9137 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9138 {
9139         return &intel_attached_encoder(connector)->base;
9140 }
9141
9142 void intel_connector_attach_encoder(struct intel_connector *connector,
9143                                     struct intel_encoder *encoder)
9144 {
9145         connector->encoder = encoder;
9146         drm_mode_connector_attach_encoder(&connector->base,
9147                                           &encoder->base);
9148 }
9149
9150 /*
9151  * set vga decode state - true == enable VGA decode
9152  */
9153 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9154 {
9155         struct drm_i915_private *dev_priv = dev->dev_private;
9156         u16 gmch_ctrl;
9157
9158         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9159         if (state)
9160                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9161         else
9162                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9163         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9164         return 0;
9165 }
9166
9167 #ifdef CONFIG_DEBUG_FS
9168 #include <linux/seq_file.h>
9169
9170 struct intel_display_error_state {
9171         struct intel_cursor_error_state {
9172                 u32 control;
9173                 u32 position;
9174                 u32 base;
9175                 u32 size;
9176         } cursor[I915_MAX_PIPES];
9177
9178         struct intel_pipe_error_state {
9179                 u32 conf;
9180                 u32 source;
9181
9182                 u32 htotal;
9183                 u32 hblank;
9184                 u32 hsync;
9185                 u32 vtotal;
9186                 u32 vblank;
9187                 u32 vsync;
9188         } pipe[I915_MAX_PIPES];
9189
9190         struct intel_plane_error_state {
9191                 u32 control;
9192                 u32 stride;
9193                 u32 size;
9194                 u32 pos;
9195                 u32 addr;
9196                 u32 surface;
9197                 u32 tile_offset;
9198         } plane[I915_MAX_PIPES];
9199 };
9200
9201 struct intel_display_error_state *
9202 intel_display_capture_error_state(struct drm_device *dev)
9203 {
9204         drm_i915_private_t *dev_priv = dev->dev_private;
9205         struct intel_display_error_state *error;
9206         enum transcoder cpu_transcoder;
9207         int i;
9208
9209         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9210         if (error == NULL)
9211                 return NULL;
9212
9213         for_each_pipe(i) {
9214                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9215
9216                 error->cursor[i].control = I915_READ(CURCNTR(i));
9217                 error->cursor[i].position = I915_READ(CURPOS(i));
9218                 error->cursor[i].base = I915_READ(CURBASE(i));
9219
9220                 error->plane[i].control = I915_READ(DSPCNTR(i));
9221                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9222                 error->plane[i].size = I915_READ(DSPSIZE(i));
9223                 error->plane[i].pos = I915_READ(DSPPOS(i));
9224                 error->plane[i].addr = I915_READ(DSPADDR(i));
9225                 if (INTEL_INFO(dev)->gen >= 4) {
9226                         error->plane[i].surface = I915_READ(DSPSURF(i));
9227                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9228                 }
9229
9230                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9231                 error->pipe[i].source = I915_READ(PIPESRC(i));
9232                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9233                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9234                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9235                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9236                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9237                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9238         }
9239
9240         return error;
9241 }
9242
9243 void
9244 intel_display_print_error_state(struct seq_file *m,
9245                                 struct drm_device *dev,
9246                                 struct intel_display_error_state *error)
9247 {
9248         drm_i915_private_t *dev_priv = dev->dev_private;
9249         int i;
9250
9251         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9252         for_each_pipe(i) {
9253                 seq_printf(m, "Pipe [%d]:\n", i);
9254                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9255                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9256                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9257                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9258                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9259                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9260                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9261                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9262
9263                 seq_printf(m, "Plane [%d]:\n", i);
9264                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9265                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9266                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9267                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9268                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9269                 if (INTEL_INFO(dev)->gen >= 4) {
9270                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9271                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9272                 }
9273
9274                 seq_printf(m, "Cursor [%d]:\n", i);
9275                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9276                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9277                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9278         }
9279 }
9280 #endif