Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 941 {
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         u32 frame, frame_reg = PIPEFRAME(pipe);
 944
 945         frame = I915_READ(frame_reg);
 946
 947         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 948                 DRM_DEBUG_KMS("vblank wait timed out\n");
 949 }
 950
 951 /**
 952  * intel_wait_for_vblank - wait for vblank on a given pipe
 953  * @dev: drm device
 954  * @pipe: pipe to wait for
 955  *
 956  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 957  * mode setting code.
 958  */
 959 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 960 {
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         int pipestat_reg = PIPESTAT(pipe);
 963
 964         if (INTEL_INFO(dev)->gen >= 5) {
 965                 ironlake_wait_for_vblank(dev, pipe);
 966                 return;
 967         }
 968
 969         /* Clear existing vblank status. Note this will clear any other
 970          * sticky status fields as well.
 971          *
 972          * This races with i915_driver_irq_handler() with the result
 973          * that either function could miss a vblank event.  Here it is not
 974          * fatal, as we will either wait upon the next vblank interrupt or
 975          * timeout.  Generally speaking intel_wait_for_vblank() is only
 976          * called during modeset at which time the GPU should be idle and
 977          * should *not* be performing page flips and thus not waiting on
 978          * vblanks...
 979          * Currently, the result of us stealing a vblank from the irq
 980          * handler is that a single frame will be skipped during swapbuffers.
 981          */
 982         I915_WRITE(pipestat_reg,
 983                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 984
 985         /* Wait for vblank interrupt bit to set */
 986         if (wait_for(I915_READ(pipestat_reg) &
 987                      PIPE_VBLANK_INTERRUPT_STATUS,
 988                      50))
 989                 DRM_DEBUG_KMS("vblank wait timed out\n");
 990 }
 991
 992 /*
 993  * intel_wait_for_pipe_off - wait for pipe to turn off
 994  * @dev: drm device
 995  * @pipe: pipe to wait for
 996  *
 997  * After disabling a pipe, we can't wait for vblank in the usual way,
 998  * spinning on the vblank interrupt status bit, since we won't actually
 999  * see an interrupt when the pipe is disabled.
1000  *
1001  * On Gen4 and above:
1002  *   wait for the pipe register state bit to turn off
1003  *
1004  * Otherwise:
1005  *   wait for the display line value to settle (it usually
1006  *   ends up stopping at the start of the next frame).
1007  *
1008  */
1009 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013         if (INTEL_INFO(dev)->gen >= 4) {
1014                 int reg = PIPECONF(pipe);
1015
1016                 /* Wait for the Pipe State to go off */
1017                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1018                              100))
1019                         WARN(1, "pipe_off wait timed out\n");
1020         } else {
1021                 u32 last_line, line_mask;
1022                 int reg = PIPEDSL(pipe);
1023                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1024
1025                 if (IS_GEN2(dev))
1026                         line_mask = DSL_LINEMASK_GEN2;
1027                 else
1028                         line_mask = DSL_LINEMASK_GEN3;
1029
1030                 /* Wait for the display line to settle */
1031                 do {
1032                         last_line = I915_READ(reg) & line_mask;
1033                         mdelay(5);
1034                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1035                          time_after(timeout, jiffies));
1036                 if (time_after(jiffies, timeout))
1037                         WARN(1, "pipe_off wait timed out\n");
1038         }
1039 }
1040
1041 static const char *state_string(bool enabled)
1042 {
1043         return enabled ? "on" : "off";
1044 }
1045
1046 /* Only for pre-ILK configs */
1047 static void assert_pll(struct drm_i915_private *dev_priv,
1048                        enum pipe pipe, bool state)
1049 {
1050         int reg;
1051         u32 val;
1052         bool cur_state;
1053
1054         reg = DPLL(pipe);
1055         val = I915_READ(reg);
1056         cur_state = !!(val & DPLL_VCO_ENABLE);
1057         WARN(cur_state != state,
1058              "PLL state assertion failure (expected %s, current %s)\n",
1059              state_string(state), state_string(cur_state));
1060 }
1061 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1062 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1063
1064 /* For ILK+ */
1065 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1066                            struct intel_pch_pll *pll,
1067                            struct intel_crtc *crtc,
1068                            bool state)
1069 {
1070         u32 val;
1071         bool cur_state;
1072
1073         if (HAS_PCH_LPT(dev_priv->dev)) {
1074                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1075                 return;
1076         }
1077
1078         if (WARN (!pll,
1079                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1080                 return;
1081
1082         val = I915_READ(pll->pll_reg);
1083         cur_state = !!(val & DPLL_VCO_ENABLE);
1084         WARN(cur_state != state,
1085              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1086              pll->pll_reg, state_string(state), state_string(cur_state), val);
1087
1088         /* Make sure the selected PLL is correctly attached to the transcoder */
1089         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1090                 u32 pch_dpll;
1091
1092                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1093                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1094                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1095                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1096                           cur_state, crtc->pipe, pch_dpll)) {
1097                         cur_state = !!(val >> (4*crtc->pipe + 3));
1098                         WARN(cur_state != state,
1099                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1100                              pll->pll_reg == _PCH_DPLL_B,
1101                              state_string(state),
1102                              crtc->pipe,
1103                              val);
1104                 }
1105         }
1106 }
1107 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1108 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1109
1110 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         int reg;
1114         u32 val;
1115         bool cur_state;
1116
1117         if (IS_HASWELL(dev_priv->dev)) {
1118                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1119                 reg = DDI_FUNC_CTL(pipe);
1120                 val = I915_READ(reg);
1121                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1122         } else {
1123                 reg = FDI_TX_CTL(pipe);
1124                 val = I915_READ(reg);
1125                 cur_state = !!(val & FDI_TX_ENABLE);
1126         }
1127         WARN(cur_state != state,
1128              "FDI TX state assertion failure (expected %s, current %s)\n",
1129              state_string(state), state_string(cur_state));
1130 }
1131 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1132 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1133
1134 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1135                           enum pipe pipe, bool state)
1136 {
1137         int reg;
1138         u32 val;
1139         bool cur_state;
1140
1141         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1142                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1143                         return;
1144         } else {
1145                 reg = FDI_RX_CTL(pipe);
1146                 val = I915_READ(reg);
1147                 cur_state = !!(val & FDI_RX_ENABLE);
1148         }
1149         WARN(cur_state != state,
1150              "FDI RX state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1154 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1155
1156 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1157                                       enum pipe pipe)
1158 {
1159         int reg;
1160         u32 val;
1161
1162         /* ILK FDI PLL is always enabled */
1163         if (dev_priv->info->gen == 5)
1164                 return;
1165
1166         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1167         if (IS_HASWELL(dev_priv->dev))
1168                 return;
1169
1170         reg = FDI_TX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1176                                       enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1182                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1183                 return;
1184         }
1185         reg = FDI_RX_CTL(pipe);
1186         val = I915_READ(reg);
1187         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                                   enum pipe pipe)
1192 {
1193         int pp_reg, lvds_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1199                 pp_reg = PCH_PP_CONTROL;
1200                 lvds_reg = PCH_LVDS;
1201         } else {
1202                 pp_reg = PP_CONTROL;
1203                 lvds_reg = LVDS;
1204         }
1205
1206         val = I915_READ(pp_reg);
1207         if (!(val & PANEL_POWER_ON) ||
1208             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1209                 locked = false;
1210
1211         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1212                 panel_pipe = PIPE_B;
1213
1214         WARN(panel_pipe == pipe && locked,
1215              "panel assertion failure, pipe %c regs locked\n",
1216              pipe_name(pipe));
1217 }
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         reg = PIPECONF(pipe);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & PIPECONF_ENABLE);
1233         WARN(cur_state != state,
1234              "pipe %c assertion failure (expected %s, current %s)\n",
1235              pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237
1238 static void assert_plane(struct drm_i915_private *dev_priv,
1239                          enum plane plane, bool state)
1240 {
1241         int reg;
1242         u32 val;
1243         bool cur_state;
1244
1245         reg = DSPCNTR(plane);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1248         WARN(cur_state != state,
1249              "plane %c assertion failure (expected %s, current %s)\n",
1250              plane_name(plane), state_string(state), state_string(cur_state));
1251 }
1252
1253 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1254 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1255
1256 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1257                                    enum pipe pipe)
1258 {
1259         int reg, i;
1260         u32 val;
1261         int cur_pipe;
1262
1263         /* Planes are fixed to pipes on ILK+ */
1264         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1265                 reg = DSPCNTR(pipe);
1266                 val = I915_READ(reg);
1267                 WARN((val & DISPLAY_PLANE_ENABLE),
1268                      "plane %c assertion failure, should be disabled but not\n",
1269                      plane_name(pipe));
1270                 return;
1271         }
1272
1273         /* Need to check both planes against the pipe */
1274         for (i = 0; i < 2; i++) {
1275                 reg = DSPCNTR(i);
1276                 val = I915_READ(reg);
1277                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1278                         DISPPLANE_SEL_PIPE_SHIFT;
1279                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1280                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1281                      plane_name(i), pipe_name(pipe));
1282         }
1283 }
1284
1285 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1286 {
1287         u32 val;
1288         bool enabled;
1289
1290         if (HAS_PCH_LPT(dev_priv->dev)) {
1291                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1292                 return;
1293         }
1294
1295         val = I915_READ(PCH_DREF_CONTROL);
1296         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1297                             DREF_SUPERSPREAD_SOURCE_MASK));
1298         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1299 }
1300
1301 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1302                                        enum pipe pipe)
1303 {
1304         int reg;
1305         u32 val;
1306         bool enabled;
1307
1308         reg = TRANSCONF(pipe);
1309         val = I915_READ(reg);
1310         enabled = !!(val & TRANS_ENABLE);
1311         WARN(enabled,
1312              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313              pipe_name(pipe));
1314 }
1315
1316 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1317                             enum pipe pipe, u32 port_sel, u32 val)
1318 {
1319         if ((val & DP_PORT_EN) == 0)
1320                 return false;
1321
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1324                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1325                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1326                         return false;
1327         } else {
1328                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1329                         return false;
1330         }
1331         return true;
1332 }
1333
1334 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1335                               enum pipe pipe, u32 val)
1336 {
1337         if ((val & PORT_ENABLE) == 0)
1338                 return false;
1339
1340         if (HAS_PCH_CPT(dev_priv->dev)) {
1341                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & LVDS_PORT_EN) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1358                         return false;
1359         } else {
1360                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1361                         return false;
1362         }
1363         return true;
1364 }
1365
1366 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1367                               enum pipe pipe, u32 val)
1368 {
1369         if ((val & ADPA_DAC_ENABLE) == 0)
1370                 return false;
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1382                                    enum pipe pipe, int reg, u32 port_sel)
1383 {
1384         u32 val = I915_READ(reg);
1385         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1386              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1387              reg, pipe_name(pipe));
1388
1389         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1390              && (val & DP_PIPEB_SELECT),
1391              "IBX PCH dp port still using transcoder B\n");
1392 }
1393
1394 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1395                                      enum pipe pipe, int reg)
1396 {
1397         u32 val = I915_READ(reg);
1398         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1399              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1400              reg, pipe_name(pipe));
1401
1402         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1403              && (val & SDVO_PIPE_B_SELECT),
1404              "IBX PCH hdmi port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1408                                       enum pipe pipe)
1409 {
1410         int reg;
1411         u32 val;
1412
1413         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1414         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1415         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1416
1417         reg = PCH_ADPA;
1418         val = I915_READ(reg);
1419         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1420              "PCH VGA enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         reg = PCH_LVDS;
1424         val = I915_READ(reg);
1425         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1426              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1427              pipe_name(pipe));
1428
1429         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1430         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1431         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1432 }
1433
1434 /**
1435  * intel_enable_pll - enable a PLL
1436  * @dev_priv: i915 private structure
1437  * @pipe: pipe PLL to enable
1438  *
1439  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1440  * make sure the PLL reg is writable first though, since the panel write
1441  * protect mechanism may be enabled.
1442  *
1443  * Note!  This is for pre-ILK only.
1444  *
1445  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1446  */
1447 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451
1452         /* No really, not for ILK+ */
1453         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1454
1455         /* PLL is protected by panel, make sure we can write it */
1456         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1457                 assert_panel_unlocked(dev_priv, pipe);
1458
1459         reg = DPLL(pipe);
1460         val = I915_READ(reg);
1461         val |= DPLL_VCO_ENABLE;
1462
1463         /* We do this three times for luck */
1464         I915_WRITE(reg, val);
1465         POSTING_READ(reg);
1466         udelay(150); /* wait for warmup */
1467         I915_WRITE(reg, val);
1468         POSTING_READ(reg);
1469         udelay(150); /* wait for warmup */
1470         I915_WRITE(reg, val);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473 }
1474
1475 /**
1476  * intel_disable_pll - disable a PLL
1477  * @dev_priv: i915 private structure
1478  * @pipe: pipe PLL to disable
1479  *
1480  * Disable the PLL for @pipe, making sure the pipe is off first.
1481  *
1482  * Note!  This is for pre-ILK only.
1483  */
1484 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1485 {
1486         int reg;
1487         u32 val;
1488
1489         /* Don't disable pipe A or pipe A PLLs if needed */
1490         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1491                 return;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         reg = DPLL(pipe);
1497         val = I915_READ(reg);
1498         val &= ~DPLL_VCO_ENABLE;
1499         I915_WRITE(reg, val);
1500         POSTING_READ(reg);
1501 }
1502
1503 /* SBI access */
1504 static void
1505 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1506 {
1507         unsigned long flags;
1508
1509         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1510         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1511                                 100)) {
1512                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1513                 goto out_unlock;
1514         }
1515
1516         I915_WRITE(SBI_ADDR,
1517                         (reg << 16));
1518         I915_WRITE(SBI_DATA,
1519                         value);
1520         I915_WRITE(SBI_CTL_STAT,
1521                         SBI_BUSY |
1522                         SBI_CTL_OP_CRWR);
1523
1524         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1525                                 100)) {
1526                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1527                 goto out_unlock;
1528         }
1529
1530 out_unlock:
1531         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1532 }
1533
1534 static u32
1535 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1536 {
1537         unsigned long flags;
1538         u32 value = 0;
1539
1540         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1544                 goto out_unlock;
1545         }
1546
1547         I915_WRITE(SBI_ADDR,
1548                         (reg << 16));
1549         I915_WRITE(SBI_CTL_STAT,
1550                         SBI_BUSY |
1551                         SBI_CTL_OP_CRRD);
1552
1553         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1554                                 100)) {
1555                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1556                 goto out_unlock;
1557         }
1558
1559         value = I915_READ(SBI_DATA);
1560
1561 out_unlock:
1562         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1563         return value;
1564 }
1565
1566 /**
1567  * intel_enable_pch_pll - enable PCH PLL
1568  * @dev_priv: i915 private structure
1569  * @pipe: pipe PLL to enable
1570  *
1571  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1572  * drives the transcoder clock.
1573  */
1574 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1575 {
1576         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1577         struct intel_pch_pll *pll;
1578         int reg;
1579         u32 val;
1580
1581         /* PCH PLLs only available on ILK, SNB and IVB */
1582         BUG_ON(dev_priv->info->gen < 5);
1583         pll = intel_crtc->pch_pll;
1584         if (pll == NULL)
1585                 return;
1586
1587         if (WARN_ON(pll->refcount == 0))
1588                 return;
1589
1590         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1591                       pll->pll_reg, pll->active, pll->on,
1592                       intel_crtc->base.base.id);
1593
1594         /* PCH refclock must be enabled first */
1595         assert_pch_refclk_enabled(dev_priv);
1596
1597         if (pll->active++ && pll->on) {
1598                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1599                 return;
1600         }
1601
1602         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1603
1604         reg = pll->pll_reg;
1605         val = I915_READ(reg);
1606         val |= DPLL_VCO_ENABLE;
1607         I915_WRITE(reg, val);
1608         POSTING_READ(reg);
1609         udelay(200);
1610
1611         pll->on = true;
1612 }
1613
1614 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1615 {
1616         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1617         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1618         int reg;
1619         u32 val;
1620
1621         /* PCH only available on ILK+ */
1622         BUG_ON(dev_priv->info->gen < 5);
1623         if (pll == NULL)
1624                return;
1625
1626         if (WARN_ON(pll->refcount == 0))
1627                 return;
1628
1629         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1630                       pll->pll_reg, pll->active, pll->on,
1631                       intel_crtc->base.base.id);
1632
1633         if (WARN_ON(pll->active == 0)) {
1634                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1635                 return;
1636         }
1637
1638         if (--pll->active) {
1639                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1640                 return;
1641         }
1642
1643         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1644
1645         /* Make sure transcoder isn't still depending on us */
1646         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1647
1648         reg = pll->pll_reg;
1649         val = I915_READ(reg);
1650         val &= ~DPLL_VCO_ENABLE;
1651         I915_WRITE(reg, val);
1652         POSTING_READ(reg);
1653         udelay(200);
1654
1655         pll->on = false;
1656 }
1657
1658 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1659                                     enum pipe pipe)
1660 {
1661         int reg;
1662         u32 val, pipeconf_val;
1663         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1664
1665         /* PCH only available on ILK+ */
1666         BUG_ON(dev_priv->info->gen < 5);
1667
1668         /* Make sure PCH DPLL is enabled */
1669         assert_pch_pll_enabled(dev_priv,
1670                                to_intel_crtc(crtc)->pch_pll,
1671                                to_intel_crtc(crtc));
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, pipe);
1675         assert_fdi_rx_enabled(dev_priv, pipe);
1676
1677         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1678                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1679                 return;
1680         }
1681         reg = TRANSCONF(pipe);
1682         val = I915_READ(reg);
1683         pipeconf_val = I915_READ(PIPECONF(pipe));
1684
1685         if (HAS_PCH_IBX(dev_priv->dev)) {
1686                 /*
1687                  * make the BPC in transcoder be consistent with
1688                  * that in pipeconf reg.
1689                  */
1690                 val &= ~PIPE_BPC_MASK;
1691                 val |= pipeconf_val & PIPE_BPC_MASK;
1692         }
1693
1694         val &= ~TRANS_INTERLACE_MASK;
1695         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1696                 if (HAS_PCH_IBX(dev_priv->dev) &&
1697                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1698                         val |= TRANS_LEGACY_INTERLACED_ILK;
1699                 else
1700                         val |= TRANS_INTERLACED;
1701         else
1702                 val |= TRANS_PROGRESSIVE;
1703
1704         I915_WRITE(reg, val | TRANS_ENABLE);
1705         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1706                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1707 }
1708
1709 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1710                                      enum pipe pipe)
1711 {
1712         int reg;
1713         u32 val;
1714
1715         /* FDI relies on the transcoder */
1716         assert_fdi_tx_disabled(dev_priv, pipe);
1717         assert_fdi_rx_disabled(dev_priv, pipe);
1718
1719         /* Ports must be off as well */
1720         assert_pch_ports_disabled(dev_priv, pipe);
1721
1722         reg = TRANSCONF(pipe);
1723         val = I915_READ(reg);
1724         val &= ~TRANS_ENABLE;
1725         I915_WRITE(reg, val);
1726         /* wait for PCH transcoder off, transcoder state */
1727         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1728                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1729 }
1730
1731 /**
1732  * intel_enable_pipe - enable a pipe, asserting requirements
1733  * @dev_priv: i915 private structure
1734  * @pipe: pipe to enable
1735  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1736  *
1737  * Enable @pipe, making sure that various hardware specific requirements
1738  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1739  *
1740  * @pipe should be %PIPE_A or %PIPE_B.
1741  *
1742  * Will wait until the pipe is actually running (i.e. first vblank) before
1743  * returning.
1744  */
1745 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1746                               bool pch_port)
1747 {
1748         int reg;
1749         u32 val;
1750
1751         /*
1752          * A pipe without a PLL won't actually be able to drive bits from
1753          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1754          * need the check.
1755          */
1756         if (!HAS_PCH_SPLIT(dev_priv->dev))
1757                 assert_pll_enabled(dev_priv, pipe);
1758         else {
1759                 if (pch_port) {
1760                         /* if driving the PCH, we need FDI enabled */
1761                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1762                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1763                 }
1764                 /* FIXME: assert CPU port conditions for SNB+ */
1765         }
1766
1767         reg = PIPECONF(pipe);
1768         val = I915_READ(reg);
1769         if (val & PIPECONF_ENABLE)
1770                 return;
1771
1772         I915_WRITE(reg, val | PIPECONF_ENABLE);
1773         intel_wait_for_vblank(dev_priv->dev, pipe);
1774 }
1775
1776 /**
1777  * intel_disable_pipe - disable a pipe, asserting requirements
1778  * @dev_priv: i915 private structure
1779  * @pipe: pipe to disable
1780  *
1781  * Disable @pipe, making sure that various hardware specific requirements
1782  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1783  *
1784  * @pipe should be %PIPE_A or %PIPE_B.
1785  *
1786  * Will wait until the pipe has shut down before returning.
1787  */
1788 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1789                                enum pipe pipe)
1790 {
1791         int reg;
1792         u32 val;
1793
1794         /*
1795          * Make sure planes won't keep trying to pump pixels to us,
1796          * or we might hang the display.
1797          */
1798         assert_planes_disabled(dev_priv, pipe);
1799
1800         /* Don't disable pipe A or pipe A PLLs if needed */
1801         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802                 return;
1803
1804         reg = PIPECONF(pipe);
1805         val = I915_READ(reg);
1806         if ((val & PIPECONF_ENABLE) == 0)
1807                 return;
1808
1809         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1810         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1811 }
1812
1813 /*
1814  * Plane regs are double buffered, going from enabled->disabled needs a
1815  * trigger in order to latch.  The display address reg provides this.
1816  */
1817 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1818                                       enum plane plane)
1819 {
1820         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1821         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 int
1876 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1877                            struct drm_i915_gem_object *obj,
1878                            struct intel_ring_buffer *pipelined)
1879 {
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         u32 alignment;
1882         int ret;
1883
1884         switch (obj->tiling_mode) {
1885         case I915_TILING_NONE:
1886                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887                         alignment = 128 * 1024;
1888                 else if (INTEL_INFO(dev)->gen >= 4)
1889                         alignment = 4 * 1024;
1890                 else
1891                         alignment = 64 * 1024;
1892                 break;
1893         case I915_TILING_X:
1894                 /* pin() will align the object as required by fence */
1895                 alignment = 0;
1896                 break;
1897         case I915_TILING_Y:
1898                 /* FIXME: Is this true? */
1899                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1900                 return -EINVAL;
1901         default:
1902                 BUG();
1903         }
1904
1905         dev_priv->mm.interruptible = false;
1906         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1907         if (ret)
1908                 goto err_interruptible;
1909
1910         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1911          * fence, whereas 965+ only requires a fence if using
1912          * framebuffer compression.  For simplicity, we always install
1913          * a fence as the cost is not that onerous.
1914          */
1915         ret = i915_gem_object_get_fence(obj);
1916         if (ret)
1917                 goto err_unpin;
1918
1919         i915_gem_object_pin_fence(obj);
1920
1921         dev_priv->mm.interruptible = true;
1922         return 0;
1923
1924 err_unpin:
1925         i915_gem_object_unpin(obj);
1926 err_interruptible:
1927         dev_priv->mm.interruptible = true;
1928         return ret;
1929 }
1930
1931 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1932 {
1933         i915_gem_object_unpin_fence(obj);
1934         i915_gem_object_unpin(obj);
1935 }
1936
1937 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1938  * is assumed to be a power-of-two. */
1939 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1940                                                         unsigned int bpp,
1941                                                         unsigned int pitch)
1942 {
1943         int tile_rows, tiles;
1944
1945         tile_rows = *y / 8;
1946         *y %= 8;
1947         tiles = *x / (512/bpp);
1948         *x %= 512/bpp;
1949
1950         return tile_rows * pitch * 8 + tiles * 4096;
1951 }
1952
1953 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1954                              int x, int y)
1955 {
1956         struct drm_device *dev = crtc->dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1959         struct intel_framebuffer *intel_fb;
1960         struct drm_i915_gem_object *obj;
1961         int plane = intel_crtc->plane;
1962         unsigned long linear_offset;
1963         u32 dspcntr;
1964         u32 reg;
1965
1966         switch (plane) {
1967         case 0:
1968         case 1:
1969                 break;
1970         default:
1971                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1972                 return -EINVAL;
1973         }
1974
1975         intel_fb = to_intel_framebuffer(fb);
1976         obj = intel_fb->obj;
1977
1978         reg = DSPCNTR(plane);
1979         dspcntr = I915_READ(reg);
1980         /* Mask out pixel format bits in case we change it */
1981         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1982         switch (fb->bits_per_pixel) {
1983         case 8:
1984                 dspcntr |= DISPPLANE_8BPP;
1985                 break;
1986         case 16:
1987                 if (fb->depth == 15)
1988                         dspcntr |= DISPPLANE_15_16BPP;
1989                 else
1990                         dspcntr |= DISPPLANE_16BPP;
1991                 break;
1992         case 24:
1993         case 32:
1994                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1995                 break;
1996         default:
1997                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1998                 return -EINVAL;
1999         }
2000         if (INTEL_INFO(dev)->gen >= 4) {
2001                 if (obj->tiling_mode != I915_TILING_NONE)
2002                         dspcntr |= DISPPLANE_TILED;
2003                 else
2004                         dspcntr &= ~DISPPLANE_TILED;
2005         }
2006
2007         I915_WRITE(reg, dspcntr);
2008
2009         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2010
2011         if (INTEL_INFO(dev)->gen >= 4) {
2012                 intel_crtc->dspaddr_offset =
2013                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2014                                                            fb->bits_per_pixel / 8,
2015                                                            fb->pitches[0]);
2016                 linear_offset -= intel_crtc->dspaddr_offset;
2017         } else {
2018                 intel_crtc->dspaddr_offset = linear_offset;
2019         }
2020
2021         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2022                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2023         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2024         if (INTEL_INFO(dev)->gen >= 4) {
2025                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2026                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2027                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2028                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2029         } else
2030                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2031         POSTING_READ(reg);
2032
2033         return 0;
2034 }
2035
2036 static int ironlake_update_plane(struct drm_crtc *crtc,
2037                                  struct drm_framebuffer *fb, int x, int y)
2038 {
2039         struct drm_device *dev = crtc->dev;
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042         struct intel_framebuffer *intel_fb;
2043         struct drm_i915_gem_object *obj;
2044         int plane = intel_crtc->plane;
2045         unsigned long linear_offset;
2046         u32 dspcntr;
2047         u32 reg;
2048
2049         switch (plane) {
2050         case 0:
2051         case 1:
2052         case 2:
2053                 break;
2054         default:
2055                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056                 return -EINVAL;
2057         }
2058
2059         intel_fb = to_intel_framebuffer(fb);
2060         obj = intel_fb->obj;
2061
2062         reg = DSPCNTR(plane);
2063         dspcntr = I915_READ(reg);
2064         /* Mask out pixel format bits in case we change it */
2065         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066         switch (fb->bits_per_pixel) {
2067         case 8:
2068                 dspcntr |= DISPPLANE_8BPP;
2069                 break;
2070         case 16:
2071                 if (fb->depth != 16)
2072                         return -EINVAL;
2073
2074                 dspcntr |= DISPPLANE_16BPP;
2075                 break;
2076         case 24:
2077         case 32:
2078                 if (fb->depth == 24)
2079                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2080                 else if (fb->depth == 30)
2081                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2082                 else
2083                         return -EINVAL;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2087                 return -EINVAL;
2088         }
2089
2090         if (obj->tiling_mode != I915_TILING_NONE)
2091                 dspcntr |= DISPPLANE_TILED;
2092         else
2093                 dspcntr &= ~DISPPLANE_TILED;
2094
2095         /* must disable */
2096         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101         intel_crtc->dspaddr_offset =
2102                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2103                                                    fb->bits_per_pixel / 8,
2104                                                    fb->pitches[0]);
2105         linear_offset -= intel_crtc->dspaddr_offset;
2106
2107         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2108                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2109         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2110         I915_MODIFY_DISPBASE(DSPSURF(plane),
2111                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2112         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2113         I915_WRITE(DSPLINOFF(plane), linear_offset);
2114         POSTING_READ(reg);
2115
2116         return 0;
2117 }
2118
2119 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2120 static int
2121 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2122                            int x, int y, enum mode_set_atomic state)
2123 {
2124         struct drm_device *dev = crtc->dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126
2127         if (dev_priv->display.disable_fbc)
2128                 dev_priv->display.disable_fbc(dev);
2129         intel_increase_pllclock(crtc);
2130
2131         return dev_priv->display.update_plane(crtc, fb, x, y);
2132 }
2133
2134 static int
2135 intel_finish_fb(struct drm_framebuffer *old_fb)
2136 {
2137         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2138         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2139         bool was_interruptible = dev_priv->mm.interruptible;
2140         int ret;
2141
2142         wait_event(dev_priv->pending_flip_queue,
2143                    atomic_read(&dev_priv->mm.wedged) ||
2144                    atomic_read(&obj->pending_flip) == 0);
2145
2146         /* Big Hammer, we also need to ensure that any pending
2147          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2148          * current scanout is retired before unpinning the old
2149          * framebuffer.
2150          *
2151          * This should only fail upon a hung GPU, in which case we
2152          * can safely continue.
2153          */
2154         dev_priv->mm.interruptible = false;
2155         ret = i915_gem_object_finish_gpu(obj);
2156         dev_priv->mm.interruptible = was_interruptible;
2157
2158         return ret;
2159 }
2160
2161 static int
2162 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2163                     struct drm_framebuffer *fb)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         struct drm_i915_master_private *master_priv;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169         struct drm_framebuffer *old_fb;
2170         int ret;
2171
2172         /* no fb bound */
2173         if (!fb) {
2174                 DRM_ERROR("No FB bound\n");
2175                 return 0;
2176         }
2177
2178         if(intel_crtc->plane > dev_priv->num_pipe) {
2179                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2180                                 intel_crtc->plane,
2181                                 dev_priv->num_pipe);
2182                 return -EINVAL;
2183         }
2184
2185         mutex_lock(&dev->struct_mutex);
2186         ret = intel_pin_and_fence_fb_obj(dev,
2187                                          to_intel_framebuffer(fb)->obj,
2188                                          NULL);
2189         if (ret != 0) {
2190                 mutex_unlock(&dev->struct_mutex);
2191                 DRM_ERROR("pin & fence failed\n");
2192                 return ret;
2193         }
2194
2195         if (crtc->fb)
2196                 intel_finish_fb(crtc->fb);
2197
2198         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2199         if (ret) {
2200                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2201                 mutex_unlock(&dev->struct_mutex);
2202                 DRM_ERROR("failed to update base address\n");
2203                 return ret;
2204         }
2205
2206         old_fb = crtc->fb;
2207         crtc->fb = fb;
2208         crtc->x = x;
2209         crtc->y = y;
2210
2211         if (old_fb) {
2212                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2213                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2214         }
2215
2216         intel_update_fbc(dev);
2217         mutex_unlock(&dev->struct_mutex);
2218
2219         if (!dev->primary->master)
2220                 return 0;
2221
2222         master_priv = dev->primary->master->driver_priv;
2223         if (!master_priv->sarea_priv)
2224                 return 0;
2225
2226         if (intel_crtc->pipe) {
2227                 master_priv->sarea_priv->pipeB_x = x;
2228                 master_priv->sarea_priv->pipeB_y = y;
2229         } else {
2230                 master_priv->sarea_priv->pipeA_x = x;
2231                 master_priv->sarea_priv->pipeA_y = y;
2232         }
2233
2234         return 0;
2235 }
2236
2237 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         u32 dpa_ctl;
2242
2243         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2244         dpa_ctl = I915_READ(DP_A);
2245         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2246
2247         if (clock < 200000) {
2248                 u32 temp;
2249                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2250                 /* workaround for 160Mhz:
2251                    1) program 0x4600c bits 15:0 = 0x8124
2252                    2) program 0x46010 bit 0 = 1
2253                    3) program 0x46034 bit 24 = 1
2254                    4) program 0x64000 bit 14 = 1
2255                    */
2256                 temp = I915_READ(0x4600c);
2257                 temp &= 0xffff0000;
2258                 I915_WRITE(0x4600c, temp | 0x8124);
2259
2260                 temp = I915_READ(0x46010);
2261                 I915_WRITE(0x46010, temp | 1);
2262
2263                 temp = I915_READ(0x46034);
2264                 I915_WRITE(0x46034, temp | (1 << 24));
2265         } else {
2266                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2267         }
2268         I915_WRITE(DP_A, dpa_ctl);
2269
2270         POSTING_READ(DP_A);
2271         udelay(500);
2272 }
2273
2274 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         int pipe = intel_crtc->pipe;
2280         u32 reg, temp;
2281
2282         /* enable normal train */
2283         reg = FDI_TX_CTL(pipe);
2284         temp = I915_READ(reg);
2285         if (IS_IVYBRIDGE(dev)) {
2286                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2287                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2288         } else {
2289                 temp &= ~FDI_LINK_TRAIN_NONE;
2290                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2291         }
2292         I915_WRITE(reg, temp);
2293
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (HAS_PCH_CPT(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2298                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE;
2302         }
2303         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2304
2305         /* wait one idle pattern time */
2306         POSTING_READ(reg);
2307         udelay(1000);
2308
2309         /* IVB wants error correction enabled */
2310         if (IS_IVYBRIDGE(dev))
2311                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2312                            FDI_FE_ERRC_ENABLE);
2313 }
2314
2315 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         u32 flags = I915_READ(SOUTH_CHICKEN1);
2319
2320         flags |= FDI_PHASE_SYNC_OVR(pipe);
2321         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2322         flags |= FDI_PHASE_SYNC_EN(pipe);
2323         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2324         POSTING_READ(SOUTH_CHICKEN1);
2325 }
2326
2327 /* The FDI link training functions for ILK/Ibexpeak. */
2328 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2329 {
2330         struct drm_device *dev = crtc->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         int pipe = intel_crtc->pipe;
2334         int plane = intel_crtc->plane;
2335         u32 reg, temp, tries;
2336
2337         /* FDI needs bits from pipe & plane first */
2338         assert_pipe_enabled(dev_priv, pipe);
2339         assert_plane_enabled(dev_priv, plane);
2340
2341         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2342            for train result */
2343         reg = FDI_RX_IMR(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_RX_SYMBOL_LOCK;
2346         temp &= ~FDI_RX_BIT_LOCK;
2347         I915_WRITE(reg, temp);
2348         I915_READ(reg);
2349         udelay(150);
2350
2351         /* enable CPU FDI TX and PCH FDI RX */
2352         reg = FDI_TX_CTL(pipe);
2353         temp = I915_READ(reg);
2354         temp &= ~(7 << 19);
2355         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2356         temp &= ~FDI_LINK_TRAIN_NONE;
2357         temp |= FDI_LINK_TRAIN_PATTERN_1;
2358         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         temp &= ~FDI_LINK_TRAIN_NONE;
2363         temp |= FDI_LINK_TRAIN_PATTERN_1;
2364         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2365
2366         POSTING_READ(reg);
2367         udelay(150);
2368
2369         /* Ironlake workaround, enable clock pointer after FDI enable*/
2370         if (HAS_PCH_IBX(dev)) {
2371                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2372                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2373                            FDI_RX_PHASE_SYNC_POINTER_EN);
2374         }
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if ((temp & FDI_RX_BIT_LOCK)) {
2382                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2383                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 1 fail!\n");
2389
2390         /* Train 2 */
2391         reg = FDI_TX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         temp &= ~FDI_LINK_TRAIN_NONE;
2394         temp |= FDI_LINK_TRAIN_PATTERN_2;
2395         I915_WRITE(reg, temp);
2396
2397         reg = FDI_RX_CTL(pipe);
2398         temp = I915_READ(reg);
2399         temp &= ~FDI_LINK_TRAIN_NONE;
2400         temp |= FDI_LINK_TRAIN_PATTERN_2;
2401         I915_WRITE(reg, temp);
2402
2403         POSTING_READ(reg);
2404         udelay(150);
2405
2406         reg = FDI_RX_IIR(pipe);
2407         for (tries = 0; tries < 5; tries++) {
2408                 temp = I915_READ(reg);
2409                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411                 if (temp & FDI_RX_SYMBOL_LOCK) {
2412                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2414                         break;
2415                 }
2416         }
2417         if (tries == 5)
2418                 DRM_ERROR("FDI train 2 fail!\n");
2419
2420         DRM_DEBUG_KMS("FDI train done\n");
2421
2422 }
2423
2424 static const int snb_b_fdi_train_param[] = {
2425         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2426         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2427         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2428         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2429 };
2430
2431 /* The FDI link training functions for SNB/Cougarpoint. */
2432 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2433 {
2434         struct drm_device *dev = crtc->dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437         int pipe = intel_crtc->pipe;
2438         u32 reg, temp, i, retry;
2439
2440         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2441            for train result */
2442         reg = FDI_RX_IMR(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_RX_SYMBOL_LOCK;
2445         temp &= ~FDI_RX_BIT_LOCK;
2446         I915_WRITE(reg, temp);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         /* enable CPU FDI TX and PCH FDI RX */
2452         reg = FDI_TX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         temp &= ~(7 << 19);
2455         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2456         temp &= ~FDI_LINK_TRAIN_NONE;
2457         temp |= FDI_LINK_TRAIN_PATTERN_1;
2458         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2459         /* SNB-B */
2460         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2461         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2462
2463         reg = FDI_RX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         if (HAS_PCH_CPT(dev)) {
2466                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2467                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2468         } else {
2469                 temp &= ~FDI_LINK_TRAIN_NONE;
2470                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2471         }
2472         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2473
2474         POSTING_READ(reg);
2475         udelay(150);
2476
2477         if (HAS_PCH_CPT(dev))
2478                 cpt_phase_pointer_enable(dev, pipe);
2479
2480         for (i = 0; i < 4; i++) {
2481                 reg = FDI_TX_CTL(pipe);
2482                 temp = I915_READ(reg);
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 temp |= snb_b_fdi_train_param[i];
2485                 I915_WRITE(reg, temp);
2486
2487                 POSTING_READ(reg);
2488                 udelay(500);
2489
2490                 for (retry = 0; retry < 5; retry++) {
2491                         reg = FDI_RX_IIR(pipe);
2492                         temp = I915_READ(reg);
2493                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2494                         if (temp & FDI_RX_BIT_LOCK) {
2495                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2497                                 break;
2498                         }
2499                         udelay(50);
2500                 }
2501                 if (retry < 5)
2502                         break;
2503         }
2504         if (i == 4)
2505                 DRM_ERROR("FDI train 1 fail!\n");
2506
2507         /* Train 2 */
2508         reg = FDI_TX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_2;
2512         if (IS_GEN6(dev)) {
2513                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514                 /* SNB-B */
2515                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2516         }
2517         I915_WRITE(reg, temp);
2518
2519         reg = FDI_RX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         if (HAS_PCH_CPT(dev)) {
2522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2524         } else {
2525                 temp &= ~FDI_LINK_TRAIN_NONE;
2526                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         }
2528         I915_WRITE(reg, temp);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         for (i = 0; i < 4; i++) {
2534                 reg = FDI_TX_CTL(pipe);
2535                 temp = I915_READ(reg);
2536                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537                 temp |= snb_b_fdi_train_param[i];
2538                 I915_WRITE(reg, temp);
2539
2540                 POSTING_READ(reg);
2541                 udelay(500);
2542
2543                 for (retry = 0; retry < 5; retry++) {
2544                         reg = FDI_RX_IIR(pipe);
2545                         temp = I915_READ(reg);
2546                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547                         if (temp & FDI_RX_SYMBOL_LOCK) {
2548                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2550                                 break;
2551                         }
2552                         udelay(50);
2553                 }
2554                 if (retry < 5)
2555                         break;
2556         }
2557         if (i == 4)
2558                 DRM_ERROR("FDI train 2 fail!\n");
2559
2560         DRM_DEBUG_KMS("FDI train done.\n");
2561 }
2562
2563 /* Manual link training for Ivy Bridge A0 parts */
2564 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2565 {
2566         struct drm_device *dev = crtc->dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2569         int pipe = intel_crtc->pipe;
2570         u32 reg, temp, i;
2571
2572         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2573            for train result */
2574         reg = FDI_RX_IMR(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_RX_SYMBOL_LOCK;
2577         temp &= ~FDI_RX_BIT_LOCK;
2578         I915_WRITE(reg, temp);
2579
2580         POSTING_READ(reg);
2581         udelay(150);
2582
2583         /* enable CPU FDI TX and PCH FDI RX */
2584         reg = FDI_TX_CTL(pipe);
2585         temp = I915_READ(reg);
2586         temp &= ~(7 << 19);
2587         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2588         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2590         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2591         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2592         temp |= FDI_COMPOSITE_SYNC;
2593         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_LINK_TRAIN_AUTO;
2598         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600         temp |= FDI_COMPOSITE_SYNC;
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         if (HAS_PCH_CPT(dev))
2607                 cpt_phase_pointer_enable(dev, pipe);
2608
2609         for (i = 0; i < 4; i++) {
2610                 reg = FDI_TX_CTL(pipe);
2611                 temp = I915_READ(reg);
2612                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613                 temp |= snb_b_fdi_train_param[i];
2614                 I915_WRITE(reg, temp);
2615
2616                 POSTING_READ(reg);
2617                 udelay(500);
2618
2619                 reg = FDI_RX_IIR(pipe);
2620                 temp = I915_READ(reg);
2621                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2622
2623                 if (temp & FDI_RX_BIT_LOCK ||
2624                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2625                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2626                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2627                         break;
2628                 }
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2638         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2646         I915_WRITE(reg, temp);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         for (i = 0; i < 4; i++) {
2652                 reg = FDI_TX_CTL(pipe);
2653                 temp = I915_READ(reg);
2654                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655                 temp |= snb_b_fdi_train_param[i];
2656                 I915_WRITE(reg, temp);
2657
2658                 POSTING_READ(reg);
2659                 udelay(500);
2660
2661                 reg = FDI_RX_IIR(pipe);
2662                 temp = I915_READ(reg);
2663                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2664
2665                 if (temp & FDI_RX_SYMBOL_LOCK) {
2666                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2667                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2668                         break;
2669                 }
2670         }
2671         if (i == 4)
2672                 DRM_ERROR("FDI train 2 fail!\n");
2673
2674         DRM_DEBUG_KMS("FDI train done.\n");
2675 }
2676
2677 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2678 {
2679         struct drm_device *dev = intel_crtc->base.dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         int pipe = intel_crtc->pipe;
2682         u32 reg, temp;
2683
2684         /* Write the TU size bits so error detection works */
2685         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2686                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2687
2688         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2689         reg = FDI_RX_CTL(pipe);
2690         temp = I915_READ(reg);
2691         temp &= ~((0x7 << 19) | (0x7 << 16));
2692         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2693         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2694         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2695
2696         POSTING_READ(reg);
2697         udelay(200);
2698
2699         /* Switch from Rawclk to PCDclk */
2700         temp = I915_READ(reg);
2701         I915_WRITE(reg, temp | FDI_PCDCLK);
2702
2703         POSTING_READ(reg);
2704         udelay(200);
2705
2706         /* On Haswell, the PLL configuration for ports and pipes is handled
2707          * separately, as part of DDI setup */
2708         if (!IS_HASWELL(dev)) {
2709                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2710                 reg = FDI_TX_CTL(pipe);
2711                 temp = I915_READ(reg);
2712                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2713                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2714
2715                         POSTING_READ(reg);
2716                         udelay(100);
2717                 }
2718         }
2719 }
2720
2721 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2722 {
2723         struct drm_device *dev = intel_crtc->base.dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* Switch from PCDclk to Rawclk */
2729         reg = FDI_RX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2732
2733         /* Disable CPU FDI TX PLL */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2737
2738         POSTING_READ(reg);
2739         udelay(100);
2740
2741         reg = FDI_RX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2744
2745         /* Wait for the clocks to turn off. */
2746         POSTING_READ(reg);
2747         udelay(100);
2748 }
2749
2750 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2751 {
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         u32 flags = I915_READ(SOUTH_CHICKEN1);
2754
2755         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2756         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2757         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2758         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2759         POSTING_READ(SOUTH_CHICKEN1);
2760 }
2761 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2762 {
2763         struct drm_device *dev = crtc->dev;
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2766         int pipe = intel_crtc->pipe;
2767         u32 reg, temp;
2768
2769         /* disable CPU FDI tx and PCH FDI rx */
2770         reg = FDI_TX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2773         POSTING_READ(reg);
2774
2775         reg = FDI_RX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         temp &= ~(0x7 << 16);
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(100);
2783
2784         /* Ironlake workaround, disable clock pointer after downing FDI */
2785         if (HAS_PCH_IBX(dev)) {
2786                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2787                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2788                            I915_READ(FDI_RX_CHICKEN(pipe) &
2789                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2790         } else if (HAS_PCH_CPT(dev)) {
2791                 cpt_phase_pointer_disable(dev, pipe);
2792         }
2793
2794         /* still set train pattern 1 */
2795         reg = FDI_TX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         temp &= ~FDI_LINK_TRAIN_NONE;
2798         temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         I915_WRITE(reg, temp);
2800
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         if (HAS_PCH_CPT(dev)) {
2804                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2805                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2806         } else {
2807                 temp &= ~FDI_LINK_TRAIN_NONE;
2808                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809         }
2810         /* BPC in FDI rx is consistent with that in PIPECONF */
2811         temp &= ~(0x07 << 16);
2812         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2813         I915_WRITE(reg, temp);
2814
2815         POSTING_READ(reg);
2816         udelay(100);
2817 }
2818
2819 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2820 {
2821         struct drm_device *dev = crtc->dev;
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         unsigned long flags;
2824         bool pending;
2825
2826         if (atomic_read(&dev_priv->mm.wedged))
2827                 return false;
2828
2829         spin_lock_irqsave(&dev->event_lock, flags);
2830         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2831         spin_unlock_irqrestore(&dev->event_lock, flags);
2832
2833         return pending;
2834 }
2835
2836 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840
2841         if (crtc->fb == NULL)
2842                 return;
2843
2844         wait_event(dev_priv->pending_flip_queue,
2845                    !intel_crtc_has_pending_flip(crtc));
2846
2847         mutex_lock(&dev->struct_mutex);
2848         intel_finish_fb(crtc->fb);
2849         mutex_unlock(&dev->struct_mutex);
2850 }
2851
2852 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct intel_encoder *intel_encoder;
2856
2857         /*
2858          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2859          * must be driven by its own crtc; no sharing is possible.
2860          */
2861         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2862
2863                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2864                  * CPU handles all others */
2865                 if (IS_HASWELL(dev)) {
2866                         /* It is still unclear how this will work on PPT, so throw up a warning */
2867                         WARN_ON(!HAS_PCH_LPT(dev));
2868
2869                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2870                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2871                                 return true;
2872                         } else {
2873                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2874                                               intel_encoder->type);
2875                                 return false;
2876                         }
2877                 }
2878
2879                 switch (intel_encoder->type) {
2880                 case INTEL_OUTPUT_EDP:
2881                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2882                                 return false;
2883                         continue;
2884                 }
2885         }
2886
2887         return true;
2888 }
2889
2890 /* Program iCLKIP clock to the desired frequency */
2891 static void lpt_program_iclkip(struct drm_crtc *crtc)
2892 {
2893         struct drm_device *dev = crtc->dev;
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2896         u32 temp;
2897
2898         /* It is necessary to ungate the pixclk gate prior to programming
2899          * the divisors, and gate it back when it is done.
2900          */
2901         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2902
2903         /* Disable SSCCTL */
2904         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2905                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2906                                         SBI_SSCCTL_DISABLE);
2907
2908         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2909         if (crtc->mode.clock == 20000) {
2910                 auxdiv = 1;
2911                 divsel = 0x41;
2912                 phaseinc = 0x20;
2913         } else {
2914                 /* The iCLK virtual clock root frequency is in MHz,
2915                  * but the crtc->mode.clock in in KHz. To get the divisors,
2916                  * it is necessary to divide one by another, so we
2917                  * convert the virtual clock precision to KHz here for higher
2918                  * precision.
2919                  */
2920                 u32 iclk_virtual_root_freq = 172800 * 1000;
2921                 u32 iclk_pi_range = 64;
2922                 u32 desired_divisor, msb_divisor_value, pi_value;
2923
2924                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2925                 msb_divisor_value = desired_divisor / iclk_pi_range;
2926                 pi_value = desired_divisor % iclk_pi_range;
2927
2928                 auxdiv = 0;
2929                 divsel = msb_divisor_value - 2;
2930                 phaseinc = pi_value;
2931         }
2932
2933         /* This should not happen with any sane values */
2934         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2935                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2936         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2937                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2938
2939         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2940                         crtc->mode.clock,
2941                         auxdiv,
2942                         divsel,
2943                         phasedir,
2944                         phaseinc);
2945
2946         /* Program SSCDIVINTPHASE6 */
2947         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2948         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2949         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2950         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2951         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2952         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2953         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2954
2955         intel_sbi_write(dev_priv,
2956                         SBI_SSCDIVINTPHASE6,
2957                         temp);
2958
2959         /* Program SSCAUXDIV */
2960         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2961         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2962         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2963         intel_sbi_write(dev_priv,
2964                         SBI_SSCAUXDIV6,
2965                         temp);
2966
2967
2968         /* Enable modulator and associated divider */
2969         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2970         temp &= ~SBI_SSCCTL_DISABLE;
2971         intel_sbi_write(dev_priv,
2972                         SBI_SSCCTL6,
2973                         temp);
2974
2975         /* Wait for initialization time */
2976         udelay(24);
2977
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2979 }
2980
2981 /*
2982  * Enable PCH resources required for PCH ports:
2983  *   - PCH PLLs
2984  *   - FDI training & RX/TX
2985  *   - update transcoder timings
2986  *   - DP transcoding bits
2987  *   - transcoder
2988  */
2989 static void ironlake_pch_enable(struct drm_crtc *crtc)
2990 {
2991         struct drm_device *dev = crtc->dev;
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2994         int pipe = intel_crtc->pipe;
2995         u32 reg, temp;
2996
2997         assert_transcoder_disabled(dev_priv, pipe);
2998
2999         /* For PCH output, training FDI link */
3000         dev_priv->display.fdi_link_train(crtc);
3001
3002         intel_enable_pch_pll(intel_crtc);
3003
3004         if (HAS_PCH_LPT(dev)) {
3005                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3006                 lpt_program_iclkip(crtc);
3007         } else if (HAS_PCH_CPT(dev)) {
3008                 u32 sel;
3009
3010                 temp = I915_READ(PCH_DPLL_SEL);
3011                 switch (pipe) {
3012                 default:
3013                 case 0:
3014                         temp |= TRANSA_DPLL_ENABLE;
3015                         sel = TRANSA_DPLLB_SEL;
3016                         break;
3017                 case 1:
3018                         temp |= TRANSB_DPLL_ENABLE;
3019                         sel = TRANSB_DPLLB_SEL;
3020                         break;
3021                 case 2:
3022                         temp |= TRANSC_DPLL_ENABLE;
3023                         sel = TRANSC_DPLLB_SEL;
3024                         break;
3025                 }
3026                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3027                         temp |= sel;
3028                 else
3029                         temp &= ~sel;
3030                 I915_WRITE(PCH_DPLL_SEL, temp);
3031         }
3032
3033         /* set transcoder timing, panel must allow it */
3034         assert_panel_unlocked(dev_priv, pipe);
3035         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3036         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3037         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3038
3039         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3040         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3041         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3042         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3043
3044         if (!IS_HASWELL(dev))
3045                 intel_fdi_normal_train(crtc);
3046
3047         /* For PCH DP, enable TRANS_DP_CTL */
3048         if (HAS_PCH_CPT(dev) &&
3049             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3050              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3051                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3052                 reg = TRANS_DP_CTL(pipe);
3053                 temp = I915_READ(reg);
3054                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3055                           TRANS_DP_SYNC_MASK |
3056                           TRANS_DP_BPC_MASK);
3057                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3058                          TRANS_DP_ENH_FRAMING);
3059                 temp |= bpc << 9; /* same format but at 11:9 */
3060
3061                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3062                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3063                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3064                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3065
3066                 switch (intel_trans_dp_port_sel(crtc)) {
3067                 case PCH_DP_B:
3068                         temp |= TRANS_DP_PORT_SEL_B;
3069                         break;
3070                 case PCH_DP_C:
3071                         temp |= TRANS_DP_PORT_SEL_C;
3072                         break;
3073                 case PCH_DP_D:
3074                         temp |= TRANS_DP_PORT_SEL_D;
3075                         break;
3076                 default:
3077                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3078                         temp |= TRANS_DP_PORT_SEL_B;
3079                         break;
3080                 }
3081
3082                 I915_WRITE(reg, temp);
3083         }
3084
3085         intel_enable_transcoder(dev_priv, pipe);
3086 }
3087
3088 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3089 {
3090         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3091
3092         if (pll == NULL)
3093                 return;
3094
3095         if (pll->refcount == 0) {
3096                 WARN(1, "bad PCH PLL refcount\n");
3097                 return;
3098         }
3099
3100         --pll->refcount;
3101         intel_crtc->pch_pll = NULL;
3102 }
3103
3104 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3105 {
3106         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3107         struct intel_pch_pll *pll;
3108         int i;
3109
3110         pll = intel_crtc->pch_pll;
3111         if (pll) {
3112                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3113                               intel_crtc->base.base.id, pll->pll_reg);
3114                 goto prepare;
3115         }
3116
3117         if (HAS_PCH_IBX(dev_priv->dev)) {
3118                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3119                 i = intel_crtc->pipe;
3120                 pll = &dev_priv->pch_plls[i];
3121
3122                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3123                               intel_crtc->base.base.id, pll->pll_reg);
3124
3125                 goto found;
3126         }
3127
3128         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3129                 pll = &dev_priv->pch_plls[i];
3130
3131                 /* Only want to check enabled timings first */
3132                 if (pll->refcount == 0)
3133                         continue;
3134
3135                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3136                     fp == I915_READ(pll->fp0_reg)) {
3137                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3138                                       intel_crtc->base.base.id,
3139                                       pll->pll_reg, pll->refcount, pll->active);
3140
3141                         goto found;
3142                 }
3143         }
3144
3145         /* Ok no matching timings, maybe there's a free one? */
3146         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147                 pll = &dev_priv->pch_plls[i];
3148                 if (pll->refcount == 0) {
3149                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3150                                       intel_crtc->base.base.id, pll->pll_reg);
3151                         goto found;
3152                 }
3153         }
3154
3155         return NULL;
3156
3157 found:
3158         intel_crtc->pch_pll = pll;
3159         pll->refcount++;
3160         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3161 prepare: /* separate function? */
3162         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3163
3164         /* Wait for the clocks to stabilize before rewriting the regs */
3165         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3166         POSTING_READ(pll->pll_reg);
3167         udelay(150);
3168
3169         I915_WRITE(pll->fp0_reg, fp);
3170         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3171         pll->on = false;
3172         return pll;
3173 }
3174
3175 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3176 {
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3179         u32 temp;
3180
3181         temp = I915_READ(dslreg);
3182         udelay(500);
3183         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3184                 /* Without this, mode sets may fail silently on FDI */
3185                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3186                 udelay(250);
3187                 I915_WRITE(tc2reg, 0);
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3190         }
3191 }
3192
3193 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198         struct intel_encoder *encoder;
3199         int pipe = intel_crtc->pipe;
3200         int plane = intel_crtc->plane;
3201         u32 temp;
3202         bool is_pch_port;
3203
3204         WARN_ON(!crtc->enabled);
3205
3206         if (intel_crtc->active)
3207                 return;
3208
3209         intel_crtc->active = true;
3210         intel_update_watermarks(dev);
3211
3212         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3213                 temp = I915_READ(PCH_LVDS);
3214                 if ((temp & LVDS_PORT_EN) == 0)
3215                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3216         }
3217
3218         is_pch_port = intel_crtc_driving_pch(crtc);
3219
3220         if (is_pch_port) {
3221                 ironlake_fdi_pll_enable(intel_crtc);
3222         } else {
3223                 assert_fdi_tx_disabled(dev_priv, pipe);
3224                 assert_fdi_rx_disabled(dev_priv, pipe);
3225         }
3226
3227         for_each_encoder_on_crtc(dev, crtc, encoder)
3228                 if (encoder->pre_enable)
3229                         encoder->pre_enable(encoder);
3230
3231         /* Enable panel fitting for LVDS */
3232         if (dev_priv->pch_pf_size &&
3233             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3234                 /* Force use of hard-coded filter coefficients
3235                  * as some pre-programmed values are broken,
3236                  * e.g. x201.
3237                  */
3238                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3239                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3240                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3241         }
3242
3243         /*
3244          * On ILK+ LUT must be loaded before the pipe is running but with
3245          * clocks enabled
3246          */
3247         intel_crtc_load_lut(crtc);
3248
3249         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3250         intel_enable_plane(dev_priv, plane, pipe);
3251
3252         if (is_pch_port)
3253                 ironlake_pch_enable(crtc);
3254
3255         mutex_lock(&dev->struct_mutex);
3256         intel_update_fbc(dev);
3257         mutex_unlock(&dev->struct_mutex);
3258
3259         intel_crtc_update_cursor(crtc, true);
3260
3261         for_each_encoder_on_crtc(dev, crtc, encoder)
3262                 encoder->enable(encoder);
3263
3264         if (HAS_PCH_CPT(dev))
3265                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3266
3267         /*
3268          * There seems to be a race in PCH platform hw (at least on some
3269          * outputs) where an enabled pipe still completes any pageflip right
3270          * away (as if the pipe is off) instead of waiting for vblank. As soon
3271          * as the first vblank happend, everything works as expected. Hence just
3272          * wait for one vblank before returning to avoid strange things
3273          * happening.
3274          */
3275         intel_wait_for_vblank(dev, intel_crtc->pipe);
3276 }
3277
3278 static void haswell_crtc_enable(struct drm_crtc *crtc)
3279 {
3280         struct drm_device *dev = crtc->dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3283         struct intel_encoder *encoder;
3284         int pipe = intel_crtc->pipe;
3285         int plane = intel_crtc->plane;
3286         bool is_pch_port;
3287
3288         WARN_ON(!crtc->enabled);
3289
3290         if (intel_crtc->active)
3291                 return;
3292
3293         intel_crtc->active = true;
3294         intel_update_watermarks(dev);
3295
3296         is_pch_port = intel_crtc_driving_pch(crtc);
3297
3298         if (is_pch_port) {
3299                 ironlake_fdi_pll_enable(intel_crtc);
3300         } else {
3301                 assert_fdi_tx_disabled(dev_priv, pipe);
3302                 assert_fdi_rx_disabled(dev_priv, pipe);
3303         }
3304
3305         for_each_encoder_on_crtc(dev, crtc, encoder)
3306                 if (encoder->pre_enable)
3307                         encoder->pre_enable(encoder);
3308
3309         intel_ddi_enable_pipe_clock(intel_crtc);
3310
3311         /* Enable panel fitting for eDP */
3312         if (dev_priv->pch_pf_size && HAS_eDP) {
3313                 /* Force use of hard-coded filter coefficients
3314                  * as some pre-programmed values are broken,
3315                  * e.g. x201.
3316                  */
3317                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3318                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3319                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3320         }
3321
3322         /*
3323          * On ILK+ LUT must be loaded before the pipe is running but with
3324          * clocks enabled
3325          */
3326         intel_crtc_load_lut(crtc);
3327
3328         intel_ddi_set_pipe_settings(crtc);
3329         intel_ddi_enable_pipe_func(crtc);
3330
3331         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3332         intel_enable_plane(dev_priv, plane, pipe);
3333
3334         if (is_pch_port)
3335                 ironlake_pch_enable(crtc);
3336
3337         mutex_lock(&dev->struct_mutex);
3338         intel_update_fbc(dev);
3339         mutex_unlock(&dev->struct_mutex);
3340
3341         intel_crtc_update_cursor(crtc, true);
3342
3343         for_each_encoder_on_crtc(dev, crtc, encoder)
3344                 encoder->enable(encoder);
3345
3346         /*
3347          * There seems to be a race in PCH platform hw (at least on some
3348          * outputs) where an enabled pipe still completes any pageflip right
3349          * away (as if the pipe is off) instead of waiting for vblank. As soon
3350          * as the first vblank happend, everything works as expected. Hence just
3351          * wait for one vblank before returning to avoid strange things
3352          * happening.
3353          */
3354         intel_wait_for_vblank(dev, intel_crtc->pipe);
3355 }
3356
3357 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3358 {
3359         struct drm_device *dev = crtc->dev;
3360         struct drm_i915_private *dev_priv = dev->dev_private;
3361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362         struct intel_encoder *encoder;
3363         int pipe = intel_crtc->pipe;
3364         int plane = intel_crtc->plane;
3365         u32 reg, temp;
3366
3367
3368         if (!intel_crtc->active)
3369                 return;
3370
3371         for_each_encoder_on_crtc(dev, crtc, encoder)
3372                 encoder->disable(encoder);
3373
3374         intel_crtc_wait_for_pending_flips(crtc);
3375         drm_vblank_off(dev, pipe);
3376         intel_crtc_update_cursor(crtc, false);
3377
3378         intel_disable_plane(dev_priv, plane, pipe);
3379
3380         if (dev_priv->cfb_plane == plane)
3381                 intel_disable_fbc(dev);
3382
3383         intel_disable_pipe(dev_priv, pipe);
3384
3385         /* Disable PF */
3386         I915_WRITE(PF_CTL(pipe), 0);
3387         I915_WRITE(PF_WIN_SZ(pipe), 0);
3388
3389         for_each_encoder_on_crtc(dev, crtc, encoder)
3390                 if (encoder->post_disable)
3391                         encoder->post_disable(encoder);
3392
3393         ironlake_fdi_disable(crtc);
3394
3395         intel_disable_transcoder(dev_priv, pipe);
3396
3397         if (HAS_PCH_CPT(dev)) {
3398                 /* disable TRANS_DP_CTL */
3399                 reg = TRANS_DP_CTL(pipe);
3400                 temp = I915_READ(reg);
3401                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3402                 temp |= TRANS_DP_PORT_SEL_NONE;
3403                 I915_WRITE(reg, temp);
3404
3405                 /* disable DPLL_SEL */
3406                 temp = I915_READ(PCH_DPLL_SEL);
3407                 switch (pipe) {
3408                 case 0:
3409                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3410                         break;
3411                 case 1:
3412                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3413                         break;
3414                 case 2:
3415                         /* C shares PLL A or B */
3416                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3417                         break;
3418                 default:
3419                         BUG(); /* wtf */
3420                 }
3421                 I915_WRITE(PCH_DPLL_SEL, temp);
3422         }
3423
3424         /* disable PCH DPLL */
3425         intel_disable_pch_pll(intel_crtc);
3426
3427         ironlake_fdi_pll_disable(intel_crtc);
3428
3429         intel_crtc->active = false;
3430         intel_update_watermarks(dev);
3431
3432         mutex_lock(&dev->struct_mutex);
3433         intel_update_fbc(dev);
3434         mutex_unlock(&dev->struct_mutex);
3435 }
3436
3437 static void haswell_crtc_disable(struct drm_crtc *crtc)
3438 {
3439         struct drm_device *dev = crtc->dev;
3440         struct drm_i915_private *dev_priv = dev->dev_private;
3441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3442         struct intel_encoder *encoder;
3443         int pipe = intel_crtc->pipe;
3444         int plane = intel_crtc->plane;
3445
3446         if (!intel_crtc->active)
3447                 return;
3448
3449         for_each_encoder_on_crtc(dev, crtc, encoder)
3450                 encoder->disable(encoder);
3451
3452         intel_crtc_wait_for_pending_flips(crtc);
3453         drm_vblank_off(dev, pipe);
3454         intel_crtc_update_cursor(crtc, false);
3455
3456         intel_disable_plane(dev_priv, plane, pipe);
3457
3458         if (dev_priv->cfb_plane == plane)
3459                 intel_disable_fbc(dev);
3460
3461         intel_disable_pipe(dev_priv, pipe);
3462
3463         intel_ddi_disable_pipe_func(dev_priv, pipe);
3464
3465         /* Disable PF */
3466         I915_WRITE(PF_CTL(pipe), 0);
3467         I915_WRITE(PF_WIN_SZ(pipe), 0);
3468
3469         intel_ddi_disable_pipe_clock(intel_crtc);
3470
3471         for_each_encoder_on_crtc(dev, crtc, encoder)
3472                 if (encoder->post_disable)
3473                         encoder->post_disable(encoder);
3474
3475         ironlake_fdi_disable(crtc);
3476
3477         intel_disable_transcoder(dev_priv, pipe);
3478
3479         /* disable PCH DPLL */
3480         intel_disable_pch_pll(intel_crtc);
3481
3482         ironlake_fdi_pll_disable(intel_crtc);
3483
3484         intel_crtc->active = false;
3485         intel_update_watermarks(dev);
3486
3487         mutex_lock(&dev->struct_mutex);
3488         intel_update_fbc(dev);
3489         mutex_unlock(&dev->struct_mutex);
3490 }
3491
3492 static void ironlake_crtc_off(struct drm_crtc *crtc)
3493 {
3494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495         intel_put_pch_pll(intel_crtc);
3496 }
3497
3498 static void haswell_crtc_off(struct drm_crtc *crtc)
3499 {
3500         intel_ddi_put_crtc_pll(crtc);
3501 }
3502
3503 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3504 {
3505         if (!enable && intel_crtc->overlay) {
3506                 struct drm_device *dev = intel_crtc->base.dev;
3507                 struct drm_i915_private *dev_priv = dev->dev_private;
3508
3509                 mutex_lock(&dev->struct_mutex);
3510                 dev_priv->mm.interruptible = false;
3511                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3512                 dev_priv->mm.interruptible = true;
3513                 mutex_unlock(&dev->struct_mutex);
3514         }
3515
3516         /* Let userspace switch the overlay on again. In most cases userspace
3517          * has to recompute where to put it anyway.
3518          */
3519 }
3520
3521 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526         struct intel_encoder *encoder;
3527         int pipe = intel_crtc->pipe;
3528         int plane = intel_crtc->plane;
3529
3530         WARN_ON(!crtc->enabled);
3531
3532         if (intel_crtc->active)
3533                 return;
3534
3535         intel_crtc->active = true;
3536         intel_update_watermarks(dev);
3537
3538         intel_enable_pll(dev_priv, pipe);
3539         intel_enable_pipe(dev_priv, pipe, false);
3540         intel_enable_plane(dev_priv, plane, pipe);
3541
3542         intel_crtc_load_lut(crtc);
3543         intel_update_fbc(dev);
3544
3545         /* Give the overlay scaler a chance to enable if it's on this pipe */
3546         intel_crtc_dpms_overlay(intel_crtc, true);
3547         intel_crtc_update_cursor(crtc, true);
3548
3549         for_each_encoder_on_crtc(dev, crtc, encoder)
3550                 encoder->enable(encoder);
3551 }
3552
3553 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3554 {
3555         struct drm_device *dev = crtc->dev;
3556         struct drm_i915_private *dev_priv = dev->dev_private;
3557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558         struct intel_encoder *encoder;
3559         int pipe = intel_crtc->pipe;
3560         int plane = intel_crtc->plane;
3561
3562
3563         if (!intel_crtc->active)
3564                 return;
3565
3566         for_each_encoder_on_crtc(dev, crtc, encoder)
3567                 encoder->disable(encoder);
3568
3569         /* Give the overlay scaler a chance to disable if it's on this pipe */
3570         intel_crtc_wait_for_pending_flips(crtc);
3571         drm_vblank_off(dev, pipe);
3572         intel_crtc_dpms_overlay(intel_crtc, false);
3573         intel_crtc_update_cursor(crtc, false);
3574
3575         if (dev_priv->cfb_plane == plane)
3576                 intel_disable_fbc(dev);
3577
3578         intel_disable_plane(dev_priv, plane, pipe);
3579         intel_disable_pipe(dev_priv, pipe);
3580         intel_disable_pll(dev_priv, pipe);
3581
3582         intel_crtc->active = false;
3583         intel_update_fbc(dev);
3584         intel_update_watermarks(dev);
3585 }
3586
3587 static void i9xx_crtc_off(struct drm_crtc *crtc)
3588 {
3589 }
3590
3591 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3592                                     bool enabled)
3593 {
3594         struct drm_device *dev = crtc->dev;
3595         struct drm_i915_master_private *master_priv;
3596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597         int pipe = intel_crtc->pipe;
3598
3599         if (!dev->primary->master)
3600                 return;
3601
3602         master_priv = dev->primary->master->driver_priv;
3603         if (!master_priv->sarea_priv)
3604                 return;
3605
3606         switch (pipe) {
3607         case 0:
3608                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3609                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3610                 break;
3611         case 1:
3612                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3613                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3614                 break;
3615         default:
3616                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3617                 break;
3618         }
3619 }
3620
3621 /**
3622  * Sets the power management mode of the pipe and plane.
3623  */
3624 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_encoder *intel_encoder;
3629         bool enable = false;
3630
3631         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3632                 enable |= intel_encoder->connectors_active;
3633
3634         if (enable)
3635                 dev_priv->display.crtc_enable(crtc);
3636         else
3637                 dev_priv->display.crtc_disable(crtc);
3638
3639         intel_crtc_update_sarea(crtc, enable);
3640 }
3641
3642 static void intel_crtc_noop(struct drm_crtc *crtc)
3643 {
3644 }
3645
3646 static void intel_crtc_disable(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_connector *connector;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651
3652         /* crtc should still be enabled when we disable it. */
3653         WARN_ON(!crtc->enabled);
3654
3655         dev_priv->display.crtc_disable(crtc);
3656         intel_crtc_update_sarea(crtc, false);
3657         dev_priv->display.off(crtc);
3658
3659         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3660         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3661
3662         if (crtc->fb) {
3663                 mutex_lock(&dev->struct_mutex);
3664                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3665                 mutex_unlock(&dev->struct_mutex);
3666                 crtc->fb = NULL;
3667         }
3668
3669         /* Update computed state. */
3670         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3671                 if (!connector->encoder || !connector->encoder->crtc)
3672                         continue;
3673
3674                 if (connector->encoder->crtc != crtc)
3675                         continue;
3676
3677                 connector->dpms = DRM_MODE_DPMS_OFF;
3678                 to_intel_encoder(connector->encoder)->connectors_active = false;
3679         }
3680 }
3681
3682 void intel_modeset_disable(struct drm_device *dev)
3683 {
3684         struct drm_crtc *crtc;
3685
3686         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3687                 if (crtc->enabled)
3688                         intel_crtc_disable(crtc);
3689         }
3690 }
3691
3692 void intel_encoder_noop(struct drm_encoder *encoder)
3693 {
3694 }
3695
3696 void intel_encoder_destroy(struct drm_encoder *encoder)
3697 {
3698         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3699
3700         drm_encoder_cleanup(encoder);
3701         kfree(intel_encoder);
3702 }
3703
3704 /* Simple dpms helper for encodres with just one connector, no cloning and only
3705  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3706  * state of the entire output pipe. */
3707 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3708 {
3709         if (mode == DRM_MODE_DPMS_ON) {
3710                 encoder->connectors_active = true;
3711
3712                 intel_crtc_update_dpms(encoder->base.crtc);
3713         } else {
3714                 encoder->connectors_active = false;
3715
3716                 intel_crtc_update_dpms(encoder->base.crtc);
3717         }
3718 }
3719
3720 /* Cross check the actual hw state with our own modeset state tracking (and it's
3721  * internal consistency). */
3722 static void intel_connector_check_state(struct intel_connector *connector)
3723 {
3724         if (connector->get_hw_state(connector)) {
3725                 struct intel_encoder *encoder = connector->encoder;
3726                 struct drm_crtc *crtc;
3727                 bool encoder_enabled;
3728                 enum pipe pipe;
3729
3730                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3731                               connector->base.base.id,
3732                               drm_get_connector_name(&connector->base));
3733
3734                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3735                      "wrong connector dpms state\n");
3736                 WARN(connector->base.encoder != &encoder->base,
3737                      "active connector not linked to encoder\n");
3738                 WARN(!encoder->connectors_active,
3739                      "encoder->connectors_active not set\n");
3740
3741                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3742                 WARN(!encoder_enabled, "encoder not enabled\n");
3743                 if (WARN_ON(!encoder->base.crtc))
3744                         return;
3745
3746                 crtc = encoder->base.crtc;
3747
3748                 WARN(!crtc->enabled, "crtc not enabled\n");
3749                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3750                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3751                      "encoder active on the wrong pipe\n");
3752         }
3753 }
3754
3755 /* Even simpler default implementation, if there's really no special case to
3756  * consider. */
3757 void intel_connector_dpms(struct drm_connector *connector, int mode)
3758 {
3759         struct intel_encoder *encoder = intel_attached_encoder(connector);
3760
3761         /* All the simple cases only support two dpms states. */
3762         if (mode != DRM_MODE_DPMS_ON)
3763                 mode = DRM_MODE_DPMS_OFF;
3764
3765         if (mode == connector->dpms)
3766                 return;
3767
3768         connector->dpms = mode;
3769
3770         /* Only need to change hw state when actually enabled */
3771         if (encoder->base.crtc)
3772                 intel_encoder_dpms(encoder, mode);
3773         else
3774                 WARN_ON(encoder->connectors_active != false);
3775
3776         intel_modeset_check_state(connector->dev);
3777 }
3778
3779 /* Simple connector->get_hw_state implementation for encoders that support only
3780  * one connector and no cloning and hence the encoder state determines the state
3781  * of the connector. */
3782 bool intel_connector_get_hw_state(struct intel_connector *connector)
3783 {
3784         enum pipe pipe = 0;
3785         struct intel_encoder *encoder = connector->encoder;
3786
3787         return encoder->get_hw_state(encoder, &pipe);
3788 }
3789
3790 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3791                                   const struct drm_display_mode *mode,
3792                                   struct drm_display_mode *adjusted_mode)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795
3796         if (HAS_PCH_SPLIT(dev)) {
3797                 /* FDI link clock is fixed at 2.7G */
3798                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3799                         return false;
3800         }
3801
3802         /* All interlaced capable intel hw wants timings in frames. Note though
3803          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3804          * timings, so we need to be careful not to clobber these.*/
3805         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3806                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3807
3808         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3809          * with a hsync front porch of 0.
3810          */
3811         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3812                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3813                 return false;
3814
3815         return true;
3816 }
3817
3818 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3819 {
3820         return 400000; /* FIXME */
3821 }
3822
3823 static int i945_get_display_clock_speed(struct drm_device *dev)
3824 {
3825         return 400000;
3826 }
3827
3828 static int i915_get_display_clock_speed(struct drm_device *dev)
3829 {
3830         return 333000;
3831 }
3832
3833 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3834 {
3835         return 200000;
3836 }
3837
3838 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3839 {
3840         u16 gcfgc = 0;
3841
3842         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3843
3844         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3845                 return 133000;
3846         else {
3847                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3848                 case GC_DISPLAY_CLOCK_333_MHZ:
3849                         return 333000;
3850                 default:
3851                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3852                         return 190000;
3853                 }
3854         }
3855 }
3856
3857 static int i865_get_display_clock_speed(struct drm_device *dev)
3858 {
3859         return 266000;
3860 }
3861
3862 static int i855_get_display_clock_speed(struct drm_device *dev)
3863 {
3864         u16 hpllcc = 0;
3865         /* Assume that the hardware is in the high speed state.  This
3866          * should be the default.
3867          */
3868         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3869         case GC_CLOCK_133_200:
3870         case GC_CLOCK_100_200:
3871                 return 200000;
3872         case GC_CLOCK_166_250:
3873                 return 250000;
3874         case GC_CLOCK_100_133:
3875                 return 133000;
3876         }
3877
3878         /* Shouldn't happen */
3879         return 0;
3880 }
3881
3882 static int i830_get_display_clock_speed(struct drm_device *dev)
3883 {
3884         return 133000;
3885 }
3886
3887 struct fdi_m_n {
3888         u32        tu;
3889         u32        gmch_m;
3890         u32        gmch_n;
3891         u32        link_m;
3892         u32        link_n;
3893 };
3894
3895 static void
3896 fdi_reduce_ratio(u32 *num, u32 *den)
3897 {
3898         while (*num > 0xffffff || *den > 0xffffff) {
3899                 *num >>= 1;
3900                 *den >>= 1;
3901         }
3902 }
3903
3904 static void
3905 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3906                      int link_clock, struct fdi_m_n *m_n)
3907 {
3908         m_n->tu = 64; /* default size */
3909
3910         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3911         m_n->gmch_m = bits_per_pixel * pixel_clock;
3912         m_n->gmch_n = link_clock * nlanes * 8;
3913         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3914
3915         m_n->link_m = pixel_clock;
3916         m_n->link_n = link_clock;
3917         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3918 }
3919
3920 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3921 {
3922         if (i915_panel_use_ssc >= 0)
3923                 return i915_panel_use_ssc != 0;
3924         return dev_priv->lvds_use_ssc
3925                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3926 }
3927
3928 /**
3929  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3930  * @crtc: CRTC structure
3931  * @mode: requested mode
3932  *
3933  * A pipe may be connected to one or more outputs.  Based on the depth of the
3934  * attached framebuffer, choose a good color depth to use on the pipe.
3935  *
3936  * If possible, match the pipe depth to the fb depth.  In some cases, this
3937  * isn't ideal, because the connected output supports a lesser or restricted
3938  * set of depths.  Resolve that here:
3939  *    LVDS typically supports only 6bpc, so clamp down in that case
3940  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3941  *    Displays may support a restricted set as well, check EDID and clamp as
3942  *      appropriate.
3943  *    DP may want to dither down to 6bpc to fit larger modes
3944  *
3945  * RETURNS:
3946  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3947  * true if they don't match).
3948  */
3949 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3950                                          struct drm_framebuffer *fb,
3951                                          unsigned int *pipe_bpp,
3952                                          struct drm_display_mode *mode)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955         struct drm_i915_private *dev_priv = dev->dev_private;
3956         struct drm_connector *connector;
3957         struct intel_encoder *intel_encoder;
3958         unsigned int display_bpc = UINT_MAX, bpc;
3959
3960         /* Walk the encoders & connectors on this crtc, get min bpc */
3961         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3962
3963                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3964                         unsigned int lvds_bpc;
3965
3966                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3967                             LVDS_A3_POWER_UP)
3968                                 lvds_bpc = 8;
3969                         else
3970                                 lvds_bpc = 6;
3971
3972                         if (lvds_bpc < display_bpc) {
3973                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3974                                 display_bpc = lvds_bpc;
3975                         }
3976                         continue;
3977                 }
3978
3979                 /* Not one of the known troublemakers, check the EDID */
3980                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3981                                     head) {
3982                         if (connector->encoder != &intel_encoder->base)
3983                                 continue;
3984
3985                         /* Don't use an invalid EDID bpc value */
3986                         if (connector->display_info.bpc &&
3987                             connector->display_info.bpc < display_bpc) {
3988                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3989                                 display_bpc = connector->display_info.bpc;
3990                         }
3991                 }
3992
3993                 /*
3994                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3995                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3996                  */
3997                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3998                         if (display_bpc > 8 && display_bpc < 12) {
3999                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4000                                 display_bpc = 12;
4001                         } else {
4002                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4003                                 display_bpc = 8;
4004                         }
4005                 }
4006         }
4007
4008         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4009                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4010                 display_bpc = 6;
4011         }
4012
4013         /*
4014          * We could just drive the pipe at the highest bpc all the time and
4015          * enable dithering as needed, but that costs bandwidth.  So choose
4016          * the minimum value that expresses the full color range of the fb but
4017          * also stays within the max display bpc discovered above.
4018          */
4019
4020         switch (fb->depth) {
4021         case 8:
4022                 bpc = 8; /* since we go through a colormap */
4023                 break;
4024         case 15:
4025         case 16:
4026                 bpc = 6; /* min is 18bpp */
4027                 break;
4028         case 24:
4029                 bpc = 8;
4030                 break;
4031         case 30:
4032                 bpc = 10;
4033                 break;
4034         case 48:
4035                 bpc = 12;
4036                 break;
4037         default:
4038                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4039                 bpc = min((unsigned int)8, display_bpc);
4040                 break;
4041         }
4042
4043         display_bpc = min(display_bpc, bpc);
4044
4045         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4046                       bpc, display_bpc);
4047
4048         *pipe_bpp = display_bpc * 3;
4049
4050         return display_bpc != bpc;
4051 }
4052
4053 static int vlv_get_refclk(struct drm_crtc *crtc)
4054 {
4055         struct drm_device *dev = crtc->dev;
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         int refclk = 27000; /* for DP & HDMI */
4058
4059         return 100000; /* only one validated so far */
4060
4061         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4062                 refclk = 96000;
4063         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4064                 if (intel_panel_use_ssc(dev_priv))
4065                         refclk = 100000;
4066                 else
4067                         refclk = 96000;
4068         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4069                 refclk = 100000;
4070         }
4071
4072         return refclk;
4073 }
4074
4075 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4076 {
4077         struct drm_device *dev = crtc->dev;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         int refclk;
4080
4081         if (IS_VALLEYVIEW(dev)) {
4082                 refclk = vlv_get_refclk(crtc);
4083         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4084             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4085                 refclk = dev_priv->lvds_ssc_freq * 1000;
4086                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4087                               refclk / 1000);
4088         } else if (!IS_GEN2(dev)) {
4089                 refclk = 96000;
4090         } else {
4091                 refclk = 48000;
4092         }
4093
4094         return refclk;
4095 }
4096
4097 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4098                                       intel_clock_t *clock)
4099 {
4100         /* SDVO TV has fixed PLL values depend on its clock range,
4101            this mirrors vbios setting. */
4102         if (adjusted_mode->clock >= 100000
4103             && adjusted_mode->clock < 140500) {
4104                 clock->p1 = 2;
4105                 clock->p2 = 10;
4106                 clock->n = 3;
4107                 clock->m1 = 16;
4108                 clock->m2 = 8;
4109         } else if (adjusted_mode->clock >= 140500
4110                    && adjusted_mode->clock <= 200000) {
4111                 clock->p1 = 1;
4112                 clock->p2 = 10;
4113                 clock->n = 6;
4114                 clock->m1 = 12;
4115                 clock->m2 = 8;
4116         }
4117 }
4118
4119 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4120                                      intel_clock_t *clock,
4121                                      intel_clock_t *reduced_clock)
4122 {
4123         struct drm_device *dev = crtc->dev;
4124         struct drm_i915_private *dev_priv = dev->dev_private;
4125         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4126         int pipe = intel_crtc->pipe;
4127         u32 fp, fp2 = 0;
4128
4129         if (IS_PINEVIEW(dev)) {
4130                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4131                 if (reduced_clock)
4132                         fp2 = (1 << reduced_clock->n) << 16 |
4133                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4134         } else {
4135                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4136                 if (reduced_clock)
4137                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4138                                 reduced_clock->m2;
4139         }
4140
4141         I915_WRITE(FP0(pipe), fp);
4142
4143         intel_crtc->lowfreq_avail = false;
4144         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4145             reduced_clock && i915_powersave) {
4146                 I915_WRITE(FP1(pipe), fp2);
4147                 intel_crtc->lowfreq_avail = true;
4148         } else {
4149                 I915_WRITE(FP1(pipe), fp);
4150         }
4151 }
4152
4153 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4154                               struct drm_display_mode *adjusted_mode)
4155 {
4156         struct drm_device *dev = crtc->dev;
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159         int pipe = intel_crtc->pipe;
4160         u32 temp;
4161
4162         temp = I915_READ(LVDS);
4163         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4164         if (pipe == 1) {
4165                 temp |= LVDS_PIPEB_SELECT;
4166         } else {
4167                 temp &= ~LVDS_PIPEB_SELECT;
4168         }
4169         /* set the corresponsding LVDS_BORDER bit */
4170         temp |= dev_priv->lvds_border_bits;
4171         /* Set the B0-B3 data pairs corresponding to whether we're going to
4172          * set the DPLLs for dual-channel mode or not.
4173          */
4174         if (clock->p2 == 7)
4175                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4176         else
4177                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4178
4179         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4180          * appropriately here, but we need to look more thoroughly into how
4181          * panels behave in the two modes.
4182          */
4183         /* set the dithering flag on LVDS as needed */
4184         if (INTEL_INFO(dev)->gen >= 4) {
4185                 if (dev_priv->lvds_dither)
4186                         temp |= LVDS_ENABLE_DITHER;
4187                 else
4188                         temp &= ~LVDS_ENABLE_DITHER;
4189         }
4190         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4191         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4192                 temp |= LVDS_HSYNC_POLARITY;
4193         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4194                 temp |= LVDS_VSYNC_POLARITY;
4195         I915_WRITE(LVDS, temp);
4196 }
4197
4198 static void vlv_update_pll(struct drm_crtc *crtc,
4199                            struct drm_display_mode *mode,
4200                            struct drm_display_mode *adjusted_mode,
4201                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4202                            int num_connectors)
4203 {
4204         struct drm_device *dev = crtc->dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207         int pipe = intel_crtc->pipe;
4208         u32 dpll, mdiv, pdiv;
4209         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4210         bool is_sdvo;
4211         u32 temp;
4212
4213         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4214                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4215
4216         dpll = DPLL_VGA_MODE_DIS;
4217         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4218         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4219         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4220
4221         I915_WRITE(DPLL(pipe), dpll);
4222         POSTING_READ(DPLL(pipe));
4223
4224         bestn = clock->n;
4225         bestm1 = clock->m1;
4226         bestm2 = clock->m2;
4227         bestp1 = clock->p1;
4228         bestp2 = clock->p2;
4229
4230         /*
4231          * In Valleyview PLL and program lane counter registers are exposed
4232          * through DPIO interface
4233          */
4234         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4235         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4236         mdiv |= ((bestn << DPIO_N_SHIFT));
4237         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4238         mdiv |= (1 << DPIO_K_SHIFT);
4239         mdiv |= DPIO_ENABLE_CALIBRATION;
4240         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4241
4242         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4243
4244         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4245                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4246                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4247                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4248         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4249
4250         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4251
4252         dpll |= DPLL_VCO_ENABLE;
4253         I915_WRITE(DPLL(pipe), dpll);
4254         POSTING_READ(DPLL(pipe));
4255         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4256                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4257
4258         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4259
4260         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4261                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4262
4263         I915_WRITE(DPLL(pipe), dpll);
4264
4265         /* Wait for the clocks to stabilize. */
4266         POSTING_READ(DPLL(pipe));
4267         udelay(150);
4268
4269         temp = 0;
4270         if (is_sdvo) {
4271                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4272                 if (temp > 1)
4273                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4274                 else
4275                         temp = 0;
4276         }
4277         I915_WRITE(DPLL_MD(pipe), temp);
4278         POSTING_READ(DPLL_MD(pipe));
4279
4280         /* Now program lane control registers */
4281         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4282                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4283         {
4284                 temp = 0x1000C4;
4285                 if(pipe == 1)
4286                         temp |= (1 << 21);
4287                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4288         }
4289         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4290         {
4291                 temp = 0x1000C4;
4292                 if(pipe == 1)
4293                         temp |= (1 << 21);
4294                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4295         }
4296 }
4297
4298 static void i9xx_update_pll(struct drm_crtc *crtc,
4299                             struct drm_display_mode *mode,
4300                             struct drm_display_mode *adjusted_mode,
4301                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4302                             int num_connectors)
4303 {
4304         struct drm_device *dev = crtc->dev;
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307         int pipe = intel_crtc->pipe;
4308         u32 dpll;
4309         bool is_sdvo;
4310
4311         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4312
4313         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4314                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4315
4316         dpll = DPLL_VGA_MODE_DIS;
4317
4318         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4319                 dpll |= DPLLB_MODE_LVDS;
4320         else
4321                 dpll |= DPLLB_MODE_DAC_SERIAL;
4322         if (is_sdvo) {
4323                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4324                 if (pixel_multiplier > 1) {
4325                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4326                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4327                 }
4328                 dpll |= DPLL_DVO_HIGH_SPEED;
4329         }
4330         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4331                 dpll |= DPLL_DVO_HIGH_SPEED;
4332
4333         /* compute bitmask from p1 value */
4334         if (IS_PINEVIEW(dev))
4335                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4336         else {
4337                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4338                 if (IS_G4X(dev) && reduced_clock)
4339                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4340         }
4341         switch (clock->p2) {
4342         case 5:
4343                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4344                 break;
4345         case 7:
4346                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4347                 break;
4348         case 10:
4349                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4350                 break;
4351         case 14:
4352                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4353                 break;
4354         }
4355         if (INTEL_INFO(dev)->gen >= 4)
4356                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4357
4358         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4359                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4360         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4361                 /* XXX: just matching BIOS for now */
4362                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4363                 dpll |= 3;
4364         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4365                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4366                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4367         else
4368                 dpll |= PLL_REF_INPUT_DREFCLK;
4369
4370         dpll |= DPLL_VCO_ENABLE;
4371         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4372         POSTING_READ(DPLL(pipe));
4373         udelay(150);
4374
4375         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4376          * This is an exception to the general rule that mode_set doesn't turn
4377          * things on.
4378          */
4379         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4380                 intel_update_lvds(crtc, clock, adjusted_mode);
4381
4382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4383                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4384
4385         I915_WRITE(DPLL(pipe), dpll);
4386
4387         /* Wait for the clocks to stabilize. */
4388         POSTING_READ(DPLL(pipe));
4389         udelay(150);
4390
4391         if (INTEL_INFO(dev)->gen >= 4) {
4392                 u32 temp = 0;
4393                 if (is_sdvo) {
4394                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4395                         if (temp > 1)
4396                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4397                         else
4398                                 temp = 0;
4399                 }
4400                 I915_WRITE(DPLL_MD(pipe), temp);
4401         } else {
4402                 /* The pixel multiplier can only be updated once the
4403                  * DPLL is enabled and the clocks are stable.
4404                  *
4405                  * So write it again.
4406                  */
4407                 I915_WRITE(DPLL(pipe), dpll);
4408         }
4409 }
4410
4411 static void i8xx_update_pll(struct drm_crtc *crtc,
4412                             struct drm_display_mode *adjusted_mode,
4413                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4414                             int num_connectors)
4415 {
4416         struct drm_device *dev = crtc->dev;
4417         struct drm_i915_private *dev_priv = dev->dev_private;
4418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419         int pipe = intel_crtc->pipe;
4420         u32 dpll;
4421
4422         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4423
4424         dpll = DPLL_VGA_MODE_DIS;
4425
4426         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4427                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4428         } else {
4429                 if (clock->p1 == 2)
4430                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4431                 else
4432                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4433                 if (clock->p2 == 4)
4434                         dpll |= PLL_P2_DIVIDE_BY_4;
4435         }
4436
4437         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4438                 /* XXX: just matching BIOS for now */
4439                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4440                 dpll |= 3;
4441         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4442                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4443                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4444         else
4445                 dpll |= PLL_REF_INPUT_DREFCLK;
4446
4447         dpll |= DPLL_VCO_ENABLE;
4448         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4449         POSTING_READ(DPLL(pipe));
4450         udelay(150);
4451
4452         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4453          * This is an exception to the general rule that mode_set doesn't turn
4454          * things on.
4455          */
4456         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4457                 intel_update_lvds(crtc, clock, adjusted_mode);
4458
4459         I915_WRITE(DPLL(pipe), dpll);
4460
4461         /* Wait for the clocks to stabilize. */
4462         POSTING_READ(DPLL(pipe));
4463         udelay(150);
4464
4465         /* The pixel multiplier can only be updated once the
4466          * DPLL is enabled and the clocks are stable.
4467          *
4468          * So write it again.
4469          */
4470         I915_WRITE(DPLL(pipe), dpll);
4471 }
4472
4473 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4474                                    struct drm_display_mode *mode,
4475                                    struct drm_display_mode *adjusted_mode)
4476 {
4477         struct drm_device *dev = intel_crtc->base.dev;
4478         struct drm_i915_private *dev_priv = dev->dev_private;
4479         enum pipe pipe = intel_crtc->pipe;
4480         uint32_t vsyncshift;
4481
4482         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4483                 /* the chip adds 2 halflines automatically */
4484                 adjusted_mode->crtc_vtotal -= 1;
4485                 adjusted_mode->crtc_vblank_end -= 1;
4486                 vsyncshift = adjusted_mode->crtc_hsync_start
4487                              - adjusted_mode->crtc_htotal / 2;
4488         } else {
4489                 vsyncshift = 0;
4490         }
4491
4492         if (INTEL_INFO(dev)->gen > 3)
4493                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4494
4495         I915_WRITE(HTOTAL(pipe),
4496                    (adjusted_mode->crtc_hdisplay - 1) |
4497                    ((adjusted_mode->crtc_htotal - 1) << 16));
4498         I915_WRITE(HBLANK(pipe),
4499                    (adjusted_mode->crtc_hblank_start - 1) |
4500                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4501         I915_WRITE(HSYNC(pipe),
4502                    (adjusted_mode->crtc_hsync_start - 1) |
4503                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4504
4505         I915_WRITE(VTOTAL(pipe),
4506                    (adjusted_mode->crtc_vdisplay - 1) |
4507                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4508         I915_WRITE(VBLANK(pipe),
4509                    (adjusted_mode->crtc_vblank_start - 1) |
4510                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4511         I915_WRITE(VSYNC(pipe),
4512                    (adjusted_mode->crtc_vsync_start - 1) |
4513                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4514
4515         /* pipesrc controls the size that is scaled from, which should
4516          * always be the user's requested size.
4517          */
4518         I915_WRITE(PIPESRC(pipe),
4519                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4520 }
4521
4522 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4523                               struct drm_display_mode *mode,
4524                               struct drm_display_mode *adjusted_mode,
4525                               int x, int y,
4526                               struct drm_framebuffer *fb)
4527 {
4528         struct drm_device *dev = crtc->dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         int pipe = intel_crtc->pipe;
4532         int plane = intel_crtc->plane;
4533         int refclk, num_connectors = 0;
4534         intel_clock_t clock, reduced_clock;
4535         u32 dspcntr, pipeconf;
4536         bool ok, has_reduced_clock = false, is_sdvo = false;
4537         bool is_lvds = false, is_tv = false, is_dp = false;
4538         struct intel_encoder *encoder;
4539         const intel_limit_t *limit;
4540         int ret;
4541
4542         for_each_encoder_on_crtc(dev, crtc, encoder) {
4543                 switch (encoder->type) {
4544                 case INTEL_OUTPUT_LVDS:
4545                         is_lvds = true;
4546                         break;
4547                 case INTEL_OUTPUT_SDVO:
4548                 case INTEL_OUTPUT_HDMI:
4549                         is_sdvo = true;
4550                         if (encoder->needs_tv_clock)
4551                                 is_tv = true;
4552                         break;
4553                 case INTEL_OUTPUT_TVOUT:
4554                         is_tv = true;
4555                         break;
4556                 case INTEL_OUTPUT_DISPLAYPORT:
4557                         is_dp = true;
4558                         break;
4559                 }
4560
4561                 num_connectors++;
4562         }
4563
4564         refclk = i9xx_get_refclk(crtc, num_connectors);
4565
4566         /*
4567          * Returns a set of divisors for the desired target clock with the given
4568          * refclk, or FALSE.  The returned values represent the clock equation:
4569          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4570          */
4571         limit = intel_limit(crtc, refclk);
4572         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4573                              &clock);
4574         if (!ok) {
4575                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4576                 return -EINVAL;
4577         }
4578
4579         /* Ensure that the cursor is valid for the new mode before changing... */
4580         intel_crtc_update_cursor(crtc, true);
4581
4582         if (is_lvds && dev_priv->lvds_downclock_avail) {
4583                 /*
4584                  * Ensure we match the reduced clock's P to the target clock.
4585                  * If the clocks don't match, we can't switch the display clock
4586                  * by using the FP0/FP1. In such case we will disable the LVDS
4587                  * downclock feature.
4588                 */
4589                 has_reduced_clock = limit->find_pll(limit, crtc,
4590                                                     dev_priv->lvds_downclock,
4591                                                     refclk,
4592                                                     &clock,
4593                                                     &reduced_clock);
4594         }
4595
4596         if (is_sdvo && is_tv)
4597                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4598
4599         if (IS_GEN2(dev))
4600                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4601                                 has_reduced_clock ? &reduced_clock : NULL,
4602                                 num_connectors);
4603         else if (IS_VALLEYVIEW(dev))
4604                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4605                                 has_reduced_clock ? &reduced_clock : NULL,
4606                                 num_connectors);
4607         else
4608                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4609                                 has_reduced_clock ? &reduced_clock : NULL,
4610                                 num_connectors);
4611
4612         /* setup pipeconf */
4613         pipeconf = I915_READ(PIPECONF(pipe));
4614
4615         /* Set up the display plane register */
4616         dspcntr = DISPPLANE_GAMMA_ENABLE;
4617
4618         if (pipe == 0)
4619                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4620         else
4621                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4622
4623         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4624                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4625                  * core speed.
4626                  *
4627                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4628                  * pipe == 0 check?
4629                  */
4630                 if (mode->clock >
4631                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4632                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4633                 else
4634                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4635         }
4636
4637         /* default to 8bpc */
4638         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4639         if (is_dp) {
4640                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4641                         pipeconf |= PIPECONF_BPP_6 |
4642                                     PIPECONF_DITHER_EN |
4643                                     PIPECONF_DITHER_TYPE_SP;
4644                 }
4645         }
4646
4647         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4648                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4649                         pipeconf |= PIPECONF_BPP_6 |
4650                                         PIPECONF_ENABLE |
4651                                         I965_PIPECONF_ACTIVE;
4652                 }
4653         }
4654
4655         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4656         drm_mode_debug_printmodeline(mode);
4657
4658         if (HAS_PIPE_CXSR(dev)) {
4659                 if (intel_crtc->lowfreq_avail) {
4660                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4661                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4662                 } else {
4663                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4664                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4665                 }
4666         }
4667
4668         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4669         if (!IS_GEN2(dev) &&
4670             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4671                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4672         else
4673                 pipeconf |= PIPECONF_PROGRESSIVE;
4674
4675         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4676
4677         /* pipesrc and dspsize control the size that is scaled from,
4678          * which should always be the user's requested size.
4679          */
4680         I915_WRITE(DSPSIZE(plane),
4681                    ((mode->vdisplay - 1) << 16) |
4682                    (mode->hdisplay - 1));
4683         I915_WRITE(DSPPOS(plane), 0);
4684
4685         I915_WRITE(PIPECONF(pipe), pipeconf);
4686         POSTING_READ(PIPECONF(pipe));
4687         intel_enable_pipe(dev_priv, pipe, false);
4688
4689         intel_wait_for_vblank(dev, pipe);
4690
4691         I915_WRITE(DSPCNTR(plane), dspcntr);
4692         POSTING_READ(DSPCNTR(plane));
4693
4694         ret = intel_pipe_set_base(crtc, x, y, fb);
4695
4696         intel_update_watermarks(dev);
4697
4698         return ret;
4699 }
4700
4701 /*
4702  * Initialize reference clocks when the driver loads
4703  */
4704 void ironlake_init_pch_refclk(struct drm_device *dev)
4705 {
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         struct drm_mode_config *mode_config = &dev->mode_config;
4708         struct intel_encoder *encoder;
4709         u32 temp;
4710         bool has_lvds = false;
4711         bool has_cpu_edp = false;
4712         bool has_pch_edp = false;
4713         bool has_panel = false;
4714         bool has_ck505 = false;
4715         bool can_ssc = false;
4716
4717         /* We need to take the global config into account */
4718         list_for_each_entry(encoder, &mode_config->encoder_list,
4719                             base.head) {
4720                 switch (encoder->type) {
4721                 case INTEL_OUTPUT_LVDS:
4722                         has_panel = true;
4723                         has_lvds = true;
4724                         break;
4725                 case INTEL_OUTPUT_EDP:
4726                         has_panel = true;
4727                         if (intel_encoder_is_pch_edp(&encoder->base))
4728                                 has_pch_edp = true;
4729                         else
4730                                 has_cpu_edp = true;
4731                         break;
4732                 }
4733         }
4734
4735         if (HAS_PCH_IBX(dev)) {
4736                 has_ck505 = dev_priv->display_clock_mode;
4737                 can_ssc = has_ck505;
4738         } else {
4739                 has_ck505 = false;
4740                 can_ssc = true;
4741         }
4742
4743         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4744                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4745                       has_ck505);
4746
4747         /* Ironlake: try to setup display ref clock before DPLL
4748          * enabling. This is only under driver's control after
4749          * PCH B stepping, previous chipset stepping should be
4750          * ignoring this setting.
4751          */
4752         temp = I915_READ(PCH_DREF_CONTROL);
4753         /* Always enable nonspread source */
4754         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4755
4756         if (has_ck505)
4757                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4758         else
4759                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4760
4761         if (has_panel) {
4762                 temp &= ~DREF_SSC_SOURCE_MASK;
4763                 temp |= DREF_SSC_SOURCE_ENABLE;
4764
4765                 /* SSC must be turned on before enabling the CPU output  */
4766                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4767                         DRM_DEBUG_KMS("Using SSC on panel\n");
4768                         temp |= DREF_SSC1_ENABLE;
4769                 } else
4770                         temp &= ~DREF_SSC1_ENABLE;
4771
4772                 /* Get SSC going before enabling the outputs */
4773                 I915_WRITE(PCH_DREF_CONTROL, temp);
4774                 POSTING_READ(PCH_DREF_CONTROL);
4775                 udelay(200);
4776
4777                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4778
4779                 /* Enable CPU source on CPU attached eDP */
4780                 if (has_cpu_edp) {
4781                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4782                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4783                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4784                         }
4785                         else
4786                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4787                 } else
4788                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4789
4790                 I915_WRITE(PCH_DREF_CONTROL, temp);
4791                 POSTING_READ(PCH_DREF_CONTROL);
4792                 udelay(200);
4793         } else {
4794                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4795
4796                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4797
4798                 /* Turn off CPU output */
4799                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4800
4801                 I915_WRITE(PCH_DREF_CONTROL, temp);
4802                 POSTING_READ(PCH_DREF_CONTROL);
4803                 udelay(200);
4804
4805                 /* Turn off the SSC source */
4806                 temp &= ~DREF_SSC_SOURCE_MASK;
4807                 temp |= DREF_SSC_SOURCE_DISABLE;
4808
4809                 /* Turn off SSC1 */
4810                 temp &= ~ DREF_SSC1_ENABLE;
4811
4812                 I915_WRITE(PCH_DREF_CONTROL, temp);
4813                 POSTING_READ(PCH_DREF_CONTROL);
4814                 udelay(200);
4815         }
4816 }
4817
4818 static int ironlake_get_refclk(struct drm_crtc *crtc)
4819 {
4820         struct drm_device *dev = crtc->dev;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822         struct intel_encoder *encoder;
4823         struct intel_encoder *edp_encoder = NULL;
4824         int num_connectors = 0;
4825         bool is_lvds = false;
4826
4827         for_each_encoder_on_crtc(dev, crtc, encoder) {
4828                 switch (encoder->type) {
4829                 case INTEL_OUTPUT_LVDS:
4830                         is_lvds = true;
4831                         break;
4832                 case INTEL_OUTPUT_EDP:
4833                         edp_encoder = encoder;
4834                         break;
4835                 }
4836                 num_connectors++;
4837         }
4838
4839         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4840                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4841                               dev_priv->lvds_ssc_freq);
4842                 return dev_priv->lvds_ssc_freq * 1000;
4843         }
4844
4845         return 120000;
4846 }
4847
4848 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4849                                   struct drm_display_mode *adjusted_mode,
4850                                   bool dither)
4851 {
4852         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854         int pipe = intel_crtc->pipe;
4855         uint32_t val;
4856
4857         val = I915_READ(PIPECONF(pipe));
4858
4859         val &= ~PIPE_BPC_MASK;
4860         switch (intel_crtc->bpp) {
4861         case 18:
4862                 val |= PIPE_6BPC;
4863                 break;
4864         case 24:
4865                 val |= PIPE_8BPC;
4866                 break;
4867         case 30:
4868                 val |= PIPE_10BPC;
4869                 break;
4870         case 36:
4871                 val |= PIPE_12BPC;
4872                 break;
4873         default:
4874                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4875                 BUG();
4876         }
4877
4878         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4879         if (dither)
4880                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4881
4882         val &= ~PIPECONF_INTERLACE_MASK;
4883         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4884                 val |= PIPECONF_INTERLACED_ILK;
4885         else
4886                 val |= PIPECONF_PROGRESSIVE;
4887
4888         I915_WRITE(PIPECONF(pipe), val);
4889         POSTING_READ(PIPECONF(pipe));
4890 }
4891
4892 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4893                                  struct drm_display_mode *adjusted_mode,
4894                                  bool dither)
4895 {
4896         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898         int pipe = intel_crtc->pipe;
4899         uint32_t val;
4900
4901         val = I915_READ(PIPECONF(pipe));
4902
4903         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4904         if (dither)
4905                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4906
4907         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4908         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4909                 val |= PIPECONF_INTERLACED_ILK;
4910         else
4911                 val |= PIPECONF_PROGRESSIVE;
4912
4913         I915_WRITE(PIPECONF(pipe), val);
4914         POSTING_READ(PIPECONF(pipe));
4915 }
4916
4917 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4918                                     struct drm_display_mode *adjusted_mode,
4919                                     intel_clock_t *clock,
4920                                     bool *has_reduced_clock,
4921                                     intel_clock_t *reduced_clock)
4922 {
4923         struct drm_device *dev = crtc->dev;
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925         struct intel_encoder *intel_encoder;
4926         int refclk;
4927         const intel_limit_t *limit;
4928         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4929
4930         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4931                 switch (intel_encoder->type) {
4932                 case INTEL_OUTPUT_LVDS:
4933                         is_lvds = true;
4934                         break;
4935                 case INTEL_OUTPUT_SDVO:
4936                 case INTEL_OUTPUT_HDMI:
4937                         is_sdvo = true;
4938                         if (intel_encoder->needs_tv_clock)
4939                                 is_tv = true;
4940                         break;
4941                 case INTEL_OUTPUT_TVOUT:
4942                         is_tv = true;
4943                         break;
4944                 }
4945         }
4946
4947         refclk = ironlake_get_refclk(crtc);
4948
4949         /*
4950          * Returns a set of divisors for the desired target clock with the given
4951          * refclk, or FALSE.  The returned values represent the clock equation:
4952          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4953          */
4954         limit = intel_limit(crtc, refclk);
4955         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4956                               clock);
4957         if (!ret)
4958                 return false;
4959
4960         if (is_lvds && dev_priv->lvds_downclock_avail) {
4961                 /*
4962                  * Ensure we match the reduced clock's P to the target clock.
4963                  * If the clocks don't match, we can't switch the display clock
4964                  * by using the FP0/FP1. In such case we will disable the LVDS
4965                  * downclock feature.
4966                 */
4967                 *has_reduced_clock = limit->find_pll(limit, crtc,
4968                                                      dev_priv->lvds_downclock,
4969                                                      refclk,
4970                                                      clock,
4971                                                      reduced_clock);
4972         }
4973
4974         if (is_sdvo && is_tv)
4975                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4976
4977         return true;
4978 }
4979
4980 static void ironlake_set_m_n(struct drm_crtc *crtc,
4981                              struct drm_display_mode *mode,
4982                              struct drm_display_mode *adjusted_mode)
4983 {
4984         struct drm_device *dev = crtc->dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4987         enum pipe pipe = intel_crtc->pipe;
4988         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4989         struct fdi_m_n m_n = {0};
4990         int target_clock, pixel_multiplier, lane, link_bw;
4991         bool is_dp = false, is_cpu_edp = false;
4992
4993         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4994                 switch (intel_encoder->type) {
4995                 case INTEL_OUTPUT_DISPLAYPORT:
4996                         is_dp = true;
4997                         break;
4998                 case INTEL_OUTPUT_EDP:
4999                         is_dp = true;
5000                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5001                                 is_cpu_edp = true;
5002                         edp_encoder = intel_encoder;
5003                         break;
5004                 }
5005         }
5006
5007         /* FDI link */
5008         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5009         lane = 0;
5010         /* CPU eDP doesn't require FDI link, so just set DP M/N
5011            according to current link config */
5012         if (is_cpu_edp) {
5013                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5014         } else {
5015                 /* FDI is a binary signal running at ~2.7GHz, encoding
5016                  * each output octet as 10 bits. The actual frequency
5017                  * is stored as a divider into a 100MHz clock, and the
5018                  * mode pixel clock is stored in units of 1KHz.
5019                  * Hence the bw of each lane in terms of the mode signal
5020                  * is:
5021                  */
5022                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5023         }
5024
5025         /* [e]DP over FDI requires target mode clock instead of link clock. */
5026         if (edp_encoder)
5027                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5028         else if (is_dp)
5029                 target_clock = mode->clock;
5030         else
5031                 target_clock = adjusted_mode->clock;
5032
5033         if (!lane) {
5034                 /*
5035                  * Account for spread spectrum to avoid
5036                  * oversubscribing the link. Max center spread
5037                  * is 2.5%; use 5% for safety's sake.
5038                  */
5039                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5040                 lane = bps / (link_bw * 8) + 1;
5041         }
5042
5043         intel_crtc->fdi_lanes = lane;
5044
5045         if (pixel_multiplier > 1)
5046                 link_bw *= pixel_multiplier;
5047         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5048                              &m_n);
5049
5050         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5051         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5052         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5053         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5054 }
5055
5056 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5057                                       struct drm_display_mode *adjusted_mode,
5058                                       intel_clock_t *clock, u32 fp)
5059 {
5060         struct drm_crtc *crtc = &intel_crtc->base;
5061         struct drm_device *dev = crtc->dev;
5062         struct drm_i915_private *dev_priv = dev->dev_private;
5063         struct intel_encoder *intel_encoder;
5064         uint32_t dpll;
5065         int factor, pixel_multiplier, num_connectors = 0;
5066         bool is_lvds = false, is_sdvo = false, is_tv = false;
5067         bool is_dp = false, is_cpu_edp = false;
5068
5069         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5070                 switch (intel_encoder->type) {
5071                 case INTEL_OUTPUT_LVDS:
5072                         is_lvds = true;
5073                         break;
5074                 case INTEL_OUTPUT_SDVO:
5075                 case INTEL_OUTPUT_HDMI:
5076                         is_sdvo = true;
5077                         if (intel_encoder->needs_tv_clock)
5078                                 is_tv = true;
5079                         break;
5080                 case INTEL_OUTPUT_TVOUT:
5081                         is_tv = true;
5082                         break;
5083                 case INTEL_OUTPUT_DISPLAYPORT:
5084                         is_dp = true;
5085                         break;
5086                 case INTEL_OUTPUT_EDP:
5087                         is_dp = true;
5088                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5089                                 is_cpu_edp = true;
5090                         break;
5091                 }
5092
5093                 num_connectors++;
5094         }
5095
5096         /* Enable autotuning of the PLL clock (if permissible) */
5097         factor = 21;
5098         if (is_lvds) {
5099                 if ((intel_panel_use_ssc(dev_priv) &&
5100                      dev_priv->lvds_ssc_freq == 100) ||
5101                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5102                         factor = 25;
5103         } else if (is_sdvo && is_tv)
5104                 factor = 20;
5105
5106         if (clock->m < factor * clock->n)
5107                 fp |= FP_CB_TUNE;
5108
5109         dpll = 0;
5110
5111         if (is_lvds)
5112                 dpll |= DPLLB_MODE_LVDS;
5113         else
5114                 dpll |= DPLLB_MODE_DAC_SERIAL;
5115         if (is_sdvo) {
5116                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5117                 if (pixel_multiplier > 1) {
5118                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5119                 }
5120                 dpll |= DPLL_DVO_HIGH_SPEED;
5121         }
5122         if (is_dp && !is_cpu_edp)
5123                 dpll |= DPLL_DVO_HIGH_SPEED;
5124
5125         /* compute bitmask from p1 value */
5126         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5127         /* also FPA1 */
5128         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5129
5130         switch (clock->p2) {
5131         case 5:
5132                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5133                 break;
5134         case 7:
5135                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5136                 break;
5137         case 10:
5138                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5139                 break;
5140         case 14:
5141                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5142                 break;
5143         }
5144
5145         if (is_sdvo && is_tv)
5146                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5147         else if (is_tv)
5148                 /* XXX: just matching BIOS for now */
5149                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5150                 dpll |= 3;
5151         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5152                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5153         else
5154                 dpll |= PLL_REF_INPUT_DREFCLK;
5155
5156         return dpll;
5157 }
5158
5159 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5160                                   struct drm_display_mode *mode,
5161                                   struct drm_display_mode *adjusted_mode,
5162                                   int x, int y,
5163                                   struct drm_framebuffer *fb)
5164 {
5165         struct drm_device *dev = crtc->dev;
5166         struct drm_i915_private *dev_priv = dev->dev_private;
5167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168         int pipe = intel_crtc->pipe;
5169         int plane = intel_crtc->plane;
5170         int num_connectors = 0;
5171         intel_clock_t clock, reduced_clock;
5172         u32 dpll, fp = 0, fp2 = 0;
5173         bool ok, has_reduced_clock = false;
5174         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5175         struct intel_encoder *encoder;
5176         u32 temp;
5177         int ret;
5178         bool dither;
5179
5180         for_each_encoder_on_crtc(dev, crtc, encoder) {
5181                 switch (encoder->type) {
5182                 case INTEL_OUTPUT_LVDS:
5183                         is_lvds = true;
5184                         break;
5185                 case INTEL_OUTPUT_DISPLAYPORT:
5186                         is_dp = true;
5187                         break;
5188                 case INTEL_OUTPUT_EDP:
5189                         is_dp = true;
5190                         if (!intel_encoder_is_pch_edp(&encoder->base))
5191                                 is_cpu_edp = true;
5192                         break;
5193                 }
5194
5195                 num_connectors++;
5196         }
5197
5198         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5199              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5200
5201         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5202                                      &has_reduced_clock, &reduced_clock);
5203         if (!ok) {
5204                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5205                 return -EINVAL;
5206         }
5207
5208         /* Ensure that the cursor is valid for the new mode before changing... */
5209         intel_crtc_update_cursor(crtc, true);
5210
5211         /* determine panel color depth */
5212         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5213         if (is_lvds && dev_priv->lvds_dither)
5214                 dither = true;
5215
5216         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5217         if (has_reduced_clock)
5218                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5219                         reduced_clock.m2;
5220
5221         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5222
5223         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5224         drm_mode_debug_printmodeline(mode);
5225
5226         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5227         if (!is_cpu_edp) {
5228                 struct intel_pch_pll *pll;
5229
5230                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5231                 if (pll == NULL) {
5232                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5233                                          pipe);
5234                         return -EINVAL;
5235                 }
5236         } else
5237                 intel_put_pch_pll(intel_crtc);
5238
5239         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5240          * This is an exception to the general rule that mode_set doesn't turn
5241          * things on.
5242          */
5243         if (is_lvds) {
5244                 temp = I915_READ(PCH_LVDS);
5245                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5246                 if (HAS_PCH_CPT(dev)) {
5247                         temp &= ~PORT_TRANS_SEL_MASK;
5248                         temp |= PORT_TRANS_SEL_CPT(pipe);
5249                 } else {
5250                         if (pipe == 1)
5251                                 temp |= LVDS_PIPEB_SELECT;
5252                         else
5253                                 temp &= ~LVDS_PIPEB_SELECT;
5254                 }
5255
5256                 /* set the corresponsding LVDS_BORDER bit */
5257                 temp |= dev_priv->lvds_border_bits;
5258                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5259                  * set the DPLLs for dual-channel mode or not.
5260                  */
5261                 if (clock.p2 == 7)
5262                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5263                 else
5264                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5265
5266                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5267                  * appropriately here, but we need to look more thoroughly into how
5268                  * panels behave in the two modes.
5269                  */
5270                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5271                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5272                         temp |= LVDS_HSYNC_POLARITY;
5273                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5274                         temp |= LVDS_VSYNC_POLARITY;
5275                 I915_WRITE(PCH_LVDS, temp);
5276         }
5277
5278         if (is_dp && !is_cpu_edp) {
5279                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5280         } else {
5281                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5282                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5283                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5284                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5285                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5286         }
5287
5288         if (intel_crtc->pch_pll) {
5289                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5290
5291                 /* Wait for the clocks to stabilize. */
5292                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5293                 udelay(150);
5294
5295                 /* The pixel multiplier can only be updated once the
5296                  * DPLL is enabled and the clocks are stable.
5297                  *
5298                  * So write it again.
5299                  */
5300                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5301         }
5302
5303         intel_crtc->lowfreq_avail = false;
5304         if (intel_crtc->pch_pll) {
5305                 if (is_lvds && has_reduced_clock && i915_powersave) {
5306                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5307                         intel_crtc->lowfreq_avail = true;
5308                 } else {
5309                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5310                 }
5311         }
5312
5313         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5314
5315         ironlake_set_m_n(crtc, mode, adjusted_mode);
5316
5317         if (is_cpu_edp)
5318                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5319
5320         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5321
5322         intel_wait_for_vblank(dev, pipe);
5323
5324         /* Set up the display plane register */
5325         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5326         POSTING_READ(DSPCNTR(plane));
5327
5328         ret = intel_pipe_set_base(crtc, x, y, fb);
5329
5330         intel_update_watermarks(dev);
5331
5332         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5333
5334         return ret;
5335 }
5336
5337 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5338                                  struct drm_display_mode *mode,
5339                                  struct drm_display_mode *adjusted_mode,
5340                                  int x, int y,
5341                                  struct drm_framebuffer *fb)
5342 {
5343         struct drm_device *dev = crtc->dev;
5344         struct drm_i915_private *dev_priv = dev->dev_private;
5345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5346         int pipe = intel_crtc->pipe;
5347         int plane = intel_crtc->plane;
5348         int num_connectors = 0;
5349         intel_clock_t clock, reduced_clock;
5350         u32 dpll = 0, fp = 0, fp2 = 0;
5351         bool ok, has_reduced_clock = false;
5352         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5353         struct intel_encoder *encoder;
5354         u32 temp;
5355         int ret;
5356         bool dither;
5357
5358         for_each_encoder_on_crtc(dev, crtc, encoder) {
5359                 switch (encoder->type) {
5360                 case INTEL_OUTPUT_LVDS:
5361                         is_lvds = true;
5362                         break;
5363                 case INTEL_OUTPUT_DISPLAYPORT:
5364                         is_dp = true;
5365                         break;
5366                 case INTEL_OUTPUT_EDP:
5367                         is_dp = true;
5368                         if (!intel_encoder_is_pch_edp(&encoder->base))
5369                                 is_cpu_edp = true;
5370                         break;
5371                 }
5372
5373                 num_connectors++;
5374         }
5375
5376         /* We are not sure yet this won't happen. */
5377         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5378              INTEL_PCH_TYPE(dev));
5379
5380         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5381              num_connectors, pipe_name(pipe));
5382
5383         WARN_ON(I915_READ(PIPECONF(pipe)) &
5384                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5385
5386         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5387
5388         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5389                 return -EINVAL;
5390
5391         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5392                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5393                                              &has_reduced_clock,
5394                                              &reduced_clock);
5395                 if (!ok) {
5396                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5397                         return -EINVAL;
5398                 }
5399         }
5400
5401         /* Ensure that the cursor is valid for the new mode before changing... */
5402         intel_crtc_update_cursor(crtc, true);
5403
5404         /* determine panel color depth */
5405         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5406         if (is_lvds && dev_priv->lvds_dither)
5407                 dither = true;
5408
5409         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5410         drm_mode_debug_printmodeline(mode);
5411
5412         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5413                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5414                 if (has_reduced_clock)
5415                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5416                               reduced_clock.m2;
5417
5418                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5419                                              fp);
5420
5421                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5422                  * own on pre-Haswell/LPT generation */
5423                 if (!is_cpu_edp) {
5424                         struct intel_pch_pll *pll;
5425
5426                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5427                         if (pll == NULL) {
5428                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5429                                                  pipe);
5430                                 return -EINVAL;
5431                         }
5432                 } else
5433                         intel_put_pch_pll(intel_crtc);
5434
5435                 /* The LVDS pin pair needs to be on before the DPLLs are
5436                  * enabled.  This is an exception to the general rule that
5437                  * mode_set doesn't turn things on.
5438                  */
5439                 if (is_lvds) {
5440                         temp = I915_READ(PCH_LVDS);
5441                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5442                         if (HAS_PCH_CPT(dev)) {
5443                                 temp &= ~PORT_TRANS_SEL_MASK;
5444                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5445                         } else {
5446                                 if (pipe == 1)
5447                                         temp |= LVDS_PIPEB_SELECT;
5448                                 else
5449                                         temp &= ~LVDS_PIPEB_SELECT;
5450                         }
5451
5452                         /* set the corresponsding LVDS_BORDER bit */
5453                         temp |= dev_priv->lvds_border_bits;
5454                         /* Set the B0-B3 data pairs corresponding to whether
5455                          * we're going to set the DPLLs for dual-channel mode or
5456                          * not.
5457                          */
5458                         if (clock.p2 == 7)
5459                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5460                         else
5461                                 temp &= ~(LVDS_B0B3_POWER_UP |
5462                                           LVDS_CLKB_POWER_UP);
5463
5464                         /* It would be nice to set 24 vs 18-bit mode
5465                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5466                          * look more thoroughly into how panels behave in the
5467                          * two modes.
5468                          */
5469                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5470                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5471                                 temp |= LVDS_HSYNC_POLARITY;
5472                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5473                                 temp |= LVDS_VSYNC_POLARITY;
5474                         I915_WRITE(PCH_LVDS, temp);
5475                 }
5476         }
5477
5478         if (is_dp && !is_cpu_edp) {
5479                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5480         } else {
5481                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5482                         /* For non-DP output, clear any trans DP clock recovery
5483                          * setting.*/
5484                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5485                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5486                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5487                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5488                 }
5489         }
5490
5491         intel_crtc->lowfreq_avail = false;
5492         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5493                 if (intel_crtc->pch_pll) {
5494                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5495
5496                         /* Wait for the clocks to stabilize. */
5497                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5498                         udelay(150);
5499
5500                         /* The pixel multiplier can only be updated once the
5501                          * DPLL is enabled and the clocks are stable.
5502                          *
5503                          * So write it again.
5504                          */
5505                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5506                 }
5507
5508                 if (intel_crtc->pch_pll) {
5509                         if (is_lvds && has_reduced_clock && i915_powersave) {
5510                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5511                                 intel_crtc->lowfreq_avail = true;
5512                         } else {
5513                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5514                         }
5515                 }
5516         }
5517
5518         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5519
5520         if (!is_dp || is_cpu_edp)
5521                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5522
5523         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5524                 if (is_cpu_edp)
5525                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5526
5527         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5528
5529         /* Set up the display plane register */
5530         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5531         POSTING_READ(DSPCNTR(plane));
5532
5533         ret = intel_pipe_set_base(crtc, x, y, fb);
5534
5535         intel_update_watermarks(dev);
5536
5537         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5538
5539         return ret;
5540 }
5541
5542 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5543                                struct drm_display_mode *mode,
5544                                struct drm_display_mode *adjusted_mode,
5545                                int x, int y,
5546                                struct drm_framebuffer *fb)
5547 {
5548         struct drm_device *dev = crtc->dev;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5551         int pipe = intel_crtc->pipe;
5552         int ret;
5553
5554         drm_vblank_pre_modeset(dev, pipe);
5555
5556         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5557                                               x, y, fb);
5558         drm_vblank_post_modeset(dev, pipe);
5559
5560         return ret;
5561 }
5562
5563 static bool intel_eld_uptodate(struct drm_connector *connector,
5564                                int reg_eldv, uint32_t bits_eldv,
5565                                int reg_elda, uint32_t bits_elda,
5566                                int reg_edid)
5567 {
5568         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5569         uint8_t *eld = connector->eld;
5570         uint32_t i;
5571
5572         i = I915_READ(reg_eldv);
5573         i &= bits_eldv;
5574
5575         if (!eld[0])
5576                 return !i;
5577
5578         if (!i)
5579                 return false;
5580
5581         i = I915_READ(reg_elda);
5582         i &= ~bits_elda;
5583         I915_WRITE(reg_elda, i);
5584
5585         for (i = 0; i < eld[2]; i++)
5586                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5587                         return false;
5588
5589         return true;
5590 }
5591
5592 static void g4x_write_eld(struct drm_connector *connector,
5593                           struct drm_crtc *crtc)
5594 {
5595         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5596         uint8_t *eld = connector->eld;
5597         uint32_t eldv;
5598         uint32_t len;
5599         uint32_t i;
5600
5601         i = I915_READ(G4X_AUD_VID_DID);
5602
5603         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5604                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5605         else
5606                 eldv = G4X_ELDV_DEVCTG;
5607
5608         if (intel_eld_uptodate(connector,
5609                                G4X_AUD_CNTL_ST, eldv,
5610                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5611                                G4X_HDMIW_HDMIEDID))
5612                 return;
5613
5614         i = I915_READ(G4X_AUD_CNTL_ST);
5615         i &= ~(eldv | G4X_ELD_ADDR);
5616         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5617         I915_WRITE(G4X_AUD_CNTL_ST, i);
5618
5619         if (!eld[0])
5620                 return;
5621
5622         len = min_t(uint8_t, eld[2], len);
5623         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5624         for (i = 0; i < len; i++)
5625                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5626
5627         i = I915_READ(G4X_AUD_CNTL_ST);
5628         i |= eldv;
5629         I915_WRITE(G4X_AUD_CNTL_ST, i);
5630 }
5631
5632 static void haswell_write_eld(struct drm_connector *connector,
5633                                      struct drm_crtc *crtc)
5634 {
5635         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5636         uint8_t *eld = connector->eld;
5637         struct drm_device *dev = crtc->dev;
5638         uint32_t eldv;
5639         uint32_t i;
5640         int len;
5641         int pipe = to_intel_crtc(crtc)->pipe;
5642         int tmp;
5643
5644         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5645         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5646         int aud_config = HSW_AUD_CFG(pipe);
5647         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5648
5649
5650         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5651
5652         /* Audio output enable */
5653         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5654         tmp = I915_READ(aud_cntrl_st2);
5655         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5656         I915_WRITE(aud_cntrl_st2, tmp);
5657
5658         /* Wait for 1 vertical blank */
5659         intel_wait_for_vblank(dev, pipe);
5660
5661         /* Set ELD valid state */
5662         tmp = I915_READ(aud_cntrl_st2);
5663         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5664         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5665         I915_WRITE(aud_cntrl_st2, tmp);
5666         tmp = I915_READ(aud_cntrl_st2);
5667         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5668
5669         /* Enable HDMI mode */
5670         tmp = I915_READ(aud_config);
5671         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5672         /* clear N_programing_enable and N_value_index */
5673         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5674         I915_WRITE(aud_config, tmp);
5675
5676         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5677
5678         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5679
5680         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5681                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5682                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5683                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5684         } else
5685                 I915_WRITE(aud_config, 0);
5686
5687         if (intel_eld_uptodate(connector,
5688                                aud_cntrl_st2, eldv,
5689                                aud_cntl_st, IBX_ELD_ADDRESS,
5690                                hdmiw_hdmiedid))
5691                 return;
5692
5693         i = I915_READ(aud_cntrl_st2);
5694         i &= ~eldv;
5695         I915_WRITE(aud_cntrl_st2, i);
5696
5697         if (!eld[0])
5698                 return;
5699
5700         i = I915_READ(aud_cntl_st);
5701         i &= ~IBX_ELD_ADDRESS;
5702         I915_WRITE(aud_cntl_st, i);
5703         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5704         DRM_DEBUG_DRIVER("port num:%d\n", i);
5705
5706         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5707         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5708         for (i = 0; i < len; i++)
5709                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5710
5711         i = I915_READ(aud_cntrl_st2);
5712         i |= eldv;
5713         I915_WRITE(aud_cntrl_st2, i);
5714
5715 }
5716
5717 static void ironlake_write_eld(struct drm_connector *connector,
5718                                      struct drm_crtc *crtc)
5719 {
5720         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5721         uint8_t *eld = connector->eld;
5722         uint32_t eldv;
5723         uint32_t i;
5724         int len;
5725         int hdmiw_hdmiedid;
5726         int aud_config;
5727         int aud_cntl_st;
5728         int aud_cntrl_st2;
5729         int pipe = to_intel_crtc(crtc)->pipe;
5730
5731         if (HAS_PCH_IBX(connector->dev)) {
5732                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5733                 aud_config = IBX_AUD_CFG(pipe);
5734                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5735                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5736         } else {
5737                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5738                 aud_config = CPT_AUD_CFG(pipe);
5739                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5740                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5741         }
5742
5743         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5744
5745         i = I915_READ(aud_cntl_st);
5746         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5747         if (!i) {
5748                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5749                 /* operate blindly on all ports */
5750                 eldv = IBX_ELD_VALIDB;
5751                 eldv |= IBX_ELD_VALIDB << 4;
5752                 eldv |= IBX_ELD_VALIDB << 8;
5753         } else {
5754                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5755                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5756         }
5757
5758         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5759                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5760                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5761                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5762         } else
5763                 I915_WRITE(aud_config, 0);
5764
5765         if (intel_eld_uptodate(connector,
5766                                aud_cntrl_st2, eldv,
5767                                aud_cntl_st, IBX_ELD_ADDRESS,
5768                                hdmiw_hdmiedid))
5769                 return;
5770
5771         i = I915_READ(aud_cntrl_st2);
5772         i &= ~eldv;
5773         I915_WRITE(aud_cntrl_st2, i);
5774
5775         if (!eld[0])
5776                 return;
5777
5778         i = I915_READ(aud_cntl_st);
5779         i &= ~IBX_ELD_ADDRESS;
5780         I915_WRITE(aud_cntl_st, i);
5781
5782         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5783         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5784         for (i = 0; i < len; i++)
5785                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5786
5787         i = I915_READ(aud_cntrl_st2);
5788         i |= eldv;
5789         I915_WRITE(aud_cntrl_st2, i);
5790 }
5791
5792 void intel_write_eld(struct drm_encoder *encoder,
5793                      struct drm_display_mode *mode)
5794 {
5795         struct drm_crtc *crtc = encoder->crtc;
5796         struct drm_connector *connector;
5797         struct drm_device *dev = encoder->dev;
5798         struct drm_i915_private *dev_priv = dev->dev_private;
5799
5800         connector = drm_select_eld(encoder, mode);
5801         if (!connector)
5802                 return;
5803
5804         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5805                          connector->base.id,
5806                          drm_get_connector_name(connector),
5807                          connector->encoder->base.id,
5808                          drm_get_encoder_name(connector->encoder));
5809
5810         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5811
5812         if (dev_priv->display.write_eld)
5813                 dev_priv->display.write_eld(connector, crtc);
5814 }
5815
5816 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5817 void intel_crtc_load_lut(struct drm_crtc *crtc)
5818 {
5819         struct drm_device *dev = crtc->dev;
5820         struct drm_i915_private *dev_priv = dev->dev_private;
5821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5822         int palreg = PALETTE(intel_crtc->pipe);
5823         int i;
5824
5825         /* The clocks have to be on to load the palette. */
5826         if (!crtc->enabled || !intel_crtc->active)
5827                 return;
5828
5829         /* use legacy palette for Ironlake */
5830         if (HAS_PCH_SPLIT(dev))
5831                 palreg = LGC_PALETTE(intel_crtc->pipe);
5832
5833         for (i = 0; i < 256; i++) {
5834                 I915_WRITE(palreg + 4 * i,
5835                            (intel_crtc->lut_r[i] << 16) |
5836                            (intel_crtc->lut_g[i] << 8) |
5837                            intel_crtc->lut_b[i]);
5838         }
5839 }
5840
5841 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5842 {
5843         struct drm_device *dev = crtc->dev;
5844         struct drm_i915_private *dev_priv = dev->dev_private;
5845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5846         bool visible = base != 0;
5847         u32 cntl;
5848
5849         if (intel_crtc->cursor_visible == visible)
5850                 return;
5851
5852         cntl = I915_READ(_CURACNTR);
5853         if (visible) {
5854                 /* On these chipsets we can only modify the base whilst
5855                  * the cursor is disabled.
5856                  */
5857                 I915_WRITE(_CURABASE, base);
5858
5859                 cntl &= ~(CURSOR_FORMAT_MASK);
5860                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5861                 cntl |= CURSOR_ENABLE |
5862                         CURSOR_GAMMA_ENABLE |
5863                         CURSOR_FORMAT_ARGB;
5864         } else
5865                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5866         I915_WRITE(_CURACNTR, cntl);
5867
5868         intel_crtc->cursor_visible = visible;
5869 }
5870
5871 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5872 {
5873         struct drm_device *dev = crtc->dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5876         int pipe = intel_crtc->pipe;
5877         bool visible = base != 0;
5878
5879         if (intel_crtc->cursor_visible != visible) {
5880                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5881                 if (base) {
5882                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5883                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5884                         cntl |= pipe << 28; /* Connect to correct pipe */
5885                 } else {
5886                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5887                         cntl |= CURSOR_MODE_DISABLE;
5888                 }
5889                 I915_WRITE(CURCNTR(pipe), cntl);
5890
5891                 intel_crtc->cursor_visible = visible;
5892         }
5893         /* and commit changes on next vblank */
5894         I915_WRITE(CURBASE(pipe), base);
5895 }
5896
5897 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5898 {
5899         struct drm_device *dev = crtc->dev;
5900         struct drm_i915_private *dev_priv = dev->dev_private;
5901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5902         int pipe = intel_crtc->pipe;
5903         bool visible = base != 0;
5904
5905         if (intel_crtc->cursor_visible != visible) {
5906                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5907                 if (base) {
5908                         cntl &= ~CURSOR_MODE;
5909                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5910                 } else {
5911                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5912                         cntl |= CURSOR_MODE_DISABLE;
5913                 }
5914                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5915
5916                 intel_crtc->cursor_visible = visible;
5917         }
5918         /* and commit changes on next vblank */
5919         I915_WRITE(CURBASE_IVB(pipe), base);
5920 }
5921
5922 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5923 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5924                                      bool on)
5925 {
5926         struct drm_device *dev = crtc->dev;
5927         struct drm_i915_private *dev_priv = dev->dev_private;
5928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5929         int pipe = intel_crtc->pipe;
5930         int x = intel_crtc->cursor_x;
5931         int y = intel_crtc->cursor_y;
5932         u32 base, pos;
5933         bool visible;
5934
5935         pos = 0;
5936
5937         if (on && crtc->enabled && crtc->fb) {
5938                 base = intel_crtc->cursor_addr;
5939                 if (x > (int) crtc->fb->width)
5940                         base = 0;
5941
5942                 if (y > (int) crtc->fb->height)
5943                         base = 0;
5944         } else
5945                 base = 0;
5946
5947         if (x < 0) {
5948                 if (x + intel_crtc->cursor_width < 0)
5949                         base = 0;
5950
5951                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5952                 x = -x;
5953         }
5954         pos |= x << CURSOR_X_SHIFT;
5955
5956         if (y < 0) {
5957                 if (y + intel_crtc->cursor_height < 0)
5958                         base = 0;
5959
5960                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5961                 y = -y;
5962         }
5963         pos |= y << CURSOR_Y_SHIFT;
5964
5965         visible = base != 0;
5966         if (!visible && !intel_crtc->cursor_visible)
5967                 return;
5968
5969         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5970                 I915_WRITE(CURPOS_IVB(pipe), pos);
5971                 ivb_update_cursor(crtc, base);
5972         } else {
5973                 I915_WRITE(CURPOS(pipe), pos);
5974                 if (IS_845G(dev) || IS_I865G(dev))
5975                         i845_update_cursor(crtc, base);
5976                 else
5977                         i9xx_update_cursor(crtc, base);
5978         }
5979 }
5980
5981 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5982                                  struct drm_file *file,
5983                                  uint32_t handle,
5984                                  uint32_t width, uint32_t height)
5985 {
5986         struct drm_device *dev = crtc->dev;
5987         struct drm_i915_private *dev_priv = dev->dev_private;
5988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5989         struct drm_i915_gem_object *obj;
5990         uint32_t addr;
5991         int ret;
5992
5993         /* if we want to turn off the cursor ignore width and height */
5994         if (!handle) {
5995                 DRM_DEBUG_KMS("cursor off\n");
5996                 addr = 0;
5997                 obj = NULL;
5998                 mutex_lock(&dev->struct_mutex);
5999                 goto finish;
6000         }
6001
6002         /* Currently we only support 64x64 cursors */
6003         if (width != 64 || height != 64) {
6004                 DRM_ERROR("we currently only support 64x64 cursors\n");
6005                 return -EINVAL;
6006         }
6007
6008         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6009         if (&obj->base == NULL)
6010                 return -ENOENT;
6011
6012         if (obj->base.size < width * height * 4) {
6013                 DRM_ERROR("buffer is to small\n");
6014                 ret = -ENOMEM;
6015                 goto fail;
6016         }
6017
6018         /* we only need to pin inside GTT if cursor is non-phy */
6019         mutex_lock(&dev->struct_mutex);
6020         if (!dev_priv->info->cursor_needs_physical) {
6021                 if (obj->tiling_mode) {
6022                         DRM_ERROR("cursor cannot be tiled\n");
6023                         ret = -EINVAL;
6024                         goto fail_locked;
6025                 }
6026
6027                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6028                 if (ret) {
6029                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6030                         goto fail_locked;
6031                 }
6032
6033                 ret = i915_gem_object_put_fence(obj);
6034                 if (ret) {
6035                         DRM_ERROR("failed to release fence for cursor");
6036                         goto fail_unpin;
6037                 }
6038
6039                 addr = obj->gtt_offset;
6040         } else {
6041                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6042                 ret = i915_gem_attach_phys_object(dev, obj,
6043                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6044                                                   align);
6045                 if (ret) {
6046                         DRM_ERROR("failed to attach phys object\n");
6047                         goto fail_locked;
6048                 }
6049                 addr = obj->phys_obj->handle->busaddr;
6050         }
6051
6052         if (IS_GEN2(dev))
6053                 I915_WRITE(CURSIZE, (height << 12) | width);
6054
6055  finish:
6056         if (intel_crtc->cursor_bo) {
6057                 if (dev_priv->info->cursor_needs_physical) {
6058                         if (intel_crtc->cursor_bo != obj)
6059                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6060                 } else
6061                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6062                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6063         }
6064
6065         mutex_unlock(&dev->struct_mutex);
6066
6067         intel_crtc->cursor_addr = addr;
6068         intel_crtc->cursor_bo = obj;
6069         intel_crtc->cursor_width = width;
6070         intel_crtc->cursor_height = height;
6071
6072         intel_crtc_update_cursor(crtc, true);
6073
6074         return 0;
6075 fail_unpin:
6076         i915_gem_object_unpin(obj);
6077 fail_locked:
6078         mutex_unlock(&dev->struct_mutex);
6079 fail:
6080         drm_gem_object_unreference_unlocked(&obj->base);
6081         return ret;
6082 }
6083
6084 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6085 {
6086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6087
6088         intel_crtc->cursor_x = x;
6089         intel_crtc->cursor_y = y;
6090
6091         intel_crtc_update_cursor(crtc, true);
6092
6093         return 0;
6094 }
6095
6096 /** Sets the color ramps on behalf of RandR */
6097 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6098                                  u16 blue, int regno)
6099 {
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101
6102         intel_crtc->lut_r[regno] = red >> 8;
6103         intel_crtc->lut_g[regno] = green >> 8;
6104         intel_crtc->lut_b[regno] = blue >> 8;
6105 }
6106
6107 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6108                              u16 *blue, int regno)
6109 {
6110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6111
6112         *red = intel_crtc->lut_r[regno] << 8;
6113         *green = intel_crtc->lut_g[regno] << 8;
6114         *blue = intel_crtc->lut_b[regno] << 8;
6115 }
6116
6117 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6118                                  u16 *blue, uint32_t start, uint32_t size)
6119 {
6120         int end = (start + size > 256) ? 256 : start + size, i;
6121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122
6123         for (i = start; i < end; i++) {
6124                 intel_crtc->lut_r[i] = red[i] >> 8;
6125                 intel_crtc->lut_g[i] = green[i] >> 8;
6126                 intel_crtc->lut_b[i] = blue[i] >> 8;
6127         }
6128
6129         intel_crtc_load_lut(crtc);
6130 }
6131
6132 /**
6133  * Get a pipe with a simple mode set on it for doing load-based monitor
6134  * detection.
6135  *
6136  * It will be up to the load-detect code to adjust the pipe as appropriate for
6137  * its requirements.  The pipe will be connected to no other encoders.
6138  *
6139  * Currently this code will only succeed if there is a pipe with no encoders
6140  * configured for it.  In the future, it could choose to temporarily disable
6141  * some outputs to free up a pipe for its use.
6142  *
6143  * \return crtc, or NULL if no pipes are available.
6144  */
6145
6146 /* VESA 640x480x72Hz mode to set on the pipe */
6147 static struct drm_display_mode load_detect_mode = {
6148         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6149                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6150 };
6151
6152 static struct drm_framebuffer *
6153 intel_framebuffer_create(struct drm_device *dev,
6154                          struct drm_mode_fb_cmd2 *mode_cmd,
6155                          struct drm_i915_gem_object *obj)
6156 {
6157         struct intel_framebuffer *intel_fb;
6158         int ret;
6159
6160         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6161         if (!intel_fb) {
6162                 drm_gem_object_unreference_unlocked(&obj->base);
6163                 return ERR_PTR(-ENOMEM);
6164         }
6165
6166         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6167         if (ret) {
6168                 drm_gem_object_unreference_unlocked(&obj->base);
6169                 kfree(intel_fb);
6170                 return ERR_PTR(ret);
6171         }
6172
6173         return &intel_fb->base;
6174 }
6175
6176 static u32
6177 intel_framebuffer_pitch_for_width(int width, int bpp)
6178 {
6179         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6180         return ALIGN(pitch, 64);
6181 }
6182
6183 static u32
6184 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6185 {
6186         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6187         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6188 }
6189
6190 static struct drm_framebuffer *
6191 intel_framebuffer_create_for_mode(struct drm_device *dev,
6192                                   struct drm_display_mode *mode,
6193                                   int depth, int bpp)
6194 {
6195         struct drm_i915_gem_object *obj;
6196         struct drm_mode_fb_cmd2 mode_cmd;
6197
6198         obj = i915_gem_alloc_object(dev,
6199                                     intel_framebuffer_size_for_mode(mode, bpp));
6200         if (obj == NULL)
6201                 return ERR_PTR(-ENOMEM);
6202
6203         mode_cmd.width = mode->hdisplay;
6204         mode_cmd.height = mode->vdisplay;
6205         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6206                                                                 bpp);
6207         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6208
6209         return intel_framebuffer_create(dev, &mode_cmd, obj);
6210 }
6211
6212 static struct drm_framebuffer *
6213 mode_fits_in_fbdev(struct drm_device *dev,
6214                    struct drm_display_mode *mode)
6215 {
6216         struct drm_i915_private *dev_priv = dev->dev_private;
6217         struct drm_i915_gem_object *obj;
6218         struct drm_framebuffer *fb;
6219
6220         if (dev_priv->fbdev == NULL)
6221                 return NULL;
6222
6223         obj = dev_priv->fbdev->ifb.obj;
6224         if (obj == NULL)
6225                 return NULL;
6226
6227         fb = &dev_priv->fbdev->ifb.base;
6228         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6229                                                                fb->bits_per_pixel))
6230                 return NULL;
6231
6232         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6233                 return NULL;
6234
6235         return fb;
6236 }
6237
6238 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6239                                 struct drm_display_mode *mode,
6240                                 struct intel_load_detect_pipe *old)
6241 {
6242         struct intel_crtc *intel_crtc;
6243         struct intel_encoder *intel_encoder =
6244                 intel_attached_encoder(connector);
6245         struct drm_crtc *possible_crtc;
6246         struct drm_encoder *encoder = &intel_encoder->base;
6247         struct drm_crtc *crtc = NULL;
6248         struct drm_device *dev = encoder->dev;
6249         struct drm_framebuffer *fb;
6250         int i = -1;
6251
6252         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6253                       connector->base.id, drm_get_connector_name(connector),
6254                       encoder->base.id, drm_get_encoder_name(encoder));
6255
6256         /*
6257          * Algorithm gets a little messy:
6258          *
6259          *   - if the connector already has an assigned crtc, use it (but make
6260          *     sure it's on first)
6261          *
6262          *   - try to find the first unused crtc that can drive this connector,
6263          *     and use that if we find one
6264          */
6265
6266         /* See if we already have a CRTC for this connector */
6267         if (encoder->crtc) {
6268                 crtc = encoder->crtc;
6269
6270                 old->dpms_mode = connector->dpms;
6271                 old->load_detect_temp = false;
6272
6273                 /* Make sure the crtc and connector are running */
6274                 if (connector->dpms != DRM_MODE_DPMS_ON)
6275                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6276
6277                 return true;
6278         }
6279
6280         /* Find an unused one (if possible) */
6281         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6282                 i++;
6283                 if (!(encoder->possible_crtcs & (1 << i)))
6284                         continue;
6285                 if (!possible_crtc->enabled) {
6286                         crtc = possible_crtc;
6287                         break;
6288                 }
6289         }
6290
6291         /*
6292          * If we didn't find an unused CRTC, don't use any.
6293          */
6294         if (!crtc) {
6295                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6296                 return false;
6297         }
6298
6299         intel_encoder->new_crtc = to_intel_crtc(crtc);
6300         to_intel_connector(connector)->new_encoder = intel_encoder;
6301
6302         intel_crtc = to_intel_crtc(crtc);
6303         old->dpms_mode = connector->dpms;
6304         old->load_detect_temp = true;
6305         old->release_fb = NULL;
6306
6307         if (!mode)
6308                 mode = &load_detect_mode;
6309
6310         /* We need a framebuffer large enough to accommodate all accesses
6311          * that the plane may generate whilst we perform load detection.
6312          * We can not rely on the fbcon either being present (we get called
6313          * during its initialisation to detect all boot displays, or it may
6314          * not even exist) or that it is large enough to satisfy the
6315          * requested mode.
6316          */
6317         fb = mode_fits_in_fbdev(dev, mode);
6318         if (fb == NULL) {
6319                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6320                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6321                 old->release_fb = fb;
6322         } else
6323                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6324         if (IS_ERR(fb)) {
6325                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6326                 goto fail;
6327         }
6328
6329         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6330                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6331                 if (old->release_fb)
6332                         old->release_fb->funcs->destroy(old->release_fb);
6333                 goto fail;
6334         }
6335
6336         /* let the connector get through one full cycle before testing */
6337         intel_wait_for_vblank(dev, intel_crtc->pipe);
6338
6339         return true;
6340 fail:
6341         connector->encoder = NULL;
6342         encoder->crtc = NULL;
6343         return false;
6344 }
6345
6346 void intel_release_load_detect_pipe(struct drm_connector *connector,
6347                                     struct intel_load_detect_pipe *old)
6348 {
6349         struct intel_encoder *intel_encoder =
6350                 intel_attached_encoder(connector);
6351         struct drm_encoder *encoder = &intel_encoder->base;
6352
6353         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6354                       connector->base.id, drm_get_connector_name(connector),
6355                       encoder->base.id, drm_get_encoder_name(encoder));
6356
6357         if (old->load_detect_temp) {
6358                 struct drm_crtc *crtc = encoder->crtc;
6359
6360                 to_intel_connector(connector)->new_encoder = NULL;
6361                 intel_encoder->new_crtc = NULL;
6362                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6363
6364                 if (old->release_fb)
6365                         old->release_fb->funcs->destroy(old->release_fb);
6366
6367                 return;
6368         }
6369
6370         /* Switch crtc and encoder back off if necessary */
6371         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6372                 connector->funcs->dpms(connector, old->dpms_mode);
6373 }
6374
6375 /* Returns the clock of the currently programmed mode of the given pipe. */
6376 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6377 {
6378         struct drm_i915_private *dev_priv = dev->dev_private;
6379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380         int pipe = intel_crtc->pipe;
6381         u32 dpll = I915_READ(DPLL(pipe));
6382         u32 fp;
6383         intel_clock_t clock;
6384
6385         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6386                 fp = I915_READ(FP0(pipe));
6387         else
6388                 fp = I915_READ(FP1(pipe));
6389
6390         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6391         if (IS_PINEVIEW(dev)) {
6392                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6393                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6394         } else {
6395                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6396                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6397         }
6398
6399         if (!IS_GEN2(dev)) {
6400                 if (IS_PINEVIEW(dev))
6401                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6402                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6403                 else
6404                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6405                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6406
6407                 switch (dpll & DPLL_MODE_MASK) {
6408                 case DPLLB_MODE_DAC_SERIAL:
6409                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6410                                 5 : 10;
6411                         break;
6412                 case DPLLB_MODE_LVDS:
6413                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6414                                 7 : 14;
6415                         break;
6416                 default:
6417                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6418                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6419                         return 0;
6420                 }
6421
6422                 /* XXX: Handle the 100Mhz refclk */
6423                 intel_clock(dev, 96000, &clock);
6424         } else {
6425                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6426
6427                 if (is_lvds) {
6428                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6429                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6430                         clock.p2 = 14;
6431
6432                         if ((dpll & PLL_REF_INPUT_MASK) ==
6433                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6434                                 /* XXX: might not be 66MHz */
6435                                 intel_clock(dev, 66000, &clock);
6436                         } else
6437                                 intel_clock(dev, 48000, &clock);
6438                 } else {
6439                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6440                                 clock.p1 = 2;
6441                         else {
6442                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6443                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6444                         }
6445                         if (dpll & PLL_P2_DIVIDE_BY_4)
6446                                 clock.p2 = 4;
6447                         else
6448                                 clock.p2 = 2;
6449
6450                         intel_clock(dev, 48000, &clock);
6451                 }
6452         }
6453
6454         /* XXX: It would be nice to validate the clocks, but we can't reuse
6455          * i830PllIsValid() because it relies on the xf86_config connector
6456          * configuration being accurate, which it isn't necessarily.
6457          */
6458
6459         return clock.dot;
6460 }
6461
6462 /** Returns the currently programmed mode of the given pipe. */
6463 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6464                                              struct drm_crtc *crtc)
6465 {
6466         struct drm_i915_private *dev_priv = dev->dev_private;
6467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6468         int pipe = intel_crtc->pipe;
6469         struct drm_display_mode *mode;
6470         int htot = I915_READ(HTOTAL(pipe));
6471         int hsync = I915_READ(HSYNC(pipe));
6472         int vtot = I915_READ(VTOTAL(pipe));
6473         int vsync = I915_READ(VSYNC(pipe));
6474
6475         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6476         if (!mode)
6477                 return NULL;
6478
6479         mode->clock = intel_crtc_clock_get(dev, crtc);
6480         mode->hdisplay = (htot & 0xffff) + 1;
6481         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6482         mode->hsync_start = (hsync & 0xffff) + 1;
6483         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6484         mode->vdisplay = (vtot & 0xffff) + 1;
6485         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6486         mode->vsync_start = (vsync & 0xffff) + 1;
6487         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6488
6489         drm_mode_set_name(mode);
6490
6491         return mode;
6492 }
6493
6494 static void intel_increase_pllclock(struct drm_crtc *crtc)
6495 {
6496         struct drm_device *dev = crtc->dev;
6497         drm_i915_private_t *dev_priv = dev->dev_private;
6498         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6499         int pipe = intel_crtc->pipe;
6500         int dpll_reg = DPLL(pipe);
6501         int dpll;
6502
6503         if (HAS_PCH_SPLIT(dev))
6504                 return;
6505
6506         if (!dev_priv->lvds_downclock_avail)
6507                 return;
6508
6509         dpll = I915_READ(dpll_reg);
6510         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6511                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6512
6513                 assert_panel_unlocked(dev_priv, pipe);
6514
6515                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6516                 I915_WRITE(dpll_reg, dpll);
6517                 intel_wait_for_vblank(dev, pipe);
6518
6519                 dpll = I915_READ(dpll_reg);
6520                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6521                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6522         }
6523 }
6524
6525 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6526 {
6527         struct drm_device *dev = crtc->dev;
6528         drm_i915_private_t *dev_priv = dev->dev_private;
6529         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6530
6531         if (HAS_PCH_SPLIT(dev))
6532                 return;
6533
6534         if (!dev_priv->lvds_downclock_avail)
6535                 return;
6536
6537         /*
6538          * Since this is called by a timer, we should never get here in
6539          * the manual case.
6540          */
6541         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6542                 int pipe = intel_crtc->pipe;
6543                 int dpll_reg = DPLL(pipe);
6544                 int dpll;
6545
6546                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6547
6548                 assert_panel_unlocked(dev_priv, pipe);
6549
6550                 dpll = I915_READ(dpll_reg);
6551                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6552                 I915_WRITE(dpll_reg, dpll);
6553                 intel_wait_for_vblank(dev, pipe);
6554                 dpll = I915_READ(dpll_reg);
6555                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6556                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6557         }
6558
6559 }
6560
6561 void intel_mark_busy(struct drm_device *dev)
6562 {
6563         i915_update_gfx_val(dev->dev_private);
6564 }
6565
6566 void intel_mark_idle(struct drm_device *dev)
6567 {
6568 }
6569
6570 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6571 {
6572         struct drm_device *dev = obj->base.dev;
6573         struct drm_crtc *crtc;
6574
6575         if (!i915_powersave)
6576                 return;
6577
6578         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6579                 if (!crtc->fb)
6580                         continue;
6581
6582                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6583                         intel_increase_pllclock(crtc);
6584         }
6585 }
6586
6587 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6588 {
6589         struct drm_device *dev = obj->base.dev;
6590         struct drm_crtc *crtc;
6591
6592         if (!i915_powersave)
6593                 return;
6594
6595         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6596                 if (!crtc->fb)
6597                         continue;
6598
6599                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6600                         intel_decrease_pllclock(crtc);
6601         }
6602 }
6603
6604 static void intel_crtc_destroy(struct drm_crtc *crtc)
6605 {
6606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6607         struct drm_device *dev = crtc->dev;
6608         struct intel_unpin_work *work;
6609         unsigned long flags;
6610
6611         spin_lock_irqsave(&dev->event_lock, flags);
6612         work = intel_crtc->unpin_work;
6613         intel_crtc->unpin_work = NULL;
6614         spin_unlock_irqrestore(&dev->event_lock, flags);
6615
6616         if (work) {
6617                 cancel_work_sync(&work->work);
6618                 kfree(work);
6619         }
6620
6621         drm_crtc_cleanup(crtc);
6622
6623         kfree(intel_crtc);
6624 }
6625
6626 static void intel_unpin_work_fn(struct work_struct *__work)
6627 {
6628         struct intel_unpin_work *work =
6629                 container_of(__work, struct intel_unpin_work, work);
6630
6631         mutex_lock(&work->dev->struct_mutex);
6632         intel_unpin_fb_obj(work->old_fb_obj);
6633         drm_gem_object_unreference(&work->pending_flip_obj->base);
6634         drm_gem_object_unreference(&work->old_fb_obj->base);
6635
6636         intel_update_fbc(work->dev);
6637         mutex_unlock(&work->dev->struct_mutex);
6638         kfree(work);
6639 }
6640
6641 static void do_intel_finish_page_flip(struct drm_device *dev,
6642                                       struct drm_crtc *crtc)
6643 {
6644         drm_i915_private_t *dev_priv = dev->dev_private;
6645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6646         struct intel_unpin_work *work;
6647         struct drm_i915_gem_object *obj;
6648         struct drm_pending_vblank_event *e;
6649         struct timeval tvbl;
6650         unsigned long flags;
6651
6652         /* Ignore early vblank irqs */
6653         if (intel_crtc == NULL)
6654                 return;
6655
6656         spin_lock_irqsave(&dev->event_lock, flags);
6657         work = intel_crtc->unpin_work;
6658         if (work == NULL || !work->pending) {
6659                 spin_unlock_irqrestore(&dev->event_lock, flags);
6660                 return;
6661         }
6662
6663         intel_crtc->unpin_work = NULL;
6664
6665         if (work->event) {
6666                 e = work->event;
6667                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6668
6669                 e->event.tv_sec = tvbl.tv_sec;
6670                 e->event.tv_usec = tvbl.tv_usec;
6671
6672                 list_add_tail(&e->base.link,
6673                               &e->base.file_priv->event_list);
6674                 wake_up_interruptible(&e->base.file_priv->event_wait);
6675         }
6676
6677         drm_vblank_put(dev, intel_crtc->pipe);
6678
6679         spin_unlock_irqrestore(&dev->event_lock, flags);
6680
6681         obj = work->old_fb_obj;
6682
6683         atomic_clear_mask(1 << intel_crtc->plane,
6684                           &obj->pending_flip.counter);
6685
6686         wake_up(&dev_priv->pending_flip_queue);
6687         schedule_work(&work->work);
6688
6689         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6690 }
6691
6692 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6693 {
6694         drm_i915_private_t *dev_priv = dev->dev_private;
6695         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6696
6697         do_intel_finish_page_flip(dev, crtc);
6698 }
6699
6700 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6701 {
6702         drm_i915_private_t *dev_priv = dev->dev_private;
6703         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6704
6705         do_intel_finish_page_flip(dev, crtc);
6706 }
6707
6708 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6709 {
6710         drm_i915_private_t *dev_priv = dev->dev_private;
6711         struct intel_crtc *intel_crtc =
6712                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6713         unsigned long flags;
6714
6715         spin_lock_irqsave(&dev->event_lock, flags);
6716         if (intel_crtc->unpin_work) {
6717                 if ((++intel_crtc->unpin_work->pending) > 1)
6718                         DRM_ERROR("Prepared flip multiple times\n");
6719         } else {
6720                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6721         }
6722         spin_unlock_irqrestore(&dev->event_lock, flags);
6723 }
6724
6725 static int intel_gen2_queue_flip(struct drm_device *dev,
6726                                  struct drm_crtc *crtc,
6727                                  struct drm_framebuffer *fb,
6728                                  struct drm_i915_gem_object *obj)
6729 {
6730         struct drm_i915_private *dev_priv = dev->dev_private;
6731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6732         u32 flip_mask;
6733         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6734         int ret;
6735
6736         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6737         if (ret)
6738                 goto err;
6739
6740         ret = intel_ring_begin(ring, 6);
6741         if (ret)
6742                 goto err_unpin;
6743
6744         /* Can't queue multiple flips, so wait for the previous
6745          * one to finish before executing the next.
6746          */
6747         if (intel_crtc->plane)
6748                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6749         else
6750                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6751         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6752         intel_ring_emit(ring, MI_NOOP);
6753         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6754                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6755         intel_ring_emit(ring, fb->pitches[0]);
6756         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6757         intel_ring_emit(ring, 0); /* aux display base address, unused */
6758         intel_ring_advance(ring);
6759         return 0;
6760
6761 err_unpin:
6762         intel_unpin_fb_obj(obj);
6763 err:
6764         return ret;
6765 }
6766
6767 static int intel_gen3_queue_flip(struct drm_device *dev,
6768                                  struct drm_crtc *crtc,
6769                                  struct drm_framebuffer *fb,
6770                                  struct drm_i915_gem_object *obj)
6771 {
6772         struct drm_i915_private *dev_priv = dev->dev_private;
6773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6774         u32 flip_mask;
6775         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6776         int ret;
6777
6778         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6779         if (ret)
6780                 goto err;
6781
6782         ret = intel_ring_begin(ring, 6);
6783         if (ret)
6784                 goto err_unpin;
6785
6786         if (intel_crtc->plane)
6787                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6788         else
6789                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6790         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6791         intel_ring_emit(ring, MI_NOOP);
6792         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6793                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6794         intel_ring_emit(ring, fb->pitches[0]);
6795         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6796         intel_ring_emit(ring, MI_NOOP);
6797
6798         intel_ring_advance(ring);
6799         return 0;
6800
6801 err_unpin:
6802         intel_unpin_fb_obj(obj);
6803 err:
6804         return ret;
6805 }
6806
6807 static int intel_gen4_queue_flip(struct drm_device *dev,
6808                                  struct drm_crtc *crtc,
6809                                  struct drm_framebuffer *fb,
6810                                  struct drm_i915_gem_object *obj)
6811 {
6812         struct drm_i915_private *dev_priv = dev->dev_private;
6813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814         uint32_t pf, pipesrc;
6815         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6816         int ret;
6817
6818         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6819         if (ret)
6820                 goto err;
6821
6822         ret = intel_ring_begin(ring, 4);
6823         if (ret)
6824                 goto err_unpin;
6825
6826         /* i965+ uses the linear or tiled offsets from the
6827          * Display Registers (which do not change across a page-flip)
6828          * so we need only reprogram the base address.
6829          */
6830         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6831                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6832         intel_ring_emit(ring, fb->pitches[0]);
6833         intel_ring_emit(ring,
6834                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6835                         obj->tiling_mode);
6836
6837         /* XXX Enabling the panel-fitter across page-flip is so far
6838          * untested on non-native modes, so ignore it for now.
6839          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6840          */
6841         pf = 0;
6842         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6843         intel_ring_emit(ring, pf | pipesrc);
6844         intel_ring_advance(ring);
6845         return 0;
6846
6847 err_unpin:
6848         intel_unpin_fb_obj(obj);
6849 err:
6850         return ret;
6851 }
6852
6853 static int intel_gen6_queue_flip(struct drm_device *dev,
6854                                  struct drm_crtc *crtc,
6855                                  struct drm_framebuffer *fb,
6856                                  struct drm_i915_gem_object *obj)
6857 {
6858         struct drm_i915_private *dev_priv = dev->dev_private;
6859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6860         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6861         uint32_t pf, pipesrc;
6862         int ret;
6863
6864         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6865         if (ret)
6866                 goto err;
6867
6868         ret = intel_ring_begin(ring, 4);
6869         if (ret)
6870                 goto err_unpin;
6871
6872         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6873                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6874         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6875         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6876
6877         /* Contrary to the suggestions in the documentation,
6878          * "Enable Panel Fitter" does not seem to be required when page
6879          * flipping with a non-native mode, and worse causes a normal
6880          * modeset to fail.
6881          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6882          */
6883         pf = 0;
6884         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6885         intel_ring_emit(ring, pf | pipesrc);
6886         intel_ring_advance(ring);
6887         return 0;
6888
6889 err_unpin:
6890         intel_unpin_fb_obj(obj);
6891 err:
6892         return ret;
6893 }
6894
6895 /*
6896  * On gen7 we currently use the blit ring because (in early silicon at least)
6897  * the render ring doesn't give us interrpts for page flip completion, which
6898  * means clients will hang after the first flip is queued.  Fortunately the
6899  * blit ring generates interrupts properly, so use it instead.
6900  */
6901 static int intel_gen7_queue_flip(struct drm_device *dev,
6902                                  struct drm_crtc *crtc,
6903                                  struct drm_framebuffer *fb,
6904                                  struct drm_i915_gem_object *obj)
6905 {
6906         struct drm_i915_private *dev_priv = dev->dev_private;
6907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6908         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6909         uint32_t plane_bit = 0;
6910         int ret;
6911
6912         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6913         if (ret)
6914                 goto err;
6915
6916         switch(intel_crtc->plane) {
6917         case PLANE_A:
6918                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6919                 break;
6920         case PLANE_B:
6921                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6922                 break;
6923         case PLANE_C:
6924                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6925                 break;
6926         default:
6927                 WARN_ONCE(1, "unknown plane in flip command\n");
6928                 ret = -ENODEV;
6929                 goto err_unpin;
6930         }
6931
6932         ret = intel_ring_begin(ring, 4);
6933         if (ret)
6934                 goto err_unpin;
6935
6936         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6937         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6938         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6939         intel_ring_emit(ring, (MI_NOOP));
6940         intel_ring_advance(ring);
6941         return 0;
6942
6943 err_unpin:
6944         intel_unpin_fb_obj(obj);
6945 err:
6946         return ret;
6947 }
6948
6949 static int intel_default_queue_flip(struct drm_device *dev,
6950                                     struct drm_crtc *crtc,
6951                                     struct drm_framebuffer *fb,
6952                                     struct drm_i915_gem_object *obj)
6953 {
6954         return -ENODEV;
6955 }
6956
6957 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6958                                 struct drm_framebuffer *fb,
6959                                 struct drm_pending_vblank_event *event)
6960 {
6961         struct drm_device *dev = crtc->dev;
6962         struct drm_i915_private *dev_priv = dev->dev_private;
6963         struct intel_framebuffer *intel_fb;
6964         struct drm_i915_gem_object *obj;
6965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6966         struct intel_unpin_work *work;
6967         unsigned long flags;
6968         int ret;
6969
6970         /* Can't change pixel format via MI display flips. */
6971         if (fb->pixel_format != crtc->fb->pixel_format)
6972                 return -EINVAL;
6973
6974         /*
6975          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6976          * Note that pitch changes could also affect these register.
6977          */
6978         if (INTEL_INFO(dev)->gen > 3 &&
6979             (fb->offsets[0] != crtc->fb->offsets[0] ||
6980              fb->pitches[0] != crtc->fb->pitches[0]))
6981                 return -EINVAL;
6982
6983         work = kzalloc(sizeof *work, GFP_KERNEL);
6984         if (work == NULL)
6985                 return -ENOMEM;
6986
6987         work->event = event;
6988         work->dev = crtc->dev;
6989         intel_fb = to_intel_framebuffer(crtc->fb);
6990         work->old_fb_obj = intel_fb->obj;
6991         INIT_WORK(&work->work, intel_unpin_work_fn);
6992
6993         ret = drm_vblank_get(dev, intel_crtc->pipe);
6994         if (ret)
6995                 goto free_work;
6996
6997         /* We borrow the event spin lock for protecting unpin_work */
6998         spin_lock_irqsave(&dev->event_lock, flags);
6999         if (intel_crtc->unpin_work) {
7000                 spin_unlock_irqrestore(&dev->event_lock, flags);
7001                 kfree(work);
7002                 drm_vblank_put(dev, intel_crtc->pipe);
7003
7004                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7005                 return -EBUSY;
7006         }
7007         intel_crtc->unpin_work = work;
7008         spin_unlock_irqrestore(&dev->event_lock, flags);
7009
7010         intel_fb = to_intel_framebuffer(fb);
7011         obj = intel_fb->obj;
7012
7013         ret = i915_mutex_lock_interruptible(dev);
7014         if (ret)
7015                 goto cleanup;
7016
7017         /* Reference the objects for the scheduled work. */
7018         drm_gem_object_reference(&work->old_fb_obj->base);
7019         drm_gem_object_reference(&obj->base);
7020
7021         crtc->fb = fb;
7022
7023         work->pending_flip_obj = obj;
7024
7025         work->enable_stall_check = true;
7026
7027         /* Block clients from rendering to the new back buffer until
7028          * the flip occurs and the object is no longer visible.
7029          */
7030         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7031
7032         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7033         if (ret)
7034                 goto cleanup_pending;
7035
7036         intel_disable_fbc(dev);
7037         intel_mark_fb_busy(obj);
7038         mutex_unlock(&dev->struct_mutex);
7039
7040         trace_i915_flip_request(intel_crtc->plane, obj);
7041
7042         return 0;
7043
7044 cleanup_pending:
7045         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7046         drm_gem_object_unreference(&work->old_fb_obj->base);
7047         drm_gem_object_unreference(&obj->base);
7048         mutex_unlock(&dev->struct_mutex);
7049
7050 cleanup:
7051         spin_lock_irqsave(&dev->event_lock, flags);
7052         intel_crtc->unpin_work = NULL;
7053         spin_unlock_irqrestore(&dev->event_lock, flags);
7054
7055         drm_vblank_put(dev, intel_crtc->pipe);
7056 free_work:
7057         kfree(work);
7058
7059         return ret;
7060 }
7061
7062 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7063         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7064         .load_lut = intel_crtc_load_lut,
7065         .disable = intel_crtc_noop,
7066 };
7067
7068 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7069 {
7070         struct intel_encoder *other_encoder;
7071         struct drm_crtc *crtc = &encoder->new_crtc->base;
7072
7073         if (WARN_ON(!crtc))
7074                 return false;
7075
7076         list_for_each_entry(other_encoder,
7077                             &crtc->dev->mode_config.encoder_list,
7078                             base.head) {
7079
7080                 if (&other_encoder->new_crtc->base != crtc ||
7081                     encoder == other_encoder)
7082                         continue;
7083                 else
7084                         return true;
7085         }
7086
7087         return false;
7088 }
7089
7090 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7091                                   struct drm_crtc *crtc)
7092 {
7093         struct drm_device *dev;
7094         struct drm_crtc *tmp;
7095         int crtc_mask = 1;
7096
7097         WARN(!crtc, "checking null crtc?\n");
7098
7099         dev = crtc->dev;
7100
7101         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7102                 if (tmp == crtc)
7103                         break;
7104                 crtc_mask <<= 1;
7105         }
7106
7107         if (encoder->possible_crtcs & crtc_mask)
7108                 return true;
7109         return false;
7110 }
7111
7112 /**
7113  * intel_modeset_update_staged_output_state
7114  *
7115  * Updates the staged output configuration state, e.g. after we've read out the
7116  * current hw state.
7117  */
7118 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7119 {
7120         struct intel_encoder *encoder;
7121         struct intel_connector *connector;
7122
7123         list_for_each_entry(connector, &dev->mode_config.connector_list,
7124                             base.head) {
7125                 connector->new_encoder =
7126                         to_intel_encoder(connector->base.encoder);
7127         }
7128
7129         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7130                             base.head) {
7131                 encoder->new_crtc =
7132                         to_intel_crtc(encoder->base.crtc);
7133         }
7134 }
7135
7136 /**
7137  * intel_modeset_commit_output_state
7138  *
7139  * This function copies the stage display pipe configuration to the real one.
7140  */
7141 static void intel_modeset_commit_output_state(struct drm_device *dev)
7142 {
7143         struct intel_encoder *encoder;
7144         struct intel_connector *connector;
7145
7146         list_for_each_entry(connector, &dev->mode_config.connector_list,
7147                             base.head) {
7148                 connector->base.encoder = &connector->new_encoder->base;
7149         }
7150
7151         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7152                             base.head) {
7153                 encoder->base.crtc = &encoder->new_crtc->base;
7154         }
7155 }
7156
7157 static struct drm_display_mode *
7158 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7159                             struct drm_display_mode *mode)
7160 {
7161         struct drm_device *dev = crtc->dev;
7162         struct drm_display_mode *adjusted_mode;
7163         struct drm_encoder_helper_funcs *encoder_funcs;
7164         struct intel_encoder *encoder;
7165
7166         adjusted_mode = drm_mode_duplicate(dev, mode);
7167         if (!adjusted_mode)
7168                 return ERR_PTR(-ENOMEM);
7169
7170         /* Pass our mode to the connectors and the CRTC to give them a chance to
7171          * adjust it according to limitations or connector properties, and also
7172          * a chance to reject the mode entirely.
7173          */
7174         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7175                             base.head) {
7176
7177                 if (&encoder->new_crtc->base != crtc)
7178                         continue;
7179                 encoder_funcs = encoder->base.helper_private;
7180                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7181                                                 adjusted_mode))) {
7182                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7183                         goto fail;
7184                 }
7185         }
7186
7187         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7188                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7189                 goto fail;
7190         }
7191         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7192
7193         return adjusted_mode;
7194 fail:
7195         drm_mode_destroy(dev, adjusted_mode);
7196         return ERR_PTR(-EINVAL);
7197 }
7198
7199 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7200  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7201 static void
7202 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7203                              unsigned *prepare_pipes, unsigned *disable_pipes)
7204 {
7205         struct intel_crtc *intel_crtc;
7206         struct drm_device *dev = crtc->dev;
7207         struct intel_encoder *encoder;
7208         struct intel_connector *connector;
7209         struct drm_crtc *tmp_crtc;
7210
7211         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7212
7213         /* Check which crtcs have changed outputs connected to them, these need
7214          * to be part of the prepare_pipes mask. We don't (yet) support global
7215          * modeset across multiple crtcs, so modeset_pipes will only have one
7216          * bit set at most. */
7217         list_for_each_entry(connector, &dev->mode_config.connector_list,
7218                             base.head) {
7219                 if (connector->base.encoder == &connector->new_encoder->base)
7220                         continue;
7221
7222                 if (connector->base.encoder) {
7223                         tmp_crtc = connector->base.encoder->crtc;
7224
7225                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7226                 }
7227
7228                 if (connector->new_encoder)
7229                         *prepare_pipes |=
7230                                 1 << connector->new_encoder->new_crtc->pipe;
7231         }
7232
7233         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7234                             base.head) {
7235                 if (encoder->base.crtc == &encoder->new_crtc->base)
7236                         continue;
7237
7238                 if (encoder->base.crtc) {
7239                         tmp_crtc = encoder->base.crtc;
7240
7241                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7242                 }
7243
7244                 if (encoder->new_crtc)
7245                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7246         }
7247
7248         /* Check for any pipes that will be fully disabled ... */
7249         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7250                             base.head) {
7251                 bool used = false;
7252
7253                 /* Don't try to disable disabled crtcs. */
7254                 if (!intel_crtc->base.enabled)
7255                         continue;
7256
7257                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7258                                     base.head) {
7259                         if (encoder->new_crtc == intel_crtc)
7260                                 used = true;
7261                 }
7262
7263                 if (!used)
7264                         *disable_pipes |= 1 << intel_crtc->pipe;
7265         }
7266
7267
7268         /* set_mode is also used to update properties on life display pipes. */
7269         intel_crtc = to_intel_crtc(crtc);
7270         if (crtc->enabled)
7271                 *prepare_pipes |= 1 << intel_crtc->pipe;
7272
7273         /* We only support modeset on one single crtc, hence we need to do that
7274          * only for the passed in crtc iff we change anything else than just
7275          * disable crtcs.
7276          *
7277          * This is actually not true, to be fully compatible with the old crtc
7278          * helper we automatically disable _any_ output (i.e. doesn't need to be
7279          * connected to the crtc we're modesetting on) if it's disconnected.
7280          * Which is a rather nutty api (since changed the output configuration
7281          * without userspace's explicit request can lead to confusion), but
7282          * alas. Hence we currently need to modeset on all pipes we prepare. */
7283         if (*prepare_pipes)
7284                 *modeset_pipes = *prepare_pipes;
7285
7286         /* ... and mask these out. */
7287         *modeset_pipes &= ~(*disable_pipes);
7288         *prepare_pipes &= ~(*disable_pipes);
7289 }
7290
7291 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7292 {
7293         struct drm_encoder *encoder;
7294         struct drm_device *dev = crtc->dev;
7295
7296         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7297                 if (encoder->crtc == crtc)
7298                         return true;
7299
7300         return false;
7301 }
7302
7303 static void
7304 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7305 {
7306         struct intel_encoder *intel_encoder;
7307         struct intel_crtc *intel_crtc;
7308         struct drm_connector *connector;
7309
7310         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7311                             base.head) {
7312                 if (!intel_encoder->base.crtc)
7313                         continue;
7314
7315                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7316
7317                 if (prepare_pipes & (1 << intel_crtc->pipe))
7318                         intel_encoder->connectors_active = false;
7319         }
7320
7321         intel_modeset_commit_output_state(dev);
7322
7323         /* Update computed state. */
7324         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7325                             base.head) {
7326                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7327         }
7328
7329         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7330                 if (!connector->encoder || !connector->encoder->crtc)
7331                         continue;
7332
7333                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7334
7335                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7336                         struct drm_property *dpms_property =
7337                                 dev->mode_config.dpms_property;
7338
7339                         connector->dpms = DRM_MODE_DPMS_ON;
7340                         drm_connector_property_set_value(connector,
7341                                                          dpms_property,
7342                                                          DRM_MODE_DPMS_ON);
7343
7344                         intel_encoder = to_intel_encoder(connector->encoder);
7345                         intel_encoder->connectors_active = true;
7346                 }
7347         }
7348
7349 }
7350
7351 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7352         list_for_each_entry((intel_crtc), \
7353                             &(dev)->mode_config.crtc_list, \
7354                             base.head) \
7355                 if (mask & (1 <<(intel_crtc)->pipe)) \
7356
7357 void
7358 intel_modeset_check_state(struct drm_device *dev)
7359 {
7360         struct intel_crtc *crtc;
7361         struct intel_encoder *encoder;
7362         struct intel_connector *connector;
7363
7364         list_for_each_entry(connector, &dev->mode_config.connector_list,
7365                             base.head) {
7366                 /* This also checks the encoder/connector hw state with the
7367                  * ->get_hw_state callbacks. */
7368                 intel_connector_check_state(connector);
7369
7370                 WARN(&connector->new_encoder->base != connector->base.encoder,
7371                      "connector's staged encoder doesn't match current encoder\n");
7372         }
7373
7374         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7375                             base.head) {
7376                 bool enabled = false;
7377                 bool active = false;
7378                 enum pipe pipe, tracked_pipe;
7379
7380                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7381                               encoder->base.base.id,
7382                               drm_get_encoder_name(&encoder->base));
7383
7384                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7385                      "encoder's stage crtc doesn't match current crtc\n");
7386                 WARN(encoder->connectors_active && !encoder->base.crtc,
7387                      "encoder's active_connectors set, but no crtc\n");
7388
7389                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7390                                     base.head) {
7391                         if (connector->base.encoder != &encoder->base)
7392                                 continue;
7393                         enabled = true;
7394                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7395                                 active = true;
7396                 }
7397                 WARN(!!encoder->base.crtc != enabled,
7398                      "encoder's enabled state mismatch "
7399                      "(expected %i, found %i)\n",
7400                      !!encoder->base.crtc, enabled);
7401                 WARN(active && !encoder->base.crtc,
7402                      "active encoder with no crtc\n");
7403
7404                 WARN(encoder->connectors_active != active,
7405                      "encoder's computed active state doesn't match tracked active state "
7406                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7407
7408                 active = encoder->get_hw_state(encoder, &pipe);
7409                 WARN(active != encoder->connectors_active,
7410                      "encoder's hw state doesn't match sw tracking "
7411                      "(expected %i, found %i)\n",
7412                      encoder->connectors_active, active);
7413
7414                 if (!encoder->base.crtc)
7415                         continue;
7416
7417                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7418                 WARN(active && pipe != tracked_pipe,
7419                      "active encoder's pipe doesn't match"
7420                      "(expected %i, found %i)\n",
7421                      tracked_pipe, pipe);
7422
7423         }
7424
7425         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7426                             base.head) {
7427                 bool enabled = false;
7428                 bool active = false;
7429
7430                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7431                               crtc->base.base.id);
7432
7433                 WARN(crtc->active && !crtc->base.enabled,
7434                      "active crtc, but not enabled in sw tracking\n");
7435
7436                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7437                                     base.head) {
7438                         if (encoder->base.crtc != &crtc->base)
7439                                 continue;
7440                         enabled = true;
7441                         if (encoder->connectors_active)
7442                                 active = true;
7443                 }
7444                 WARN(active != crtc->active,
7445                      "crtc's computed active state doesn't match tracked active state "
7446                      "(expected %i, found %i)\n", active, crtc->active);
7447                 WARN(enabled != crtc->base.enabled,
7448                      "crtc's computed enabled state doesn't match tracked enabled state "
7449                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7450
7451                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7452         }
7453 }
7454
7455 bool intel_set_mode(struct drm_crtc *crtc,
7456                     struct drm_display_mode *mode,
7457                     int x, int y, struct drm_framebuffer *fb)
7458 {
7459         struct drm_device *dev = crtc->dev;
7460         drm_i915_private_t *dev_priv = dev->dev_private;
7461         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7462         struct drm_encoder_helper_funcs *encoder_funcs;
7463         struct drm_encoder *encoder;
7464         struct intel_crtc *intel_crtc;
7465         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7466         bool ret = true;
7467
7468         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7469                                      &prepare_pipes, &disable_pipes);
7470
7471         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7472                       modeset_pipes, prepare_pipes, disable_pipes);
7473
7474         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7475                 intel_crtc_disable(&intel_crtc->base);
7476
7477         saved_hwmode = crtc->hwmode;
7478         saved_mode = crtc->mode;
7479
7480         /* Hack: Because we don't (yet) support global modeset on multiple
7481          * crtcs, we don't keep track of the new mode for more than one crtc.
7482          * Hence simply check whether any bit is set in modeset_pipes in all the
7483          * pieces of code that are not yet converted to deal with mutliple crtcs
7484          * changing their mode at the same time. */
7485         adjusted_mode = NULL;
7486         if (modeset_pipes) {
7487                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7488                 if (IS_ERR(adjusted_mode)) {
7489                         return false;
7490                 }
7491         }
7492
7493         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7494                 if (intel_crtc->base.enabled)
7495                         dev_priv->display.crtc_disable(&intel_crtc->base);
7496         }
7497
7498         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7499          * to set it here already despite that we pass it down the callchain.
7500          */
7501         if (modeset_pipes)
7502                 crtc->mode = *mode;
7503
7504         /* Only after disabling all output pipelines that will be changed can we
7505          * update the the output configuration. */
7506         intel_modeset_update_state(dev, prepare_pipes);
7507
7508         /* Set up the DPLL and any encoders state that needs to adjust or depend
7509          * on the DPLL.
7510          */
7511         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7512                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7513                                            mode, adjusted_mode,
7514                                            x, y, fb);
7515                 if (!ret)
7516                     goto done;
7517
7518                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7519
7520                         if (encoder->crtc != &intel_crtc->base)
7521                                 continue;
7522
7523                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7524                                 encoder->base.id, drm_get_encoder_name(encoder),
7525                                 mode->base.id, mode->name);
7526                         encoder_funcs = encoder->helper_private;
7527                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7528                 }
7529         }
7530
7531         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7532         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7533                 dev_priv->display.crtc_enable(&intel_crtc->base);
7534
7535         if (modeset_pipes) {
7536                 /* Store real post-adjustment hardware mode. */
7537                 crtc->hwmode = *adjusted_mode;
7538
7539                 /* Calculate and store various constants which
7540                  * are later needed by vblank and swap-completion
7541                  * timestamping. They are derived from true hwmode.
7542                  */
7543                 drm_calc_timestamping_constants(crtc);
7544         }
7545
7546         /* FIXME: add subpixel order */
7547 done:
7548         drm_mode_destroy(dev, adjusted_mode);
7549         if (!ret && crtc->enabled) {
7550                 crtc->hwmode = saved_hwmode;
7551                 crtc->mode = saved_mode;
7552         } else {
7553                 intel_modeset_check_state(dev);
7554         }
7555
7556         return ret;
7557 }
7558
7559 #undef for_each_intel_crtc_masked
7560
7561 static void intel_set_config_free(struct intel_set_config *config)
7562 {
7563         if (!config)
7564                 return;
7565
7566         kfree(config->save_connector_encoders);
7567         kfree(config->save_encoder_crtcs);
7568         kfree(config);
7569 }
7570
7571 static int intel_set_config_save_state(struct drm_device *dev,
7572                                        struct intel_set_config *config)
7573 {
7574         struct drm_encoder *encoder;
7575         struct drm_connector *connector;
7576         int count;
7577
7578         config->save_encoder_crtcs =
7579                 kcalloc(dev->mode_config.num_encoder,
7580                         sizeof(struct drm_crtc *), GFP_KERNEL);
7581         if (!config->save_encoder_crtcs)
7582                 return -ENOMEM;
7583
7584         config->save_connector_encoders =
7585                 kcalloc(dev->mode_config.num_connector,
7586                         sizeof(struct drm_encoder *), GFP_KERNEL);
7587         if (!config->save_connector_encoders)
7588                 return -ENOMEM;
7589
7590         /* Copy data. Note that driver private data is not affected.
7591          * Should anything bad happen only the expected state is
7592          * restored, not the drivers personal bookkeeping.
7593          */
7594         count = 0;
7595         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7596                 config->save_encoder_crtcs[count++] = encoder->crtc;
7597         }
7598
7599         count = 0;
7600         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7601                 config->save_connector_encoders[count++] = connector->encoder;
7602         }
7603
7604         return 0;
7605 }
7606
7607 static void intel_set_config_restore_state(struct drm_device *dev,
7608                                            struct intel_set_config *config)
7609 {
7610         struct intel_encoder *encoder;
7611         struct intel_connector *connector;
7612         int count;
7613
7614         count = 0;
7615         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7616                 encoder->new_crtc =
7617                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7618         }
7619
7620         count = 0;
7621         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7622                 connector->new_encoder =
7623                         to_intel_encoder(config->save_connector_encoders[count++]);
7624         }
7625 }
7626
7627 static void
7628 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7629                                       struct intel_set_config *config)
7630 {
7631
7632         /* We should be able to check here if the fb has the same properties
7633          * and then just flip_or_move it */
7634         if (set->crtc->fb != set->fb) {
7635                 /* If we have no fb then treat it as a full mode set */
7636                 if (set->crtc->fb == NULL) {
7637                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7638                         config->mode_changed = true;
7639                 } else if (set->fb == NULL) {
7640                         config->mode_changed = true;
7641                 } else if (set->fb->depth != set->crtc->fb->depth) {
7642                         config->mode_changed = true;
7643                 } else if (set->fb->bits_per_pixel !=
7644                            set->crtc->fb->bits_per_pixel) {
7645                         config->mode_changed = true;
7646                 } else
7647                         config->fb_changed = true;
7648         }
7649
7650         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7651                 config->fb_changed = true;
7652
7653         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7654                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7655                 drm_mode_debug_printmodeline(&set->crtc->mode);
7656                 drm_mode_debug_printmodeline(set->mode);
7657                 config->mode_changed = true;
7658         }
7659 }
7660
7661 static int
7662 intel_modeset_stage_output_state(struct drm_device *dev,
7663                                  struct drm_mode_set *set,
7664                                  struct intel_set_config *config)
7665 {
7666         struct drm_crtc *new_crtc;
7667         struct intel_connector *connector;
7668         struct intel_encoder *encoder;
7669         int count, ro;
7670
7671         /* The upper layers ensure that we either disabl a crtc or have a list
7672          * of connectors. For paranoia, double-check this. */
7673         WARN_ON(!set->fb && (set->num_connectors != 0));
7674         WARN_ON(set->fb && (set->num_connectors == 0));
7675
7676         count = 0;
7677         list_for_each_entry(connector, &dev->mode_config.connector_list,
7678                             base.head) {
7679                 /* Otherwise traverse passed in connector list and get encoders
7680                  * for them. */
7681                 for (ro = 0; ro < set->num_connectors; ro++) {
7682                         if (set->connectors[ro] == &connector->base) {
7683                                 connector->new_encoder = connector->encoder;
7684                                 break;
7685                         }
7686                 }
7687
7688                 /* If we disable the crtc, disable all its connectors. Also, if
7689                  * the connector is on the changing crtc but not on the new
7690                  * connector list, disable it. */
7691                 if ((!set->fb || ro == set->num_connectors) &&
7692                     connector->base.encoder &&
7693                     connector->base.encoder->crtc == set->crtc) {
7694                         connector->new_encoder = NULL;
7695
7696                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7697                                 connector->base.base.id,
7698                                 drm_get_connector_name(&connector->base));
7699                 }
7700
7701
7702                 if (&connector->new_encoder->base != connector->base.encoder) {
7703                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7704                         config->mode_changed = true;
7705                 }
7706
7707                 /* Disable all disconnected encoders. */
7708                 if (connector->base.status == connector_status_disconnected)
7709                         connector->new_encoder = NULL;
7710         }
7711         /* connector->new_encoder is now updated for all connectors. */
7712
7713         /* Update crtc of enabled connectors. */
7714         count = 0;
7715         list_for_each_entry(connector, &dev->mode_config.connector_list,
7716                             base.head) {
7717                 if (!connector->new_encoder)
7718                         continue;
7719
7720                 new_crtc = connector->new_encoder->base.crtc;
7721
7722                 for (ro = 0; ro < set->num_connectors; ro++) {
7723                         if (set->connectors[ro] == &connector->base)
7724                                 new_crtc = set->crtc;
7725                 }
7726
7727                 /* Make sure the new CRTC will work with the encoder */
7728                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7729                                            new_crtc)) {
7730                         return -EINVAL;
7731                 }
7732                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7733
7734                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7735                         connector->base.base.id,
7736                         drm_get_connector_name(&connector->base),
7737                         new_crtc->base.id);
7738         }
7739
7740         /* Check for any encoders that needs to be disabled. */
7741         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7742                             base.head) {
7743                 list_for_each_entry(connector,
7744                                     &dev->mode_config.connector_list,
7745                                     base.head) {
7746                         if (connector->new_encoder == encoder) {
7747                                 WARN_ON(!connector->new_encoder->new_crtc);
7748
7749                                 goto next_encoder;
7750                         }
7751                 }
7752                 encoder->new_crtc = NULL;
7753 next_encoder:
7754                 /* Only now check for crtc changes so we don't miss encoders
7755                  * that will be disabled. */
7756                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7757                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7758                         config->mode_changed = true;
7759                 }
7760         }
7761         /* Now we've also updated encoder->new_crtc for all encoders. */
7762
7763         return 0;
7764 }
7765
7766 static int intel_crtc_set_config(struct drm_mode_set *set)
7767 {
7768         struct drm_device *dev;
7769         struct drm_mode_set save_set;
7770         struct intel_set_config *config;
7771         int ret;
7772
7773         BUG_ON(!set);
7774         BUG_ON(!set->crtc);
7775         BUG_ON(!set->crtc->helper_private);
7776
7777         if (!set->mode)
7778                 set->fb = NULL;
7779
7780         /* The fb helper likes to play gross jokes with ->mode_set_config.
7781          * Unfortunately the crtc helper doesn't do much at all for this case,
7782          * so we have to cope with this madness until the fb helper is fixed up. */
7783         if (set->fb && set->num_connectors == 0)
7784                 return 0;
7785
7786         if (set->fb) {
7787                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7788                                 set->crtc->base.id, set->fb->base.id,
7789                                 (int)set->num_connectors, set->x, set->y);
7790         } else {
7791                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7792         }
7793
7794         dev = set->crtc->dev;
7795
7796         ret = -ENOMEM;
7797         config = kzalloc(sizeof(*config), GFP_KERNEL);
7798         if (!config)
7799                 goto out_config;
7800
7801         ret = intel_set_config_save_state(dev, config);
7802         if (ret)
7803                 goto out_config;
7804
7805         save_set.crtc = set->crtc;
7806         save_set.mode = &set->crtc->mode;
7807         save_set.x = set->crtc->x;
7808         save_set.y = set->crtc->y;
7809         save_set.fb = set->crtc->fb;
7810
7811         /* Compute whether we need a full modeset, only an fb base update or no
7812          * change at all. In the future we might also check whether only the
7813          * mode changed, e.g. for LVDS where we only change the panel fitter in
7814          * such cases. */
7815         intel_set_config_compute_mode_changes(set, config);
7816
7817         ret = intel_modeset_stage_output_state(dev, set, config);
7818         if (ret)
7819                 goto fail;
7820
7821         if (config->mode_changed) {
7822                 if (set->mode) {
7823                         DRM_DEBUG_KMS("attempting to set mode from"
7824                                         " userspace\n");
7825                         drm_mode_debug_printmodeline(set->mode);
7826                 }
7827
7828                 if (!intel_set_mode(set->crtc, set->mode,
7829                                     set->x, set->y, set->fb)) {
7830                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7831                                   set->crtc->base.id);
7832                         ret = -EINVAL;
7833                         goto fail;
7834                 }
7835         } else if (config->fb_changed) {
7836                 ret = intel_pipe_set_base(set->crtc,
7837                                           set->x, set->y, set->fb);
7838         }
7839
7840         intel_set_config_free(config);
7841
7842         return 0;
7843
7844 fail:
7845         intel_set_config_restore_state(dev, config);
7846
7847         /* Try to restore the config */
7848         if (config->mode_changed &&
7849             !intel_set_mode(save_set.crtc, save_set.mode,
7850                             save_set.x, save_set.y, save_set.fb))
7851                 DRM_ERROR("failed to restore config after modeset failure\n");
7852
7853 out_config:
7854         intel_set_config_free(config);
7855         return ret;
7856 }
7857
7858 static const struct drm_crtc_funcs intel_crtc_funcs = {
7859         .cursor_set = intel_crtc_cursor_set,
7860         .cursor_move = intel_crtc_cursor_move,
7861         .gamma_set = intel_crtc_gamma_set,
7862         .set_config = intel_crtc_set_config,
7863         .destroy = intel_crtc_destroy,
7864         .page_flip = intel_crtc_page_flip,
7865 };
7866
7867 static void intel_cpu_pll_init(struct drm_device *dev)
7868 {
7869         if (IS_HASWELL(dev))
7870                 intel_ddi_pll_init(dev);
7871 }
7872
7873 static void intel_pch_pll_init(struct drm_device *dev)
7874 {
7875         drm_i915_private_t *dev_priv = dev->dev_private;
7876         int i;
7877
7878         if (dev_priv->num_pch_pll == 0) {
7879                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7880                 return;
7881         }
7882
7883         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7884                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7885                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7886                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7887         }
7888 }
7889
7890 static void intel_crtc_init(struct drm_device *dev, int pipe)
7891 {
7892         drm_i915_private_t *dev_priv = dev->dev_private;
7893         struct intel_crtc *intel_crtc;
7894         int i;
7895
7896         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7897         if (intel_crtc == NULL)
7898                 return;
7899
7900         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7901
7902         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7903         for (i = 0; i < 256; i++) {
7904                 intel_crtc->lut_r[i] = i;
7905                 intel_crtc->lut_g[i] = i;
7906                 intel_crtc->lut_b[i] = i;
7907         }
7908
7909         /* Swap pipes & planes for FBC on pre-965 */
7910         intel_crtc->pipe = pipe;
7911         intel_crtc->plane = pipe;
7912         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7913                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7914                 intel_crtc->plane = !pipe;
7915         }
7916
7917         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7918                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7919         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7920         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7921
7922         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7923
7924         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7925 }
7926
7927 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7928                                 struct drm_file *file)
7929 {
7930         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7931         struct drm_mode_object *drmmode_obj;
7932         struct intel_crtc *crtc;
7933
7934         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7935                 return -ENODEV;
7936
7937         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7938                         DRM_MODE_OBJECT_CRTC);
7939
7940         if (!drmmode_obj) {
7941                 DRM_ERROR("no such CRTC id\n");
7942                 return -EINVAL;
7943         }
7944
7945         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7946         pipe_from_crtc_id->pipe = crtc->pipe;
7947
7948         return 0;
7949 }
7950
7951 static int intel_encoder_clones(struct intel_encoder *encoder)
7952 {
7953         struct drm_device *dev = encoder->base.dev;
7954         struct intel_encoder *source_encoder;
7955         int index_mask = 0;
7956         int entry = 0;
7957
7958         list_for_each_entry(source_encoder,
7959                             &dev->mode_config.encoder_list, base.head) {
7960
7961                 if (encoder == source_encoder)
7962                         index_mask |= (1 << entry);
7963
7964                 /* Intel hw has only one MUX where enocoders could be cloned. */
7965                 if (encoder->cloneable && source_encoder->cloneable)
7966                         index_mask |= (1 << entry);
7967
7968                 entry++;
7969         }
7970
7971         return index_mask;
7972 }
7973
7974 static bool has_edp_a(struct drm_device *dev)
7975 {
7976         struct drm_i915_private *dev_priv = dev->dev_private;
7977
7978         if (!IS_MOBILE(dev))
7979                 return false;
7980
7981         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7982                 return false;
7983
7984         if (IS_GEN5(dev) &&
7985             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7986                 return false;
7987
7988         return true;
7989 }
7990
7991 static void intel_setup_outputs(struct drm_device *dev)
7992 {
7993         struct drm_i915_private *dev_priv = dev->dev_private;
7994         struct intel_encoder *encoder;
7995         bool dpd_is_edp = false;
7996         bool has_lvds;
7997
7998         has_lvds = intel_lvds_init(dev);
7999         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8000                 /* disable the panel fitter on everything but LVDS */
8001                 I915_WRITE(PFIT_CONTROL, 0);
8002         }
8003
8004         if (HAS_PCH_SPLIT(dev)) {
8005                 dpd_is_edp = intel_dpd_is_edp(dev);
8006
8007                 if (has_edp_a(dev))
8008                         intel_dp_init(dev, DP_A, PORT_A);
8009
8010                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8011                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8012         }
8013
8014         intel_crt_init(dev);
8015
8016         if (IS_HASWELL(dev)) {
8017                 int found;
8018
8019                 /* Haswell uses DDI functions to detect digital outputs */
8020                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8021                 /* DDI A only supports eDP */
8022                 if (found)
8023                         intel_ddi_init(dev, PORT_A);
8024
8025                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8026                  * register */
8027                 found = I915_READ(SFUSE_STRAP);
8028
8029                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8030                         intel_ddi_init(dev, PORT_B);
8031                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8032                         intel_ddi_init(dev, PORT_C);
8033                 if (found & SFUSE_STRAP_DDID_DETECTED)
8034                         intel_ddi_init(dev, PORT_D);
8035         } else if (HAS_PCH_SPLIT(dev)) {
8036                 int found;
8037
8038                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8039                         /* PCH SDVOB multiplex with HDMIB */
8040                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8041                         if (!found)
8042                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8043                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8044                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8045                 }
8046
8047                 if (I915_READ(HDMIC) & PORT_DETECTED)
8048                         intel_hdmi_init(dev, HDMIC, PORT_C);
8049
8050                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8051                         intel_hdmi_init(dev, HDMID, PORT_D);
8052
8053                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8054                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8055
8056                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8057                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8058         } else if (IS_VALLEYVIEW(dev)) {
8059                 int found;
8060
8061                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8062                 if (I915_READ(DP_C) & DP_DETECTED)
8063                         intel_dp_init(dev, DP_C, PORT_C);
8064
8065                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8066                         /* SDVOB multiplex with HDMIB */
8067                         found = intel_sdvo_init(dev, SDVOB, true);
8068                         if (!found)
8069                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8070                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8071                                 intel_dp_init(dev, DP_B, PORT_B);
8072                 }
8073
8074                 if (I915_READ(SDVOC) & PORT_DETECTED)
8075                         intel_hdmi_init(dev, SDVOC, PORT_C);
8076
8077         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8078                 bool found = false;
8079
8080                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8081                         DRM_DEBUG_KMS("probing SDVOB\n");
8082                         found = intel_sdvo_init(dev, SDVOB, true);
8083                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8084                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8085                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8086                         }
8087
8088                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8089                                 DRM_DEBUG_KMS("probing DP_B\n");
8090                                 intel_dp_init(dev, DP_B, PORT_B);
8091                         }
8092                 }
8093
8094                 /* Before G4X SDVOC doesn't have its own detect register */
8095
8096                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8097                         DRM_DEBUG_KMS("probing SDVOC\n");
8098                         found = intel_sdvo_init(dev, SDVOC, false);
8099                 }
8100
8101                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8102
8103                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8104                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8105                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8106                         }
8107                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8108                                 DRM_DEBUG_KMS("probing DP_C\n");
8109                                 intel_dp_init(dev, DP_C, PORT_C);
8110                         }
8111                 }
8112
8113                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8114                     (I915_READ(DP_D) & DP_DETECTED)) {
8115                         DRM_DEBUG_KMS("probing DP_D\n");
8116                         intel_dp_init(dev, DP_D, PORT_D);
8117                 }
8118         } else if (IS_GEN2(dev))
8119                 intel_dvo_init(dev);
8120
8121         if (SUPPORTS_TV(dev))
8122                 intel_tv_init(dev);
8123
8124         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8125                 encoder->base.possible_crtcs = encoder->crtc_mask;
8126                 encoder->base.possible_clones =
8127                         intel_encoder_clones(encoder);
8128         }
8129
8130         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8131                 ironlake_init_pch_refclk(dev);
8132 }
8133
8134 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8135 {
8136         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8137
8138         drm_framebuffer_cleanup(fb);
8139         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8140
8141         kfree(intel_fb);
8142 }
8143
8144 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8145                                                 struct drm_file *file,
8146                                                 unsigned int *handle)
8147 {
8148         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8149         struct drm_i915_gem_object *obj = intel_fb->obj;
8150
8151         return drm_gem_handle_create(file, &obj->base, handle);
8152 }
8153
8154 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8155         .destroy = intel_user_framebuffer_destroy,
8156         .create_handle = intel_user_framebuffer_create_handle,
8157 };
8158
8159 int intel_framebuffer_init(struct drm_device *dev,
8160                            struct intel_framebuffer *intel_fb,
8161                            struct drm_mode_fb_cmd2 *mode_cmd,
8162                            struct drm_i915_gem_object *obj)
8163 {
8164         int ret;
8165
8166         if (obj->tiling_mode == I915_TILING_Y)
8167                 return -EINVAL;
8168
8169         if (mode_cmd->pitches[0] & 63)
8170                 return -EINVAL;
8171
8172         switch (mode_cmd->pixel_format) {
8173         case DRM_FORMAT_RGB332:
8174         case DRM_FORMAT_RGB565:
8175         case DRM_FORMAT_XRGB8888:
8176         case DRM_FORMAT_XBGR8888:
8177         case DRM_FORMAT_ARGB8888:
8178         case DRM_FORMAT_XRGB2101010:
8179         case DRM_FORMAT_ARGB2101010:
8180                 /* RGB formats are common across chipsets */
8181                 break;
8182         case DRM_FORMAT_YUYV:
8183         case DRM_FORMAT_UYVY:
8184         case DRM_FORMAT_YVYU:
8185         case DRM_FORMAT_VYUY:
8186                 break;
8187         default:
8188                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8189                                 mode_cmd->pixel_format);
8190                 return -EINVAL;
8191         }
8192
8193         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8194         if (ret) {
8195                 DRM_ERROR("framebuffer init failed %d\n", ret);
8196                 return ret;
8197         }
8198
8199         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8200         intel_fb->obj = obj;
8201         return 0;
8202 }
8203
8204 static struct drm_framebuffer *
8205 intel_user_framebuffer_create(struct drm_device *dev,
8206                               struct drm_file *filp,
8207                               struct drm_mode_fb_cmd2 *mode_cmd)
8208 {
8209         struct drm_i915_gem_object *obj;
8210
8211         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8212                                                 mode_cmd->handles[0]));
8213         if (&obj->base == NULL)
8214                 return ERR_PTR(-ENOENT);
8215
8216         return intel_framebuffer_create(dev, mode_cmd, obj);
8217 }
8218
8219 static const struct drm_mode_config_funcs intel_mode_funcs = {
8220         .fb_create = intel_user_framebuffer_create,
8221         .output_poll_changed = intel_fb_output_poll_changed,
8222 };
8223
8224 /* Set up chip specific display functions */
8225 static void intel_init_display(struct drm_device *dev)
8226 {
8227         struct drm_i915_private *dev_priv = dev->dev_private;
8228
8229         /* We always want a DPMS function */
8230         if (IS_HASWELL(dev)) {
8231                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8232                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8233                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8234                 dev_priv->display.off = haswell_crtc_off;
8235                 dev_priv->display.update_plane = ironlake_update_plane;
8236         } else if (HAS_PCH_SPLIT(dev)) {
8237                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8238                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8239                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8240                 dev_priv->display.off = ironlake_crtc_off;
8241                 dev_priv->display.update_plane = ironlake_update_plane;
8242         } else {
8243                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8244                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8245                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8246                 dev_priv->display.off = i9xx_crtc_off;
8247                 dev_priv->display.update_plane = i9xx_update_plane;
8248         }
8249
8250         /* Returns the core display clock speed */
8251         if (IS_VALLEYVIEW(dev))
8252                 dev_priv->display.get_display_clock_speed =
8253                         valleyview_get_display_clock_speed;
8254         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8255                 dev_priv->display.get_display_clock_speed =
8256                         i945_get_display_clock_speed;
8257         else if (IS_I915G(dev))
8258                 dev_priv->display.get_display_clock_speed =
8259                         i915_get_display_clock_speed;
8260         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8261                 dev_priv->display.get_display_clock_speed =
8262                         i9xx_misc_get_display_clock_speed;
8263         else if (IS_I915GM(dev))
8264                 dev_priv->display.get_display_clock_speed =
8265                         i915gm_get_display_clock_speed;
8266         else if (IS_I865G(dev))
8267                 dev_priv->display.get_display_clock_speed =
8268                         i865_get_display_clock_speed;
8269         else if (IS_I85X(dev))
8270                 dev_priv->display.get_display_clock_speed =
8271                         i855_get_display_clock_speed;
8272         else /* 852, 830 */
8273                 dev_priv->display.get_display_clock_speed =
8274                         i830_get_display_clock_speed;
8275
8276         if (HAS_PCH_SPLIT(dev)) {
8277                 if (IS_GEN5(dev)) {
8278                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8279                         dev_priv->display.write_eld = ironlake_write_eld;
8280                 } else if (IS_GEN6(dev)) {
8281                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8282                         dev_priv->display.write_eld = ironlake_write_eld;
8283                 } else if (IS_IVYBRIDGE(dev)) {
8284                         /* FIXME: detect B0+ stepping and use auto training */
8285                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8286                         dev_priv->display.write_eld = ironlake_write_eld;
8287                 } else if (IS_HASWELL(dev)) {
8288                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8289                         dev_priv->display.write_eld = haswell_write_eld;
8290                 } else
8291                         dev_priv->display.update_wm = NULL;
8292         } else if (IS_G4X(dev)) {
8293                 dev_priv->display.write_eld = g4x_write_eld;
8294         }
8295
8296         /* Default just returns -ENODEV to indicate unsupported */
8297         dev_priv->display.queue_flip = intel_default_queue_flip;
8298
8299         switch (INTEL_INFO(dev)->gen) {
8300         case 2:
8301                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8302                 break;
8303
8304         case 3:
8305                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8306                 break;
8307
8308         case 4:
8309         case 5:
8310                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8311                 break;
8312
8313         case 6:
8314                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8315                 break;
8316         case 7:
8317                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8318                 break;
8319         }
8320 }
8321
8322 /*
8323  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8324  * resume, or other times.  This quirk makes sure that's the case for
8325  * affected systems.
8326  */
8327 static void quirk_pipea_force(struct drm_device *dev)
8328 {
8329         struct drm_i915_private *dev_priv = dev->dev_private;
8330
8331         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8332         DRM_INFO("applying pipe a force quirk\n");
8333 }
8334
8335 /*
8336  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8337  */
8338 static void quirk_ssc_force_disable(struct drm_device *dev)
8339 {
8340         struct drm_i915_private *dev_priv = dev->dev_private;
8341         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8342         DRM_INFO("applying lvds SSC disable quirk\n");
8343 }
8344
8345 /*
8346  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8347  * brightness value
8348  */
8349 static void quirk_invert_brightness(struct drm_device *dev)
8350 {
8351         struct drm_i915_private *dev_priv = dev->dev_private;
8352         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8353         DRM_INFO("applying inverted panel brightness quirk\n");
8354 }
8355
8356 struct intel_quirk {
8357         int device;
8358         int subsystem_vendor;
8359         int subsystem_device;
8360         void (*hook)(struct drm_device *dev);
8361 };
8362
8363 static struct intel_quirk intel_quirks[] = {
8364         /* HP Mini needs pipe A force quirk (LP: #322104) */
8365         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8366
8367         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8368         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8369
8370         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8371         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8372
8373         /* 830/845 need to leave pipe A & dpll A up */
8374         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8375         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8376
8377         /* Lenovo U160 cannot use SSC on LVDS */
8378         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8379
8380         /* Sony Vaio Y cannot use SSC on LVDS */
8381         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8382
8383         /* Acer Aspire 5734Z must invert backlight brightness */
8384         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8385 };
8386
8387 static void intel_init_quirks(struct drm_device *dev)
8388 {
8389         struct pci_dev *d = dev->pdev;
8390         int i;
8391
8392         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8393                 struct intel_quirk *q = &intel_quirks[i];
8394
8395                 if (d->device == q->device &&
8396                     (d->subsystem_vendor == q->subsystem_vendor ||
8397                      q->subsystem_vendor == PCI_ANY_ID) &&
8398                     (d->subsystem_device == q->subsystem_device ||
8399                      q->subsystem_device == PCI_ANY_ID))
8400                         q->hook(dev);
8401         }
8402 }
8403
8404 /* Disable the VGA plane that we never use */
8405 static void i915_disable_vga(struct drm_device *dev)
8406 {
8407         struct drm_i915_private *dev_priv = dev->dev_private;
8408         u8 sr1;
8409         u32 vga_reg;
8410
8411         if (HAS_PCH_SPLIT(dev))
8412                 vga_reg = CPU_VGACNTRL;
8413         else
8414                 vga_reg = VGACNTRL;
8415
8416         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8417         outb(SR01, VGA_SR_INDEX);
8418         sr1 = inb(VGA_SR_DATA);
8419         outb(sr1 | 1<<5, VGA_SR_DATA);
8420         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8421         udelay(300);
8422
8423         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8424         POSTING_READ(vga_reg);
8425 }
8426
8427 void intel_modeset_init_hw(struct drm_device *dev)
8428 {
8429         /* We attempt to init the necessary power wells early in the initialization
8430          * time, so the subsystems that expect power to be enabled can work.
8431          */
8432         intel_init_power_wells(dev);
8433
8434         intel_prepare_ddi(dev);
8435
8436         intel_init_clock_gating(dev);
8437
8438         mutex_lock(&dev->struct_mutex);
8439         intel_enable_gt_powersave(dev);
8440         mutex_unlock(&dev->struct_mutex);
8441 }
8442
8443 void intel_modeset_init(struct drm_device *dev)
8444 {
8445         struct drm_i915_private *dev_priv = dev->dev_private;
8446         int i, ret;
8447
8448         drm_mode_config_init(dev);
8449
8450         dev->mode_config.min_width = 0;
8451         dev->mode_config.min_height = 0;
8452
8453         dev->mode_config.preferred_depth = 24;
8454         dev->mode_config.prefer_shadow = 1;
8455
8456         dev->mode_config.funcs = &intel_mode_funcs;
8457
8458         intel_init_quirks(dev);
8459
8460         intel_init_pm(dev);
8461
8462         intel_init_display(dev);
8463
8464         if (IS_GEN2(dev)) {
8465                 dev->mode_config.max_width = 2048;
8466                 dev->mode_config.max_height = 2048;
8467         } else if (IS_GEN3(dev)) {
8468                 dev->mode_config.max_width = 4096;
8469                 dev->mode_config.max_height = 4096;
8470         } else {
8471                 dev->mode_config.max_width = 8192;
8472                 dev->mode_config.max_height = 8192;
8473         }
8474         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8475
8476         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8477                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8478
8479         for (i = 0; i < dev_priv->num_pipe; i++) {
8480                 intel_crtc_init(dev, i);
8481                 ret = intel_plane_init(dev, i);
8482                 if (ret)
8483                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8484         }
8485
8486         intel_cpu_pll_init(dev);
8487         intel_pch_pll_init(dev);
8488
8489         /* Just disable it once at startup */
8490         i915_disable_vga(dev);
8491         intel_setup_outputs(dev);
8492 }
8493
8494 static void
8495 intel_connector_break_all_links(struct intel_connector *connector)
8496 {
8497         connector->base.dpms = DRM_MODE_DPMS_OFF;
8498         connector->base.encoder = NULL;
8499         connector->encoder->connectors_active = false;
8500         connector->encoder->base.crtc = NULL;
8501 }
8502
8503 static void intel_enable_pipe_a(struct drm_device *dev)
8504 {
8505         struct intel_connector *connector;
8506         struct drm_connector *crt = NULL;
8507         struct intel_load_detect_pipe load_detect_temp;
8508
8509         /* We can't just switch on the pipe A, we need to set things up with a
8510          * proper mode and output configuration. As a gross hack, enable pipe A
8511          * by enabling the load detect pipe once. */
8512         list_for_each_entry(connector,
8513                             &dev->mode_config.connector_list,
8514                             base.head) {
8515                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8516                         crt = &connector->base;
8517                         break;
8518                 }
8519         }
8520
8521         if (!crt)
8522                 return;
8523
8524         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8525                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8526
8527
8528 }
8529
8530 static bool
8531 intel_check_plane_mapping(struct intel_crtc *crtc)
8532 {
8533         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8534         u32 reg, val;
8535
8536         if (dev_priv->num_pipe == 1)
8537                 return true;
8538
8539         reg = DSPCNTR(!crtc->plane);
8540         val = I915_READ(reg);
8541
8542         if ((val & DISPLAY_PLANE_ENABLE) &&
8543             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8544                 return false;
8545
8546         return true;
8547 }
8548
8549 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8550 {
8551         struct drm_device *dev = crtc->base.dev;
8552         struct drm_i915_private *dev_priv = dev->dev_private;
8553         u32 reg;
8554
8555         /* Clear any frame start delays used for debugging left by the BIOS */
8556         reg = PIPECONF(crtc->pipe);
8557         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8558
8559         /* We need to sanitize the plane -> pipe mapping first because this will
8560          * disable the crtc (and hence change the state) if it is wrong. Note
8561          * that gen4+ has a fixed plane -> pipe mapping.  */
8562         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8563                 struct intel_connector *connector;
8564                 bool plane;
8565
8566                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8567                               crtc->base.base.id);
8568
8569                 /* Pipe has the wrong plane attached and the plane is active.
8570                  * Temporarily change the plane mapping and disable everything
8571                  * ...  */
8572                 plane = crtc->plane;
8573                 crtc->plane = !plane;
8574                 dev_priv->display.crtc_disable(&crtc->base);
8575                 crtc->plane = plane;
8576
8577                 /* ... and break all links. */
8578                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8579                                     base.head) {
8580                         if (connector->encoder->base.crtc != &crtc->base)
8581                                 continue;
8582
8583                         intel_connector_break_all_links(connector);
8584                 }
8585
8586                 WARN_ON(crtc->active);
8587                 crtc->base.enabled = false;
8588         }
8589
8590         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8591             crtc->pipe == PIPE_A && !crtc->active) {
8592                 /* BIOS forgot to enable pipe A, this mostly happens after
8593                  * resume. Force-enable the pipe to fix this, the update_dpms
8594                  * call below we restore the pipe to the right state, but leave
8595                  * the required bits on. */
8596                 intel_enable_pipe_a(dev);
8597         }
8598
8599         /* Adjust the state of the output pipe according to whether we
8600          * have active connectors/encoders. */
8601         intel_crtc_update_dpms(&crtc->base);
8602
8603         if (crtc->active != crtc->base.enabled) {
8604                 struct intel_encoder *encoder;
8605
8606                 /* This can happen either due to bugs in the get_hw_state
8607                  * functions or because the pipe is force-enabled due to the
8608                  * pipe A quirk. */
8609                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8610                               crtc->base.base.id,
8611                               crtc->base.enabled ? "enabled" : "disabled",
8612                               crtc->active ? "enabled" : "disabled");
8613
8614                 crtc->base.enabled = crtc->active;
8615
8616                 /* Because we only establish the connector -> encoder ->
8617                  * crtc links if something is active, this means the
8618                  * crtc is now deactivated. Break the links. connector
8619                  * -> encoder links are only establish when things are
8620                  *  actually up, hence no need to break them. */
8621                 WARN_ON(crtc->active);
8622
8623                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8624                         WARN_ON(encoder->connectors_active);
8625                         encoder->base.crtc = NULL;
8626                 }
8627         }
8628 }
8629
8630 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8631 {
8632         struct intel_connector *connector;
8633         struct drm_device *dev = encoder->base.dev;
8634
8635         /* We need to check both for a crtc link (meaning that the
8636          * encoder is active and trying to read from a pipe) and the
8637          * pipe itself being active. */
8638         bool has_active_crtc = encoder->base.crtc &&
8639                 to_intel_crtc(encoder->base.crtc)->active;
8640
8641         if (encoder->connectors_active && !has_active_crtc) {
8642                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8643                               encoder->base.base.id,
8644                               drm_get_encoder_name(&encoder->base));
8645
8646                 /* Connector is active, but has no active pipe. This is
8647                  * fallout from our resume register restoring. Disable
8648                  * the encoder manually again. */
8649                 if (encoder->base.crtc) {
8650                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8651                                       encoder->base.base.id,
8652                                       drm_get_encoder_name(&encoder->base));
8653                         encoder->disable(encoder);
8654                 }
8655
8656                 /* Inconsistent output/port/pipe state happens presumably due to
8657                  * a bug in one of the get_hw_state functions. Or someplace else
8658                  * in our code, like the register restore mess on resume. Clamp
8659                  * things to off as a safer default. */
8660                 list_for_each_entry(connector,
8661                                     &dev->mode_config.connector_list,
8662                                     base.head) {
8663                         if (connector->encoder != encoder)
8664                                 continue;
8665
8666                         intel_connector_break_all_links(connector);
8667                 }
8668         }
8669         /* Enabled encoders without active connectors will be fixed in
8670          * the crtc fixup. */
8671 }
8672
8673 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8674  * and i915 state tracking structures. */
8675 void intel_modeset_setup_hw_state(struct drm_device *dev)
8676 {
8677         struct drm_i915_private *dev_priv = dev->dev_private;
8678         enum pipe pipe;
8679         u32 tmp;
8680         struct intel_crtc *crtc;
8681         struct intel_encoder *encoder;
8682         struct intel_connector *connector;
8683
8684         for_each_pipe(pipe) {
8685                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8686
8687                 tmp = I915_READ(PIPECONF(pipe));
8688                 if (tmp & PIPECONF_ENABLE)
8689                         crtc->active = true;
8690                 else
8691                         crtc->active = false;
8692
8693                 crtc->base.enabled = crtc->active;
8694
8695                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8696                               crtc->base.base.id,
8697                               crtc->active ? "enabled" : "disabled");
8698         }
8699
8700         if (IS_HASWELL(dev))
8701                 intel_ddi_setup_hw_pll_state(dev);
8702
8703         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8704                             base.head) {
8705                 pipe = 0;
8706
8707                 if (encoder->get_hw_state(encoder, &pipe)) {
8708                         encoder->base.crtc =
8709                                 dev_priv->pipe_to_crtc_mapping[pipe];
8710                 } else {
8711                         encoder->base.crtc = NULL;
8712                 }
8713
8714                 encoder->connectors_active = false;
8715                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8716                               encoder->base.base.id,
8717                               drm_get_encoder_name(&encoder->base),
8718                               encoder->base.crtc ? "enabled" : "disabled",
8719                               pipe);
8720         }
8721
8722         list_for_each_entry(connector, &dev->mode_config.connector_list,
8723                             base.head) {
8724                 if (connector->get_hw_state(connector)) {
8725                         connector->base.dpms = DRM_MODE_DPMS_ON;
8726                         connector->encoder->connectors_active = true;
8727                         connector->base.encoder = &connector->encoder->base;
8728                 } else {
8729                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8730                         connector->base.encoder = NULL;
8731                 }
8732                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8733                               connector->base.base.id,
8734                               drm_get_connector_name(&connector->base),
8735                               connector->base.encoder ? "enabled" : "disabled");
8736         }
8737
8738         /* HW state is read out, now we need to sanitize this mess. */
8739         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8740                             base.head) {
8741                 intel_sanitize_encoder(encoder);
8742         }
8743
8744         for_each_pipe(pipe) {
8745                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8746                 intel_sanitize_crtc(crtc);
8747         }
8748
8749         intel_modeset_update_staged_output_state(dev);
8750
8751         intel_modeset_check_state(dev);
8752
8753         drm_mode_config_reset(dev);
8754 }
8755
8756 void intel_modeset_gem_init(struct drm_device *dev)
8757 {
8758         intel_modeset_init_hw(dev);
8759
8760         intel_setup_overlay(dev);
8761
8762         intel_modeset_setup_hw_state(dev);
8763 }
8764
8765 void intel_modeset_cleanup(struct drm_device *dev)
8766 {
8767         struct drm_i915_private *dev_priv = dev->dev_private;
8768         struct drm_crtc *crtc;
8769         struct intel_crtc *intel_crtc;
8770
8771         drm_kms_helper_poll_fini(dev);
8772         mutex_lock(&dev->struct_mutex);
8773
8774         intel_unregister_dsm_handler();
8775
8776
8777         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8778                 /* Skip inactive CRTCs */
8779                 if (!crtc->fb)
8780                         continue;
8781
8782                 intel_crtc = to_intel_crtc(crtc);
8783                 intel_increase_pllclock(crtc);
8784         }
8785
8786         intel_disable_fbc(dev);
8787
8788         intel_disable_gt_powersave(dev);
8789
8790         ironlake_teardown_rc6(dev);
8791
8792         if (IS_VALLEYVIEW(dev))
8793                 vlv_init_dpio(dev);
8794
8795         mutex_unlock(&dev->struct_mutex);
8796
8797         /* Disable the irq before mode object teardown, for the irq might
8798          * enqueue unpin/hotplug work. */
8799         drm_irq_uninstall(dev);
8800         cancel_work_sync(&dev_priv->hotplug_work);
8801         cancel_work_sync(&dev_priv->rps.work);
8802
8803         /* flush any delayed tasks or pending work */
8804         flush_scheduled_work();
8805
8806         drm_mode_config_cleanup(dev);
8807 }
8808
8809 /*
8810  * Return which encoder is currently attached for connector.
8811  */
8812 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8813 {
8814         return &intel_attached_encoder(connector)->base;
8815 }
8816
8817 void intel_connector_attach_encoder(struct intel_connector *connector,
8818                                     struct intel_encoder *encoder)
8819 {
8820         connector->encoder = encoder;
8821         drm_mode_connector_attach_encoder(&connector->base,
8822                                           &encoder->base);
8823 }
8824
8825 /*
8826  * set vga decode state - true == enable VGA decode
8827  */
8828 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         u16 gmch_ctrl;
8832
8833         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8834         if (state)
8835                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8836         else
8837                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8838         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8839         return 0;
8840 }
8841
8842 #ifdef CONFIG_DEBUG_FS
8843 #include <linux/seq_file.h>
8844
8845 struct intel_display_error_state {
8846         struct intel_cursor_error_state {
8847                 u32 control;
8848                 u32 position;
8849                 u32 base;
8850                 u32 size;
8851         } cursor[I915_MAX_PIPES];
8852
8853         struct intel_pipe_error_state {
8854                 u32 conf;
8855                 u32 source;
8856
8857                 u32 htotal;
8858                 u32 hblank;
8859                 u32 hsync;
8860                 u32 vtotal;
8861                 u32 vblank;
8862                 u32 vsync;
8863         } pipe[I915_MAX_PIPES];
8864
8865         struct intel_plane_error_state {
8866                 u32 control;
8867                 u32 stride;
8868                 u32 size;
8869                 u32 pos;
8870                 u32 addr;
8871                 u32 surface;
8872                 u32 tile_offset;
8873         } plane[I915_MAX_PIPES];
8874 };
8875
8876 struct intel_display_error_state *
8877 intel_display_capture_error_state(struct drm_device *dev)
8878 {
8879         drm_i915_private_t *dev_priv = dev->dev_private;
8880         struct intel_display_error_state *error;
8881         int i;
8882
8883         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8884         if (error == NULL)
8885                 return NULL;
8886
8887         for_each_pipe(i) {
8888                 error->cursor[i].control = I915_READ(CURCNTR(i));
8889                 error->cursor[i].position = I915_READ(CURPOS(i));
8890                 error->cursor[i].base = I915_READ(CURBASE(i));
8891
8892                 error->plane[i].control = I915_READ(DSPCNTR(i));
8893                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8894                 error->plane[i].size = I915_READ(DSPSIZE(i));
8895                 error->plane[i].pos = I915_READ(DSPPOS(i));
8896                 error->plane[i].addr = I915_READ(DSPADDR(i));
8897                 if (INTEL_INFO(dev)->gen >= 4) {
8898                         error->plane[i].surface = I915_READ(DSPSURF(i));
8899                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8900                 }
8901
8902                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8903                 error->pipe[i].source = I915_READ(PIPESRC(i));
8904                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8905                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8906                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8907                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8908                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8909                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8910         }
8911
8912         return error;
8913 }
8914
8915 void
8916 intel_display_print_error_state(struct seq_file *m,
8917                                 struct drm_device *dev,
8918                                 struct intel_display_error_state *error)
8919 {
8920         drm_i915_private_t *dev_priv = dev->dev_private;
8921         int i;
8922
8923         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8924         for_each_pipe(i) {
8925                 seq_printf(m, "Pipe [%d]:\n", i);
8926                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8927                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8928                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8929                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8930                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8931                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8932                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8933                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8934
8935                 seq_printf(m, "Plane [%d]:\n", i);
8936                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8937                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8938                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8939                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8940                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8941                 if (INTEL_INFO(dev)->gen >= 4) {
8942                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8943                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8944                 }
8945
8946                 seq_printf(m, "Cursor [%d]:\n", i);
8947                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8948                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8949                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8950         }
8951 }
8952 #endif