Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 10, .max = 22 },
 172         .m2 = { .min = 5, .max = 9 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         unsigned long flags;
 420         u32 val = 0;
 421
 422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO idle wait timed out\n");
 425                 goto out_unlock;
 426         }
 427
 428         I915_WRITE(DPIO_REG, reg);
 429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 430                    DPIO_BYTE);
 431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 432                 DRM_ERROR("DPIO read wait timed out\n");
 433                 goto out_unlock;
 434         }
 435         val = I915_READ(DPIO_DATA);
 436
 437 out_unlock:
 438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 439         return val;
 440 }
 441
 442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 443                              u32 val)
 444 {
 445         unsigned long flags;
 446
 447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 449                 DRM_ERROR("DPIO idle wait timed out\n");
 450                 goto out_unlock;
 451         }
 452
 453         I915_WRITE(DPIO_DATA, val);
 454         I915_WRITE(DPIO_REG, reg);
 455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 456                    DPIO_BYTE);
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 458                 DRM_ERROR("DPIO write wait timed out\n");
 459
 460 out_unlock:
 461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 462 }
 463
 464 static void vlv_init_dpio(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         /* Reset the DPIO config */
 469         I915_WRITE(DPIO_CTL, 0);
 470         POSTING_READ(DPIO_CTL);
 471         I915_WRITE(DPIO_CTL, 1);
 472         POSTING_READ(DPIO_CTL);
 473 }
 474
 475 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 476                                                 int refclk)
 477 {
 478         struct drm_device *dev = crtc->dev;
 479         const intel_limit_t *limit;
 480
 481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 482                 if (intel_is_dual_link_lvds(dev)) {
 483                         /* LVDS dual channel */
 484                         if (refclk == 100000)
 485                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 486                         else
 487                                 limit = &intel_limits_ironlake_dual_lvds;
 488                 } else {
 489                         if (refclk == 100000)
 490                                 limit = &intel_limits_ironlake_single_lvds_100m;
 491                         else
 492                                 limit = &intel_limits_ironlake_single_lvds;
 493                 }
 494         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 495                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 496                 limit = &intel_limits_ironlake_display_port;
 497         else
 498                 limit = &intel_limits_ironlake_dac;
 499
 500         return limit;
 501 }
 502
 503 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         const intel_limit_t *limit;
 507
 508         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 509                 if (intel_is_dual_link_lvds(dev))
 510                         /* LVDS with dual channel */
 511                         limit = &intel_limits_g4x_dual_channel_lvds;
 512                 else
 513                         /* LVDS with dual channel */
 514                         limit = &intel_limits_g4x_single_channel_lvds;
 515         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 516                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 517                 limit = &intel_limits_g4x_hdmi;
 518         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 519                 limit = &intel_limits_g4x_sdvo;
 520         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 521                 limit = &intel_limits_g4x_display_port;
 522         } else /* The option is for other outputs */
 523                 limit = &intel_limits_i9xx_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         const intel_limit_t *limit;
 532
 533         if (HAS_PCH_SPLIT(dev))
 534                 limit = intel_ironlake_limit(crtc, refclk);
 535         else if (IS_G4X(dev)) {
 536                 limit = intel_g4x_limit(crtc);
 537         } else if (IS_PINEVIEW(dev)) {
 538                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_pineview_lvds;
 540                 else
 541                         limit = &intel_limits_pineview_sdvo;
 542         } else if (IS_VALLEYVIEW(dev)) {
 543                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 544                         limit = &intel_limits_vlv_dac;
 545                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 546                         limit = &intel_limits_vlv_hdmi;
 547                 else
 548                         limit = &intel_limits_vlv_dp;
 549         } else if (!IS_GEN2(dev)) {
 550                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 551                         limit = &intel_limits_i9xx_lvds;
 552                 else
 553                         limit = &intel_limits_i9xx_sdvo;
 554         } else {
 555                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 556                         limit = &intel_limits_i8xx_lvds;
 557                 else
 558                         limit = &intel_limits_i8xx_dvo;
 559         }
 560         return limit;
 561 }
 562
 563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 564 static void pineview_clock(int refclk, intel_clock_t *clock)
 565 {
 566         clock->m = clock->m2 + 2;
 567         clock->p = clock->p1 * clock->p2;
 568         clock->vco = refclk * clock->m / clock->n;
 569         clock->dot = clock->vco / clock->p;
 570 }
 571
 572 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 573 {
 574         if (IS_PINEVIEW(dev)) {
 575                 pineview_clock(refclk, clock);
 576                 return;
 577         }
 578         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 579         clock->p = clock->p1 * clock->p2;
 580         clock->vco = refclk * clock->m / (clock->n + 2);
 581         clock->dot = clock->vco / clock->p;
 582 }
 583
 584 /**
 585  * Returns whether any output on the specified pipe is of the specified type
 586  */
 587 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 588 {
 589         struct drm_device *dev = crtc->dev;
 590         struct intel_encoder *encoder;
 591
 592         for_each_encoder_on_crtc(dev, crtc, encoder)
 593                 if (encoder->type == type)
 594                         return true;
 595
 596         return false;
 597 }
 598
 599 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 600 /**
 601  * Returns whether the given set of divisors are valid for a given refclk with
 602  * the given connectors.
 603  */
 604
 605 static bool intel_PLL_is_valid(struct drm_device *dev,
 606                                const intel_limit_t *limit,
 607                                const intel_clock_t *clock)
 608 {
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 612                 INTELPllInvalid("p out of range\n");
 613         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 614                 INTELPllInvalid("m2 out of range\n");
 615         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 616                 INTELPllInvalid("m1 out of range\n");
 617         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 618                 INTELPllInvalid("m1 <= m2\n");
 619         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 620                 INTELPllInvalid("m out of range\n");
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 624                 INTELPllInvalid("vco out of range\n");
 625         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 626          * connector, etc., rather than just a single range.
 627          */
 628         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 629                 INTELPllInvalid("dot out of range\n");
 630
 631         return true;
 632 }
 633
 634 static bool
 635 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 636                     int target, int refclk, intel_clock_t *match_clock,
 637                     intel_clock_t *best_clock)
 638
 639 {
 640         struct drm_device *dev = crtc->dev;
 641         intel_clock_t clock;
 642         int err = target;
 643
 644         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 645                 /*
 646                  * For LVDS just rely on its current settings for dual-channel.
 647                  * We haven't figured out how to reliably set up different
 648                  * single/dual channel state, if we even can.
 649                  */
 650                 if (intel_is_dual_link_lvds(dev))
 651                         clock.p2 = limit->p2.p2_fast;
 652                 else
 653                         clock.p2 = limit->p2.p2_slow;
 654         } else {
 655                 if (target < limit->p2.dot_limit)
 656                         clock.p2 = limit->p2.p2_slow;
 657                 else
 658                         clock.p2 = limit->p2.p2_fast;
 659         }
 660
 661         memset(best_clock, 0, sizeof(*best_clock));
 662
 663         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 664              clock.m1++) {
 665                 for (clock.m2 = limit->m2.min;
 666                      clock.m2 <= limit->m2.max; clock.m2++) {
 667                         /* m1 is always 0 in Pineview */
 668                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 669                                 break;
 670                         for (clock.n = limit->n.min;
 671                              clock.n <= limit->n.max; clock.n++) {
 672                                 for (clock.p1 = limit->p1.min;
 673                                         clock.p1 <= limit->p1.max; clock.p1++) {
 674                                         int this_err;
 675
 676                                         intel_clock(dev, refclk, &clock);
 677                                         if (!intel_PLL_is_valid(dev, limit,
 678                                                                 &clock))
 679                                                 continue;
 680                                         if (match_clock &&
 681                                             clock.p != match_clock->p)
 682                                                 continue;
 683
 684                                         this_err = abs(clock.dot - target);
 685                                         if (this_err < err) {
 686                                                 *best_clock = clock;
 687                                                 err = this_err;
 688                                         }
 689                                 }
 690                         }
 691                 }
 692         }
 693
 694         return (err != target);
 695 }
 696
 697 static bool
 698 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 699                         int target, int refclk, intel_clock_t *match_clock,
 700                         intel_clock_t *best_clock)
 701 {
 702         struct drm_device *dev = crtc->dev;
 703         intel_clock_t clock;
 704         int max_n;
 705         bool found;
 706         /* approximately equals target * 0.00585 */
 707         int err_most = (target >> 8) + (target >> 9);
 708         found = false;
 709
 710         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 711                 int lvds_reg;
 712
 713                 if (HAS_PCH_SPLIT(dev))
 714                         lvds_reg = PCH_LVDS;
 715                 else
 716                         lvds_reg = LVDS;
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requirement, prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirement, prefere larger m1,m2 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         intel_clock(dev, refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745                                         if (match_clock &&
 746                                             clock.p != match_clock->p)
 747                                                 continue;
 748
 749                                         this_err = abs(clock.dot - target);
 750                                         if (this_err < err_most) {
 751                                                 *best_clock = clock;
 752                                                 err_most = this_err;
 753                                                 max_n = clock.n;
 754                                                 found = true;
 755                                         }
 756                                 }
 757                         }
 758                 }
 759         }
 760         return found;
 761 }
 762
 763 static bool
 764 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 765                            int target, int refclk, intel_clock_t *match_clock,
 766                            intel_clock_t *best_clock)
 767 {
 768         struct drm_device *dev = crtc->dev;
 769         intel_clock_t clock;
 770
 771         if (target < 200000) {
 772                 clock.n = 1;
 773                 clock.p1 = 2;
 774                 clock.p2 = 10;
 775                 clock.m1 = 12;
 776                 clock.m2 = 9;
 777         } else {
 778                 clock.n = 2;
 779                 clock.p1 = 1;
 780                 clock.p2 = 10;
 781                 clock.m1 = 14;
 782                 clock.m2 = 8;
 783         }
 784         intel_clock(dev, refclk, &clock);
 785         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 786         return true;
 787 }
 788
 789 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 790 static bool
 791 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 792                       int target, int refclk, intel_clock_t *match_clock,
 793                       intel_clock_t *best_clock)
 794 {
 795         intel_clock_t clock;
 796         if (target < 200000) {
 797                 clock.p1 = 2;
 798                 clock.p2 = 10;
 799                 clock.n = 2;
 800                 clock.m1 = 23;
 801                 clock.m2 = 8;
 802         } else {
 803                 clock.p1 = 1;
 804                 clock.p2 = 10;
 805                 clock.n = 1;
 806                 clock.m1 = 14;
 807                 clock.m2 = 2;
 808         }
 809         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 810         clock.p = (clock.p1 * clock.p2);
 811         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 812         clock.vco = 0;
 813         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 814         return true;
 815 }
 816 static bool
 817 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                         int target, int refclk, intel_clock_t *match_clock,
 819                         intel_clock_t *best_clock)
 820 {
 821         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 822         u32 m, n, fastclk;
 823         u32 updrate, minupdate, fracbits, p;
 824         unsigned long bestppm, ppm, absppm;
 825         int dotclk, flag;
 826
 827         flag = 0;
 828         dotclk = target * 1000;
 829         bestppm = 1000000;
 830         ppm = absppm = 0;
 831         fastclk = dotclk / (2*100);
 832         updrate = 0;
 833         minupdate = 19200;
 834         fracbits = 1;
 835         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 836         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 837
 838         /* based on hardware requirement, prefer smaller n to precision */
 839         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 840                 updrate = refclk / n;
 841                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 842                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 843                                 if (p2 > 10)
 844                                         p2 = p2 - 1;
 845                                 p = p1 * p2;
 846                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 847                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 848                                         m2 = (((2*(fastclk * p * n / m1 )) +
 849                                                refclk) / (2*refclk));
 850                                         m = m1 * m2;
 851                                         vco = updrate * m;
 852                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 853                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 854                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 855                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 856                                                         bestppm = 0;
 857                                                         flag = 1;
 858                                                 }
 859                                                 if (absppm < bestppm - 10) {
 860                                                         bestppm = absppm;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (flag) {
 864                                                         bestn = n;
 865                                                         bestm1 = m1;
 866                                                         bestm2 = m2;
 867                                                         bestp1 = p1;
 868                                                         bestp2 = p2;
 869                                                         flag = 0;
 870                                                 }
 871                                         }
 872                                 }
 873                         }
 874                 }
 875         }
 876         best_clock->n = bestn;
 877         best_clock->m1 = bestm1;
 878         best_clock->m2 = bestm2;
 879         best_clock->p1 = bestp1;
 880         best_clock->p2 = bestp2;
 881
 882         return true;
 883 }
 884
 885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 886                                              enum pipe pipe)
 887 {
 888         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         return intel_crtc->cpu_transcoder;
 892 }
 893
 894 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 895 {
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         u32 frame, frame_reg = PIPEFRAME(pipe);
 898
 899         frame = I915_READ(frame_reg);
 900
 901         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 /**
 906  * intel_wait_for_vblank - wait for vblank on a given pipe
 907  * @dev: drm device
 908  * @pipe: pipe to wait for
 909  *
 910  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 911  * mode setting code.
 912  */
 913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int pipestat_reg = PIPESTAT(pipe);
 917
 918         if (INTEL_INFO(dev)->gen >= 5) {
 919                 ironlake_wait_for_vblank(dev, pipe);
 920                 return;
 921         }
 922
 923         /* Clear existing vblank status. Note this will clear any other
 924          * sticky status fields as well.
 925          *
 926          * This races with i915_driver_irq_handler() with the result
 927          * that either function could miss a vblank event.  Here it is not
 928          * fatal, as we will either wait upon the next vblank interrupt or
 929          * timeout.  Generally speaking intel_wait_for_vblank() is only
 930          * called during modeset at which time the GPU should be idle and
 931          * should *not* be performing page flips and thus not waiting on
 932          * vblanks...
 933          * Currently, the result of us stealing a vblank from the irq
 934          * handler is that a single frame will be skipped during swapbuffers.
 935          */
 936         I915_WRITE(pipestat_reg,
 937                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 938
 939         /* Wait for vblank interrupt bit to set */
 940         if (wait_for(I915_READ(pipestat_reg) &
 941                      PIPE_VBLANK_INTERRUPT_STATUS,
 942                      50))
 943                 DRM_DEBUG_KMS("vblank wait timed out\n");
 944 }
 945
 946 /*
 947  * intel_wait_for_pipe_off - wait for pipe to turn off
 948  * @dev: drm device
 949  * @pipe: pipe to wait for
 950  *
 951  * After disabling a pipe, we can't wait for vblank in the usual way,
 952  * spinning on the vblank interrupt status bit, since we won't actually
 953  * see an interrupt when the pipe is disabled.
 954  *
 955  * On Gen4 and above:
 956  *   wait for the pipe register state bit to turn off
 957  *
 958  * Otherwise:
 959  *   wait for the display line value to settle (it usually
 960  *   ends up stopping at the start of the next frame).
 961  *
 962  */
 963 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 964 {
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 967                                                                       pipe);
 968
 969         if (INTEL_INFO(dev)->gen >= 4) {
 970                 int reg = PIPECONF(cpu_transcoder);
 971
 972                 /* Wait for the Pipe State to go off */
 973                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 974                              100))
 975                         WARN(1, "pipe_off wait timed out\n");
 976         } else {
 977                 u32 last_line, line_mask;
 978                 int reg = PIPEDSL(pipe);
 979                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 980
 981                 if (IS_GEN2(dev))
 982                         line_mask = DSL_LINEMASK_GEN2;
 983                 else
 984                         line_mask = DSL_LINEMASK_GEN3;
 985
 986                 /* Wait for the display line to settle */
 987                 do {
 988                         last_line = I915_READ(reg) & line_mask;
 989                         mdelay(5);
 990                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 991                          time_after(timeout, jiffies));
 992                 if (time_after(jiffies, timeout))
 993                         WARN(1, "pipe_off wait timed out\n");
 994         }
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 static void assert_pll(struct drm_i915_private *dev_priv,
1004                        enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1018 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1019
1020 /* For ILK+ */
1021 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1022                            struct intel_pch_pll *pll,
1023                            struct intel_crtc *crtc,
1024                            bool state)
1025 {
1026         u32 val;
1027         bool cur_state;
1028
1029         if (HAS_PCH_LPT(dev_priv->dev)) {
1030                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1031                 return;
1032         }
1033
1034         if (WARN (!pll,
1035                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1036                 return;
1037
1038         val = I915_READ(pll->pll_reg);
1039         cur_state = !!(val & DPLL_VCO_ENABLE);
1040         WARN(cur_state != state,
1041              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1042              pll->pll_reg, state_string(state), state_string(cur_state), val);
1043
1044         /* Make sure the selected PLL is correctly attached to the transcoder */
1045         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1046                 u32 pch_dpll;
1047
1048                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1049                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1050                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1051                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1052                           cur_state, crtc->pipe, pch_dpll)) {
1053                         cur_state = !!(val >> (4*crtc->pipe + 3));
1054                         WARN(cur_state != state,
1055                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1056                              pll->pll_reg == _PCH_DPLL_B,
1057                              state_string(state),
1058                              crtc->pipe,
1059                              val);
1060                 }
1061         }
1062 }
1063 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1064 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1065
1066 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1067                           enum pipe pipe, bool state)
1068 {
1069         int reg;
1070         u32 val;
1071         bool cur_state;
1072         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1073                                                                       pipe);
1074
1075         if (IS_HASWELL(dev_priv->dev)) {
1076                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1077                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1080         } else {
1081                 reg = FDI_TX_CTL(pipe);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & FDI_TX_ENABLE);
1084         }
1085         WARN(cur_state != state,
1086              "FDI TX state assertion failure (expected %s, current %s)\n",
1087              state_string(state), state_string(cur_state));
1088 }
1089 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1090 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1091
1092 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         int reg;
1096         u32 val;
1097         bool cur_state;
1098
1099         reg = FDI_RX_CTL(pipe);
1100         val = I915_READ(reg);
1101         cur_state = !!(val & FDI_RX_ENABLE);
1102         WARN(cur_state != state,
1103              "FDI RX state assertion failure (expected %s, current %s)\n",
1104              state_string(state), state_string(cur_state));
1105 }
1106 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1107 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1108
1109 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110                                       enum pipe pipe)
1111 {
1112         int reg;
1113         u32 val;
1114
1115         /* ILK FDI PLL is always enabled */
1116         if (dev_priv->info->gen == 5)
1117                 return;
1118
1119         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1120         if (IS_HASWELL(dev_priv->dev))
1121                 return;
1122
1123         reg = FDI_TX_CTL(pipe);
1124         val = I915_READ(reg);
1125         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126 }
1127
1128 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1129                                       enum pipe pipe)
1130 {
1131         int reg;
1132         u32 val;
1133
1134         reg = FDI_RX_CTL(pipe);
1135         val = I915_READ(reg);
1136         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1137 }
1138
1139 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1140                                   enum pipe pipe)
1141 {
1142         int pp_reg, lvds_reg;
1143         u32 val;
1144         enum pipe panel_pipe = PIPE_A;
1145         bool locked = true;
1146
1147         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1148                 pp_reg = PCH_PP_CONTROL;
1149                 lvds_reg = PCH_LVDS;
1150         } else {
1151                 pp_reg = PP_CONTROL;
1152                 lvds_reg = LVDS;
1153         }
1154
1155         val = I915_READ(pp_reg);
1156         if (!(val & PANEL_POWER_ON) ||
1157             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1158                 locked = false;
1159
1160         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1161                 panel_pipe = PIPE_B;
1162
1163         WARN(panel_pipe == pipe && locked,
1164              "panel assertion failure, pipe %c regs locked\n",
1165              pipe_name(pipe));
1166 }
1167
1168 void assert_pipe(struct drm_i915_private *dev_priv,
1169                  enum pipe pipe, bool state)
1170 {
1171         int reg;
1172         u32 val;
1173         bool cur_state;
1174         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1175                                                                       pipe);
1176
1177         /* if we need the pipe A quirk it must be always on */
1178         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1179                 state = true;
1180
1181         reg = PIPECONF(cpu_transcoder);
1182         val = I915_READ(reg);
1183         cur_state = !!(val & PIPECONF_ENABLE);
1184         WARN(cur_state != state,
1185              "pipe %c assertion failure (expected %s, current %s)\n",
1186              pipe_name(pipe), state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_plane(struct drm_i915_private *dev_priv,
1190                          enum plane plane, bool state)
1191 {
1192         int reg;
1193         u32 val;
1194         bool cur_state;
1195
1196         reg = DSPCNTR(plane);
1197         val = I915_READ(reg);
1198         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1199         WARN(cur_state != state,
1200              "plane %c assertion failure (expected %s, current %s)\n",
1201              plane_name(plane), state_string(state), state_string(cur_state));
1202 }
1203
1204 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1205 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1206
1207 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1208                                    enum pipe pipe)
1209 {
1210         int reg, i;
1211         u32 val;
1212         int cur_pipe;
1213
1214         /* Planes are fixed to pipes on ILK+ */
1215         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1216                 reg = DSPCNTR(pipe);
1217                 val = I915_READ(reg);
1218                 WARN((val & DISPLAY_PLANE_ENABLE),
1219                      "plane %c assertion failure, should be disabled but not\n",
1220                      plane_name(pipe));
1221                 return;
1222         }
1223
1224         /* Need to check both planes against the pipe */
1225         for (i = 0; i < 2; i++) {
1226                 reg = DSPCNTR(i);
1227                 val = I915_READ(reg);
1228                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1229                         DISPPLANE_SEL_PIPE_SHIFT;
1230                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1231                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1232                      plane_name(i), pipe_name(pipe));
1233         }
1234 }
1235
1236 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1237 {
1238         u32 val;
1239         bool enabled;
1240
1241         if (HAS_PCH_LPT(dev_priv->dev)) {
1242                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1243                 return;
1244         }
1245
1246         val = I915_READ(PCH_DREF_CONTROL);
1247         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1248                             DREF_SUPERSPREAD_SOURCE_MASK));
1249         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1250 }
1251
1252 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1253                                        enum pipe pipe)
1254 {
1255         int reg;
1256         u32 val;
1257         bool enabled;
1258
1259         reg = TRANSCONF(pipe);
1260         val = I915_READ(reg);
1261         enabled = !!(val & TRANS_ENABLE);
1262         WARN(enabled,
1263              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1264              pipe_name(pipe));
1265 }
1266
1267 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1268                             enum pipe pipe, u32 port_sel, u32 val)
1269 {
1270         if ((val & DP_PORT_EN) == 0)
1271                 return false;
1272
1273         if (HAS_PCH_CPT(dev_priv->dev)) {
1274                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1275                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1276                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1277                         return false;
1278         } else {
1279                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1280                         return false;
1281         }
1282         return true;
1283 }
1284
1285 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286                               enum pipe pipe, u32 val)
1287 {
1288         if ((val & PORT_ENABLE) == 0)
1289                 return false;
1290
1291         if (HAS_PCH_CPT(dev_priv->dev)) {
1292                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293                         return false;
1294         } else {
1295                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1296                         return false;
1297         }
1298         return true;
1299 }
1300
1301 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1302                               enum pipe pipe, u32 val)
1303 {
1304         if ((val & LVDS_PORT_EN) == 0)
1305                 return false;
1306
1307         if (HAS_PCH_CPT(dev_priv->dev)) {
1308                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1309                         return false;
1310         } else {
1311                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1312                         return false;
1313         }
1314         return true;
1315 }
1316
1317 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1318                               enum pipe pipe, u32 val)
1319 {
1320         if ((val & ADPA_DAC_ENABLE) == 0)
1321                 return false;
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1324                         return false;
1325         } else {
1326                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1327                         return false;
1328         }
1329         return true;
1330 }
1331
1332 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1333                                    enum pipe pipe, int reg, u32 port_sel)
1334 {
1335         u32 val = I915_READ(reg);
1336         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1337              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1338              reg, pipe_name(pipe));
1339
1340         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1341              && (val & DP_PIPEB_SELECT),
1342              "IBX PCH dp port still using transcoder B\n");
1343 }
1344
1345 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1346                                      enum pipe pipe, int reg)
1347 {
1348         u32 val = I915_READ(reg);
1349         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1350              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1351              reg, pipe_name(pipe));
1352
1353         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1354              && (val & SDVO_PIPE_B_SELECT),
1355              "IBX PCH hdmi port still using transcoder B\n");
1356 }
1357
1358 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1359                                       enum pipe pipe)
1360 {
1361         int reg;
1362         u32 val;
1363
1364         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1365         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1366         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1367
1368         reg = PCH_ADPA;
1369         val = I915_READ(reg);
1370         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1371              "PCH VGA enabled on transcoder %c, should be disabled\n",
1372              pipe_name(pipe));
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1377              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1378              pipe_name(pipe));
1379
1380         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1381         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1382         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1383 }
1384
1385 /**
1386  * intel_enable_pll - enable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to enable
1389  *
1390  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1391  * make sure the PLL reg is writable first though, since the panel write
1392  * protect mechanism may be enabled.
1393  *
1394  * Note!  This is for pre-ILK only.
1395  *
1396  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1397  */
1398 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         /* No really, not for ILK+ */
1404         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1405
1406         /* PLL is protected by panel, make sure we can write it */
1407         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408                 assert_panel_unlocked(dev_priv, pipe);
1409
1410         reg = DPLL(pipe);
1411         val = I915_READ(reg);
1412         val |= DPLL_VCO_ENABLE;
1413
1414         /* We do this three times for luck */
1415         I915_WRITE(reg, val);
1416         POSTING_READ(reg);
1417         udelay(150); /* wait for warmup */
1418         I915_WRITE(reg, val);
1419         POSTING_READ(reg);
1420         udelay(150); /* wait for warmup */
1421         I915_WRITE(reg, val);
1422         POSTING_READ(reg);
1423         udelay(150); /* wait for warmup */
1424 }
1425
1426 /**
1427  * intel_disable_pll - disable a PLL
1428  * @dev_priv: i915 private structure
1429  * @pipe: pipe PLL to disable
1430  *
1431  * Disable the PLL for @pipe, making sure the pipe is off first.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  */
1435 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* Don't disable pipe A or pipe A PLLs if needed */
1441         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1442                 return;
1443
1444         /* Make sure the pipe isn't still relying on us */
1445         assert_pipe_disabled(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val &= ~DPLL_VCO_ENABLE;
1450         I915_WRITE(reg, val);
1451         POSTING_READ(reg);
1452 }
1453
1454 /* SBI access */
1455 static void
1456 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1457 {
1458         unsigned long flags;
1459
1460         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1461         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1462                                 100)) {
1463                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1464                 goto out_unlock;
1465         }
1466
1467         I915_WRITE(SBI_ADDR,
1468                         (reg << 16));
1469         I915_WRITE(SBI_DATA,
1470                         value);
1471         I915_WRITE(SBI_CTL_STAT,
1472                         SBI_BUSY |
1473                         SBI_CTL_OP_CRWR);
1474
1475         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1476                                 100)) {
1477                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1478                 goto out_unlock;
1479         }
1480
1481 out_unlock:
1482         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1483 }
1484
1485 static u32
1486 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1487 {
1488         unsigned long flags;
1489         u32 value = 0;
1490
1491         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1492         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1493                                 100)) {
1494                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1495                 goto out_unlock;
1496         }
1497
1498         I915_WRITE(SBI_ADDR,
1499                         (reg << 16));
1500         I915_WRITE(SBI_CTL_STAT,
1501                         SBI_BUSY |
1502                         SBI_CTL_OP_CRRD);
1503
1504         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1505                                 100)) {
1506                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1507                 goto out_unlock;
1508         }
1509
1510         value = I915_READ(SBI_DATA);
1511
1512 out_unlock:
1513         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1514         return value;
1515 }
1516
1517 /**
1518  * ironlake_enable_pch_pll - enable PCH PLL
1519  * @dev_priv: i915 private structure
1520  * @pipe: pipe PLL to enable
1521  *
1522  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523  * drives the transcoder clock.
1524  */
1525 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1526 {
1527         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1528         struct intel_pch_pll *pll;
1529         int reg;
1530         u32 val;
1531
1532         /* PCH PLLs only available on ILK, SNB and IVB */
1533         BUG_ON(dev_priv->info->gen < 5);
1534         pll = intel_crtc->pch_pll;
1535         if (pll == NULL)
1536                 return;
1537
1538         if (WARN_ON(pll->refcount == 0))
1539                 return;
1540
1541         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1542                       pll->pll_reg, pll->active, pll->on,
1543                       intel_crtc->base.base.id);
1544
1545         /* PCH refclock must be enabled first */
1546         assert_pch_refclk_enabled(dev_priv);
1547
1548         if (pll->active++ && pll->on) {
1549                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1550                 return;
1551         }
1552
1553         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1554
1555         reg = pll->pll_reg;
1556         val = I915_READ(reg);
1557         val |= DPLL_VCO_ENABLE;
1558         I915_WRITE(reg, val);
1559         POSTING_READ(reg);
1560         udelay(200);
1561
1562         pll->on = true;
1563 }
1564
1565 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH only available on ILK+ */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         if (pll == NULL)
1575                return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         if (WARN_ON(pll->active == 0)) {
1585                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1586                 return;
1587         }
1588
1589         if (--pll->active) {
1590                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1591                 return;
1592         }
1593
1594         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1595
1596         /* Make sure transcoder isn't still depending on us */
1597         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1598
1599         reg = pll->pll_reg;
1600         val = I915_READ(reg);
1601         val &= ~DPLL_VCO_ENABLE;
1602         I915_WRITE(reg, val);
1603         POSTING_READ(reg);
1604         udelay(200);
1605
1606         pll->on = false;
1607 }
1608
1609 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610                                            enum pipe pipe)
1611 {
1612         struct drm_device *dev = dev_priv->dev;
1613         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1614         uint32_t reg, val, pipeconf_val;
1615
1616         /* PCH only available on ILK+ */
1617         BUG_ON(dev_priv->info->gen < 5);
1618
1619         /* Make sure PCH DPLL is enabled */
1620         assert_pch_pll_enabled(dev_priv,
1621                                to_intel_crtc(crtc)->pch_pll,
1622                                to_intel_crtc(crtc));
1623
1624         /* FDI must be feeding us bits for PCH ports */
1625         assert_fdi_tx_enabled(dev_priv, pipe);
1626         assert_fdi_rx_enabled(dev_priv, pipe);
1627
1628         if (HAS_PCH_CPT(dev)) {
1629                 /* Workaround: Set the timing override bit before enabling the
1630                  * pch transcoder. */
1631                 reg = TRANS_CHICKEN2(pipe);
1632                 val = I915_READ(reg);
1633                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1634                 I915_WRITE(reg, val);
1635         }
1636
1637         reg = TRANSCONF(pipe);
1638         val = I915_READ(reg);
1639         pipeconf_val = I915_READ(PIPECONF(pipe));
1640
1641         if (HAS_PCH_IBX(dev_priv->dev)) {
1642                 /*
1643                  * make the BPC in transcoder be consistent with
1644                  * that in pipeconf reg.
1645                  */
1646                 val &= ~PIPE_BPC_MASK;
1647                 val |= pipeconf_val & PIPE_BPC_MASK;
1648         }
1649
1650         val &= ~TRANS_INTERLACE_MASK;
1651         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1652                 if (HAS_PCH_IBX(dev_priv->dev) &&
1653                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1654                         val |= TRANS_LEGACY_INTERLACED_ILK;
1655                 else
1656                         val |= TRANS_INTERLACED;
1657         else
1658                 val |= TRANS_PROGRESSIVE;
1659
1660         I915_WRITE(reg, val | TRANS_ENABLE);
1661         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1662                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1663 }
1664
1665 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1666                                       enum transcoder cpu_transcoder)
1667 {
1668         u32 val, pipeconf_val;
1669
1670         /* PCH only available on ILK+ */
1671         BUG_ON(dev_priv->info->gen < 5);
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1675         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1676
1677         /* Workaround: set timing override bit. */
1678         val = I915_READ(_TRANSA_CHICKEN2);
1679         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1680         I915_WRITE(_TRANSA_CHICKEN2, val);
1681
1682         val = TRANS_ENABLE;
1683         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1684
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1686             PIPECONF_INTERLACED_ILK)
1687                 val |= TRANS_INTERLACED;
1688         else
1689                 val |= TRANS_PROGRESSIVE;
1690
1691         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1692         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1693                 DRM_ERROR("Failed to enable PCH transcoder\n");
1694 }
1695
1696 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697                                             enum pipe pipe)
1698 {
1699         struct drm_device *dev = dev_priv->dev;
1700         uint32_t reg, val;
1701
1702         /* FDI relies on the transcoder */
1703         assert_fdi_tx_disabled(dev_priv, pipe);
1704         assert_fdi_rx_disabled(dev_priv, pipe);
1705
1706         /* Ports must be off as well */
1707         assert_pch_ports_disabled(dev_priv, pipe);
1708
1709         reg = TRANSCONF(pipe);
1710         val = I915_READ(reg);
1711         val &= ~TRANS_ENABLE;
1712         I915_WRITE(reg, val);
1713         /* wait for PCH transcoder off, transcoder state */
1714         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1715                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1716
1717         if (!HAS_PCH_IBX(dev)) {
1718                 /* Workaround: Clear the timing override chicken bit again. */
1719                 reg = TRANS_CHICKEN2(pipe);
1720                 val = I915_READ(reg);
1721                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1722                 I915_WRITE(reg, val);
1723         }
1724 }
1725
1726 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1727 {
1728         u32 val;
1729
1730         val = I915_READ(_TRANSACONF);
1731         val &= ~TRANS_ENABLE;
1732         I915_WRITE(_TRANSACONF, val);
1733         /* wait for PCH transcoder off, transcoder state */
1734         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1735                 DRM_ERROR("Failed to disable PCH transcoder\n");
1736
1737         /* Workaround: clear timing override bit. */
1738         val = I915_READ(_TRANSA_CHICKEN2);
1739         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1740         I915_WRITE(_TRANSA_CHICKEN2, val);
1741 }
1742
1743 /**
1744  * intel_enable_pipe - enable a pipe, asserting requirements
1745  * @dev_priv: i915 private structure
1746  * @pipe: pipe to enable
1747  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1748  *
1749  * Enable @pipe, making sure that various hardware specific requirements
1750  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1751  *
1752  * @pipe should be %PIPE_A or %PIPE_B.
1753  *
1754  * Will wait until the pipe is actually running (i.e. first vblank) before
1755  * returning.
1756  */
1757 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1758                               bool pch_port)
1759 {
1760         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1761                                                                       pipe);
1762         enum transcoder pch_transcoder;
1763         int reg;
1764         u32 val;
1765
1766         if (IS_HASWELL(dev_priv->dev))
1767                 pch_transcoder = TRANSCODER_A;
1768         else
1769                 pch_transcoder = pipe;
1770
1771         /*
1772          * A pipe without a PLL won't actually be able to drive bits from
1773          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1774          * need the check.
1775          */
1776         if (!HAS_PCH_SPLIT(dev_priv->dev))
1777                 assert_pll_enabled(dev_priv, pipe);
1778         else {
1779                 if (pch_port) {
1780                         /* if driving the PCH, we need FDI enabled */
1781                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1782                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1783                 }
1784                 /* FIXME: assert CPU port conditions for SNB+ */
1785         }
1786
1787         reg = PIPECONF(cpu_transcoder);
1788         val = I915_READ(reg);
1789         if (val & PIPECONF_ENABLE)
1790                 return;
1791
1792         I915_WRITE(reg, val | PIPECONF_ENABLE);
1793         intel_wait_for_vblank(dev_priv->dev, pipe);
1794 }
1795
1796 /**
1797  * intel_disable_pipe - disable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to disable
1800  *
1801  * Disable @pipe, making sure that various hardware specific requirements
1802  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1803  *
1804  * @pipe should be %PIPE_A or %PIPE_B.
1805  *
1806  * Will wait until the pipe has shut down before returning.
1807  */
1808 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1809                                enum pipe pipe)
1810 {
1811         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1812                                                                       pipe);
1813         int reg;
1814         u32 val;
1815
1816         /*
1817          * Make sure planes won't keep trying to pump pixels to us,
1818          * or we might hang the display.
1819          */
1820         assert_planes_disabled(dev_priv, pipe);
1821
1822         /* Don't disable pipe A or pipe A PLLs if needed */
1823         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1824                 return;
1825
1826         reg = PIPECONF(cpu_transcoder);
1827         val = I915_READ(reg);
1828         if ((val & PIPECONF_ENABLE) == 0)
1829                 return;
1830
1831         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1832         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1833 }
1834
1835 /*
1836  * Plane regs are double buffered, going from enabled->disabled needs a
1837  * trigger in order to latch.  The display address reg provides this.
1838  */
1839 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1840                                       enum plane plane)
1841 {
1842         if (dev_priv->info->gen >= 4)
1843                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1844         else
1845                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1846 }
1847
1848 /**
1849  * intel_enable_plane - enable a display plane on a given pipe
1850  * @dev_priv: i915 private structure
1851  * @plane: plane to enable
1852  * @pipe: pipe being fed
1853  *
1854  * Enable @plane on @pipe, making sure that @pipe is running first.
1855  */
1856 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1857                                enum plane plane, enum pipe pipe)
1858 {
1859         int reg;
1860         u32 val;
1861
1862         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1863         assert_pipe_enabled(dev_priv, pipe);
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if (val & DISPLAY_PLANE_ENABLE)
1868                 return;
1869
1870         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 /**
1876  * intel_disable_plane - disable a display plane
1877  * @dev_priv: i915 private structure
1878  * @plane: plane to disable
1879  * @pipe: pipe consuming the data
1880  *
1881  * Disable @plane; should be an independent operation.
1882  */
1883 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1884                                 enum plane plane, enum pipe pipe)
1885 {
1886         int reg;
1887         u32 val;
1888
1889         reg = DSPCNTR(plane);
1890         val = I915_READ(reg);
1891         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1892                 return;
1893
1894         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1895         intel_flush_display_plane(dev_priv, plane);
1896         intel_wait_for_vblank(dev_priv->dev, pipe);
1897 }
1898
1899 int
1900 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1901                            struct drm_i915_gem_object *obj,
1902                            struct intel_ring_buffer *pipelined)
1903 {
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905         u32 alignment;
1906         int ret;
1907
1908         switch (obj->tiling_mode) {
1909         case I915_TILING_NONE:
1910                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1911                         alignment = 128 * 1024;
1912                 else if (INTEL_INFO(dev)->gen >= 4)
1913                         alignment = 4 * 1024;
1914                 else
1915                         alignment = 64 * 1024;
1916                 break;
1917         case I915_TILING_X:
1918                 /* pin() will align the object as required by fence */
1919                 alignment = 0;
1920                 break;
1921         case I915_TILING_Y:
1922                 /* FIXME: Is this true? */
1923                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1924                 return -EINVAL;
1925         default:
1926                 BUG();
1927         }
1928
1929         dev_priv->mm.interruptible = false;
1930         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1931         if (ret)
1932                 goto err_interruptible;
1933
1934         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1935          * fence, whereas 965+ only requires a fence if using
1936          * framebuffer compression.  For simplicity, we always install
1937          * a fence as the cost is not that onerous.
1938          */
1939         ret = i915_gem_object_get_fence(obj);
1940         if (ret)
1941                 goto err_unpin;
1942
1943         i915_gem_object_pin_fence(obj);
1944
1945         dev_priv->mm.interruptible = true;
1946         return 0;
1947
1948 err_unpin:
1949         i915_gem_object_unpin(obj);
1950 err_interruptible:
1951         dev_priv->mm.interruptible = true;
1952         return ret;
1953 }
1954
1955 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1956 {
1957         i915_gem_object_unpin_fence(obj);
1958         i915_gem_object_unpin(obj);
1959 }
1960
1961 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1962  * is assumed to be a power-of-two. */
1963 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1964                                                unsigned int bpp,
1965                                                unsigned int pitch)
1966 {
1967         int tile_rows, tiles;
1968
1969         tile_rows = *y / 8;
1970         *y %= 8;
1971         tiles = *x / (512/bpp);
1972         *x %= 512/bpp;
1973
1974         return tile_rows * pitch * 8 + tiles * 4096;
1975 }
1976
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978                              int x, int y)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         struct intel_framebuffer *intel_fb;
1984         struct drm_i915_gem_object *obj;
1985         int plane = intel_crtc->plane;
1986         unsigned long linear_offset;
1987         u32 dspcntr;
1988         u32 reg;
1989
1990         switch (plane) {
1991         case 0:
1992         case 1:
1993                 break;
1994         default:
1995                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1996                 return -EINVAL;
1997         }
1998
1999         intel_fb = to_intel_framebuffer(fb);
2000         obj = intel_fb->obj;
2001
2002         reg = DSPCNTR(plane);
2003         dspcntr = I915_READ(reg);
2004         /* Mask out pixel format bits in case we change it */
2005         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006         switch (fb->pixel_format) {
2007         case DRM_FORMAT_C8:
2008                 dspcntr |= DISPPLANE_8BPP;
2009                 break;
2010         case DRM_FORMAT_XRGB1555:
2011         case DRM_FORMAT_ARGB1555:
2012                 dspcntr |= DISPPLANE_BGRX555;
2013                 break;
2014         case DRM_FORMAT_RGB565:
2015                 dspcntr |= DISPPLANE_BGRX565;
2016                 break;
2017         case DRM_FORMAT_XRGB8888:
2018         case DRM_FORMAT_ARGB8888:
2019                 dspcntr |= DISPPLANE_BGRX888;
2020                 break;
2021         case DRM_FORMAT_XBGR8888:
2022         case DRM_FORMAT_ABGR8888:
2023                 dspcntr |= DISPPLANE_RGBX888;
2024                 break;
2025         case DRM_FORMAT_XRGB2101010:
2026         case DRM_FORMAT_ARGB2101010:
2027                 dspcntr |= DISPPLANE_BGRX101010;
2028                 break;
2029         case DRM_FORMAT_XBGR2101010:
2030         case DRM_FORMAT_ABGR2101010:
2031                 dspcntr |= DISPPLANE_RGBX101010;
2032                 break;
2033         default:
2034                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2035                 return -EINVAL;
2036         }
2037
2038         if (INTEL_INFO(dev)->gen >= 4) {
2039                 if (obj->tiling_mode != I915_TILING_NONE)
2040                         dspcntr |= DISPPLANE_TILED;
2041                 else
2042                         dspcntr &= ~DISPPLANE_TILED;
2043         }
2044
2045         I915_WRITE(reg, dspcntr);
2046
2047         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2048
2049         if (INTEL_INFO(dev)->gen >= 4) {
2050                 intel_crtc->dspaddr_offset =
2051                         intel_gen4_compute_offset_xtiled(&x, &y,
2052                                                          fb->bits_per_pixel / 8,
2053                                                          fb->pitches[0]);
2054                 linear_offset -= intel_crtc->dspaddr_offset;
2055         } else {
2056                 intel_crtc->dspaddr_offset = linear_offset;
2057         }
2058
2059         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2060                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2061         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2062         if (INTEL_INFO(dev)->gen >= 4) {
2063                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2064                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2065                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2066                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2067         } else
2068                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2069         POSTING_READ(reg);
2070
2071         return 0;
2072 }
2073
2074 static int ironlake_update_plane(struct drm_crtc *crtc,
2075                                  struct drm_framebuffer *fb, int x, int y)
2076 {
2077         struct drm_device *dev = crtc->dev;
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080         struct intel_framebuffer *intel_fb;
2081         struct drm_i915_gem_object *obj;
2082         int plane = intel_crtc->plane;
2083         unsigned long linear_offset;
2084         u32 dspcntr;
2085         u32 reg;
2086
2087         switch (plane) {
2088         case 0:
2089         case 1:
2090         case 2:
2091                 break;
2092         default:
2093                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2094                 return -EINVAL;
2095         }
2096
2097         intel_fb = to_intel_framebuffer(fb);
2098         obj = intel_fb->obj;
2099
2100         reg = DSPCNTR(plane);
2101         dspcntr = I915_READ(reg);
2102         /* Mask out pixel format bits in case we change it */
2103         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2104         switch (fb->pixel_format) {
2105         case DRM_FORMAT_C8:
2106                 dspcntr |= DISPPLANE_8BPP;
2107                 break;
2108         case DRM_FORMAT_RGB565:
2109                 dspcntr |= DISPPLANE_BGRX565;
2110                 break;
2111         case DRM_FORMAT_XRGB8888:
2112         case DRM_FORMAT_ARGB8888:
2113                 dspcntr |= DISPPLANE_BGRX888;
2114                 break;
2115         case DRM_FORMAT_XBGR8888:
2116         case DRM_FORMAT_ABGR8888:
2117                 dspcntr |= DISPPLANE_RGBX888;
2118                 break;
2119         case DRM_FORMAT_XRGB2101010:
2120         case DRM_FORMAT_ARGB2101010:
2121                 dspcntr |= DISPPLANE_BGRX101010;
2122                 break;
2123         case DRM_FORMAT_XBGR2101010:
2124         case DRM_FORMAT_ABGR2101010:
2125                 dspcntr |= DISPPLANE_RGBX101010;
2126                 break;
2127         default:
2128                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2129                 return -EINVAL;
2130         }
2131
2132         if (obj->tiling_mode != I915_TILING_NONE)
2133                 dspcntr |= DISPPLANE_TILED;
2134         else
2135                 dspcntr &= ~DISPPLANE_TILED;
2136
2137         /* must disable */
2138         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2139
2140         I915_WRITE(reg, dspcntr);
2141
2142         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2143         intel_crtc->dspaddr_offset =
2144                 intel_gen4_compute_offset_xtiled(&x, &y,
2145                                                  fb->bits_per_pixel / 8,
2146                                                  fb->pitches[0]);
2147         linear_offset -= intel_crtc->dspaddr_offset;
2148
2149         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2150                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2151         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2152         I915_MODIFY_DISPBASE(DSPSURF(plane),
2153                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2154         if (IS_HASWELL(dev)) {
2155                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2156         } else {
2157                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2158                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2159         }
2160         POSTING_READ(reg);
2161
2162         return 0;
2163 }
2164
2165 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2166 static int
2167 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2168                            int x, int y, enum mode_set_atomic state)
2169 {
2170         struct drm_device *dev = crtc->dev;
2171         struct drm_i915_private *dev_priv = dev->dev_private;
2172
2173         if (dev_priv->display.disable_fbc)
2174                 dev_priv->display.disable_fbc(dev);
2175         intel_increase_pllclock(crtc);
2176
2177         return dev_priv->display.update_plane(crtc, fb, x, y);
2178 }
2179
2180 static int
2181 intel_finish_fb(struct drm_framebuffer *old_fb)
2182 {
2183         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2184         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2185         bool was_interruptible = dev_priv->mm.interruptible;
2186         int ret;
2187
2188         wait_event(dev_priv->pending_flip_queue,
2189                    atomic_read(&dev_priv->mm.wedged) ||
2190                    atomic_read(&obj->pending_flip) == 0);
2191
2192         /* Big Hammer, we also need to ensure that any pending
2193          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2194          * current scanout is retired before unpinning the old
2195          * framebuffer.
2196          *
2197          * This should only fail upon a hung GPU, in which case we
2198          * can safely continue.
2199          */
2200         dev_priv->mm.interruptible = false;
2201         ret = i915_gem_object_finish_gpu(obj);
2202         dev_priv->mm.interruptible = was_interruptible;
2203
2204         return ret;
2205 }
2206
2207 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2208 {
2209         struct drm_device *dev = crtc->dev;
2210         struct drm_i915_master_private *master_priv;
2211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212
2213         if (!dev->primary->master)
2214                 return;
2215
2216         master_priv = dev->primary->master->driver_priv;
2217         if (!master_priv->sarea_priv)
2218                 return;
2219
2220         switch (intel_crtc->pipe) {
2221         case 0:
2222                 master_priv->sarea_priv->pipeA_x = x;
2223                 master_priv->sarea_priv->pipeA_y = y;
2224                 break;
2225         case 1:
2226                 master_priv->sarea_priv->pipeB_x = x;
2227                 master_priv->sarea_priv->pipeB_y = y;
2228                 break;
2229         default:
2230                 break;
2231         }
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236                     struct drm_framebuffer *fb)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         struct drm_framebuffer *old_fb;
2242         int ret;
2243
2244         /* no fb bound */
2245         if (!fb) {
2246                 DRM_ERROR("No FB bound\n");
2247                 return 0;
2248         }
2249
2250         if(intel_crtc->plane > dev_priv->num_pipe) {
2251                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2252                                 intel_crtc->plane,
2253                                 dev_priv->num_pipe);
2254                 return -EINVAL;
2255         }
2256
2257         mutex_lock(&dev->struct_mutex);
2258         ret = intel_pin_and_fence_fb_obj(dev,
2259                                          to_intel_framebuffer(fb)->obj,
2260                                          NULL);
2261         if (ret != 0) {
2262                 mutex_unlock(&dev->struct_mutex);
2263                 DRM_ERROR("pin & fence failed\n");
2264                 return ret;
2265         }
2266
2267         if (crtc->fb)
2268                 intel_finish_fb(crtc->fb);
2269
2270         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2271         if (ret) {
2272                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2273                 mutex_unlock(&dev->struct_mutex);
2274                 DRM_ERROR("failed to update base address\n");
2275                 return ret;
2276         }
2277
2278         old_fb = crtc->fb;
2279         crtc->fb = fb;
2280         crtc->x = x;
2281         crtc->y = y;
2282
2283         if (old_fb) {
2284                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2285                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2286         }
2287
2288         intel_update_fbc(dev);
2289         mutex_unlock(&dev->struct_mutex);
2290
2291         intel_crtc_update_sarea_pos(crtc, x, y);
2292
2293         return 0;
2294 }
2295
2296 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2297 {
2298         struct drm_device *dev = crtc->dev;
2299         struct drm_i915_private *dev_priv = dev->dev_private;
2300         u32 dpa_ctl;
2301
2302         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2303         dpa_ctl = I915_READ(DP_A);
2304         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2305
2306         if (clock < 200000) {
2307                 u32 temp;
2308                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2309                 /* workaround for 160Mhz:
2310                    1) program 0x4600c bits 15:0 = 0x8124
2311                    2) program 0x46010 bit 0 = 1
2312                    3) program 0x46034 bit 24 = 1
2313                    4) program 0x64000 bit 14 = 1
2314                    */
2315                 temp = I915_READ(0x4600c);
2316                 temp &= 0xffff0000;
2317                 I915_WRITE(0x4600c, temp | 0x8124);
2318
2319                 temp = I915_READ(0x46010);
2320                 I915_WRITE(0x46010, temp | 1);
2321
2322                 temp = I915_READ(0x46034);
2323                 I915_WRITE(0x46034, temp | (1 << 24));
2324         } else {
2325                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2326         }
2327         I915_WRITE(DP_A, dpa_ctl);
2328
2329         POSTING_READ(DP_A);
2330         udelay(500);
2331 }
2332
2333 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334 {
2335         struct drm_device *dev = crtc->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338         int pipe = intel_crtc->pipe;
2339         u32 reg, temp;
2340
2341         /* enable normal train */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         if (IS_IVYBRIDGE(dev)) {
2345                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2347         } else {
2348                 temp &= ~FDI_LINK_TRAIN_NONE;
2349                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2350         }
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (HAS_PCH_CPT(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE;
2361         }
2362         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364         /* wait one idle pattern time */
2365         POSTING_READ(reg);
2366         udelay(1000);
2367
2368         /* IVB wants error correction enabled */
2369         if (IS_IVYBRIDGE(dev))
2370                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371                            FDI_FE_ERRC_ENABLE);
2372 }
2373
2374 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         u32 flags = I915_READ(SOUTH_CHICKEN1);
2378
2379         flags |= FDI_PHASE_SYNC_OVR(pipe);
2380         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2381         flags |= FDI_PHASE_SYNC_EN(pipe);
2382         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2383         POSTING_READ(SOUTH_CHICKEN1);
2384 }
2385
2386 static void ivb_modeset_global_resources(struct drm_device *dev)
2387 {
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         struct intel_crtc *pipe_B_crtc =
2390                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2391         struct intel_crtc *pipe_C_crtc =
2392                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2393         uint32_t temp;
2394
2395         /* When everything is off disable fdi C so that we could enable fdi B
2396          * with all lanes. XXX: This misses the case where a pipe is not using
2397          * any pch resources and so doesn't need any fdi lanes. */
2398         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2399                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2400                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2401
2402                 temp = I915_READ(SOUTH_CHICKEN1);
2403                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2404                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2405                 I915_WRITE(SOUTH_CHICKEN1, temp);
2406         }
2407 }
2408
2409 /* The FDI link training functions for ILK/Ibexpeak. */
2410 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2411 {
2412         struct drm_device *dev = crtc->dev;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415         int pipe = intel_crtc->pipe;
2416         int plane = intel_crtc->plane;
2417         u32 reg, temp, tries;
2418
2419         /* FDI needs bits from pipe & plane first */
2420         assert_pipe_enabled(dev_priv, pipe);
2421         assert_plane_enabled(dev_priv, plane);
2422
2423         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2424            for train result */
2425         reg = FDI_RX_IMR(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_RX_SYMBOL_LOCK;
2428         temp &= ~FDI_RX_BIT_LOCK;
2429         I915_WRITE(reg, temp);
2430         I915_READ(reg);
2431         udelay(150);
2432
2433         /* enable CPU FDI TX and PCH FDI RX */
2434         reg = FDI_TX_CTL(pipe);
2435         temp = I915_READ(reg);
2436         temp &= ~(7 << 19);
2437         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2441
2442         reg = FDI_RX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_LINK_TRAIN_NONE;
2445         temp |= FDI_LINK_TRAIN_PATTERN_1;
2446         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         /* Ironlake workaround, enable clock pointer after FDI enable*/
2452         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2453         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2454                    FDI_RX_PHASE_SYNC_POINTER_EN);
2455
2456         reg = FDI_RX_IIR(pipe);
2457         for (tries = 0; tries < 5; tries++) {
2458                 temp = I915_READ(reg);
2459                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2460
2461                 if ((temp & FDI_RX_BIT_LOCK)) {
2462                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2463                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2464                         break;
2465                 }
2466         }
2467         if (tries == 5)
2468                 DRM_ERROR("FDI train 1 fail!\n");
2469
2470         /* Train 2 */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         reg = FDI_RX_CTL(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_LINK_TRAIN_NONE;
2480         temp |= FDI_LINK_TRAIN_PATTERN_2;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         reg = FDI_RX_IIR(pipe);
2487         for (tries = 0; tries < 5; tries++) {
2488                 temp = I915_READ(reg);
2489                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2490
2491                 if (temp & FDI_RX_SYMBOL_LOCK) {
2492                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2493                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2494                         break;
2495                 }
2496         }
2497         if (tries == 5)
2498                 DRM_ERROR("FDI train 2 fail!\n");
2499
2500         DRM_DEBUG_KMS("FDI train done\n");
2501
2502 }
2503
2504 static const int snb_b_fdi_train_param[] = {
2505         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2506         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2507         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2508         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2509 };
2510
2511 /* The FDI link training functions for SNB/Cougarpoint. */
2512 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517         int pipe = intel_crtc->pipe;
2518         u32 reg, temp, i, retry;
2519
2520         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2521            for train result */
2522         reg = FDI_RX_IMR(pipe);
2523         temp = I915_READ(reg);
2524         temp &= ~FDI_RX_SYMBOL_LOCK;
2525         temp &= ~FDI_RX_BIT_LOCK;
2526         I915_WRITE(reg, temp);
2527
2528         POSTING_READ(reg);
2529         udelay(150);
2530
2531         /* enable CPU FDI TX and PCH FDI RX */
2532         reg = FDI_TX_CTL(pipe);
2533         temp = I915_READ(reg);
2534         temp &= ~(7 << 19);
2535         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2536         temp &= ~FDI_LINK_TRAIN_NONE;
2537         temp |= FDI_LINK_TRAIN_PATTERN_1;
2538         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539         /* SNB-B */
2540         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2541         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2542
2543         I915_WRITE(FDI_RX_MISC(pipe),
2544                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2554         }
2555         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 for (retry = 0; retry < 5; retry++) {
2573                         reg = FDI_RX_IIR(pipe);
2574                         temp = I915_READ(reg);
2575                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576                         if (temp & FDI_RX_BIT_LOCK) {
2577                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579                                 break;
2580                         }
2581                         udelay(50);
2582                 }
2583                 if (retry < 5)
2584                         break;
2585         }
2586         if (i == 4)
2587                 DRM_ERROR("FDI train 1 fail!\n");
2588
2589         /* Train 2 */
2590         reg = FDI_TX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_NONE;
2593         temp |= FDI_LINK_TRAIN_PATTERN_2;
2594         if (IS_GEN6(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 /* SNB-B */
2597                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598         }
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         if (HAS_PCH_CPT(dev)) {
2604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606         } else {
2607                 temp &= ~FDI_LINK_TRAIN_NONE;
2608                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609         }
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_SYMBOL_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 2 fail!\n");
2641
2642         DRM_DEBUG_KMS("FDI train done.\n");
2643 }
2644
2645 /* Manual link training for Ivy Bridge A0 parts */
2646 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647 {
2648         struct drm_device *dev = crtc->dev;
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651         int pipe = intel_crtc->pipe;
2652         u32 reg, temp, i;
2653
2654         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655            for train result */
2656         reg = FDI_RX_IMR(pipe);
2657         temp = I915_READ(reg);
2658         temp &= ~FDI_RX_SYMBOL_LOCK;
2659         temp &= ~FDI_RX_BIT_LOCK;
2660         I915_WRITE(reg, temp);
2661
2662         POSTING_READ(reg);
2663         udelay(150);
2664
2665         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666                       I915_READ(FDI_RX_IIR(pipe)));
2667
2668         /* enable CPU FDI TX and PCH FDI RX */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~(7 << 19);
2672         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677         temp |= FDI_COMPOSITE_SYNC;
2678         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
2680         I915_WRITE(FDI_RX_MISC(pipe),
2681                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
2683         reg = FDI_RX_CTL(pipe);
2684         temp = I915_READ(reg);
2685         temp &= ~FDI_LINK_TRAIN_AUTO;
2686         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2688         temp |= FDI_COMPOSITE_SYNC;
2689         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691         POSTING_READ(reg);
2692         udelay(150);
2693
2694         cpt_phase_pointer_enable(dev, pipe);
2695
2696         for (i = 0; i < 4; i++) {
2697                 reg = FDI_TX_CTL(pipe);
2698                 temp = I915_READ(reg);
2699                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2700                 temp |= snb_b_fdi_train_param[i];
2701                 I915_WRITE(reg, temp);
2702
2703                 POSTING_READ(reg);
2704                 udelay(500);
2705
2706                 reg = FDI_RX_IIR(pipe);
2707                 temp = I915_READ(reg);
2708                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709
2710                 if (temp & FDI_RX_BIT_LOCK ||
2711                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2712                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2713                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2714                         break;
2715                 }
2716         }
2717         if (i == 4)
2718                 DRM_ERROR("FDI train 1 fail!\n");
2719
2720         /* Train 2 */
2721         reg = FDI_TX_CTL(pipe);
2722         temp = I915_READ(reg);
2723         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2724         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2725         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727         I915_WRITE(reg, temp);
2728
2729         reg = FDI_RX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2733         I915_WRITE(reg, temp);
2734
2735         POSTING_READ(reg);
2736         udelay(150);
2737
2738         for (i = 0; i < 4; i++) {
2739                 reg = FDI_TX_CTL(pipe);
2740                 temp = I915_READ(reg);
2741                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2742                 temp |= snb_b_fdi_train_param[i];
2743                 I915_WRITE(reg, temp);
2744
2745                 POSTING_READ(reg);
2746                 udelay(500);
2747
2748                 reg = FDI_RX_IIR(pipe);
2749                 temp = I915_READ(reg);
2750                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2751
2752                 if (temp & FDI_RX_SYMBOL_LOCK) {
2753                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2754                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2755                         break;
2756                 }
2757         }
2758         if (i == 4)
2759                 DRM_ERROR("FDI train 2 fail!\n");
2760
2761         DRM_DEBUG_KMS("FDI train done.\n");
2762 }
2763
2764 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2765 {
2766         struct drm_device *dev = intel_crtc->base.dev;
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         int pipe = intel_crtc->pipe;
2769         u32 reg, temp;
2770
2771
2772         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2773         reg = FDI_RX_CTL(pipe);
2774         temp = I915_READ(reg);
2775         temp &= ~((0x7 << 19) | (0x7 << 16));
2776         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2777         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2778         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2779
2780         POSTING_READ(reg);
2781         udelay(200);
2782
2783         /* Switch from Rawclk to PCDclk */
2784         temp = I915_READ(reg);
2785         I915_WRITE(reg, temp | FDI_PCDCLK);
2786
2787         POSTING_READ(reg);
2788         udelay(200);
2789
2790         /* On Haswell, the PLL configuration for ports and pipes is handled
2791          * separately, as part of DDI setup */
2792         if (!IS_HASWELL(dev)) {
2793                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2794                 reg = FDI_TX_CTL(pipe);
2795                 temp = I915_READ(reg);
2796                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2797                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2798
2799                         POSTING_READ(reg);
2800                         udelay(100);
2801                 }
2802         }
2803 }
2804
2805 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812         /* Switch from PCDclk to Rawclk */
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2816
2817         /* Disable CPU FDI TX PLL */
2818         reg = FDI_TX_CTL(pipe);
2819         temp = I915_READ(reg);
2820         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824
2825         reg = FDI_RX_CTL(pipe);
2826         temp = I915_READ(reg);
2827         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2828
2829         /* Wait for the clocks to turn off. */
2830         POSTING_READ(reg);
2831         udelay(100);
2832 }
2833
2834 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2835 {
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         u32 flags = I915_READ(SOUTH_CHICKEN1);
2838
2839         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2840         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2841         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2842         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2843         POSTING_READ(SOUTH_CHICKEN1);
2844 }
2845 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* disable CPU FDI tx and PCH FDI rx */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2857         POSTING_READ(reg);
2858
2859         reg = FDI_RX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         temp &= ~(0x7 << 16);
2862         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2863         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2864
2865         POSTING_READ(reg);
2866         udelay(100);
2867
2868         /* Ironlake workaround, disable clock pointer after downing FDI */
2869         if (HAS_PCH_IBX(dev)) {
2870                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2871         } else if (HAS_PCH_CPT(dev)) {
2872                 cpt_phase_pointer_disable(dev, pipe);
2873         }
2874
2875         /* still set train pattern 1 */
2876         reg = FDI_TX_CTL(pipe);
2877         temp = I915_READ(reg);
2878         temp &= ~FDI_LINK_TRAIN_NONE;
2879         temp |= FDI_LINK_TRAIN_PATTERN_1;
2880         I915_WRITE(reg, temp);
2881
2882         reg = FDI_RX_CTL(pipe);
2883         temp = I915_READ(reg);
2884         if (HAS_PCH_CPT(dev)) {
2885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2886                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2887         } else {
2888                 temp &= ~FDI_LINK_TRAIN_NONE;
2889                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2890         }
2891         /* BPC in FDI rx is consistent with that in PIPECONF */
2892         temp &= ~(0x07 << 16);
2893         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2894         I915_WRITE(reg, temp);
2895
2896         POSTING_READ(reg);
2897         udelay(100);
2898 }
2899
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         unsigned long flags;
2905         bool pending;
2906
2907         if (atomic_read(&dev_priv->mm.wedged))
2908                 return false;
2909
2910         spin_lock_irqsave(&dev->event_lock, flags);
2911         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2912         spin_unlock_irqrestore(&dev->event_lock, flags);
2913
2914         return pending;
2915 }
2916
2917 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2918 {
2919         struct drm_device *dev = crtc->dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922         if (crtc->fb == NULL)
2923                 return;
2924
2925         wait_event(dev_priv->pending_flip_queue,
2926                    !intel_crtc_has_pending_flip(crtc));
2927
2928         mutex_lock(&dev->struct_mutex);
2929         intel_finish_fb(crtc->fb);
2930         mutex_unlock(&dev->struct_mutex);
2931 }
2932
2933 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2934 {
2935         struct drm_device *dev = crtc->dev;
2936         struct intel_encoder *intel_encoder;
2937
2938         /*
2939          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2940          * must be driven by its own crtc; no sharing is possible.
2941          */
2942         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2943                 switch (intel_encoder->type) {
2944                 case INTEL_OUTPUT_EDP:
2945                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2946                                 return false;
2947                         continue;
2948                 }
2949         }
2950
2951         return true;
2952 }
2953
2954 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2955 {
2956         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2957 }
2958
2959 /* Program iCLKIP clock to the desired frequency */
2960 static void lpt_program_iclkip(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2965         u32 temp;
2966
2967         /* It is necessary to ungate the pixclk gate prior to programming
2968          * the divisors, and gate it back when it is done.
2969          */
2970         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2971
2972         /* Disable SSCCTL */
2973         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2974                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2975                                         SBI_SSCCTL_DISABLE);
2976
2977         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2978         if (crtc->mode.clock == 20000) {
2979                 auxdiv = 1;
2980                 divsel = 0x41;
2981                 phaseinc = 0x20;
2982         } else {
2983                 /* The iCLK virtual clock root frequency is in MHz,
2984                  * but the crtc->mode.clock in in KHz. To get the divisors,
2985                  * it is necessary to divide one by another, so we
2986                  * convert the virtual clock precision to KHz here for higher
2987                  * precision.
2988                  */
2989                 u32 iclk_virtual_root_freq = 172800 * 1000;
2990                 u32 iclk_pi_range = 64;
2991                 u32 desired_divisor, msb_divisor_value, pi_value;
2992
2993                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2994                 msb_divisor_value = desired_divisor / iclk_pi_range;
2995                 pi_value = desired_divisor % iclk_pi_range;
2996
2997                 auxdiv = 0;
2998                 divsel = msb_divisor_value - 2;
2999                 phaseinc = pi_value;
3000         }
3001
3002         /* This should not happen with any sane values */
3003         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3004                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3005         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3006                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3007
3008         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3009                         crtc->mode.clock,
3010                         auxdiv,
3011                         divsel,
3012                         phasedir,
3013                         phaseinc);
3014
3015         /* Program SSCDIVINTPHASE6 */
3016         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3017         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3018         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3019         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3020         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3021         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3022         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3023
3024         intel_sbi_write(dev_priv,
3025                         SBI_SSCDIVINTPHASE6,
3026                         temp);
3027
3028         /* Program SSCAUXDIV */
3029         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3030         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3031         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3032         intel_sbi_write(dev_priv,
3033                         SBI_SSCAUXDIV6,
3034                         temp);
3035
3036
3037         /* Enable modulator and associated divider */
3038         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3039         temp &= ~SBI_SSCCTL_DISABLE;
3040         intel_sbi_write(dev_priv,
3041                         SBI_SSCCTL6,
3042                         temp);
3043
3044         /* Wait for initialization time */
3045         udelay(24);
3046
3047         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3048 }
3049
3050 /*
3051  * Enable PCH resources required for PCH ports:
3052  *   - PCH PLLs
3053  *   - FDI training & RX/TX
3054  *   - update transcoder timings
3055  *   - DP transcoding bits
3056  *   - transcoder
3057  */
3058 static void ironlake_pch_enable(struct drm_crtc *crtc)
3059 {
3060         struct drm_device *dev = crtc->dev;
3061         struct drm_i915_private *dev_priv = dev->dev_private;
3062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3063         int pipe = intel_crtc->pipe;
3064         u32 reg, temp;
3065
3066         assert_transcoder_disabled(dev_priv, pipe);
3067
3068         /* Write the TU size bits before fdi link training, so that error
3069          * detection works. */
3070         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3071                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3072
3073         /* For PCH output, training FDI link */
3074         dev_priv->display.fdi_link_train(crtc);
3075
3076         /* XXX: pch pll's can be enabled any time before we enable the PCH
3077          * transcoder, and we actually should do this to not upset any PCH
3078          * transcoder that already use the clock when we share it.
3079          *
3080          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3081          * unconditionally resets the pll - we need that to have the right LVDS
3082          * enable sequence. */
3083         ironlake_enable_pch_pll(intel_crtc);
3084
3085         if (HAS_PCH_CPT(dev)) {
3086                 u32 sel;
3087
3088                 temp = I915_READ(PCH_DPLL_SEL);
3089                 switch (pipe) {
3090                 default:
3091                 case 0:
3092                         temp |= TRANSA_DPLL_ENABLE;
3093                         sel = TRANSA_DPLLB_SEL;
3094                         break;
3095                 case 1:
3096                         temp |= TRANSB_DPLL_ENABLE;
3097                         sel = TRANSB_DPLLB_SEL;
3098                         break;
3099                 case 2:
3100                         temp |= TRANSC_DPLL_ENABLE;
3101                         sel = TRANSC_DPLLB_SEL;
3102                         break;
3103                 }
3104                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3105                         temp |= sel;
3106                 else
3107                         temp &= ~sel;
3108                 I915_WRITE(PCH_DPLL_SEL, temp);
3109         }
3110
3111         /* set transcoder timing, panel must allow it */
3112         assert_panel_unlocked(dev_priv, pipe);
3113         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3114         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3115         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3116
3117         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3118         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3119         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3120         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3121
3122         intel_fdi_normal_train(crtc);
3123
3124         /* For PCH DP, enable TRANS_DP_CTL */
3125         if (HAS_PCH_CPT(dev) &&
3126             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3127              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3128                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3129                 reg = TRANS_DP_CTL(pipe);
3130                 temp = I915_READ(reg);
3131                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3132                           TRANS_DP_SYNC_MASK |
3133                           TRANS_DP_BPC_MASK);
3134                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3135                          TRANS_DP_ENH_FRAMING);
3136                 temp |= bpc << 9; /* same format but at 11:9 */
3137
3138                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3139                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3140                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3141                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3142
3143                 switch (intel_trans_dp_port_sel(crtc)) {
3144                 case PCH_DP_B:
3145                         temp |= TRANS_DP_PORT_SEL_B;
3146                         break;
3147                 case PCH_DP_C:
3148                         temp |= TRANS_DP_PORT_SEL_C;
3149                         break;
3150                 case PCH_DP_D:
3151                         temp |= TRANS_DP_PORT_SEL_D;
3152                         break;
3153                 default:
3154                         BUG();
3155                 }
3156
3157                 I915_WRITE(reg, temp);
3158         }
3159
3160         ironlake_enable_pch_transcoder(dev_priv, pipe);
3161 }
3162
3163 static void lpt_pch_enable(struct drm_crtc *crtc)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3169
3170         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3171
3172         lpt_program_iclkip(crtc);
3173
3174         /* Set transcoder timing. */
3175         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3176         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3177         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3178
3179         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3180         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3181         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3182         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3183
3184         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3185 }
3186
3187 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3188 {
3189         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3190
3191         if (pll == NULL)
3192                 return;
3193
3194         if (pll->refcount == 0) {
3195                 WARN(1, "bad PCH PLL refcount\n");
3196                 return;
3197         }
3198
3199         --pll->refcount;
3200         intel_crtc->pch_pll = NULL;
3201 }
3202
3203 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3204 {
3205         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3206         struct intel_pch_pll *pll;
3207         int i;
3208
3209         pll = intel_crtc->pch_pll;
3210         if (pll) {
3211                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3212                               intel_crtc->base.base.id, pll->pll_reg);
3213                 goto prepare;
3214         }
3215
3216         if (HAS_PCH_IBX(dev_priv->dev)) {
3217                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3218                 i = intel_crtc->pipe;
3219                 pll = &dev_priv->pch_plls[i];
3220
3221                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3222                               intel_crtc->base.base.id, pll->pll_reg);
3223
3224                 goto found;
3225         }
3226
3227         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3228                 pll = &dev_priv->pch_plls[i];
3229
3230                 /* Only want to check enabled timings first */
3231                 if (pll->refcount == 0)
3232                         continue;
3233
3234                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3235                     fp == I915_READ(pll->fp0_reg)) {
3236                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3237                                       intel_crtc->base.base.id,
3238                                       pll->pll_reg, pll->refcount, pll->active);
3239
3240                         goto found;
3241                 }
3242         }
3243
3244         /* Ok no matching timings, maybe there's a free one? */
3245         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3246                 pll = &dev_priv->pch_plls[i];
3247                 if (pll->refcount == 0) {
3248                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3249                                       intel_crtc->base.base.id, pll->pll_reg);
3250                         goto found;
3251                 }
3252         }
3253
3254         return NULL;
3255
3256 found:
3257         intel_crtc->pch_pll = pll;
3258         pll->refcount++;
3259         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3260 prepare: /* separate function? */
3261         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3262
3263         /* Wait for the clocks to stabilize before rewriting the regs */
3264         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3265         POSTING_READ(pll->pll_reg);
3266         udelay(150);
3267
3268         I915_WRITE(pll->fp0_reg, fp);
3269         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3270         pll->on = false;
3271         return pll;
3272 }
3273
3274 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3275 {
3276         struct drm_i915_private *dev_priv = dev->dev_private;
3277         int dslreg = PIPEDSL(pipe);
3278         u32 temp;
3279
3280         temp = I915_READ(dslreg);
3281         udelay(500);
3282         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3283                 if (wait_for(I915_READ(dslreg) != temp, 5))
3284                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3285         }
3286 }
3287
3288 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         struct intel_encoder *encoder;
3294         int pipe = intel_crtc->pipe;
3295         int plane = intel_crtc->plane;
3296         u32 temp;
3297         bool is_pch_port;
3298
3299         WARN_ON(!crtc->enabled);
3300
3301         if (intel_crtc->active)
3302                 return;
3303
3304         intel_crtc->active = true;
3305         intel_update_watermarks(dev);
3306
3307         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3308                 temp = I915_READ(PCH_LVDS);
3309                 if ((temp & LVDS_PORT_EN) == 0)
3310                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3311         }
3312
3313         is_pch_port = ironlake_crtc_driving_pch(crtc);
3314
3315         if (is_pch_port) {
3316                 /* Note: FDI PLL enabling _must_ be done before we enable the
3317                  * cpu pipes, hence this is separate from all the other fdi/pch
3318                  * enabling. */
3319                 ironlake_fdi_pll_enable(intel_crtc);
3320         } else {
3321                 assert_fdi_tx_disabled(dev_priv, pipe);
3322                 assert_fdi_rx_disabled(dev_priv, pipe);
3323         }
3324
3325         for_each_encoder_on_crtc(dev, crtc, encoder)
3326                 if (encoder->pre_enable)
3327                         encoder->pre_enable(encoder);
3328
3329         /* Enable panel fitting for LVDS */
3330         if (dev_priv->pch_pf_size &&
3331             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3332              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3333                 /* Force use of hard-coded filter coefficients
3334                  * as some pre-programmed values are broken,
3335                  * e.g. x201.
3336                  */
3337                 if (IS_IVYBRIDGE(dev))
3338                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3339                                                  PF_PIPE_SEL_IVB(pipe));
3340                 else
3341                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3342                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3343                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3344         }
3345
3346         /*
3347          * On ILK+ LUT must be loaded before the pipe is running but with
3348          * clocks enabled
3349          */
3350         intel_crtc_load_lut(crtc);
3351
3352         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3353         intel_enable_plane(dev_priv, plane, pipe);
3354
3355         if (is_pch_port)
3356                 ironlake_pch_enable(crtc);
3357
3358         mutex_lock(&dev->struct_mutex);
3359         intel_update_fbc(dev);
3360         mutex_unlock(&dev->struct_mutex);
3361
3362         intel_crtc_update_cursor(crtc, true);
3363
3364         for_each_encoder_on_crtc(dev, crtc, encoder)
3365                 encoder->enable(encoder);
3366
3367         if (HAS_PCH_CPT(dev))
3368                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3369
3370         /*
3371          * There seems to be a race in PCH platform hw (at least on some
3372          * outputs) where an enabled pipe still completes any pageflip right
3373          * away (as if the pipe is off) instead of waiting for vblank. As soon
3374          * as the first vblank happend, everything works as expected. Hence just
3375          * wait for one vblank before returning to avoid strange things
3376          * happening.
3377          */
3378         intel_wait_for_vblank(dev, intel_crtc->pipe);
3379 }
3380
3381 static void haswell_crtc_enable(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         struct intel_encoder *encoder;
3387         int pipe = intel_crtc->pipe;
3388         int plane = intel_crtc->plane;
3389         bool is_pch_port;
3390
3391         WARN_ON(!crtc->enabled);
3392
3393         if (intel_crtc->active)
3394                 return;
3395
3396         intel_crtc->active = true;
3397         intel_update_watermarks(dev);
3398
3399         is_pch_port = haswell_crtc_driving_pch(crtc);
3400
3401         if (is_pch_port)
3402                 dev_priv->display.fdi_link_train(crtc);
3403
3404         for_each_encoder_on_crtc(dev, crtc, encoder)
3405                 if (encoder->pre_enable)
3406                         encoder->pre_enable(encoder);
3407
3408         intel_ddi_enable_pipe_clock(intel_crtc);
3409
3410         /* Enable panel fitting for eDP */
3411         if (dev_priv->pch_pf_size &&
3412             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3413                 /* Force use of hard-coded filter coefficients
3414                  * as some pre-programmed values are broken,
3415                  * e.g. x201.
3416                  */
3417                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3418                                          PF_PIPE_SEL_IVB(pipe));
3419                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3420                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3421         }
3422
3423         /*
3424          * On ILK+ LUT must be loaded before the pipe is running but with
3425          * clocks enabled
3426          */
3427         intel_crtc_load_lut(crtc);
3428
3429         intel_ddi_set_pipe_settings(crtc);
3430         intel_ddi_enable_pipe_func(crtc);
3431
3432         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3433         intel_enable_plane(dev_priv, plane, pipe);
3434
3435         if (is_pch_port)
3436                 lpt_pch_enable(crtc);
3437
3438         mutex_lock(&dev->struct_mutex);
3439         intel_update_fbc(dev);
3440         mutex_unlock(&dev->struct_mutex);
3441
3442         intel_crtc_update_cursor(crtc, true);
3443
3444         for_each_encoder_on_crtc(dev, crtc, encoder)
3445                 encoder->enable(encoder);
3446
3447         /*
3448          * There seems to be a race in PCH platform hw (at least on some
3449          * outputs) where an enabled pipe still completes any pageflip right
3450          * away (as if the pipe is off) instead of waiting for vblank. As soon
3451          * as the first vblank happend, everything works as expected. Hence just
3452          * wait for one vblank before returning to avoid strange things
3453          * happening.
3454          */
3455         intel_wait_for_vblank(dev, intel_crtc->pipe);
3456 }
3457
3458 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         struct intel_encoder *encoder;
3464         int pipe = intel_crtc->pipe;
3465         int plane = intel_crtc->plane;
3466         u32 reg, temp;
3467
3468
3469         if (!intel_crtc->active)
3470                 return;
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 encoder->disable(encoder);
3474
3475         intel_crtc_wait_for_pending_flips(crtc);
3476         drm_vblank_off(dev, pipe);
3477         intel_crtc_update_cursor(crtc, false);
3478
3479         intel_disable_plane(dev_priv, plane, pipe);
3480
3481         if (dev_priv->cfb_plane == plane)
3482                 intel_disable_fbc(dev);
3483
3484         intel_disable_pipe(dev_priv, pipe);
3485
3486         /* Disable PF */
3487         I915_WRITE(PF_CTL(pipe), 0);
3488         I915_WRITE(PF_WIN_SZ(pipe), 0);
3489
3490         for_each_encoder_on_crtc(dev, crtc, encoder)
3491                 if (encoder->post_disable)
3492                         encoder->post_disable(encoder);
3493
3494         ironlake_fdi_disable(crtc);
3495
3496         ironlake_disable_pch_transcoder(dev_priv, pipe);
3497
3498         if (HAS_PCH_CPT(dev)) {
3499                 /* disable TRANS_DP_CTL */
3500                 reg = TRANS_DP_CTL(pipe);
3501                 temp = I915_READ(reg);
3502                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3503                 temp |= TRANS_DP_PORT_SEL_NONE;
3504                 I915_WRITE(reg, temp);
3505
3506                 /* disable DPLL_SEL */
3507                 temp = I915_READ(PCH_DPLL_SEL);
3508                 switch (pipe) {
3509                 case 0:
3510                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3511                         break;
3512                 case 1:
3513                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3514                         break;
3515                 case 2:
3516                         /* C shares PLL A or B */
3517                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3518                         break;
3519                 default:
3520                         BUG(); /* wtf */
3521                 }
3522                 I915_WRITE(PCH_DPLL_SEL, temp);
3523         }
3524
3525         /* disable PCH DPLL */
3526         intel_disable_pch_pll(intel_crtc);
3527
3528         ironlake_fdi_pll_disable(intel_crtc);
3529
3530         intel_crtc->active = false;
3531         intel_update_watermarks(dev);
3532
3533         mutex_lock(&dev->struct_mutex);
3534         intel_update_fbc(dev);
3535         mutex_unlock(&dev->struct_mutex);
3536 }
3537
3538 static void haswell_crtc_disable(struct drm_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543         struct intel_encoder *encoder;
3544         int pipe = intel_crtc->pipe;
3545         int plane = intel_crtc->plane;
3546         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3547         bool is_pch_port;
3548
3549         if (!intel_crtc->active)
3550                 return;
3551
3552         is_pch_port = haswell_crtc_driving_pch(crtc);
3553
3554         for_each_encoder_on_crtc(dev, crtc, encoder)
3555                 encoder->disable(encoder);
3556
3557         intel_crtc_wait_for_pending_flips(crtc);
3558         drm_vblank_off(dev, pipe);
3559         intel_crtc_update_cursor(crtc, false);
3560
3561         intel_disable_plane(dev_priv, plane, pipe);
3562
3563         if (dev_priv->cfb_plane == plane)
3564                 intel_disable_fbc(dev);
3565
3566         intel_disable_pipe(dev_priv, pipe);
3567
3568         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3569
3570         /* Disable PF */
3571         I915_WRITE(PF_CTL(pipe), 0);
3572         I915_WRITE(PF_WIN_SZ(pipe), 0);
3573
3574         intel_ddi_disable_pipe_clock(intel_crtc);
3575
3576         for_each_encoder_on_crtc(dev, crtc, encoder)
3577                 if (encoder->post_disable)
3578                         encoder->post_disable(encoder);
3579
3580         if (is_pch_port) {
3581                 lpt_disable_pch_transcoder(dev_priv);
3582                 intel_ddi_fdi_disable(crtc);
3583         }
3584
3585         intel_crtc->active = false;
3586         intel_update_watermarks(dev);
3587
3588         mutex_lock(&dev->struct_mutex);
3589         intel_update_fbc(dev);
3590         mutex_unlock(&dev->struct_mutex);
3591 }
3592
3593 static void ironlake_crtc_off(struct drm_crtc *crtc)
3594 {
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         intel_put_pch_pll(intel_crtc);
3597 }
3598
3599 static void haswell_crtc_off(struct drm_crtc *crtc)
3600 {
3601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602
3603         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3604          * start using it. */
3605         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3606
3607         intel_ddi_put_crtc_pll(crtc);
3608 }
3609
3610 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3611 {
3612         if (!enable && intel_crtc->overlay) {
3613                 struct drm_device *dev = intel_crtc->base.dev;
3614                 struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616                 mutex_lock(&dev->struct_mutex);
3617                 dev_priv->mm.interruptible = false;
3618                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3619                 dev_priv->mm.interruptible = true;
3620                 mutex_unlock(&dev->struct_mutex);
3621         }
3622
3623         /* Let userspace switch the overlay on again. In most cases userspace
3624          * has to recompute where to put it anyway.
3625          */
3626 }
3627
3628 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3629 {
3630         struct drm_device *dev = crtc->dev;
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633         struct intel_encoder *encoder;
3634         int pipe = intel_crtc->pipe;
3635         int plane = intel_crtc->plane;
3636
3637         WARN_ON(!crtc->enabled);
3638
3639         if (intel_crtc->active)
3640                 return;
3641
3642         intel_crtc->active = true;
3643         intel_update_watermarks(dev);
3644
3645         intel_enable_pll(dev_priv, pipe);
3646         intel_enable_pipe(dev_priv, pipe, false);
3647         intel_enable_plane(dev_priv, plane, pipe);
3648
3649         intel_crtc_load_lut(crtc);
3650         intel_update_fbc(dev);
3651
3652         /* Give the overlay scaler a chance to enable if it's on this pipe */
3653         intel_crtc_dpms_overlay(intel_crtc, true);
3654         intel_crtc_update_cursor(crtc, true);
3655
3656         for_each_encoder_on_crtc(dev, crtc, encoder)
3657                 encoder->enable(encoder);
3658 }
3659
3660 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3661 {
3662         struct drm_device *dev = crtc->dev;
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3665         struct intel_encoder *encoder;
3666         int pipe = intel_crtc->pipe;
3667         int plane = intel_crtc->plane;
3668
3669
3670         if (!intel_crtc->active)
3671                 return;
3672
3673         for_each_encoder_on_crtc(dev, crtc, encoder)
3674                 encoder->disable(encoder);
3675
3676         /* Give the overlay scaler a chance to disable if it's on this pipe */
3677         intel_crtc_wait_for_pending_flips(crtc);
3678         drm_vblank_off(dev, pipe);
3679         intel_crtc_dpms_overlay(intel_crtc, false);
3680         intel_crtc_update_cursor(crtc, false);
3681
3682         if (dev_priv->cfb_plane == plane)
3683                 intel_disable_fbc(dev);
3684
3685         intel_disable_plane(dev_priv, plane, pipe);
3686         intel_disable_pipe(dev_priv, pipe);
3687         intel_disable_pll(dev_priv, pipe);
3688
3689         intel_crtc->active = false;
3690         intel_update_fbc(dev);
3691         intel_update_watermarks(dev);
3692 }
3693
3694 static void i9xx_crtc_off(struct drm_crtc *crtc)
3695 {
3696 }
3697
3698 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3699                                     bool enabled)
3700 {
3701         struct drm_device *dev = crtc->dev;
3702         struct drm_i915_master_private *master_priv;
3703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3704         int pipe = intel_crtc->pipe;
3705
3706         if (!dev->primary->master)
3707                 return;
3708
3709         master_priv = dev->primary->master->driver_priv;
3710         if (!master_priv->sarea_priv)
3711                 return;
3712
3713         switch (pipe) {
3714         case 0:
3715                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3716                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3717                 break;
3718         case 1:
3719                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3720                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3721                 break;
3722         default:
3723                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3724                 break;
3725         }
3726 }
3727
3728 /**
3729  * Sets the power management mode of the pipe and plane.
3730  */
3731 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         struct intel_encoder *intel_encoder;
3736         bool enable = false;
3737
3738         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3739                 enable |= intel_encoder->connectors_active;
3740
3741         if (enable)
3742                 dev_priv->display.crtc_enable(crtc);
3743         else
3744                 dev_priv->display.crtc_disable(crtc);
3745
3746         intel_crtc_update_sarea(crtc, enable);
3747 }
3748
3749 static void intel_crtc_noop(struct drm_crtc *crtc)
3750 {
3751 }
3752
3753 static void intel_crtc_disable(struct drm_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->dev;
3756         struct drm_connector *connector;
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758
3759         /* crtc should still be enabled when we disable it. */
3760         WARN_ON(!crtc->enabled);
3761
3762         dev_priv->display.crtc_disable(crtc);
3763         intel_crtc_update_sarea(crtc, false);
3764         dev_priv->display.off(crtc);
3765
3766         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3767         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3768
3769         if (crtc->fb) {
3770                 mutex_lock(&dev->struct_mutex);
3771                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3772                 mutex_unlock(&dev->struct_mutex);
3773                 crtc->fb = NULL;
3774         }
3775
3776         /* Update computed state. */
3777         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3778                 if (!connector->encoder || !connector->encoder->crtc)
3779                         continue;
3780
3781                 if (connector->encoder->crtc != crtc)
3782                         continue;
3783
3784                 connector->dpms = DRM_MODE_DPMS_OFF;
3785                 to_intel_encoder(connector->encoder)->connectors_active = false;
3786         }
3787 }
3788
3789 void intel_modeset_disable(struct drm_device *dev)
3790 {
3791         struct drm_crtc *crtc;
3792
3793         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3794                 if (crtc->enabled)
3795                         intel_crtc_disable(crtc);
3796         }
3797 }
3798
3799 void intel_encoder_noop(struct drm_encoder *encoder)
3800 {
3801 }
3802
3803 void intel_encoder_destroy(struct drm_encoder *encoder)
3804 {
3805         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3806
3807         drm_encoder_cleanup(encoder);
3808         kfree(intel_encoder);
3809 }
3810
3811 /* Simple dpms helper for encodres with just one connector, no cloning and only
3812  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3813  * state of the entire output pipe. */
3814 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3815 {
3816         if (mode == DRM_MODE_DPMS_ON) {
3817                 encoder->connectors_active = true;
3818
3819                 intel_crtc_update_dpms(encoder->base.crtc);
3820         } else {
3821                 encoder->connectors_active = false;
3822
3823                 intel_crtc_update_dpms(encoder->base.crtc);
3824         }
3825 }
3826
3827 /* Cross check the actual hw state with our own modeset state tracking (and it's
3828  * internal consistency). */
3829 static void intel_connector_check_state(struct intel_connector *connector)
3830 {
3831         if (connector->get_hw_state(connector)) {
3832                 struct intel_encoder *encoder = connector->encoder;
3833                 struct drm_crtc *crtc;
3834                 bool encoder_enabled;
3835                 enum pipe pipe;
3836
3837                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3838                               connector->base.base.id,
3839                               drm_get_connector_name(&connector->base));
3840
3841                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3842                      "wrong connector dpms state\n");
3843                 WARN(connector->base.encoder != &encoder->base,
3844                      "active connector not linked to encoder\n");
3845                 WARN(!encoder->connectors_active,
3846                      "encoder->connectors_active not set\n");
3847
3848                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3849                 WARN(!encoder_enabled, "encoder not enabled\n");
3850                 if (WARN_ON(!encoder->base.crtc))
3851                         return;
3852
3853                 crtc = encoder->base.crtc;
3854
3855                 WARN(!crtc->enabled, "crtc not enabled\n");
3856                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3857                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3858                      "encoder active on the wrong pipe\n");
3859         }
3860 }
3861
3862 /* Even simpler default implementation, if there's really no special case to
3863  * consider. */
3864 void intel_connector_dpms(struct drm_connector *connector, int mode)
3865 {
3866         struct intel_encoder *encoder = intel_attached_encoder(connector);
3867
3868         /* All the simple cases only support two dpms states. */
3869         if (mode != DRM_MODE_DPMS_ON)
3870                 mode = DRM_MODE_DPMS_OFF;
3871
3872         if (mode == connector->dpms)
3873                 return;
3874
3875         connector->dpms = mode;
3876
3877         /* Only need to change hw state when actually enabled */
3878         if (encoder->base.crtc)
3879                 intel_encoder_dpms(encoder, mode);
3880         else
3881                 WARN_ON(encoder->connectors_active != false);
3882
3883         intel_modeset_check_state(connector->dev);
3884 }
3885
3886 /* Simple connector->get_hw_state implementation for encoders that support only
3887  * one connector and no cloning and hence the encoder state determines the state
3888  * of the connector. */
3889 bool intel_connector_get_hw_state(struct intel_connector *connector)
3890 {
3891         enum pipe pipe = 0;
3892         struct intel_encoder *encoder = connector->encoder;
3893
3894         return encoder->get_hw_state(encoder, &pipe);
3895 }
3896
3897 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3898                                   const struct drm_display_mode *mode,
3899                                   struct drm_display_mode *adjusted_mode)
3900 {
3901         struct drm_device *dev = crtc->dev;
3902
3903         if (HAS_PCH_SPLIT(dev)) {
3904                 /* FDI link clock is fixed at 2.7G */
3905                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3906                         return false;
3907         }
3908
3909         /* All interlaced capable intel hw wants timings in frames. Note though
3910          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3911          * timings, so we need to be careful not to clobber these.*/
3912         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3913                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3914
3915         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3916          * with a hsync front porch of 0.
3917          */
3918         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3919                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3920                 return false;
3921
3922         return true;
3923 }
3924
3925 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3926 {
3927         return 400000; /* FIXME */
3928 }
3929
3930 static int i945_get_display_clock_speed(struct drm_device *dev)
3931 {
3932         return 400000;
3933 }
3934
3935 static int i915_get_display_clock_speed(struct drm_device *dev)
3936 {
3937         return 333000;
3938 }
3939
3940 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3941 {
3942         return 200000;
3943 }
3944
3945 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3946 {
3947         u16 gcfgc = 0;
3948
3949         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3950
3951         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3952                 return 133000;
3953         else {
3954                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3955                 case GC_DISPLAY_CLOCK_333_MHZ:
3956                         return 333000;
3957                 default:
3958                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3959                         return 190000;
3960                 }
3961         }
3962 }
3963
3964 static int i865_get_display_clock_speed(struct drm_device *dev)
3965 {
3966         return 266000;
3967 }
3968
3969 static int i855_get_display_clock_speed(struct drm_device *dev)
3970 {
3971         u16 hpllcc = 0;
3972         /* Assume that the hardware is in the high speed state.  This
3973          * should be the default.
3974          */
3975         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3976         case GC_CLOCK_133_200:
3977         case GC_CLOCK_100_200:
3978                 return 200000;
3979         case GC_CLOCK_166_250:
3980                 return 250000;
3981         case GC_CLOCK_100_133:
3982                 return 133000;
3983         }
3984
3985         /* Shouldn't happen */
3986         return 0;
3987 }
3988
3989 static int i830_get_display_clock_speed(struct drm_device *dev)
3990 {
3991         return 133000;
3992 }
3993
3994 struct fdi_m_n {
3995         u32        tu;
3996         u32        gmch_m;
3997         u32        gmch_n;
3998         u32        link_m;
3999         u32        link_n;
4000 };
4001
4002 static void
4003 fdi_reduce_ratio(u32 *num, u32 *den)
4004 {
4005         while (*num > 0xffffff || *den > 0xffffff) {
4006                 *num >>= 1;
4007                 *den >>= 1;
4008         }
4009 }
4010
4011 static void
4012 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4013                      int link_clock, struct fdi_m_n *m_n)
4014 {
4015         m_n->tu = 64; /* default size */
4016
4017         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4018         m_n->gmch_m = bits_per_pixel * pixel_clock;
4019         m_n->gmch_n = link_clock * nlanes * 8;
4020         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4021
4022         m_n->link_m = pixel_clock;
4023         m_n->link_n = link_clock;
4024         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4025 }
4026
4027 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4028 {
4029         if (i915_panel_use_ssc >= 0)
4030                 return i915_panel_use_ssc != 0;
4031         return dev_priv->lvds_use_ssc
4032                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4033 }
4034
4035 /**
4036  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4037  * @crtc: CRTC structure
4038  * @mode: requested mode
4039  *
4040  * A pipe may be connected to one or more outputs.  Based on the depth of the
4041  * attached framebuffer, choose a good color depth to use on the pipe.
4042  *
4043  * If possible, match the pipe depth to the fb depth.  In some cases, this
4044  * isn't ideal, because the connected output supports a lesser or restricted
4045  * set of depths.  Resolve that here:
4046  *    LVDS typically supports only 6bpc, so clamp down in that case
4047  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4048  *    Displays may support a restricted set as well, check EDID and clamp as
4049  *      appropriate.
4050  *    DP may want to dither down to 6bpc to fit larger modes
4051  *
4052  * RETURNS:
4053  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4054  * true if they don't match).
4055  */
4056 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4057                                          struct drm_framebuffer *fb,
4058                                          unsigned int *pipe_bpp,
4059                                          struct drm_display_mode *mode)
4060 {
4061         struct drm_device *dev = crtc->dev;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         struct drm_connector *connector;
4064         struct intel_encoder *intel_encoder;
4065         unsigned int display_bpc = UINT_MAX, bpc;
4066
4067         /* Walk the encoders & connectors on this crtc, get min bpc */
4068         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4069
4070                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4071                         unsigned int lvds_bpc;
4072
4073                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4074                             LVDS_A3_POWER_UP)
4075                                 lvds_bpc = 8;
4076                         else
4077                                 lvds_bpc = 6;
4078
4079                         if (lvds_bpc < display_bpc) {
4080                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4081                                 display_bpc = lvds_bpc;
4082                         }
4083                         continue;
4084                 }
4085
4086                 /* Not one of the known troublemakers, check the EDID */
4087                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4088                                     head) {
4089                         if (connector->encoder != &intel_encoder->base)
4090                                 continue;
4091
4092                         /* Don't use an invalid EDID bpc value */
4093                         if (connector->display_info.bpc &&
4094                             connector->display_info.bpc < display_bpc) {
4095                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4096                                 display_bpc = connector->display_info.bpc;
4097                         }
4098                 }
4099
4100                 /*
4101                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4102                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4103                  */
4104                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4105                         if (display_bpc > 8 && display_bpc < 12) {
4106                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4107                                 display_bpc = 12;
4108                         } else {
4109                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4110                                 display_bpc = 8;
4111                         }
4112                 }
4113         }
4114
4115         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4116                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4117                 display_bpc = 6;
4118         }
4119
4120         /*
4121          * We could just drive the pipe at the highest bpc all the time and
4122          * enable dithering as needed, but that costs bandwidth.  So choose
4123          * the minimum value that expresses the full color range of the fb but
4124          * also stays within the max display bpc discovered above.
4125          */
4126
4127         switch (fb->depth) {
4128         case 8:
4129                 bpc = 8; /* since we go through a colormap */
4130                 break;
4131         case 15:
4132         case 16:
4133                 bpc = 6; /* min is 18bpp */
4134                 break;
4135         case 24:
4136                 bpc = 8;
4137                 break;
4138         case 30:
4139                 bpc = 10;
4140                 break;
4141         case 48:
4142                 bpc = 12;
4143                 break;
4144         default:
4145                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4146                 bpc = min((unsigned int)8, display_bpc);
4147                 break;
4148         }
4149
4150         display_bpc = min(display_bpc, bpc);
4151
4152         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4153                       bpc, display_bpc);
4154
4155         *pipe_bpp = display_bpc * 3;
4156
4157         return display_bpc != bpc;
4158 }
4159
4160 static int vlv_get_refclk(struct drm_crtc *crtc)
4161 {
4162         struct drm_device *dev = crtc->dev;
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         int refclk = 27000; /* for DP & HDMI */
4165
4166         return 100000; /* only one validated so far */
4167
4168         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4169                 refclk = 96000;
4170         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4171                 if (intel_panel_use_ssc(dev_priv))
4172                         refclk = 100000;
4173                 else
4174                         refclk = 96000;
4175         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4176                 refclk = 100000;
4177         }
4178
4179         return refclk;
4180 }
4181
4182 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4183 {
4184         struct drm_device *dev = crtc->dev;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         int refclk;
4187
4188         if (IS_VALLEYVIEW(dev)) {
4189                 refclk = vlv_get_refclk(crtc);
4190         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4191             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4192                 refclk = dev_priv->lvds_ssc_freq * 1000;
4193                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4194                               refclk / 1000);
4195         } else if (!IS_GEN2(dev)) {
4196                 refclk = 96000;
4197         } else {
4198                 refclk = 48000;
4199         }
4200
4201         return refclk;
4202 }
4203
4204 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4205                                       intel_clock_t *clock)
4206 {
4207         /* SDVO TV has fixed PLL values depend on its clock range,
4208            this mirrors vbios setting. */
4209         if (adjusted_mode->clock >= 100000
4210             && adjusted_mode->clock < 140500) {
4211                 clock->p1 = 2;
4212                 clock->p2 = 10;
4213                 clock->n = 3;
4214                 clock->m1 = 16;
4215                 clock->m2 = 8;
4216         } else if (adjusted_mode->clock >= 140500
4217                    && adjusted_mode->clock <= 200000) {
4218                 clock->p1 = 1;
4219                 clock->p2 = 10;
4220                 clock->n = 6;
4221                 clock->m1 = 12;
4222                 clock->m2 = 8;
4223         }
4224 }
4225
4226 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4227                                      intel_clock_t *clock,
4228                                      intel_clock_t *reduced_clock)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         u32 fp, fp2 = 0;
4235
4236         if (IS_PINEVIEW(dev)) {
4237                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4238                 if (reduced_clock)
4239                         fp2 = (1 << reduced_clock->n) << 16 |
4240                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4241         } else {
4242                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4243                 if (reduced_clock)
4244                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4245                                 reduced_clock->m2;
4246         }
4247
4248         I915_WRITE(FP0(pipe), fp);
4249
4250         intel_crtc->lowfreq_avail = false;
4251         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4252             reduced_clock && i915_powersave) {
4253                 I915_WRITE(FP1(pipe), fp2);
4254                 intel_crtc->lowfreq_avail = true;
4255         } else {
4256                 I915_WRITE(FP1(pipe), fp);
4257         }
4258 }
4259
4260 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4261                               struct drm_display_mode *adjusted_mode)
4262 {
4263         struct drm_device *dev = crtc->dev;
4264         struct drm_i915_private *dev_priv = dev->dev_private;
4265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266         int pipe = intel_crtc->pipe;
4267         u32 temp;
4268
4269         temp = I915_READ(LVDS);
4270         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4271         if (pipe == 1) {
4272                 temp |= LVDS_PIPEB_SELECT;
4273         } else {
4274                 temp &= ~LVDS_PIPEB_SELECT;
4275         }
4276         /* set the corresponsding LVDS_BORDER bit */
4277         temp |= dev_priv->lvds_border_bits;
4278         /* Set the B0-B3 data pairs corresponding to whether we're going to
4279          * set the DPLLs for dual-channel mode or not.
4280          */
4281         if (clock->p2 == 7)
4282                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4283         else
4284                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4285
4286         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4287          * appropriately here, but we need to look more thoroughly into how
4288          * panels behave in the two modes.
4289          */
4290         /* set the dithering flag on LVDS as needed */
4291         if (INTEL_INFO(dev)->gen >= 4) {
4292                 if (dev_priv->lvds_dither)
4293                         temp |= LVDS_ENABLE_DITHER;
4294                 else
4295                         temp &= ~LVDS_ENABLE_DITHER;
4296         }
4297         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4298         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4299                 temp |= LVDS_HSYNC_POLARITY;
4300         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4301                 temp |= LVDS_VSYNC_POLARITY;
4302         I915_WRITE(LVDS, temp);
4303 }
4304
4305 static void vlv_update_pll(struct drm_crtc *crtc,
4306                            struct drm_display_mode *mode,
4307                            struct drm_display_mode *adjusted_mode,
4308                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4309                            int num_connectors)
4310 {
4311         struct drm_device *dev = crtc->dev;
4312         struct drm_i915_private *dev_priv = dev->dev_private;
4313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314         int pipe = intel_crtc->pipe;
4315         u32 dpll, mdiv, pdiv;
4316         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4317         bool is_sdvo;
4318         u32 temp;
4319
4320         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4321                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4322
4323         dpll = DPLL_VGA_MODE_DIS;
4324         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4325         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4326         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4327
4328         I915_WRITE(DPLL(pipe), dpll);
4329         POSTING_READ(DPLL(pipe));
4330
4331         bestn = clock->n;
4332         bestm1 = clock->m1;
4333         bestm2 = clock->m2;
4334         bestp1 = clock->p1;
4335         bestp2 = clock->p2;
4336
4337         /*
4338          * In Valleyview PLL and program lane counter registers are exposed
4339          * through DPIO interface
4340          */
4341         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4342         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4343         mdiv |= ((bestn << DPIO_N_SHIFT));
4344         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4345         mdiv |= (1 << DPIO_K_SHIFT);
4346         mdiv |= DPIO_ENABLE_CALIBRATION;
4347         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4348
4349         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4350
4351         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4352                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4353                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4354                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4355         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4356
4357         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4358
4359         dpll |= DPLL_VCO_ENABLE;
4360         I915_WRITE(DPLL(pipe), dpll);
4361         POSTING_READ(DPLL(pipe));
4362         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4363                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4364
4365         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4366
4367         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4368                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4369
4370         I915_WRITE(DPLL(pipe), dpll);
4371
4372         /* Wait for the clocks to stabilize. */
4373         POSTING_READ(DPLL(pipe));
4374         udelay(150);
4375
4376         temp = 0;
4377         if (is_sdvo) {
4378                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4379                 if (temp > 1)
4380                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4381                 else
4382                         temp = 0;
4383         }
4384         I915_WRITE(DPLL_MD(pipe), temp);
4385         POSTING_READ(DPLL_MD(pipe));
4386
4387         /* Now program lane control registers */
4388         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4389                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4390         {
4391                 temp = 0x1000C4;
4392                 if(pipe == 1)
4393                         temp |= (1 << 21);
4394                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4395         }
4396         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4397         {
4398                 temp = 0x1000C4;
4399                 if(pipe == 1)
4400                         temp |= (1 << 21);
4401                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4402         }
4403 }
4404
4405 static void i9xx_update_pll(struct drm_crtc *crtc,
4406                             struct drm_display_mode *mode,
4407                             struct drm_display_mode *adjusted_mode,
4408                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4409                             int num_connectors)
4410 {
4411         struct drm_device *dev = crtc->dev;
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4414         struct intel_encoder *encoder;
4415         int pipe = intel_crtc->pipe;
4416         u32 dpll;
4417         bool is_sdvo;
4418
4419         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4420
4421         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4422                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4423
4424         dpll = DPLL_VGA_MODE_DIS;
4425
4426         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4427                 dpll |= DPLLB_MODE_LVDS;
4428         else
4429                 dpll |= DPLLB_MODE_DAC_SERIAL;
4430         if (is_sdvo) {
4431                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4432                 if (pixel_multiplier > 1) {
4433                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4434                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4435                 }
4436                 dpll |= DPLL_DVO_HIGH_SPEED;
4437         }
4438         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4439                 dpll |= DPLL_DVO_HIGH_SPEED;
4440
4441         /* compute bitmask from p1 value */
4442         if (IS_PINEVIEW(dev))
4443                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4444         else {
4445                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4446                 if (IS_G4X(dev) && reduced_clock)
4447                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4448         }
4449         switch (clock->p2) {
4450         case 5:
4451                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4452                 break;
4453         case 7:
4454                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4455                 break;
4456         case 10:
4457                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4458                 break;
4459         case 14:
4460                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4461                 break;
4462         }
4463         if (INTEL_INFO(dev)->gen >= 4)
4464                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4465
4466         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4467                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4468         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4469                 /* XXX: just matching BIOS for now */
4470                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4471                 dpll |= 3;
4472         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4473                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4474                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4475         else
4476                 dpll |= PLL_REF_INPUT_DREFCLK;
4477
4478         dpll |= DPLL_VCO_ENABLE;
4479         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4480         POSTING_READ(DPLL(pipe));
4481         udelay(150);
4482
4483         for_each_encoder_on_crtc(dev, crtc, encoder)
4484                 if (encoder->pre_pll_enable)
4485                         encoder->pre_pll_enable(encoder);
4486
4487         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4488          * This is an exception to the general rule that mode_set doesn't turn
4489          * things on.
4490          */
4491         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4492                 intel_update_lvds(crtc, clock, adjusted_mode);
4493
4494         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4495                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4496
4497         I915_WRITE(DPLL(pipe), dpll);
4498
4499         /* Wait for the clocks to stabilize. */
4500         POSTING_READ(DPLL(pipe));
4501         udelay(150);
4502
4503         if (INTEL_INFO(dev)->gen >= 4) {
4504                 u32 temp = 0;
4505                 if (is_sdvo) {
4506                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4507                         if (temp > 1)
4508                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4509                         else
4510                                 temp = 0;
4511                 }
4512                 I915_WRITE(DPLL_MD(pipe), temp);
4513         } else {
4514                 /* The pixel multiplier can only be updated once the
4515                  * DPLL is enabled and the clocks are stable.
4516                  *
4517                  * So write it again.
4518                  */
4519                 I915_WRITE(DPLL(pipe), dpll);
4520         }
4521 }
4522
4523 static void i8xx_update_pll(struct drm_crtc *crtc,
4524                             struct drm_display_mode *adjusted_mode,
4525                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4526                             int num_connectors)
4527 {
4528         struct drm_device *dev = crtc->dev;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531         struct intel_encoder *encoder;
4532         int pipe = intel_crtc->pipe;
4533         u32 dpll;
4534
4535         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4536
4537         dpll = DPLL_VGA_MODE_DIS;
4538
4539         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4540                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4541         } else {
4542                 if (clock->p1 == 2)
4543                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4544                 else
4545                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4546                 if (clock->p2 == 4)
4547                         dpll |= PLL_P2_DIVIDE_BY_4;
4548         }
4549
4550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4551                 /* XXX: just matching BIOS for now */
4552                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4553                 dpll |= 3;
4554         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4555                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4556                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4557         else
4558                 dpll |= PLL_REF_INPUT_DREFCLK;
4559
4560         dpll |= DPLL_VCO_ENABLE;
4561         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4562         POSTING_READ(DPLL(pipe));
4563         udelay(150);
4564
4565         for_each_encoder_on_crtc(dev, crtc, encoder)
4566                 if (encoder->pre_pll_enable)
4567                         encoder->pre_pll_enable(encoder);
4568
4569         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4570          * This is an exception to the general rule that mode_set doesn't turn
4571          * things on.
4572          */
4573         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4574                 intel_update_lvds(crtc, clock, adjusted_mode);
4575
4576         I915_WRITE(DPLL(pipe), dpll);
4577
4578         /* Wait for the clocks to stabilize. */
4579         POSTING_READ(DPLL(pipe));
4580         udelay(150);
4581
4582         /* The pixel multiplier can only be updated once the
4583          * DPLL is enabled and the clocks are stable.
4584          *
4585          * So write it again.
4586          */
4587         I915_WRITE(DPLL(pipe), dpll);
4588 }
4589
4590 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4591                                    struct drm_display_mode *mode,
4592                                    struct drm_display_mode *adjusted_mode)
4593 {
4594         struct drm_device *dev = intel_crtc->base.dev;
4595         struct drm_i915_private *dev_priv = dev->dev_private;
4596         enum pipe pipe = intel_crtc->pipe;
4597         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4598         uint32_t vsyncshift;
4599
4600         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4601                 /* the chip adds 2 halflines automatically */
4602                 adjusted_mode->crtc_vtotal -= 1;
4603                 adjusted_mode->crtc_vblank_end -= 1;
4604                 vsyncshift = adjusted_mode->crtc_hsync_start
4605                              - adjusted_mode->crtc_htotal / 2;
4606         } else {
4607                 vsyncshift = 0;
4608         }
4609
4610         if (INTEL_INFO(dev)->gen > 3)
4611                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4612
4613         I915_WRITE(HTOTAL(cpu_transcoder),
4614                    (adjusted_mode->crtc_hdisplay - 1) |
4615                    ((adjusted_mode->crtc_htotal - 1) << 16));
4616         I915_WRITE(HBLANK(cpu_transcoder),
4617                    (adjusted_mode->crtc_hblank_start - 1) |
4618                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4619         I915_WRITE(HSYNC(cpu_transcoder),
4620                    (adjusted_mode->crtc_hsync_start - 1) |
4621                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4622
4623         I915_WRITE(VTOTAL(cpu_transcoder),
4624                    (adjusted_mode->crtc_vdisplay - 1) |
4625                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4626         I915_WRITE(VBLANK(cpu_transcoder),
4627                    (adjusted_mode->crtc_vblank_start - 1) |
4628                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4629         I915_WRITE(VSYNC(cpu_transcoder),
4630                    (adjusted_mode->crtc_vsync_start - 1) |
4631                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4632
4633         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4634          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4635          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4636          * bits. */
4637         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4638             (pipe == PIPE_B || pipe == PIPE_C))
4639                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4640
4641         /* pipesrc controls the size that is scaled from, which should
4642          * always be the user's requested size.
4643          */
4644         I915_WRITE(PIPESRC(pipe),
4645                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4646 }
4647
4648 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4649                               struct drm_display_mode *mode,
4650                               struct drm_display_mode *adjusted_mode,
4651                               int x, int y,
4652                               struct drm_framebuffer *fb)
4653 {
4654         struct drm_device *dev = crtc->dev;
4655         struct drm_i915_private *dev_priv = dev->dev_private;
4656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657         int pipe = intel_crtc->pipe;
4658         int plane = intel_crtc->plane;
4659         int refclk, num_connectors = 0;
4660         intel_clock_t clock, reduced_clock;
4661         u32 dspcntr, pipeconf;
4662         bool ok, has_reduced_clock = false, is_sdvo = false;
4663         bool is_lvds = false, is_tv = false, is_dp = false;
4664         struct intel_encoder *encoder;
4665         const intel_limit_t *limit;
4666         int ret;
4667
4668         for_each_encoder_on_crtc(dev, crtc, encoder) {
4669                 switch (encoder->type) {
4670                 case INTEL_OUTPUT_LVDS:
4671                         is_lvds = true;
4672                         break;
4673                 case INTEL_OUTPUT_SDVO:
4674                 case INTEL_OUTPUT_HDMI:
4675                         is_sdvo = true;
4676                         if (encoder->needs_tv_clock)
4677                                 is_tv = true;
4678                         break;
4679                 case INTEL_OUTPUT_TVOUT:
4680                         is_tv = true;
4681                         break;
4682                 case INTEL_OUTPUT_DISPLAYPORT:
4683                         is_dp = true;
4684                         break;
4685                 }
4686
4687                 num_connectors++;
4688         }
4689
4690         refclk = i9xx_get_refclk(crtc, num_connectors);
4691
4692         /*
4693          * Returns a set of divisors for the desired target clock with the given
4694          * refclk, or FALSE.  The returned values represent the clock equation:
4695          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4696          */
4697         limit = intel_limit(crtc, refclk);
4698         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4699                              &clock);
4700         if (!ok) {
4701                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4702                 return -EINVAL;
4703         }
4704
4705         /* Ensure that the cursor is valid for the new mode before changing... */
4706         intel_crtc_update_cursor(crtc, true);
4707
4708         if (is_lvds && dev_priv->lvds_downclock_avail) {
4709                 /*
4710                  * Ensure we match the reduced clock's P to the target clock.
4711                  * If the clocks don't match, we can't switch the display clock
4712                  * by using the FP0/FP1. In such case we will disable the LVDS
4713                  * downclock feature.
4714                 */
4715                 has_reduced_clock = limit->find_pll(limit, crtc,
4716                                                     dev_priv->lvds_downclock,
4717                                                     refclk,
4718                                                     &clock,
4719                                                     &reduced_clock);
4720         }
4721
4722         if (is_sdvo && is_tv)
4723                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4724
4725         if (IS_GEN2(dev))
4726                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4727                                 has_reduced_clock ? &reduced_clock : NULL,
4728                                 num_connectors);
4729         else if (IS_VALLEYVIEW(dev))
4730                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4731                                 has_reduced_clock ? &reduced_clock : NULL,
4732                                 num_connectors);
4733         else
4734                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4735                                 has_reduced_clock ? &reduced_clock : NULL,
4736                                 num_connectors);
4737
4738         /* setup pipeconf */
4739         pipeconf = I915_READ(PIPECONF(pipe));
4740
4741         /* Set up the display plane register */
4742         dspcntr = DISPPLANE_GAMMA_ENABLE;
4743
4744         if (pipe == 0)
4745                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4746         else
4747                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4748
4749         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4750                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4751                  * core speed.
4752                  *
4753                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4754                  * pipe == 0 check?
4755                  */
4756                 if (mode->clock >
4757                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4758                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4759                 else
4760                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4761         }
4762
4763         /* default to 8bpc */
4764         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4765         if (is_dp) {
4766                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4767                         pipeconf |= PIPECONF_BPP_6 |
4768                                     PIPECONF_DITHER_EN |
4769                                     PIPECONF_DITHER_TYPE_SP;
4770                 }
4771         }
4772
4773         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4774                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4775                         pipeconf |= PIPECONF_BPP_6 |
4776                                         PIPECONF_ENABLE |
4777                                         I965_PIPECONF_ACTIVE;
4778                 }
4779         }
4780
4781         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4782         drm_mode_debug_printmodeline(mode);
4783
4784         if (HAS_PIPE_CXSR(dev)) {
4785                 if (intel_crtc->lowfreq_avail) {
4786                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4787                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4788                 } else {
4789                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4790                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4791                 }
4792         }
4793
4794         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4795         if (!IS_GEN2(dev) &&
4796             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4797                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4798         else
4799                 pipeconf |= PIPECONF_PROGRESSIVE;
4800
4801         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4802
4803         /* pipesrc and dspsize control the size that is scaled from,
4804          * which should always be the user's requested size.
4805          */
4806         I915_WRITE(DSPSIZE(plane),
4807                    ((mode->vdisplay - 1) << 16) |
4808                    (mode->hdisplay - 1));
4809         I915_WRITE(DSPPOS(plane), 0);
4810
4811         I915_WRITE(PIPECONF(pipe), pipeconf);
4812         POSTING_READ(PIPECONF(pipe));
4813         intel_enable_pipe(dev_priv, pipe, false);
4814
4815         intel_wait_for_vblank(dev, pipe);
4816
4817         I915_WRITE(DSPCNTR(plane), dspcntr);
4818         POSTING_READ(DSPCNTR(plane));
4819
4820         ret = intel_pipe_set_base(crtc, x, y, fb);
4821
4822         intel_update_watermarks(dev);
4823
4824         return ret;
4825 }
4826
4827 /*
4828  * Initialize reference clocks when the driver loads
4829  */
4830 void ironlake_init_pch_refclk(struct drm_device *dev)
4831 {
4832         struct drm_i915_private *dev_priv = dev->dev_private;
4833         struct drm_mode_config *mode_config = &dev->mode_config;
4834         struct intel_encoder *encoder;
4835         u32 temp;
4836         bool has_lvds = false;
4837         bool has_cpu_edp = false;
4838         bool has_pch_edp = false;
4839         bool has_panel = false;
4840         bool has_ck505 = false;
4841         bool can_ssc = false;
4842
4843         /* We need to take the global config into account */
4844         list_for_each_entry(encoder, &mode_config->encoder_list,
4845                             base.head) {
4846                 switch (encoder->type) {
4847                 case INTEL_OUTPUT_LVDS:
4848                         has_panel = true;
4849                         has_lvds = true;
4850                         break;
4851                 case INTEL_OUTPUT_EDP:
4852                         has_panel = true;
4853                         if (intel_encoder_is_pch_edp(&encoder->base))
4854                                 has_pch_edp = true;
4855                         else
4856                                 has_cpu_edp = true;
4857                         break;
4858                 }
4859         }
4860
4861         if (HAS_PCH_IBX(dev)) {
4862                 has_ck505 = dev_priv->display_clock_mode;
4863                 can_ssc = has_ck505;
4864         } else {
4865                 has_ck505 = false;
4866                 can_ssc = true;
4867         }
4868
4869         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4870                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4871                       has_ck505);
4872
4873         /* Ironlake: try to setup display ref clock before DPLL
4874          * enabling. This is only under driver's control after
4875          * PCH B stepping, previous chipset stepping should be
4876          * ignoring this setting.
4877          */
4878         temp = I915_READ(PCH_DREF_CONTROL);
4879         /* Always enable nonspread source */
4880         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4881
4882         if (has_ck505)
4883                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4884         else
4885                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4886
4887         if (has_panel) {
4888                 temp &= ~DREF_SSC_SOURCE_MASK;
4889                 temp |= DREF_SSC_SOURCE_ENABLE;
4890
4891                 /* SSC must be turned on before enabling the CPU output  */
4892                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4893                         DRM_DEBUG_KMS("Using SSC on panel\n");
4894                         temp |= DREF_SSC1_ENABLE;
4895                 } else
4896                         temp &= ~DREF_SSC1_ENABLE;
4897
4898                 /* Get SSC going before enabling the outputs */
4899                 I915_WRITE(PCH_DREF_CONTROL, temp);
4900                 POSTING_READ(PCH_DREF_CONTROL);
4901                 udelay(200);
4902
4903                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4904
4905                 /* Enable CPU source on CPU attached eDP */
4906                 if (has_cpu_edp) {
4907                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4908                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4909                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4910                         }
4911                         else
4912                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4913                 } else
4914                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4915
4916                 I915_WRITE(PCH_DREF_CONTROL, temp);
4917                 POSTING_READ(PCH_DREF_CONTROL);
4918                 udelay(200);
4919         } else {
4920                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4921
4922                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4923
4924                 /* Turn off CPU output */
4925                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4926
4927                 I915_WRITE(PCH_DREF_CONTROL, temp);
4928                 POSTING_READ(PCH_DREF_CONTROL);
4929                 udelay(200);
4930
4931                 /* Turn off the SSC source */
4932                 temp &= ~DREF_SSC_SOURCE_MASK;
4933                 temp |= DREF_SSC_SOURCE_DISABLE;
4934
4935                 /* Turn off SSC1 */
4936                 temp &= ~ DREF_SSC1_ENABLE;
4937
4938                 I915_WRITE(PCH_DREF_CONTROL, temp);
4939                 POSTING_READ(PCH_DREF_CONTROL);
4940                 udelay(200);
4941         }
4942 }
4943
4944 static int ironlake_get_refclk(struct drm_crtc *crtc)
4945 {
4946         struct drm_device *dev = crtc->dev;
4947         struct drm_i915_private *dev_priv = dev->dev_private;
4948         struct intel_encoder *encoder;
4949         struct intel_encoder *edp_encoder = NULL;
4950         int num_connectors = 0;
4951         bool is_lvds = false;
4952
4953         for_each_encoder_on_crtc(dev, crtc, encoder) {
4954                 switch (encoder->type) {
4955                 case INTEL_OUTPUT_LVDS:
4956                         is_lvds = true;
4957                         break;
4958                 case INTEL_OUTPUT_EDP:
4959                         edp_encoder = encoder;
4960                         break;
4961                 }
4962                 num_connectors++;
4963         }
4964
4965         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4966                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4967                               dev_priv->lvds_ssc_freq);
4968                 return dev_priv->lvds_ssc_freq * 1000;
4969         }
4970
4971         return 120000;
4972 }
4973
4974 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4975                                   struct drm_display_mode *adjusted_mode,
4976                                   bool dither)
4977 {
4978         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980         int pipe = intel_crtc->pipe;
4981         uint32_t val;
4982
4983         val = I915_READ(PIPECONF(pipe));
4984
4985         val &= ~PIPE_BPC_MASK;
4986         switch (intel_crtc->bpp) {
4987         case 18:
4988                 val |= PIPE_6BPC;
4989                 break;
4990         case 24:
4991                 val |= PIPE_8BPC;
4992                 break;
4993         case 30:
4994                 val |= PIPE_10BPC;
4995                 break;
4996         case 36:
4997                 val |= PIPE_12BPC;
4998                 break;
4999         default:
5000                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5001                 BUG();
5002         }
5003
5004         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5005         if (dither)
5006                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5007
5008         val &= ~PIPECONF_INTERLACE_MASK;
5009         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5010                 val |= PIPECONF_INTERLACED_ILK;
5011         else
5012                 val |= PIPECONF_PROGRESSIVE;
5013
5014         I915_WRITE(PIPECONF(pipe), val);
5015         POSTING_READ(PIPECONF(pipe));
5016 }
5017
5018 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5019                                  struct drm_display_mode *adjusted_mode,
5020                                  bool dither)
5021 {
5022         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5025         uint32_t val;
5026
5027         val = I915_READ(PIPECONF(cpu_transcoder));
5028
5029         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5030         if (dither)
5031                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5032
5033         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5034         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5035                 val |= PIPECONF_INTERLACED_ILK;
5036         else
5037                 val |= PIPECONF_PROGRESSIVE;
5038
5039         I915_WRITE(PIPECONF(cpu_transcoder), val);
5040         POSTING_READ(PIPECONF(cpu_transcoder));
5041 }
5042
5043 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5044                                     struct drm_display_mode *adjusted_mode,
5045                                     intel_clock_t *clock,
5046                                     bool *has_reduced_clock,
5047                                     intel_clock_t *reduced_clock)
5048 {
5049         struct drm_device *dev = crtc->dev;
5050         struct drm_i915_private *dev_priv = dev->dev_private;
5051         struct intel_encoder *intel_encoder;
5052         int refclk;
5053         const intel_limit_t *limit;
5054         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5055
5056         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5057                 switch (intel_encoder->type) {
5058                 case INTEL_OUTPUT_LVDS:
5059                         is_lvds = true;
5060                         break;
5061                 case INTEL_OUTPUT_SDVO:
5062                 case INTEL_OUTPUT_HDMI:
5063                         is_sdvo = true;
5064                         if (intel_encoder->needs_tv_clock)
5065                                 is_tv = true;
5066                         break;
5067                 case INTEL_OUTPUT_TVOUT:
5068                         is_tv = true;
5069                         break;
5070                 }
5071         }
5072
5073         refclk = ironlake_get_refclk(crtc);
5074
5075         /*
5076          * Returns a set of divisors for the desired target clock with the given
5077          * refclk, or FALSE.  The returned values represent the clock equation:
5078          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5079          */
5080         limit = intel_limit(crtc, refclk);
5081         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5082                               clock);
5083         if (!ret)
5084                 return false;
5085
5086         if (is_lvds && dev_priv->lvds_downclock_avail) {
5087                 /*
5088                  * Ensure we match the reduced clock's P to the target clock.
5089                  * If the clocks don't match, we can't switch the display clock
5090                  * by using the FP0/FP1. In such case we will disable the LVDS
5091                  * downclock feature.
5092                 */
5093                 *has_reduced_clock = limit->find_pll(limit, crtc,
5094                                                      dev_priv->lvds_downclock,
5095                                                      refclk,
5096                                                      clock,
5097                                                      reduced_clock);
5098         }
5099
5100         if (is_sdvo && is_tv)
5101                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5102
5103         return true;
5104 }
5105
5106 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5107 {
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109         uint32_t temp;
5110
5111         temp = I915_READ(SOUTH_CHICKEN1);
5112         if (temp & FDI_BC_BIFURCATION_SELECT)
5113                 return;
5114
5115         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5116         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5117
5118         temp |= FDI_BC_BIFURCATION_SELECT;
5119         DRM_DEBUG_KMS("enabling fdi C rx\n");
5120         I915_WRITE(SOUTH_CHICKEN1, temp);
5121         POSTING_READ(SOUTH_CHICKEN1);
5122 }
5123
5124 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5125 {
5126         struct drm_device *dev = intel_crtc->base.dev;
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         struct intel_crtc *pipe_B_crtc =
5129                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5130
5131         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5132                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5133         if (intel_crtc->fdi_lanes > 4) {
5134                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5135                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5136                 /* Clamp lanes to avoid programming the hw with bogus values. */
5137                 intel_crtc->fdi_lanes = 4;
5138
5139                 return false;
5140         }
5141
5142         if (dev_priv->num_pipe == 2)
5143                 return true;
5144
5145         switch (intel_crtc->pipe) {
5146         case PIPE_A:
5147                 return true;
5148         case PIPE_B:
5149                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5150                     intel_crtc->fdi_lanes > 2) {
5151                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5152                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5153                         /* Clamp lanes to avoid programming the hw with bogus values. */
5154                         intel_crtc->fdi_lanes = 2;
5155
5156                         return false;
5157                 }
5158
5159                 if (intel_crtc->fdi_lanes > 2)
5160                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5161                 else
5162                         cpt_enable_fdi_bc_bifurcation(dev);
5163
5164                 return true;
5165         case PIPE_C:
5166                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5167                         if (intel_crtc->fdi_lanes > 2) {
5168                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5169                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5170                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5171                                 intel_crtc->fdi_lanes = 2;
5172
5173                                 return false;
5174                         }
5175                 } else {
5176                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5177                         return false;
5178                 }
5179
5180                 cpt_enable_fdi_bc_bifurcation(dev);
5181
5182                 return true;
5183         default:
5184                 BUG();
5185         }
5186 }
5187
5188 static void ironlake_set_m_n(struct drm_crtc *crtc,
5189                              struct drm_display_mode *mode,
5190                              struct drm_display_mode *adjusted_mode)
5191 {
5192         struct drm_device *dev = crtc->dev;
5193         struct drm_i915_private *dev_priv = dev->dev_private;
5194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5196         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5197         struct fdi_m_n m_n = {0};
5198         int target_clock, pixel_multiplier, lane, link_bw;
5199         bool is_dp = false, is_cpu_edp = false;
5200
5201         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5202                 switch (intel_encoder->type) {
5203                 case INTEL_OUTPUT_DISPLAYPORT:
5204                         is_dp = true;
5205                         break;
5206                 case INTEL_OUTPUT_EDP:
5207                         is_dp = true;
5208                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5209                                 is_cpu_edp = true;
5210                         edp_encoder = intel_encoder;
5211                         break;
5212                 }
5213         }
5214
5215         /* FDI link */
5216         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5217         lane = 0;
5218         /* CPU eDP doesn't require FDI link, so just set DP M/N
5219            according to current link config */
5220         if (is_cpu_edp) {
5221                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5222         } else {
5223                 /* FDI is a binary signal running at ~2.7GHz, encoding
5224                  * each output octet as 10 bits. The actual frequency
5225                  * is stored as a divider into a 100MHz clock, and the
5226                  * mode pixel clock is stored in units of 1KHz.
5227                  * Hence the bw of each lane in terms of the mode signal
5228                  * is:
5229                  */
5230                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5231         }
5232
5233         /* [e]DP over FDI requires target mode clock instead of link clock. */
5234         if (edp_encoder)
5235                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5236         else if (is_dp)
5237                 target_clock = mode->clock;
5238         else
5239                 target_clock = adjusted_mode->clock;
5240
5241         if (!lane) {
5242                 /*
5243                  * Account for spread spectrum to avoid
5244                  * oversubscribing the link. Max center spread
5245                  * is 2.5%; use 5% for safety's sake.
5246                  */
5247                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5248                 lane = bps / (link_bw * 8) + 1;
5249         }
5250
5251         intel_crtc->fdi_lanes = lane;
5252
5253         if (pixel_multiplier > 1)
5254                 link_bw *= pixel_multiplier;
5255         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5256                              &m_n);
5257
5258         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5259         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5260         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5261         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5262 }
5263
5264 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5265                                       struct drm_display_mode *adjusted_mode,
5266                                       intel_clock_t *clock, u32 fp)
5267 {
5268         struct drm_crtc *crtc = &intel_crtc->base;
5269         struct drm_device *dev = crtc->dev;
5270         struct drm_i915_private *dev_priv = dev->dev_private;
5271         struct intel_encoder *intel_encoder;
5272         uint32_t dpll;
5273         int factor, pixel_multiplier, num_connectors = 0;
5274         bool is_lvds = false, is_sdvo = false, is_tv = false;
5275         bool is_dp = false, is_cpu_edp = false;
5276
5277         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5278                 switch (intel_encoder->type) {
5279                 case INTEL_OUTPUT_LVDS:
5280                         is_lvds = true;
5281                         break;
5282                 case INTEL_OUTPUT_SDVO:
5283                 case INTEL_OUTPUT_HDMI:
5284                         is_sdvo = true;
5285                         if (intel_encoder->needs_tv_clock)
5286                                 is_tv = true;
5287                         break;
5288                 case INTEL_OUTPUT_TVOUT:
5289                         is_tv = true;
5290                         break;
5291                 case INTEL_OUTPUT_DISPLAYPORT:
5292                         is_dp = true;
5293                         break;
5294                 case INTEL_OUTPUT_EDP:
5295                         is_dp = true;
5296                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5297                                 is_cpu_edp = true;
5298                         break;
5299                 }
5300
5301                 num_connectors++;
5302         }
5303
5304         /* Enable autotuning of the PLL clock (if permissible) */
5305         factor = 21;
5306         if (is_lvds) {
5307                 if ((intel_panel_use_ssc(dev_priv) &&
5308                      dev_priv->lvds_ssc_freq == 100) ||
5309                     intel_is_dual_link_lvds(dev))
5310                         factor = 25;
5311         } else if (is_sdvo && is_tv)
5312                 factor = 20;
5313
5314         if (clock->m < factor * clock->n)
5315                 fp |= FP_CB_TUNE;
5316
5317         dpll = 0;
5318
5319         if (is_lvds)
5320                 dpll |= DPLLB_MODE_LVDS;
5321         else
5322                 dpll |= DPLLB_MODE_DAC_SERIAL;
5323         if (is_sdvo) {
5324                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5325                 if (pixel_multiplier > 1) {
5326                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5327                 }
5328                 dpll |= DPLL_DVO_HIGH_SPEED;
5329         }
5330         if (is_dp && !is_cpu_edp)
5331                 dpll |= DPLL_DVO_HIGH_SPEED;
5332
5333         /* compute bitmask from p1 value */
5334         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5335         /* also FPA1 */
5336         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5337
5338         switch (clock->p2) {
5339         case 5:
5340                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5341                 break;
5342         case 7:
5343                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5344                 break;
5345         case 10:
5346                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5347                 break;
5348         case 14:
5349                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5350                 break;
5351         }
5352
5353         if (is_sdvo && is_tv)
5354                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5355         else if (is_tv)
5356                 /* XXX: just matching BIOS for now */
5357                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5358                 dpll |= 3;
5359         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5360                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5361         else
5362                 dpll |= PLL_REF_INPUT_DREFCLK;
5363
5364         return dpll;
5365 }
5366
5367 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5368                                   struct drm_display_mode *mode,
5369                                   struct drm_display_mode *adjusted_mode,
5370                                   int x, int y,
5371                                   struct drm_framebuffer *fb)
5372 {
5373         struct drm_device *dev = crtc->dev;
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe;
5377         int plane = intel_crtc->plane;
5378         int num_connectors = 0;
5379         intel_clock_t clock, reduced_clock;
5380         u32 dpll, fp = 0, fp2 = 0;
5381         bool ok, has_reduced_clock = false;
5382         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5383         struct intel_encoder *encoder;
5384         u32 temp;
5385         int ret;
5386         bool dither, fdi_config_ok;
5387
5388         for_each_encoder_on_crtc(dev, crtc, encoder) {
5389                 switch (encoder->type) {
5390                 case INTEL_OUTPUT_LVDS:
5391                         is_lvds = true;
5392                         break;
5393                 case INTEL_OUTPUT_DISPLAYPORT:
5394                         is_dp = true;
5395                         break;
5396                 case INTEL_OUTPUT_EDP:
5397                         is_dp = true;
5398                         if (!intel_encoder_is_pch_edp(&encoder->base))
5399                                 is_cpu_edp = true;
5400                         break;
5401                 }
5402
5403                 num_connectors++;
5404         }
5405
5406         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5407              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5408
5409         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5410                                      &has_reduced_clock, &reduced_clock);
5411         if (!ok) {
5412                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5413                 return -EINVAL;
5414         }
5415
5416         /* Ensure that the cursor is valid for the new mode before changing... */
5417         intel_crtc_update_cursor(crtc, true);
5418
5419         /* determine panel color depth */
5420         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5421                                               adjusted_mode);
5422         if (is_lvds && dev_priv->lvds_dither)
5423                 dither = true;
5424
5425         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5426         if (has_reduced_clock)
5427                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5428                         reduced_clock.m2;
5429
5430         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5431
5432         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5433         drm_mode_debug_printmodeline(mode);
5434
5435         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5436         if (!is_cpu_edp) {
5437                 struct intel_pch_pll *pll;
5438
5439                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5440                 if (pll == NULL) {
5441                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5442                                          pipe);
5443                         return -EINVAL;
5444                 }
5445         } else
5446                 intel_put_pch_pll(intel_crtc);
5447
5448         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5449          * This is an exception to the general rule that mode_set doesn't turn
5450          * things on.
5451          */
5452         if (is_lvds) {
5453                 temp = I915_READ(PCH_LVDS);
5454                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5455                 if (HAS_PCH_CPT(dev)) {
5456                         temp &= ~PORT_TRANS_SEL_MASK;
5457                         temp |= PORT_TRANS_SEL_CPT(pipe);
5458                 } else {
5459                         if (pipe == 1)
5460                                 temp |= LVDS_PIPEB_SELECT;
5461                         else
5462                                 temp &= ~LVDS_PIPEB_SELECT;
5463                 }
5464
5465                 /* set the corresponsding LVDS_BORDER bit */
5466                 temp |= dev_priv->lvds_border_bits;
5467                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5468                  * set the DPLLs for dual-channel mode or not.
5469                  */
5470                 if (clock.p2 == 7)
5471                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5472                 else
5473                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5474
5475                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5476                  * appropriately here, but we need to look more thoroughly into how
5477                  * panels behave in the two modes.
5478                  */
5479                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5480                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5481                         temp |= LVDS_HSYNC_POLARITY;
5482                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5483                         temp |= LVDS_VSYNC_POLARITY;
5484                 I915_WRITE(PCH_LVDS, temp);
5485         }
5486
5487         if (is_dp && !is_cpu_edp) {
5488                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5489         } else {
5490                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5491                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5492                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5493                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5494                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5495         }
5496
5497         for_each_encoder_on_crtc(dev, crtc, encoder)
5498                 if (encoder->pre_pll_enable)
5499                         encoder->pre_pll_enable(encoder);
5500
5501         if (intel_crtc->pch_pll) {
5502                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5503
5504                 /* Wait for the clocks to stabilize. */
5505                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5506                 udelay(150);
5507
5508                 /* The pixel multiplier can only be updated once the
5509                  * DPLL is enabled and the clocks are stable.
5510                  *
5511                  * So write it again.
5512                  */
5513                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5514         }
5515
5516         intel_crtc->lowfreq_avail = false;
5517         if (intel_crtc->pch_pll) {
5518                 if (is_lvds && has_reduced_clock && i915_powersave) {
5519                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5520                         intel_crtc->lowfreq_avail = true;
5521                 } else {
5522                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5523                 }
5524         }
5525
5526         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5527
5528         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5529          * ironlake_check_fdi_lanes. */
5530         ironlake_set_m_n(crtc, mode, adjusted_mode);
5531
5532         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5533
5534         if (is_cpu_edp)
5535                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5536
5537         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5538
5539         intel_wait_for_vblank(dev, pipe);
5540
5541         /* Set up the display plane register */
5542         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5543         POSTING_READ(DSPCNTR(plane));
5544
5545         ret = intel_pipe_set_base(crtc, x, y, fb);
5546
5547         intel_update_watermarks(dev);
5548
5549         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5550
5551         return fdi_config_ok ? ret : -EINVAL;
5552 }
5553
5554 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5555                                  struct drm_display_mode *mode,
5556                                  struct drm_display_mode *adjusted_mode,
5557                                  int x, int y,
5558                                  struct drm_framebuffer *fb)
5559 {
5560         struct drm_device *dev = crtc->dev;
5561         struct drm_i915_private *dev_priv = dev->dev_private;
5562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5563         int pipe = intel_crtc->pipe;
5564         int plane = intel_crtc->plane;
5565         int num_connectors = 0;
5566         intel_clock_t clock, reduced_clock;
5567         u32 dpll = 0, fp = 0, fp2 = 0;
5568         bool ok, has_reduced_clock = false;
5569         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5570         struct intel_encoder *encoder;
5571         u32 temp;
5572         int ret;
5573         bool dither;
5574
5575         for_each_encoder_on_crtc(dev, crtc, encoder) {
5576                 switch (encoder->type) {
5577                 case INTEL_OUTPUT_LVDS:
5578                         is_lvds = true;
5579                         break;
5580                 case INTEL_OUTPUT_DISPLAYPORT:
5581                         is_dp = true;
5582                         break;
5583                 case INTEL_OUTPUT_EDP:
5584                         is_dp = true;
5585                         if (!intel_encoder_is_pch_edp(&encoder->base))
5586                                 is_cpu_edp = true;
5587                         break;
5588                 }
5589
5590                 num_connectors++;
5591         }
5592
5593         if (is_cpu_edp)
5594                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5595         else
5596                 intel_crtc->cpu_transcoder = pipe;
5597
5598         /* We are not sure yet this won't happen. */
5599         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5600              INTEL_PCH_TYPE(dev));
5601
5602         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5603              num_connectors, pipe_name(pipe));
5604
5605         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5606                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5607
5608         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5609
5610         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5611                 return -EINVAL;
5612
5613         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5614                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5615                                              &has_reduced_clock,
5616                                              &reduced_clock);
5617                 if (!ok) {
5618                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5619                         return -EINVAL;
5620                 }
5621         }
5622
5623         /* Ensure that the cursor is valid for the new mode before changing... */
5624         intel_crtc_update_cursor(crtc, true);
5625
5626         /* determine panel color depth */
5627         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5628                                               adjusted_mode);
5629         if (is_lvds && dev_priv->lvds_dither)
5630                 dither = true;
5631
5632         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5633         drm_mode_debug_printmodeline(mode);
5634
5635         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5636                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5637                 if (has_reduced_clock)
5638                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5639                               reduced_clock.m2;
5640
5641                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5642                                              fp);
5643
5644                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5645                  * own on pre-Haswell/LPT generation */
5646                 if (!is_cpu_edp) {
5647                         struct intel_pch_pll *pll;
5648
5649                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5650                         if (pll == NULL) {
5651                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5652                                                  pipe);
5653                                 return -EINVAL;
5654                         }
5655                 } else
5656                         intel_put_pch_pll(intel_crtc);
5657
5658                 /* The LVDS pin pair needs to be on before the DPLLs are
5659                  * enabled.  This is an exception to the general rule that
5660                  * mode_set doesn't turn things on.
5661                  */
5662                 if (is_lvds) {
5663                         temp = I915_READ(PCH_LVDS);
5664                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5665                         if (HAS_PCH_CPT(dev)) {
5666                                 temp &= ~PORT_TRANS_SEL_MASK;
5667                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5668                         } else {
5669                                 if (pipe == 1)
5670                                         temp |= LVDS_PIPEB_SELECT;
5671                                 else
5672                                         temp &= ~LVDS_PIPEB_SELECT;
5673                         }
5674
5675                         /* set the corresponsding LVDS_BORDER bit */
5676                         temp |= dev_priv->lvds_border_bits;
5677                         /* Set the B0-B3 data pairs corresponding to whether
5678                          * we're going to set the DPLLs for dual-channel mode or
5679                          * not.
5680                          */
5681                         if (clock.p2 == 7)
5682                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5683                         else
5684                                 temp &= ~(LVDS_B0B3_POWER_UP |
5685                                           LVDS_CLKB_POWER_UP);
5686
5687                         /* It would be nice to set 24 vs 18-bit mode
5688                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5689                          * look more thoroughly into how panels behave in the
5690                          * two modes.
5691                          */
5692                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5693                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5694                                 temp |= LVDS_HSYNC_POLARITY;
5695                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5696                                 temp |= LVDS_VSYNC_POLARITY;
5697                         I915_WRITE(PCH_LVDS, temp);
5698                 }
5699         }
5700
5701         if (is_dp && !is_cpu_edp) {
5702                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5703         } else {
5704                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5705                         /* For non-DP output, clear any trans DP clock recovery
5706                          * setting.*/
5707                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5708                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5709                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5710                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5711                 }
5712         }
5713
5714         intel_crtc->lowfreq_avail = false;
5715         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5716                 if (intel_crtc->pch_pll) {
5717                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5718
5719                         /* Wait for the clocks to stabilize. */
5720                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5721                         udelay(150);
5722
5723                         /* The pixel multiplier can only be updated once the
5724                          * DPLL is enabled and the clocks are stable.
5725                          *
5726                          * So write it again.
5727                          */
5728                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5729                 }
5730
5731                 if (intel_crtc->pch_pll) {
5732                         if (is_lvds && has_reduced_clock && i915_powersave) {
5733                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5734                                 intel_crtc->lowfreq_avail = true;
5735                         } else {
5736                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5737                         }
5738                 }
5739         }
5740
5741         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5742
5743         if (!is_dp || is_cpu_edp)
5744                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5745
5746         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5747                 if (is_cpu_edp)
5748                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5749
5750         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5751
5752         /* Set up the display plane register */
5753         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5754         POSTING_READ(DSPCNTR(plane));
5755
5756         ret = intel_pipe_set_base(crtc, x, y, fb);
5757
5758         intel_update_watermarks(dev);
5759
5760         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5761
5762         return ret;
5763 }
5764
5765 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5766                                struct drm_display_mode *mode,
5767                                struct drm_display_mode *adjusted_mode,
5768                                int x, int y,
5769                                struct drm_framebuffer *fb)
5770 {
5771         struct drm_device *dev = crtc->dev;
5772         struct drm_i915_private *dev_priv = dev->dev_private;
5773         struct drm_encoder_helper_funcs *encoder_funcs;
5774         struct intel_encoder *encoder;
5775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776         int pipe = intel_crtc->pipe;
5777         int ret;
5778
5779         drm_vblank_pre_modeset(dev, pipe);
5780
5781         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5782                                               x, y, fb);
5783         drm_vblank_post_modeset(dev, pipe);
5784
5785         if (ret != 0)
5786                 return ret;
5787
5788         for_each_encoder_on_crtc(dev, crtc, encoder) {
5789                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5790                         encoder->base.base.id,
5791                         drm_get_encoder_name(&encoder->base),
5792                         mode->base.id, mode->name);
5793                 encoder_funcs = encoder->base.helper_private;
5794                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5795         }
5796
5797         return 0;
5798 }
5799
5800 static bool intel_eld_uptodate(struct drm_connector *connector,
5801                                int reg_eldv, uint32_t bits_eldv,
5802                                int reg_elda, uint32_t bits_elda,
5803                                int reg_edid)
5804 {
5805         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5806         uint8_t *eld = connector->eld;
5807         uint32_t i;
5808
5809         i = I915_READ(reg_eldv);
5810         i &= bits_eldv;
5811
5812         if (!eld[0])
5813                 return !i;
5814
5815         if (!i)
5816                 return false;
5817
5818         i = I915_READ(reg_elda);
5819         i &= ~bits_elda;
5820         I915_WRITE(reg_elda, i);
5821
5822         for (i = 0; i < eld[2]; i++)
5823                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5824                         return false;
5825
5826         return true;
5827 }
5828
5829 static void g4x_write_eld(struct drm_connector *connector,
5830                           struct drm_crtc *crtc)
5831 {
5832         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5833         uint8_t *eld = connector->eld;
5834         uint32_t eldv;
5835         uint32_t len;
5836         uint32_t i;
5837
5838         i = I915_READ(G4X_AUD_VID_DID);
5839
5840         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5841                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5842         else
5843                 eldv = G4X_ELDV_DEVCTG;
5844
5845         if (intel_eld_uptodate(connector,
5846                                G4X_AUD_CNTL_ST, eldv,
5847                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5848                                G4X_HDMIW_HDMIEDID))
5849                 return;
5850
5851         i = I915_READ(G4X_AUD_CNTL_ST);
5852         i &= ~(eldv | G4X_ELD_ADDR);
5853         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5854         I915_WRITE(G4X_AUD_CNTL_ST, i);
5855
5856         if (!eld[0])
5857                 return;
5858
5859         len = min_t(uint8_t, eld[2], len);
5860         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5861         for (i = 0; i < len; i++)
5862                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5863
5864         i = I915_READ(G4X_AUD_CNTL_ST);
5865         i |= eldv;
5866         I915_WRITE(G4X_AUD_CNTL_ST, i);
5867 }
5868
5869 static void haswell_write_eld(struct drm_connector *connector,
5870                                      struct drm_crtc *crtc)
5871 {
5872         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5873         uint8_t *eld = connector->eld;
5874         struct drm_device *dev = crtc->dev;
5875         uint32_t eldv;
5876         uint32_t i;
5877         int len;
5878         int pipe = to_intel_crtc(crtc)->pipe;
5879         int tmp;
5880
5881         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5882         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5883         int aud_config = HSW_AUD_CFG(pipe);
5884         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5885
5886
5887         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5888
5889         /* Audio output enable */
5890         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5891         tmp = I915_READ(aud_cntrl_st2);
5892         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5893         I915_WRITE(aud_cntrl_st2, tmp);
5894
5895         /* Wait for 1 vertical blank */
5896         intel_wait_for_vblank(dev, pipe);
5897
5898         /* Set ELD valid state */
5899         tmp = I915_READ(aud_cntrl_st2);
5900         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5901         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5902         I915_WRITE(aud_cntrl_st2, tmp);
5903         tmp = I915_READ(aud_cntrl_st2);
5904         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5905
5906         /* Enable HDMI mode */
5907         tmp = I915_READ(aud_config);
5908         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5909         /* clear N_programing_enable and N_value_index */
5910         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5911         I915_WRITE(aud_config, tmp);
5912
5913         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5914
5915         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5916
5917         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5918                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5919                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5920                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5921         } else
5922                 I915_WRITE(aud_config, 0);
5923
5924         if (intel_eld_uptodate(connector,
5925                                aud_cntrl_st2, eldv,
5926                                aud_cntl_st, IBX_ELD_ADDRESS,
5927                                hdmiw_hdmiedid))
5928                 return;
5929
5930         i = I915_READ(aud_cntrl_st2);
5931         i &= ~eldv;
5932         I915_WRITE(aud_cntrl_st2, i);
5933
5934         if (!eld[0])
5935                 return;
5936
5937         i = I915_READ(aud_cntl_st);
5938         i &= ~IBX_ELD_ADDRESS;
5939         I915_WRITE(aud_cntl_st, i);
5940         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5941         DRM_DEBUG_DRIVER("port num:%d\n", i);
5942
5943         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5944         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5945         for (i = 0; i < len; i++)
5946                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5947
5948         i = I915_READ(aud_cntrl_st2);
5949         i |= eldv;
5950         I915_WRITE(aud_cntrl_st2, i);
5951
5952 }
5953
5954 static void ironlake_write_eld(struct drm_connector *connector,
5955                                      struct drm_crtc *crtc)
5956 {
5957         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5958         uint8_t *eld = connector->eld;
5959         uint32_t eldv;
5960         uint32_t i;
5961         int len;
5962         int hdmiw_hdmiedid;
5963         int aud_config;
5964         int aud_cntl_st;
5965         int aud_cntrl_st2;
5966         int pipe = to_intel_crtc(crtc)->pipe;
5967
5968         if (HAS_PCH_IBX(connector->dev)) {
5969                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5970                 aud_config = IBX_AUD_CFG(pipe);
5971                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5972                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5973         } else {
5974                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5975                 aud_config = CPT_AUD_CFG(pipe);
5976                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5977                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5978         }
5979
5980         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5981
5982         i = I915_READ(aud_cntl_st);
5983         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5984         if (!i) {
5985                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5986                 /* operate blindly on all ports */
5987                 eldv = IBX_ELD_VALIDB;
5988                 eldv |= IBX_ELD_VALIDB << 4;
5989                 eldv |= IBX_ELD_VALIDB << 8;
5990         } else {
5991                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5992                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5993         }
5994
5995         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5996                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5997                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5998                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5999         } else
6000                 I915_WRITE(aud_config, 0);
6001
6002         if (intel_eld_uptodate(connector,
6003                                aud_cntrl_st2, eldv,
6004                                aud_cntl_st, IBX_ELD_ADDRESS,
6005                                hdmiw_hdmiedid))
6006                 return;
6007
6008         i = I915_READ(aud_cntrl_st2);
6009         i &= ~eldv;
6010         I915_WRITE(aud_cntrl_st2, i);
6011
6012         if (!eld[0])
6013                 return;
6014
6015         i = I915_READ(aud_cntl_st);
6016         i &= ~IBX_ELD_ADDRESS;
6017         I915_WRITE(aud_cntl_st, i);
6018
6019         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6020         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6021         for (i = 0; i < len; i++)
6022                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6023
6024         i = I915_READ(aud_cntrl_st2);
6025         i |= eldv;
6026         I915_WRITE(aud_cntrl_st2, i);
6027 }
6028
6029 void intel_write_eld(struct drm_encoder *encoder,
6030                      struct drm_display_mode *mode)
6031 {
6032         struct drm_crtc *crtc = encoder->crtc;
6033         struct drm_connector *connector;
6034         struct drm_device *dev = encoder->dev;
6035         struct drm_i915_private *dev_priv = dev->dev_private;
6036
6037         connector = drm_select_eld(encoder, mode);
6038         if (!connector)
6039                 return;
6040
6041         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6042                          connector->base.id,
6043                          drm_get_connector_name(connector),
6044                          connector->encoder->base.id,
6045                          drm_get_encoder_name(connector->encoder));
6046
6047         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6048
6049         if (dev_priv->display.write_eld)
6050                 dev_priv->display.write_eld(connector, crtc);
6051 }
6052
6053 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6054 void intel_crtc_load_lut(struct drm_crtc *crtc)
6055 {
6056         struct drm_device *dev = crtc->dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059         int palreg = PALETTE(intel_crtc->pipe);
6060         int i;
6061
6062         /* The clocks have to be on to load the palette. */
6063         if (!crtc->enabled || !intel_crtc->active)
6064                 return;
6065
6066         /* use legacy palette for Ironlake */
6067         if (HAS_PCH_SPLIT(dev))
6068                 palreg = LGC_PALETTE(intel_crtc->pipe);
6069
6070         for (i = 0; i < 256; i++) {
6071                 I915_WRITE(palreg + 4 * i,
6072                            (intel_crtc->lut_r[i] << 16) |
6073                            (intel_crtc->lut_g[i] << 8) |
6074                            intel_crtc->lut_b[i]);
6075         }
6076 }
6077
6078 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6079 {
6080         struct drm_device *dev = crtc->dev;
6081         struct drm_i915_private *dev_priv = dev->dev_private;
6082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083         bool visible = base != 0;
6084         u32 cntl;
6085
6086         if (intel_crtc->cursor_visible == visible)
6087                 return;
6088
6089         cntl = I915_READ(_CURACNTR);
6090         if (visible) {
6091                 /* On these chipsets we can only modify the base whilst
6092                  * the cursor is disabled.
6093                  */
6094                 I915_WRITE(_CURABASE, base);
6095
6096                 cntl &= ~(CURSOR_FORMAT_MASK);
6097                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6098                 cntl |= CURSOR_ENABLE |
6099                         CURSOR_GAMMA_ENABLE |
6100                         CURSOR_FORMAT_ARGB;
6101         } else
6102                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6103         I915_WRITE(_CURACNTR, cntl);
6104
6105         intel_crtc->cursor_visible = visible;
6106 }
6107
6108 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6109 {
6110         struct drm_device *dev = crtc->dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6113         int pipe = intel_crtc->pipe;
6114         bool visible = base != 0;
6115
6116         if (intel_crtc->cursor_visible != visible) {
6117                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6118                 if (base) {
6119                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6120                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6121                         cntl |= pipe << 28; /* Connect to correct pipe */
6122                 } else {
6123                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6124                         cntl |= CURSOR_MODE_DISABLE;
6125                 }
6126                 I915_WRITE(CURCNTR(pipe), cntl);
6127
6128                 intel_crtc->cursor_visible = visible;
6129         }
6130         /* and commit changes on next vblank */
6131         I915_WRITE(CURBASE(pipe), base);
6132 }
6133
6134 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6135 {
6136         struct drm_device *dev = crtc->dev;
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139         int pipe = intel_crtc->pipe;
6140         bool visible = base != 0;
6141
6142         if (intel_crtc->cursor_visible != visible) {
6143                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6144                 if (base) {
6145                         cntl &= ~CURSOR_MODE;
6146                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6147                 } else {
6148                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6149                         cntl |= CURSOR_MODE_DISABLE;
6150                 }
6151                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6152
6153                 intel_crtc->cursor_visible = visible;
6154         }
6155         /* and commit changes on next vblank */
6156         I915_WRITE(CURBASE_IVB(pipe), base);
6157 }
6158
6159 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6160 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6161                                      bool on)
6162 {
6163         struct drm_device *dev = crtc->dev;
6164         struct drm_i915_private *dev_priv = dev->dev_private;
6165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6166         int pipe = intel_crtc->pipe;
6167         int x = intel_crtc->cursor_x;
6168         int y = intel_crtc->cursor_y;
6169         u32 base, pos;
6170         bool visible;
6171
6172         pos = 0;
6173
6174         if (on && crtc->enabled && crtc->fb) {
6175                 base = intel_crtc->cursor_addr;
6176                 if (x > (int) crtc->fb->width)
6177                         base = 0;
6178
6179                 if (y > (int) crtc->fb->height)
6180                         base = 0;
6181         } else
6182                 base = 0;
6183
6184         if (x < 0) {
6185                 if (x + intel_crtc->cursor_width < 0)
6186                         base = 0;
6187
6188                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6189                 x = -x;
6190         }
6191         pos |= x << CURSOR_X_SHIFT;
6192
6193         if (y < 0) {
6194                 if (y + intel_crtc->cursor_height < 0)
6195                         base = 0;
6196
6197                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6198                 y = -y;
6199         }
6200         pos |= y << CURSOR_Y_SHIFT;
6201
6202         visible = base != 0;
6203         if (!visible && !intel_crtc->cursor_visible)
6204                 return;
6205
6206         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6207                 I915_WRITE(CURPOS_IVB(pipe), pos);
6208                 ivb_update_cursor(crtc, base);
6209         } else {
6210                 I915_WRITE(CURPOS(pipe), pos);
6211                 if (IS_845G(dev) || IS_I865G(dev))
6212                         i845_update_cursor(crtc, base);
6213                 else
6214                         i9xx_update_cursor(crtc, base);
6215         }
6216 }
6217
6218 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6219                                  struct drm_file *file,
6220                                  uint32_t handle,
6221                                  uint32_t width, uint32_t height)
6222 {
6223         struct drm_device *dev = crtc->dev;
6224         struct drm_i915_private *dev_priv = dev->dev_private;
6225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226         struct drm_i915_gem_object *obj;
6227         uint32_t addr;
6228         int ret;
6229
6230         /* if we want to turn off the cursor ignore width and height */
6231         if (!handle) {
6232                 DRM_DEBUG_KMS("cursor off\n");
6233                 addr = 0;
6234                 obj = NULL;
6235                 mutex_lock(&dev->struct_mutex);
6236                 goto finish;
6237         }
6238
6239         /* Currently we only support 64x64 cursors */
6240         if (width != 64 || height != 64) {
6241                 DRM_ERROR("we currently only support 64x64 cursors\n");
6242                 return -EINVAL;
6243         }
6244
6245         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6246         if (&obj->base == NULL)
6247                 return -ENOENT;
6248
6249         if (obj->base.size < width * height * 4) {
6250                 DRM_ERROR("buffer is to small\n");
6251                 ret = -ENOMEM;
6252                 goto fail;
6253         }
6254
6255         /* we only need to pin inside GTT if cursor is non-phy */
6256         mutex_lock(&dev->struct_mutex);
6257         if (!dev_priv->info->cursor_needs_physical) {
6258                 if (obj->tiling_mode) {
6259                         DRM_ERROR("cursor cannot be tiled\n");
6260                         ret = -EINVAL;
6261                         goto fail_locked;
6262                 }
6263
6264                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6265                 if (ret) {
6266                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6267                         goto fail_locked;
6268                 }
6269
6270                 ret = i915_gem_object_put_fence(obj);
6271                 if (ret) {
6272                         DRM_ERROR("failed to release fence for cursor");
6273                         goto fail_unpin;
6274                 }
6275
6276                 addr = obj->gtt_offset;
6277         } else {
6278                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6279                 ret = i915_gem_attach_phys_object(dev, obj,
6280                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6281                                                   align);
6282                 if (ret) {
6283                         DRM_ERROR("failed to attach phys object\n");
6284                         goto fail_locked;
6285                 }
6286                 addr = obj->phys_obj->handle->busaddr;
6287         }
6288
6289         if (IS_GEN2(dev))
6290                 I915_WRITE(CURSIZE, (height << 12) | width);
6291
6292  finish:
6293         if (intel_crtc->cursor_bo) {
6294                 if (dev_priv->info->cursor_needs_physical) {
6295                         if (intel_crtc->cursor_bo != obj)
6296                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6297                 } else
6298                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6299                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6300         }
6301
6302         mutex_unlock(&dev->struct_mutex);
6303
6304         intel_crtc->cursor_addr = addr;
6305         intel_crtc->cursor_bo = obj;
6306         intel_crtc->cursor_width = width;
6307         intel_crtc->cursor_height = height;
6308
6309         intel_crtc_update_cursor(crtc, true);
6310
6311         return 0;
6312 fail_unpin:
6313         i915_gem_object_unpin(obj);
6314 fail_locked:
6315         mutex_unlock(&dev->struct_mutex);
6316 fail:
6317         drm_gem_object_unreference_unlocked(&obj->base);
6318         return ret;
6319 }
6320
6321 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6322 {
6323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6324
6325         intel_crtc->cursor_x = x;
6326         intel_crtc->cursor_y = y;
6327
6328         intel_crtc_update_cursor(crtc, true);
6329
6330         return 0;
6331 }
6332
6333 /** Sets the color ramps on behalf of RandR */
6334 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6335                                  u16 blue, int regno)
6336 {
6337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6338
6339         intel_crtc->lut_r[regno] = red >> 8;
6340         intel_crtc->lut_g[regno] = green >> 8;
6341         intel_crtc->lut_b[regno] = blue >> 8;
6342 }
6343
6344 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6345                              u16 *blue, int regno)
6346 {
6347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348
6349         *red = intel_crtc->lut_r[regno] << 8;
6350         *green = intel_crtc->lut_g[regno] << 8;
6351         *blue = intel_crtc->lut_b[regno] << 8;
6352 }
6353
6354 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6355                                  u16 *blue, uint32_t start, uint32_t size)
6356 {
6357         int end = (start + size > 256) ? 256 : start + size, i;
6358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6359
6360         for (i = start; i < end; i++) {
6361                 intel_crtc->lut_r[i] = red[i] >> 8;
6362                 intel_crtc->lut_g[i] = green[i] >> 8;
6363                 intel_crtc->lut_b[i] = blue[i] >> 8;
6364         }
6365
6366         intel_crtc_load_lut(crtc);
6367 }
6368
6369 /**
6370  * Get a pipe with a simple mode set on it for doing load-based monitor
6371  * detection.
6372  *
6373  * It will be up to the load-detect code to adjust the pipe as appropriate for
6374  * its requirements.  The pipe will be connected to no other encoders.
6375  *
6376  * Currently this code will only succeed if there is a pipe with no encoders
6377  * configured for it.  In the future, it could choose to temporarily disable
6378  * some outputs to free up a pipe for its use.
6379  *
6380  * \return crtc, or NULL if no pipes are available.
6381  */
6382
6383 /* VESA 640x480x72Hz mode to set on the pipe */
6384 static struct drm_display_mode load_detect_mode = {
6385         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6386                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6387 };
6388
6389 static struct drm_framebuffer *
6390 intel_framebuffer_create(struct drm_device *dev,
6391                          struct drm_mode_fb_cmd2 *mode_cmd,
6392                          struct drm_i915_gem_object *obj)
6393 {
6394         struct intel_framebuffer *intel_fb;
6395         int ret;
6396
6397         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6398         if (!intel_fb) {
6399                 drm_gem_object_unreference_unlocked(&obj->base);
6400                 return ERR_PTR(-ENOMEM);
6401         }
6402
6403         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6404         if (ret) {
6405                 drm_gem_object_unreference_unlocked(&obj->base);
6406                 kfree(intel_fb);
6407                 return ERR_PTR(ret);
6408         }
6409
6410         return &intel_fb->base;
6411 }
6412
6413 static u32
6414 intel_framebuffer_pitch_for_width(int width, int bpp)
6415 {
6416         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6417         return ALIGN(pitch, 64);
6418 }
6419
6420 static u32
6421 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6422 {
6423         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6424         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6425 }
6426
6427 static struct drm_framebuffer *
6428 intel_framebuffer_create_for_mode(struct drm_device *dev,
6429                                   struct drm_display_mode *mode,
6430                                   int depth, int bpp)
6431 {
6432         struct drm_i915_gem_object *obj;
6433         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6434
6435         obj = i915_gem_alloc_object(dev,
6436                                     intel_framebuffer_size_for_mode(mode, bpp));
6437         if (obj == NULL)
6438                 return ERR_PTR(-ENOMEM);
6439
6440         mode_cmd.width = mode->hdisplay;
6441         mode_cmd.height = mode->vdisplay;
6442         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6443                                                                 bpp);
6444         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6445
6446         return intel_framebuffer_create(dev, &mode_cmd, obj);
6447 }
6448
6449 static struct drm_framebuffer *
6450 mode_fits_in_fbdev(struct drm_device *dev,
6451                    struct drm_display_mode *mode)
6452 {
6453         struct drm_i915_private *dev_priv = dev->dev_private;
6454         struct drm_i915_gem_object *obj;
6455         struct drm_framebuffer *fb;
6456
6457         if (dev_priv->fbdev == NULL)
6458                 return NULL;
6459
6460         obj = dev_priv->fbdev->ifb.obj;
6461         if (obj == NULL)
6462                 return NULL;
6463
6464         fb = &dev_priv->fbdev->ifb.base;
6465         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6466                                                                fb->bits_per_pixel))
6467                 return NULL;
6468
6469         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6470                 return NULL;
6471
6472         return fb;
6473 }
6474
6475 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6476                                 struct drm_display_mode *mode,
6477                                 struct intel_load_detect_pipe *old)
6478 {
6479         struct intel_crtc *intel_crtc;
6480         struct intel_encoder *intel_encoder =
6481                 intel_attached_encoder(connector);
6482         struct drm_crtc *possible_crtc;
6483         struct drm_encoder *encoder = &intel_encoder->base;
6484         struct drm_crtc *crtc = NULL;
6485         struct drm_device *dev = encoder->dev;
6486         struct drm_framebuffer *fb;
6487         int i = -1;
6488
6489         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6490                       connector->base.id, drm_get_connector_name(connector),
6491                       encoder->base.id, drm_get_encoder_name(encoder));
6492
6493         /*
6494          * Algorithm gets a little messy:
6495          *
6496          *   - if the connector already has an assigned crtc, use it (but make
6497          *     sure it's on first)
6498          *
6499          *   - try to find the first unused crtc that can drive this connector,
6500          *     and use that if we find one
6501          */
6502
6503         /* See if we already have a CRTC for this connector */
6504         if (encoder->crtc) {
6505                 crtc = encoder->crtc;
6506
6507                 old->dpms_mode = connector->dpms;
6508                 old->load_detect_temp = false;
6509
6510                 /* Make sure the crtc and connector are running */
6511                 if (connector->dpms != DRM_MODE_DPMS_ON)
6512                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6513
6514                 return true;
6515         }
6516
6517         /* Find an unused one (if possible) */
6518         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6519                 i++;
6520                 if (!(encoder->possible_crtcs & (1 << i)))
6521                         continue;
6522                 if (!possible_crtc->enabled) {
6523                         crtc = possible_crtc;
6524                         break;
6525                 }
6526         }
6527
6528         /*
6529          * If we didn't find an unused CRTC, don't use any.
6530          */
6531         if (!crtc) {
6532                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6533                 return false;
6534         }
6535
6536         intel_encoder->new_crtc = to_intel_crtc(crtc);
6537         to_intel_connector(connector)->new_encoder = intel_encoder;
6538
6539         intel_crtc = to_intel_crtc(crtc);
6540         old->dpms_mode = connector->dpms;
6541         old->load_detect_temp = true;
6542         old->release_fb = NULL;
6543
6544         if (!mode)
6545                 mode = &load_detect_mode;
6546
6547         /* We need a framebuffer large enough to accommodate all accesses
6548          * that the plane may generate whilst we perform load detection.
6549          * We can not rely on the fbcon either being present (we get called
6550          * during its initialisation to detect all boot displays, or it may
6551          * not even exist) or that it is large enough to satisfy the
6552          * requested mode.
6553          */
6554         fb = mode_fits_in_fbdev(dev, mode);
6555         if (fb == NULL) {
6556                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6557                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6558                 old->release_fb = fb;
6559         } else
6560                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6561         if (IS_ERR(fb)) {
6562                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6563                 return false;
6564         }
6565
6566         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6567                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6568                 if (old->release_fb)
6569                         old->release_fb->funcs->destroy(old->release_fb);
6570                 return false;
6571         }
6572
6573         /* let the connector get through one full cycle before testing */
6574         intel_wait_for_vblank(dev, intel_crtc->pipe);
6575         return true;
6576 }
6577
6578 void intel_release_load_detect_pipe(struct drm_connector *connector,
6579                                     struct intel_load_detect_pipe *old)
6580 {
6581         struct intel_encoder *intel_encoder =
6582                 intel_attached_encoder(connector);
6583         struct drm_encoder *encoder = &intel_encoder->base;
6584
6585         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6586                       connector->base.id, drm_get_connector_name(connector),
6587                       encoder->base.id, drm_get_encoder_name(encoder));
6588
6589         if (old->load_detect_temp) {
6590                 struct drm_crtc *crtc = encoder->crtc;
6591
6592                 to_intel_connector(connector)->new_encoder = NULL;
6593                 intel_encoder->new_crtc = NULL;
6594                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6595
6596                 if (old->release_fb)
6597                         old->release_fb->funcs->destroy(old->release_fb);
6598
6599                 return;
6600         }
6601
6602         /* Switch crtc and encoder back off if necessary */
6603         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6604                 connector->funcs->dpms(connector, old->dpms_mode);
6605 }
6606
6607 /* Returns the clock of the currently programmed mode of the given pipe. */
6608 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6609 {
6610         struct drm_i915_private *dev_priv = dev->dev_private;
6611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612         int pipe = intel_crtc->pipe;
6613         u32 dpll = I915_READ(DPLL(pipe));
6614         u32 fp;
6615         intel_clock_t clock;
6616
6617         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6618                 fp = I915_READ(FP0(pipe));
6619         else
6620                 fp = I915_READ(FP1(pipe));
6621
6622         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6623         if (IS_PINEVIEW(dev)) {
6624                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6625                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6626         } else {
6627                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6628                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6629         }
6630
6631         if (!IS_GEN2(dev)) {
6632                 if (IS_PINEVIEW(dev))
6633                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6634                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6635                 else
6636                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6637                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6638
6639                 switch (dpll & DPLL_MODE_MASK) {
6640                 case DPLLB_MODE_DAC_SERIAL:
6641                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6642                                 5 : 10;
6643                         break;
6644                 case DPLLB_MODE_LVDS:
6645                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6646                                 7 : 14;
6647                         break;
6648                 default:
6649                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6650                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6651                         return 0;
6652                 }
6653
6654                 /* XXX: Handle the 100Mhz refclk */
6655                 intel_clock(dev, 96000, &clock);
6656         } else {
6657                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6658
6659                 if (is_lvds) {
6660                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6661                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6662                         clock.p2 = 14;
6663
6664                         if ((dpll & PLL_REF_INPUT_MASK) ==
6665                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6666                                 /* XXX: might not be 66MHz */
6667                                 intel_clock(dev, 66000, &clock);
6668                         } else
6669                                 intel_clock(dev, 48000, &clock);
6670                 } else {
6671                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6672                                 clock.p1 = 2;
6673                         else {
6674                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6675                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6676                         }
6677                         if (dpll & PLL_P2_DIVIDE_BY_4)
6678                                 clock.p2 = 4;
6679                         else
6680                                 clock.p2 = 2;
6681
6682                         intel_clock(dev, 48000, &clock);
6683                 }
6684         }
6685
6686         /* XXX: It would be nice to validate the clocks, but we can't reuse
6687          * i830PllIsValid() because it relies on the xf86_config connector
6688          * configuration being accurate, which it isn't necessarily.
6689          */
6690
6691         return clock.dot;
6692 }
6693
6694 /** Returns the currently programmed mode of the given pipe. */
6695 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6696                                              struct drm_crtc *crtc)
6697 {
6698         struct drm_i915_private *dev_priv = dev->dev_private;
6699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6701         struct drm_display_mode *mode;
6702         int htot = I915_READ(HTOTAL(cpu_transcoder));
6703         int hsync = I915_READ(HSYNC(cpu_transcoder));
6704         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6705         int vsync = I915_READ(VSYNC(cpu_transcoder));
6706
6707         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6708         if (!mode)
6709                 return NULL;
6710
6711         mode->clock = intel_crtc_clock_get(dev, crtc);
6712         mode->hdisplay = (htot & 0xffff) + 1;
6713         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6714         mode->hsync_start = (hsync & 0xffff) + 1;
6715         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6716         mode->vdisplay = (vtot & 0xffff) + 1;
6717         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6718         mode->vsync_start = (vsync & 0xffff) + 1;
6719         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6720
6721         drm_mode_set_name(mode);
6722
6723         return mode;
6724 }
6725
6726 static void intel_increase_pllclock(struct drm_crtc *crtc)
6727 {
6728         struct drm_device *dev = crtc->dev;
6729         drm_i915_private_t *dev_priv = dev->dev_private;
6730         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6731         int pipe = intel_crtc->pipe;
6732         int dpll_reg = DPLL(pipe);
6733         int dpll;
6734
6735         if (HAS_PCH_SPLIT(dev))
6736                 return;
6737
6738         if (!dev_priv->lvds_downclock_avail)
6739                 return;
6740
6741         dpll = I915_READ(dpll_reg);
6742         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6743                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6744
6745                 assert_panel_unlocked(dev_priv, pipe);
6746
6747                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6748                 I915_WRITE(dpll_reg, dpll);
6749                 intel_wait_for_vblank(dev, pipe);
6750
6751                 dpll = I915_READ(dpll_reg);
6752                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6753                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6754         }
6755 }
6756
6757 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6758 {
6759         struct drm_device *dev = crtc->dev;
6760         drm_i915_private_t *dev_priv = dev->dev_private;
6761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6762
6763         if (HAS_PCH_SPLIT(dev))
6764                 return;
6765
6766         if (!dev_priv->lvds_downclock_avail)
6767                 return;
6768
6769         /*
6770          * Since this is called by a timer, we should never get here in
6771          * the manual case.
6772          */
6773         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6774                 int pipe = intel_crtc->pipe;
6775                 int dpll_reg = DPLL(pipe);
6776                 int dpll;
6777
6778                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6779
6780                 assert_panel_unlocked(dev_priv, pipe);
6781
6782                 dpll = I915_READ(dpll_reg);
6783                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6784                 I915_WRITE(dpll_reg, dpll);
6785                 intel_wait_for_vblank(dev, pipe);
6786                 dpll = I915_READ(dpll_reg);
6787                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6788                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6789         }
6790
6791 }
6792
6793 void intel_mark_busy(struct drm_device *dev)
6794 {
6795         i915_update_gfx_val(dev->dev_private);
6796 }
6797
6798 void intel_mark_idle(struct drm_device *dev)
6799 {
6800 }
6801
6802 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6803 {
6804         struct drm_device *dev = obj->base.dev;
6805         struct drm_crtc *crtc;
6806
6807         if (!i915_powersave)
6808                 return;
6809
6810         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6811                 if (!crtc->fb)
6812                         continue;
6813
6814                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6815                         intel_increase_pllclock(crtc);
6816         }
6817 }
6818
6819 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6820 {
6821         struct drm_device *dev = obj->base.dev;
6822         struct drm_crtc *crtc;
6823
6824         if (!i915_powersave)
6825                 return;
6826
6827         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6828                 if (!crtc->fb)
6829                         continue;
6830
6831                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6832                         intel_decrease_pllclock(crtc);
6833         }
6834 }
6835
6836 static void intel_crtc_destroy(struct drm_crtc *crtc)
6837 {
6838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6839         struct drm_device *dev = crtc->dev;
6840         struct intel_unpin_work *work;
6841         unsigned long flags;
6842
6843         spin_lock_irqsave(&dev->event_lock, flags);
6844         work = intel_crtc->unpin_work;
6845         intel_crtc->unpin_work = NULL;
6846         spin_unlock_irqrestore(&dev->event_lock, flags);
6847
6848         if (work) {
6849                 cancel_work_sync(&work->work);
6850                 kfree(work);
6851         }
6852
6853         drm_crtc_cleanup(crtc);
6854
6855         kfree(intel_crtc);
6856 }
6857
6858 static void intel_unpin_work_fn(struct work_struct *__work)
6859 {
6860         struct intel_unpin_work *work =
6861                 container_of(__work, struct intel_unpin_work, work);
6862         struct drm_device *dev = work->crtc->dev;
6863
6864         mutex_lock(&dev->struct_mutex);
6865         intel_unpin_fb_obj(work->old_fb_obj);
6866         drm_gem_object_unreference(&work->pending_flip_obj->base);
6867         drm_gem_object_unreference(&work->old_fb_obj->base);
6868
6869         intel_update_fbc(dev);
6870         mutex_unlock(&dev->struct_mutex);
6871
6872         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6873         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6874
6875         kfree(work);
6876 }
6877
6878 static void do_intel_finish_page_flip(struct drm_device *dev,
6879                                       struct drm_crtc *crtc)
6880 {
6881         drm_i915_private_t *dev_priv = dev->dev_private;
6882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6883         struct intel_unpin_work *work;
6884         struct drm_i915_gem_object *obj;
6885         unsigned long flags;
6886
6887         /* Ignore early vblank irqs */
6888         if (intel_crtc == NULL)
6889                 return;
6890
6891         spin_lock_irqsave(&dev->event_lock, flags);
6892         work = intel_crtc->unpin_work;
6893         if (work == NULL || !work->pending) {
6894                 spin_unlock_irqrestore(&dev->event_lock, flags);
6895                 return;
6896         }
6897
6898         intel_crtc->unpin_work = NULL;
6899
6900         if (work->event)
6901                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6902
6903         drm_vblank_put(dev, intel_crtc->pipe);
6904
6905         spin_unlock_irqrestore(&dev->event_lock, flags);
6906
6907         obj = work->old_fb_obj;
6908
6909         wake_up(&dev_priv->pending_flip_queue);
6910
6911         queue_work(dev_priv->wq, &work->work);
6912
6913         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6914 }
6915
6916 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6917 {
6918         drm_i915_private_t *dev_priv = dev->dev_private;
6919         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6920
6921         do_intel_finish_page_flip(dev, crtc);
6922 }
6923
6924 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6925 {
6926         drm_i915_private_t *dev_priv = dev->dev_private;
6927         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6928
6929         do_intel_finish_page_flip(dev, crtc);
6930 }
6931
6932 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6933 {
6934         drm_i915_private_t *dev_priv = dev->dev_private;
6935         struct intel_crtc *intel_crtc =
6936                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6937         unsigned long flags;
6938
6939         spin_lock_irqsave(&dev->event_lock, flags);
6940         if (intel_crtc->unpin_work) {
6941                 if ((++intel_crtc->unpin_work->pending) > 1)
6942                         DRM_ERROR("Prepared flip multiple times\n");
6943         } else {
6944                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6945         }
6946         spin_unlock_irqrestore(&dev->event_lock, flags);
6947 }
6948
6949 static int intel_gen2_queue_flip(struct drm_device *dev,
6950                                  struct drm_crtc *crtc,
6951                                  struct drm_framebuffer *fb,
6952                                  struct drm_i915_gem_object *obj)
6953 {
6954         struct drm_i915_private *dev_priv = dev->dev_private;
6955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956         u32 flip_mask;
6957         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6958         int ret;
6959
6960         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6961         if (ret)
6962                 goto err;
6963
6964         ret = intel_ring_begin(ring, 6);
6965         if (ret)
6966                 goto err_unpin;
6967
6968         /* Can't queue multiple flips, so wait for the previous
6969          * one to finish before executing the next.
6970          */
6971         if (intel_crtc->plane)
6972                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6973         else
6974                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6975         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6976         intel_ring_emit(ring, MI_NOOP);
6977         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6978                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6979         intel_ring_emit(ring, fb->pitches[0]);
6980         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6981         intel_ring_emit(ring, 0); /* aux display base address, unused */
6982         intel_ring_advance(ring);
6983         return 0;
6984
6985 err_unpin:
6986         intel_unpin_fb_obj(obj);
6987 err:
6988         return ret;
6989 }
6990
6991 static int intel_gen3_queue_flip(struct drm_device *dev,
6992                                  struct drm_crtc *crtc,
6993                                  struct drm_framebuffer *fb,
6994                                  struct drm_i915_gem_object *obj)
6995 {
6996         struct drm_i915_private *dev_priv = dev->dev_private;
6997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6998         u32 flip_mask;
6999         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7000         int ret;
7001
7002         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7003         if (ret)
7004                 goto err;
7005
7006         ret = intel_ring_begin(ring, 6);
7007         if (ret)
7008                 goto err_unpin;
7009
7010         if (intel_crtc->plane)
7011                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7012         else
7013                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7014         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7015         intel_ring_emit(ring, MI_NOOP);
7016         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7017                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7018         intel_ring_emit(ring, fb->pitches[0]);
7019         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7020         intel_ring_emit(ring, MI_NOOP);
7021
7022         intel_ring_advance(ring);
7023         return 0;
7024
7025 err_unpin:
7026         intel_unpin_fb_obj(obj);
7027 err:
7028         return ret;
7029 }
7030
7031 static int intel_gen4_queue_flip(struct drm_device *dev,
7032                                  struct drm_crtc *crtc,
7033                                  struct drm_framebuffer *fb,
7034                                  struct drm_i915_gem_object *obj)
7035 {
7036         struct drm_i915_private *dev_priv = dev->dev_private;
7037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7038         uint32_t pf, pipesrc;
7039         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7040         int ret;
7041
7042         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7043         if (ret)
7044                 goto err;
7045
7046         ret = intel_ring_begin(ring, 4);
7047         if (ret)
7048                 goto err_unpin;
7049
7050         /* i965+ uses the linear or tiled offsets from the
7051          * Display Registers (which do not change across a page-flip)
7052          * so we need only reprogram the base address.
7053          */
7054         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7055                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7056         intel_ring_emit(ring, fb->pitches[0]);
7057         intel_ring_emit(ring,
7058                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7059                         obj->tiling_mode);
7060
7061         /* XXX Enabling the panel-fitter across page-flip is so far
7062          * untested on non-native modes, so ignore it for now.
7063          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7064          */
7065         pf = 0;
7066         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7067         intel_ring_emit(ring, pf | pipesrc);
7068         intel_ring_advance(ring);
7069         return 0;
7070
7071 err_unpin:
7072         intel_unpin_fb_obj(obj);
7073 err:
7074         return ret;
7075 }
7076
7077 static int intel_gen6_queue_flip(struct drm_device *dev,
7078                                  struct drm_crtc *crtc,
7079                                  struct drm_framebuffer *fb,
7080                                  struct drm_i915_gem_object *obj)
7081 {
7082         struct drm_i915_private *dev_priv = dev->dev_private;
7083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7084         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7085         uint32_t pf, pipesrc;
7086         int ret;
7087
7088         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7089         if (ret)
7090                 goto err;
7091
7092         ret = intel_ring_begin(ring, 4);
7093         if (ret)
7094                 goto err_unpin;
7095
7096         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7097                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7098         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7099         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7100
7101         /* Contrary to the suggestions in the documentation,
7102          * "Enable Panel Fitter" does not seem to be required when page
7103          * flipping with a non-native mode, and worse causes a normal
7104          * modeset to fail.
7105          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7106          */
7107         pf = 0;
7108         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7109         intel_ring_emit(ring, pf | pipesrc);
7110         intel_ring_advance(ring);
7111         return 0;
7112
7113 err_unpin:
7114         intel_unpin_fb_obj(obj);
7115 err:
7116         return ret;
7117 }
7118
7119 /*
7120  * On gen7 we currently use the blit ring because (in early silicon at least)
7121  * the render ring doesn't give us interrpts for page flip completion, which
7122  * means clients will hang after the first flip is queued.  Fortunately the
7123  * blit ring generates interrupts properly, so use it instead.
7124  */
7125 static int intel_gen7_queue_flip(struct drm_device *dev,
7126                                  struct drm_crtc *crtc,
7127                                  struct drm_framebuffer *fb,
7128                                  struct drm_i915_gem_object *obj)
7129 {
7130         struct drm_i915_private *dev_priv = dev->dev_private;
7131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7132         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7133         uint32_t plane_bit = 0;
7134         int ret;
7135
7136         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7137         if (ret)
7138                 goto err;
7139
7140         switch(intel_crtc->plane) {
7141         case PLANE_A:
7142                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7143                 break;
7144         case PLANE_B:
7145                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7146                 break;
7147         case PLANE_C:
7148                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7149                 break;
7150         default:
7151                 WARN_ONCE(1, "unknown plane in flip command\n");
7152                 ret = -ENODEV;
7153                 goto err_unpin;
7154         }
7155
7156         ret = intel_ring_begin(ring, 4);
7157         if (ret)
7158                 goto err_unpin;
7159
7160         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7161         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7162         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7163         intel_ring_emit(ring, (MI_NOOP));
7164         intel_ring_advance(ring);
7165         return 0;
7166
7167 err_unpin:
7168         intel_unpin_fb_obj(obj);
7169 err:
7170         return ret;
7171 }
7172
7173 static int intel_default_queue_flip(struct drm_device *dev,
7174                                     struct drm_crtc *crtc,
7175                                     struct drm_framebuffer *fb,
7176                                     struct drm_i915_gem_object *obj)
7177 {
7178         return -ENODEV;
7179 }
7180
7181 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7182                                 struct drm_framebuffer *fb,
7183                                 struct drm_pending_vblank_event *event)
7184 {
7185         struct drm_device *dev = crtc->dev;
7186         struct drm_i915_private *dev_priv = dev->dev_private;
7187         struct intel_framebuffer *intel_fb;
7188         struct drm_i915_gem_object *obj;
7189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7190         struct intel_unpin_work *work;
7191         unsigned long flags;
7192         int ret;
7193
7194         /* Can't change pixel format via MI display flips. */
7195         if (fb->pixel_format != crtc->fb->pixel_format)
7196                 return -EINVAL;
7197
7198         /*
7199          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7200          * Note that pitch changes could also affect these register.
7201          */
7202         if (INTEL_INFO(dev)->gen > 3 &&
7203             (fb->offsets[0] != crtc->fb->offsets[0] ||
7204              fb->pitches[0] != crtc->fb->pitches[0]))
7205                 return -EINVAL;
7206
7207         work = kzalloc(sizeof *work, GFP_KERNEL);
7208         if (work == NULL)
7209                 return -ENOMEM;
7210
7211         work->event = event;
7212         work->crtc = crtc;
7213         intel_fb = to_intel_framebuffer(crtc->fb);
7214         work->old_fb_obj = intel_fb->obj;
7215         INIT_WORK(&work->work, intel_unpin_work_fn);
7216
7217         ret = drm_vblank_get(dev, intel_crtc->pipe);
7218         if (ret)
7219                 goto free_work;
7220
7221         /* We borrow the event spin lock for protecting unpin_work */
7222         spin_lock_irqsave(&dev->event_lock, flags);
7223         if (intel_crtc->unpin_work) {
7224                 spin_unlock_irqrestore(&dev->event_lock, flags);
7225                 kfree(work);
7226                 drm_vblank_put(dev, intel_crtc->pipe);
7227
7228                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7229                 return -EBUSY;
7230         }
7231         intel_crtc->unpin_work = work;
7232         spin_unlock_irqrestore(&dev->event_lock, flags);
7233
7234         intel_fb = to_intel_framebuffer(fb);
7235         obj = intel_fb->obj;
7236
7237         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7238                 flush_workqueue(dev_priv->wq);
7239
7240         ret = i915_mutex_lock_interruptible(dev);
7241         if (ret)
7242                 goto cleanup;
7243
7244         /* Reference the objects for the scheduled work. */
7245         drm_gem_object_reference(&work->old_fb_obj->base);
7246         drm_gem_object_reference(&obj->base);
7247
7248         crtc->fb = fb;
7249
7250         work->pending_flip_obj = obj;
7251
7252         work->enable_stall_check = true;
7253
7254         atomic_inc(&intel_crtc->unpin_work_count);
7255
7256         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7257         if (ret)
7258                 goto cleanup_pending;
7259
7260         intel_disable_fbc(dev);
7261         intel_mark_fb_busy(obj);
7262         mutex_unlock(&dev->struct_mutex);
7263
7264         trace_i915_flip_request(intel_crtc->plane, obj);
7265
7266         return 0;
7267
7268 cleanup_pending:
7269         atomic_dec(&intel_crtc->unpin_work_count);
7270         drm_gem_object_unreference(&work->old_fb_obj->base);
7271         drm_gem_object_unreference(&obj->base);
7272         mutex_unlock(&dev->struct_mutex);
7273
7274 cleanup:
7275         spin_lock_irqsave(&dev->event_lock, flags);
7276         intel_crtc->unpin_work = NULL;
7277         spin_unlock_irqrestore(&dev->event_lock, flags);
7278
7279         drm_vblank_put(dev, intel_crtc->pipe);
7280 free_work:
7281         kfree(work);
7282
7283         return ret;
7284 }
7285
7286 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7287         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7288         .load_lut = intel_crtc_load_lut,
7289         .disable = intel_crtc_noop,
7290 };
7291
7292 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7293 {
7294         struct intel_encoder *other_encoder;
7295         struct drm_crtc *crtc = &encoder->new_crtc->base;
7296
7297         if (WARN_ON(!crtc))
7298                 return false;
7299
7300         list_for_each_entry(other_encoder,
7301                             &crtc->dev->mode_config.encoder_list,
7302                             base.head) {
7303
7304                 if (&other_encoder->new_crtc->base != crtc ||
7305                     encoder == other_encoder)
7306                         continue;
7307                 else
7308                         return true;
7309         }
7310
7311         return false;
7312 }
7313
7314 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7315                                   struct drm_crtc *crtc)
7316 {
7317         struct drm_device *dev;
7318         struct drm_crtc *tmp;
7319         int crtc_mask = 1;
7320
7321         WARN(!crtc, "checking null crtc?\n");
7322
7323         dev = crtc->dev;
7324
7325         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7326                 if (tmp == crtc)
7327                         break;
7328                 crtc_mask <<= 1;
7329         }
7330
7331         if (encoder->possible_crtcs & crtc_mask)
7332                 return true;
7333         return false;
7334 }
7335
7336 /**
7337  * intel_modeset_update_staged_output_state
7338  *
7339  * Updates the staged output configuration state, e.g. after we've read out the
7340  * current hw state.
7341  */
7342 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7343 {
7344         struct intel_encoder *encoder;
7345         struct intel_connector *connector;
7346
7347         list_for_each_entry(connector, &dev->mode_config.connector_list,
7348                             base.head) {
7349                 connector->new_encoder =
7350                         to_intel_encoder(connector->base.encoder);
7351         }
7352
7353         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7354                             base.head) {
7355                 encoder->new_crtc =
7356                         to_intel_crtc(encoder->base.crtc);
7357         }
7358 }
7359
7360 /**
7361  * intel_modeset_commit_output_state
7362  *
7363  * This function copies the stage display pipe configuration to the real one.
7364  */
7365 static void intel_modeset_commit_output_state(struct drm_device *dev)
7366 {
7367         struct intel_encoder *encoder;
7368         struct intel_connector *connector;
7369
7370         list_for_each_entry(connector, &dev->mode_config.connector_list,
7371                             base.head) {
7372                 connector->base.encoder = &connector->new_encoder->base;
7373         }
7374
7375         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7376                             base.head) {
7377                 encoder->base.crtc = &encoder->new_crtc->base;
7378         }
7379 }
7380
7381 static struct drm_display_mode *
7382 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7383                             struct drm_display_mode *mode)
7384 {
7385         struct drm_device *dev = crtc->dev;
7386         struct drm_display_mode *adjusted_mode;
7387         struct drm_encoder_helper_funcs *encoder_funcs;
7388         struct intel_encoder *encoder;
7389
7390         adjusted_mode = drm_mode_duplicate(dev, mode);
7391         if (!adjusted_mode)
7392                 return ERR_PTR(-ENOMEM);
7393
7394         /* Pass our mode to the connectors and the CRTC to give them a chance to
7395          * adjust it according to limitations or connector properties, and also
7396          * a chance to reject the mode entirely.
7397          */
7398         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7399                             base.head) {
7400
7401                 if (&encoder->new_crtc->base != crtc)
7402                         continue;
7403                 encoder_funcs = encoder->base.helper_private;
7404                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7405                                                 adjusted_mode))) {
7406                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7407                         goto fail;
7408                 }
7409         }
7410
7411         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7412                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7413                 goto fail;
7414         }
7415         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7416
7417         return adjusted_mode;
7418 fail:
7419         drm_mode_destroy(dev, adjusted_mode);
7420         return ERR_PTR(-EINVAL);
7421 }
7422
7423 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7424  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7425 static void
7426 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7427                              unsigned *prepare_pipes, unsigned *disable_pipes)
7428 {
7429         struct intel_crtc *intel_crtc;
7430         struct drm_device *dev = crtc->dev;
7431         struct intel_encoder *encoder;
7432         struct intel_connector *connector;
7433         struct drm_crtc *tmp_crtc;
7434
7435         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7436
7437         /* Check which crtcs have changed outputs connected to them, these need
7438          * to be part of the prepare_pipes mask. We don't (yet) support global
7439          * modeset across multiple crtcs, so modeset_pipes will only have one
7440          * bit set at most. */
7441         list_for_each_entry(connector, &dev->mode_config.connector_list,
7442                             base.head) {
7443                 if (connector->base.encoder == &connector->new_encoder->base)
7444                         continue;
7445
7446                 if (connector->base.encoder) {
7447                         tmp_crtc = connector->base.encoder->crtc;
7448
7449                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7450                 }
7451
7452                 if (connector->new_encoder)
7453                         *prepare_pipes |=
7454                                 1 << connector->new_encoder->new_crtc->pipe;
7455         }
7456
7457         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7458                             base.head) {
7459                 if (encoder->base.crtc == &encoder->new_crtc->base)
7460                         continue;
7461
7462                 if (encoder->base.crtc) {
7463                         tmp_crtc = encoder->base.crtc;
7464
7465                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7466                 }
7467
7468                 if (encoder->new_crtc)
7469                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7470         }
7471
7472         /* Check for any pipes that will be fully disabled ... */
7473         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7474                             base.head) {
7475                 bool used = false;
7476
7477                 /* Don't try to disable disabled crtcs. */
7478                 if (!intel_crtc->base.enabled)
7479                         continue;
7480
7481                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7482                                     base.head) {
7483                         if (encoder->new_crtc == intel_crtc)
7484                                 used = true;
7485                 }
7486
7487                 if (!used)
7488                         *disable_pipes |= 1 << intel_crtc->pipe;
7489         }
7490
7491
7492         /* set_mode is also used to update properties on life display pipes. */
7493         intel_crtc = to_intel_crtc(crtc);
7494         if (crtc->enabled)
7495                 *prepare_pipes |= 1 << intel_crtc->pipe;
7496
7497         /* We only support modeset on one single crtc, hence we need to do that
7498          * only for the passed in crtc iff we change anything else than just
7499          * disable crtcs.
7500          *
7501          * This is actually not true, to be fully compatible with the old crtc
7502          * helper we automatically disable _any_ output (i.e. doesn't need to be
7503          * connected to the crtc we're modesetting on) if it's disconnected.
7504          * Which is a rather nutty api (since changed the output configuration
7505          * without userspace's explicit request can lead to confusion), but
7506          * alas. Hence we currently need to modeset on all pipes we prepare. */
7507         if (*prepare_pipes)
7508                 *modeset_pipes = *prepare_pipes;
7509
7510         /* ... and mask these out. */
7511         *modeset_pipes &= ~(*disable_pipes);
7512         *prepare_pipes &= ~(*disable_pipes);
7513 }
7514
7515 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7516 {
7517         struct drm_encoder *encoder;
7518         struct drm_device *dev = crtc->dev;
7519
7520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7521                 if (encoder->crtc == crtc)
7522                         return true;
7523
7524         return false;
7525 }
7526
7527 static void
7528 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7529 {
7530         struct intel_encoder *intel_encoder;
7531         struct intel_crtc *intel_crtc;
7532         struct drm_connector *connector;
7533
7534         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7535                             base.head) {
7536                 if (!intel_encoder->base.crtc)
7537                         continue;
7538
7539                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7540
7541                 if (prepare_pipes & (1 << intel_crtc->pipe))
7542                         intel_encoder->connectors_active = false;
7543         }
7544
7545         intel_modeset_commit_output_state(dev);
7546
7547         /* Update computed state. */
7548         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7549                             base.head) {
7550                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7551         }
7552
7553         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7554                 if (!connector->encoder || !connector->encoder->crtc)
7555                         continue;
7556
7557                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7558
7559                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7560                         struct drm_property *dpms_property =
7561                                 dev->mode_config.dpms_property;
7562
7563                         connector->dpms = DRM_MODE_DPMS_ON;
7564                         drm_object_property_set_value(&connector->base,
7565                                                          dpms_property,
7566                                                          DRM_MODE_DPMS_ON);
7567
7568                         intel_encoder = to_intel_encoder(connector->encoder);
7569                         intel_encoder->connectors_active = true;
7570                 }
7571         }
7572
7573 }
7574
7575 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7576         list_for_each_entry((intel_crtc), \
7577                             &(dev)->mode_config.crtc_list, \
7578                             base.head) \
7579                 if (mask & (1 <<(intel_crtc)->pipe)) \
7580
7581 void
7582 intel_modeset_check_state(struct drm_device *dev)
7583 {
7584         struct intel_crtc *crtc;
7585         struct intel_encoder *encoder;
7586         struct intel_connector *connector;
7587
7588         list_for_each_entry(connector, &dev->mode_config.connector_list,
7589                             base.head) {
7590                 /* This also checks the encoder/connector hw state with the
7591                  * ->get_hw_state callbacks. */
7592                 intel_connector_check_state(connector);
7593
7594                 WARN(&connector->new_encoder->base != connector->base.encoder,
7595                      "connector's staged encoder doesn't match current encoder\n");
7596         }
7597
7598         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7599                             base.head) {
7600                 bool enabled = false;
7601                 bool active = false;
7602                 enum pipe pipe, tracked_pipe;
7603
7604                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7605                               encoder->base.base.id,
7606                               drm_get_encoder_name(&encoder->base));
7607
7608                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7609                      "encoder's stage crtc doesn't match current crtc\n");
7610                 WARN(encoder->connectors_active && !encoder->base.crtc,
7611                      "encoder's active_connectors set, but no crtc\n");
7612
7613                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7614                                     base.head) {
7615                         if (connector->base.encoder != &encoder->base)
7616                                 continue;
7617                         enabled = true;
7618                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7619                                 active = true;
7620                 }
7621                 WARN(!!encoder->base.crtc != enabled,
7622                      "encoder's enabled state mismatch "
7623                      "(expected %i, found %i)\n",
7624                      !!encoder->base.crtc, enabled);
7625                 WARN(active && !encoder->base.crtc,
7626                      "active encoder with no crtc\n");
7627
7628                 WARN(encoder->connectors_active != active,
7629                      "encoder's computed active state doesn't match tracked active state "
7630                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7631
7632                 active = encoder->get_hw_state(encoder, &pipe);
7633                 WARN(active != encoder->connectors_active,
7634                      "encoder's hw state doesn't match sw tracking "
7635                      "(expected %i, found %i)\n",
7636                      encoder->connectors_active, active);
7637
7638                 if (!encoder->base.crtc)
7639                         continue;
7640
7641                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7642                 WARN(active && pipe != tracked_pipe,
7643                      "active encoder's pipe doesn't match"
7644                      "(expected %i, found %i)\n",
7645                      tracked_pipe, pipe);
7646
7647         }
7648
7649         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7650                             base.head) {
7651                 bool enabled = false;
7652                 bool active = false;
7653
7654                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7655                               crtc->base.base.id);
7656
7657                 WARN(crtc->active && !crtc->base.enabled,
7658                      "active crtc, but not enabled in sw tracking\n");
7659
7660                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7661                                     base.head) {
7662                         if (encoder->base.crtc != &crtc->base)
7663                                 continue;
7664                         enabled = true;
7665                         if (encoder->connectors_active)
7666                                 active = true;
7667                 }
7668                 WARN(active != crtc->active,
7669                      "crtc's computed active state doesn't match tracked active state "
7670                      "(expected %i, found %i)\n", active, crtc->active);
7671                 WARN(enabled != crtc->base.enabled,
7672                      "crtc's computed enabled state doesn't match tracked enabled state "
7673                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7674
7675                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7676         }
7677 }
7678
7679 bool intel_set_mode(struct drm_crtc *crtc,
7680                     struct drm_display_mode *mode,
7681                     int x, int y, struct drm_framebuffer *fb)
7682 {
7683         struct drm_device *dev = crtc->dev;
7684         drm_i915_private_t *dev_priv = dev->dev_private;
7685         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7686         struct intel_crtc *intel_crtc;
7687         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7688         bool ret = true;
7689
7690         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7691                                      &prepare_pipes, &disable_pipes);
7692
7693         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7694                       modeset_pipes, prepare_pipes, disable_pipes);
7695
7696         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7697                 intel_crtc_disable(&intel_crtc->base);
7698
7699         saved_hwmode = crtc->hwmode;
7700         saved_mode = crtc->mode;
7701
7702         /* Hack: Because we don't (yet) support global modeset on multiple
7703          * crtcs, we don't keep track of the new mode for more than one crtc.
7704          * Hence simply check whether any bit is set in modeset_pipes in all the
7705          * pieces of code that are not yet converted to deal with mutliple crtcs
7706          * changing their mode at the same time. */
7707         adjusted_mode = NULL;
7708         if (modeset_pipes) {
7709                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7710                 if (IS_ERR(adjusted_mode)) {
7711                         return false;
7712                 }
7713         }
7714
7715         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7716                 if (intel_crtc->base.enabled)
7717                         dev_priv->display.crtc_disable(&intel_crtc->base);
7718         }
7719
7720         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7721          * to set it here already despite that we pass it down the callchain.
7722          */
7723         if (modeset_pipes)
7724                 crtc->mode = *mode;
7725
7726         /* Only after disabling all output pipelines that will be changed can we
7727          * update the the output configuration. */
7728         intel_modeset_update_state(dev, prepare_pipes);
7729
7730         if (dev_priv->display.modeset_global_resources)
7731                 dev_priv->display.modeset_global_resources(dev);
7732
7733         /* Set up the DPLL and any encoders state that needs to adjust or depend
7734          * on the DPLL.
7735          */
7736         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7737                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7738                                            mode, adjusted_mode,
7739                                            x, y, fb);
7740                 if (!ret)
7741                     goto done;
7742         }
7743
7744         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7745         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7746                 dev_priv->display.crtc_enable(&intel_crtc->base);
7747
7748         if (modeset_pipes) {
7749                 /* Store real post-adjustment hardware mode. */
7750                 crtc->hwmode = *adjusted_mode;
7751
7752                 /* Calculate and store various constants which
7753                  * are later needed by vblank and swap-completion
7754                  * timestamping. They are derived from true hwmode.
7755                  */
7756                 drm_calc_timestamping_constants(crtc);
7757         }
7758
7759         /* FIXME: add subpixel order */
7760 done:
7761         drm_mode_destroy(dev, adjusted_mode);
7762         if (!ret && crtc->enabled) {
7763                 crtc->hwmode = saved_hwmode;
7764                 crtc->mode = saved_mode;
7765         } else {
7766                 intel_modeset_check_state(dev);
7767         }
7768
7769         return ret;
7770 }
7771
7772 #undef for_each_intel_crtc_masked
7773
7774 static void intel_set_config_free(struct intel_set_config *config)
7775 {
7776         if (!config)
7777                 return;
7778
7779         kfree(config->save_connector_encoders);
7780         kfree(config->save_encoder_crtcs);
7781         kfree(config);
7782 }
7783
7784 static int intel_set_config_save_state(struct drm_device *dev,
7785                                        struct intel_set_config *config)
7786 {
7787         struct drm_encoder *encoder;
7788         struct drm_connector *connector;
7789         int count;
7790
7791         config->save_encoder_crtcs =
7792                 kcalloc(dev->mode_config.num_encoder,
7793                         sizeof(struct drm_crtc *), GFP_KERNEL);
7794         if (!config->save_encoder_crtcs)
7795                 return -ENOMEM;
7796
7797         config->save_connector_encoders =
7798                 kcalloc(dev->mode_config.num_connector,
7799                         sizeof(struct drm_encoder *), GFP_KERNEL);
7800         if (!config->save_connector_encoders)
7801                 return -ENOMEM;
7802
7803         /* Copy data. Note that driver private data is not affected.
7804          * Should anything bad happen only the expected state is
7805          * restored, not the drivers personal bookkeeping.
7806          */
7807         count = 0;
7808         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7809                 config->save_encoder_crtcs[count++] = encoder->crtc;
7810         }
7811
7812         count = 0;
7813         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7814                 config->save_connector_encoders[count++] = connector->encoder;
7815         }
7816
7817         return 0;
7818 }
7819
7820 static void intel_set_config_restore_state(struct drm_device *dev,
7821                                            struct intel_set_config *config)
7822 {
7823         struct intel_encoder *encoder;
7824         struct intel_connector *connector;
7825         int count;
7826
7827         count = 0;
7828         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7829                 encoder->new_crtc =
7830                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7831         }
7832
7833         count = 0;
7834         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7835                 connector->new_encoder =
7836                         to_intel_encoder(config->save_connector_encoders[count++]);
7837         }
7838 }
7839
7840 static void
7841 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7842                                       struct intel_set_config *config)
7843 {
7844
7845         /* We should be able to check here if the fb has the same properties
7846          * and then just flip_or_move it */
7847         if (set->crtc->fb != set->fb) {
7848                 /* If we have no fb then treat it as a full mode set */
7849                 if (set->crtc->fb == NULL) {
7850                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7851                         config->mode_changed = true;
7852                 } else if (set->fb == NULL) {
7853                         config->mode_changed = true;
7854                 } else if (set->fb->depth != set->crtc->fb->depth) {
7855                         config->mode_changed = true;
7856                 } else if (set->fb->bits_per_pixel !=
7857                            set->crtc->fb->bits_per_pixel) {
7858                         config->mode_changed = true;
7859                 } else
7860                         config->fb_changed = true;
7861         }
7862
7863         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7864                 config->fb_changed = true;
7865
7866         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7867                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7868                 drm_mode_debug_printmodeline(&set->crtc->mode);
7869                 drm_mode_debug_printmodeline(set->mode);
7870                 config->mode_changed = true;
7871         }
7872 }
7873
7874 static int
7875 intel_modeset_stage_output_state(struct drm_device *dev,
7876                                  struct drm_mode_set *set,
7877                                  struct intel_set_config *config)
7878 {
7879         struct drm_crtc *new_crtc;
7880         struct intel_connector *connector;
7881         struct intel_encoder *encoder;
7882         int count, ro;
7883
7884         /* The upper layers ensure that we either disabl a crtc or have a list
7885          * of connectors. For paranoia, double-check this. */
7886         WARN_ON(!set->fb && (set->num_connectors != 0));
7887         WARN_ON(set->fb && (set->num_connectors == 0));
7888
7889         count = 0;
7890         list_for_each_entry(connector, &dev->mode_config.connector_list,
7891                             base.head) {
7892                 /* Otherwise traverse passed in connector list and get encoders
7893                  * for them. */
7894                 for (ro = 0; ro < set->num_connectors; ro++) {
7895                         if (set->connectors[ro] == &connector->base) {
7896                                 connector->new_encoder = connector->encoder;
7897                                 break;
7898                         }
7899                 }
7900
7901                 /* If we disable the crtc, disable all its connectors. Also, if
7902                  * the connector is on the changing crtc but not on the new
7903                  * connector list, disable it. */
7904                 if ((!set->fb || ro == set->num_connectors) &&
7905                     connector->base.encoder &&
7906                     connector->base.encoder->crtc == set->crtc) {
7907                         connector->new_encoder = NULL;
7908
7909                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7910                                 connector->base.base.id,
7911                                 drm_get_connector_name(&connector->base));
7912                 }
7913
7914
7915                 if (&connector->new_encoder->base != connector->base.encoder) {
7916                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7917                         config->mode_changed = true;
7918                 }
7919
7920                 /* Disable all disconnected encoders. */
7921                 if (connector->base.status == connector_status_disconnected)
7922                         connector->new_encoder = NULL;
7923         }
7924         /* connector->new_encoder is now updated for all connectors. */
7925
7926         /* Update crtc of enabled connectors. */
7927         count = 0;
7928         list_for_each_entry(connector, &dev->mode_config.connector_list,
7929                             base.head) {
7930                 if (!connector->new_encoder)
7931                         continue;
7932
7933                 new_crtc = connector->new_encoder->base.crtc;
7934
7935                 for (ro = 0; ro < set->num_connectors; ro++) {
7936                         if (set->connectors[ro] == &connector->base)
7937                                 new_crtc = set->crtc;
7938                 }
7939
7940                 /* Make sure the new CRTC will work with the encoder */
7941                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7942                                            new_crtc)) {
7943                         return -EINVAL;
7944                 }
7945                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7946
7947                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7948                         connector->base.base.id,
7949                         drm_get_connector_name(&connector->base),
7950                         new_crtc->base.id);
7951         }
7952
7953         /* Check for any encoders that needs to be disabled. */
7954         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7955                             base.head) {
7956                 list_for_each_entry(connector,
7957                                     &dev->mode_config.connector_list,
7958                                     base.head) {
7959                         if (connector->new_encoder == encoder) {
7960                                 WARN_ON(!connector->new_encoder->new_crtc);
7961
7962                                 goto next_encoder;
7963                         }
7964                 }
7965                 encoder->new_crtc = NULL;
7966 next_encoder:
7967                 /* Only now check for crtc changes so we don't miss encoders
7968                  * that will be disabled. */
7969                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7970                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7971                         config->mode_changed = true;
7972                 }
7973         }
7974         /* Now we've also updated encoder->new_crtc for all encoders. */
7975
7976         return 0;
7977 }
7978
7979 static int intel_crtc_set_config(struct drm_mode_set *set)
7980 {
7981         struct drm_device *dev;
7982         struct drm_mode_set save_set;
7983         struct intel_set_config *config;
7984         int ret;
7985
7986         BUG_ON(!set);
7987         BUG_ON(!set->crtc);
7988         BUG_ON(!set->crtc->helper_private);
7989
7990         if (!set->mode)
7991                 set->fb = NULL;
7992
7993         /* The fb helper likes to play gross jokes with ->mode_set_config.
7994          * Unfortunately the crtc helper doesn't do much at all for this case,
7995          * so we have to cope with this madness until the fb helper is fixed up. */
7996         if (set->fb && set->num_connectors == 0)
7997                 return 0;
7998
7999         if (set->fb) {
8000                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8001                                 set->crtc->base.id, set->fb->base.id,
8002                                 (int)set->num_connectors, set->x, set->y);
8003         } else {
8004                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8005         }
8006
8007         dev = set->crtc->dev;
8008
8009         ret = -ENOMEM;
8010         config = kzalloc(sizeof(*config), GFP_KERNEL);
8011         if (!config)
8012                 goto out_config;
8013
8014         ret = intel_set_config_save_state(dev, config);
8015         if (ret)
8016                 goto out_config;
8017
8018         save_set.crtc = set->crtc;
8019         save_set.mode = &set->crtc->mode;
8020         save_set.x = set->crtc->x;
8021         save_set.y = set->crtc->y;
8022         save_set.fb = set->crtc->fb;
8023
8024         /* Compute whether we need a full modeset, only an fb base update or no
8025          * change at all. In the future we might also check whether only the
8026          * mode changed, e.g. for LVDS where we only change the panel fitter in
8027          * such cases. */
8028         intel_set_config_compute_mode_changes(set, config);
8029
8030         ret = intel_modeset_stage_output_state(dev, set, config);
8031         if (ret)
8032                 goto fail;
8033
8034         if (config->mode_changed) {
8035                 if (set->mode) {
8036                         DRM_DEBUG_KMS("attempting to set mode from"
8037                                         " userspace\n");
8038                         drm_mode_debug_printmodeline(set->mode);
8039                 }
8040
8041                 if (!intel_set_mode(set->crtc, set->mode,
8042                                     set->x, set->y, set->fb)) {
8043                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8044                                   set->crtc->base.id);
8045                         ret = -EINVAL;
8046                         goto fail;
8047                 }
8048         } else if (config->fb_changed) {
8049                 ret = intel_pipe_set_base(set->crtc,
8050                                           set->x, set->y, set->fb);
8051         }
8052
8053         intel_set_config_free(config);
8054
8055         return 0;
8056
8057 fail:
8058         intel_set_config_restore_state(dev, config);
8059
8060         /* Try to restore the config */
8061         if (config->mode_changed &&
8062             !intel_set_mode(save_set.crtc, save_set.mode,
8063                             save_set.x, save_set.y, save_set.fb))
8064                 DRM_ERROR("failed to restore config after modeset failure\n");
8065
8066 out_config:
8067         intel_set_config_free(config);
8068         return ret;
8069 }
8070
8071 static const struct drm_crtc_funcs intel_crtc_funcs = {
8072         .cursor_set = intel_crtc_cursor_set,
8073         .cursor_move = intel_crtc_cursor_move,
8074         .gamma_set = intel_crtc_gamma_set,
8075         .set_config = intel_crtc_set_config,
8076         .destroy = intel_crtc_destroy,
8077         .page_flip = intel_crtc_page_flip,
8078 };
8079
8080 static void intel_cpu_pll_init(struct drm_device *dev)
8081 {
8082         if (IS_HASWELL(dev))
8083                 intel_ddi_pll_init(dev);
8084 }
8085
8086 static void intel_pch_pll_init(struct drm_device *dev)
8087 {
8088         drm_i915_private_t *dev_priv = dev->dev_private;
8089         int i;
8090
8091         if (dev_priv->num_pch_pll == 0) {
8092                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8093                 return;
8094         }
8095
8096         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8097                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8098                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8099                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8100         }
8101 }
8102
8103 static void intel_crtc_init(struct drm_device *dev, int pipe)
8104 {
8105         drm_i915_private_t *dev_priv = dev->dev_private;
8106         struct intel_crtc *intel_crtc;
8107         int i;
8108
8109         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8110         if (intel_crtc == NULL)
8111                 return;
8112
8113         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8114
8115         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8116         for (i = 0; i < 256; i++) {
8117                 intel_crtc->lut_r[i] = i;
8118                 intel_crtc->lut_g[i] = i;
8119                 intel_crtc->lut_b[i] = i;
8120         }
8121
8122         /* Swap pipes & planes for FBC on pre-965 */
8123         intel_crtc->pipe = pipe;
8124         intel_crtc->plane = pipe;
8125         intel_crtc->cpu_transcoder = pipe;
8126         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8127                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8128                 intel_crtc->plane = !pipe;
8129         }
8130
8131         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8132                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8133         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8134         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8135
8136         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8137
8138         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8139 }
8140
8141 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8142                                 struct drm_file *file)
8143 {
8144         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8145         struct drm_mode_object *drmmode_obj;
8146         struct intel_crtc *crtc;
8147
8148         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8149                 return -ENODEV;
8150
8151         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8152                         DRM_MODE_OBJECT_CRTC);
8153
8154         if (!drmmode_obj) {
8155                 DRM_ERROR("no such CRTC id\n");
8156                 return -EINVAL;
8157         }
8158
8159         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8160         pipe_from_crtc_id->pipe = crtc->pipe;
8161
8162         return 0;
8163 }
8164
8165 static int intel_encoder_clones(struct intel_encoder *encoder)
8166 {
8167         struct drm_device *dev = encoder->base.dev;
8168         struct intel_encoder *source_encoder;
8169         int index_mask = 0;
8170         int entry = 0;
8171
8172         list_for_each_entry(source_encoder,
8173                             &dev->mode_config.encoder_list, base.head) {
8174
8175                 if (encoder == source_encoder)
8176                         index_mask |= (1 << entry);
8177
8178                 /* Intel hw has only one MUX where enocoders could be cloned. */
8179                 if (encoder->cloneable && source_encoder->cloneable)
8180                         index_mask |= (1 << entry);
8181
8182                 entry++;
8183         }
8184
8185         return index_mask;
8186 }
8187
8188 static bool has_edp_a(struct drm_device *dev)
8189 {
8190         struct drm_i915_private *dev_priv = dev->dev_private;
8191
8192         if (!IS_MOBILE(dev))
8193                 return false;
8194
8195         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8196                 return false;
8197
8198         if (IS_GEN5(dev) &&
8199             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8200                 return false;
8201
8202         return true;
8203 }
8204
8205 static void intel_setup_outputs(struct drm_device *dev)
8206 {
8207         struct drm_i915_private *dev_priv = dev->dev_private;
8208         struct intel_encoder *encoder;
8209         bool dpd_is_edp = false;
8210         bool has_lvds;
8211
8212         has_lvds = intel_lvds_init(dev);
8213         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8214                 /* disable the panel fitter on everything but LVDS */
8215                 I915_WRITE(PFIT_CONTROL, 0);
8216         }
8217
8218         if (!(IS_HASWELL(dev) &&
8219               (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8220                 intel_crt_init(dev);
8221
8222         if (IS_HASWELL(dev)) {
8223                 int found;
8224
8225                 /* Haswell uses DDI functions to detect digital outputs */
8226                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8227                 /* DDI A only supports eDP */
8228                 if (found)
8229                         intel_ddi_init(dev, PORT_A);
8230
8231                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8232                  * register */
8233                 found = I915_READ(SFUSE_STRAP);
8234
8235                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8236                         intel_ddi_init(dev, PORT_B);
8237                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8238                         intel_ddi_init(dev, PORT_C);
8239                 if (found & SFUSE_STRAP_DDID_DETECTED)
8240                         intel_ddi_init(dev, PORT_D);
8241         } else if (HAS_PCH_SPLIT(dev)) {
8242                 int found;
8243                 dpd_is_edp = intel_dpd_is_edp(dev);
8244
8245                 if (has_edp_a(dev))
8246                         intel_dp_init(dev, DP_A, PORT_A);
8247
8248                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8249                         /* PCH SDVOB multiplex with HDMIB */
8250                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8251                         if (!found)
8252                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8253                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8254                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8255                 }
8256
8257                 if (I915_READ(HDMIC) & PORT_DETECTED)
8258                         intel_hdmi_init(dev, HDMIC, PORT_C);
8259
8260                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8261                         intel_hdmi_init(dev, HDMID, PORT_D);
8262
8263                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8264                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8265
8266                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8267                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8268         } else if (IS_VALLEYVIEW(dev)) {
8269                 int found;
8270
8271                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8272                 if (I915_READ(DP_C) & DP_DETECTED)
8273                         intel_dp_init(dev, DP_C, PORT_C);
8274
8275                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8276                         /* SDVOB multiplex with HDMIB */
8277                         found = intel_sdvo_init(dev, SDVOB, true);
8278                         if (!found)
8279                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8280                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8281                                 intel_dp_init(dev, DP_B, PORT_B);
8282                 }
8283
8284                 if (I915_READ(SDVOC) & PORT_DETECTED)
8285                         intel_hdmi_init(dev, SDVOC, PORT_C);
8286
8287         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8288                 bool found = false;
8289
8290                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8291                         DRM_DEBUG_KMS("probing SDVOB\n");
8292                         found = intel_sdvo_init(dev, SDVOB, true);
8293                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8294                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8295                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8296                         }
8297
8298                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8299                                 DRM_DEBUG_KMS("probing DP_B\n");
8300                                 intel_dp_init(dev, DP_B, PORT_B);
8301                         }
8302                 }
8303
8304                 /* Before G4X SDVOC doesn't have its own detect register */
8305
8306                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8307                         DRM_DEBUG_KMS("probing SDVOC\n");
8308                         found = intel_sdvo_init(dev, SDVOC, false);
8309                 }
8310
8311                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8312
8313                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8314                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8315                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8316                         }
8317                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8318                                 DRM_DEBUG_KMS("probing DP_C\n");
8319                                 intel_dp_init(dev, DP_C, PORT_C);
8320                         }
8321                 }
8322
8323                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8324                     (I915_READ(DP_D) & DP_DETECTED)) {
8325                         DRM_DEBUG_KMS("probing DP_D\n");
8326                         intel_dp_init(dev, DP_D, PORT_D);
8327                 }
8328         } else if (IS_GEN2(dev))
8329                 intel_dvo_init(dev);
8330
8331         if (SUPPORTS_TV(dev))
8332                 intel_tv_init(dev);
8333
8334         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8335                 encoder->base.possible_crtcs = encoder->crtc_mask;
8336                 encoder->base.possible_clones =
8337                         intel_encoder_clones(encoder);
8338         }
8339
8340         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8341                 ironlake_init_pch_refclk(dev);
8342
8343         drm_helper_move_panel_connectors_to_head(dev);
8344 }
8345
8346 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8347 {
8348         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8349
8350         drm_framebuffer_cleanup(fb);
8351         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8352
8353         kfree(intel_fb);
8354 }
8355
8356 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8357                                                 struct drm_file *file,
8358                                                 unsigned int *handle)
8359 {
8360         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8361         struct drm_i915_gem_object *obj = intel_fb->obj;
8362
8363         return drm_gem_handle_create(file, &obj->base, handle);
8364 }
8365
8366 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8367         .destroy = intel_user_framebuffer_destroy,
8368         .create_handle = intel_user_framebuffer_create_handle,
8369 };
8370
8371 int intel_framebuffer_init(struct drm_device *dev,
8372                            struct intel_framebuffer *intel_fb,
8373                            struct drm_mode_fb_cmd2 *mode_cmd,
8374                            struct drm_i915_gem_object *obj)
8375 {
8376         int ret;
8377
8378         if (obj->tiling_mode == I915_TILING_Y)
8379                 return -EINVAL;
8380
8381         if (mode_cmd->pitches[0] & 63)
8382                 return -EINVAL;
8383
8384         /* FIXME <= Gen4 stride limits are bit unclear */
8385         if (mode_cmd->pitches[0] > 32768)
8386                 return -EINVAL;
8387
8388         if (obj->tiling_mode != I915_TILING_NONE &&
8389             mode_cmd->pitches[0] != obj->stride)
8390                 return -EINVAL;
8391
8392         /* Reject formats not supported by any plane early. */
8393         switch (mode_cmd->pixel_format) {
8394         case DRM_FORMAT_C8:
8395         case DRM_FORMAT_RGB565:
8396         case DRM_FORMAT_XRGB8888:
8397         case DRM_FORMAT_ARGB8888:
8398                 break;
8399         case DRM_FORMAT_XRGB1555:
8400         case DRM_FORMAT_ARGB1555:
8401                 if (INTEL_INFO(dev)->gen > 3)
8402                         return -EINVAL;
8403                 break;
8404         case DRM_FORMAT_XBGR8888:
8405         case DRM_FORMAT_ABGR8888:
8406         case DRM_FORMAT_XRGB2101010:
8407         case DRM_FORMAT_ARGB2101010:
8408         case DRM_FORMAT_XBGR2101010:
8409         case DRM_FORMAT_ABGR2101010:
8410                 if (INTEL_INFO(dev)->gen < 4)
8411                         return -EINVAL;
8412                 break;
8413         case DRM_FORMAT_YUYV:
8414         case DRM_FORMAT_UYVY:
8415         case DRM_FORMAT_YVYU:
8416         case DRM_FORMAT_VYUY:
8417                 if (INTEL_INFO(dev)->gen < 6)
8418                         return -EINVAL;
8419                 break;
8420         default:
8421                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8422                 return -EINVAL;
8423         }
8424
8425         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8426         if (mode_cmd->offsets[0] != 0)
8427                 return -EINVAL;
8428
8429         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8430         if (ret) {
8431                 DRM_ERROR("framebuffer init failed %d\n", ret);
8432                 return ret;
8433         }
8434
8435         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8436         intel_fb->obj = obj;
8437         return 0;
8438 }
8439
8440 static struct drm_framebuffer *
8441 intel_user_framebuffer_create(struct drm_device *dev,
8442                               struct drm_file *filp,
8443                               struct drm_mode_fb_cmd2 *mode_cmd)
8444 {
8445         struct drm_i915_gem_object *obj;
8446
8447         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8448                                                 mode_cmd->handles[0]));
8449         if (&obj->base == NULL)
8450                 return ERR_PTR(-ENOENT);
8451
8452         return intel_framebuffer_create(dev, mode_cmd, obj);
8453 }
8454
8455 static const struct drm_mode_config_funcs intel_mode_funcs = {
8456         .fb_create = intel_user_framebuffer_create,
8457         .output_poll_changed = intel_fb_output_poll_changed,
8458 };
8459
8460 /* Set up chip specific display functions */
8461 static void intel_init_display(struct drm_device *dev)
8462 {
8463         struct drm_i915_private *dev_priv = dev->dev_private;
8464
8465         /* We always want a DPMS function */
8466         if (IS_HASWELL(dev)) {
8467                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8468                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8469                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8470                 dev_priv->display.off = haswell_crtc_off;
8471                 dev_priv->display.update_plane = ironlake_update_plane;
8472         } else if (HAS_PCH_SPLIT(dev)) {
8473                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8474                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8475                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8476                 dev_priv->display.off = ironlake_crtc_off;
8477                 dev_priv->display.update_plane = ironlake_update_plane;
8478         } else {
8479                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8480                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8481                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8482                 dev_priv->display.off = i9xx_crtc_off;
8483                 dev_priv->display.update_plane = i9xx_update_plane;
8484         }
8485
8486         /* Returns the core display clock speed */
8487         if (IS_VALLEYVIEW(dev))
8488                 dev_priv->display.get_display_clock_speed =
8489                         valleyview_get_display_clock_speed;
8490         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8491                 dev_priv->display.get_display_clock_speed =
8492                         i945_get_display_clock_speed;
8493         else if (IS_I915G(dev))
8494                 dev_priv->display.get_display_clock_speed =
8495                         i915_get_display_clock_speed;
8496         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8497                 dev_priv->display.get_display_clock_speed =
8498                         i9xx_misc_get_display_clock_speed;
8499         else if (IS_I915GM(dev))
8500                 dev_priv->display.get_display_clock_speed =
8501                         i915gm_get_display_clock_speed;
8502         else if (IS_I865G(dev))
8503                 dev_priv->display.get_display_clock_speed =
8504                         i865_get_display_clock_speed;
8505         else if (IS_I85X(dev))
8506                 dev_priv->display.get_display_clock_speed =
8507                         i855_get_display_clock_speed;
8508         else /* 852, 830 */
8509                 dev_priv->display.get_display_clock_speed =
8510                         i830_get_display_clock_speed;
8511
8512         if (HAS_PCH_SPLIT(dev)) {
8513                 if (IS_GEN5(dev)) {
8514                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8515                         dev_priv->display.write_eld = ironlake_write_eld;
8516                 } else if (IS_GEN6(dev)) {
8517                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8518                         dev_priv->display.write_eld = ironlake_write_eld;
8519                 } else if (IS_IVYBRIDGE(dev)) {
8520                         /* FIXME: detect B0+ stepping and use auto training */
8521                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8522                         dev_priv->display.write_eld = ironlake_write_eld;
8523                         dev_priv->display.modeset_global_resources =
8524                                 ivb_modeset_global_resources;
8525                 } else if (IS_HASWELL(dev)) {
8526                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8527                         dev_priv->display.write_eld = haswell_write_eld;
8528                 } else
8529                         dev_priv->display.update_wm = NULL;
8530         } else if (IS_G4X(dev)) {
8531                 dev_priv->display.write_eld = g4x_write_eld;
8532         }
8533
8534         /* Default just returns -ENODEV to indicate unsupported */
8535         dev_priv->display.queue_flip = intel_default_queue_flip;
8536
8537         switch (INTEL_INFO(dev)->gen) {
8538         case 2:
8539                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8540                 break;
8541
8542         case 3:
8543                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8544                 break;
8545
8546         case 4:
8547         case 5:
8548                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8549                 break;
8550
8551         case 6:
8552                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8553                 break;
8554         case 7:
8555                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8556                 break;
8557         }
8558 }
8559
8560 /*
8561  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8562  * resume, or other times.  This quirk makes sure that's the case for
8563  * affected systems.
8564  */
8565 static void quirk_pipea_force(struct drm_device *dev)
8566 {
8567         struct drm_i915_private *dev_priv = dev->dev_private;
8568
8569         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8570         DRM_INFO("applying pipe a force quirk\n");
8571 }
8572
8573 /*
8574  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8575  */
8576 static void quirk_ssc_force_disable(struct drm_device *dev)
8577 {
8578         struct drm_i915_private *dev_priv = dev->dev_private;
8579         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8580         DRM_INFO("applying lvds SSC disable quirk\n");
8581 }
8582
8583 /*
8584  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8585  * brightness value
8586  */
8587 static void quirk_invert_brightness(struct drm_device *dev)
8588 {
8589         struct drm_i915_private *dev_priv = dev->dev_private;
8590         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8591         DRM_INFO("applying inverted panel brightness quirk\n");
8592 }
8593
8594 struct intel_quirk {
8595         int device;
8596         int subsystem_vendor;
8597         int subsystem_device;
8598         void (*hook)(struct drm_device *dev);
8599 };
8600
8601 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8602 struct intel_dmi_quirk {
8603         void (*hook)(struct drm_device *dev);
8604         const struct dmi_system_id (*dmi_id_list)[];
8605 };
8606
8607 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8608 {
8609         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8610         return 1;
8611 }
8612
8613 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8614         {
8615                 .dmi_id_list = &(const struct dmi_system_id[]) {
8616                         {
8617                                 .callback = intel_dmi_reverse_brightness,
8618                                 .ident = "NCR Corporation",
8619                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8620                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8621                                 },
8622                         },
8623                         { }  /* terminating entry */
8624                 },
8625                 .hook = quirk_invert_brightness,
8626         },
8627 };
8628
8629 static struct intel_quirk intel_quirks[] = {
8630         /* HP Mini needs pipe A force quirk (LP: #322104) */
8631         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8632
8633         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8634         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8635
8636         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8637         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8638
8639         /* 830/845 need to leave pipe A & dpll A up */
8640         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8641         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8642
8643         /* Lenovo U160 cannot use SSC on LVDS */
8644         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8645
8646         /* Sony Vaio Y cannot use SSC on LVDS */
8647         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8648
8649         /* Acer Aspire 5734Z must invert backlight brightness */
8650         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8651 };
8652
8653 static void intel_init_quirks(struct drm_device *dev)
8654 {
8655         struct pci_dev *d = dev->pdev;
8656         int i;
8657
8658         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8659                 struct intel_quirk *q = &intel_quirks[i];
8660
8661                 if (d->device == q->device &&
8662                     (d->subsystem_vendor == q->subsystem_vendor ||
8663                      q->subsystem_vendor == PCI_ANY_ID) &&
8664                     (d->subsystem_device == q->subsystem_device ||
8665                      q->subsystem_device == PCI_ANY_ID))
8666                         q->hook(dev);
8667         }
8668         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8669                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8670                         intel_dmi_quirks[i].hook(dev);
8671         }
8672 }
8673
8674 /* Disable the VGA plane that we never use */
8675 static void i915_disable_vga(struct drm_device *dev)
8676 {
8677         struct drm_i915_private *dev_priv = dev->dev_private;
8678         u8 sr1;
8679         u32 vga_reg;
8680
8681         if (HAS_PCH_SPLIT(dev))
8682                 vga_reg = CPU_VGACNTRL;
8683         else
8684                 vga_reg = VGACNTRL;
8685
8686         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8687         outb(SR01, VGA_SR_INDEX);
8688         sr1 = inb(VGA_SR_DATA);
8689         outb(sr1 | 1<<5, VGA_SR_DATA);
8690         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8691         udelay(300);
8692
8693         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8694         POSTING_READ(vga_reg);
8695 }
8696
8697 void intel_modeset_init_hw(struct drm_device *dev)
8698 {
8699         /* We attempt to init the necessary power wells early in the initialization
8700          * time, so the subsystems that expect power to be enabled can work.
8701          */
8702         intel_init_power_wells(dev);
8703
8704         intel_prepare_ddi(dev);
8705
8706         intel_init_clock_gating(dev);
8707
8708         mutex_lock(&dev->struct_mutex);
8709         intel_enable_gt_powersave(dev);
8710         mutex_unlock(&dev->struct_mutex);
8711 }
8712
8713 void intel_modeset_init(struct drm_device *dev)
8714 {
8715         struct drm_i915_private *dev_priv = dev->dev_private;
8716         int i, ret;
8717
8718         drm_mode_config_init(dev);
8719
8720         dev->mode_config.min_width = 0;
8721         dev->mode_config.min_height = 0;
8722
8723         dev->mode_config.preferred_depth = 24;
8724         dev->mode_config.prefer_shadow = 1;
8725
8726         dev->mode_config.funcs = &intel_mode_funcs;
8727
8728         intel_init_quirks(dev);
8729
8730         intel_init_pm(dev);
8731
8732         intel_init_display(dev);
8733
8734         if (IS_GEN2(dev)) {
8735                 dev->mode_config.max_width = 2048;
8736                 dev->mode_config.max_height = 2048;
8737         } else if (IS_GEN3(dev)) {
8738                 dev->mode_config.max_width = 4096;
8739                 dev->mode_config.max_height = 4096;
8740         } else {
8741                 dev->mode_config.max_width = 8192;
8742                 dev->mode_config.max_height = 8192;
8743         }
8744         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8745
8746         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8747                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8748
8749         for (i = 0; i < dev_priv->num_pipe; i++) {
8750                 intel_crtc_init(dev, i);
8751                 ret = intel_plane_init(dev, i);
8752                 if (ret)
8753                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8754         }
8755
8756         intel_cpu_pll_init(dev);
8757         intel_pch_pll_init(dev);
8758
8759         /* Just disable it once at startup */
8760         i915_disable_vga(dev);
8761         intel_setup_outputs(dev);
8762 }
8763
8764 static void
8765 intel_connector_break_all_links(struct intel_connector *connector)
8766 {
8767         connector->base.dpms = DRM_MODE_DPMS_OFF;
8768         connector->base.encoder = NULL;
8769         connector->encoder->connectors_active = false;
8770         connector->encoder->base.crtc = NULL;
8771 }
8772
8773 static void intel_enable_pipe_a(struct drm_device *dev)
8774 {
8775         struct intel_connector *connector;
8776         struct drm_connector *crt = NULL;
8777         struct intel_load_detect_pipe load_detect_temp;
8778
8779         /* We can't just switch on the pipe A, we need to set things up with a
8780          * proper mode and output configuration. As a gross hack, enable pipe A
8781          * by enabling the load detect pipe once. */
8782         list_for_each_entry(connector,
8783                             &dev->mode_config.connector_list,
8784                             base.head) {
8785                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8786                         crt = &connector->base;
8787                         break;
8788                 }
8789         }
8790
8791         if (!crt)
8792                 return;
8793
8794         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8795                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8796
8797
8798 }
8799
8800 static bool
8801 intel_check_plane_mapping(struct intel_crtc *crtc)
8802 {
8803         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8804         u32 reg, val;
8805
8806         if (dev_priv->num_pipe == 1)
8807                 return true;
8808
8809         reg = DSPCNTR(!crtc->plane);
8810         val = I915_READ(reg);
8811
8812         if ((val & DISPLAY_PLANE_ENABLE) &&
8813             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8814                 return false;
8815
8816         return true;
8817 }
8818
8819 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8820 {
8821         struct drm_device *dev = crtc->base.dev;
8822         struct drm_i915_private *dev_priv = dev->dev_private;
8823         u32 reg;
8824
8825         /* Clear any frame start delays used for debugging left by the BIOS */
8826         reg = PIPECONF(crtc->cpu_transcoder);
8827         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8828
8829         /* We need to sanitize the plane -> pipe mapping first because this will
8830          * disable the crtc (and hence change the state) if it is wrong. Note
8831          * that gen4+ has a fixed plane -> pipe mapping.  */
8832         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8833                 struct intel_connector *connector;
8834                 bool plane;
8835
8836                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8837                               crtc->base.base.id);
8838
8839                 /* Pipe has the wrong plane attached and the plane is active.
8840                  * Temporarily change the plane mapping and disable everything
8841                  * ...  */
8842                 plane = crtc->plane;
8843                 crtc->plane = !plane;
8844                 dev_priv->display.crtc_disable(&crtc->base);
8845                 crtc->plane = plane;
8846
8847                 /* ... and break all links. */
8848                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8849                                     base.head) {
8850                         if (connector->encoder->base.crtc != &crtc->base)
8851                                 continue;
8852
8853                         intel_connector_break_all_links(connector);
8854                 }
8855
8856                 WARN_ON(crtc->active);
8857                 crtc->base.enabled = false;
8858         }
8859
8860         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8861             crtc->pipe == PIPE_A && !crtc->active) {
8862                 /* BIOS forgot to enable pipe A, this mostly happens after
8863                  * resume. Force-enable the pipe to fix this, the update_dpms
8864                  * call below we restore the pipe to the right state, but leave
8865                  * the required bits on. */
8866                 intel_enable_pipe_a(dev);
8867         }
8868
8869         /* Adjust the state of the output pipe according to whether we
8870          * have active connectors/encoders. */
8871         intel_crtc_update_dpms(&crtc->base);
8872
8873         if (crtc->active != crtc->base.enabled) {
8874                 struct intel_encoder *encoder;
8875
8876                 /* This can happen either due to bugs in the get_hw_state
8877                  * functions or because the pipe is force-enabled due to the
8878                  * pipe A quirk. */
8879                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8880                               crtc->base.base.id,
8881                               crtc->base.enabled ? "enabled" : "disabled",
8882                               crtc->active ? "enabled" : "disabled");
8883
8884                 crtc->base.enabled = crtc->active;
8885
8886                 /* Because we only establish the connector -> encoder ->
8887                  * crtc links if something is active, this means the
8888                  * crtc is now deactivated. Break the links. connector
8889                  * -> encoder links are only establish when things are
8890                  *  actually up, hence no need to break them. */
8891                 WARN_ON(crtc->active);
8892
8893                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8894                         WARN_ON(encoder->connectors_active);
8895                         encoder->base.crtc = NULL;
8896                 }
8897         }
8898 }
8899
8900 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8901 {
8902         struct intel_connector *connector;
8903         struct drm_device *dev = encoder->base.dev;
8904
8905         /* We need to check both for a crtc link (meaning that the
8906          * encoder is active and trying to read from a pipe) and the
8907          * pipe itself being active. */
8908         bool has_active_crtc = encoder->base.crtc &&
8909                 to_intel_crtc(encoder->base.crtc)->active;
8910
8911         if (encoder->connectors_active && !has_active_crtc) {
8912                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8913                               encoder->base.base.id,
8914                               drm_get_encoder_name(&encoder->base));
8915
8916                 /* Connector is active, but has no active pipe. This is
8917                  * fallout from our resume register restoring. Disable
8918                  * the encoder manually again. */
8919                 if (encoder->base.crtc) {
8920                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8921                                       encoder->base.base.id,
8922                                       drm_get_encoder_name(&encoder->base));
8923                         encoder->disable(encoder);
8924                 }
8925
8926                 /* Inconsistent output/port/pipe state happens presumably due to
8927                  * a bug in one of the get_hw_state functions. Or someplace else
8928                  * in our code, like the register restore mess on resume. Clamp
8929                  * things to off as a safer default. */
8930                 list_for_each_entry(connector,
8931                                     &dev->mode_config.connector_list,
8932                                     base.head) {
8933                         if (connector->encoder != encoder)
8934                                 continue;
8935
8936                         intel_connector_break_all_links(connector);
8937                 }
8938         }
8939         /* Enabled encoders without active connectors will be fixed in
8940          * the crtc fixup. */
8941 }
8942
8943 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8944  * and i915 state tracking structures. */
8945 void intel_modeset_setup_hw_state(struct drm_device *dev,
8946                                   bool force_restore)
8947 {
8948         struct drm_i915_private *dev_priv = dev->dev_private;
8949         enum pipe pipe;
8950         u32 tmp;
8951         struct intel_crtc *crtc;
8952         struct intel_encoder *encoder;
8953         struct intel_connector *connector;
8954
8955         if (IS_HASWELL(dev)) {
8956                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8957
8958                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8959                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8960                         case TRANS_DDI_EDP_INPUT_A_ON:
8961                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8962                                 pipe = PIPE_A;
8963                                 break;
8964                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8965                                 pipe = PIPE_B;
8966                                 break;
8967                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8968                                 pipe = PIPE_C;
8969                                 break;
8970                         }
8971
8972                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8973                         crtc->cpu_transcoder = TRANSCODER_EDP;
8974
8975                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8976                                       pipe_name(pipe));
8977                 }
8978         }
8979
8980         for_each_pipe(pipe) {
8981                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8982
8983                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8984                 if (tmp & PIPECONF_ENABLE)
8985                         crtc->active = true;
8986                 else
8987                         crtc->active = false;
8988
8989                 crtc->base.enabled = crtc->active;
8990
8991                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8992                               crtc->base.base.id,
8993                               crtc->active ? "enabled" : "disabled");
8994         }
8995
8996         if (IS_HASWELL(dev))
8997                 intel_ddi_setup_hw_pll_state(dev);
8998
8999         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9000                             base.head) {
9001                 pipe = 0;
9002
9003                 if (encoder->get_hw_state(encoder, &pipe)) {
9004                         encoder->base.crtc =
9005                                 dev_priv->pipe_to_crtc_mapping[pipe];
9006                 } else {
9007                         encoder->base.crtc = NULL;
9008                 }
9009
9010                 encoder->connectors_active = false;
9011                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9012                               encoder->base.base.id,
9013                               drm_get_encoder_name(&encoder->base),
9014                               encoder->base.crtc ? "enabled" : "disabled",
9015                               pipe);
9016         }
9017
9018         list_for_each_entry(connector, &dev->mode_config.connector_list,
9019                             base.head) {
9020                 if (connector->get_hw_state(connector)) {
9021                         connector->base.dpms = DRM_MODE_DPMS_ON;
9022                         connector->encoder->connectors_active = true;
9023                         connector->base.encoder = &connector->encoder->base;
9024                 } else {
9025                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9026                         connector->base.encoder = NULL;
9027                 }
9028                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9029                               connector->base.base.id,
9030                               drm_get_connector_name(&connector->base),
9031                               connector->base.encoder ? "enabled" : "disabled");
9032         }
9033
9034         /* HW state is read out, now we need to sanitize this mess. */
9035         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9036                             base.head) {
9037                 intel_sanitize_encoder(encoder);
9038         }
9039
9040         for_each_pipe(pipe) {
9041                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9042                 intel_sanitize_crtc(crtc);
9043         }
9044
9045         if (force_restore) {
9046                 for_each_pipe(pipe) {
9047                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9048                         intel_set_mode(&crtc->base, &crtc->base.mode,
9049                                        crtc->base.x, crtc->base.y, crtc->base.fb);
9050                 }
9051         } else {
9052                 intel_modeset_update_staged_output_state(dev);
9053         }
9054
9055         intel_modeset_check_state(dev);
9056
9057         drm_mode_config_reset(dev);
9058 }
9059
9060 void intel_modeset_gem_init(struct drm_device *dev)
9061 {
9062         intel_modeset_init_hw(dev);
9063
9064         intel_setup_overlay(dev);
9065
9066         intel_modeset_setup_hw_state(dev, false);
9067 }
9068
9069 void intel_modeset_cleanup(struct drm_device *dev)
9070 {
9071         struct drm_i915_private *dev_priv = dev->dev_private;
9072         struct drm_crtc *crtc;
9073         struct intel_crtc *intel_crtc;
9074
9075         drm_kms_helper_poll_fini(dev);
9076         mutex_lock(&dev->struct_mutex);
9077
9078         intel_unregister_dsm_handler();
9079
9080
9081         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9082                 /* Skip inactive CRTCs */
9083                 if (!crtc->fb)
9084                         continue;
9085
9086                 intel_crtc = to_intel_crtc(crtc);
9087                 intel_increase_pllclock(crtc);
9088         }
9089
9090         intel_disable_fbc(dev);
9091
9092         intel_disable_gt_powersave(dev);
9093
9094         ironlake_teardown_rc6(dev);
9095
9096         if (IS_VALLEYVIEW(dev))
9097                 vlv_init_dpio(dev);
9098
9099         mutex_unlock(&dev->struct_mutex);
9100
9101         /* Disable the irq before mode object teardown, for the irq might
9102          * enqueue unpin/hotplug work. */
9103         drm_irq_uninstall(dev);
9104         cancel_work_sync(&dev_priv->hotplug_work);
9105         cancel_work_sync(&dev_priv->rps.work);
9106
9107         /* flush any delayed tasks or pending work */
9108         flush_scheduled_work();
9109
9110         drm_mode_config_cleanup(dev);
9111 }
9112
9113 /*
9114  * Return which encoder is currently attached for connector.
9115  */
9116 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9117 {
9118         return &intel_attached_encoder(connector)->base;
9119 }
9120
9121 void intel_connector_attach_encoder(struct intel_connector *connector,
9122                                     struct intel_encoder *encoder)
9123 {
9124         connector->encoder = encoder;
9125         drm_mode_connector_attach_encoder(&connector->base,
9126                                           &encoder->base);
9127 }
9128
9129 /*
9130  * set vga decode state - true == enable VGA decode
9131  */
9132 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9133 {
9134         struct drm_i915_private *dev_priv = dev->dev_private;
9135         u16 gmch_ctrl;
9136
9137         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9138         if (state)
9139                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9140         else
9141                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9142         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9143         return 0;
9144 }
9145
9146 #ifdef CONFIG_DEBUG_FS
9147 #include <linux/seq_file.h>
9148
9149 struct intel_display_error_state {
9150         struct intel_cursor_error_state {
9151                 u32 control;
9152                 u32 position;
9153                 u32 base;
9154                 u32 size;
9155         } cursor[I915_MAX_PIPES];
9156
9157         struct intel_pipe_error_state {
9158                 u32 conf;
9159                 u32 source;
9160
9161                 u32 htotal;
9162                 u32 hblank;
9163                 u32 hsync;
9164                 u32 vtotal;
9165                 u32 vblank;
9166                 u32 vsync;
9167         } pipe[I915_MAX_PIPES];
9168
9169         struct intel_plane_error_state {
9170                 u32 control;
9171                 u32 stride;
9172                 u32 size;
9173                 u32 pos;
9174                 u32 addr;
9175                 u32 surface;
9176                 u32 tile_offset;
9177         } plane[I915_MAX_PIPES];
9178 };
9179
9180 struct intel_display_error_state *
9181 intel_display_capture_error_state(struct drm_device *dev)
9182 {
9183         drm_i915_private_t *dev_priv = dev->dev_private;
9184         struct intel_display_error_state *error;
9185         enum transcoder cpu_transcoder;
9186         int i;
9187
9188         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9189         if (error == NULL)
9190                 return NULL;
9191
9192         for_each_pipe(i) {
9193                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9194
9195                 error->cursor[i].control = I915_READ(CURCNTR(i));
9196                 error->cursor[i].position = I915_READ(CURPOS(i));
9197                 error->cursor[i].base = I915_READ(CURBASE(i));
9198
9199                 error->plane[i].control = I915_READ(DSPCNTR(i));
9200                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9201                 error->plane[i].size = I915_READ(DSPSIZE(i));
9202                 error->plane[i].pos = I915_READ(DSPPOS(i));
9203                 error->plane[i].addr = I915_READ(DSPADDR(i));
9204                 if (INTEL_INFO(dev)->gen >= 4) {
9205                         error->plane[i].surface = I915_READ(DSPSURF(i));
9206                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9207                 }
9208
9209                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9210                 error->pipe[i].source = I915_READ(PIPESRC(i));
9211                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9212                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9213                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9214                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9215                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9216                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9217         }
9218
9219         return error;
9220 }
9221
9222 void
9223 intel_display_print_error_state(struct seq_file *m,
9224                                 struct drm_device *dev,
9225                                 struct intel_display_error_state *error)
9226 {
9227         drm_i915_private_t *dev_priv = dev->dev_private;
9228         int i;
9229
9230         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9231         for_each_pipe(i) {
9232                 seq_printf(m, "Pipe [%d]:\n", i);
9233                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9234                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9235                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9236                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9237                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9238                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9239                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9240                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9241
9242                 seq_printf(m, "Plane [%d]:\n", i);
9243                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9244                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9245                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9246                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9247                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9248                 if (INTEL_INFO(dev)->gen >= 4) {
9249                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9250                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9251                 }
9252
9253                 seq_printf(m, "Cursor [%d]:\n", i);
9254                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9255                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9256                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9257         }
9258 }
9259 #endif