]> Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c
drm/i915: make the panel fitter work on pipes B and C on IVB
[~andy/linux] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Eric Anholt <eric@anholt.net>
25  */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49         /* given values */
50         int n;
51         int m1, m2;
52         int p1, p2;
53         /* derived values */
54         int     dot;
55         int     vco;
56         int     m;
57         int     p;
58 } intel_clock_t;
59
60 typedef struct {
61         int     min, max;
62 } intel_range_t;
63
64 typedef struct {
65         int     dot_limit;
66         int     p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM                  2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
73         intel_p2_t          p2;
74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75                         int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84         struct drm_i915_private *dev_priv = dev->dev_private;
85
86         WARN_ON(!HAS_PCH_SPLIT(dev));
87
88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93                     int target, int refclk, intel_clock_t *match_clock,
94                     intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97                         int target, int refclk, intel_clock_t *match_clock,
98                         intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102                       int target, int refclk, intel_clock_t *match_clock,
103                       intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106                            int target, int refclk, intel_clock_t *match_clock,
107                            intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111                         int target, int refclk, intel_clock_t *match_clock,
112                         intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117         if (IS_GEN5(dev)) {
118                 struct drm_i915_private *dev_priv = dev->dev_private;
119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120         } else
121                 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125         .dot = { .min = 25000, .max = 350000 },
126         .vco = { .min = 930000, .max = 1400000 },
127         .n = { .min = 3, .max = 16 },
128         .m = { .min = 96, .max = 140 },
129         .m1 = { .min = 18, .max = 26 },
130         .m2 = { .min = 6, .max = 16 },
131         .p = { .min = 4, .max = 128 },
132         .p1 = { .min = 2, .max = 33 },
133         .p2 = { .dot_limit = 165000,
134                 .p2_slow = 4, .p2_fast = 2 },
135         .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139         .dot = { .min = 25000, .max = 350000 },
140         .vco = { .min = 930000, .max = 1400000 },
141         .n = { .min = 3, .max = 16 },
142         .m = { .min = 96, .max = 140 },
143         .m1 = { .min = 18, .max = 26 },
144         .m2 = { .min = 6, .max = 16 },
145         .p = { .min = 4, .max = 128 },
146         .p1 = { .min = 1, .max = 6 },
147         .p2 = { .dot_limit = 165000,
148                 .p2_slow = 14, .p2_fast = 7 },
149         .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153         .dot = { .min = 20000, .max = 400000 },
154         .vco = { .min = 1400000, .max = 2800000 },
155         .n = { .min = 1, .max = 6 },
156         .m = { .min = 70, .max = 120 },
157         .m1 = { .min = 10, .max = 22 },
158         .m2 = { .min = 5, .max = 9 },
159         .p = { .min = 5, .max = 80 },
160         .p1 = { .min = 1, .max = 8 },
161         .p2 = { .dot_limit = 200000,
162                 .p2_slow = 10, .p2_fast = 5 },
163         .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167         .dot = { .min = 20000, .max = 400000 },
168         .vco = { .min = 1400000, .max = 2800000 },
169         .n = { .min = 1, .max = 6 },
170         .m = { .min = 70, .max = 120 },
171         .m1 = { .min = 10, .max = 22 },
172         .m2 = { .min = 5, .max = 9 },
173         .p = { .min = 7, .max = 98 },
174         .p1 = { .min = 1, .max = 8 },
175         .p2 = { .dot_limit = 112000,
176                 .p2_slow = 14, .p2_fast = 7 },
177         .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182         .dot = { .min = 25000, .max = 270000 },
183         .vco = { .min = 1750000, .max = 3500000},
184         .n = { .min = 1, .max = 4 },
185         .m = { .min = 104, .max = 138 },
186         .m1 = { .min = 17, .max = 23 },
187         .m2 = { .min = 5, .max = 11 },
188         .p = { .min = 10, .max = 30 },
189         .p1 = { .min = 1, .max = 3},
190         .p2 = { .dot_limit = 270000,
191                 .p2_slow = 10,
192                 .p2_fast = 10
193         },
194         .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198         .dot = { .min = 22000, .max = 400000 },
199         .vco = { .min = 1750000, .max = 3500000},
200         .n = { .min = 1, .max = 4 },
201         .m = { .min = 104, .max = 138 },
202         .m1 = { .min = 16, .max = 23 },
203         .m2 = { .min = 5, .max = 11 },
204         .p = { .min = 5, .max = 80 },
205         .p1 = { .min = 1, .max = 8},
206         .p2 = { .dot_limit = 165000,
207                 .p2_slow = 10, .p2_fast = 5 },
208         .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212         .dot = { .min = 20000, .max = 115000 },
213         .vco = { .min = 1750000, .max = 3500000 },
214         .n = { .min = 1, .max = 3 },
215         .m = { .min = 104, .max = 138 },
216         .m1 = { .min = 17, .max = 23 },
217         .m2 = { .min = 5, .max = 11 },
218         .p = { .min = 28, .max = 112 },
219         .p1 = { .min = 2, .max = 8 },
220         .p2 = { .dot_limit = 0,
221                 .p2_slow = 14, .p2_fast = 14
222         },
223         .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227         .dot = { .min = 80000, .max = 224000 },
228         .vco = { .min = 1750000, .max = 3500000 },
229         .n = { .min = 1, .max = 3 },
230         .m = { .min = 104, .max = 138 },
231         .m1 = { .min = 17, .max = 23 },
232         .m2 = { .min = 5, .max = 11 },
233         .p = { .min = 14, .max = 42 },
234         .p1 = { .min = 2, .max = 6 },
235         .p2 = { .dot_limit = 0,
236                 .p2_slow = 7, .p2_fast = 7
237         },
238         .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242         .dot = { .min = 161670, .max = 227000 },
243         .vco = { .min = 1750000, .max = 3500000},
244         .n = { .min = 1, .max = 2 },
245         .m = { .min = 97, .max = 108 },
246         .m1 = { .min = 0x10, .max = 0x12 },
247         .m2 = { .min = 0x05, .max = 0x06 },
248         .p = { .min = 10, .max = 20 },
249         .p1 = { .min = 1, .max = 2},
250         .p2 = { .dot_limit = 0,
251                 .p2_slow = 10, .p2_fast = 10 },
252         .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256         .dot = { .min = 20000, .max = 400000},
257         .vco = { .min = 1700000, .max = 3500000 },
258         /* Pineview's Ncounter is a ring counter */
259         .n = { .min = 3, .max = 6 },
260         .m = { .min = 2, .max = 256 },
261         /* Pineview only has one combined m divider, which we treat as m2. */
262         .m1 = { .min = 0, .max = 0 },
263         .m2 = { .min = 0, .max = 254 },
264         .p = { .min = 5, .max = 80 },
265         .p1 = { .min = 1, .max = 8 },
266         .p2 = { .dot_limit = 200000,
267                 .p2_slow = 10, .p2_fast = 5 },
268         .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272         .dot = { .min = 20000, .max = 400000 },
273         .vco = { .min = 1700000, .max = 3500000 },
274         .n = { .min = 3, .max = 6 },
275         .m = { .min = 2, .max = 256 },
276         .m1 = { .min = 0, .max = 0 },
277         .m2 = { .min = 0, .max = 254 },
278         .p = { .min = 7, .max = 112 },
279         .p1 = { .min = 1, .max = 8 },
280         .p2 = { .dot_limit = 112000,
281                 .p2_slow = 14, .p2_fast = 14 },
282         .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286  *
287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
288  * the range value for them is (actual_value - 2).
289  */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291         .dot = { .min = 25000, .max = 350000 },
292         .vco = { .min = 1760000, .max = 3510000 },
293         .n = { .min = 1, .max = 5 },
294         .m = { .min = 79, .max = 127 },
295         .m1 = { .min = 12, .max = 22 },
296         .m2 = { .min = 5, .max = 9 },
297         .p = { .min = 5, .max = 80 },
298         .p1 = { .min = 1, .max = 8 },
299         .p2 = { .dot_limit = 225000,
300                 .p2_slow = 10, .p2_fast = 5 },
301         .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305         .dot = { .min = 25000, .max = 350000 },
306         .vco = { .min = 1760000, .max = 3510000 },
307         .n = { .min = 1, .max = 3 },
308         .m = { .min = 79, .max = 118 },
309         .m1 = { .min = 12, .max = 22 },
310         .m2 = { .min = 5, .max = 9 },
311         .p = { .min = 28, .max = 112 },
312         .p1 = { .min = 2, .max = 8 },
313         .p2 = { .dot_limit = 225000,
314                 .p2_slow = 14, .p2_fast = 14 },
315         .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319         .dot = { .min = 25000, .max = 350000 },
320         .vco = { .min = 1760000, .max = 3510000 },
321         .n = { .min = 1, .max = 3 },
322         .m = { .min = 79, .max = 127 },
323         .m1 = { .min = 12, .max = 22 },
324         .m2 = { .min = 5, .max = 9 },
325         .p = { .min = 14, .max = 56 },
326         .p1 = { .min = 2, .max = 8 },
327         .p2 = { .dot_limit = 225000,
328                 .p2_slow = 7, .p2_fast = 7 },
329         .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334         .dot = { .min = 25000, .max = 350000 },
335         .vco = { .min = 1760000, .max = 3510000 },
336         .n = { .min = 1, .max = 2 },
337         .m = { .min = 79, .max = 126 },
338         .m1 = { .min = 12, .max = 22 },
339         .m2 = { .min = 5, .max = 9 },
340         .p = { .min = 28, .max = 112 },
341         .p1 = { .min = 2, .max = 8 },
342         .p2 = { .dot_limit = 225000,
343                 .p2_slow = 14, .p2_fast = 14 },
344         .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348         .dot = { .min = 25000, .max = 350000 },
349         .vco = { .min = 1760000, .max = 3510000 },
350         .n = { .min = 1, .max = 3 },
351         .m = { .min = 79, .max = 126 },
352         .m1 = { .min = 12, .max = 22 },
353         .m2 = { .min = 5, .max = 9 },
354         .p = { .min = 14, .max = 42 },
355         .p1 = { .min = 2, .max = 6 },
356         .p2 = { .dot_limit = 225000,
357                 .p2_slow = 7, .p2_fast = 7 },
358         .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362         .dot = { .min = 25000, .max = 350000 },
363         .vco = { .min = 1760000, .max = 3510000},
364         .n = { .min = 1, .max = 2 },
365         .m = { .min = 81, .max = 90 },
366         .m1 = { .min = 12, .max = 22 },
367         .m2 = { .min = 5, .max = 9 },
368         .p = { .min = 10, .max = 20 },
369         .p1 = { .min = 1, .max = 2},
370         .p2 = { .dot_limit = 0,
371                 .p2_slow = 10, .p2_fast = 10 },
372         .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376         .dot = { .min = 25000, .max = 270000 },
377         .vco = { .min = 4000000, .max = 6000000 },
378         .n = { .min = 1, .max = 7 },
379         .m = { .min = 22, .max = 450 }, /* guess */
380         .m1 = { .min = 2, .max = 3 },
381         .m2 = { .min = 11, .max = 156 },
382         .p = { .min = 10, .max = 30 },
383         .p1 = { .min = 2, .max = 3 },
384         .p2 = { .dot_limit = 270000,
385                 .p2_slow = 2, .p2_fast = 20 },
386         .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390         .dot = { .min = 20000, .max = 165000 },
391         .vco = { .min = 4000000, .max = 5994000},
392         .n = { .min = 1, .max = 7 },
393         .m = { .min = 60, .max = 300 }, /* guess */
394         .m1 = { .min = 2, .max = 3 },
395         .m2 = { .min = 11, .max = 156 },
396         .p = { .min = 10, .max = 30 },
397         .p1 = { .min = 2, .max = 3 },
398         .p2 = { .dot_limit = 270000,
399                 .p2_slow = 2, .p2_fast = 20 },
400         .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404         .dot = { .min = 25000, .max = 270000 },
405         .vco = { .min = 4000000, .max = 6000000 },
406         .n = { .min = 1, .max = 7 },
407         .m = { .min = 22, .max = 450 },
408         .m1 = { .min = 2, .max = 3 },
409         .m2 = { .min = 11, .max = 156 },
410         .p = { .min = 10, .max = 30 },
411         .p1 = { .min = 2, .max = 3 },
412         .p2 = { .dot_limit = 270000,
413                 .p2_slow = 2, .p2_fast = 20 },
414         .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419         unsigned long flags;
420         u32 val = 0;
421
422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424                 DRM_ERROR("DPIO idle wait timed out\n");
425                 goto out_unlock;
426         }
427
428         I915_WRITE(DPIO_REG, reg);
429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430                    DPIO_BYTE);
431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432                 DRM_ERROR("DPIO read wait timed out\n");
433                 goto out_unlock;
434         }
435         val = I915_READ(DPIO_DATA);
436
437 out_unlock:
438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439         return val;
440 }
441
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443                              u32 val)
444 {
445         unsigned long flags;
446
447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449                 DRM_ERROR("DPIO idle wait timed out\n");
450                 goto out_unlock;
451         }
452
453         I915_WRITE(DPIO_DATA, val);
454         I915_WRITE(DPIO_REG, reg);
455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456                    DPIO_BYTE);
457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458                 DRM_ERROR("DPIO write wait timed out\n");
459
460 out_unlock:
461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462 }
463
464 static void vlv_init_dpio(struct drm_device *dev)
465 {
466         struct drm_i915_private *dev_priv = dev->dev_private;
467
468         /* Reset the DPIO config */
469         I915_WRITE(DPIO_CTL, 0);
470         POSTING_READ(DPIO_CTL);
471         I915_WRITE(DPIO_CTL, 1);
472         POSTING_READ(DPIO_CTL);
473 }
474
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476 {
477         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478         return 1;
479 }
480
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
482         {
483                 .callback = intel_dual_link_lvds_callback,
484                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485                 .matches = {
486                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488                 },
489         },
490         { }     /* terminating entry */
491 };
492
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494                               unsigned int reg)
495 {
496         unsigned int val;
497
498         /* use the module option value if specified */
499         if (i915_lvds_channel_mode > 0)
500                 return i915_lvds_channel_mode == 2;
501
502         if (dmi_check_system(intel_dual_link_lvds))
503                 return true;
504
505         if (dev_priv->lvds_val)
506                 val = dev_priv->lvds_val;
507         else {
508                 /* BIOS should set the proper LVDS register value at boot, but
509                  * in reality, it doesn't set the value when the lid is closed;
510                  * we need to check "the value to be set" in VBT when LVDS
511                  * register is uninitialized.
512                  */
513                 val = I915_READ(reg);
514                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515                         val = dev_priv->bios_lvds_val;
516                 dev_priv->lvds_val = val;
517         }
518         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519 }
520
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522                                                 int refclk)
523 {
524         struct drm_device *dev = crtc->dev;
525         struct drm_i915_private *dev_priv = dev->dev_private;
526         const intel_limit_t *limit;
527
528         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530                         /* LVDS dual channel */
531                         if (refclk == 100000)
532                                 limit = &intel_limits_ironlake_dual_lvds_100m;
533                         else
534                                 limit = &intel_limits_ironlake_dual_lvds;
535                 } else {
536                         if (refclk == 100000)
537                                 limit = &intel_limits_ironlake_single_lvds_100m;
538                         else
539                                 limit = &intel_limits_ironlake_single_lvds;
540                 }
541         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543                 limit = &intel_limits_ironlake_display_port;
544         else
545                 limit = &intel_limits_ironlake_dac;
546
547         return limit;
548 }
549
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551 {
552         struct drm_device *dev = crtc->dev;
553         struct drm_i915_private *dev_priv = dev->dev_private;
554         const intel_limit_t *limit;
555
556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557                 if (is_dual_link_lvds(dev_priv, LVDS))
558                         /* LVDS with dual channel */
559                         limit = &intel_limits_g4x_dual_channel_lvds;
560                 else
561                         /* LVDS with dual channel */
562                         limit = &intel_limits_g4x_single_channel_lvds;
563         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565                 limit = &intel_limits_g4x_hdmi;
566         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567                 limit = &intel_limits_g4x_sdvo;
568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569                 limit = &intel_limits_g4x_display_port;
570         } else /* The option is for other outputs */
571                 limit = &intel_limits_i9xx_sdvo;
572
573         return limit;
574 }
575
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
577 {
578         struct drm_device *dev = crtc->dev;
579         const intel_limit_t *limit;
580
581         if (HAS_PCH_SPLIT(dev))
582                 limit = intel_ironlake_limit(crtc, refclk);
583         else if (IS_G4X(dev)) {
584                 limit = intel_g4x_limit(crtc);
585         } else if (IS_PINEVIEW(dev)) {
586                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587                         limit = &intel_limits_pineview_lvds;
588                 else
589                         limit = &intel_limits_pineview_sdvo;
590         } else if (IS_VALLEYVIEW(dev)) {
591                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592                         limit = &intel_limits_vlv_dac;
593                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594                         limit = &intel_limits_vlv_hdmi;
595                 else
596                         limit = &intel_limits_vlv_dp;
597         } else if (!IS_GEN2(dev)) {
598                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599                         limit = &intel_limits_i9xx_lvds;
600                 else
601                         limit = &intel_limits_i9xx_sdvo;
602         } else {
603                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604                         limit = &intel_limits_i8xx_lvds;
605                 else
606                         limit = &intel_limits_i8xx_dvo;
607         }
608         return limit;
609 }
610
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
613 {
614         clock->m = clock->m2 + 2;
615         clock->p = clock->p1 * clock->p2;
616         clock->vco = refclk * clock->m / clock->n;
617         clock->dot = clock->vco / clock->p;
618 }
619
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621 {
622         if (IS_PINEVIEW(dev)) {
623                 pineview_clock(refclk, clock);
624                 return;
625         }
626         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627         clock->p = clock->p1 * clock->p2;
628         clock->vco = refclk * clock->m / (clock->n + 2);
629         clock->dot = clock->vco / clock->p;
630 }
631
632 /**
633  * Returns whether any output on the specified pipe is of the specified type
634  */
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
636 {
637         struct drm_device *dev = crtc->dev;
638         struct intel_encoder *encoder;
639
640         for_each_encoder_on_crtc(dev, crtc, encoder)
641                 if (encoder->type == type)
642                         return true;
643
644         return false;
645 }
646
647 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
648 /**
649  * Returns whether the given set of divisors are valid for a given refclk with
650  * the given connectors.
651  */
652
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654                                const intel_limit_t *limit,
655                                const intel_clock_t *clock)
656 {
657         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
658                 INTELPllInvalid("p1 out of range\n");
659         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
660                 INTELPllInvalid("p out of range\n");
661         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
662                 INTELPllInvalid("m2 out of range\n");
663         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
664                 INTELPllInvalid("m1 out of range\n");
665         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666                 INTELPllInvalid("m1 <= m2\n");
667         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
668                 INTELPllInvalid("m out of range\n");
669         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
670                 INTELPllInvalid("n out of range\n");
671         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672                 INTELPllInvalid("vco out of range\n");
673         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674          * connector, etc., rather than just a single range.
675          */
676         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677                 INTELPllInvalid("dot out of range\n");
678
679         return true;
680 }
681
682 static bool
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684                     int target, int refclk, intel_clock_t *match_clock,
685                     intel_clock_t *best_clock)
686
687 {
688         struct drm_device *dev = crtc->dev;
689         struct drm_i915_private *dev_priv = dev->dev_private;
690         intel_clock_t clock;
691         int err = target;
692
693         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694             (I915_READ(LVDS)) != 0) {
695                 /*
696                  * For LVDS, if the panel is on, just rely on its current
697                  * settings for dual-channel.  We haven't figured out how to
698                  * reliably set up different single/dual channel state, if we
699                  * even can.
700                  */
701                 if (is_dual_link_lvds(dev_priv, LVDS))
702                         clock.p2 = limit->p2.p2_fast;
703                 else
704                         clock.p2 = limit->p2.p2_slow;
705         } else {
706                 if (target < limit->p2.dot_limit)
707                         clock.p2 = limit->p2.p2_slow;
708                 else
709                         clock.p2 = limit->p2.p2_fast;
710         }
711
712         memset(best_clock, 0, sizeof(*best_clock));
713
714         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715              clock.m1++) {
716                 for (clock.m2 = limit->m2.min;
717                      clock.m2 <= limit->m2.max; clock.m2++) {
718                         /* m1 is always 0 in Pineview */
719                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
720                                 break;
721                         for (clock.n = limit->n.min;
722                              clock.n <= limit->n.max; clock.n++) {
723                                 for (clock.p1 = limit->p1.min;
724                                         clock.p1 <= limit->p1.max; clock.p1++) {
725                                         int this_err;
726
727                                         intel_clock(dev, refclk, &clock);
728                                         if (!intel_PLL_is_valid(dev, limit,
729                                                                 &clock))
730                                                 continue;
731                                         if (match_clock &&
732                                             clock.p != match_clock->p)
733                                                 continue;
734
735                                         this_err = abs(clock.dot - target);
736                                         if (this_err < err) {
737                                                 *best_clock = clock;
738                                                 err = this_err;
739                                         }
740                                 }
741                         }
742                 }
743         }
744
745         return (err != target);
746 }
747
748 static bool
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750                         int target, int refclk, intel_clock_t *match_clock,
751                         intel_clock_t *best_clock)
752 {
753         struct drm_device *dev = crtc->dev;
754         struct drm_i915_private *dev_priv = dev->dev_private;
755         intel_clock_t clock;
756         int max_n;
757         bool found;
758         /* approximately equals target * 0.00585 */
759         int err_most = (target >> 8) + (target >> 9);
760         found = false;
761
762         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
763                 int lvds_reg;
764
765                 if (HAS_PCH_SPLIT(dev))
766                         lvds_reg = PCH_LVDS;
767                 else
768                         lvds_reg = LVDS;
769                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
770                     LVDS_CLKB_POWER_UP)
771                         clock.p2 = limit->p2.p2_fast;
772                 else
773                         clock.p2 = limit->p2.p2_slow;
774         } else {
775                 if (target < limit->p2.dot_limit)
776                         clock.p2 = limit->p2.p2_slow;
777                 else
778                         clock.p2 = limit->p2.p2_fast;
779         }
780
781         memset(best_clock, 0, sizeof(*best_clock));
782         max_n = limit->n.max;
783         /* based on hardware requirement, prefer smaller n to precision */
784         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785                 /* based on hardware requirement, prefere larger m1,m2 */
786                 for (clock.m1 = limit->m1.max;
787                      clock.m1 >= limit->m1.min; clock.m1--) {
788                         for (clock.m2 = limit->m2.max;
789                              clock.m2 >= limit->m2.min; clock.m2--) {
790                                 for (clock.p1 = limit->p1.max;
791                                      clock.p1 >= limit->p1.min; clock.p1--) {
792                                         int this_err;
793
794                                         intel_clock(dev, refclk, &clock);
795                                         if (!intel_PLL_is_valid(dev, limit,
796                                                                 &clock))
797                                                 continue;
798                                         if (match_clock &&
799                                             clock.p != match_clock->p)
800                                                 continue;
801
802                                         this_err = abs(clock.dot - target);
803                                         if (this_err < err_most) {
804                                                 *best_clock = clock;
805                                                 err_most = this_err;
806                                                 max_n = clock.n;
807                                                 found = true;
808                                         }
809                                 }
810                         }
811                 }
812         }
813         return found;
814 }
815
816 static bool
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818                            int target, int refclk, intel_clock_t *match_clock,
819                            intel_clock_t *best_clock)
820 {
821         struct drm_device *dev = crtc->dev;
822         intel_clock_t clock;
823
824         if (target < 200000) {
825                 clock.n = 1;
826                 clock.p1 = 2;
827                 clock.p2 = 10;
828                 clock.m1 = 12;
829                 clock.m2 = 9;
830         } else {
831                 clock.n = 2;
832                 clock.p1 = 1;
833                 clock.p2 = 10;
834                 clock.m1 = 14;
835                 clock.m2 = 8;
836         }
837         intel_clock(dev, refclk, &clock);
838         memcpy(best_clock, &clock, sizeof(intel_clock_t));
839         return true;
840 }
841
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
843 static bool
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845                       int target, int refclk, intel_clock_t *match_clock,
846                       intel_clock_t *best_clock)
847 {
848         intel_clock_t clock;
849         if (target < 200000) {
850                 clock.p1 = 2;
851                 clock.p2 = 10;
852                 clock.n = 2;
853                 clock.m1 = 23;
854                 clock.m2 = 8;
855         } else {
856                 clock.p1 = 1;
857                 clock.p2 = 10;
858                 clock.n = 1;
859                 clock.m1 = 14;
860                 clock.m2 = 2;
861         }
862         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863         clock.p = (clock.p1 * clock.p2);
864         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865         clock.vco = 0;
866         memcpy(best_clock, &clock, sizeof(intel_clock_t));
867         return true;
868 }
869 static bool
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871                         int target, int refclk, intel_clock_t *match_clock,
872                         intel_clock_t *best_clock)
873 {
874         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875         u32 m, n, fastclk;
876         u32 updrate, minupdate, fracbits, p;
877         unsigned long bestppm, ppm, absppm;
878         int dotclk, flag;
879
880         flag = 0;
881         dotclk = target * 1000;
882         bestppm = 1000000;
883         ppm = absppm = 0;
884         fastclk = dotclk / (2*100);
885         updrate = 0;
886         minupdate = 19200;
887         fracbits = 1;
888         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889         bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891         /* based on hardware requirement, prefer smaller n to precision */
892         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893                 updrate = refclk / n;
894                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896                                 if (p2 > 10)
897                                         p2 = p2 - 1;
898                                 p = p1 * p2;
899                                 /* based on hardware requirement, prefer bigger m1,m2 values */
900                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901                                         m2 = (((2*(fastclk * p * n / m1 )) +
902                                                refclk) / (2*refclk));
903                                         m = m1 * m2;
904                                         vco = updrate * m;
905                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
906                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907                                                 absppm = (ppm > 0) ? ppm : (-ppm);
908                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909                                                         bestppm = 0;
910                                                         flag = 1;
911                                                 }
912                                                 if (absppm < bestppm - 10) {
913                                                         bestppm = absppm;
914                                                         flag = 1;
915                                                 }
916                                                 if (flag) {
917                                                         bestn = n;
918                                                         bestm1 = m1;
919                                                         bestm2 = m2;
920                                                         bestp1 = p1;
921                                                         bestp2 = p2;
922                                                         flag = 0;
923                                                 }
924                                         }
925                                 }
926                         }
927                 }
928         }
929         best_clock->n = bestn;
930         best_clock->m1 = bestm1;
931         best_clock->m2 = bestm2;
932         best_clock->p1 = bestp1;
933         best_clock->p2 = bestp2;
934
935         return true;
936 }
937
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939                                              enum pipe pipe)
940 {
941         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944         return intel_crtc->cpu_transcoder;
945 }
946
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948 {
949         struct drm_i915_private *dev_priv = dev->dev_private;
950         u32 frame, frame_reg = PIPEFRAME(pipe);
951
952         frame = I915_READ(frame_reg);
953
954         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955                 DRM_DEBUG_KMS("vblank wait timed out\n");
956 }
957
958 /**
959  * intel_wait_for_vblank - wait for vblank on a given pipe
960  * @dev: drm device
961  * @pipe: pipe to wait for
962  *
963  * Wait for vblank to occur on a given pipe.  Needed for various bits of
964  * mode setting code.
965  */
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
967 {
968         struct drm_i915_private *dev_priv = dev->dev_private;
969         int pipestat_reg = PIPESTAT(pipe);
970
971         if (INTEL_INFO(dev)->gen >= 5) {
972                 ironlake_wait_for_vblank(dev, pipe);
973                 return;
974         }
975
976         /* Clear existing vblank status. Note this will clear any other
977          * sticky status fields as well.
978          *
979          * This races with i915_driver_irq_handler() with the result
980          * that either function could miss a vblank event.  Here it is not
981          * fatal, as we will either wait upon the next vblank interrupt or
982          * timeout.  Generally speaking intel_wait_for_vblank() is only
983          * called during modeset at which time the GPU should be idle and
984          * should *not* be performing page flips and thus not waiting on
985          * vblanks...
986          * Currently, the result of us stealing a vblank from the irq
987          * handler is that a single frame will be skipped during swapbuffers.
988          */
989         I915_WRITE(pipestat_reg,
990                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
992         /* Wait for vblank interrupt bit to set */
993         if (wait_for(I915_READ(pipestat_reg) &
994                      PIPE_VBLANK_INTERRUPT_STATUS,
995                      50))
996                 DRM_DEBUG_KMS("vblank wait timed out\n");
997 }
998
999 /*
1000  * intel_wait_for_pipe_off - wait for pipe to turn off
1001  * @dev: drm device
1002  * @pipe: pipe to wait for
1003  *
1004  * After disabling a pipe, we can't wait for vblank in the usual way,
1005  * spinning on the vblank interrupt status bit, since we won't actually
1006  * see an interrupt when the pipe is disabled.
1007  *
1008  * On Gen4 and above:
1009  *   wait for the pipe register state bit to turn off
1010  *
1011  * Otherwise:
1012  *   wait for the display line value to settle (it usually
1013  *   ends up stopping at the start of the next frame).
1014  *
1015  */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020                                                                       pipe);
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(cpu_transcoder);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126                                                                       pipe);
1127
1128         if (IS_HASWELL(dev_priv->dev)) {
1129                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 reg = FDI_TX_CTL(pipe);
1135                 val = I915_READ(reg);
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151
1152         reg = FDI_RX_CTL(pipe);
1153         val = I915_READ(reg);
1154         cur_state = !!(val & FDI_RX_ENABLE);
1155         WARN(cur_state != state,
1156              "FDI RX state assertion failure (expected %s, current %s)\n",
1157              state_string(state), state_string(cur_state));
1158 }
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1163                                       enum pipe pipe)
1164 {
1165         int reg;
1166         u32 val;
1167
1168         /* ILK FDI PLL is always enabled */
1169         if (dev_priv->info->gen == 5)
1170                 return;
1171
1172         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173         if (IS_HASWELL(dev_priv->dev))
1174                 return;
1175
1176         reg = FDI_TX_CTL(pipe);
1177         val = I915_READ(reg);
1178         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1182                                       enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186
1187         reg = FDI_RX_CTL(pipe);
1188         val = I915_READ(reg);
1189         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1190 }
1191
1192 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193                                   enum pipe pipe)
1194 {
1195         int pp_reg, lvds_reg;
1196         u32 val;
1197         enum pipe panel_pipe = PIPE_A;
1198         bool locked = true;
1199
1200         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1201                 pp_reg = PCH_PP_CONTROL;
1202                 lvds_reg = PCH_LVDS;
1203         } else {
1204                 pp_reg = PP_CONTROL;
1205                 lvds_reg = LVDS;
1206         }
1207
1208         val = I915_READ(pp_reg);
1209         if (!(val & PANEL_POWER_ON) ||
1210             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1211                 locked = false;
1212
1213         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1214                 panel_pipe = PIPE_B;
1215
1216         WARN(panel_pipe == pipe && locked,
1217              "panel assertion failure, pipe %c regs locked\n",
1218              pipe_name(pipe));
1219 }
1220
1221 void assert_pipe(struct drm_i915_private *dev_priv,
1222                  enum pipe pipe, bool state)
1223 {
1224         int reg;
1225         u32 val;
1226         bool cur_state;
1227         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1228                                                                       pipe);
1229
1230         /* if we need the pipe A quirk it must be always on */
1231         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1232                 state = true;
1233
1234         reg = PIPECONF(cpu_transcoder);
1235         val = I915_READ(reg);
1236         cur_state = !!(val & PIPECONF_ENABLE);
1237         WARN(cur_state != state,
1238              "pipe %c assertion failure (expected %s, current %s)\n",
1239              pipe_name(pipe), state_string(state), state_string(cur_state));
1240 }
1241
1242 static void assert_plane(struct drm_i915_private *dev_priv,
1243                          enum plane plane, bool state)
1244 {
1245         int reg;
1246         u32 val;
1247         bool cur_state;
1248
1249         reg = DSPCNTR(plane);
1250         val = I915_READ(reg);
1251         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1252         WARN(cur_state != state,
1253              "plane %c assertion failure (expected %s, current %s)\n",
1254              plane_name(plane), state_string(state), state_string(cur_state));
1255 }
1256
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1259
1260 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1261                                    enum pipe pipe)
1262 {
1263         int reg, i;
1264         u32 val;
1265         int cur_pipe;
1266
1267         /* Planes are fixed to pipes on ILK+ */
1268         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1269                 reg = DSPCNTR(pipe);
1270                 val = I915_READ(reg);
1271                 WARN((val & DISPLAY_PLANE_ENABLE),
1272                      "plane %c assertion failure, should be disabled but not\n",
1273                      plane_name(pipe));
1274                 return;
1275         }
1276
1277         /* Need to check both planes against the pipe */
1278         for (i = 0; i < 2; i++) {
1279                 reg = DSPCNTR(i);
1280                 val = I915_READ(reg);
1281                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1282                         DISPPLANE_SEL_PIPE_SHIFT;
1283                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1284                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285                      plane_name(i), pipe_name(pipe));
1286         }
1287 }
1288
1289 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1290 {
1291         u32 val;
1292         bool enabled;
1293
1294         if (HAS_PCH_LPT(dev_priv->dev)) {
1295                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1296                 return;
1297         }
1298
1299         val = I915_READ(PCH_DREF_CONTROL);
1300         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1301                             DREF_SUPERSPREAD_SOURCE_MASK));
1302         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1303 }
1304
1305 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1306                                        enum pipe pipe)
1307 {
1308         int reg;
1309         u32 val;
1310         bool enabled;
1311
1312         reg = TRANSCONF(pipe);
1313         val = I915_READ(reg);
1314         enabled = !!(val & TRANS_ENABLE);
1315         WARN(enabled,
1316              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1317              pipe_name(pipe));
1318 }
1319
1320 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1321                             enum pipe pipe, u32 port_sel, u32 val)
1322 {
1323         if ((val & DP_PORT_EN) == 0)
1324                 return false;
1325
1326         if (HAS_PCH_CPT(dev_priv->dev)) {
1327                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1328                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1329                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1330                         return false;
1331         } else {
1332                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1333                         return false;
1334         }
1335         return true;
1336 }
1337
1338 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1339                               enum pipe pipe, u32 val)
1340 {
1341         if ((val & PORT_ENABLE) == 0)
1342                 return false;
1343
1344         if (HAS_PCH_CPT(dev_priv->dev)) {
1345                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1346                         return false;
1347         } else {
1348                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1349                         return false;
1350         }
1351         return true;
1352 }
1353
1354 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1355                               enum pipe pipe, u32 val)
1356 {
1357         if ((val & LVDS_PORT_EN) == 0)
1358                 return false;
1359
1360         if (HAS_PCH_CPT(dev_priv->dev)) {
1361                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362                         return false;
1363         } else {
1364                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1365                         return false;
1366         }
1367         return true;
1368 }
1369
1370 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1371                               enum pipe pipe, u32 val)
1372 {
1373         if ((val & ADPA_DAC_ENABLE) == 0)
1374                 return false;
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1386                                    enum pipe pipe, int reg, u32 port_sel)
1387 {
1388         u32 val = I915_READ(reg);
1389         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1390              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391              reg, pipe_name(pipe));
1392
1393         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1394              && (val & DP_PIPEB_SELECT),
1395              "IBX PCH dp port still using transcoder B\n");
1396 }
1397
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1399                                      enum pipe pipe, int reg)
1400 {
1401         u32 val = I915_READ(reg);
1402         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1403              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404              reg, pipe_name(pipe));
1405
1406         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1407              && (val & SDVO_PIPE_B_SELECT),
1408              "IBX PCH hdmi port still using transcoder B\n");
1409 }
1410
1411 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1412                                       enum pipe pipe)
1413 {
1414         int reg;
1415         u32 val;
1416
1417         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1418         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1419         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1420
1421         reg = PCH_ADPA;
1422         val = I915_READ(reg);
1423         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1424              "PCH VGA enabled on transcoder %c, should be disabled\n",
1425              pipe_name(pipe));
1426
1427         reg = PCH_LVDS;
1428         val = I915_READ(reg);
1429         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1430              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1431              pipe_name(pipe));
1432
1433         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1434         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1435         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1436 }
1437
1438 /**
1439  * intel_enable_pll - enable a PLL
1440  * @dev_priv: i915 private structure
1441  * @pipe: pipe PLL to enable
1442  *
1443  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1444  * make sure the PLL reg is writable first though, since the panel write
1445  * protect mechanism may be enabled.
1446  *
1447  * Note!  This is for pre-ILK only.
1448  *
1449  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1450  */
1451 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1452 {
1453         int reg;
1454         u32 val;
1455
1456         /* No really, not for ILK+ */
1457         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1458
1459         /* PLL is protected by panel, make sure we can write it */
1460         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1461                 assert_panel_unlocked(dev_priv, pipe);
1462
1463         reg = DPLL(pipe);
1464         val = I915_READ(reg);
1465         val |= DPLL_VCO_ENABLE;
1466
1467         /* We do this three times for luck */
1468         I915_WRITE(reg, val);
1469         POSTING_READ(reg);
1470         udelay(150); /* wait for warmup */
1471         I915_WRITE(reg, val);
1472         POSTING_READ(reg);
1473         udelay(150); /* wait for warmup */
1474         I915_WRITE(reg, val);
1475         POSTING_READ(reg);
1476         udelay(150); /* wait for warmup */
1477 }
1478
1479 /**
1480  * intel_disable_pll - disable a PLL
1481  * @dev_priv: i915 private structure
1482  * @pipe: pipe PLL to disable
1483  *
1484  * Disable the PLL for @pipe, making sure the pipe is off first.
1485  *
1486  * Note!  This is for pre-ILK only.
1487  */
1488 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1489 {
1490         int reg;
1491         u32 val;
1492
1493         /* Don't disable pipe A or pipe A PLLs if needed */
1494         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1495                 return;
1496
1497         /* Make sure the pipe isn't still relying on us */
1498         assert_pipe_disabled(dev_priv, pipe);
1499
1500         reg = DPLL(pipe);
1501         val = I915_READ(reg);
1502         val &= ~DPLL_VCO_ENABLE;
1503         I915_WRITE(reg, val);
1504         POSTING_READ(reg);
1505 }
1506
1507 /* SBI access */
1508 static void
1509 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1510 {
1511         unsigned long flags;
1512
1513         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1517                 goto out_unlock;
1518         }
1519
1520         I915_WRITE(SBI_ADDR,
1521                         (reg << 16));
1522         I915_WRITE(SBI_DATA,
1523                         value);
1524         I915_WRITE(SBI_CTL_STAT,
1525                         SBI_BUSY |
1526                         SBI_CTL_OP_CRWR);
1527
1528         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1529                                 100)) {
1530                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1531                 goto out_unlock;
1532         }
1533
1534 out_unlock:
1535         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1536 }
1537
1538 static u32
1539 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1540 {
1541         unsigned long flags;
1542         u32 value = 0;
1543
1544         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1545         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1546                                 100)) {
1547                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1548                 goto out_unlock;
1549         }
1550
1551         I915_WRITE(SBI_ADDR,
1552                         (reg << 16));
1553         I915_WRITE(SBI_CTL_STAT,
1554                         SBI_BUSY |
1555                         SBI_CTL_OP_CRRD);
1556
1557         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1558                                 100)) {
1559                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1560                 goto out_unlock;
1561         }
1562
1563         value = I915_READ(SBI_DATA);
1564
1565 out_unlock:
1566         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1567         return value;
1568 }
1569
1570 /**
1571  * ironlake_enable_pch_pll - enable PCH PLL
1572  * @dev_priv: i915 private structure
1573  * @pipe: pipe PLL to enable
1574  *
1575  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576  * drives the transcoder clock.
1577  */
1578 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1579 {
1580         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1581         struct intel_pch_pll *pll;
1582         int reg;
1583         u32 val;
1584
1585         /* PCH PLLs only available on ILK, SNB and IVB */
1586         BUG_ON(dev_priv->info->gen < 5);
1587         pll = intel_crtc->pch_pll;
1588         if (pll == NULL)
1589                 return;
1590
1591         if (WARN_ON(pll->refcount == 0))
1592                 return;
1593
1594         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595                       pll->pll_reg, pll->active, pll->on,
1596                       intel_crtc->base.base.id);
1597
1598         /* PCH refclock must be enabled first */
1599         assert_pch_refclk_enabled(dev_priv);
1600
1601         if (pll->active++ && pll->on) {
1602                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1603                 return;
1604         }
1605
1606         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1607
1608         reg = pll->pll_reg;
1609         val = I915_READ(reg);
1610         val |= DPLL_VCO_ENABLE;
1611         I915_WRITE(reg, val);
1612         POSTING_READ(reg);
1613         udelay(200);
1614
1615         pll->on = true;
1616 }
1617
1618 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1619 {
1620         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1621         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1622         int reg;
1623         u32 val;
1624
1625         /* PCH only available on ILK+ */
1626         BUG_ON(dev_priv->info->gen < 5);
1627         if (pll == NULL)
1628                return;
1629
1630         if (WARN_ON(pll->refcount == 0))
1631                 return;
1632
1633         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634                       pll->pll_reg, pll->active, pll->on,
1635                       intel_crtc->base.base.id);
1636
1637         if (WARN_ON(pll->active == 0)) {
1638                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1639                 return;
1640         }
1641
1642         if (--pll->active) {
1643                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1644                 return;
1645         }
1646
1647         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1648
1649         /* Make sure transcoder isn't still depending on us */
1650         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1651
1652         reg = pll->pll_reg;
1653         val = I915_READ(reg);
1654         val &= ~DPLL_VCO_ENABLE;
1655         I915_WRITE(reg, val);
1656         POSTING_READ(reg);
1657         udelay(200);
1658
1659         pll->on = false;
1660 }
1661
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                            enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1667         uint32_t reg, val, pipeconf_val;
1668
1669         /* PCH only available on ILK+ */
1670         BUG_ON(dev_priv->info->gen < 5);
1671
1672         /* Make sure PCH DPLL is enabled */
1673         assert_pch_pll_enabled(dev_priv,
1674                                to_intel_crtc(crtc)->pch_pll,
1675                                to_intel_crtc(crtc));
1676
1677         /* FDI must be feeding us bits for PCH ports */
1678         assert_fdi_tx_enabled(dev_priv, pipe);
1679         assert_fdi_rx_enabled(dev_priv, pipe);
1680
1681         if (HAS_PCH_CPT(dev)) {
1682                 /* Workaround: Set the timing override bit before enabling the
1683                  * pch transcoder. */
1684                 reg = TRANS_CHICKEN2(pipe);
1685                 val = I915_READ(reg);
1686                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687                 I915_WRITE(reg, val);
1688         }
1689
1690         reg = TRANSCONF(pipe);
1691         val = I915_READ(reg);
1692         pipeconf_val = I915_READ(PIPECONF(pipe));
1693
1694         if (HAS_PCH_IBX(dev_priv->dev)) {
1695                 /*
1696                  * make the BPC in transcoder be consistent with
1697                  * that in pipeconf reg.
1698                  */
1699                 val &= ~PIPE_BPC_MASK;
1700                 val |= pipeconf_val & PIPE_BPC_MASK;
1701         }
1702
1703         val &= ~TRANS_INTERLACE_MASK;
1704         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1705                 if (HAS_PCH_IBX(dev_priv->dev) &&
1706                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1707                         val |= TRANS_LEGACY_INTERLACED_ILK;
1708                 else
1709                         val |= TRANS_INTERLACED;
1710         else
1711                 val |= TRANS_PROGRESSIVE;
1712
1713         I915_WRITE(reg, val | TRANS_ENABLE);
1714         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1715                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1716 }
1717
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1719                                       enum transcoder cpu_transcoder)
1720 {
1721         u32 val, pipeconf_val;
1722
1723         /* PCH only available on ILK+ */
1724         BUG_ON(dev_priv->info->gen < 5);
1725
1726         /* FDI must be feeding us bits for PCH ports */
1727         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1728         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1729
1730         /* Workaround: set timing override bit. */
1731         val = I915_READ(_TRANSA_CHICKEN2);
1732         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1733         I915_WRITE(_TRANSA_CHICKEN2, val);
1734
1735         val = TRANS_ENABLE;
1736         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1737
1738         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1739             PIPECONF_INTERLACED_ILK)
1740                 val |= TRANS_INTERLACED;
1741         else
1742                 val |= TRANS_PROGRESSIVE;
1743
1744         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1745         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1746                 DRM_ERROR("Failed to enable PCH transcoder\n");
1747 }
1748
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1750                                             enum pipe pipe)
1751 {
1752         struct drm_device *dev = dev_priv->dev;
1753         uint32_t reg, val;
1754
1755         /* FDI relies on the transcoder */
1756         assert_fdi_tx_disabled(dev_priv, pipe);
1757         assert_fdi_rx_disabled(dev_priv, pipe);
1758
1759         /* Ports must be off as well */
1760         assert_pch_ports_disabled(dev_priv, pipe);
1761
1762         reg = TRANSCONF(pipe);
1763         val = I915_READ(reg);
1764         val &= ~TRANS_ENABLE;
1765         I915_WRITE(reg, val);
1766         /* wait for PCH transcoder off, transcoder state */
1767         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1768                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1769
1770         if (!HAS_PCH_IBX(dev)) {
1771                 /* Workaround: Clear the timing override chicken bit again. */
1772                 reg = TRANS_CHICKEN2(pipe);
1773                 val = I915_READ(reg);
1774                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1775                 I915_WRITE(reg, val);
1776         }
1777 }
1778
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1780 {
1781         u32 val;
1782
1783         val = I915_READ(_TRANSACONF);
1784         val &= ~TRANS_ENABLE;
1785         I915_WRITE(_TRANSACONF, val);
1786         /* wait for PCH transcoder off, transcoder state */
1787         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1788                 DRM_ERROR("Failed to disable PCH transcoder\n");
1789
1790         /* Workaround: clear timing override bit. */
1791         val = I915_READ(_TRANSA_CHICKEN2);
1792         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1793         I915_WRITE(_TRANSA_CHICKEN2, val);
1794 }
1795
1796 /**
1797  * intel_enable_pipe - enable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to enable
1800  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801  *
1802  * Enable @pipe, making sure that various hardware specific requirements
1803  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804  *
1805  * @pipe should be %PIPE_A or %PIPE_B.
1806  *
1807  * Will wait until the pipe is actually running (i.e. first vblank) before
1808  * returning.
1809  */
1810 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1811                               bool pch_port)
1812 {
1813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1814                                                                       pipe);
1815         enum transcoder pch_transcoder;
1816         int reg;
1817         u32 val;
1818
1819         if (IS_HASWELL(dev_priv->dev))
1820                 pch_transcoder = TRANSCODER_A;
1821         else
1822                 pch_transcoder = pipe;
1823
1824         /*
1825          * A pipe without a PLL won't actually be able to drive bits from
1826          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1827          * need the check.
1828          */
1829         if (!HAS_PCH_SPLIT(dev_priv->dev))
1830                 assert_pll_enabled(dev_priv, pipe);
1831         else {
1832                 if (pch_port) {
1833                         /* if driving the PCH, we need FDI enabled */
1834                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1835                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1836                 }
1837                 /* FIXME: assert CPU port conditions for SNB+ */
1838         }
1839
1840         reg = PIPECONF(cpu_transcoder);
1841         val = I915_READ(reg);
1842         if (val & PIPECONF_ENABLE)
1843                 return;
1844
1845         I915_WRITE(reg, val | PIPECONF_ENABLE);
1846         intel_wait_for_vblank(dev_priv->dev, pipe);
1847 }
1848
1849 /**
1850  * intel_disable_pipe - disable a pipe, asserting requirements
1851  * @dev_priv: i915 private structure
1852  * @pipe: pipe to disable
1853  *
1854  * Disable @pipe, making sure that various hardware specific requirements
1855  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856  *
1857  * @pipe should be %PIPE_A or %PIPE_B.
1858  *
1859  * Will wait until the pipe has shut down before returning.
1860  */
1861 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862                                enum pipe pipe)
1863 {
1864         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865                                                                       pipe);
1866         int reg;
1867         u32 val;
1868
1869         /*
1870          * Make sure planes won't keep trying to pump pixels to us,
1871          * or we might hang the display.
1872          */
1873         assert_planes_disabled(dev_priv, pipe);
1874
1875         /* Don't disable pipe A or pipe A PLLs if needed */
1876         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877                 return;
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = I915_READ(reg);
1881         if ((val & PIPECONF_ENABLE) == 0)
1882                 return;
1883
1884         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1885         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886 }
1887
1888 /*
1889  * Plane regs are double buffered, going from enabled->disabled needs a
1890  * trigger in order to latch.  The display address reg provides this.
1891  */
1892 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1893                                       enum plane plane)
1894 {
1895         if (dev_priv->info->gen >= 4)
1896                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897         else
1898                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1899 }
1900
1901 /**
1902  * intel_enable_plane - enable a display plane on a given pipe
1903  * @dev_priv: i915 private structure
1904  * @plane: plane to enable
1905  * @pipe: pipe being fed
1906  *
1907  * Enable @plane on @pipe, making sure that @pipe is running first.
1908  */
1909 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910                                enum plane plane, enum pipe pipe)
1911 {
1912         int reg;
1913         u32 val;
1914
1915         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916         assert_pipe_enabled(dev_priv, pipe);
1917
1918         reg = DSPCNTR(plane);
1919         val = I915_READ(reg);
1920         if (val & DISPLAY_PLANE_ENABLE)
1921                 return;
1922
1923         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1924         intel_flush_display_plane(dev_priv, plane);
1925         intel_wait_for_vblank(dev_priv->dev, pipe);
1926 }
1927
1928 /**
1929  * intel_disable_plane - disable a display plane
1930  * @dev_priv: i915 private structure
1931  * @plane: plane to disable
1932  * @pipe: pipe consuming the data
1933  *
1934  * Disable @plane; should be an independent operation.
1935  */
1936 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937                                 enum plane plane, enum pipe pipe)
1938 {
1939         int reg;
1940         u32 val;
1941
1942         reg = DSPCNTR(plane);
1943         val = I915_READ(reg);
1944         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945                 return;
1946
1947         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1948         intel_flush_display_plane(dev_priv, plane);
1949         intel_wait_for_vblank(dev_priv->dev, pipe);
1950 }
1951
1952 int
1953 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1954                            struct drm_i915_gem_object *obj,
1955                            struct intel_ring_buffer *pipelined)
1956 {
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         u32 alignment;
1959         int ret;
1960
1961         switch (obj->tiling_mode) {
1962         case I915_TILING_NONE:
1963                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964                         alignment = 128 * 1024;
1965                 else if (INTEL_INFO(dev)->gen >= 4)
1966                         alignment = 4 * 1024;
1967                 else
1968                         alignment = 64 * 1024;
1969                 break;
1970         case I915_TILING_X:
1971                 /* pin() will align the object as required by fence */
1972                 alignment = 0;
1973                 break;
1974         case I915_TILING_Y:
1975                 /* FIXME: Is this true? */
1976                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977                 return -EINVAL;
1978         default:
1979                 BUG();
1980         }
1981
1982         dev_priv->mm.interruptible = false;
1983         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1984         if (ret)
1985                 goto err_interruptible;
1986
1987         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988          * fence, whereas 965+ only requires a fence if using
1989          * framebuffer compression.  For simplicity, we always install
1990          * a fence as the cost is not that onerous.
1991          */
1992         ret = i915_gem_object_get_fence(obj);
1993         if (ret)
1994                 goto err_unpin;
1995
1996         i915_gem_object_pin_fence(obj);
1997
1998         dev_priv->mm.interruptible = true;
1999         return 0;
2000
2001 err_unpin:
2002         i915_gem_object_unpin(obj);
2003 err_interruptible:
2004         dev_priv->mm.interruptible = true;
2005         return ret;
2006 }
2007
2008 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009 {
2010         i915_gem_object_unpin_fence(obj);
2011         i915_gem_object_unpin(obj);
2012 }
2013
2014 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015  * is assumed to be a power-of-two. */
2016 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017                                                unsigned int bpp,
2018                                                unsigned int pitch)
2019 {
2020         int tile_rows, tiles;
2021
2022         tile_rows = *y / 8;
2023         *y %= 8;
2024         tiles = *x / (512/bpp);
2025         *x %= 512/bpp;
2026
2027         return tile_rows * pitch * 8 + tiles * 4096;
2028 }
2029
2030 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031                              int x, int y)
2032 {
2033         struct drm_device *dev = crtc->dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036         struct intel_framebuffer *intel_fb;
2037         struct drm_i915_gem_object *obj;
2038         int plane = intel_crtc->plane;
2039         unsigned long linear_offset;
2040         u32 dspcntr;
2041         u32 reg;
2042
2043         switch (plane) {
2044         case 0:
2045         case 1:
2046                 break;
2047         default:
2048                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049                 return -EINVAL;
2050         }
2051
2052         intel_fb = to_intel_framebuffer(fb);
2053         obj = intel_fb->obj;
2054
2055         reg = DSPCNTR(plane);
2056         dspcntr = I915_READ(reg);
2057         /* Mask out pixel format bits in case we change it */
2058         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2059         switch (fb->pixel_format) {
2060         case DRM_FORMAT_C8:
2061                 dspcntr |= DISPPLANE_8BPP;
2062                 break;
2063         case DRM_FORMAT_XRGB1555:
2064         case DRM_FORMAT_ARGB1555:
2065                 dspcntr |= DISPPLANE_BGRX555;
2066                 break;
2067         case DRM_FORMAT_RGB565:
2068                 dspcntr |= DISPPLANE_BGRX565;
2069                 break;
2070         case DRM_FORMAT_XRGB8888:
2071         case DRM_FORMAT_ARGB8888:
2072                 dspcntr |= DISPPLANE_BGRX888;
2073                 break;
2074         case DRM_FORMAT_XBGR8888:
2075         case DRM_FORMAT_ABGR8888:
2076                 dspcntr |= DISPPLANE_RGBX888;
2077                 break;
2078         case DRM_FORMAT_XRGB2101010:
2079         case DRM_FORMAT_ARGB2101010:
2080                 dspcntr |= DISPPLANE_BGRX101010;
2081                 break;
2082         case DRM_FORMAT_XBGR2101010:
2083         case DRM_FORMAT_ABGR2101010:
2084                 dspcntr |= DISPPLANE_RGBX101010;
2085                 break;
2086         default:
2087                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2088                 return -EINVAL;
2089         }
2090
2091         if (INTEL_INFO(dev)->gen >= 4) {
2092                 if (obj->tiling_mode != I915_TILING_NONE)
2093                         dspcntr |= DISPPLANE_TILED;
2094                 else
2095                         dspcntr &= ~DISPPLANE_TILED;
2096         }
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_offset_xtiled(&x, &y,
2105                                                          fb->bits_per_pixel / 8,
2106                                                          fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2114         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2115         if (INTEL_INFO(dev)->gen >= 4) {
2116                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2118                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2119                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2120         } else
2121                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2122         POSTING_READ(reg);
2123
2124         return 0;
2125 }
2126
2127 static int ironlake_update_plane(struct drm_crtc *crtc,
2128                                  struct drm_framebuffer *fb, int x, int y)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         struct intel_framebuffer *intel_fb;
2134         struct drm_i915_gem_object *obj;
2135         int plane = intel_crtc->plane;
2136         unsigned long linear_offset;
2137         u32 dspcntr;
2138         u32 reg;
2139
2140         switch (plane) {
2141         case 0:
2142         case 1:
2143         case 2:
2144                 break;
2145         default:
2146                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147                 return -EINVAL;
2148         }
2149
2150         intel_fb = to_intel_framebuffer(fb);
2151         obj = intel_fb->obj;
2152
2153         reg = DSPCNTR(plane);
2154         dspcntr = I915_READ(reg);
2155         /* Mask out pixel format bits in case we change it */
2156         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2157         switch (fb->pixel_format) {
2158         case DRM_FORMAT_C8:
2159                 dspcntr |= DISPPLANE_8BPP;
2160                 break;
2161         case DRM_FORMAT_RGB565:
2162                 dspcntr |= DISPPLANE_BGRX565;
2163                 break;
2164         case DRM_FORMAT_XRGB8888:
2165         case DRM_FORMAT_ARGB8888:
2166                 dspcntr |= DISPPLANE_BGRX888;
2167                 break;
2168         case DRM_FORMAT_XBGR8888:
2169         case DRM_FORMAT_ABGR8888:
2170                 dspcntr |= DISPPLANE_RGBX888;
2171                 break;
2172         case DRM_FORMAT_XRGB2101010:
2173         case DRM_FORMAT_ARGB2101010:
2174                 dspcntr |= DISPPLANE_BGRX101010;
2175                 break;
2176         case DRM_FORMAT_XBGR2101010:
2177         case DRM_FORMAT_ABGR2101010:
2178                 dspcntr |= DISPPLANE_RGBX101010;
2179                 break;
2180         default:
2181                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2182                 return -EINVAL;
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         /* must disable */
2191         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193         I915_WRITE(reg, dspcntr);
2194
2195         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2196         intel_crtc->dspaddr_offset =
2197                 intel_gen4_compute_offset_xtiled(&x, &y,
2198                                                  fb->bits_per_pixel / 8,
2199                                                  fb->pitches[0]);
2200         linear_offset -= intel_crtc->dspaddr_offset;
2201
2202         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2204         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2205         I915_MODIFY_DISPBASE(DSPSURF(plane),
2206                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2207         if (IS_HASWELL(dev)) {
2208                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209         } else {
2210                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212         }
2213         POSTING_READ(reg);
2214
2215         return 0;
2216 }
2217
2218 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2219 static int
2220 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221                            int x, int y, enum mode_set_atomic state)
2222 {
2223         struct drm_device *dev = crtc->dev;
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225
2226         if (dev_priv->display.disable_fbc)
2227                 dev_priv->display.disable_fbc(dev);
2228         intel_increase_pllclock(crtc);
2229
2230         return dev_priv->display.update_plane(crtc, fb, x, y);
2231 }
2232
2233 static int
2234 intel_finish_fb(struct drm_framebuffer *old_fb)
2235 {
2236         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238         bool was_interruptible = dev_priv->mm.interruptible;
2239         int ret;
2240
2241         wait_event(dev_priv->pending_flip_queue,
2242                    atomic_read(&dev_priv->mm.wedged) ||
2243                    atomic_read(&obj->pending_flip) == 0);
2244
2245         /* Big Hammer, we also need to ensure that any pending
2246          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247          * current scanout is retired before unpinning the old
2248          * framebuffer.
2249          *
2250          * This should only fail upon a hung GPU, in which case we
2251          * can safely continue.
2252          */
2253         dev_priv->mm.interruptible = false;
2254         ret = i915_gem_object_finish_gpu(obj);
2255         dev_priv->mm.interruptible = was_interruptible;
2256
2257         return ret;
2258 }
2259
2260 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct drm_i915_master_private *master_priv;
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266         if (!dev->primary->master)
2267                 return;
2268
2269         master_priv = dev->primary->master->driver_priv;
2270         if (!master_priv->sarea_priv)
2271                 return;
2272
2273         switch (intel_crtc->pipe) {
2274         case 0:
2275                 master_priv->sarea_priv->pipeA_x = x;
2276                 master_priv->sarea_priv->pipeA_y = y;
2277                 break;
2278         case 1:
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281                 break;
2282         default:
2283                 break;
2284         }
2285 }
2286
2287 static int
2288 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2289                     struct drm_framebuffer *fb)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         struct drm_framebuffer *old_fb;
2295         int ret;
2296
2297         /* no fb bound */
2298         if (!fb) {
2299                 DRM_ERROR("No FB bound\n");
2300                 return 0;
2301         }
2302
2303         if(intel_crtc->plane > dev_priv->num_pipe) {
2304                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305                                 intel_crtc->plane,
2306                                 dev_priv->num_pipe);
2307                 return -EINVAL;
2308         }
2309
2310         mutex_lock(&dev->struct_mutex);
2311         ret = intel_pin_and_fence_fb_obj(dev,
2312                                          to_intel_framebuffer(fb)->obj,
2313                                          NULL);
2314         if (ret != 0) {
2315                 mutex_unlock(&dev->struct_mutex);
2316                 DRM_ERROR("pin & fence failed\n");
2317                 return ret;
2318         }
2319
2320         if (crtc->fb)
2321                 intel_finish_fb(crtc->fb);
2322
2323         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2324         if (ret) {
2325                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2326                 mutex_unlock(&dev->struct_mutex);
2327                 DRM_ERROR("failed to update base address\n");
2328                 return ret;
2329         }
2330
2331         old_fb = crtc->fb;
2332         crtc->fb = fb;
2333         crtc->x = x;
2334         crtc->y = y;
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         intel_update_fbc(dev);
2342         mutex_unlock(&dev->struct_mutex);
2343
2344         intel_crtc_update_sarea_pos(crtc, x, y);
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 static void ivb_modeset_global_resources(struct drm_device *dev)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *pipe_B_crtc =
2443                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444         struct intel_crtc *pipe_C_crtc =
2445                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446         uint32_t temp;
2447
2448         /* When everything is off disable fdi C so that we could enable fdi B
2449          * with all lanes. XXX: This misses the case where a pipe is not using
2450          * any pch resources and so doesn't need any fdi lanes. */
2451         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455                 temp = I915_READ(SOUTH_CHICKEN1);
2456                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458                 I915_WRITE(SOUTH_CHICKEN1, temp);
2459         }
2460 }
2461
2462 /* The FDI link training functions for ILK/Ibexpeak. */
2463 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468         int pipe = intel_crtc->pipe;
2469         int plane = intel_crtc->plane;
2470         u32 reg, temp, tries;
2471
2472         /* FDI needs bits from pipe & plane first */
2473         assert_pipe_enabled(dev_priv, pipe);
2474         assert_plane_enabled(dev_priv, plane);
2475
2476         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477            for train result */
2478         reg = FDI_RX_IMR(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_RX_SYMBOL_LOCK;
2481         temp &= ~FDI_RX_BIT_LOCK;
2482         I915_WRITE(reg, temp);
2483         I915_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         reg = FDI_RX_CTL(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_LINK_TRAIN_NONE;
2498         temp |= FDI_LINK_TRAIN_PATTERN_1;
2499         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         /* Ironlake workaround, enable clock pointer after FDI enable*/
2505         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2506         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2507                    FDI_RX_PHASE_SYNC_POINTER_EN);
2508
2509         reg = FDI_RX_IIR(pipe);
2510         for (tries = 0; tries < 5; tries++) {
2511                 temp = I915_READ(reg);
2512                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513
2514                 if ((temp & FDI_RX_BIT_LOCK)) {
2515                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2516                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2517                         break;
2518                 }
2519         }
2520         if (tries == 5)
2521                 DRM_ERROR("FDI train 1 fail!\n");
2522
2523         /* Train 2 */
2524         reg = FDI_TX_CTL(pipe);
2525         temp = I915_READ(reg);
2526         temp &= ~FDI_LINK_TRAIN_NONE;
2527         temp |= FDI_LINK_TRAIN_PATTERN_2;
2528         I915_WRITE(reg, temp);
2529
2530         reg = FDI_RX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_LINK_TRAIN_NONE;
2533         temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         I915_WRITE(reg, temp);
2535
2536         POSTING_READ(reg);
2537         udelay(150);
2538
2539         reg = FDI_RX_IIR(pipe);
2540         for (tries = 0; tries < 5; tries++) {
2541                 temp = I915_READ(reg);
2542                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543
2544                 if (temp & FDI_RX_SYMBOL_LOCK) {
2545                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2546                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2547                         break;
2548                 }
2549         }
2550         if (tries == 5)
2551                 DRM_ERROR("FDI train 2 fail!\n");
2552
2553         DRM_DEBUG_KMS("FDI train done\n");
2554
2555 }
2556
2557 static const int snb_b_fdi_train_param[] = {
2558         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2559         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2560         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2561         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2562 };
2563
2564 /* The FDI link training functions for SNB/Cougarpoint. */
2565 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2566 {
2567         struct drm_device *dev = crtc->dev;
2568         struct drm_i915_private *dev_priv = dev->dev_private;
2569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570         int pipe = intel_crtc->pipe;
2571         u32 reg, temp, i, retry;
2572
2573         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2574            for train result */
2575         reg = FDI_RX_IMR(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_RX_SYMBOL_LOCK;
2578         temp &= ~FDI_RX_BIT_LOCK;
2579         I915_WRITE(reg, temp);
2580
2581         POSTING_READ(reg);
2582         udelay(150);
2583
2584         /* enable CPU FDI TX and PCH FDI RX */
2585         reg = FDI_TX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~(7 << 19);
2588         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2589         temp &= ~FDI_LINK_TRAIN_NONE;
2590         temp |= FDI_LINK_TRAIN_PATTERN_1;
2591         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2592         /* SNB-B */
2593         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2594         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2595
2596         I915_WRITE(FDI_RX_MISC(pipe),
2597                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2598
2599         reg = FDI_RX_CTL(pipe);
2600         temp = I915_READ(reg);
2601         if (HAS_PCH_CPT(dev)) {
2602                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2603                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2604         } else {
2605                 temp &= ~FDI_LINK_TRAIN_NONE;
2606                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2607         }
2608         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2609
2610         POSTING_READ(reg);
2611         udelay(150);
2612
2613         cpt_phase_pointer_enable(dev, pipe);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_BIT_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 1 fail!\n");
2641
2642         /* Train 2 */
2643         reg = FDI_TX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         temp &= ~FDI_LINK_TRAIN_NONE;
2646         temp |= FDI_LINK_TRAIN_PATTERN_2;
2647         if (IS_GEN6(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649                 /* SNB-B */
2650                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         reg = FDI_RX_CTL(pipe);
2655         temp = I915_READ(reg);
2656         if (HAS_PCH_CPT(dev)) {
2657                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659         } else {
2660                 temp &= ~FDI_LINK_TRAIN_NONE;
2661                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2662         }
2663         I915_WRITE(reg, temp);
2664
2665         POSTING_READ(reg);
2666         udelay(150);
2667
2668         for (i = 0; i < 4; i++) {
2669                 reg = FDI_TX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672                 temp |= snb_b_fdi_train_param[i];
2673                 I915_WRITE(reg, temp);
2674
2675                 POSTING_READ(reg);
2676                 udelay(500);
2677
2678                 for (retry = 0; retry < 5; retry++) {
2679                         reg = FDI_RX_IIR(pipe);
2680                         temp = I915_READ(reg);
2681                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682                         if (temp & FDI_RX_SYMBOL_LOCK) {
2683                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2684                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2685                                 break;
2686                         }
2687                         udelay(50);
2688                 }
2689                 if (retry < 5)
2690                         break;
2691         }
2692         if (i == 4)
2693                 DRM_ERROR("FDI train 2 fail!\n");
2694
2695         DRM_DEBUG_KMS("FDI train done.\n");
2696 }
2697
2698 /* Manual link training for Ivy Bridge A0 parts */
2699 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2700 {
2701         struct drm_device *dev = crtc->dev;
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704         int pipe = intel_crtc->pipe;
2705         u32 reg, temp, i;
2706
2707         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708            for train result */
2709         reg = FDI_RX_IMR(pipe);
2710         temp = I915_READ(reg);
2711         temp &= ~FDI_RX_SYMBOL_LOCK;
2712         temp &= ~FDI_RX_BIT_LOCK;
2713         I915_WRITE(reg, temp);
2714
2715         POSTING_READ(reg);
2716         udelay(150);
2717
2718         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719                       I915_READ(FDI_RX_IIR(pipe)));
2720
2721         /* enable CPU FDI TX and PCH FDI RX */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~(7 << 19);
2725         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2726         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2727         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2728         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2729         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2730         temp |= FDI_COMPOSITE_SYNC;
2731         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2732
2733         I915_WRITE(FDI_RX_MISC(pipe),
2734                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2735
2736         reg = FDI_RX_CTL(pipe);
2737         temp = I915_READ(reg);
2738         temp &= ~FDI_LINK_TRAIN_AUTO;
2739         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2740         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2741         temp |= FDI_COMPOSITE_SYNC;
2742         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743
2744         POSTING_READ(reg);
2745         udelay(150);
2746
2747         cpt_phase_pointer_enable(dev, pipe);
2748
2749         for (i = 0; i < 4; i++) {
2750                 reg = FDI_TX_CTL(pipe);
2751                 temp = I915_READ(reg);
2752                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2753                 temp |= snb_b_fdi_train_param[i];
2754                 I915_WRITE(reg, temp);
2755
2756                 POSTING_READ(reg);
2757                 udelay(500);
2758
2759                 reg = FDI_RX_IIR(pipe);
2760                 temp = I915_READ(reg);
2761                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2762
2763                 if (temp & FDI_RX_BIT_LOCK ||
2764                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2765                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2766                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2767                         break;
2768                 }
2769         }
2770         if (i == 4)
2771                 DRM_ERROR("FDI train 1 fail!\n");
2772
2773         /* Train 2 */
2774         reg = FDI_TX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2778         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2779         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2780         I915_WRITE(reg, temp);
2781
2782         reg = FDI_RX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2785         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2786         I915_WRITE(reg, temp);
2787
2788         POSTING_READ(reg);
2789         udelay(150);
2790
2791         for (i = 0; i < 4; i++) {
2792                 reg = FDI_TX_CTL(pipe);
2793                 temp = I915_READ(reg);
2794                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2795                 temp |= snb_b_fdi_train_param[i];
2796                 I915_WRITE(reg, temp);
2797
2798                 POSTING_READ(reg);
2799                 udelay(500);
2800
2801                 reg = FDI_RX_IIR(pipe);
2802                 temp = I915_READ(reg);
2803                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2804
2805                 if (temp & FDI_RX_SYMBOL_LOCK) {
2806                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2807                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2808                         break;
2809                 }
2810         }
2811         if (i == 4)
2812                 DRM_ERROR("FDI train 2 fail!\n");
2813
2814         DRM_DEBUG_KMS("FDI train done.\n");
2815 }
2816
2817 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2818 {
2819         struct drm_device *dev = intel_crtc->base.dev;
2820         struct drm_i915_private *dev_priv = dev->dev_private;
2821         int pipe = intel_crtc->pipe;
2822         u32 reg, temp;
2823
2824
2825         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         temp &= ~((0x7 << 19) | (0x7 << 16));
2829         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2830         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2832
2833         POSTING_READ(reg);
2834         udelay(200);
2835
2836         /* Switch from Rawclk to PCDclk */
2837         temp = I915_READ(reg);
2838         I915_WRITE(reg, temp | FDI_PCDCLK);
2839
2840         POSTING_READ(reg);
2841         udelay(200);
2842
2843         /* On Haswell, the PLL configuration for ports and pipes is handled
2844          * separately, as part of DDI setup */
2845         if (!IS_HASWELL(dev)) {
2846                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847                 reg = FDI_TX_CTL(pipe);
2848                 temp = I915_READ(reg);
2849                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2850                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2851
2852                         POSTING_READ(reg);
2853                         udelay(100);
2854                 }
2855         }
2856 }
2857
2858 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2859 {
2860         struct drm_device *dev = intel_crtc->base.dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         int pipe = intel_crtc->pipe;
2863         u32 reg, temp;
2864
2865         /* Switch from PCDclk to Rawclk */
2866         reg = FDI_RX_CTL(pipe);
2867         temp = I915_READ(reg);
2868         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2869
2870         /* Disable CPU FDI TX PLL */
2871         reg = FDI_TX_CTL(pipe);
2872         temp = I915_READ(reg);
2873         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2874
2875         POSTING_READ(reg);
2876         udelay(100);
2877
2878         reg = FDI_RX_CTL(pipe);
2879         temp = I915_READ(reg);
2880         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2881
2882         /* Wait for the clocks to turn off. */
2883         POSTING_READ(reg);
2884         udelay(100);
2885 }
2886
2887 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2888 {
2889         struct drm_i915_private *dev_priv = dev->dev_private;
2890         u32 flags = I915_READ(SOUTH_CHICKEN1);
2891
2892         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2893         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2894         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2895         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2896         POSTING_READ(SOUTH_CHICKEN1);
2897 }
2898 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2899 {
2900         struct drm_device *dev = crtc->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903         int pipe = intel_crtc->pipe;
2904         u32 reg, temp;
2905
2906         /* disable CPU FDI tx and PCH FDI rx */
2907         reg = FDI_TX_CTL(pipe);
2908         temp = I915_READ(reg);
2909         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2910         POSTING_READ(reg);
2911
2912         reg = FDI_RX_CTL(pipe);
2913         temp = I915_READ(reg);
2914         temp &= ~(0x7 << 16);
2915         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2916         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2917
2918         POSTING_READ(reg);
2919         udelay(100);
2920
2921         /* Ironlake workaround, disable clock pointer after downing FDI */
2922         if (HAS_PCH_IBX(dev)) {
2923                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2924         } else if (HAS_PCH_CPT(dev)) {
2925                 cpt_phase_pointer_disable(dev, pipe);
2926         }
2927
2928         /* still set train pattern 1 */
2929         reg = FDI_TX_CTL(pipe);
2930         temp = I915_READ(reg);
2931         temp &= ~FDI_LINK_TRAIN_NONE;
2932         temp |= FDI_LINK_TRAIN_PATTERN_1;
2933         I915_WRITE(reg, temp);
2934
2935         reg = FDI_RX_CTL(pipe);
2936         temp = I915_READ(reg);
2937         if (HAS_PCH_CPT(dev)) {
2938                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2940         } else {
2941                 temp &= ~FDI_LINK_TRAIN_NONE;
2942                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2943         }
2944         /* BPC in FDI rx is consistent with that in PIPECONF */
2945         temp &= ~(0x07 << 16);
2946         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947         I915_WRITE(reg, temp);
2948
2949         POSTING_READ(reg);
2950         udelay(100);
2951 }
2952
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2954 {
2955         struct drm_device *dev = crtc->dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         unsigned long flags;
2958         bool pending;
2959
2960         if (atomic_read(&dev_priv->mm.wedged))
2961                 return false;
2962
2963         spin_lock_irqsave(&dev->event_lock, flags);
2964         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965         spin_unlock_irqrestore(&dev->event_lock, flags);
2966
2967         return pending;
2968 }
2969
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2971 {
2972         struct drm_device *dev = crtc->dev;
2973         struct drm_i915_private *dev_priv = dev->dev_private;
2974
2975         if (crtc->fb == NULL)
2976                 return;
2977
2978         wait_event(dev_priv->pending_flip_queue,
2979                    !intel_crtc_has_pending_flip(crtc));
2980
2981         mutex_lock(&dev->struct_mutex);
2982         intel_finish_fb(crtc->fb);
2983         mutex_unlock(&dev->struct_mutex);
2984 }
2985
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2987 {
2988         struct drm_device *dev = crtc->dev;
2989         struct intel_encoder *intel_encoder;
2990
2991         /*
2992          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993          * must be driven by its own crtc; no sharing is possible.
2994          */
2995         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2996                 switch (intel_encoder->type) {
2997                 case INTEL_OUTPUT_EDP:
2998                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2999                                 return false;
3000                         continue;
3001                 }
3002         }
3003
3004         return true;
3005 }
3006
3007 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3008 {
3009         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3010 }
3011
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc *crtc)
3014 {
3015         struct drm_device *dev = crtc->dev;
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3018         u32 temp;
3019
3020         /* It is necessary to ungate the pixclk gate prior to programming
3021          * the divisors, and gate it back when it is done.
3022          */
3023         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3024
3025         /* Disable SSCCTL */
3026         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028                                         SBI_SSCCTL_DISABLE);
3029
3030         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031         if (crtc->mode.clock == 20000) {
3032                 auxdiv = 1;
3033                 divsel = 0x41;
3034                 phaseinc = 0x20;
3035         } else {
3036                 /* The iCLK virtual clock root frequency is in MHz,
3037                  * but the crtc->mode.clock in in KHz. To get the divisors,
3038                  * it is necessary to divide one by another, so we
3039                  * convert the virtual clock precision to KHz here for higher
3040                  * precision.
3041                  */
3042                 u32 iclk_virtual_root_freq = 172800 * 1000;
3043                 u32 iclk_pi_range = 64;
3044                 u32 desired_divisor, msb_divisor_value, pi_value;
3045
3046                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047                 msb_divisor_value = desired_divisor / iclk_pi_range;
3048                 pi_value = desired_divisor % iclk_pi_range;
3049
3050                 auxdiv = 0;
3051                 divsel = msb_divisor_value - 2;
3052                 phaseinc = pi_value;
3053         }
3054
3055         /* This should not happen with any sane values */
3056         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3060
3061         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3062                         crtc->mode.clock,
3063                         auxdiv,
3064                         divsel,
3065                         phasedir,
3066                         phaseinc);
3067
3068         /* Program SSCDIVINTPHASE6 */
3069         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3076
3077         intel_sbi_write(dev_priv,
3078                         SBI_SSCDIVINTPHASE6,
3079                         temp);
3080
3081         /* Program SSCAUXDIV */
3082         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085         intel_sbi_write(dev_priv,
3086                         SBI_SSCAUXDIV6,
3087                         temp);
3088
3089
3090         /* Enable modulator and associated divider */
3091         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092         temp &= ~SBI_SSCCTL_DISABLE;
3093         intel_sbi_write(dev_priv,
3094                         SBI_SSCCTL6,
3095                         temp);
3096
3097         /* Wait for initialization time */
3098         udelay(24);
3099
3100         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3101 }
3102
3103 /*
3104  * Enable PCH resources required for PCH ports:
3105  *   - PCH PLLs
3106  *   - FDI training & RX/TX
3107  *   - update transcoder timings
3108  *   - DP transcoding bits
3109  *   - transcoder
3110  */
3111 static void ironlake_pch_enable(struct drm_crtc *crtc)
3112 {
3113         struct drm_device *dev = crtc->dev;
3114         struct drm_i915_private *dev_priv = dev->dev_private;
3115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116         int pipe = intel_crtc->pipe;
3117         u32 reg, temp;
3118
3119         assert_transcoder_disabled(dev_priv, pipe);
3120
3121         /* Write the TU size bits before fdi link training, so that error
3122          * detection works. */
3123         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3125
3126         /* For PCH output, training FDI link */
3127         dev_priv->display.fdi_link_train(crtc);
3128
3129         /* XXX: pch pll's can be enabled any time before we enable the PCH
3130          * transcoder, and we actually should do this to not upset any PCH
3131          * transcoder that already use the clock when we share it.
3132          *
3133          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134          * unconditionally resets the pll - we need that to have the right LVDS
3135          * enable sequence. */
3136         ironlake_enable_pch_pll(intel_crtc);
3137
3138         if (HAS_PCH_CPT(dev)) {
3139                 u32 sel;
3140
3141                 temp = I915_READ(PCH_DPLL_SEL);
3142                 switch (pipe) {
3143                 default:
3144                 case 0:
3145                         temp |= TRANSA_DPLL_ENABLE;
3146                         sel = TRANSA_DPLLB_SEL;
3147                         break;
3148                 case 1:
3149                         temp |= TRANSB_DPLL_ENABLE;
3150                         sel = TRANSB_DPLLB_SEL;
3151                         break;
3152                 case 2:
3153                         temp |= TRANSC_DPLL_ENABLE;
3154                         sel = TRANSC_DPLLB_SEL;
3155                         break;
3156                 }
3157                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3158                         temp |= sel;
3159                 else
3160                         temp &= ~sel;
3161                 I915_WRITE(PCH_DPLL_SEL, temp);
3162         }
3163
3164         /* set transcoder timing, panel must allow it */
3165         assert_panel_unlocked(dev_priv, pipe);
3166         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3169
3170         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3173         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3174
3175         intel_fdi_normal_train(crtc);
3176
3177         /* For PCH DP, enable TRANS_DP_CTL */
3178         if (HAS_PCH_CPT(dev) &&
3179             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3181                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3182                 reg = TRANS_DP_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3185                           TRANS_DP_SYNC_MASK |
3186                           TRANS_DP_BPC_MASK);
3187                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188                          TRANS_DP_ENH_FRAMING);
3189                 temp |= bpc << 9; /* same format but at 11:9 */
3190
3191                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3192                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3193                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3194                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3195
3196                 switch (intel_trans_dp_port_sel(crtc)) {
3197                 case PCH_DP_B:
3198                         temp |= TRANS_DP_PORT_SEL_B;
3199                         break;
3200                 case PCH_DP_C:
3201                         temp |= TRANS_DP_PORT_SEL_C;
3202                         break;
3203                 case PCH_DP_D:
3204                         temp |= TRANS_DP_PORT_SEL_D;
3205                         break;
3206                 default:
3207                         BUG();
3208                 }
3209
3210                 I915_WRITE(reg, temp);
3211         }
3212
3213         ironlake_enable_pch_transcoder(dev_priv, pipe);
3214 }
3215
3216 static void lpt_pch_enable(struct drm_crtc *crtc)
3217 {
3218         struct drm_device *dev = crtc->dev;
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3222
3223         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3224
3225         lpt_program_iclkip(crtc);
3226
3227         /* Set transcoder timing. */
3228         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3229         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3230         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3231
3232         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3233         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3234         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3235         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3236
3237         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3238 }
3239
3240 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3241 {
3242         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3243
3244         if (pll == NULL)
3245                 return;
3246
3247         if (pll->refcount == 0) {
3248                 WARN(1, "bad PCH PLL refcount\n");
3249                 return;
3250         }
3251
3252         --pll->refcount;
3253         intel_crtc->pch_pll = NULL;
3254 }
3255
3256 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3257 {
3258         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3259         struct intel_pch_pll *pll;
3260         int i;
3261
3262         pll = intel_crtc->pch_pll;
3263         if (pll) {
3264                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265                               intel_crtc->base.base.id, pll->pll_reg);
3266                 goto prepare;
3267         }
3268
3269         if (HAS_PCH_IBX(dev_priv->dev)) {
3270                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271                 i = intel_crtc->pipe;
3272                 pll = &dev_priv->pch_plls[i];
3273
3274                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275                               intel_crtc->base.base.id, pll->pll_reg);
3276
3277                 goto found;
3278         }
3279
3280         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3281                 pll = &dev_priv->pch_plls[i];
3282
3283                 /* Only want to check enabled timings first */
3284                 if (pll->refcount == 0)
3285                         continue;
3286
3287                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3288                     fp == I915_READ(pll->fp0_reg)) {
3289                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290                                       intel_crtc->base.base.id,
3291                                       pll->pll_reg, pll->refcount, pll->active);
3292
3293                         goto found;
3294                 }
3295         }
3296
3297         /* Ok no matching timings, maybe there's a free one? */
3298         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3299                 pll = &dev_priv->pch_plls[i];
3300                 if (pll->refcount == 0) {
3301                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302                                       intel_crtc->base.base.id, pll->pll_reg);
3303                         goto found;
3304                 }
3305         }
3306
3307         return NULL;
3308
3309 found:
3310         intel_crtc->pch_pll = pll;
3311         pll->refcount++;
3312         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3313 prepare: /* separate function? */
3314         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3315
3316         /* Wait for the clocks to stabilize before rewriting the regs */
3317         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3318         POSTING_READ(pll->pll_reg);
3319         udelay(150);
3320
3321         I915_WRITE(pll->fp0_reg, fp);
3322         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3323         pll->on = false;
3324         return pll;
3325 }
3326
3327 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3328 {
3329         struct drm_i915_private *dev_priv = dev->dev_private;
3330         int dslreg = PIPEDSL(pipe);
3331         u32 temp;
3332
3333         temp = I915_READ(dslreg);
3334         udelay(500);
3335         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3336                 if (wait_for(I915_READ(dslreg) != temp, 5))
3337                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3338         }
3339 }
3340
3341 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3342 {
3343         struct drm_device *dev = crtc->dev;
3344         struct drm_i915_private *dev_priv = dev->dev_private;
3345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346         struct intel_encoder *encoder;
3347         int pipe = intel_crtc->pipe;
3348         int plane = intel_crtc->plane;
3349         u32 temp;
3350         bool is_pch_port;
3351
3352         WARN_ON(!crtc->enabled);
3353
3354         if (intel_crtc->active)
3355                 return;
3356
3357         intel_crtc->active = true;
3358         intel_update_watermarks(dev);
3359
3360         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3361                 temp = I915_READ(PCH_LVDS);
3362                 if ((temp & LVDS_PORT_EN) == 0)
3363                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3364         }
3365
3366         is_pch_port = ironlake_crtc_driving_pch(crtc);
3367
3368         if (is_pch_port) {
3369                 /* Note: FDI PLL enabling _must_ be done before we enable the
3370                  * cpu pipes, hence this is separate from all the other fdi/pch
3371                  * enabling. */
3372                 ironlake_fdi_pll_enable(intel_crtc);
3373         } else {
3374                 assert_fdi_tx_disabled(dev_priv, pipe);
3375                 assert_fdi_rx_disabled(dev_priv, pipe);
3376         }
3377
3378         for_each_encoder_on_crtc(dev, crtc, encoder)
3379                 if (encoder->pre_enable)
3380                         encoder->pre_enable(encoder);
3381
3382         /* Enable panel fitting for LVDS */
3383         if (dev_priv->pch_pf_size &&
3384             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3385              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3386                 /* Force use of hard-coded filter coefficients
3387                  * as some pre-programmed values are broken,
3388                  * e.g. x201.
3389                  */
3390                 if (IS_IVYBRIDGE(dev))
3391                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3392                                                  PF_PIPE_SEL_IVB(pipe));
3393                 else
3394                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3395                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3396                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3397         }
3398
3399         /*
3400          * On ILK+ LUT must be loaded before the pipe is running but with
3401          * clocks enabled
3402          */
3403         intel_crtc_load_lut(crtc);
3404
3405         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3406         intel_enable_plane(dev_priv, plane, pipe);
3407
3408         if (is_pch_port)
3409                 ironlake_pch_enable(crtc);
3410
3411         mutex_lock(&dev->struct_mutex);
3412         intel_update_fbc(dev);
3413         mutex_unlock(&dev->struct_mutex);
3414
3415         intel_crtc_update_cursor(crtc, true);
3416
3417         for_each_encoder_on_crtc(dev, crtc, encoder)
3418                 encoder->enable(encoder);
3419
3420         if (HAS_PCH_CPT(dev))
3421                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3422
3423         /*
3424          * There seems to be a race in PCH platform hw (at least on some
3425          * outputs) where an enabled pipe still completes any pageflip right
3426          * away (as if the pipe is off) instead of waiting for vblank. As soon
3427          * as the first vblank happend, everything works as expected. Hence just
3428          * wait for one vblank before returning to avoid strange things
3429          * happening.
3430          */
3431         intel_wait_for_vblank(dev, intel_crtc->pipe);
3432 }
3433
3434 static void haswell_crtc_enable(struct drm_crtc *crtc)
3435 {
3436         struct drm_device *dev = crtc->dev;
3437         struct drm_i915_private *dev_priv = dev->dev_private;
3438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439         struct intel_encoder *encoder;
3440         int pipe = intel_crtc->pipe;
3441         int plane = intel_crtc->plane;
3442         bool is_pch_port;
3443
3444         WARN_ON(!crtc->enabled);
3445
3446         if (intel_crtc->active)
3447                 return;
3448
3449         intel_crtc->active = true;
3450         intel_update_watermarks(dev);
3451
3452         is_pch_port = haswell_crtc_driving_pch(crtc);
3453
3454         if (is_pch_port)
3455                 dev_priv->display.fdi_link_train(crtc);
3456
3457         for_each_encoder_on_crtc(dev, crtc, encoder)
3458                 if (encoder->pre_enable)
3459                         encoder->pre_enable(encoder);
3460
3461         intel_ddi_enable_pipe_clock(intel_crtc);
3462
3463         /* Enable panel fitting for eDP */
3464         if (dev_priv->pch_pf_size &&
3465             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3466                 /* Force use of hard-coded filter coefficients
3467                  * as some pre-programmed values are broken,
3468                  * e.g. x201.
3469                  */
3470                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3471                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3472                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3473         }
3474
3475         /*
3476          * On ILK+ LUT must be loaded before the pipe is running but with
3477          * clocks enabled
3478          */
3479         intel_crtc_load_lut(crtc);
3480
3481         intel_ddi_set_pipe_settings(crtc);
3482         intel_ddi_enable_pipe_func(crtc);
3483
3484         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3485         intel_enable_plane(dev_priv, plane, pipe);
3486
3487         if (is_pch_port)
3488                 lpt_pch_enable(crtc);
3489
3490         mutex_lock(&dev->struct_mutex);
3491         intel_update_fbc(dev);
3492         mutex_unlock(&dev->struct_mutex);
3493
3494         intel_crtc_update_cursor(crtc, true);
3495
3496         for_each_encoder_on_crtc(dev, crtc, encoder)
3497                 encoder->enable(encoder);
3498
3499         /*
3500          * There seems to be a race in PCH platform hw (at least on some
3501          * outputs) where an enabled pipe still completes any pageflip right
3502          * away (as if the pipe is off) instead of waiting for vblank. As soon
3503          * as the first vblank happend, everything works as expected. Hence just
3504          * wait for one vblank before returning to avoid strange things
3505          * happening.
3506          */
3507         intel_wait_for_vblank(dev, intel_crtc->pipe);
3508 }
3509
3510 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3511 {
3512         struct drm_device *dev = crtc->dev;
3513         struct drm_i915_private *dev_priv = dev->dev_private;
3514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515         struct intel_encoder *encoder;
3516         int pipe = intel_crtc->pipe;
3517         int plane = intel_crtc->plane;
3518         u32 reg, temp;
3519
3520
3521         if (!intel_crtc->active)
3522                 return;
3523
3524         for_each_encoder_on_crtc(dev, crtc, encoder)
3525                 encoder->disable(encoder);
3526
3527         intel_crtc_wait_for_pending_flips(crtc);
3528         drm_vblank_off(dev, pipe);
3529         intel_crtc_update_cursor(crtc, false);
3530
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (dev_priv->cfb_plane == plane)
3534                 intel_disable_fbc(dev);
3535
3536         intel_disable_pipe(dev_priv, pipe);
3537
3538         /* Disable PF */
3539         I915_WRITE(PF_CTL(pipe), 0);
3540         I915_WRITE(PF_WIN_SZ(pipe), 0);
3541
3542         for_each_encoder_on_crtc(dev, crtc, encoder)
3543                 if (encoder->post_disable)
3544                         encoder->post_disable(encoder);
3545
3546         ironlake_fdi_disable(crtc);
3547
3548         ironlake_disable_pch_transcoder(dev_priv, pipe);
3549
3550         if (HAS_PCH_CPT(dev)) {
3551                 /* disable TRANS_DP_CTL */
3552                 reg = TRANS_DP_CTL(pipe);
3553                 temp = I915_READ(reg);
3554                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3555                 temp |= TRANS_DP_PORT_SEL_NONE;
3556                 I915_WRITE(reg, temp);
3557
3558                 /* disable DPLL_SEL */
3559                 temp = I915_READ(PCH_DPLL_SEL);
3560                 switch (pipe) {
3561                 case 0:
3562                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3563                         break;
3564                 case 1:
3565                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3566                         break;
3567                 case 2:
3568                         /* C shares PLL A or B */
3569                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3570                         break;
3571                 default:
3572                         BUG(); /* wtf */
3573                 }
3574                 I915_WRITE(PCH_DPLL_SEL, temp);
3575         }
3576
3577         /* disable PCH DPLL */
3578         intel_disable_pch_pll(intel_crtc);
3579
3580         ironlake_fdi_pll_disable(intel_crtc);
3581
3582         intel_crtc->active = false;
3583         intel_update_watermarks(dev);
3584
3585         mutex_lock(&dev->struct_mutex);
3586         intel_update_fbc(dev);
3587         mutex_unlock(&dev->struct_mutex);
3588 }
3589
3590 static void haswell_crtc_disable(struct drm_crtc *crtc)
3591 {
3592         struct drm_device *dev = crtc->dev;
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595         struct intel_encoder *encoder;
3596         int pipe = intel_crtc->pipe;
3597         int plane = intel_crtc->plane;
3598         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3599         bool is_pch_port;
3600
3601         if (!intel_crtc->active)
3602                 return;
3603
3604         is_pch_port = haswell_crtc_driving_pch(crtc);
3605
3606         for_each_encoder_on_crtc(dev, crtc, encoder)
3607                 encoder->disable(encoder);
3608
3609         intel_crtc_wait_for_pending_flips(crtc);
3610         drm_vblank_off(dev, pipe);
3611         intel_crtc_update_cursor(crtc, false);
3612
3613         intel_disable_plane(dev_priv, plane, pipe);
3614
3615         if (dev_priv->cfb_plane == plane)
3616                 intel_disable_fbc(dev);
3617
3618         intel_disable_pipe(dev_priv, pipe);
3619
3620         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3621
3622         /* Disable PF */
3623         I915_WRITE(PF_CTL(pipe), 0);
3624         I915_WRITE(PF_WIN_SZ(pipe), 0);
3625
3626         intel_ddi_disable_pipe_clock(intel_crtc);
3627
3628         for_each_encoder_on_crtc(dev, crtc, encoder)
3629                 if (encoder->post_disable)
3630                         encoder->post_disable(encoder);
3631
3632         if (is_pch_port) {
3633                 lpt_disable_pch_transcoder(dev_priv);
3634                 intel_ddi_fdi_disable(crtc);
3635         }
3636
3637         intel_crtc->active = false;
3638         intel_update_watermarks(dev);
3639
3640         mutex_lock(&dev->struct_mutex);
3641         intel_update_fbc(dev);
3642         mutex_unlock(&dev->struct_mutex);
3643 }
3644
3645 static void ironlake_crtc_off(struct drm_crtc *crtc)
3646 {
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         intel_put_pch_pll(intel_crtc);
3649 }
3650
3651 static void haswell_crtc_off(struct drm_crtc *crtc)
3652 {
3653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654
3655         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3656          * start using it. */
3657         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3658
3659         intel_ddi_put_crtc_pll(crtc);
3660 }
3661
3662 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3663 {
3664         if (!enable && intel_crtc->overlay) {
3665                 struct drm_device *dev = intel_crtc->base.dev;
3666                 struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668                 mutex_lock(&dev->struct_mutex);
3669                 dev_priv->mm.interruptible = false;
3670                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3671                 dev_priv->mm.interruptible = true;
3672                 mutex_unlock(&dev->struct_mutex);
3673         }
3674
3675         /* Let userspace switch the overlay on again. In most cases userspace
3676          * has to recompute where to put it anyway.
3677          */
3678 }
3679
3680 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3681 {
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685         struct intel_encoder *encoder;
3686         int pipe = intel_crtc->pipe;
3687         int plane = intel_crtc->plane;
3688
3689         WARN_ON(!crtc->enabled);
3690
3691         if (intel_crtc->active)
3692                 return;
3693
3694         intel_crtc->active = true;
3695         intel_update_watermarks(dev);
3696
3697         intel_enable_pll(dev_priv, pipe);
3698         intel_enable_pipe(dev_priv, pipe, false);
3699         intel_enable_plane(dev_priv, plane, pipe);
3700
3701         intel_crtc_load_lut(crtc);
3702         intel_update_fbc(dev);
3703
3704         /* Give the overlay scaler a chance to enable if it's on this pipe */
3705         intel_crtc_dpms_overlay(intel_crtc, true);
3706         intel_crtc_update_cursor(crtc, true);
3707
3708         for_each_encoder_on_crtc(dev, crtc, encoder)
3709                 encoder->enable(encoder);
3710 }
3711
3712 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717         struct intel_encoder *encoder;
3718         int pipe = intel_crtc->pipe;
3719         int plane = intel_crtc->plane;
3720
3721
3722         if (!intel_crtc->active)
3723                 return;
3724
3725         for_each_encoder_on_crtc(dev, crtc, encoder)
3726                 encoder->disable(encoder);
3727
3728         /* Give the overlay scaler a chance to disable if it's on this pipe */
3729         intel_crtc_wait_for_pending_flips(crtc);
3730         drm_vblank_off(dev, pipe);
3731         intel_crtc_dpms_overlay(intel_crtc, false);
3732         intel_crtc_update_cursor(crtc, false);
3733
3734         if (dev_priv->cfb_plane == plane)
3735                 intel_disable_fbc(dev);
3736
3737         intel_disable_plane(dev_priv, plane, pipe);
3738         intel_disable_pipe(dev_priv, pipe);
3739         intel_disable_pll(dev_priv, pipe);
3740
3741         intel_crtc->active = false;
3742         intel_update_fbc(dev);
3743         intel_update_watermarks(dev);
3744 }
3745
3746 static void i9xx_crtc_off(struct drm_crtc *crtc)
3747 {
3748 }
3749
3750 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3751                                     bool enabled)
3752 {
3753         struct drm_device *dev = crtc->dev;
3754         struct drm_i915_master_private *master_priv;
3755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756         int pipe = intel_crtc->pipe;
3757
3758         if (!dev->primary->master)
3759                 return;
3760
3761         master_priv = dev->primary->master->driver_priv;
3762         if (!master_priv->sarea_priv)
3763                 return;
3764
3765         switch (pipe) {
3766         case 0:
3767                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3768                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3769                 break;
3770         case 1:
3771                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3772                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3773                 break;
3774         default:
3775                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3776                 break;
3777         }
3778 }
3779
3780 /**
3781  * Sets the power management mode of the pipe and plane.
3782  */
3783 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3784 {
3785         struct drm_device *dev = crtc->dev;
3786         struct drm_i915_private *dev_priv = dev->dev_private;
3787         struct intel_encoder *intel_encoder;
3788         bool enable = false;
3789
3790         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3791                 enable |= intel_encoder->connectors_active;
3792
3793         if (enable)
3794                 dev_priv->display.crtc_enable(crtc);
3795         else
3796                 dev_priv->display.crtc_disable(crtc);
3797
3798         intel_crtc_update_sarea(crtc, enable);
3799 }
3800
3801 static void intel_crtc_noop(struct drm_crtc *crtc)
3802 {
3803 }
3804
3805 static void intel_crtc_disable(struct drm_crtc *crtc)
3806 {
3807         struct drm_device *dev = crtc->dev;
3808         struct drm_connector *connector;
3809         struct drm_i915_private *dev_priv = dev->dev_private;
3810
3811         /* crtc should still be enabled when we disable it. */
3812         WARN_ON(!crtc->enabled);
3813
3814         dev_priv->display.crtc_disable(crtc);
3815         intel_crtc_update_sarea(crtc, false);
3816         dev_priv->display.off(crtc);
3817
3818         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3819         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3820
3821         if (crtc->fb) {
3822                 mutex_lock(&dev->struct_mutex);
3823                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3824                 mutex_unlock(&dev->struct_mutex);
3825                 crtc->fb = NULL;
3826         }
3827
3828         /* Update computed state. */
3829         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3830                 if (!connector->encoder || !connector->encoder->crtc)
3831                         continue;
3832
3833                 if (connector->encoder->crtc != crtc)
3834                         continue;
3835
3836                 connector->dpms = DRM_MODE_DPMS_OFF;
3837                 to_intel_encoder(connector->encoder)->connectors_active = false;
3838         }
3839 }
3840
3841 void intel_modeset_disable(struct drm_device *dev)
3842 {
3843         struct drm_crtc *crtc;
3844
3845         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3846                 if (crtc->enabled)
3847                         intel_crtc_disable(crtc);
3848         }
3849 }
3850
3851 void intel_encoder_noop(struct drm_encoder *encoder)
3852 {
3853 }
3854
3855 void intel_encoder_destroy(struct drm_encoder *encoder)
3856 {
3857         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3858
3859         drm_encoder_cleanup(encoder);
3860         kfree(intel_encoder);
3861 }
3862
3863 /* Simple dpms helper for encodres with just one connector, no cloning and only
3864  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3865  * state of the entire output pipe. */
3866 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3867 {
3868         if (mode == DRM_MODE_DPMS_ON) {
3869                 encoder->connectors_active = true;
3870
3871                 intel_crtc_update_dpms(encoder->base.crtc);
3872         } else {
3873                 encoder->connectors_active = false;
3874
3875                 intel_crtc_update_dpms(encoder->base.crtc);
3876         }
3877 }
3878
3879 /* Cross check the actual hw state with our own modeset state tracking (and it's
3880  * internal consistency). */
3881 static void intel_connector_check_state(struct intel_connector *connector)
3882 {
3883         if (connector->get_hw_state(connector)) {
3884                 struct intel_encoder *encoder = connector->encoder;
3885                 struct drm_crtc *crtc;
3886                 bool encoder_enabled;
3887                 enum pipe pipe;
3888
3889                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3890                               connector->base.base.id,
3891                               drm_get_connector_name(&connector->base));
3892
3893                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3894                      "wrong connector dpms state\n");
3895                 WARN(connector->base.encoder != &encoder->base,
3896                      "active connector not linked to encoder\n");
3897                 WARN(!encoder->connectors_active,
3898                      "encoder->connectors_active not set\n");
3899
3900                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3901                 WARN(!encoder_enabled, "encoder not enabled\n");
3902                 if (WARN_ON(!encoder->base.crtc))
3903                         return;
3904
3905                 crtc = encoder->base.crtc;
3906
3907                 WARN(!crtc->enabled, "crtc not enabled\n");
3908                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3909                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3910                      "encoder active on the wrong pipe\n");
3911         }
3912 }
3913
3914 /* Even simpler default implementation, if there's really no special case to
3915  * consider. */
3916 void intel_connector_dpms(struct drm_connector *connector, int mode)
3917 {
3918         struct intel_encoder *encoder = intel_attached_encoder(connector);
3919
3920         /* All the simple cases only support two dpms states. */
3921         if (mode != DRM_MODE_DPMS_ON)
3922                 mode = DRM_MODE_DPMS_OFF;
3923
3924         if (mode == connector->dpms)
3925                 return;
3926
3927         connector->dpms = mode;
3928
3929         /* Only need to change hw state when actually enabled */
3930         if (encoder->base.crtc)
3931                 intel_encoder_dpms(encoder, mode);
3932         else
3933                 WARN_ON(encoder->connectors_active != false);
3934
3935         intel_modeset_check_state(connector->dev);
3936 }
3937
3938 /* Simple connector->get_hw_state implementation for encoders that support only
3939  * one connector and no cloning and hence the encoder state determines the state
3940  * of the connector. */
3941 bool intel_connector_get_hw_state(struct intel_connector *connector)
3942 {
3943         enum pipe pipe = 0;
3944         struct intel_encoder *encoder = connector->encoder;
3945
3946         return encoder->get_hw_state(encoder, &pipe);
3947 }
3948
3949 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3950                                   const struct drm_display_mode *mode,
3951                                   struct drm_display_mode *adjusted_mode)
3952 {
3953         struct drm_device *dev = crtc->dev;
3954
3955         if (HAS_PCH_SPLIT(dev)) {
3956                 /* FDI link clock is fixed at 2.7G */
3957                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3958                         return false;
3959         }
3960
3961         /* All interlaced capable intel hw wants timings in frames. Note though
3962          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3963          * timings, so we need to be careful not to clobber these.*/
3964         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3965                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3966
3967         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3968          * with a hsync front porch of 0.
3969          */
3970         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3971                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3972                 return false;
3973
3974         return true;
3975 }
3976
3977 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3978 {
3979         return 400000; /* FIXME */
3980 }
3981
3982 static int i945_get_display_clock_speed(struct drm_device *dev)
3983 {
3984         return 400000;
3985 }
3986
3987 static int i915_get_display_clock_speed(struct drm_device *dev)
3988 {
3989         return 333000;
3990 }
3991
3992 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3993 {
3994         return 200000;
3995 }
3996
3997 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3998 {
3999         u16 gcfgc = 0;
4000
4001         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4002
4003         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4004                 return 133000;
4005         else {
4006                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4007                 case GC_DISPLAY_CLOCK_333_MHZ:
4008                         return 333000;
4009                 default:
4010                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4011                         return 190000;
4012                 }
4013         }
4014 }
4015
4016 static int i865_get_display_clock_speed(struct drm_device *dev)
4017 {
4018         return 266000;
4019 }
4020
4021 static int i855_get_display_clock_speed(struct drm_device *dev)
4022 {
4023         u16 hpllcc = 0;
4024         /* Assume that the hardware is in the high speed state.  This
4025          * should be the default.
4026          */
4027         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4028         case GC_CLOCK_133_200:
4029         case GC_CLOCK_100_200:
4030                 return 200000;
4031         case GC_CLOCK_166_250:
4032                 return 250000;
4033         case GC_CLOCK_100_133:
4034                 return 133000;
4035         }
4036
4037         /* Shouldn't happen */
4038         return 0;
4039 }
4040
4041 static int i830_get_display_clock_speed(struct drm_device *dev)
4042 {
4043         return 133000;
4044 }
4045
4046 struct fdi_m_n {
4047         u32        tu;
4048         u32        gmch_m;
4049         u32        gmch_n;
4050         u32        link_m;
4051         u32        link_n;
4052 };
4053
4054 static void
4055 fdi_reduce_ratio(u32 *num, u32 *den)
4056 {
4057         while (*num > 0xffffff || *den > 0xffffff) {
4058                 *num >>= 1;
4059                 *den >>= 1;
4060         }
4061 }
4062
4063 static void
4064 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4065                      int link_clock, struct fdi_m_n *m_n)
4066 {
4067         m_n->tu = 64; /* default size */
4068
4069         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4070         m_n->gmch_m = bits_per_pixel * pixel_clock;
4071         m_n->gmch_n = link_clock * nlanes * 8;
4072         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4073
4074         m_n->link_m = pixel_clock;
4075         m_n->link_n = link_clock;
4076         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4077 }
4078
4079 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4080 {
4081         if (i915_panel_use_ssc >= 0)
4082                 return i915_panel_use_ssc != 0;
4083         return dev_priv->lvds_use_ssc
4084                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4085 }
4086
4087 /**
4088  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4089  * @crtc: CRTC structure
4090  * @mode: requested mode
4091  *
4092  * A pipe may be connected to one or more outputs.  Based on the depth of the
4093  * attached framebuffer, choose a good color depth to use on the pipe.
4094  *
4095  * If possible, match the pipe depth to the fb depth.  In some cases, this
4096  * isn't ideal, because the connected output supports a lesser or restricted
4097  * set of depths.  Resolve that here:
4098  *    LVDS typically supports only 6bpc, so clamp down in that case
4099  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4100  *    Displays may support a restricted set as well, check EDID and clamp as
4101  *      appropriate.
4102  *    DP may want to dither down to 6bpc to fit larger modes
4103  *
4104  * RETURNS:
4105  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4106  * true if they don't match).
4107  */
4108 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4109                                          struct drm_framebuffer *fb,
4110                                          unsigned int *pipe_bpp,
4111                                          struct drm_display_mode *mode)
4112 {
4113         struct drm_device *dev = crtc->dev;
4114         struct drm_i915_private *dev_priv = dev->dev_private;
4115         struct drm_connector *connector;
4116         struct intel_encoder *intel_encoder;
4117         unsigned int display_bpc = UINT_MAX, bpc;
4118
4119         /* Walk the encoders & connectors on this crtc, get min bpc */
4120         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4121
4122                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4123                         unsigned int lvds_bpc;
4124
4125                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4126                             LVDS_A3_POWER_UP)
4127                                 lvds_bpc = 8;
4128                         else
4129                                 lvds_bpc = 6;
4130
4131                         if (lvds_bpc < display_bpc) {
4132                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4133                                 display_bpc = lvds_bpc;
4134                         }
4135                         continue;
4136                 }
4137
4138                 /* Not one of the known troublemakers, check the EDID */
4139                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4140                                     head) {
4141                         if (connector->encoder != &intel_encoder->base)
4142                                 continue;
4143
4144                         /* Don't use an invalid EDID bpc value */
4145                         if (connector->display_info.bpc &&
4146                             connector->display_info.bpc < display_bpc) {
4147                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4148                                 display_bpc = connector->display_info.bpc;
4149                         }
4150                 }
4151
4152                 /*
4153                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4154                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4155                  */
4156                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4157                         if (display_bpc > 8 && display_bpc < 12) {
4158                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4159                                 display_bpc = 12;
4160                         } else {
4161                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4162                                 display_bpc = 8;
4163                         }
4164                 }
4165         }
4166
4167         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4168                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4169                 display_bpc = 6;
4170         }
4171
4172         /*
4173          * We could just drive the pipe at the highest bpc all the time and
4174          * enable dithering as needed, but that costs bandwidth.  So choose
4175          * the minimum value that expresses the full color range of the fb but
4176          * also stays within the max display bpc discovered above.
4177          */
4178
4179         switch (fb->depth) {
4180         case 8:
4181                 bpc = 8; /* since we go through a colormap */
4182                 break;
4183         case 15:
4184         case 16:
4185                 bpc = 6; /* min is 18bpp */
4186                 break;
4187         case 24:
4188                 bpc = 8;
4189                 break;
4190         case 30:
4191                 bpc = 10;
4192                 break;
4193         case 48:
4194                 bpc = 12;
4195                 break;
4196         default:
4197                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4198                 bpc = min((unsigned int)8, display_bpc);
4199                 break;
4200         }
4201
4202         display_bpc = min(display_bpc, bpc);
4203
4204         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4205                       bpc, display_bpc);
4206
4207         *pipe_bpp = display_bpc * 3;
4208
4209         return display_bpc != bpc;
4210 }
4211
4212 static int vlv_get_refclk(struct drm_crtc *crtc)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         int refclk = 27000; /* for DP & HDMI */
4217
4218         return 100000; /* only one validated so far */
4219
4220         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4221                 refclk = 96000;
4222         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4223                 if (intel_panel_use_ssc(dev_priv))
4224                         refclk = 100000;
4225                 else
4226                         refclk = 96000;
4227         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4228                 refclk = 100000;
4229         }
4230
4231         return refclk;
4232 }
4233
4234 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         int refclk;
4239
4240         if (IS_VALLEYVIEW(dev)) {
4241                 refclk = vlv_get_refclk(crtc);
4242         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4243             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4244                 refclk = dev_priv->lvds_ssc_freq * 1000;
4245                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4246                               refclk / 1000);
4247         } else if (!IS_GEN2(dev)) {
4248                 refclk = 96000;
4249         } else {
4250                 refclk = 48000;
4251         }
4252
4253         return refclk;
4254 }
4255
4256 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4257                                       intel_clock_t *clock)
4258 {
4259         /* SDVO TV has fixed PLL values depend on its clock range,
4260            this mirrors vbios setting. */
4261         if (adjusted_mode->clock >= 100000
4262             && adjusted_mode->clock < 140500) {
4263                 clock->p1 = 2;
4264                 clock->p2 = 10;
4265                 clock->n = 3;
4266                 clock->m1 = 16;
4267                 clock->m2 = 8;
4268         } else if (adjusted_mode->clock >= 140500
4269                    && adjusted_mode->clock <= 200000) {
4270                 clock->p1 = 1;
4271                 clock->p2 = 10;
4272                 clock->n = 6;
4273                 clock->m1 = 12;
4274                 clock->m2 = 8;
4275         }
4276 }
4277
4278 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4279                                      intel_clock_t *clock,
4280                                      intel_clock_t *reduced_clock)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285         int pipe = intel_crtc->pipe;
4286         u32 fp, fp2 = 0;
4287
4288         if (IS_PINEVIEW(dev)) {
4289                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4290                 if (reduced_clock)
4291                         fp2 = (1 << reduced_clock->n) << 16 |
4292                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4293         } else {
4294                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4295                 if (reduced_clock)
4296                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4297                                 reduced_clock->m2;
4298         }
4299
4300         I915_WRITE(FP0(pipe), fp);
4301
4302         intel_crtc->lowfreq_avail = false;
4303         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4304             reduced_clock && i915_powersave) {
4305                 I915_WRITE(FP1(pipe), fp2);
4306                 intel_crtc->lowfreq_avail = true;
4307         } else {
4308                 I915_WRITE(FP1(pipe), fp);
4309         }
4310 }
4311
4312 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4313                               struct drm_display_mode *adjusted_mode)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4318         int pipe = intel_crtc->pipe;
4319         u32 temp;
4320
4321         temp = I915_READ(LVDS);
4322         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4323         if (pipe == 1) {
4324                 temp |= LVDS_PIPEB_SELECT;
4325         } else {
4326                 temp &= ~LVDS_PIPEB_SELECT;
4327         }
4328         /* set the corresponsding LVDS_BORDER bit */
4329         temp |= dev_priv->lvds_border_bits;
4330         /* Set the B0-B3 data pairs corresponding to whether we're going to
4331          * set the DPLLs for dual-channel mode or not.
4332          */
4333         if (clock->p2 == 7)
4334                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4335         else
4336                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4337
4338         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4339          * appropriately here, but we need to look more thoroughly into how
4340          * panels behave in the two modes.
4341          */
4342         /* set the dithering flag on LVDS as needed */
4343         if (INTEL_INFO(dev)->gen >= 4) {
4344                 if (dev_priv->lvds_dither)
4345                         temp |= LVDS_ENABLE_DITHER;
4346                 else
4347                         temp &= ~LVDS_ENABLE_DITHER;
4348         }
4349         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4350         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4351                 temp |= LVDS_HSYNC_POLARITY;
4352         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4353                 temp |= LVDS_VSYNC_POLARITY;
4354         I915_WRITE(LVDS, temp);
4355 }
4356
4357 static void vlv_update_pll(struct drm_crtc *crtc,
4358                            struct drm_display_mode *mode,
4359                            struct drm_display_mode *adjusted_mode,
4360                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4361                            int num_connectors)
4362 {
4363         struct drm_device *dev = crtc->dev;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366         int pipe = intel_crtc->pipe;
4367         u32 dpll, mdiv, pdiv;
4368         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4369         bool is_sdvo;
4370         u32 temp;
4371
4372         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4373                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4374
4375         dpll = DPLL_VGA_MODE_DIS;
4376         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4377         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4378         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4379
4380         I915_WRITE(DPLL(pipe), dpll);
4381         POSTING_READ(DPLL(pipe));
4382
4383         bestn = clock->n;
4384         bestm1 = clock->m1;
4385         bestm2 = clock->m2;
4386         bestp1 = clock->p1;
4387         bestp2 = clock->p2;
4388
4389         /*
4390          * In Valleyview PLL and program lane counter registers are exposed
4391          * through DPIO interface
4392          */
4393         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4394         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4395         mdiv |= ((bestn << DPIO_N_SHIFT));
4396         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4397         mdiv |= (1 << DPIO_K_SHIFT);
4398         mdiv |= DPIO_ENABLE_CALIBRATION;
4399         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4400
4401         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4402
4403         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4404                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4405                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4406                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4407         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4408
4409         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4410
4411         dpll |= DPLL_VCO_ENABLE;
4412         I915_WRITE(DPLL(pipe), dpll);
4413         POSTING_READ(DPLL(pipe));
4414         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4415                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4416
4417         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4418
4419         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4420                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4421
4422         I915_WRITE(DPLL(pipe), dpll);
4423
4424         /* Wait for the clocks to stabilize. */
4425         POSTING_READ(DPLL(pipe));
4426         udelay(150);
4427
4428         temp = 0;
4429         if (is_sdvo) {
4430                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4431                 if (temp > 1)
4432                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4433                 else
4434                         temp = 0;
4435         }
4436         I915_WRITE(DPLL_MD(pipe), temp);
4437         POSTING_READ(DPLL_MD(pipe));
4438
4439         /* Now program lane control registers */
4440         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4441                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4442         {
4443                 temp = 0x1000C4;
4444                 if(pipe == 1)
4445                         temp |= (1 << 21);
4446                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4447         }
4448         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4449         {
4450                 temp = 0x1000C4;
4451                 if(pipe == 1)
4452                         temp |= (1 << 21);
4453                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4454         }
4455 }
4456
4457 static void i9xx_update_pll(struct drm_crtc *crtc,
4458                             struct drm_display_mode *mode,
4459                             struct drm_display_mode *adjusted_mode,
4460                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4461                             int num_connectors)
4462 {
4463         struct drm_device *dev = crtc->dev;
4464         struct drm_i915_private *dev_priv = dev->dev_private;
4465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4466         int pipe = intel_crtc->pipe;
4467         u32 dpll;
4468         bool is_sdvo;
4469
4470         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4471
4472         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4473                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4474
4475         dpll = DPLL_VGA_MODE_DIS;
4476
4477         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4478                 dpll |= DPLLB_MODE_LVDS;
4479         else
4480                 dpll |= DPLLB_MODE_DAC_SERIAL;
4481         if (is_sdvo) {
4482                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4483                 if (pixel_multiplier > 1) {
4484                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4485                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4486                 }
4487                 dpll |= DPLL_DVO_HIGH_SPEED;
4488         }
4489         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4490                 dpll |= DPLL_DVO_HIGH_SPEED;
4491
4492         /* compute bitmask from p1 value */
4493         if (IS_PINEVIEW(dev))
4494                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4495         else {
4496                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4497                 if (IS_G4X(dev) && reduced_clock)
4498                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4499         }
4500         switch (clock->p2) {
4501         case 5:
4502                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4503                 break;
4504         case 7:
4505                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4506                 break;
4507         case 10:
4508                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4509                 break;
4510         case 14:
4511                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4512                 break;
4513         }
4514         if (INTEL_INFO(dev)->gen >= 4)
4515                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4516
4517         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4518                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4519         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4520                 /* XXX: just matching BIOS for now */
4521                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4522                 dpll |= 3;
4523         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4524                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4525                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4526         else
4527                 dpll |= PLL_REF_INPUT_DREFCLK;
4528
4529         dpll |= DPLL_VCO_ENABLE;
4530         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4531         POSTING_READ(DPLL(pipe));
4532         udelay(150);
4533
4534         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4535          * This is an exception to the general rule that mode_set doesn't turn
4536          * things on.
4537          */
4538         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4539                 intel_update_lvds(crtc, clock, adjusted_mode);
4540
4541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4542                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4543
4544         I915_WRITE(DPLL(pipe), dpll);
4545
4546         /* Wait for the clocks to stabilize. */
4547         POSTING_READ(DPLL(pipe));
4548         udelay(150);
4549
4550         if (INTEL_INFO(dev)->gen >= 4) {
4551                 u32 temp = 0;
4552                 if (is_sdvo) {
4553                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4554                         if (temp > 1)
4555                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4556                         else
4557                                 temp = 0;
4558                 }
4559                 I915_WRITE(DPLL_MD(pipe), temp);
4560         } else {
4561                 /* The pixel multiplier can only be updated once the
4562                  * DPLL is enabled and the clocks are stable.
4563                  *
4564                  * So write it again.
4565                  */
4566                 I915_WRITE(DPLL(pipe), dpll);
4567         }
4568 }
4569
4570 static void i8xx_update_pll(struct drm_crtc *crtc,
4571                             struct drm_display_mode *adjusted_mode,
4572                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4573                             int num_connectors)
4574 {
4575         struct drm_device *dev = crtc->dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4578         int pipe = intel_crtc->pipe;
4579         u32 dpll;
4580
4581         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4582
4583         dpll = DPLL_VGA_MODE_DIS;
4584
4585         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4586                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4587         } else {
4588                 if (clock->p1 == 2)
4589                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4590                 else
4591                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592                 if (clock->p2 == 4)
4593                         dpll |= PLL_P2_DIVIDE_BY_4;
4594         }
4595
4596         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4597                 /* XXX: just matching BIOS for now */
4598                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4599                 dpll |= 3;
4600         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4601                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4602                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4603         else
4604                 dpll |= PLL_REF_INPUT_DREFCLK;
4605
4606         dpll |= DPLL_VCO_ENABLE;
4607         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4608         POSTING_READ(DPLL(pipe));
4609         udelay(150);
4610
4611         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4612          * This is an exception to the general rule that mode_set doesn't turn
4613          * things on.
4614          */
4615         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4616                 intel_update_lvds(crtc, clock, adjusted_mode);
4617
4618         I915_WRITE(DPLL(pipe), dpll);
4619
4620         /* Wait for the clocks to stabilize. */
4621         POSTING_READ(DPLL(pipe));
4622         udelay(150);
4623
4624         /* The pixel multiplier can only be updated once the
4625          * DPLL is enabled and the clocks are stable.
4626          *
4627          * So write it again.
4628          */
4629         I915_WRITE(DPLL(pipe), dpll);
4630 }
4631
4632 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4633                                    struct drm_display_mode *mode,
4634                                    struct drm_display_mode *adjusted_mode)
4635 {
4636         struct drm_device *dev = intel_crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         enum pipe pipe = intel_crtc->pipe;
4639         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4640         uint32_t vsyncshift;
4641
4642         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4643                 /* the chip adds 2 halflines automatically */
4644                 adjusted_mode->crtc_vtotal -= 1;
4645                 adjusted_mode->crtc_vblank_end -= 1;
4646                 vsyncshift = adjusted_mode->crtc_hsync_start
4647                              - adjusted_mode->crtc_htotal / 2;
4648         } else {
4649                 vsyncshift = 0;
4650         }
4651
4652         if (INTEL_INFO(dev)->gen > 3)
4653                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4654
4655         I915_WRITE(HTOTAL(cpu_transcoder),
4656                    (adjusted_mode->crtc_hdisplay - 1) |
4657                    ((adjusted_mode->crtc_htotal - 1) << 16));
4658         I915_WRITE(HBLANK(cpu_transcoder),
4659                    (adjusted_mode->crtc_hblank_start - 1) |
4660                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4661         I915_WRITE(HSYNC(cpu_transcoder),
4662                    (adjusted_mode->crtc_hsync_start - 1) |
4663                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4664
4665         I915_WRITE(VTOTAL(cpu_transcoder),
4666                    (adjusted_mode->crtc_vdisplay - 1) |
4667                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4668         I915_WRITE(VBLANK(cpu_transcoder),
4669                    (adjusted_mode->crtc_vblank_start - 1) |
4670                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4671         I915_WRITE(VSYNC(cpu_transcoder),
4672                    (adjusted_mode->crtc_vsync_start - 1) |
4673                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4674
4675         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4676          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4677          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4678          * bits. */
4679         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4680             (pipe == PIPE_B || pipe == PIPE_C))
4681                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4682
4683         /* pipesrc controls the size that is scaled from, which should
4684          * always be the user's requested size.
4685          */
4686         I915_WRITE(PIPESRC(pipe),
4687                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4688 }
4689
4690 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4691                               struct drm_display_mode *mode,
4692                               struct drm_display_mode *adjusted_mode,
4693                               int x, int y,
4694                               struct drm_framebuffer *fb)
4695 {
4696         struct drm_device *dev = crtc->dev;
4697         struct drm_i915_private *dev_priv = dev->dev_private;
4698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699         int pipe = intel_crtc->pipe;
4700         int plane = intel_crtc->plane;
4701         int refclk, num_connectors = 0;
4702         intel_clock_t clock, reduced_clock;
4703         u32 dspcntr, pipeconf;
4704         bool ok, has_reduced_clock = false, is_sdvo = false;
4705         bool is_lvds = false, is_tv = false, is_dp = false;
4706         struct intel_encoder *encoder;
4707         const intel_limit_t *limit;
4708         int ret;
4709
4710         for_each_encoder_on_crtc(dev, crtc, encoder) {
4711                 switch (encoder->type) {
4712                 case INTEL_OUTPUT_LVDS:
4713                         is_lvds = true;
4714                         break;
4715                 case INTEL_OUTPUT_SDVO:
4716                 case INTEL_OUTPUT_HDMI:
4717                         is_sdvo = true;
4718                         if (encoder->needs_tv_clock)
4719                                 is_tv = true;
4720                         break;
4721                 case INTEL_OUTPUT_TVOUT:
4722                         is_tv = true;
4723                         break;
4724                 case INTEL_OUTPUT_DISPLAYPORT:
4725                         is_dp = true;
4726                         break;
4727                 }
4728
4729                 num_connectors++;
4730         }
4731
4732         refclk = i9xx_get_refclk(crtc, num_connectors);
4733
4734         /*
4735          * Returns a set of divisors for the desired target clock with the given
4736          * refclk, or FALSE.  The returned values represent the clock equation:
4737          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4738          */
4739         limit = intel_limit(crtc, refclk);
4740         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4741                              &clock);
4742         if (!ok) {
4743                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4744                 return -EINVAL;
4745         }
4746
4747         /* Ensure that the cursor is valid for the new mode before changing... */
4748         intel_crtc_update_cursor(crtc, true);
4749
4750         if (is_lvds && dev_priv->lvds_downclock_avail) {
4751                 /*
4752                  * Ensure we match the reduced clock's P to the target clock.
4753                  * If the clocks don't match, we can't switch the display clock
4754                  * by using the FP0/FP1. In such case we will disable the LVDS
4755                  * downclock feature.
4756                 */
4757                 has_reduced_clock = limit->find_pll(limit, crtc,
4758                                                     dev_priv->lvds_downclock,
4759                                                     refclk,
4760                                                     &clock,
4761                                                     &reduced_clock);
4762         }
4763
4764         if (is_sdvo && is_tv)
4765                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4766
4767         if (IS_GEN2(dev))
4768                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4769                                 has_reduced_clock ? &reduced_clock : NULL,
4770                                 num_connectors);
4771         else if (IS_VALLEYVIEW(dev))
4772                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4773                                 has_reduced_clock ? &reduced_clock : NULL,
4774                                 num_connectors);
4775         else
4776                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4777                                 has_reduced_clock ? &reduced_clock : NULL,
4778                                 num_connectors);
4779
4780         /* setup pipeconf */
4781         pipeconf = I915_READ(PIPECONF(pipe));
4782
4783         /* Set up the display plane register */
4784         dspcntr = DISPPLANE_GAMMA_ENABLE;
4785
4786         if (pipe == 0)
4787                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4788         else
4789                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4790
4791         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4792                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4793                  * core speed.
4794                  *
4795                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4796                  * pipe == 0 check?
4797                  */
4798                 if (mode->clock >
4799                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4800                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4801                 else
4802                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4803         }
4804
4805         /* default to 8bpc */
4806         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4807         if (is_dp) {
4808                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4809                         pipeconf |= PIPECONF_BPP_6 |
4810                                     PIPECONF_DITHER_EN |
4811                                     PIPECONF_DITHER_TYPE_SP;
4812                 }
4813         }
4814
4815         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4816                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4817                         pipeconf |= PIPECONF_BPP_6 |
4818                                         PIPECONF_ENABLE |
4819                                         I965_PIPECONF_ACTIVE;
4820                 }
4821         }
4822
4823         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4824         drm_mode_debug_printmodeline(mode);
4825
4826         if (HAS_PIPE_CXSR(dev)) {
4827                 if (intel_crtc->lowfreq_avail) {
4828                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4829                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4830                 } else {
4831                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4832                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4833                 }
4834         }
4835
4836         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4837         if (!IS_GEN2(dev) &&
4838             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4839                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4840         else
4841                 pipeconf |= PIPECONF_PROGRESSIVE;
4842
4843         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4844
4845         /* pipesrc and dspsize control the size that is scaled from,
4846          * which should always be the user's requested size.
4847          */
4848         I915_WRITE(DSPSIZE(plane),
4849                    ((mode->vdisplay - 1) << 16) |
4850                    (mode->hdisplay - 1));
4851         I915_WRITE(DSPPOS(plane), 0);
4852
4853         I915_WRITE(PIPECONF(pipe), pipeconf);
4854         POSTING_READ(PIPECONF(pipe));
4855         intel_enable_pipe(dev_priv, pipe, false);
4856
4857         intel_wait_for_vblank(dev, pipe);
4858
4859         I915_WRITE(DSPCNTR(plane), dspcntr);
4860         POSTING_READ(DSPCNTR(plane));
4861
4862         ret = intel_pipe_set_base(crtc, x, y, fb);
4863
4864         intel_update_watermarks(dev);
4865
4866         return ret;
4867 }
4868
4869 /*
4870  * Initialize reference clocks when the driver loads
4871  */
4872 void ironlake_init_pch_refclk(struct drm_device *dev)
4873 {
4874         struct drm_i915_private *dev_priv = dev->dev_private;
4875         struct drm_mode_config *mode_config = &dev->mode_config;
4876         struct intel_encoder *encoder;
4877         u32 temp;
4878         bool has_lvds = false;
4879         bool has_cpu_edp = false;
4880         bool has_pch_edp = false;
4881         bool has_panel = false;
4882         bool has_ck505 = false;
4883         bool can_ssc = false;
4884
4885         /* We need to take the global config into account */
4886         list_for_each_entry(encoder, &mode_config->encoder_list,
4887                             base.head) {
4888                 switch (encoder->type) {
4889                 case INTEL_OUTPUT_LVDS:
4890                         has_panel = true;
4891                         has_lvds = true;
4892                         break;
4893                 case INTEL_OUTPUT_EDP:
4894                         has_panel = true;
4895                         if (intel_encoder_is_pch_edp(&encoder->base))
4896                                 has_pch_edp = true;
4897                         else
4898                                 has_cpu_edp = true;
4899                         break;
4900                 }
4901         }
4902
4903         if (HAS_PCH_IBX(dev)) {
4904                 has_ck505 = dev_priv->display_clock_mode;
4905                 can_ssc = has_ck505;
4906         } else {
4907                 has_ck505 = false;
4908                 can_ssc = true;
4909         }
4910
4911         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4912                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4913                       has_ck505);
4914
4915         /* Ironlake: try to setup display ref clock before DPLL
4916          * enabling. This is only under driver's control after
4917          * PCH B stepping, previous chipset stepping should be
4918          * ignoring this setting.
4919          */
4920         temp = I915_READ(PCH_DREF_CONTROL);
4921         /* Always enable nonspread source */
4922         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4923
4924         if (has_ck505)
4925                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4926         else
4927                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4928
4929         if (has_panel) {
4930                 temp &= ~DREF_SSC_SOURCE_MASK;
4931                 temp |= DREF_SSC_SOURCE_ENABLE;
4932
4933                 /* SSC must be turned on before enabling the CPU output  */
4934                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4935                         DRM_DEBUG_KMS("Using SSC on panel\n");
4936                         temp |= DREF_SSC1_ENABLE;
4937                 } else
4938                         temp &= ~DREF_SSC1_ENABLE;
4939
4940                 /* Get SSC going before enabling the outputs */
4941                 I915_WRITE(PCH_DREF_CONTROL, temp);
4942                 POSTING_READ(PCH_DREF_CONTROL);
4943                 udelay(200);
4944
4945                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4946
4947                 /* Enable CPU source on CPU attached eDP */
4948                 if (has_cpu_edp) {
4949                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4950                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4951                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4952                         }
4953                         else
4954                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4955                 } else
4956                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4957
4958                 I915_WRITE(PCH_DREF_CONTROL, temp);
4959                 POSTING_READ(PCH_DREF_CONTROL);
4960                 udelay(200);
4961         } else {
4962                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4963
4964                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4965
4966                 /* Turn off CPU output */
4967                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4968
4969                 I915_WRITE(PCH_DREF_CONTROL, temp);
4970                 POSTING_READ(PCH_DREF_CONTROL);
4971                 udelay(200);
4972
4973                 /* Turn off the SSC source */
4974                 temp &= ~DREF_SSC_SOURCE_MASK;
4975                 temp |= DREF_SSC_SOURCE_DISABLE;
4976
4977                 /* Turn off SSC1 */
4978                 temp &= ~ DREF_SSC1_ENABLE;
4979
4980                 I915_WRITE(PCH_DREF_CONTROL, temp);
4981                 POSTING_READ(PCH_DREF_CONTROL);
4982                 udelay(200);
4983         }
4984 }
4985
4986 static int ironlake_get_refclk(struct drm_crtc *crtc)
4987 {
4988         struct drm_device *dev = crtc->dev;
4989         struct drm_i915_private *dev_priv = dev->dev_private;
4990         struct intel_encoder *encoder;
4991         struct intel_encoder *edp_encoder = NULL;
4992         int num_connectors = 0;
4993         bool is_lvds = false;
4994
4995         for_each_encoder_on_crtc(dev, crtc, encoder) {
4996                 switch (encoder->type) {
4997                 case INTEL_OUTPUT_LVDS:
4998                         is_lvds = true;
4999                         break;
5000                 case INTEL_OUTPUT_EDP:
5001                         edp_encoder = encoder;
5002                         break;
5003                 }
5004                 num_connectors++;
5005         }
5006
5007         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5008                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5009                               dev_priv->lvds_ssc_freq);
5010                 return dev_priv->lvds_ssc_freq * 1000;
5011         }
5012
5013         return 120000;
5014 }
5015
5016 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5017                                   struct drm_display_mode *adjusted_mode,
5018                                   bool dither)
5019 {
5020         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5022         int pipe = intel_crtc->pipe;
5023         uint32_t val;
5024
5025         val = I915_READ(PIPECONF(pipe));
5026
5027         val &= ~PIPE_BPC_MASK;
5028         switch (intel_crtc->bpp) {
5029         case 18:
5030                 val |= PIPE_6BPC;
5031                 break;
5032         case 24:
5033                 val |= PIPE_8BPC;
5034                 break;
5035         case 30:
5036                 val |= PIPE_10BPC;
5037                 break;
5038         case 36:
5039                 val |= PIPE_12BPC;
5040                 break;
5041         default:
5042                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5043                 BUG();
5044         }
5045
5046         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5047         if (dither)
5048                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5049
5050         val &= ~PIPECONF_INTERLACE_MASK;
5051         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5052                 val |= PIPECONF_INTERLACED_ILK;
5053         else
5054                 val |= PIPECONF_PROGRESSIVE;
5055
5056         I915_WRITE(PIPECONF(pipe), val);
5057         POSTING_READ(PIPECONF(pipe));
5058 }
5059
5060 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5061                                  struct drm_display_mode *adjusted_mode,
5062                                  bool dither)
5063 {
5064         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5067         uint32_t val;
5068
5069         val = I915_READ(PIPECONF(cpu_transcoder));
5070
5071         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5072         if (dither)
5073                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5074
5075         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5076         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5077                 val |= PIPECONF_INTERLACED_ILK;
5078         else
5079                 val |= PIPECONF_PROGRESSIVE;
5080
5081         I915_WRITE(PIPECONF(cpu_transcoder), val);
5082         POSTING_READ(PIPECONF(cpu_transcoder));
5083 }
5084
5085 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5086                                     struct drm_display_mode *adjusted_mode,
5087                                     intel_clock_t *clock,
5088                                     bool *has_reduced_clock,
5089                                     intel_clock_t *reduced_clock)
5090 {
5091         struct drm_device *dev = crtc->dev;
5092         struct drm_i915_private *dev_priv = dev->dev_private;
5093         struct intel_encoder *intel_encoder;
5094         int refclk;
5095         const intel_limit_t *limit;
5096         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5097
5098         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5099                 switch (intel_encoder->type) {
5100                 case INTEL_OUTPUT_LVDS:
5101                         is_lvds = true;
5102                         break;
5103                 case INTEL_OUTPUT_SDVO:
5104                 case INTEL_OUTPUT_HDMI:
5105                         is_sdvo = true;
5106                         if (intel_encoder->needs_tv_clock)
5107                                 is_tv = true;
5108                         break;
5109                 case INTEL_OUTPUT_TVOUT:
5110                         is_tv = true;
5111                         break;
5112                 }
5113         }
5114
5115         refclk = ironlake_get_refclk(crtc);
5116
5117         /*
5118          * Returns a set of divisors for the desired target clock with the given
5119          * refclk, or FALSE.  The returned values represent the clock equation:
5120          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5121          */
5122         limit = intel_limit(crtc, refclk);
5123         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5124                               clock);
5125         if (!ret)
5126                 return false;
5127
5128         if (is_lvds && dev_priv->lvds_downclock_avail) {
5129                 /*
5130                  * Ensure we match the reduced clock's P to the target clock.
5131                  * If the clocks don't match, we can't switch the display clock
5132                  * by using the FP0/FP1. In such case we will disable the LVDS
5133                  * downclock feature.
5134                 */
5135                 *has_reduced_clock = limit->find_pll(limit, crtc,
5136                                                      dev_priv->lvds_downclock,
5137                                                      refclk,
5138                                                      clock,
5139                                                      reduced_clock);
5140         }
5141
5142         if (is_sdvo && is_tv)
5143                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5144
5145         return true;
5146 }
5147
5148 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5149 {
5150         struct drm_i915_private *dev_priv = dev->dev_private;
5151         uint32_t temp;
5152
5153         temp = I915_READ(SOUTH_CHICKEN1);
5154         if (temp & FDI_BC_BIFURCATION_SELECT)
5155                 return;
5156
5157         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5158         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5159
5160         temp |= FDI_BC_BIFURCATION_SELECT;
5161         DRM_DEBUG_KMS("enabling fdi C rx\n");
5162         I915_WRITE(SOUTH_CHICKEN1, temp);
5163         POSTING_READ(SOUTH_CHICKEN1);
5164 }
5165
5166 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5167 {
5168         struct drm_device *dev = intel_crtc->base.dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         struct intel_crtc *pipe_B_crtc =
5171                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5172
5173         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5174                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5175         if (intel_crtc->fdi_lanes > 4) {
5176                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5177                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5178                 /* Clamp lanes to avoid programming the hw with bogus values. */
5179                 intel_crtc->fdi_lanes = 4;
5180
5181                 return false;
5182         }
5183
5184         if (dev_priv->num_pipe == 2)
5185                 return true;
5186
5187         switch (intel_crtc->pipe) {
5188         case PIPE_A:
5189                 return true;
5190         case PIPE_B:
5191                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5192                     intel_crtc->fdi_lanes > 2) {
5193                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5194                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5195                         /* Clamp lanes to avoid programming the hw with bogus values. */
5196                         intel_crtc->fdi_lanes = 2;
5197
5198                         return false;
5199                 }
5200
5201                 if (intel_crtc->fdi_lanes > 2)
5202                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5203                 else
5204                         cpt_enable_fdi_bc_bifurcation(dev);
5205
5206                 return true;
5207         case PIPE_C:
5208                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5209                         if (intel_crtc->fdi_lanes > 2) {
5210                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5211                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5212                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5213                                 intel_crtc->fdi_lanes = 2;
5214
5215                                 return false;
5216                         }
5217                 } else {
5218                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5219                         return false;
5220                 }
5221
5222                 cpt_enable_fdi_bc_bifurcation(dev);
5223
5224                 return true;
5225         default:
5226                 BUG();
5227         }
5228 }
5229
5230 static void ironlake_set_m_n(struct drm_crtc *crtc,
5231                              struct drm_display_mode *mode,
5232                              struct drm_display_mode *adjusted_mode)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5238         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5239         struct fdi_m_n m_n = {0};
5240         int target_clock, pixel_multiplier, lane, link_bw;
5241         bool is_dp = false, is_cpu_edp = false;
5242
5243         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5244                 switch (intel_encoder->type) {
5245                 case INTEL_OUTPUT_DISPLAYPORT:
5246                         is_dp = true;
5247                         break;
5248                 case INTEL_OUTPUT_EDP:
5249                         is_dp = true;
5250                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5251                                 is_cpu_edp = true;
5252                         edp_encoder = intel_encoder;
5253                         break;
5254                 }
5255         }
5256
5257         /* FDI link */
5258         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5259         lane = 0;
5260         /* CPU eDP doesn't require FDI link, so just set DP M/N
5261            according to current link config */
5262         if (is_cpu_edp) {
5263                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5264         } else {
5265                 /* FDI is a binary signal running at ~2.7GHz, encoding
5266                  * each output octet as 10 bits. The actual frequency
5267                  * is stored as a divider into a 100MHz clock, and the
5268                  * mode pixel clock is stored in units of 1KHz.
5269                  * Hence the bw of each lane in terms of the mode signal
5270                  * is:
5271                  */
5272                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5273         }
5274
5275         /* [e]DP over FDI requires target mode clock instead of link clock. */
5276         if (edp_encoder)
5277                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5278         else if (is_dp)
5279                 target_clock = mode->clock;
5280         else
5281                 target_clock = adjusted_mode->clock;
5282
5283         if (!lane) {
5284                 /*
5285                  * Account for spread spectrum to avoid
5286                  * oversubscribing the link. Max center spread
5287                  * is 2.5%; use 5% for safety's sake.
5288                  */
5289                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5290                 lane = bps / (link_bw * 8) + 1;
5291         }
5292
5293         intel_crtc->fdi_lanes = lane;
5294
5295         if (pixel_multiplier > 1)
5296                 link_bw *= pixel_multiplier;
5297         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5298                              &m_n);
5299
5300         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5301         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5302         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5303         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5304 }
5305
5306 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5307                                       struct drm_display_mode *adjusted_mode,
5308                                       intel_clock_t *clock, u32 fp)
5309 {
5310         struct drm_crtc *crtc = &intel_crtc->base;
5311         struct drm_device *dev = crtc->dev;
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         struct intel_encoder *intel_encoder;
5314         uint32_t dpll;
5315         int factor, pixel_multiplier, num_connectors = 0;
5316         bool is_lvds = false, is_sdvo = false, is_tv = false;
5317         bool is_dp = false, is_cpu_edp = false;
5318
5319         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5320                 switch (intel_encoder->type) {
5321                 case INTEL_OUTPUT_LVDS:
5322                         is_lvds = true;
5323                         break;
5324                 case INTEL_OUTPUT_SDVO:
5325                 case INTEL_OUTPUT_HDMI:
5326                         is_sdvo = true;
5327                         if (intel_encoder->needs_tv_clock)
5328                                 is_tv = true;
5329                         break;
5330                 case INTEL_OUTPUT_TVOUT:
5331                         is_tv = true;
5332                         break;
5333                 case INTEL_OUTPUT_DISPLAYPORT:
5334                         is_dp = true;
5335                         break;
5336                 case INTEL_OUTPUT_EDP:
5337                         is_dp = true;
5338                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5339                                 is_cpu_edp = true;
5340                         break;
5341                 }
5342
5343                 num_connectors++;
5344         }
5345
5346         /* Enable autotuning of the PLL clock (if permissible) */
5347         factor = 21;
5348         if (is_lvds) {
5349                 if ((intel_panel_use_ssc(dev_priv) &&
5350                      dev_priv->lvds_ssc_freq == 100) ||
5351                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5352                         factor = 25;
5353         } else if (is_sdvo && is_tv)
5354                 factor = 20;
5355
5356         if (clock->m < factor * clock->n)
5357                 fp |= FP_CB_TUNE;
5358
5359         dpll = 0;
5360
5361         if (is_lvds)
5362                 dpll |= DPLLB_MODE_LVDS;
5363         else
5364                 dpll |= DPLLB_MODE_DAC_SERIAL;
5365         if (is_sdvo) {
5366                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5367                 if (pixel_multiplier > 1) {
5368                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5369                 }
5370                 dpll |= DPLL_DVO_HIGH_SPEED;
5371         }
5372         if (is_dp && !is_cpu_edp)
5373                 dpll |= DPLL_DVO_HIGH_SPEED;
5374
5375         /* compute bitmask from p1 value */
5376         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5377         /* also FPA1 */
5378         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5379
5380         switch (clock->p2) {
5381         case 5:
5382                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5383                 break;
5384         case 7:
5385                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5386                 break;
5387         case 10:
5388                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5389                 break;
5390         case 14:
5391                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5392                 break;
5393         }
5394
5395         if (is_sdvo && is_tv)
5396                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5397         else if (is_tv)
5398                 /* XXX: just matching BIOS for now */
5399                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5400                 dpll |= 3;
5401         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5402                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5403         else
5404                 dpll |= PLL_REF_INPUT_DREFCLK;
5405
5406         return dpll;
5407 }
5408
5409 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5410                                   struct drm_display_mode *mode,
5411                                   struct drm_display_mode *adjusted_mode,
5412                                   int x, int y,
5413                                   struct drm_framebuffer *fb)
5414 {
5415         struct drm_device *dev = crtc->dev;
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418         int pipe = intel_crtc->pipe;
5419         int plane = intel_crtc->plane;
5420         int num_connectors = 0;
5421         intel_clock_t clock, reduced_clock;
5422         u32 dpll, fp = 0, fp2 = 0;
5423         bool ok, has_reduced_clock = false;
5424         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5425         struct intel_encoder *encoder;
5426         u32 temp;
5427         int ret;
5428         bool dither, fdi_config_ok;
5429
5430         for_each_encoder_on_crtc(dev, crtc, encoder) {
5431                 switch (encoder->type) {
5432                 case INTEL_OUTPUT_LVDS:
5433                         is_lvds = true;
5434                         break;
5435                 case INTEL_OUTPUT_DISPLAYPORT:
5436                         is_dp = true;
5437                         break;
5438                 case INTEL_OUTPUT_EDP:
5439                         is_dp = true;
5440                         if (!intel_encoder_is_pch_edp(&encoder->base))
5441                                 is_cpu_edp = true;
5442                         break;
5443                 }
5444
5445                 num_connectors++;
5446         }
5447
5448         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5449              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5450
5451         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5452                                      &has_reduced_clock, &reduced_clock);
5453         if (!ok) {
5454                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5455                 return -EINVAL;
5456         }
5457
5458         /* Ensure that the cursor is valid for the new mode before changing... */
5459         intel_crtc_update_cursor(crtc, true);
5460
5461         /* determine panel color depth */
5462         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5463                                               adjusted_mode);
5464         if (is_lvds && dev_priv->lvds_dither)
5465                 dither = true;
5466
5467         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5468         if (has_reduced_clock)
5469                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5470                         reduced_clock.m2;
5471
5472         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5473
5474         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5475         drm_mode_debug_printmodeline(mode);
5476
5477         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5478         if (!is_cpu_edp) {
5479                 struct intel_pch_pll *pll;
5480
5481                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5482                 if (pll == NULL) {
5483                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5484                                          pipe);
5485                         return -EINVAL;
5486                 }
5487         } else
5488                 intel_put_pch_pll(intel_crtc);
5489
5490         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5491          * This is an exception to the general rule that mode_set doesn't turn
5492          * things on.
5493          */
5494         if (is_lvds) {
5495                 temp = I915_READ(PCH_LVDS);
5496                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5497                 if (HAS_PCH_CPT(dev)) {
5498                         temp &= ~PORT_TRANS_SEL_MASK;
5499                         temp |= PORT_TRANS_SEL_CPT(pipe);
5500                 } else {
5501                         if (pipe == 1)
5502                                 temp |= LVDS_PIPEB_SELECT;
5503                         else
5504                                 temp &= ~LVDS_PIPEB_SELECT;
5505                 }
5506
5507                 /* set the corresponsding LVDS_BORDER bit */
5508                 temp |= dev_priv->lvds_border_bits;
5509                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5510                  * set the DPLLs for dual-channel mode or not.
5511                  */
5512                 if (clock.p2 == 7)
5513                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5514                 else
5515                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5516
5517                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5518                  * appropriately here, but we need to look more thoroughly into how
5519                  * panels behave in the two modes.
5520                  */
5521                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5522                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5523                         temp |= LVDS_HSYNC_POLARITY;
5524                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5525                         temp |= LVDS_VSYNC_POLARITY;
5526                 I915_WRITE(PCH_LVDS, temp);
5527         }
5528
5529         if (is_dp && !is_cpu_edp) {
5530                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5531         } else {
5532                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5533                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5534                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5535                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5536                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5537         }
5538
5539         if (intel_crtc->pch_pll) {
5540                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5541
5542                 /* Wait for the clocks to stabilize. */
5543                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5544                 udelay(150);
5545
5546                 /* The pixel multiplier can only be updated once the
5547                  * DPLL is enabled and the clocks are stable.
5548                  *
5549                  * So write it again.
5550                  */
5551                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5552         }
5553
5554         intel_crtc->lowfreq_avail = false;
5555         if (intel_crtc->pch_pll) {
5556                 if (is_lvds && has_reduced_clock && i915_powersave) {
5557                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5558                         intel_crtc->lowfreq_avail = true;
5559                 } else {
5560                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5561                 }
5562         }
5563
5564         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5565
5566         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5567          * ironlake_check_fdi_lanes. */
5568         ironlake_set_m_n(crtc, mode, adjusted_mode);
5569
5570         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5571
5572         if (is_cpu_edp)
5573                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5574
5575         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5576
5577         intel_wait_for_vblank(dev, pipe);
5578
5579         /* Set up the display plane register */
5580         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5581         POSTING_READ(DSPCNTR(plane));
5582
5583         ret = intel_pipe_set_base(crtc, x, y, fb);
5584
5585         intel_update_watermarks(dev);
5586
5587         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5588
5589         return fdi_config_ok ? ret : -EINVAL;
5590 }
5591
5592 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5593                                  struct drm_display_mode *mode,
5594                                  struct drm_display_mode *adjusted_mode,
5595                                  int x, int y,
5596                                  struct drm_framebuffer *fb)
5597 {
5598         struct drm_device *dev = crtc->dev;
5599         struct drm_i915_private *dev_priv = dev->dev_private;
5600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601         int pipe = intel_crtc->pipe;
5602         int plane = intel_crtc->plane;
5603         int num_connectors = 0;
5604         intel_clock_t clock, reduced_clock;
5605         u32 dpll = 0, fp = 0, fp2 = 0;
5606         bool ok, has_reduced_clock = false;
5607         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5608         struct intel_encoder *encoder;
5609         u32 temp;
5610         int ret;
5611         bool dither;
5612
5613         for_each_encoder_on_crtc(dev, crtc, encoder) {
5614                 switch (encoder->type) {
5615                 case INTEL_OUTPUT_LVDS:
5616                         is_lvds = true;
5617                         break;
5618                 case INTEL_OUTPUT_DISPLAYPORT:
5619                         is_dp = true;
5620                         break;
5621                 case INTEL_OUTPUT_EDP:
5622                         is_dp = true;
5623                         if (!intel_encoder_is_pch_edp(&encoder->base))
5624                                 is_cpu_edp = true;
5625                         break;
5626                 }
5627
5628                 num_connectors++;
5629         }
5630
5631         if (is_cpu_edp)
5632                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5633         else
5634                 intel_crtc->cpu_transcoder = pipe;
5635
5636         /* We are not sure yet this won't happen. */
5637         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5638              INTEL_PCH_TYPE(dev));
5639
5640         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5641              num_connectors, pipe_name(pipe));
5642
5643         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5644                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5645
5646         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5647
5648         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5649                 return -EINVAL;
5650
5651         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5652                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5653                                              &has_reduced_clock,
5654                                              &reduced_clock);
5655                 if (!ok) {
5656                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5657                         return -EINVAL;
5658                 }
5659         }
5660
5661         /* Ensure that the cursor is valid for the new mode before changing... */
5662         intel_crtc_update_cursor(crtc, true);
5663
5664         /* determine panel color depth */
5665         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5666                                               adjusted_mode);
5667         if (is_lvds && dev_priv->lvds_dither)
5668                 dither = true;
5669
5670         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5671         drm_mode_debug_printmodeline(mode);
5672
5673         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5674                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5675                 if (has_reduced_clock)
5676                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5677                               reduced_clock.m2;
5678
5679                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5680                                              fp);
5681
5682                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5683                  * own on pre-Haswell/LPT generation */
5684                 if (!is_cpu_edp) {
5685                         struct intel_pch_pll *pll;
5686
5687                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5688                         if (pll == NULL) {
5689                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5690                                                  pipe);
5691                                 return -EINVAL;
5692                         }
5693                 } else
5694                         intel_put_pch_pll(intel_crtc);
5695
5696                 /* The LVDS pin pair needs to be on before the DPLLs are
5697                  * enabled.  This is an exception to the general rule that
5698                  * mode_set doesn't turn things on.
5699                  */
5700                 if (is_lvds) {
5701                         temp = I915_READ(PCH_LVDS);
5702                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5703                         if (HAS_PCH_CPT(dev)) {
5704                                 temp &= ~PORT_TRANS_SEL_MASK;
5705                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5706                         } else {
5707                                 if (pipe == 1)
5708                                         temp |= LVDS_PIPEB_SELECT;
5709                                 else
5710                                         temp &= ~LVDS_PIPEB_SELECT;
5711                         }
5712
5713                         /* set the corresponsding LVDS_BORDER bit */
5714                         temp |= dev_priv->lvds_border_bits;
5715                         /* Set the B0-B3 data pairs corresponding to whether
5716                          * we're going to set the DPLLs for dual-channel mode or
5717                          * not.
5718                          */
5719                         if (clock.p2 == 7)
5720                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5721                         else
5722                                 temp &= ~(LVDS_B0B3_POWER_UP |
5723                                           LVDS_CLKB_POWER_UP);
5724
5725                         /* It would be nice to set 24 vs 18-bit mode
5726                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5727                          * look more thoroughly into how panels behave in the
5728                          * two modes.
5729                          */
5730                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5731                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5732                                 temp |= LVDS_HSYNC_POLARITY;
5733                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5734                                 temp |= LVDS_VSYNC_POLARITY;
5735                         I915_WRITE(PCH_LVDS, temp);
5736                 }
5737         }
5738
5739         if (is_dp && !is_cpu_edp) {
5740                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5741         } else {
5742                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5743                         /* For non-DP output, clear any trans DP clock recovery
5744                          * setting.*/
5745                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5746                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5747                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5748                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5749                 }
5750         }
5751
5752         intel_crtc->lowfreq_avail = false;
5753         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5754                 if (intel_crtc->pch_pll) {
5755                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5756
5757                         /* Wait for the clocks to stabilize. */
5758                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5759                         udelay(150);
5760
5761                         /* The pixel multiplier can only be updated once the
5762                          * DPLL is enabled and the clocks are stable.
5763                          *
5764                          * So write it again.
5765                          */
5766                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5767                 }
5768
5769                 if (intel_crtc->pch_pll) {
5770                         if (is_lvds && has_reduced_clock && i915_powersave) {
5771                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5772                                 intel_crtc->lowfreq_avail = true;
5773                         } else {
5774                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5775                         }
5776                 }
5777         }
5778
5779         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5780
5781         if (!is_dp || is_cpu_edp)
5782                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5783
5784         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5785                 if (is_cpu_edp)
5786                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5787
5788         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5789
5790         /* Set up the display plane register */
5791         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5792         POSTING_READ(DSPCNTR(plane));
5793
5794         ret = intel_pipe_set_base(crtc, x, y, fb);
5795
5796         intel_update_watermarks(dev);
5797
5798         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5799
5800         return ret;
5801 }
5802
5803 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5804                                struct drm_display_mode *mode,
5805                                struct drm_display_mode *adjusted_mode,
5806                                int x, int y,
5807                                struct drm_framebuffer *fb)
5808 {
5809         struct drm_device *dev = crtc->dev;
5810         struct drm_i915_private *dev_priv = dev->dev_private;
5811         struct drm_encoder_helper_funcs *encoder_funcs;
5812         struct intel_encoder *encoder;
5813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5814         int pipe = intel_crtc->pipe;
5815         int ret;
5816
5817         drm_vblank_pre_modeset(dev, pipe);
5818
5819         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5820                                               x, y, fb);
5821         drm_vblank_post_modeset(dev, pipe);
5822
5823         if (ret != 0)
5824                 return ret;
5825
5826         for_each_encoder_on_crtc(dev, crtc, encoder) {
5827                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5828                         encoder->base.base.id,
5829                         drm_get_encoder_name(&encoder->base),
5830                         mode->base.id, mode->name);
5831                 encoder_funcs = encoder->base.helper_private;
5832                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5833         }
5834
5835         return 0;
5836 }
5837
5838 static bool intel_eld_uptodate(struct drm_connector *connector,
5839                                int reg_eldv, uint32_t bits_eldv,
5840                                int reg_elda, uint32_t bits_elda,
5841                                int reg_edid)
5842 {
5843         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5844         uint8_t *eld = connector->eld;
5845         uint32_t i;
5846
5847         i = I915_READ(reg_eldv);
5848         i &= bits_eldv;
5849
5850         if (!eld[0])
5851                 return !i;
5852
5853         if (!i)
5854                 return false;
5855
5856         i = I915_READ(reg_elda);
5857         i &= ~bits_elda;
5858         I915_WRITE(reg_elda, i);
5859
5860         for (i = 0; i < eld[2]; i++)
5861                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5862                         return false;
5863
5864         return true;
5865 }
5866
5867 static void g4x_write_eld(struct drm_connector *connector,
5868                           struct drm_crtc *crtc)
5869 {
5870         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5871         uint8_t *eld = connector->eld;
5872         uint32_t eldv;
5873         uint32_t len;
5874         uint32_t i;
5875
5876         i = I915_READ(G4X_AUD_VID_DID);
5877
5878         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5879                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5880         else
5881                 eldv = G4X_ELDV_DEVCTG;
5882
5883         if (intel_eld_uptodate(connector,
5884                                G4X_AUD_CNTL_ST, eldv,
5885                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5886                                G4X_HDMIW_HDMIEDID))
5887                 return;
5888
5889         i = I915_READ(G4X_AUD_CNTL_ST);
5890         i &= ~(eldv | G4X_ELD_ADDR);
5891         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5892         I915_WRITE(G4X_AUD_CNTL_ST, i);
5893
5894         if (!eld[0])
5895                 return;
5896
5897         len = min_t(uint8_t, eld[2], len);
5898         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5899         for (i = 0; i < len; i++)
5900                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5901
5902         i = I915_READ(G4X_AUD_CNTL_ST);
5903         i |= eldv;
5904         I915_WRITE(G4X_AUD_CNTL_ST, i);
5905 }
5906
5907 static void haswell_write_eld(struct drm_connector *connector,
5908                                      struct drm_crtc *crtc)
5909 {
5910         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5911         uint8_t *eld = connector->eld;
5912         struct drm_device *dev = crtc->dev;
5913         uint32_t eldv;
5914         uint32_t i;
5915         int len;
5916         int pipe = to_intel_crtc(crtc)->pipe;
5917         int tmp;
5918
5919         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5920         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5921         int aud_config = HSW_AUD_CFG(pipe);
5922         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5923
5924
5925         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5926
5927         /* Audio output enable */
5928         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5929         tmp = I915_READ(aud_cntrl_st2);
5930         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5931         I915_WRITE(aud_cntrl_st2, tmp);
5932
5933         /* Wait for 1 vertical blank */
5934         intel_wait_for_vblank(dev, pipe);
5935
5936         /* Set ELD valid state */
5937         tmp = I915_READ(aud_cntrl_st2);
5938         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5939         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5940         I915_WRITE(aud_cntrl_st2, tmp);
5941         tmp = I915_READ(aud_cntrl_st2);
5942         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5943
5944         /* Enable HDMI mode */
5945         tmp = I915_READ(aud_config);
5946         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5947         /* clear N_programing_enable and N_value_index */
5948         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5949         I915_WRITE(aud_config, tmp);
5950
5951         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5952
5953         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5954
5955         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5956                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5957                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5958                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5959         } else
5960                 I915_WRITE(aud_config, 0);
5961
5962         if (intel_eld_uptodate(connector,
5963                                aud_cntrl_st2, eldv,
5964                                aud_cntl_st, IBX_ELD_ADDRESS,
5965                                hdmiw_hdmiedid))
5966                 return;
5967
5968         i = I915_READ(aud_cntrl_st2);
5969         i &= ~eldv;
5970         I915_WRITE(aud_cntrl_st2, i);
5971
5972         if (!eld[0])
5973                 return;
5974
5975         i = I915_READ(aud_cntl_st);
5976         i &= ~IBX_ELD_ADDRESS;
5977         I915_WRITE(aud_cntl_st, i);
5978         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5979         DRM_DEBUG_DRIVER("port num:%d\n", i);
5980
5981         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5982         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5983         for (i = 0; i < len; i++)
5984                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5985
5986         i = I915_READ(aud_cntrl_st2);
5987         i |= eldv;
5988         I915_WRITE(aud_cntrl_st2, i);
5989
5990 }
5991
5992 static void ironlake_write_eld(struct drm_connector *connector,
5993                                      struct drm_crtc *crtc)
5994 {
5995         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5996         uint8_t *eld = connector->eld;
5997         uint32_t eldv;
5998         uint32_t i;
5999         int len;
6000         int hdmiw_hdmiedid;
6001         int aud_config;
6002         int aud_cntl_st;
6003         int aud_cntrl_st2;
6004         int pipe = to_intel_crtc(crtc)->pipe;
6005
6006         if (HAS_PCH_IBX(connector->dev)) {
6007                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6008                 aud_config = IBX_AUD_CFG(pipe);
6009                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6010                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6011         } else {
6012                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6013                 aud_config = CPT_AUD_CFG(pipe);
6014                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6015                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6016         }
6017
6018         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6019
6020         i = I915_READ(aud_cntl_st);
6021         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6022         if (!i) {
6023                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6024                 /* operate blindly on all ports */
6025                 eldv = IBX_ELD_VALIDB;
6026                 eldv |= IBX_ELD_VALIDB << 4;
6027                 eldv |= IBX_ELD_VALIDB << 8;
6028         } else {
6029                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6030                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6031         }
6032
6033         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6034                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6035                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6036                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6037         } else
6038                 I915_WRITE(aud_config, 0);
6039
6040         if (intel_eld_uptodate(connector,
6041                                aud_cntrl_st2, eldv,
6042                                aud_cntl_st, IBX_ELD_ADDRESS,
6043                                hdmiw_hdmiedid))
6044                 return;
6045
6046         i = I915_READ(aud_cntrl_st2);
6047         i &= ~eldv;
6048         I915_WRITE(aud_cntrl_st2, i);
6049
6050         if (!eld[0])
6051                 return;
6052
6053         i = I915_READ(aud_cntl_st);
6054         i &= ~IBX_ELD_ADDRESS;
6055         I915_WRITE(aud_cntl_st, i);
6056
6057         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6058         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6059         for (i = 0; i < len; i++)
6060                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6061
6062         i = I915_READ(aud_cntrl_st2);
6063         i |= eldv;
6064         I915_WRITE(aud_cntrl_st2, i);
6065 }
6066
6067 void intel_write_eld(struct drm_encoder *encoder,
6068                      struct drm_display_mode *mode)
6069 {
6070         struct drm_crtc *crtc = encoder->crtc;
6071         struct drm_connector *connector;
6072         struct drm_device *dev = encoder->dev;
6073         struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075         connector = drm_select_eld(encoder, mode);
6076         if (!connector)
6077                 return;
6078
6079         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6080                          connector->base.id,
6081                          drm_get_connector_name(connector),
6082                          connector->encoder->base.id,
6083                          drm_get_encoder_name(connector->encoder));
6084
6085         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6086
6087         if (dev_priv->display.write_eld)
6088                 dev_priv->display.write_eld(connector, crtc);
6089 }
6090
6091 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6092 void intel_crtc_load_lut(struct drm_crtc *crtc)
6093 {
6094         struct drm_device *dev = crtc->dev;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097         int palreg = PALETTE(intel_crtc->pipe);
6098         int i;
6099
6100         /* The clocks have to be on to load the palette. */
6101         if (!crtc->enabled || !intel_crtc->active)
6102                 return;
6103
6104         /* use legacy palette for Ironlake */
6105         if (HAS_PCH_SPLIT(dev))
6106                 palreg = LGC_PALETTE(intel_crtc->pipe);
6107
6108         for (i = 0; i < 256; i++) {
6109                 I915_WRITE(palreg + 4 * i,
6110                            (intel_crtc->lut_r[i] << 16) |
6111                            (intel_crtc->lut_g[i] << 8) |
6112                            intel_crtc->lut_b[i]);
6113         }
6114 }
6115
6116 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6117 {
6118         struct drm_device *dev = crtc->dev;
6119         struct drm_i915_private *dev_priv = dev->dev_private;
6120         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6121         bool visible = base != 0;
6122         u32 cntl;
6123
6124         if (intel_crtc->cursor_visible == visible)
6125                 return;
6126
6127         cntl = I915_READ(_CURACNTR);
6128         if (visible) {
6129                 /* On these chipsets we can only modify the base whilst
6130                  * the cursor is disabled.
6131                  */
6132                 I915_WRITE(_CURABASE, base);
6133
6134                 cntl &= ~(CURSOR_FORMAT_MASK);
6135                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6136                 cntl |= CURSOR_ENABLE |
6137                         CURSOR_GAMMA_ENABLE |
6138                         CURSOR_FORMAT_ARGB;
6139         } else
6140                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6141         I915_WRITE(_CURACNTR, cntl);
6142
6143         intel_crtc->cursor_visible = visible;
6144 }
6145
6146 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6147 {
6148         struct drm_device *dev = crtc->dev;
6149         struct drm_i915_private *dev_priv = dev->dev_private;
6150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151         int pipe = intel_crtc->pipe;
6152         bool visible = base != 0;
6153
6154         if (intel_crtc->cursor_visible != visible) {
6155                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6156                 if (base) {
6157                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6158                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6159                         cntl |= pipe << 28; /* Connect to correct pipe */
6160                 } else {
6161                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6162                         cntl |= CURSOR_MODE_DISABLE;
6163                 }
6164                 I915_WRITE(CURCNTR(pipe), cntl);
6165
6166                 intel_crtc->cursor_visible = visible;
6167         }
6168         /* and commit changes on next vblank */
6169         I915_WRITE(CURBASE(pipe), base);
6170 }
6171
6172 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6173 {
6174         struct drm_device *dev = crtc->dev;
6175         struct drm_i915_private *dev_priv = dev->dev_private;
6176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6177         int pipe = intel_crtc->pipe;
6178         bool visible = base != 0;
6179
6180         if (intel_crtc->cursor_visible != visible) {
6181                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6182                 if (base) {
6183                         cntl &= ~CURSOR_MODE;
6184                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6185                 } else {
6186                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6187                         cntl |= CURSOR_MODE_DISABLE;
6188                 }
6189                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6190
6191                 intel_crtc->cursor_visible = visible;
6192         }
6193         /* and commit changes on next vblank */
6194         I915_WRITE(CURBASE_IVB(pipe), base);
6195 }
6196
6197 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6198 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6199                                      bool on)
6200 {
6201         struct drm_device *dev = crtc->dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204         int pipe = intel_crtc->pipe;
6205         int x = intel_crtc->cursor_x;
6206         int y = intel_crtc->cursor_y;
6207         u32 base, pos;
6208         bool visible;
6209
6210         pos = 0;
6211
6212         if (on && crtc->enabled && crtc->fb) {
6213                 base = intel_crtc->cursor_addr;
6214                 if (x > (int) crtc->fb->width)
6215                         base = 0;
6216
6217                 if (y > (int) crtc->fb->height)
6218                         base = 0;
6219         } else
6220                 base = 0;
6221
6222         if (x < 0) {
6223                 if (x + intel_crtc->cursor_width < 0)
6224                         base = 0;
6225
6226                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6227                 x = -x;
6228         }
6229         pos |= x << CURSOR_X_SHIFT;
6230
6231         if (y < 0) {
6232                 if (y + intel_crtc->cursor_height < 0)
6233                         base = 0;
6234
6235                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6236                 y = -y;
6237         }
6238         pos |= y << CURSOR_Y_SHIFT;
6239
6240         visible = base != 0;
6241         if (!visible && !intel_crtc->cursor_visible)
6242                 return;
6243
6244         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6245                 I915_WRITE(CURPOS_IVB(pipe), pos);
6246                 ivb_update_cursor(crtc, base);
6247         } else {
6248                 I915_WRITE(CURPOS(pipe), pos);
6249                 if (IS_845G(dev) || IS_I865G(dev))
6250                         i845_update_cursor(crtc, base);
6251                 else
6252                         i9xx_update_cursor(crtc, base);
6253         }
6254 }
6255
6256 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6257                                  struct drm_file *file,
6258                                  uint32_t handle,
6259                                  uint32_t width, uint32_t height)
6260 {
6261         struct drm_device *dev = crtc->dev;
6262         struct drm_i915_private *dev_priv = dev->dev_private;
6263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264         struct drm_i915_gem_object *obj;
6265         uint32_t addr;
6266         int ret;
6267
6268         /* if we want to turn off the cursor ignore width and height */
6269         if (!handle) {
6270                 DRM_DEBUG_KMS("cursor off\n");
6271                 addr = 0;
6272                 obj = NULL;
6273                 mutex_lock(&dev->struct_mutex);
6274                 goto finish;
6275         }
6276
6277         /* Currently we only support 64x64 cursors */
6278         if (width != 64 || height != 64) {
6279                 DRM_ERROR("we currently only support 64x64 cursors\n");
6280                 return -EINVAL;
6281         }
6282
6283         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6284         if (&obj->base == NULL)
6285                 return -ENOENT;
6286
6287         if (obj->base.size < width * height * 4) {
6288                 DRM_ERROR("buffer is to small\n");
6289                 ret = -ENOMEM;
6290                 goto fail;
6291         }
6292
6293         /* we only need to pin inside GTT if cursor is non-phy */
6294         mutex_lock(&dev->struct_mutex);
6295         if (!dev_priv->info->cursor_needs_physical) {
6296                 if (obj->tiling_mode) {
6297                         DRM_ERROR("cursor cannot be tiled\n");
6298                         ret = -EINVAL;
6299                         goto fail_locked;
6300                 }
6301
6302                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6303                 if (ret) {
6304                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6305                         goto fail_locked;
6306                 }
6307
6308                 ret = i915_gem_object_put_fence(obj);
6309                 if (ret) {
6310                         DRM_ERROR("failed to release fence for cursor");
6311                         goto fail_unpin;
6312                 }
6313
6314                 addr = obj->gtt_offset;
6315         } else {
6316                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6317                 ret = i915_gem_attach_phys_object(dev, obj,
6318                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6319                                                   align);
6320                 if (ret) {
6321                         DRM_ERROR("failed to attach phys object\n");
6322                         goto fail_locked;
6323                 }
6324                 addr = obj->phys_obj->handle->busaddr;
6325         }
6326
6327         if (IS_GEN2(dev))
6328                 I915_WRITE(CURSIZE, (height << 12) | width);
6329
6330  finish:
6331         if (intel_crtc->cursor_bo) {
6332                 if (dev_priv->info->cursor_needs_physical) {
6333                         if (intel_crtc->cursor_bo != obj)
6334                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6335                 } else
6336                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6337                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6338         }
6339
6340         mutex_unlock(&dev->struct_mutex);
6341
6342         intel_crtc->cursor_addr = addr;
6343         intel_crtc->cursor_bo = obj;
6344         intel_crtc->cursor_width = width;
6345         intel_crtc->cursor_height = height;
6346
6347         intel_crtc_update_cursor(crtc, true);
6348
6349         return 0;
6350 fail_unpin:
6351         i915_gem_object_unpin(obj);
6352 fail_locked:
6353         mutex_unlock(&dev->struct_mutex);
6354 fail:
6355         drm_gem_object_unreference_unlocked(&obj->base);
6356         return ret;
6357 }
6358
6359 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6360 {
6361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362
6363         intel_crtc->cursor_x = x;
6364         intel_crtc->cursor_y = y;
6365
6366         intel_crtc_update_cursor(crtc, true);
6367
6368         return 0;
6369 }
6370
6371 /** Sets the color ramps on behalf of RandR */
6372 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6373                                  u16 blue, int regno)
6374 {
6375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376
6377         intel_crtc->lut_r[regno] = red >> 8;
6378         intel_crtc->lut_g[regno] = green >> 8;
6379         intel_crtc->lut_b[regno] = blue >> 8;
6380 }
6381
6382 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6383                              u16 *blue, int regno)
6384 {
6385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386
6387         *red = intel_crtc->lut_r[regno] << 8;
6388         *green = intel_crtc->lut_g[regno] << 8;
6389         *blue = intel_crtc->lut_b[regno] << 8;
6390 }
6391
6392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6393                                  u16 *blue, uint32_t start, uint32_t size)
6394 {
6395         int end = (start + size > 256) ? 256 : start + size, i;
6396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6397
6398         for (i = start; i < end; i++) {
6399                 intel_crtc->lut_r[i] = red[i] >> 8;
6400                 intel_crtc->lut_g[i] = green[i] >> 8;
6401                 intel_crtc->lut_b[i] = blue[i] >> 8;
6402         }
6403
6404         intel_crtc_load_lut(crtc);
6405 }
6406
6407 /**
6408  * Get a pipe with a simple mode set on it for doing load-based monitor
6409  * detection.
6410  *
6411  * It will be up to the load-detect code to adjust the pipe as appropriate for
6412  * its requirements.  The pipe will be connected to no other encoders.
6413  *
6414  * Currently this code will only succeed if there is a pipe with no encoders
6415  * configured for it.  In the future, it could choose to temporarily disable
6416  * some outputs to free up a pipe for its use.
6417  *
6418  * \return crtc, or NULL if no pipes are available.
6419  */
6420
6421 /* VESA 640x480x72Hz mode to set on the pipe */
6422 static struct drm_display_mode load_detect_mode = {
6423         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6424                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6425 };
6426
6427 static struct drm_framebuffer *
6428 intel_framebuffer_create(struct drm_device *dev,
6429                          struct drm_mode_fb_cmd2 *mode_cmd,
6430                          struct drm_i915_gem_object *obj)
6431 {
6432         struct intel_framebuffer *intel_fb;
6433         int ret;
6434
6435         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6436         if (!intel_fb) {
6437                 drm_gem_object_unreference_unlocked(&obj->base);
6438                 return ERR_PTR(-ENOMEM);
6439         }
6440
6441         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6442         if (ret) {
6443                 drm_gem_object_unreference_unlocked(&obj->base);
6444                 kfree(intel_fb);
6445                 return ERR_PTR(ret);
6446         }
6447
6448         return &intel_fb->base;
6449 }
6450
6451 static u32
6452 intel_framebuffer_pitch_for_width(int width, int bpp)
6453 {
6454         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6455         return ALIGN(pitch, 64);
6456 }
6457
6458 static u32
6459 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6460 {
6461         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6462         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6463 }
6464
6465 static struct drm_framebuffer *
6466 intel_framebuffer_create_for_mode(struct drm_device *dev,
6467                                   struct drm_display_mode *mode,
6468                                   int depth, int bpp)
6469 {
6470         struct drm_i915_gem_object *obj;
6471         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6472
6473         obj = i915_gem_alloc_object(dev,
6474                                     intel_framebuffer_size_for_mode(mode, bpp));
6475         if (obj == NULL)
6476                 return ERR_PTR(-ENOMEM);
6477
6478         mode_cmd.width = mode->hdisplay;
6479         mode_cmd.height = mode->vdisplay;
6480         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6481                                                                 bpp);
6482         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6483
6484         return intel_framebuffer_create(dev, &mode_cmd, obj);
6485 }
6486
6487 static struct drm_framebuffer *
6488 mode_fits_in_fbdev(struct drm_device *dev,
6489                    struct drm_display_mode *mode)
6490 {
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         struct drm_i915_gem_object *obj;
6493         struct drm_framebuffer *fb;
6494
6495         if (dev_priv->fbdev == NULL)
6496                 return NULL;
6497
6498         obj = dev_priv->fbdev->ifb.obj;
6499         if (obj == NULL)
6500                 return NULL;
6501
6502         fb = &dev_priv->fbdev->ifb.base;
6503         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6504                                                                fb->bits_per_pixel))
6505                 return NULL;
6506
6507         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6508                 return NULL;
6509
6510         return fb;
6511 }
6512
6513 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6514                                 struct drm_display_mode *mode,
6515                                 struct intel_load_detect_pipe *old)
6516 {
6517         struct intel_crtc *intel_crtc;
6518         struct intel_encoder *intel_encoder =
6519                 intel_attached_encoder(connector);
6520         struct drm_crtc *possible_crtc;
6521         struct drm_encoder *encoder = &intel_encoder->base;
6522         struct drm_crtc *crtc = NULL;
6523         struct drm_device *dev = encoder->dev;
6524         struct drm_framebuffer *fb;
6525         int i = -1;
6526
6527         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6528                       connector->base.id, drm_get_connector_name(connector),
6529                       encoder->base.id, drm_get_encoder_name(encoder));
6530
6531         /*
6532          * Algorithm gets a little messy:
6533          *
6534          *   - if the connector already has an assigned crtc, use it (but make
6535          *     sure it's on first)
6536          *
6537          *   - try to find the first unused crtc that can drive this connector,
6538          *     and use that if we find one
6539          */
6540
6541         /* See if we already have a CRTC for this connector */
6542         if (encoder->crtc) {
6543                 crtc = encoder->crtc;
6544
6545                 old->dpms_mode = connector->dpms;
6546                 old->load_detect_temp = false;
6547
6548                 /* Make sure the crtc and connector are running */
6549                 if (connector->dpms != DRM_MODE_DPMS_ON)
6550                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6551
6552                 return true;
6553         }
6554
6555         /* Find an unused one (if possible) */
6556         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6557                 i++;
6558                 if (!(encoder->possible_crtcs & (1 << i)))
6559                         continue;
6560                 if (!possible_crtc->enabled) {
6561                         crtc = possible_crtc;
6562                         break;
6563                 }
6564         }
6565
6566         /*
6567          * If we didn't find an unused CRTC, don't use any.
6568          */
6569         if (!crtc) {
6570                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6571                 return false;
6572         }
6573
6574         intel_encoder->new_crtc = to_intel_crtc(crtc);
6575         to_intel_connector(connector)->new_encoder = intel_encoder;
6576
6577         intel_crtc = to_intel_crtc(crtc);
6578         old->dpms_mode = connector->dpms;
6579         old->load_detect_temp = true;
6580         old->release_fb = NULL;
6581
6582         if (!mode)
6583                 mode = &load_detect_mode;
6584
6585         /* We need a framebuffer large enough to accommodate all accesses
6586          * that the plane may generate whilst we perform load detection.
6587          * We can not rely on the fbcon either being present (we get called
6588          * during its initialisation to detect all boot displays, or it may
6589          * not even exist) or that it is large enough to satisfy the
6590          * requested mode.
6591          */
6592         fb = mode_fits_in_fbdev(dev, mode);
6593         if (fb == NULL) {
6594                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6595                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6596                 old->release_fb = fb;
6597         } else
6598                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6599         if (IS_ERR(fb)) {
6600                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6601                 return false;
6602         }
6603
6604         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6605                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6606                 if (old->release_fb)
6607                         old->release_fb->funcs->destroy(old->release_fb);
6608                 return false;
6609         }
6610
6611         /* let the connector get through one full cycle before testing */
6612         intel_wait_for_vblank(dev, intel_crtc->pipe);
6613         return true;
6614 }
6615
6616 void intel_release_load_detect_pipe(struct drm_connector *connector,
6617                                     struct intel_load_detect_pipe *old)
6618 {
6619         struct intel_encoder *intel_encoder =
6620                 intel_attached_encoder(connector);
6621         struct drm_encoder *encoder = &intel_encoder->base;
6622
6623         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6624                       connector->base.id, drm_get_connector_name(connector),
6625                       encoder->base.id, drm_get_encoder_name(encoder));
6626
6627         if (old->load_detect_temp) {
6628                 struct drm_crtc *crtc = encoder->crtc;
6629
6630                 to_intel_connector(connector)->new_encoder = NULL;
6631                 intel_encoder->new_crtc = NULL;
6632                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6633
6634                 if (old->release_fb)
6635                         old->release_fb->funcs->destroy(old->release_fb);
6636
6637                 return;
6638         }
6639
6640         /* Switch crtc and encoder back off if necessary */
6641         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6642                 connector->funcs->dpms(connector, old->dpms_mode);
6643 }
6644
6645 /* Returns the clock of the currently programmed mode of the given pipe. */
6646 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6647 {
6648         struct drm_i915_private *dev_priv = dev->dev_private;
6649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650         int pipe = intel_crtc->pipe;
6651         u32 dpll = I915_READ(DPLL(pipe));
6652         u32 fp;
6653         intel_clock_t clock;
6654
6655         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6656                 fp = I915_READ(FP0(pipe));
6657         else
6658                 fp = I915_READ(FP1(pipe));
6659
6660         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6661         if (IS_PINEVIEW(dev)) {
6662                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6663                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6664         } else {
6665                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6666                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6667         }
6668
6669         if (!IS_GEN2(dev)) {
6670                 if (IS_PINEVIEW(dev))
6671                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6672                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6673                 else
6674                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6675                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6676
6677                 switch (dpll & DPLL_MODE_MASK) {
6678                 case DPLLB_MODE_DAC_SERIAL:
6679                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6680                                 5 : 10;
6681                         break;
6682                 case DPLLB_MODE_LVDS:
6683                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6684                                 7 : 14;
6685                         break;
6686                 default:
6687                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6688                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6689                         return 0;
6690                 }
6691
6692                 /* XXX: Handle the 100Mhz refclk */
6693                 intel_clock(dev, 96000, &clock);
6694         } else {
6695                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6696
6697                 if (is_lvds) {
6698                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6699                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6700                         clock.p2 = 14;
6701
6702                         if ((dpll & PLL_REF_INPUT_MASK) ==
6703                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6704                                 /* XXX: might not be 66MHz */
6705                                 intel_clock(dev, 66000, &clock);
6706                         } else
6707                                 intel_clock(dev, 48000, &clock);
6708                 } else {
6709                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6710                                 clock.p1 = 2;
6711                         else {
6712                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6713                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6714                         }
6715                         if (dpll & PLL_P2_DIVIDE_BY_4)
6716                                 clock.p2 = 4;
6717                         else
6718                                 clock.p2 = 2;
6719
6720                         intel_clock(dev, 48000, &clock);
6721                 }
6722         }
6723
6724         /* XXX: It would be nice to validate the clocks, but we can't reuse
6725          * i830PllIsValid() because it relies on the xf86_config connector
6726          * configuration being accurate, which it isn't necessarily.
6727          */
6728
6729         return clock.dot;
6730 }
6731
6732 /** Returns the currently programmed mode of the given pipe. */
6733 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6734                                              struct drm_crtc *crtc)
6735 {
6736         struct drm_i915_private *dev_priv = dev->dev_private;
6737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6738         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6739         struct drm_display_mode *mode;
6740         int htot = I915_READ(HTOTAL(cpu_transcoder));
6741         int hsync = I915_READ(HSYNC(cpu_transcoder));
6742         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6743         int vsync = I915_READ(VSYNC(cpu_transcoder));
6744
6745         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6746         if (!mode)
6747                 return NULL;
6748
6749         mode->clock = intel_crtc_clock_get(dev, crtc);
6750         mode->hdisplay = (htot & 0xffff) + 1;
6751         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6752         mode->hsync_start = (hsync & 0xffff) + 1;
6753         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6754         mode->vdisplay = (vtot & 0xffff) + 1;
6755         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6756         mode->vsync_start = (vsync & 0xffff) + 1;
6757         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6758
6759         drm_mode_set_name(mode);
6760
6761         return mode;
6762 }
6763
6764 static void intel_increase_pllclock(struct drm_crtc *crtc)
6765 {
6766         struct drm_device *dev = crtc->dev;
6767         drm_i915_private_t *dev_priv = dev->dev_private;
6768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6769         int pipe = intel_crtc->pipe;
6770         int dpll_reg = DPLL(pipe);
6771         int dpll;
6772
6773         if (HAS_PCH_SPLIT(dev))
6774                 return;
6775
6776         if (!dev_priv->lvds_downclock_avail)
6777                 return;
6778
6779         dpll = I915_READ(dpll_reg);
6780         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6781                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6782
6783                 assert_panel_unlocked(dev_priv, pipe);
6784
6785                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6786                 I915_WRITE(dpll_reg, dpll);
6787                 intel_wait_for_vblank(dev, pipe);
6788
6789                 dpll = I915_READ(dpll_reg);
6790                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6791                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6792         }
6793 }
6794
6795 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6796 {
6797         struct drm_device *dev = crtc->dev;
6798         drm_i915_private_t *dev_priv = dev->dev_private;
6799         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6800
6801         if (HAS_PCH_SPLIT(dev))
6802                 return;
6803
6804         if (!dev_priv->lvds_downclock_avail)
6805                 return;
6806
6807         /*
6808          * Since this is called by a timer, we should never get here in
6809          * the manual case.
6810          */
6811         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6812                 int pipe = intel_crtc->pipe;
6813                 int dpll_reg = DPLL(pipe);
6814                 int dpll;
6815
6816                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6817
6818                 assert_panel_unlocked(dev_priv, pipe);
6819
6820                 dpll = I915_READ(dpll_reg);
6821                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6822                 I915_WRITE(dpll_reg, dpll);
6823                 intel_wait_for_vblank(dev, pipe);
6824                 dpll = I915_READ(dpll_reg);
6825                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6826                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6827         }
6828
6829 }
6830
6831 void intel_mark_busy(struct drm_device *dev)
6832 {
6833         i915_update_gfx_val(dev->dev_private);
6834 }
6835
6836 void intel_mark_idle(struct drm_device *dev)
6837 {
6838 }
6839
6840 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6841 {
6842         struct drm_device *dev = obj->base.dev;
6843         struct drm_crtc *crtc;
6844
6845         if (!i915_powersave)
6846                 return;
6847
6848         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6849                 if (!crtc->fb)
6850                         continue;
6851
6852                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6853                         intel_increase_pllclock(crtc);
6854         }
6855 }
6856
6857 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6858 {
6859         struct drm_device *dev = obj->base.dev;
6860         struct drm_crtc *crtc;
6861
6862         if (!i915_powersave)
6863                 return;
6864
6865         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6866                 if (!crtc->fb)
6867                         continue;
6868
6869                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6870                         intel_decrease_pllclock(crtc);
6871         }
6872 }
6873
6874 static void intel_crtc_destroy(struct drm_crtc *crtc)
6875 {
6876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6877         struct drm_device *dev = crtc->dev;
6878         struct intel_unpin_work *work;
6879         unsigned long flags;
6880
6881         spin_lock_irqsave(&dev->event_lock, flags);
6882         work = intel_crtc->unpin_work;
6883         intel_crtc->unpin_work = NULL;
6884         spin_unlock_irqrestore(&dev->event_lock, flags);
6885
6886         if (work) {
6887                 cancel_work_sync(&work->work);
6888                 kfree(work);
6889         }
6890
6891         drm_crtc_cleanup(crtc);
6892
6893         kfree(intel_crtc);
6894 }
6895
6896 static void intel_unpin_work_fn(struct work_struct *__work)
6897 {
6898         struct intel_unpin_work *work =
6899                 container_of(__work, struct intel_unpin_work, work);
6900         struct drm_device *dev = work->crtc->dev;
6901
6902         mutex_lock(&dev->struct_mutex);
6903         intel_unpin_fb_obj(work->old_fb_obj);
6904         drm_gem_object_unreference(&work->pending_flip_obj->base);
6905         drm_gem_object_unreference(&work->old_fb_obj->base);
6906
6907         intel_update_fbc(dev);
6908         mutex_unlock(&dev->struct_mutex);
6909
6910         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6911         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6912
6913         kfree(work);
6914 }
6915
6916 static void do_intel_finish_page_flip(struct drm_device *dev,
6917                                       struct drm_crtc *crtc)
6918 {
6919         drm_i915_private_t *dev_priv = dev->dev_private;
6920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6921         struct intel_unpin_work *work;
6922         struct drm_i915_gem_object *obj;
6923         struct drm_pending_vblank_event *e;
6924         struct timeval tvbl;
6925         unsigned long flags;
6926
6927         /* Ignore early vblank irqs */
6928         if (intel_crtc == NULL)
6929                 return;
6930
6931         spin_lock_irqsave(&dev->event_lock, flags);
6932         work = intel_crtc->unpin_work;
6933         if (work == NULL || !work->pending) {
6934                 spin_unlock_irqrestore(&dev->event_lock, flags);
6935                 return;
6936         }
6937
6938         intel_crtc->unpin_work = NULL;
6939
6940         if (work->event) {
6941                 e = work->event;
6942                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6943
6944                 e->event.tv_sec = tvbl.tv_sec;
6945                 e->event.tv_usec = tvbl.tv_usec;
6946
6947                 list_add_tail(&e->base.link,
6948                               &e->base.file_priv->event_list);
6949                 wake_up_interruptible(&e->base.file_priv->event_wait);
6950         }
6951
6952         drm_vblank_put(dev, intel_crtc->pipe);
6953
6954         spin_unlock_irqrestore(&dev->event_lock, flags);
6955
6956         obj = work->old_fb_obj;
6957
6958         atomic_clear_mask(1 << intel_crtc->plane,
6959                           &obj->pending_flip.counter);
6960         wake_up(&dev_priv->pending_flip_queue);
6961
6962         queue_work(dev_priv->wq, &work->work);
6963
6964         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6965 }
6966
6967 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6968 {
6969         drm_i915_private_t *dev_priv = dev->dev_private;
6970         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6971
6972         do_intel_finish_page_flip(dev, crtc);
6973 }
6974
6975 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6976 {
6977         drm_i915_private_t *dev_priv = dev->dev_private;
6978         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6979
6980         do_intel_finish_page_flip(dev, crtc);
6981 }
6982
6983 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6984 {
6985         drm_i915_private_t *dev_priv = dev->dev_private;
6986         struct intel_crtc *intel_crtc =
6987                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6988         unsigned long flags;
6989
6990         spin_lock_irqsave(&dev->event_lock, flags);
6991         if (intel_crtc->unpin_work) {
6992                 if ((++intel_crtc->unpin_work->pending) > 1)
6993                         DRM_ERROR("Prepared flip multiple times\n");
6994         } else {
6995                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6996         }
6997         spin_unlock_irqrestore(&dev->event_lock, flags);
6998 }
6999
7000 static int intel_gen2_queue_flip(struct drm_device *dev,
7001                                  struct drm_crtc *crtc,
7002                                  struct drm_framebuffer *fb,
7003                                  struct drm_i915_gem_object *obj)
7004 {
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007         u32 flip_mask;
7008         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7009         int ret;
7010
7011         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7012         if (ret)
7013                 goto err;
7014
7015         ret = intel_ring_begin(ring, 6);
7016         if (ret)
7017                 goto err_unpin;
7018
7019         /* Can't queue multiple flips, so wait for the previous
7020          * one to finish before executing the next.
7021          */
7022         if (intel_crtc->plane)
7023                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7024         else
7025                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7026         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7027         intel_ring_emit(ring, MI_NOOP);
7028         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7029                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7030         intel_ring_emit(ring, fb->pitches[0]);
7031         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7032         intel_ring_emit(ring, 0); /* aux display base address, unused */
7033         intel_ring_advance(ring);
7034         return 0;
7035
7036 err_unpin:
7037         intel_unpin_fb_obj(obj);
7038 err:
7039         return ret;
7040 }
7041
7042 static int intel_gen3_queue_flip(struct drm_device *dev,
7043                                  struct drm_crtc *crtc,
7044                                  struct drm_framebuffer *fb,
7045                                  struct drm_i915_gem_object *obj)
7046 {
7047         struct drm_i915_private *dev_priv = dev->dev_private;
7048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7049         u32 flip_mask;
7050         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7051         int ret;
7052
7053         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7054         if (ret)
7055                 goto err;
7056
7057         ret = intel_ring_begin(ring, 6);
7058         if (ret)
7059                 goto err_unpin;
7060
7061         if (intel_crtc->plane)
7062                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7063         else
7064                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7065         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7066         intel_ring_emit(ring, MI_NOOP);
7067         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7068                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7069         intel_ring_emit(ring, fb->pitches[0]);
7070         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7071         intel_ring_emit(ring, MI_NOOP);
7072
7073         intel_ring_advance(ring);
7074         return 0;
7075
7076 err_unpin:
7077         intel_unpin_fb_obj(obj);
7078 err:
7079         return ret;
7080 }
7081
7082 static int intel_gen4_queue_flip(struct drm_device *dev,
7083                                  struct drm_crtc *crtc,
7084                                  struct drm_framebuffer *fb,
7085                                  struct drm_i915_gem_object *obj)
7086 {
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089         uint32_t pf, pipesrc;
7090         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7091         int ret;
7092
7093         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7094         if (ret)
7095                 goto err;
7096
7097         ret = intel_ring_begin(ring, 4);
7098         if (ret)
7099                 goto err_unpin;
7100
7101         /* i965+ uses the linear or tiled offsets from the
7102          * Display Registers (which do not change across a page-flip)
7103          * so we need only reprogram the base address.
7104          */
7105         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7106                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7107         intel_ring_emit(ring, fb->pitches[0]);
7108         intel_ring_emit(ring,
7109                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7110                         obj->tiling_mode);
7111
7112         /* XXX Enabling the panel-fitter across page-flip is so far
7113          * untested on non-native modes, so ignore it for now.
7114          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7115          */
7116         pf = 0;
7117         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7118         intel_ring_emit(ring, pf | pipesrc);
7119         intel_ring_advance(ring);
7120         return 0;
7121
7122 err_unpin:
7123         intel_unpin_fb_obj(obj);
7124 err:
7125         return ret;
7126 }
7127
7128 static int intel_gen6_queue_flip(struct drm_device *dev,
7129                                  struct drm_crtc *crtc,
7130                                  struct drm_framebuffer *fb,
7131                                  struct drm_i915_gem_object *obj)
7132 {
7133         struct drm_i915_private *dev_priv = dev->dev_private;
7134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7136         uint32_t pf, pipesrc;
7137         int ret;
7138
7139         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7140         if (ret)
7141                 goto err;
7142
7143         ret = intel_ring_begin(ring, 4);
7144         if (ret)
7145                 goto err_unpin;
7146
7147         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7148                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7149         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7150         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7151
7152         /* Contrary to the suggestions in the documentation,
7153          * "Enable Panel Fitter" does not seem to be required when page
7154          * flipping with a non-native mode, and worse causes a normal
7155          * modeset to fail.
7156          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7157          */
7158         pf = 0;
7159         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7160         intel_ring_emit(ring, pf | pipesrc);
7161         intel_ring_advance(ring);
7162         return 0;
7163
7164 err_unpin:
7165         intel_unpin_fb_obj(obj);
7166 err:
7167         return ret;
7168 }
7169
7170 /*
7171  * On gen7 we currently use the blit ring because (in early silicon at least)
7172  * the render ring doesn't give us interrpts for page flip completion, which
7173  * means clients will hang after the first flip is queued.  Fortunately the
7174  * blit ring generates interrupts properly, so use it instead.
7175  */
7176 static int intel_gen7_queue_flip(struct drm_device *dev,
7177                                  struct drm_crtc *crtc,
7178                                  struct drm_framebuffer *fb,
7179                                  struct drm_i915_gem_object *obj)
7180 {
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7184         uint32_t plane_bit = 0;
7185         int ret;
7186
7187         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7188         if (ret)
7189                 goto err;
7190
7191         switch(intel_crtc->plane) {
7192         case PLANE_A:
7193                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7194                 break;
7195         case PLANE_B:
7196                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7197                 break;
7198         case PLANE_C:
7199                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7200                 break;
7201         default:
7202                 WARN_ONCE(1, "unknown plane in flip command\n");
7203                 ret = -ENODEV;
7204                 goto err_unpin;
7205         }
7206
7207         ret = intel_ring_begin(ring, 4);
7208         if (ret)
7209                 goto err_unpin;
7210
7211         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7212         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7213         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7214         intel_ring_emit(ring, (MI_NOOP));
7215         intel_ring_advance(ring);
7216         return 0;
7217
7218 err_unpin:
7219         intel_unpin_fb_obj(obj);
7220 err:
7221         return ret;
7222 }
7223
7224 static int intel_default_queue_flip(struct drm_device *dev,
7225                                     struct drm_crtc *crtc,
7226                                     struct drm_framebuffer *fb,
7227                                     struct drm_i915_gem_object *obj)
7228 {
7229         return -ENODEV;
7230 }
7231
7232 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7233                                 struct drm_framebuffer *fb,
7234                                 struct drm_pending_vblank_event *event)
7235 {
7236         struct drm_device *dev = crtc->dev;
7237         struct drm_i915_private *dev_priv = dev->dev_private;
7238         struct intel_framebuffer *intel_fb;
7239         struct drm_i915_gem_object *obj;
7240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7241         struct intel_unpin_work *work;
7242         unsigned long flags;
7243         int ret;
7244
7245         /* Can't change pixel format via MI display flips. */
7246         if (fb->pixel_format != crtc->fb->pixel_format)
7247                 return -EINVAL;
7248
7249         /*
7250          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7251          * Note that pitch changes could also affect these register.
7252          */
7253         if (INTEL_INFO(dev)->gen > 3 &&
7254             (fb->offsets[0] != crtc->fb->offsets[0] ||
7255              fb->pitches[0] != crtc->fb->pitches[0]))
7256                 return -EINVAL;
7257
7258         work = kzalloc(sizeof *work, GFP_KERNEL);
7259         if (work == NULL)
7260                 return -ENOMEM;
7261
7262         work->event = event;
7263         work->crtc = crtc;
7264         intel_fb = to_intel_framebuffer(crtc->fb);
7265         work->old_fb_obj = intel_fb->obj;
7266         INIT_WORK(&work->work, intel_unpin_work_fn);
7267
7268         ret = drm_vblank_get(dev, intel_crtc->pipe);
7269         if (ret)
7270                 goto free_work;
7271
7272         /* We borrow the event spin lock for protecting unpin_work */
7273         spin_lock_irqsave(&dev->event_lock, flags);
7274         if (intel_crtc->unpin_work) {
7275                 spin_unlock_irqrestore(&dev->event_lock, flags);
7276                 kfree(work);
7277                 drm_vblank_put(dev, intel_crtc->pipe);
7278
7279                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7280                 return -EBUSY;
7281         }
7282         intel_crtc->unpin_work = work;
7283         spin_unlock_irqrestore(&dev->event_lock, flags);
7284
7285         intel_fb = to_intel_framebuffer(fb);
7286         obj = intel_fb->obj;
7287
7288         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7289                 flush_workqueue(dev_priv->wq);
7290
7291         ret = i915_mutex_lock_interruptible(dev);
7292         if (ret)
7293                 goto cleanup;
7294
7295         /* Reference the objects for the scheduled work. */
7296         drm_gem_object_reference(&work->old_fb_obj->base);
7297         drm_gem_object_reference(&obj->base);
7298
7299         crtc->fb = fb;
7300
7301         work->pending_flip_obj = obj;
7302
7303         work->enable_stall_check = true;
7304
7305         /* Block clients from rendering to the new back buffer until
7306          * the flip occurs and the object is no longer visible.
7307          */
7308         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7309         atomic_inc(&intel_crtc->unpin_work_count);
7310
7311         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7312         if (ret)
7313                 goto cleanup_pending;
7314
7315         intel_disable_fbc(dev);
7316         intel_mark_fb_busy(obj);
7317         mutex_unlock(&dev->struct_mutex);
7318
7319         trace_i915_flip_request(intel_crtc->plane, obj);
7320
7321         return 0;
7322
7323 cleanup_pending:
7324         atomic_dec(&intel_crtc->unpin_work_count);
7325         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7326         drm_gem_object_unreference(&work->old_fb_obj->base);
7327         drm_gem_object_unreference(&obj->base);
7328         mutex_unlock(&dev->struct_mutex);
7329
7330 cleanup:
7331         spin_lock_irqsave(&dev->event_lock, flags);
7332         intel_crtc->unpin_work = NULL;
7333         spin_unlock_irqrestore(&dev->event_lock, flags);
7334
7335         drm_vblank_put(dev, intel_crtc->pipe);
7336 free_work:
7337         kfree(work);
7338
7339         return ret;
7340 }
7341
7342 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7343         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7344         .load_lut = intel_crtc_load_lut,
7345         .disable = intel_crtc_noop,
7346 };
7347
7348 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7349 {
7350         struct intel_encoder *other_encoder;
7351         struct drm_crtc *crtc = &encoder->new_crtc->base;
7352
7353         if (WARN_ON(!crtc))
7354                 return false;
7355
7356         list_for_each_entry(other_encoder,
7357                             &crtc->dev->mode_config.encoder_list,
7358                             base.head) {
7359
7360                 if (&other_encoder->new_crtc->base != crtc ||
7361                     encoder == other_encoder)
7362                         continue;
7363                 else
7364                         return true;
7365         }
7366
7367         return false;
7368 }
7369
7370 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7371                                   struct drm_crtc *crtc)
7372 {
7373         struct drm_device *dev;
7374         struct drm_crtc *tmp;
7375         int crtc_mask = 1;
7376
7377         WARN(!crtc, "checking null crtc?\n");
7378
7379         dev = crtc->dev;
7380
7381         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7382                 if (tmp == crtc)
7383                         break;
7384                 crtc_mask <<= 1;
7385         }
7386
7387         if (encoder->possible_crtcs & crtc_mask)
7388                 return true;
7389         return false;
7390 }
7391
7392 /**
7393  * intel_modeset_update_staged_output_state
7394  *
7395  * Updates the staged output configuration state, e.g. after we've read out the
7396  * current hw state.
7397  */
7398 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7399 {
7400         struct intel_encoder *encoder;
7401         struct intel_connector *connector;
7402
7403         list_for_each_entry(connector, &dev->mode_config.connector_list,
7404                             base.head) {
7405                 connector->new_encoder =
7406                         to_intel_encoder(connector->base.encoder);
7407         }
7408
7409         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7410                             base.head) {
7411                 encoder->new_crtc =
7412                         to_intel_crtc(encoder->base.crtc);
7413         }
7414 }
7415
7416 /**
7417  * intel_modeset_commit_output_state
7418  *
7419  * This function copies the stage display pipe configuration to the real one.
7420  */
7421 static void intel_modeset_commit_output_state(struct drm_device *dev)
7422 {
7423         struct intel_encoder *encoder;
7424         struct intel_connector *connector;
7425
7426         list_for_each_entry(connector, &dev->mode_config.connector_list,
7427                             base.head) {
7428                 connector->base.encoder = &connector->new_encoder->base;
7429         }
7430
7431         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7432                             base.head) {
7433                 encoder->base.crtc = &encoder->new_crtc->base;
7434         }
7435 }
7436
7437 static struct drm_display_mode *
7438 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7439                             struct drm_display_mode *mode)
7440 {
7441         struct drm_device *dev = crtc->dev;
7442         struct drm_display_mode *adjusted_mode;
7443         struct drm_encoder_helper_funcs *encoder_funcs;
7444         struct intel_encoder *encoder;
7445
7446         adjusted_mode = drm_mode_duplicate(dev, mode);
7447         if (!adjusted_mode)
7448                 return ERR_PTR(-ENOMEM);
7449
7450         /* Pass our mode to the connectors and the CRTC to give them a chance to
7451          * adjust it according to limitations or connector properties, and also
7452          * a chance to reject the mode entirely.
7453          */
7454         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7455                             base.head) {
7456
7457                 if (&encoder->new_crtc->base != crtc)
7458                         continue;
7459                 encoder_funcs = encoder->base.helper_private;
7460                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7461                                                 adjusted_mode))) {
7462                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7463                         goto fail;
7464                 }
7465         }
7466
7467         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7468                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7469                 goto fail;
7470         }
7471         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7472
7473         return adjusted_mode;
7474 fail:
7475         drm_mode_destroy(dev, adjusted_mode);
7476         return ERR_PTR(-EINVAL);
7477 }
7478
7479 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7480  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7481 static void
7482 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7483                              unsigned *prepare_pipes, unsigned *disable_pipes)
7484 {
7485         struct intel_crtc *intel_crtc;
7486         struct drm_device *dev = crtc->dev;
7487         struct intel_encoder *encoder;
7488         struct intel_connector *connector;
7489         struct drm_crtc *tmp_crtc;
7490
7491         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7492
7493         /* Check which crtcs have changed outputs connected to them, these need
7494          * to be part of the prepare_pipes mask. We don't (yet) support global
7495          * modeset across multiple crtcs, so modeset_pipes will only have one
7496          * bit set at most. */
7497         list_for_each_entry(connector, &dev->mode_config.connector_list,
7498                             base.head) {
7499                 if (connector->base.encoder == &connector->new_encoder->base)
7500                         continue;
7501
7502                 if (connector->base.encoder) {
7503                         tmp_crtc = connector->base.encoder->crtc;
7504
7505                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7506                 }
7507
7508                 if (connector->new_encoder)
7509                         *prepare_pipes |=
7510                                 1 << connector->new_encoder->new_crtc->pipe;
7511         }
7512
7513         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7514                             base.head) {
7515                 if (encoder->base.crtc == &encoder->new_crtc->base)
7516                         continue;
7517
7518                 if (encoder->base.crtc) {
7519                         tmp_crtc = encoder->base.crtc;
7520
7521                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7522                 }
7523
7524                 if (encoder->new_crtc)
7525                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7526         }
7527
7528         /* Check for any pipes that will be fully disabled ... */
7529         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7530                             base.head) {
7531                 bool used = false;
7532
7533                 /* Don't try to disable disabled crtcs. */
7534                 if (!intel_crtc->base.enabled)
7535                         continue;
7536
7537                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7538                                     base.head) {
7539                         if (encoder->new_crtc == intel_crtc)
7540                                 used = true;
7541                 }
7542
7543                 if (!used)
7544                         *disable_pipes |= 1 << intel_crtc->pipe;
7545         }
7546
7547
7548         /* set_mode is also used to update properties on life display pipes. */
7549         intel_crtc = to_intel_crtc(crtc);
7550         if (crtc->enabled)
7551                 *prepare_pipes |= 1 << intel_crtc->pipe;
7552
7553         /* We only support modeset on one single crtc, hence we need to do that
7554          * only for the passed in crtc iff we change anything else than just
7555          * disable crtcs.
7556          *
7557          * This is actually not true, to be fully compatible with the old crtc
7558          * helper we automatically disable _any_ output (i.e. doesn't need to be
7559          * connected to the crtc we're modesetting on) if it's disconnected.
7560          * Which is a rather nutty api (since changed the output configuration
7561          * without userspace's explicit request can lead to confusion), but
7562          * alas. Hence we currently need to modeset on all pipes we prepare. */
7563         if (*prepare_pipes)
7564                 *modeset_pipes = *prepare_pipes;
7565
7566         /* ... and mask these out. */
7567         *modeset_pipes &= ~(*disable_pipes);
7568         *prepare_pipes &= ~(*disable_pipes);
7569 }
7570
7571 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7572 {
7573         struct drm_encoder *encoder;
7574         struct drm_device *dev = crtc->dev;
7575
7576         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7577                 if (encoder->crtc == crtc)
7578                         return true;
7579
7580         return false;
7581 }
7582
7583 static void
7584 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7585 {
7586         struct intel_encoder *intel_encoder;
7587         struct intel_crtc *intel_crtc;
7588         struct drm_connector *connector;
7589
7590         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7591                             base.head) {
7592                 if (!intel_encoder->base.crtc)
7593                         continue;
7594
7595                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7596
7597                 if (prepare_pipes & (1 << intel_crtc->pipe))
7598                         intel_encoder->connectors_active = false;
7599         }
7600
7601         intel_modeset_commit_output_state(dev);
7602
7603         /* Update computed state. */
7604         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7605                             base.head) {
7606                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7607         }
7608
7609         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7610                 if (!connector->encoder || !connector->encoder->crtc)
7611                         continue;
7612
7613                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7614
7615                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7616                         struct drm_property *dpms_property =
7617                                 dev->mode_config.dpms_property;
7618
7619                         connector->dpms = DRM_MODE_DPMS_ON;
7620                         drm_connector_property_set_value(connector,
7621                                                          dpms_property,
7622                                                          DRM_MODE_DPMS_ON);
7623
7624                         intel_encoder = to_intel_encoder(connector->encoder);
7625                         intel_encoder->connectors_active = true;
7626                 }
7627         }
7628
7629 }
7630
7631 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7632         list_for_each_entry((intel_crtc), \
7633                             &(dev)->mode_config.crtc_list, \
7634                             base.head) \
7635                 if (mask & (1 <<(intel_crtc)->pipe)) \
7636
7637 void
7638 intel_modeset_check_state(struct drm_device *dev)
7639 {
7640         struct intel_crtc *crtc;
7641         struct intel_encoder *encoder;
7642         struct intel_connector *connector;
7643
7644         list_for_each_entry(connector, &dev->mode_config.connector_list,
7645                             base.head) {
7646                 /* This also checks the encoder/connector hw state with the
7647                  * ->get_hw_state callbacks. */
7648                 intel_connector_check_state(connector);
7649
7650                 WARN(&connector->new_encoder->base != connector->base.encoder,
7651                      "connector's staged encoder doesn't match current encoder\n");
7652         }
7653
7654         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7655                             base.head) {
7656                 bool enabled = false;
7657                 bool active = false;
7658                 enum pipe pipe, tracked_pipe;
7659
7660                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7661                               encoder->base.base.id,
7662                               drm_get_encoder_name(&encoder->base));
7663
7664                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7665                      "encoder's stage crtc doesn't match current crtc\n");
7666                 WARN(encoder->connectors_active && !encoder->base.crtc,
7667                      "encoder's active_connectors set, but no crtc\n");
7668
7669                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7670                                     base.head) {
7671                         if (connector->base.encoder != &encoder->base)
7672                                 continue;
7673                         enabled = true;
7674                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7675                                 active = true;
7676                 }
7677                 WARN(!!encoder->base.crtc != enabled,
7678                      "encoder's enabled state mismatch "
7679                      "(expected %i, found %i)\n",
7680                      !!encoder->base.crtc, enabled);
7681                 WARN(active && !encoder->base.crtc,
7682                      "active encoder with no crtc\n");
7683
7684                 WARN(encoder->connectors_active != active,
7685                      "encoder's computed active state doesn't match tracked active state "
7686                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7687
7688                 active = encoder->get_hw_state(encoder, &pipe);
7689                 WARN(active != encoder->connectors_active,
7690                      "encoder's hw state doesn't match sw tracking "
7691                      "(expected %i, found %i)\n",
7692                      encoder->connectors_active, active);
7693
7694                 if (!encoder->base.crtc)
7695                         continue;
7696
7697                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7698                 WARN(active && pipe != tracked_pipe,
7699                      "active encoder's pipe doesn't match"
7700                      "(expected %i, found %i)\n",
7701                      tracked_pipe, pipe);
7702
7703         }
7704
7705         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7706                             base.head) {
7707                 bool enabled = false;
7708                 bool active = false;
7709
7710                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7711                               crtc->base.base.id);
7712
7713                 WARN(crtc->active && !crtc->base.enabled,
7714                      "active crtc, but not enabled in sw tracking\n");
7715
7716                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7717                                     base.head) {
7718                         if (encoder->base.crtc != &crtc->base)
7719                                 continue;
7720                         enabled = true;
7721                         if (encoder->connectors_active)
7722                                 active = true;
7723                 }
7724                 WARN(active != crtc->active,
7725                      "crtc's computed active state doesn't match tracked active state "
7726                      "(expected %i, found %i)\n", active, crtc->active);
7727                 WARN(enabled != crtc->base.enabled,
7728                      "crtc's computed enabled state doesn't match tracked enabled state "
7729                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7730
7731                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7732         }
7733 }
7734
7735 bool intel_set_mode(struct drm_crtc *crtc,
7736                     struct drm_display_mode *mode,
7737                     int x, int y, struct drm_framebuffer *fb)
7738 {
7739         struct drm_device *dev = crtc->dev;
7740         drm_i915_private_t *dev_priv = dev->dev_private;
7741         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7742         struct intel_crtc *intel_crtc;
7743         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7744         bool ret = true;
7745
7746         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7747                                      &prepare_pipes, &disable_pipes);
7748
7749         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7750                       modeset_pipes, prepare_pipes, disable_pipes);
7751
7752         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7753                 intel_crtc_disable(&intel_crtc->base);
7754
7755         saved_hwmode = crtc->hwmode;
7756         saved_mode = crtc->mode;
7757
7758         /* Hack: Because we don't (yet) support global modeset on multiple
7759          * crtcs, we don't keep track of the new mode for more than one crtc.
7760          * Hence simply check whether any bit is set in modeset_pipes in all the
7761          * pieces of code that are not yet converted to deal with mutliple crtcs
7762          * changing their mode at the same time. */
7763         adjusted_mode = NULL;
7764         if (modeset_pipes) {
7765                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7766                 if (IS_ERR(adjusted_mode)) {
7767                         return false;
7768                 }
7769         }
7770
7771         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7772                 if (intel_crtc->base.enabled)
7773                         dev_priv->display.crtc_disable(&intel_crtc->base);
7774         }
7775
7776         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7777          * to set it here already despite that we pass it down the callchain.
7778          */
7779         if (modeset_pipes)
7780                 crtc->mode = *mode;
7781
7782         /* Only after disabling all output pipelines that will be changed can we
7783          * update the the output configuration. */
7784         intel_modeset_update_state(dev, prepare_pipes);
7785
7786         if (dev_priv->display.modeset_global_resources)
7787                 dev_priv->display.modeset_global_resources(dev);
7788
7789         /* Set up the DPLL and any encoders state that needs to adjust or depend
7790          * on the DPLL.
7791          */
7792         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7793                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7794                                            mode, adjusted_mode,
7795                                            x, y, fb);
7796                 if (!ret)
7797                     goto done;
7798         }
7799
7800         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7801         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7802                 dev_priv->display.crtc_enable(&intel_crtc->base);
7803
7804         if (modeset_pipes) {
7805                 /* Store real post-adjustment hardware mode. */
7806                 crtc->hwmode = *adjusted_mode;
7807
7808                 /* Calculate and store various constants which
7809                  * are later needed by vblank and swap-completion
7810                  * timestamping. They are derived from true hwmode.
7811                  */
7812                 drm_calc_timestamping_constants(crtc);
7813         }
7814
7815         /* FIXME: add subpixel order */
7816 done:
7817         drm_mode_destroy(dev, adjusted_mode);
7818         if (!ret && crtc->enabled) {
7819                 crtc->hwmode = saved_hwmode;
7820                 crtc->mode = saved_mode;
7821         } else {
7822                 intel_modeset_check_state(dev);
7823         }
7824
7825         return ret;
7826 }
7827
7828 #undef for_each_intel_crtc_masked
7829
7830 static void intel_set_config_free(struct intel_set_config *config)
7831 {
7832         if (!config)
7833                 return;
7834
7835         kfree(config->save_connector_encoders);
7836         kfree(config->save_encoder_crtcs);
7837         kfree(config);
7838 }
7839
7840 static int intel_set_config_save_state(struct drm_device *dev,
7841                                        struct intel_set_config *config)
7842 {
7843         struct drm_encoder *encoder;
7844         struct drm_connector *connector;
7845         int count;
7846
7847         config->save_encoder_crtcs =
7848                 kcalloc(dev->mode_config.num_encoder,
7849                         sizeof(struct drm_crtc *), GFP_KERNEL);
7850         if (!config->save_encoder_crtcs)
7851                 return -ENOMEM;
7852
7853         config->save_connector_encoders =
7854                 kcalloc(dev->mode_config.num_connector,
7855                         sizeof(struct drm_encoder *), GFP_KERNEL);
7856         if (!config->save_connector_encoders)
7857                 return -ENOMEM;
7858
7859         /* Copy data. Note that driver private data is not affected.
7860          * Should anything bad happen only the expected state is
7861          * restored, not the drivers personal bookkeeping.
7862          */
7863         count = 0;
7864         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7865                 config->save_encoder_crtcs[count++] = encoder->crtc;
7866         }
7867
7868         count = 0;
7869         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7870                 config->save_connector_encoders[count++] = connector->encoder;
7871         }
7872
7873         return 0;
7874 }
7875
7876 static void intel_set_config_restore_state(struct drm_device *dev,
7877                                            struct intel_set_config *config)
7878 {
7879         struct intel_encoder *encoder;
7880         struct intel_connector *connector;
7881         int count;
7882
7883         count = 0;
7884         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7885                 encoder->new_crtc =
7886                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7887         }
7888
7889         count = 0;
7890         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7891                 connector->new_encoder =
7892                         to_intel_encoder(config->save_connector_encoders[count++]);
7893         }
7894 }
7895
7896 static void
7897 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7898                                       struct intel_set_config *config)
7899 {
7900
7901         /* We should be able to check here if the fb has the same properties
7902          * and then just flip_or_move it */
7903         if (set->crtc->fb != set->fb) {
7904                 /* If we have no fb then treat it as a full mode set */
7905                 if (set->crtc->fb == NULL) {
7906                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7907                         config->mode_changed = true;
7908                 } else if (set->fb == NULL) {
7909                         config->mode_changed = true;
7910                 } else if (set->fb->depth != set->crtc->fb->depth) {
7911                         config->mode_changed = true;
7912                 } else if (set->fb->bits_per_pixel !=
7913                            set->crtc->fb->bits_per_pixel) {
7914                         config->mode_changed = true;
7915                 } else
7916                         config->fb_changed = true;
7917         }
7918
7919         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7920                 config->fb_changed = true;
7921
7922         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7923                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7924                 drm_mode_debug_printmodeline(&set->crtc->mode);
7925                 drm_mode_debug_printmodeline(set->mode);
7926                 config->mode_changed = true;
7927         }
7928 }
7929
7930 static int
7931 intel_modeset_stage_output_state(struct drm_device *dev,
7932                                  struct drm_mode_set *set,
7933                                  struct intel_set_config *config)
7934 {
7935         struct drm_crtc *new_crtc;
7936         struct intel_connector *connector;
7937         struct intel_encoder *encoder;
7938         int count, ro;
7939
7940         /* The upper layers ensure that we either disabl a crtc or have a list
7941          * of connectors. For paranoia, double-check this. */
7942         WARN_ON(!set->fb && (set->num_connectors != 0));
7943         WARN_ON(set->fb && (set->num_connectors == 0));
7944
7945         count = 0;
7946         list_for_each_entry(connector, &dev->mode_config.connector_list,
7947                             base.head) {
7948                 /* Otherwise traverse passed in connector list and get encoders
7949                  * for them. */
7950                 for (ro = 0; ro < set->num_connectors; ro++) {
7951                         if (set->connectors[ro] == &connector->base) {
7952                                 connector->new_encoder = connector->encoder;
7953                                 break;
7954                         }
7955                 }
7956
7957                 /* If we disable the crtc, disable all its connectors. Also, if
7958                  * the connector is on the changing crtc but not on the new
7959                  * connector list, disable it. */
7960                 if ((!set->fb || ro == set->num_connectors) &&
7961                     connector->base.encoder &&
7962                     connector->base.encoder->crtc == set->crtc) {
7963                         connector->new_encoder = NULL;
7964
7965                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7966                                 connector->base.base.id,
7967                                 drm_get_connector_name(&connector->base));
7968                 }
7969
7970
7971                 if (&connector->new_encoder->base != connector->base.encoder) {
7972                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7973                         config->mode_changed = true;
7974                 }
7975
7976                 /* Disable all disconnected encoders. */
7977                 if (connector->base.status == connector_status_disconnected)
7978                         connector->new_encoder = NULL;
7979         }
7980         /* connector->new_encoder is now updated for all connectors. */
7981
7982         /* Update crtc of enabled connectors. */
7983         count = 0;
7984         list_for_each_entry(connector, &dev->mode_config.connector_list,
7985                             base.head) {
7986                 if (!connector->new_encoder)
7987                         continue;
7988
7989                 new_crtc = connector->new_encoder->base.crtc;
7990
7991                 for (ro = 0; ro < set->num_connectors; ro++) {
7992                         if (set->connectors[ro] == &connector->base)
7993                                 new_crtc = set->crtc;
7994                 }
7995
7996                 /* Make sure the new CRTC will work with the encoder */
7997                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7998                                            new_crtc)) {
7999                         return -EINVAL;
8000                 }
8001                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8002
8003                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8004                         connector->base.base.id,
8005                         drm_get_connector_name(&connector->base),
8006                         new_crtc->base.id);
8007         }
8008
8009         /* Check for any encoders that needs to be disabled. */
8010         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8011                             base.head) {
8012                 list_for_each_entry(connector,
8013                                     &dev->mode_config.connector_list,
8014                                     base.head) {
8015                         if (connector->new_encoder == encoder) {
8016                                 WARN_ON(!connector->new_encoder->new_crtc);
8017
8018                                 goto next_encoder;
8019                         }
8020                 }
8021                 encoder->new_crtc = NULL;
8022 next_encoder:
8023                 /* Only now check for crtc changes so we don't miss encoders
8024                  * that will be disabled. */
8025                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8026                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8027                         config->mode_changed = true;
8028                 }
8029         }
8030         /* Now we've also updated encoder->new_crtc for all encoders. */
8031
8032         return 0;
8033 }
8034
8035 static int intel_crtc_set_config(struct drm_mode_set *set)
8036 {
8037         struct drm_device *dev;
8038         struct drm_mode_set save_set;
8039         struct intel_set_config *config;
8040         int ret;
8041
8042         BUG_ON(!set);
8043         BUG_ON(!set->crtc);
8044         BUG_ON(!set->crtc->helper_private);
8045
8046         if (!set->mode)
8047                 set->fb = NULL;
8048
8049         /* The fb helper likes to play gross jokes with ->mode_set_config.
8050          * Unfortunately the crtc helper doesn't do much at all for this case,
8051          * so we have to cope with this madness until the fb helper is fixed up. */
8052         if (set->fb && set->num_connectors == 0)
8053                 return 0;
8054
8055         if (set->fb) {
8056                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8057                                 set->crtc->base.id, set->fb->base.id,
8058                                 (int)set->num_connectors, set->x, set->y);
8059         } else {
8060                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8061         }
8062
8063         dev = set->crtc->dev;
8064
8065         ret = -ENOMEM;
8066         config = kzalloc(sizeof(*config), GFP_KERNEL);
8067         if (!config)
8068                 goto out_config;
8069
8070         ret = intel_set_config_save_state(dev, config);
8071         if (ret)
8072                 goto out_config;
8073
8074         save_set.crtc = set->crtc;
8075         save_set.mode = &set->crtc->mode;
8076         save_set.x = set->crtc->x;
8077         save_set.y = set->crtc->y;
8078         save_set.fb = set->crtc->fb;
8079
8080         /* Compute whether we need a full modeset, only an fb base update or no
8081          * change at all. In the future we might also check whether only the
8082          * mode changed, e.g. for LVDS where we only change the panel fitter in
8083          * such cases. */
8084         intel_set_config_compute_mode_changes(set, config);
8085
8086         ret = intel_modeset_stage_output_state(dev, set, config);
8087         if (ret)
8088                 goto fail;
8089
8090         if (config->mode_changed) {
8091                 if (set->mode) {
8092                         DRM_DEBUG_KMS("attempting to set mode from"
8093                                         " userspace\n");
8094                         drm_mode_debug_printmodeline(set->mode);
8095                 }
8096
8097                 if (!intel_set_mode(set->crtc, set->mode,
8098                                     set->x, set->y, set->fb)) {
8099                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8100                                   set->crtc->base.id);
8101                         ret = -EINVAL;
8102                         goto fail;
8103                 }
8104         } else if (config->fb_changed) {
8105                 ret = intel_pipe_set_base(set->crtc,
8106                                           set->x, set->y, set->fb);
8107         }
8108
8109         intel_set_config_free(config);
8110
8111         return 0;
8112
8113 fail:
8114         intel_set_config_restore_state(dev, config);
8115
8116         /* Try to restore the config */
8117         if (config->mode_changed &&
8118             !intel_set_mode(save_set.crtc, save_set.mode,
8119                             save_set.x, save_set.y, save_set.fb))
8120                 DRM_ERROR("failed to restore config after modeset failure\n");
8121
8122 out_config:
8123         intel_set_config_free(config);
8124         return ret;
8125 }
8126
8127 static const struct drm_crtc_funcs intel_crtc_funcs = {
8128         .cursor_set = intel_crtc_cursor_set,
8129         .cursor_move = intel_crtc_cursor_move,
8130         .gamma_set = intel_crtc_gamma_set,
8131         .set_config = intel_crtc_set_config,
8132         .destroy = intel_crtc_destroy,
8133         .page_flip = intel_crtc_page_flip,
8134 };
8135
8136 static void intel_cpu_pll_init(struct drm_device *dev)
8137 {
8138         if (IS_HASWELL(dev))
8139                 intel_ddi_pll_init(dev);
8140 }
8141
8142 static void intel_pch_pll_init(struct drm_device *dev)
8143 {
8144         drm_i915_private_t *dev_priv = dev->dev_private;
8145         int i;
8146
8147         if (dev_priv->num_pch_pll == 0) {
8148                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8149                 return;
8150         }
8151
8152         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8153                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8154                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8155                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8156         }
8157 }
8158
8159 static void intel_crtc_init(struct drm_device *dev, int pipe)
8160 {
8161         drm_i915_private_t *dev_priv = dev->dev_private;
8162         struct intel_crtc *intel_crtc;
8163         int i;
8164
8165         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8166         if (intel_crtc == NULL)
8167                 return;
8168
8169         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8170
8171         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8172         for (i = 0; i < 256; i++) {
8173                 intel_crtc->lut_r[i] = i;
8174                 intel_crtc->lut_g[i] = i;
8175                 intel_crtc->lut_b[i] = i;
8176         }
8177
8178         /* Swap pipes & planes for FBC on pre-965 */
8179         intel_crtc->pipe = pipe;
8180         intel_crtc->plane = pipe;
8181         intel_crtc->cpu_transcoder = pipe;
8182         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8183                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8184                 intel_crtc->plane = !pipe;
8185         }
8186
8187         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8188                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8189         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8190         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8191
8192         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8193
8194         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8195 }
8196
8197 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8198                                 struct drm_file *file)
8199 {
8200         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8201         struct drm_mode_object *drmmode_obj;
8202         struct intel_crtc *crtc;
8203
8204         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8205                 return -ENODEV;
8206
8207         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8208                         DRM_MODE_OBJECT_CRTC);
8209
8210         if (!drmmode_obj) {
8211                 DRM_ERROR("no such CRTC id\n");
8212                 return -EINVAL;
8213         }
8214
8215         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8216         pipe_from_crtc_id->pipe = crtc->pipe;
8217
8218         return 0;
8219 }
8220
8221 static int intel_encoder_clones(struct intel_encoder *encoder)
8222 {
8223         struct drm_device *dev = encoder->base.dev;
8224         struct intel_encoder *source_encoder;
8225         int index_mask = 0;
8226         int entry = 0;
8227
8228         list_for_each_entry(source_encoder,
8229                             &dev->mode_config.encoder_list, base.head) {
8230
8231                 if (encoder == source_encoder)
8232                         index_mask |= (1 << entry);
8233
8234                 /* Intel hw has only one MUX where enocoders could be cloned. */
8235                 if (encoder->cloneable && source_encoder->cloneable)
8236                         index_mask |= (1 << entry);
8237
8238                 entry++;
8239         }
8240
8241         return index_mask;
8242 }
8243
8244 static bool has_edp_a(struct drm_device *dev)
8245 {
8246         struct drm_i915_private *dev_priv = dev->dev_private;
8247
8248         if (!IS_MOBILE(dev))
8249                 return false;
8250
8251         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8252                 return false;
8253
8254         if (IS_GEN5(dev) &&
8255             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8256                 return false;
8257
8258         return true;
8259 }
8260
8261 static void intel_setup_outputs(struct drm_device *dev)
8262 {
8263         struct drm_i915_private *dev_priv = dev->dev_private;
8264         struct intel_encoder *encoder;
8265         bool dpd_is_edp = false;
8266         bool has_lvds;
8267
8268         has_lvds = intel_lvds_init(dev);
8269         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8270                 /* disable the panel fitter on everything but LVDS */
8271                 I915_WRITE(PFIT_CONTROL, 0);
8272         }
8273
8274         if (!(IS_HASWELL(dev) &&
8275               (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8276                 intel_crt_init(dev);
8277
8278         if (IS_HASWELL(dev)) {
8279                 int found;
8280
8281                 /* Haswell uses DDI functions to detect digital outputs */
8282                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8283                 /* DDI A only supports eDP */
8284                 if (found)
8285                         intel_ddi_init(dev, PORT_A);
8286
8287                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8288                  * register */
8289                 found = I915_READ(SFUSE_STRAP);
8290
8291                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8292                         intel_ddi_init(dev, PORT_B);
8293                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8294                         intel_ddi_init(dev, PORT_C);
8295                 if (found & SFUSE_STRAP_DDID_DETECTED)
8296                         intel_ddi_init(dev, PORT_D);
8297         } else if (HAS_PCH_SPLIT(dev)) {
8298                 int found;
8299                 dpd_is_edp = intel_dpd_is_edp(dev);
8300
8301                 if (has_edp_a(dev))
8302                         intel_dp_init(dev, DP_A, PORT_A);
8303
8304                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8305                         /* PCH SDVOB multiplex with HDMIB */
8306                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8307                         if (!found)
8308                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8309                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8310                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8311                 }
8312
8313                 if (I915_READ(HDMIC) & PORT_DETECTED)
8314                         intel_hdmi_init(dev, HDMIC, PORT_C);
8315
8316                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8317                         intel_hdmi_init(dev, HDMID, PORT_D);
8318
8319                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8320                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8321
8322                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8323                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8324         } else if (IS_VALLEYVIEW(dev)) {
8325                 int found;
8326
8327                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8328                 if (I915_READ(DP_C) & DP_DETECTED)
8329                         intel_dp_init(dev, DP_C, PORT_C);
8330
8331                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8332                         /* SDVOB multiplex with HDMIB */
8333                         found = intel_sdvo_init(dev, SDVOB, true);
8334                         if (!found)
8335                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8336                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8337                                 intel_dp_init(dev, DP_B, PORT_B);
8338                 }
8339
8340                 if (I915_READ(SDVOC) & PORT_DETECTED)
8341                         intel_hdmi_init(dev, SDVOC, PORT_C);
8342
8343         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8344                 bool found = false;
8345
8346                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8347                         DRM_DEBUG_KMS("probing SDVOB\n");
8348                         found = intel_sdvo_init(dev, SDVOB, true);
8349                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8350                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8351                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8352                         }
8353
8354                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8355                                 DRM_DEBUG_KMS("probing DP_B\n");
8356                                 intel_dp_init(dev, DP_B, PORT_B);
8357                         }
8358                 }
8359
8360                 /* Before G4X SDVOC doesn't have its own detect register */
8361
8362                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8363                         DRM_DEBUG_KMS("probing SDVOC\n");
8364                         found = intel_sdvo_init(dev, SDVOC, false);
8365                 }
8366
8367                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8368
8369                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8370                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8371                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8372                         }
8373                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8374                                 DRM_DEBUG_KMS("probing DP_C\n");
8375                                 intel_dp_init(dev, DP_C, PORT_C);
8376                         }
8377                 }
8378
8379                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8380                     (I915_READ(DP_D) & DP_DETECTED)) {
8381                         DRM_DEBUG_KMS("probing DP_D\n");
8382                         intel_dp_init(dev, DP_D, PORT_D);
8383                 }
8384         } else if (IS_GEN2(dev))
8385                 intel_dvo_init(dev);
8386
8387         if (SUPPORTS_TV(dev))
8388                 intel_tv_init(dev);
8389
8390         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8391                 encoder->base.possible_crtcs = encoder->crtc_mask;
8392                 encoder->base.possible_clones =
8393                         intel_encoder_clones(encoder);
8394         }
8395
8396         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8397                 ironlake_init_pch_refclk(dev);
8398
8399         drm_helper_move_panel_connectors_to_head(dev);
8400 }
8401
8402 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8403 {
8404         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8405
8406         drm_framebuffer_cleanup(fb);
8407         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8408
8409         kfree(intel_fb);
8410 }
8411
8412 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8413                                                 struct drm_file *file,
8414                                                 unsigned int *handle)
8415 {
8416         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8417         struct drm_i915_gem_object *obj = intel_fb->obj;
8418
8419         return drm_gem_handle_create(file, &obj->base, handle);
8420 }
8421
8422 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8423         .destroy = intel_user_framebuffer_destroy,
8424         .create_handle = intel_user_framebuffer_create_handle,
8425 };
8426
8427 int intel_framebuffer_init(struct drm_device *dev,
8428                            struct intel_framebuffer *intel_fb,
8429                            struct drm_mode_fb_cmd2 *mode_cmd,
8430                            struct drm_i915_gem_object *obj)
8431 {
8432         int ret;
8433
8434         if (obj->tiling_mode == I915_TILING_Y)
8435                 return -EINVAL;
8436
8437         if (mode_cmd->pitches[0] & 63)
8438                 return -EINVAL;
8439
8440         /* FIXME <= Gen4 stride limits are bit unclear */
8441         if (mode_cmd->pitches[0] > 32768)
8442                 return -EINVAL;
8443
8444         if (obj->tiling_mode != I915_TILING_NONE &&
8445             mode_cmd->pitches[0] != obj->stride)
8446                 return -EINVAL;
8447
8448         /* Reject formats not supported by any plane early. */
8449         switch (mode_cmd->pixel_format) {
8450         case DRM_FORMAT_C8:
8451         case DRM_FORMAT_RGB565:
8452         case DRM_FORMAT_XRGB8888:
8453         case DRM_FORMAT_ARGB8888:
8454                 break;
8455         case DRM_FORMAT_XRGB1555:
8456         case DRM_FORMAT_ARGB1555:
8457                 if (INTEL_INFO(dev)->gen > 3)
8458                         return -EINVAL;
8459                 break;
8460         case DRM_FORMAT_XBGR8888:
8461         case DRM_FORMAT_ABGR8888:
8462         case DRM_FORMAT_XRGB2101010:
8463         case DRM_FORMAT_ARGB2101010:
8464         case DRM_FORMAT_XBGR2101010:
8465         case DRM_FORMAT_ABGR2101010:
8466                 if (INTEL_INFO(dev)->gen < 4)
8467                         return -EINVAL;
8468                 break;
8469         case DRM_FORMAT_YUYV:
8470         case DRM_FORMAT_UYVY:
8471         case DRM_FORMAT_YVYU:
8472         case DRM_FORMAT_VYUY:
8473                 if (INTEL_INFO(dev)->gen < 6)
8474                         return -EINVAL;
8475                 break;
8476         default:
8477                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8478                 return -EINVAL;
8479         }
8480
8481         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8482         if (mode_cmd->offsets[0] != 0)
8483                 return -EINVAL;
8484
8485         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8486         if (ret) {
8487                 DRM_ERROR("framebuffer init failed %d\n", ret);
8488                 return ret;
8489         }
8490
8491         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8492         intel_fb->obj = obj;
8493         return 0;
8494 }
8495
8496 static struct drm_framebuffer *
8497 intel_user_framebuffer_create(struct drm_device *dev,
8498                               struct drm_file *filp,
8499                               struct drm_mode_fb_cmd2 *mode_cmd)
8500 {
8501         struct drm_i915_gem_object *obj;
8502
8503         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8504                                                 mode_cmd->handles[0]));
8505         if (&obj->base == NULL)
8506                 return ERR_PTR(-ENOENT);
8507
8508         return intel_framebuffer_create(dev, mode_cmd, obj);
8509 }
8510
8511 static const struct drm_mode_config_funcs intel_mode_funcs = {
8512         .fb_create = intel_user_framebuffer_create,
8513         .output_poll_changed = intel_fb_output_poll_changed,
8514 };
8515
8516 /* Set up chip specific display functions */
8517 static void intel_init_display(struct drm_device *dev)
8518 {
8519         struct drm_i915_private *dev_priv = dev->dev_private;
8520
8521         /* We always want a DPMS function */
8522         if (IS_HASWELL(dev)) {
8523                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8524                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8525                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8526                 dev_priv->display.off = haswell_crtc_off;
8527                 dev_priv->display.update_plane = ironlake_update_plane;
8528         } else if (HAS_PCH_SPLIT(dev)) {
8529                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8530                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8531                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8532                 dev_priv->display.off = ironlake_crtc_off;
8533                 dev_priv->display.update_plane = ironlake_update_plane;
8534         } else {
8535                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8536                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8537                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8538                 dev_priv->display.off = i9xx_crtc_off;
8539                 dev_priv->display.update_plane = i9xx_update_plane;
8540         }
8541
8542         /* Returns the core display clock speed */
8543         if (IS_VALLEYVIEW(dev))
8544                 dev_priv->display.get_display_clock_speed =
8545                         valleyview_get_display_clock_speed;
8546         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8547                 dev_priv->display.get_display_clock_speed =
8548                         i945_get_display_clock_speed;
8549         else if (IS_I915G(dev))
8550                 dev_priv->display.get_display_clock_speed =
8551                         i915_get_display_clock_speed;
8552         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8553                 dev_priv->display.get_display_clock_speed =
8554                         i9xx_misc_get_display_clock_speed;
8555         else if (IS_I915GM(dev))
8556                 dev_priv->display.get_display_clock_speed =
8557                         i915gm_get_display_clock_speed;
8558         else if (IS_I865G(dev))
8559                 dev_priv->display.get_display_clock_speed =
8560                         i865_get_display_clock_speed;
8561         else if (IS_I85X(dev))
8562                 dev_priv->display.get_display_clock_speed =
8563                         i855_get_display_clock_speed;
8564         else /* 852, 830 */
8565                 dev_priv->display.get_display_clock_speed =
8566                         i830_get_display_clock_speed;
8567
8568         if (HAS_PCH_SPLIT(dev)) {
8569                 if (IS_GEN5(dev)) {
8570                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8571                         dev_priv->display.write_eld = ironlake_write_eld;
8572                 } else if (IS_GEN6(dev)) {
8573                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8574                         dev_priv->display.write_eld = ironlake_write_eld;
8575                 } else if (IS_IVYBRIDGE(dev)) {
8576                         /* FIXME: detect B0+ stepping and use auto training */
8577                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8578                         dev_priv->display.write_eld = ironlake_write_eld;
8579                         dev_priv->display.modeset_global_resources =
8580                                 ivb_modeset_global_resources;
8581                 } else if (IS_HASWELL(dev)) {
8582                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8583                         dev_priv->display.write_eld = haswell_write_eld;
8584                 } else
8585                         dev_priv->display.update_wm = NULL;
8586         } else if (IS_G4X(dev)) {
8587                 dev_priv->display.write_eld = g4x_write_eld;
8588         }
8589
8590         /* Default just returns -ENODEV to indicate unsupported */
8591         dev_priv->display.queue_flip = intel_default_queue_flip;
8592
8593         switch (INTEL_INFO(dev)->gen) {
8594         case 2:
8595                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8596                 break;
8597
8598         case 3:
8599                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8600                 break;
8601
8602         case 4:
8603         case 5:
8604                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8605                 break;
8606
8607         case 6:
8608                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8609                 break;
8610         case 7:
8611                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8612                 break;
8613         }
8614 }
8615
8616 /*
8617  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8618  * resume, or other times.  This quirk makes sure that's the case for
8619  * affected systems.
8620  */
8621 static void quirk_pipea_force(struct drm_device *dev)
8622 {
8623         struct drm_i915_private *dev_priv = dev->dev_private;
8624
8625         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8626         DRM_INFO("applying pipe a force quirk\n");
8627 }
8628
8629 /*
8630  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8631  */
8632 static void quirk_ssc_force_disable(struct drm_device *dev)
8633 {
8634         struct drm_i915_private *dev_priv = dev->dev_private;
8635         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8636         DRM_INFO("applying lvds SSC disable quirk\n");
8637 }
8638
8639 /*
8640  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8641  * brightness value
8642  */
8643 static void quirk_invert_brightness(struct drm_device *dev)
8644 {
8645         struct drm_i915_private *dev_priv = dev->dev_private;
8646         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8647         DRM_INFO("applying inverted panel brightness quirk\n");
8648 }
8649
8650 struct intel_quirk {
8651         int device;
8652         int subsystem_vendor;
8653         int subsystem_device;
8654         void (*hook)(struct drm_device *dev);
8655 };
8656
8657 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8658 struct intel_dmi_quirk {
8659         void (*hook)(struct drm_device *dev);
8660         const struct dmi_system_id (*dmi_id_list)[];
8661 };
8662
8663 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8664 {
8665         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8666         return 1;
8667 }
8668
8669 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8670         {
8671                 .dmi_id_list = &(const struct dmi_system_id[]) {
8672                         {
8673                                 .callback = intel_dmi_reverse_brightness,
8674                                 .ident = "NCR Corporation",
8675                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8676                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8677                                 },
8678                         },
8679                         { }  /* terminating entry */
8680                 },
8681                 .hook = quirk_invert_brightness,
8682         },
8683 };
8684
8685 static struct intel_quirk intel_quirks[] = {
8686         /* HP Mini needs pipe A force quirk (LP: #322104) */
8687         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8688
8689         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8690         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8691
8692         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8693         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8694
8695         /* 830/845 need to leave pipe A & dpll A up */
8696         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8697         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8698
8699         /* Lenovo U160 cannot use SSC on LVDS */
8700         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8701
8702         /* Sony Vaio Y cannot use SSC on LVDS */
8703         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8704
8705         /* Acer Aspire 5734Z must invert backlight brightness */
8706         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8707 };
8708
8709 static void intel_init_quirks(struct drm_device *dev)
8710 {
8711         struct pci_dev *d = dev->pdev;
8712         int i;
8713
8714         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8715                 struct intel_quirk *q = &intel_quirks[i];
8716
8717                 if (d->device == q->device &&
8718                     (d->subsystem_vendor == q->subsystem_vendor ||
8719                      q->subsystem_vendor == PCI_ANY_ID) &&
8720                     (d->subsystem_device == q->subsystem_device ||
8721                      q->subsystem_device == PCI_ANY_ID))
8722                         q->hook(dev);
8723         }
8724         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8725                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8726                         intel_dmi_quirks[i].hook(dev);
8727         }
8728 }
8729
8730 /* Disable the VGA plane that we never use */
8731 static void i915_disable_vga(struct drm_device *dev)
8732 {
8733         struct drm_i915_private *dev_priv = dev->dev_private;
8734         u8 sr1;
8735         u32 vga_reg;
8736
8737         if (HAS_PCH_SPLIT(dev))
8738                 vga_reg = CPU_VGACNTRL;
8739         else
8740                 vga_reg = VGACNTRL;
8741
8742         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8743         outb(SR01, VGA_SR_INDEX);
8744         sr1 = inb(VGA_SR_DATA);
8745         outb(sr1 | 1<<5, VGA_SR_DATA);
8746         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8747         udelay(300);
8748
8749         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8750         POSTING_READ(vga_reg);
8751 }
8752
8753 void intel_modeset_init_hw(struct drm_device *dev)
8754 {
8755         /* We attempt to init the necessary power wells early in the initialization
8756          * time, so the subsystems that expect power to be enabled can work.
8757          */
8758         intel_init_power_wells(dev);
8759
8760         intel_prepare_ddi(dev);
8761
8762         intel_init_clock_gating(dev);
8763
8764         mutex_lock(&dev->struct_mutex);
8765         intel_enable_gt_powersave(dev);
8766         mutex_unlock(&dev->struct_mutex);
8767 }
8768
8769 void intel_modeset_init(struct drm_device *dev)
8770 {
8771         struct drm_i915_private *dev_priv = dev->dev_private;
8772         int i, ret;
8773
8774         drm_mode_config_init(dev);
8775
8776         dev->mode_config.min_width = 0;
8777         dev->mode_config.min_height = 0;
8778
8779         dev->mode_config.preferred_depth = 24;
8780         dev->mode_config.prefer_shadow = 1;
8781
8782         dev->mode_config.funcs = &intel_mode_funcs;
8783
8784         intel_init_quirks(dev);
8785
8786         intel_init_pm(dev);
8787
8788         intel_init_display(dev);
8789
8790         if (IS_GEN2(dev)) {
8791                 dev->mode_config.max_width = 2048;
8792                 dev->mode_config.max_height = 2048;
8793         } else if (IS_GEN3(dev)) {
8794                 dev->mode_config.max_width = 4096;
8795                 dev->mode_config.max_height = 4096;
8796         } else {
8797                 dev->mode_config.max_width = 8192;
8798                 dev->mode_config.max_height = 8192;
8799         }
8800         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8801
8802         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8803                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8804
8805         for (i = 0; i < dev_priv->num_pipe; i++) {
8806                 intel_crtc_init(dev, i);
8807                 ret = intel_plane_init(dev, i);
8808                 if (ret)
8809                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8810         }
8811
8812         intel_cpu_pll_init(dev);
8813         intel_pch_pll_init(dev);
8814
8815         /* Just disable it once at startup */
8816         i915_disable_vga(dev);
8817         intel_setup_outputs(dev);
8818 }
8819
8820 static void
8821 intel_connector_break_all_links(struct intel_connector *connector)
8822 {
8823         connector->base.dpms = DRM_MODE_DPMS_OFF;
8824         connector->base.encoder = NULL;
8825         connector->encoder->connectors_active = false;
8826         connector->encoder->base.crtc = NULL;
8827 }
8828
8829 static void intel_enable_pipe_a(struct drm_device *dev)
8830 {
8831         struct intel_connector *connector;
8832         struct drm_connector *crt = NULL;
8833         struct intel_load_detect_pipe load_detect_temp;
8834
8835         /* We can't just switch on the pipe A, we need to set things up with a
8836          * proper mode and output configuration. As a gross hack, enable pipe A
8837          * by enabling the load detect pipe once. */
8838         list_for_each_entry(connector,
8839                             &dev->mode_config.connector_list,
8840                             base.head) {
8841                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8842                         crt = &connector->base;
8843                         break;
8844                 }
8845         }
8846
8847         if (!crt)
8848                 return;
8849
8850         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8851                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8852
8853
8854 }
8855
8856 static bool
8857 intel_check_plane_mapping(struct intel_crtc *crtc)
8858 {
8859         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8860         u32 reg, val;
8861
8862         if (dev_priv->num_pipe == 1)
8863                 return true;
8864
8865         reg = DSPCNTR(!crtc->plane);
8866         val = I915_READ(reg);
8867
8868         if ((val & DISPLAY_PLANE_ENABLE) &&
8869             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8870                 return false;
8871
8872         return true;
8873 }
8874
8875 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8876 {
8877         struct drm_device *dev = crtc->base.dev;
8878         struct drm_i915_private *dev_priv = dev->dev_private;
8879         u32 reg;
8880
8881         /* Clear any frame start delays used for debugging left by the BIOS */
8882         reg = PIPECONF(crtc->cpu_transcoder);
8883         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8884
8885         /* We need to sanitize the plane -> pipe mapping first because this will
8886          * disable the crtc (and hence change the state) if it is wrong. Note
8887          * that gen4+ has a fixed plane -> pipe mapping.  */
8888         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8889                 struct intel_connector *connector;
8890                 bool plane;
8891
8892                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8893                               crtc->base.base.id);
8894
8895                 /* Pipe has the wrong plane attached and the plane is active.
8896                  * Temporarily change the plane mapping and disable everything
8897                  * ...  */
8898                 plane = crtc->plane;
8899                 crtc->plane = !plane;
8900                 dev_priv->display.crtc_disable(&crtc->base);
8901                 crtc->plane = plane;
8902
8903                 /* ... and break all links. */
8904                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8905                                     base.head) {
8906                         if (connector->encoder->base.crtc != &crtc->base)
8907                                 continue;
8908
8909                         intel_connector_break_all_links(connector);
8910                 }
8911
8912                 WARN_ON(crtc->active);
8913                 crtc->base.enabled = false;
8914         }
8915
8916         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8917             crtc->pipe == PIPE_A && !crtc->active) {
8918                 /* BIOS forgot to enable pipe A, this mostly happens after
8919                  * resume. Force-enable the pipe to fix this, the update_dpms
8920                  * call below we restore the pipe to the right state, but leave
8921                  * the required bits on. */
8922                 intel_enable_pipe_a(dev);
8923         }
8924
8925         /* Adjust the state of the output pipe according to whether we
8926          * have active connectors/encoders. */
8927         intel_crtc_update_dpms(&crtc->base);
8928
8929         if (crtc->active != crtc->base.enabled) {
8930                 struct intel_encoder *encoder;
8931
8932                 /* This can happen either due to bugs in the get_hw_state
8933                  * functions or because the pipe is force-enabled due to the
8934                  * pipe A quirk. */
8935                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8936                               crtc->base.base.id,
8937                               crtc->base.enabled ? "enabled" : "disabled",
8938                               crtc->active ? "enabled" : "disabled");
8939
8940                 crtc->base.enabled = crtc->active;
8941
8942                 /* Because we only establish the connector -> encoder ->
8943                  * crtc links if something is active, this means the
8944                  * crtc is now deactivated. Break the links. connector
8945                  * -> encoder links are only establish when things are
8946                  *  actually up, hence no need to break them. */
8947                 WARN_ON(crtc->active);
8948
8949                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8950                         WARN_ON(encoder->connectors_active);
8951                         encoder->base.crtc = NULL;
8952                 }
8953         }
8954 }
8955
8956 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8957 {
8958         struct intel_connector *connector;
8959         struct drm_device *dev = encoder->base.dev;
8960
8961         /* We need to check both for a crtc link (meaning that the
8962          * encoder is active and trying to read from a pipe) and the
8963          * pipe itself being active. */
8964         bool has_active_crtc = encoder->base.crtc &&
8965                 to_intel_crtc(encoder->base.crtc)->active;
8966
8967         if (encoder->connectors_active && !has_active_crtc) {
8968                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8969                               encoder->base.base.id,
8970                               drm_get_encoder_name(&encoder->base));
8971
8972                 /* Connector is active, but has no active pipe. This is
8973                  * fallout from our resume register restoring. Disable
8974                  * the encoder manually again. */
8975                 if (encoder->base.crtc) {
8976                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8977                                       encoder->base.base.id,
8978                                       drm_get_encoder_name(&encoder->base));
8979                         encoder->disable(encoder);
8980                 }
8981
8982                 /* Inconsistent output/port/pipe state happens presumably due to
8983                  * a bug in one of the get_hw_state functions. Or someplace else
8984                  * in our code, like the register restore mess on resume. Clamp
8985                  * things to off as a safer default. */
8986                 list_for_each_entry(connector,
8987                                     &dev->mode_config.connector_list,
8988                                     base.head) {
8989                         if (connector->encoder != encoder)
8990                                 continue;
8991
8992                         intel_connector_break_all_links(connector);
8993                 }
8994         }
8995         /* Enabled encoders without active connectors will be fixed in
8996          * the crtc fixup. */
8997 }
8998
8999 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9000  * and i915 state tracking structures. */
9001 void intel_modeset_setup_hw_state(struct drm_device *dev)
9002 {
9003         struct drm_i915_private *dev_priv = dev->dev_private;
9004         enum pipe pipe;
9005         u32 tmp;
9006         struct intel_crtc *crtc;
9007         struct intel_encoder *encoder;
9008         struct intel_connector *connector;
9009
9010         if (IS_HASWELL(dev)) {
9011                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9012
9013                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9014                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9015                         case TRANS_DDI_EDP_INPUT_A_ON:
9016                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9017                                 pipe = PIPE_A;
9018                                 break;
9019                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9020                                 pipe = PIPE_B;
9021                                 break;
9022                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9023                                 pipe = PIPE_C;
9024                                 break;
9025                         }
9026
9027                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9028                         crtc->cpu_transcoder = TRANSCODER_EDP;
9029
9030                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9031                                       pipe_name(pipe));
9032                 }
9033         }
9034
9035         for_each_pipe(pipe) {
9036                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9037
9038                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9039                 if (tmp & PIPECONF_ENABLE)
9040                         crtc->active = true;
9041                 else
9042                         crtc->active = false;
9043
9044                 crtc->base.enabled = crtc->active;
9045
9046                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9047                               crtc->base.base.id,
9048                               crtc->active ? "enabled" : "disabled");
9049         }
9050
9051         if (IS_HASWELL(dev))
9052                 intel_ddi_setup_hw_pll_state(dev);
9053
9054         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9055                             base.head) {
9056                 pipe = 0;
9057
9058                 if (encoder->get_hw_state(encoder, &pipe)) {
9059                         encoder->base.crtc =
9060                                 dev_priv->pipe_to_crtc_mapping[pipe];
9061                 } else {
9062                         encoder->base.crtc = NULL;
9063                 }
9064
9065                 encoder->connectors_active = false;
9066                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9067                               encoder->base.base.id,
9068                               drm_get_encoder_name(&encoder->base),
9069                               encoder->base.crtc ? "enabled" : "disabled",
9070                               pipe);
9071         }
9072
9073         list_for_each_entry(connector, &dev->mode_config.connector_list,
9074                             base.head) {
9075                 if (connector->get_hw_state(connector)) {
9076                         connector->base.dpms = DRM_MODE_DPMS_ON;
9077                         connector->encoder->connectors_active = true;
9078                         connector->base.encoder = &connector->encoder->base;
9079                 } else {
9080                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9081                         connector->base.encoder = NULL;
9082                 }
9083                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9084                               connector->base.base.id,
9085                               drm_get_connector_name(&connector->base),
9086                               connector->base.encoder ? "enabled" : "disabled");
9087         }
9088
9089         /* HW state is read out, now we need to sanitize this mess. */
9090         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9091                             base.head) {
9092                 intel_sanitize_encoder(encoder);
9093         }
9094
9095         for_each_pipe(pipe) {
9096                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9097                 intel_sanitize_crtc(crtc);
9098         }
9099
9100         intel_modeset_update_staged_output_state(dev);
9101
9102         intel_modeset_check_state(dev);
9103
9104         drm_mode_config_reset(dev);
9105 }
9106
9107 void intel_modeset_gem_init(struct drm_device *dev)
9108 {
9109         intel_modeset_init_hw(dev);
9110
9111         intel_setup_overlay(dev);
9112
9113         intel_modeset_setup_hw_state(dev);
9114 }
9115
9116 void intel_modeset_cleanup(struct drm_device *dev)
9117 {
9118         struct drm_i915_private *dev_priv = dev->dev_private;
9119         struct drm_crtc *crtc;
9120         struct intel_crtc *intel_crtc;
9121
9122         drm_kms_helper_poll_fini(dev);
9123         mutex_lock(&dev->struct_mutex);
9124
9125         intel_unregister_dsm_handler();
9126
9127
9128         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9129                 /* Skip inactive CRTCs */
9130                 if (!crtc->fb)
9131                         continue;
9132
9133                 intel_crtc = to_intel_crtc(crtc);
9134                 intel_increase_pllclock(crtc);
9135         }
9136
9137         intel_disable_fbc(dev);
9138
9139         intel_disable_gt_powersave(dev);
9140
9141         ironlake_teardown_rc6(dev);
9142
9143         if (IS_VALLEYVIEW(dev))
9144                 vlv_init_dpio(dev);
9145
9146         mutex_unlock(&dev->struct_mutex);
9147
9148         /* Disable the irq before mode object teardown, for the irq might
9149          * enqueue unpin/hotplug work. */
9150         drm_irq_uninstall(dev);
9151         cancel_work_sync(&dev_priv->hotplug_work);
9152         cancel_work_sync(&dev_priv->rps.work);
9153
9154         /* flush any delayed tasks or pending work */
9155         flush_scheduled_work();
9156
9157         drm_mode_config_cleanup(dev);
9158 }
9159
9160 /*
9161  * Return which encoder is currently attached for connector.
9162  */
9163 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9164 {
9165         return &intel_attached_encoder(connector)->base;
9166 }
9167
9168 void intel_connector_attach_encoder(struct intel_connector *connector,
9169                                     struct intel_encoder *encoder)
9170 {
9171         connector->encoder = encoder;
9172         drm_mode_connector_attach_encoder(&connector->base,
9173                                           &encoder->base);
9174 }
9175
9176 /*
9177  * set vga decode state - true == enable VGA decode
9178  */
9179 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9180 {
9181         struct drm_i915_private *dev_priv = dev->dev_private;
9182         u16 gmch_ctrl;
9183
9184         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9185         if (state)
9186                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9187         else
9188                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9189         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9190         return 0;
9191 }
9192
9193 #ifdef CONFIG_DEBUG_FS
9194 #include <linux/seq_file.h>
9195
9196 struct intel_display_error_state {
9197         struct intel_cursor_error_state {
9198                 u32 control;
9199                 u32 position;
9200                 u32 base;
9201                 u32 size;
9202         } cursor[I915_MAX_PIPES];
9203
9204         struct intel_pipe_error_state {
9205                 u32 conf;
9206                 u32 source;
9207
9208                 u32 htotal;
9209                 u32 hblank;
9210                 u32 hsync;
9211                 u32 vtotal;
9212                 u32 vblank;
9213                 u32 vsync;
9214         } pipe[I915_MAX_PIPES];
9215
9216         struct intel_plane_error_state {
9217                 u32 control;
9218                 u32 stride;
9219                 u32 size;
9220                 u32 pos;
9221                 u32 addr;
9222                 u32 surface;
9223                 u32 tile_offset;
9224         } plane[I915_MAX_PIPES];
9225 };
9226
9227 struct intel_display_error_state *
9228 intel_display_capture_error_state(struct drm_device *dev)
9229 {
9230         drm_i915_private_t *dev_priv = dev->dev_private;
9231         struct intel_display_error_state *error;
9232         enum transcoder cpu_transcoder;
9233         int i;
9234
9235         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9236         if (error == NULL)
9237                 return NULL;
9238
9239         for_each_pipe(i) {
9240                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9241
9242                 error->cursor[i].control = I915_READ(CURCNTR(i));
9243                 error->cursor[i].position = I915_READ(CURPOS(i));
9244                 error->cursor[i].base = I915_READ(CURBASE(i));
9245
9246                 error->plane[i].control = I915_READ(DSPCNTR(i));
9247                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9248                 error->plane[i].size = I915_READ(DSPSIZE(i));
9249                 error->plane[i].pos = I915_READ(DSPPOS(i));
9250                 error->plane[i].addr = I915_READ(DSPADDR(i));
9251                 if (INTEL_INFO(dev)->gen >= 4) {
9252                         error->plane[i].surface = I915_READ(DSPSURF(i));
9253                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9254                 }
9255
9256                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9257                 error->pipe[i].source = I915_READ(PIPESRC(i));
9258                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9259                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9260                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9261                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9262                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9263                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9264         }
9265
9266         return error;
9267 }
9268
9269 void
9270 intel_display_print_error_state(struct seq_file *m,
9271                                 struct drm_device *dev,
9272                                 struct intel_display_error_state *error)
9273 {
9274         drm_i915_private_t *dev_priv = dev->dev_private;
9275         int i;
9276
9277         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9278         for_each_pipe(i) {
9279                 seq_printf(m, "Pipe [%d]:\n", i);
9280                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9281                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9282                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9283                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9284                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9285                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9286                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9287                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9288
9289                 seq_printf(m, "Plane [%d]:\n", i);
9290                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9291                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9292                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9293                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9294                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9295                 if (INTEL_INFO(dev)->gen >= 4) {
9296                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9297                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9298                 }
9299
9300                 seq_printf(m, "Cursor [%d]:\n", i);
9301                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9302                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9303                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9304         }
9305 }
9306 #endif