2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
186 .find_pll = intel_g4x_find_best_PLL,
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
215 .find_pll = intel_g4x_find_best_PLL,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
230 .find_pll = intel_g4x_find_best_PLL,
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val = I915_READ(DPIO_DATA);
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
456 static void vlv_init_dpio(struct drm_device *dev)
458 struct drm_i915_private *dev_priv = dev->dev_private;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
494 if (dmi_check_system(intel_dual_link_lvds))
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
526 limit = &intel_limits_ironlake_dual_lvds;
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
531 limit = &intel_limits_ironlake_single_lvds;
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
535 limit = &intel_limits_ironlake_display_port;
537 limit = &intel_limits_ironlake_dac;
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
593 limit = &intel_limits_i9xx_sdvo;
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
598 limit = &intel_limits_i8xx_dvo;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
696 clock.p2 = limit->p2.p2_slow;
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
701 clock.p2 = limit->p2.p2_fast;
704 memset(best_clock, 0, sizeof(*best_clock));
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
724 clock.p != match_clock->p)
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
737 return (err != target);
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
757 if (HAS_PCH_SPLIT(dev))
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
763 clock.p2 = limit->p2.p2_fast;
765 clock.p2 = limit->p2.p2_slow;
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
770 clock.p2 = limit->p2.p2_fast;
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
791 clock.p != match_clock->p)
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
813 struct drm_device *dev = crtc->dev;
816 if (target < 200000) {
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
841 if (target < 200000) {
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
873 dotclk = target * 1000;
876 fastclk = dotclk / (2*100);
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
904 if (absppm < bestppm - 10) {
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
935 frame = I915_READ(frame_reg);
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 /* Wait for the display line to settle */
1022 last_line = I915_READ(reg) & line_mask;
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled)
1033 return enabled ? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1183 int pp_reg, lvds_reg;
1185 enum pipe panel_pipe = PIPE_A;
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1192 pp_reg = PP_CONTROL;
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1309 if ((val & DP_PORT_EN) == 0)
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1327 if ((val & PORT_ENABLE) == 0)
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1343 if ((val & LVDS_PORT_EN) == 0)
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1431 * Note! This is for pre-ILK only.
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1460 udelay(150); /* wait for warmup */
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1470 * Note! This is for pre-ILK only.
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1495 unsigned long flags;
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1504 I915_WRITE(SBI_ADDR,
1506 I915_WRITE(SBI_DATA,
1508 I915_WRITE(SBI_CTL_STAT,
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1525 unsigned long flags;
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1535 I915_WRITE(SBI_ADDR,
1537 I915_WRITE(SBI_CTL_STAT,
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1547 value = I915_READ(SBI_DATA);
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1575 if (WARN_ON(pll->refcount == 0))
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1614 if (WARN_ON(pll->refcount == 0))
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1688 val |= TRANS_INTERLACED;
1690 val |= TRANS_PROGRESSIVE;
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728 * @pipe should be %PIPE_A or %PIPE_B.
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1752 /* FIXME: assert CPU port conditions for SNB+ */
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 * @pipe should be %PIPE_A or %PIPE_B.
1774 * Will wait until the pipe has shut down before returning.
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1786 assert_planes_disabled(dev_priv, pipe);
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1845 * Disable @plane; should be an independent operation.
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1932 alignment = 64 * 1024;
1935 /* pin() will align the object as required by fence */
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1949 goto err_interruptible;
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1956 ret = i915_gem_object_get_fence(obj);
1960 i915_gem_object_pin_fence(obj);
1962 dev_priv->mm.interruptible = true;
1966 i915_gem_object_unpin(obj);
1968 dev_priv->mm.interruptible = true;
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1984 int tile_rows, tiles;
1988 tiles = *x / (512/bpp);
1991 return tile_rows * pitch * 8 + tiles * 4096;
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2025 dspcntr |= DISPPLANE_8BPP;
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2031 dspcntr |= DISPPLANE_16BPP;
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2045 dspcntr &= ~DISPPLANE_TILED;
2048 I915_WRITE(reg, dspcntr);
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2057 linear_offset -= intel_crtc->dspaddr_offset;
2059 intel_crtc->dspaddr_offset = linear_offset;
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2109 dspcntr |= DISPPLANE_8BPP;
2112 if (fb->depth != 16)
2115 dspcntr |= DISPPLANE_16BPP;
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2134 dspcntr &= ~DISPPLANE_TILED;
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2139 I915_WRITE(reg, dspcntr);
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2146 linear_offset -= intel_crtc->dspaddr_offset;
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 DRM_ERROR("No FB bound\n");
2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221 dev_priv->num_pipe);
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2236 intel_finish_fb(old_fb);
2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2251 intel_update_fbc(dev);
2252 mutex_unlock(&dev->struct_mutex);
2254 if (!dev->primary->master)
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2261 if (intel_crtc->pipe) {
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2282 if (clock < 200000) {
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2291 temp = I915_READ(0x4600c);
2293 I915_WRITE(0x4600c, temp | 0x8124);
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2303 I915_WRITE(DP_A, dpa_ctl);
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 if (IS_IVYBRIDGE(dev)) {
2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2327 I915_WRITE(reg, temp);
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2340 /* wait one idle pattern time */
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2411 reg = FDI_RX_IIR(pipe);
2412 for (tries = 0; tries < 5; tries++) {
2413 temp = I915_READ(reg);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2423 DRM_ERROR("FDI train 1 fail!\n");
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 I915_WRITE(reg, temp);
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2441 reg = FDI_RX_IIR(pipe);
2442 for (tries = 0; tries < 5; tries++) {
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 DRM_ERROR("FDI train 2 fail!\n");
2455 DRM_DEBUG_KMS("FDI train done\n");
2459 static const int snb_b_fdi_train_param[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 u32 reg, temp, i, retry;
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
2481 I915_WRITE(reg, temp);
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2515 for (i = 0; i < 4; i++) {
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
2520 I915_WRITE(reg, temp);
2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2540 DRM_ERROR("FDI train 1 fail!\n");
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2552 I915_WRITE(reg, temp);
2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2563 I915_WRITE(reg, temp);
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2593 DRM_ERROR("FDI train 2 fail!\n");
2595 DRM_DEBUG_KMS("FDI train done.\n");
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 temp |= FDI_COMPOSITE_SYNC;
2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 temp |= FDI_COMPOSITE_SYNC;
2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2666 DRM_ERROR("FDI train 1 fail!\n");
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2707 DRM_ERROR("FDI train 2 fail!\n");
2709 DRM_DEBUG_KMS("FDI train done.\n");
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2714 struct drm_device *dev = intel_crtc->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int pipe = intel_crtc->pipe;
2719 /* Write the TU size bits so error detection works */
2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734 /* Switch from Rawclk to PCDclk */
2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2780 /* Wait for the clocks to turn off. */
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2856 struct drm_device *dev = crtc->dev;
2858 if (crtc->fb == NULL)
2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2868 struct drm_device *dev = crtc->dev;
2869 struct intel_encoder *intel_encoder;
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888 intel_encoder->type);
2893 switch (intel_encoder->type) {
2894 case INTEL_OUTPUT_EDP:
2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2989 /* Wait for initialization time */
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2996 * Enable PCH resources required for PCH ports:
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
3011 assert_transcoder_disabled(dev_priv, pipe);
3013 /* For PCH output, training FDI link */
3014 dev_priv->display.fdi_link_train(crtc);
3016 intel_enable_pch_pll(intel_crtc);
3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
3024 temp = I915_READ(PCH_DPLL_SEL);
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3044 I915_WRITE(PCH_DPLL_SEL, temp);
3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069 TRANS_DP_SYNC_MASK |
3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
3073 temp |= bpc << 9; /* same format but at 11:9 */
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3080 switch (intel_trans_dp_port_sel(crtc)) {
3082 temp |= TRANS_DP_PORT_SEL_B;
3085 temp |= TRANS_DP_PORT_SEL_C;
3088 temp |= TRANS_DP_PORT_SEL_D;
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092 temp |= TRANS_DP_PORT_SEL_B;
3096 I915_WRITE(reg, temp);
3099 intel_enable_transcoder(dev_priv, pipe);
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3115 intel_crtc->pch_pll = NULL;
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3124 pll = intel_crtc->pch_pll;
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3172 intel_crtc->pch_pll = pll;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180 POSTING_READ(pll->pll_reg);
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3195 temp = I915_READ(dslreg);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 struct intel_encoder *encoder;
3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3218 WARN_ON(!crtc->enabled);
3220 /* XXX: For compatability with the crtc helper code, call the encoder's
3221 * enable function unconditionally for now. */
3222 if (intel_crtc->active)
3225 intel_crtc->active = true;
3226 intel_update_watermarks(dev);
3228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3229 temp = I915_READ(PCH_LVDS);
3230 if ((temp & LVDS_PORT_EN) == 0)
3231 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3234 is_pch_port = intel_crtc_driving_pch(crtc);
3237 ironlake_fdi_pll_enable(intel_crtc);
3239 ironlake_fdi_disable(crtc);
3241 /* Enable panel fitting for LVDS */
3242 if (dev_priv->pch_pf_size &&
3243 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3248 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3249 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3250 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3254 * On ILK+ LUT must be loaded before the pipe is running but with
3257 intel_crtc_load_lut(crtc);
3259 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3260 intel_enable_plane(dev_priv, plane, pipe);
3263 ironlake_pch_enable(crtc);
3265 mutex_lock(&dev->struct_mutex);
3266 intel_update_fbc(dev);
3267 mutex_unlock(&dev->struct_mutex);
3269 intel_crtc_update_cursor(crtc, true);
3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->enable(encoder);
3275 if (HAS_PCH_CPT(dev))
3276 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3279 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 struct intel_encoder *encoder;
3285 int pipe = intel_crtc->pipe;
3286 int plane = intel_crtc->plane;
3289 /* XXX: For compatability with the crtc helper code, call the encoder's
3290 * disable function unconditionally for now. */
3291 for_each_encoder_on_crtc(dev, crtc, encoder)
3292 encoder->disable(encoder);
3294 if (!intel_crtc->active)
3297 intel_crtc_wait_for_pending_flips(crtc);
3298 drm_vblank_off(dev, pipe);
3299 intel_crtc_update_cursor(crtc, false);
3301 intel_disable_plane(dev_priv, plane, pipe);
3303 if (dev_priv->cfb_plane == plane)
3304 intel_disable_fbc(dev);
3306 intel_disable_pipe(dev_priv, pipe);
3309 I915_WRITE(PF_CTL(pipe), 0);
3310 I915_WRITE(PF_WIN_SZ(pipe), 0);
3312 ironlake_fdi_disable(crtc);
3314 /* This is a horrible layering violation; we should be doing this in
3315 * the connector/encoder ->prepare instead, but we don't always have
3316 * enough information there about the config to know whether it will
3317 * actually be necessary or just cause undesired flicker.
3319 intel_disable_pch_ports(dev_priv, pipe);
3321 intel_disable_transcoder(dev_priv, pipe);
3323 if (HAS_PCH_CPT(dev)) {
3324 /* disable TRANS_DP_CTL */
3325 reg = TRANS_DP_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3328 temp |= TRANS_DP_PORT_SEL_NONE;
3329 I915_WRITE(reg, temp);
3331 /* disable DPLL_SEL */
3332 temp = I915_READ(PCH_DPLL_SEL);
3335 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3338 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3341 /* C shares PLL A or B */
3342 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3347 I915_WRITE(PCH_DPLL_SEL, temp);
3350 /* disable PCH DPLL */
3351 intel_disable_pch_pll(intel_crtc);
3353 ironlake_fdi_pll_disable(intel_crtc);
3355 intel_crtc->active = false;
3356 intel_update_watermarks(dev);
3358 mutex_lock(&dev->struct_mutex);
3359 intel_update_fbc(dev);
3360 mutex_unlock(&dev->struct_mutex);
3363 static void ironlake_crtc_off(struct drm_crtc *crtc)
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 intel_put_pch_pll(intel_crtc);
3369 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3371 if (!enable && intel_crtc->overlay) {
3372 struct drm_device *dev = intel_crtc->base.dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3375 mutex_lock(&dev->struct_mutex);
3376 dev_priv->mm.interruptible = false;
3377 (void) intel_overlay_switch_off(intel_crtc->overlay);
3378 dev_priv->mm.interruptible = true;
3379 mutex_unlock(&dev->struct_mutex);
3382 /* Let userspace switch the overlay on again. In most cases userspace
3383 * has to recompute where to put it anyway.
3387 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3389 struct drm_device *dev = crtc->dev;
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 struct intel_encoder *encoder;
3393 int pipe = intel_crtc->pipe;
3394 int plane = intel_crtc->plane;
3396 WARN_ON(!crtc->enabled);
3398 /* XXX: For compatability with the crtc helper code, call the encoder's
3399 * enable function unconditionally for now. */
3400 if (intel_crtc->active)
3403 intel_crtc->active = true;
3404 intel_update_watermarks(dev);
3406 intel_enable_pll(dev_priv, pipe);
3407 intel_enable_pipe(dev_priv, pipe, false);
3408 intel_enable_plane(dev_priv, plane, pipe);
3410 intel_crtc_load_lut(crtc);
3411 intel_update_fbc(dev);
3413 /* Give the overlay scaler a chance to enable if it's on this pipe */
3414 intel_crtc_dpms_overlay(intel_crtc, true);
3415 intel_crtc_update_cursor(crtc, true);
3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 encoder->enable(encoder);
3422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427 struct intel_encoder *encoder;
3428 int pipe = intel_crtc->pipe;
3429 int plane = intel_crtc->plane;
3431 /* XXX: For compatability with the crtc helper code, call the encoder's
3432 * disable function unconditionally for now. */
3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
3436 if (!intel_crtc->active)
3439 /* Give the overlay scaler a chance to disable if it's on this pipe */
3440 intel_crtc_wait_for_pending_flips(crtc);
3441 drm_vblank_off(dev, pipe);
3442 intel_crtc_dpms_overlay(intel_crtc, false);
3443 intel_crtc_update_cursor(crtc, false);
3445 if (dev_priv->cfb_plane == plane)
3446 intel_disable_fbc(dev);
3448 intel_disable_plane(dev_priv, plane, pipe);
3449 intel_disable_pipe(dev_priv, pipe);
3450 intel_disable_pll(dev_priv, pipe);
3452 intel_crtc->active = false;
3453 intel_update_fbc(dev);
3454 intel_update_watermarks(dev);
3457 static void i9xx_crtc_off(struct drm_crtc *crtc)
3462 * Sets the power management mode of the pipe and plane.
3464 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct drm_i915_master_private *master_priv;
3469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3470 struct intel_encoder *intel_encoder;
3471 int pipe = intel_crtc->pipe;
3472 bool enabled, enable = false;
3475 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3476 enable |= intel_encoder->connectors_active;
3478 mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
3480 if (intel_crtc->dpms_mode == mode)
3483 intel_crtc->dpms_mode = mode;
3486 dev_priv->display.crtc_enable(crtc);
3488 dev_priv->display.crtc_disable(crtc);
3490 if (!dev->primary->master)
3493 master_priv = dev->primary->master->driver_priv;
3494 if (!master_priv->sarea_priv)
3497 enabled = crtc->enabled && enable;
3501 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3505 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3506 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3509 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3514 static void intel_crtc_disable(struct drm_crtc *crtc)
3516 struct drm_device *dev = crtc->dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3519 /* crtc->disable is only called when we have no encoders, hence this
3520 * will disable the pipe. */
3521 intel_crtc_update_dpms(crtc);
3522 dev_priv->display.off(crtc);
3524 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3525 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3528 mutex_lock(&dev->struct_mutex);
3529 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3530 mutex_unlock(&dev->struct_mutex);
3534 void intel_encoder_disable(struct drm_encoder *encoder)
3536 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3538 intel_encoder->disable(intel_encoder);
3541 void intel_encoder_destroy(struct drm_encoder *encoder)
3543 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3545 drm_encoder_cleanup(encoder);
3546 kfree(intel_encoder);
3549 /* Simple dpms helper for encodres with just one connector, no cloning and only
3550 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3551 * state of the entire output pipe. */
3552 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3554 if (mode == DRM_MODE_DPMS_ON) {
3555 encoder->connectors_active = true;
3557 intel_crtc_update_dpms(encoder->base.crtc);
3559 encoder->connectors_active = false;
3561 intel_crtc_update_dpms(encoder->base.crtc);
3565 /* Cross check the actual hw state with our own modeset state tracking (and it's
3566 * internal consistency). */
3567 void intel_connector_check_state(struct intel_connector *connector)
3569 if (connector->get_hw_state(connector)) {
3570 struct intel_encoder *encoder = connector->encoder;
3571 struct drm_crtc *crtc;
3572 bool encoder_enabled;
3575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3576 connector->base.base.id,
3577 drm_get_connector_name(&connector->base));
3579 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3580 "wrong connector dpms state\n");
3581 WARN(connector->base.encoder != &encoder->base,
3582 "active connector not linked to encoder\n");
3583 WARN(!encoder->connectors_active,
3584 "encoder->connectors_active not set\n");
3586 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3587 WARN(!encoder_enabled, "encoder not enabled\n");
3588 if (WARN_ON(!encoder->base.crtc))
3591 crtc = encoder->base.crtc;
3593 WARN(!crtc->enabled, "crtc not enabled\n");
3594 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3595 WARN(pipe != to_intel_crtc(crtc)->pipe,
3596 "encoder active on the wrong pipe\n");
3600 /* Even simpler default implementation, if there's really no special case to
3602 void intel_connector_dpms(struct drm_connector *connector, int mode)
3604 struct intel_encoder *encoder = intel_attached_encoder(connector);
3606 /* All the simple cases only support two dpms states. */
3607 if (mode != DRM_MODE_DPMS_ON)
3608 mode = DRM_MODE_DPMS_OFF;
3610 if (mode == connector->dpms)
3613 connector->dpms = mode;
3615 /* Only need to change hw state when actually enabled */
3616 if (encoder->base.crtc)
3617 intel_encoder_dpms(encoder, mode);
3619 encoder->connectors_active = false;
3621 intel_connector_check_state(to_intel_connector(connector));
3624 /* Simple connector->get_hw_state implementation for encoders that support only
3625 * one connector and no cloning and hence the encoder state determines the state
3626 * of the connector. */
3627 bool intel_connector_get_hw_state(struct intel_connector *connector)
3630 struct intel_encoder *encoder = connector->encoder;
3632 return encoder->get_hw_state(encoder, &pipe);
3635 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3636 const struct drm_display_mode *mode,
3637 struct drm_display_mode *adjusted_mode)
3639 struct drm_device *dev = crtc->dev;
3641 if (HAS_PCH_SPLIT(dev)) {
3642 /* FDI link clock is fixed at 2.7G */
3643 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3647 /* All interlaced capable intel hw wants timings in frames. Note though
3648 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3649 * timings, so we need to be careful not to clobber these.*/
3650 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3651 drm_mode_set_crtcinfo(adjusted_mode, 0);
3656 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3658 return 400000; /* FIXME */
3661 static int i945_get_display_clock_speed(struct drm_device *dev)
3666 static int i915_get_display_clock_speed(struct drm_device *dev)
3671 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3676 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3680 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3682 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3685 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3686 case GC_DISPLAY_CLOCK_333_MHZ:
3689 case GC_DISPLAY_CLOCK_190_200_MHZ:
3695 static int i865_get_display_clock_speed(struct drm_device *dev)
3700 static int i855_get_display_clock_speed(struct drm_device *dev)
3703 /* Assume that the hardware is in the high speed state. This
3704 * should be the default.
3706 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3707 case GC_CLOCK_133_200:
3708 case GC_CLOCK_100_200:
3710 case GC_CLOCK_166_250:
3712 case GC_CLOCK_100_133:
3716 /* Shouldn't happen */
3720 static int i830_get_display_clock_speed(struct drm_device *dev)
3734 fdi_reduce_ratio(u32 *num, u32 *den)
3736 while (*num > 0xffffff || *den > 0xffffff) {
3743 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3744 int link_clock, struct fdi_m_n *m_n)
3746 m_n->tu = 64; /* default size */
3748 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3749 m_n->gmch_m = bits_per_pixel * pixel_clock;
3750 m_n->gmch_n = link_clock * nlanes * 8;
3751 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3753 m_n->link_m = pixel_clock;
3754 m_n->link_n = link_clock;
3755 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3758 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3760 if (i915_panel_use_ssc >= 0)
3761 return i915_panel_use_ssc != 0;
3762 return dev_priv->lvds_use_ssc
3763 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3767 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3768 * @crtc: CRTC structure
3769 * @mode: requested mode
3771 * A pipe may be connected to one or more outputs. Based on the depth of the
3772 * attached framebuffer, choose a good color depth to use on the pipe.
3774 * If possible, match the pipe depth to the fb depth. In some cases, this
3775 * isn't ideal, because the connected output supports a lesser or restricted
3776 * set of depths. Resolve that here:
3777 * LVDS typically supports only 6bpc, so clamp down in that case
3778 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3779 * Displays may support a restricted set as well, check EDID and clamp as
3781 * DP may want to dither down to 6bpc to fit larger modes
3784 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3785 * true if they don't match).
3787 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3788 unsigned int *pipe_bpp,
3789 struct drm_display_mode *mode)
3791 struct drm_device *dev = crtc->dev;
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3793 struct drm_connector *connector;
3794 struct intel_encoder *intel_encoder;
3795 unsigned int display_bpc = UINT_MAX, bpc;
3797 /* Walk the encoders & connectors on this crtc, get min bpc */
3798 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3800 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3801 unsigned int lvds_bpc;
3803 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3809 if (lvds_bpc < display_bpc) {
3810 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3811 display_bpc = lvds_bpc;
3816 /* Not one of the known troublemakers, check the EDID */
3817 list_for_each_entry(connector, &dev->mode_config.connector_list,
3819 if (connector->encoder != &intel_encoder->base)
3822 /* Don't use an invalid EDID bpc value */
3823 if (connector->display_info.bpc &&
3824 connector->display_info.bpc < display_bpc) {
3825 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3826 display_bpc = connector->display_info.bpc;
3831 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3832 * through, clamp it down. (Note: >12bpc will be caught below.)
3834 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3835 if (display_bpc > 8 && display_bpc < 12) {
3836 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3839 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3845 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3846 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3851 * We could just drive the pipe at the highest bpc all the time and
3852 * enable dithering as needed, but that costs bandwidth. So choose
3853 * the minimum value that expresses the full color range of the fb but
3854 * also stays within the max display bpc discovered above.
3857 switch (crtc->fb->depth) {
3859 bpc = 8; /* since we go through a colormap */
3863 bpc = 6; /* min is 18bpp */
3875 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3876 bpc = min((unsigned int)8, display_bpc);
3880 display_bpc = min(display_bpc, bpc);
3882 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3885 *pipe_bpp = display_bpc * 3;
3887 return display_bpc != bpc;
3890 static int vlv_get_refclk(struct drm_crtc *crtc)
3892 struct drm_device *dev = crtc->dev;
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 int refclk = 27000; /* for DP & HDMI */
3896 return 100000; /* only one validated so far */
3898 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3900 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3901 if (intel_panel_use_ssc(dev_priv))
3905 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3912 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3914 struct drm_device *dev = crtc->dev;
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3918 if (IS_VALLEYVIEW(dev)) {
3919 refclk = vlv_get_refclk(crtc);
3920 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3921 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3922 refclk = dev_priv->lvds_ssc_freq * 1000;
3923 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3925 } else if (!IS_GEN2(dev)) {
3934 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3935 intel_clock_t *clock)
3937 /* SDVO TV has fixed PLL values depend on its clock range,
3938 this mirrors vbios setting. */
3939 if (adjusted_mode->clock >= 100000
3940 && adjusted_mode->clock < 140500) {
3946 } else if (adjusted_mode->clock >= 140500
3947 && adjusted_mode->clock <= 200000) {
3956 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3957 intel_clock_t *clock,
3958 intel_clock_t *reduced_clock)
3960 struct drm_device *dev = crtc->dev;
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963 int pipe = intel_crtc->pipe;
3966 if (IS_PINEVIEW(dev)) {
3967 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3969 fp2 = (1 << reduced_clock->n) << 16 |
3970 reduced_clock->m1 << 8 | reduced_clock->m2;
3972 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3974 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3978 I915_WRITE(FP0(pipe), fp);
3980 intel_crtc->lowfreq_avail = false;
3981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3982 reduced_clock && i915_powersave) {
3983 I915_WRITE(FP1(pipe), fp2);
3984 intel_crtc->lowfreq_avail = true;
3986 I915_WRITE(FP1(pipe), fp);
3990 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3991 struct drm_display_mode *adjusted_mode)
3993 struct drm_device *dev = crtc->dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3996 int pipe = intel_crtc->pipe;
3999 temp = I915_READ(LVDS);
4000 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4002 temp |= LVDS_PIPEB_SELECT;
4004 temp &= ~LVDS_PIPEB_SELECT;
4006 /* set the corresponsding LVDS_BORDER bit */
4007 temp |= dev_priv->lvds_border_bits;
4008 /* Set the B0-B3 data pairs corresponding to whether we're going to
4009 * set the DPLLs for dual-channel mode or not.
4012 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4014 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4016 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4017 * appropriately here, but we need to look more thoroughly into how
4018 * panels behave in the two modes.
4020 /* set the dithering flag on LVDS as needed */
4021 if (INTEL_INFO(dev)->gen >= 4) {
4022 if (dev_priv->lvds_dither)
4023 temp |= LVDS_ENABLE_DITHER;
4025 temp &= ~LVDS_ENABLE_DITHER;
4027 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4028 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4029 temp |= LVDS_HSYNC_POLARITY;
4030 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4031 temp |= LVDS_VSYNC_POLARITY;
4032 I915_WRITE(LVDS, temp);
4035 static void vlv_update_pll(struct drm_crtc *crtc,
4036 struct drm_display_mode *mode,
4037 struct drm_display_mode *adjusted_mode,
4038 intel_clock_t *clock, intel_clock_t *reduced_clock,
4039 int refclk, int num_connectors)
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044 int pipe = intel_crtc->pipe;
4045 u32 dpll, mdiv, pdiv;
4046 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4049 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4057 /* Enable DPIO clock input */
4058 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4059 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4060 I915_WRITE(DPLL(pipe), dpll);
4061 POSTING_READ(DPLL(pipe));
4063 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4064 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4065 mdiv |= ((bestn << DPIO_N_SHIFT));
4066 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4067 mdiv |= (1 << DPIO_K_SHIFT);
4068 mdiv |= DPIO_ENABLE_CALIBRATION;
4069 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4071 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4073 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4074 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4075 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4076 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4078 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4080 dpll |= DPLL_VCO_ENABLE;
4081 I915_WRITE(DPLL(pipe), dpll);
4082 POSTING_READ(DPLL(pipe));
4083 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4084 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4087 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4090 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4094 I915_WRITE(DPLL_MD(pipe), temp);
4095 POSTING_READ(DPLL_MD(pipe));
4098 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4101 static void i9xx_update_pll(struct drm_crtc *crtc,
4102 struct drm_display_mode *mode,
4103 struct drm_display_mode *adjusted_mode,
4104 intel_clock_t *clock, intel_clock_t *reduced_clock,
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4110 int pipe = intel_crtc->pipe;
4114 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4115 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4117 dpll = DPLL_VGA_MODE_DIS;
4119 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4120 dpll |= DPLLB_MODE_LVDS;
4122 dpll |= DPLLB_MODE_DAC_SERIAL;
4124 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4125 if (pixel_multiplier > 1) {
4126 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4127 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4129 dpll |= DPLL_DVO_HIGH_SPEED;
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4132 dpll |= DPLL_DVO_HIGH_SPEED;
4134 /* compute bitmask from p1 value */
4135 if (IS_PINEVIEW(dev))
4136 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4138 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4139 if (IS_G4X(dev) && reduced_clock)
4140 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4142 switch (clock->p2) {
4144 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4147 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4150 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4153 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4156 if (INTEL_INFO(dev)->gen >= 4)
4157 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4159 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4160 dpll |= PLL_REF_INPUT_TVCLKINBC;
4161 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4162 /* XXX: just matching BIOS for now */
4163 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4165 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4166 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4167 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4169 dpll |= PLL_REF_INPUT_DREFCLK;
4171 dpll |= DPLL_VCO_ENABLE;
4172 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4173 POSTING_READ(DPLL(pipe));
4176 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4177 * This is an exception to the general rule that mode_set doesn't turn
4180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4181 intel_update_lvds(crtc, clock, adjusted_mode);
4183 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4184 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4186 I915_WRITE(DPLL(pipe), dpll);
4188 /* Wait for the clocks to stabilize. */
4189 POSTING_READ(DPLL(pipe));
4192 if (INTEL_INFO(dev)->gen >= 4) {
4195 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4197 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4201 I915_WRITE(DPLL_MD(pipe), temp);
4203 /* The pixel multiplier can only be updated once the
4204 * DPLL is enabled and the clocks are stable.
4206 * So write it again.
4208 I915_WRITE(DPLL(pipe), dpll);
4212 static void i8xx_update_pll(struct drm_crtc *crtc,
4213 struct drm_display_mode *adjusted_mode,
4214 intel_clock_t *clock,
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4223 dpll = DPLL_VGA_MODE_DIS;
4225 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4229 dpll |= PLL_P1_DIVIDE_BY_TWO;
4231 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4233 dpll |= PLL_P2_DIVIDE_BY_4;
4236 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4237 /* XXX: just matching BIOS for now */
4238 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4240 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4241 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4242 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4244 dpll |= PLL_REF_INPUT_DREFCLK;
4246 dpll |= DPLL_VCO_ENABLE;
4247 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4248 POSTING_READ(DPLL(pipe));
4251 I915_WRITE(DPLL(pipe), dpll);
4253 /* Wait for the clocks to stabilize. */
4254 POSTING_READ(DPLL(pipe));
4257 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4258 * This is an exception to the general rule that mode_set doesn't turn
4261 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4262 intel_update_lvds(crtc, clock, adjusted_mode);
4264 /* The pixel multiplier can only be updated once the
4265 * DPLL is enabled and the clocks are stable.
4267 * So write it again.
4269 I915_WRITE(DPLL(pipe), dpll);
4272 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4273 struct drm_display_mode *mode,
4274 struct drm_display_mode *adjusted_mode,
4276 struct drm_framebuffer *old_fb)
4278 struct drm_device *dev = crtc->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4281 int pipe = intel_crtc->pipe;
4282 int plane = intel_crtc->plane;
4283 int refclk, num_connectors = 0;
4284 intel_clock_t clock, reduced_clock;
4285 u32 dspcntr, pipeconf, vsyncshift;
4286 bool ok, has_reduced_clock = false, is_sdvo = false;
4287 bool is_lvds = false, is_tv = false, is_dp = false;
4288 struct intel_encoder *encoder;
4289 const intel_limit_t *limit;
4292 for_each_encoder_on_crtc(dev, crtc, encoder) {
4293 switch (encoder->type) {
4294 case INTEL_OUTPUT_LVDS:
4297 case INTEL_OUTPUT_SDVO:
4298 case INTEL_OUTPUT_HDMI:
4300 if (encoder->needs_tv_clock)
4303 case INTEL_OUTPUT_TVOUT:
4306 case INTEL_OUTPUT_DISPLAYPORT:
4314 refclk = i9xx_get_refclk(crtc, num_connectors);
4317 * Returns a set of divisors for the desired target clock with the given
4318 * refclk, or FALSE. The returned values represent the clock equation:
4319 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4321 limit = intel_limit(crtc, refclk);
4322 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4325 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4329 /* Ensure that the cursor is valid for the new mode before changing... */
4330 intel_crtc_update_cursor(crtc, true);
4332 if (is_lvds && dev_priv->lvds_downclock_avail) {
4334 * Ensure we match the reduced clock's P to the target clock.
4335 * If the clocks don't match, we can't switch the display clock
4336 * by using the FP0/FP1. In such case we will disable the LVDS
4337 * downclock feature.
4339 has_reduced_clock = limit->find_pll(limit, crtc,
4340 dev_priv->lvds_downclock,
4346 if (is_sdvo && is_tv)
4347 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4349 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4350 &reduced_clock : NULL);
4353 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4354 else if (IS_VALLEYVIEW(dev))
4355 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4356 refclk, num_connectors);
4358 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4359 has_reduced_clock ? &reduced_clock : NULL,
4362 /* setup pipeconf */
4363 pipeconf = I915_READ(PIPECONF(pipe));
4365 /* Set up the display plane register */
4366 dspcntr = DISPPLANE_GAMMA_ENABLE;
4369 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4371 dspcntr |= DISPPLANE_SEL_PIPE_B;
4373 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4374 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4377 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4381 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4382 pipeconf |= PIPECONF_DOUBLE_WIDE;
4384 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4387 /* default to 8bpc */
4388 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4390 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4391 pipeconf |= PIPECONF_BPP_6 |
4392 PIPECONF_DITHER_EN |
4393 PIPECONF_DITHER_TYPE_SP;
4397 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4398 drm_mode_debug_printmodeline(mode);
4400 if (HAS_PIPE_CXSR(dev)) {
4401 if (intel_crtc->lowfreq_avail) {
4402 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4403 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4405 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4406 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4410 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4411 if (!IS_GEN2(dev) &&
4412 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4413 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4414 /* the chip adds 2 halflines automatically */
4415 adjusted_mode->crtc_vtotal -= 1;
4416 adjusted_mode->crtc_vblank_end -= 1;
4417 vsyncshift = adjusted_mode->crtc_hsync_start
4418 - adjusted_mode->crtc_htotal/2;
4420 pipeconf |= PIPECONF_PROGRESSIVE;
4425 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4427 I915_WRITE(HTOTAL(pipe),
4428 (adjusted_mode->crtc_hdisplay - 1) |
4429 ((adjusted_mode->crtc_htotal - 1) << 16));
4430 I915_WRITE(HBLANK(pipe),
4431 (adjusted_mode->crtc_hblank_start - 1) |
4432 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4433 I915_WRITE(HSYNC(pipe),
4434 (adjusted_mode->crtc_hsync_start - 1) |
4435 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4437 I915_WRITE(VTOTAL(pipe),
4438 (adjusted_mode->crtc_vdisplay - 1) |
4439 ((adjusted_mode->crtc_vtotal - 1) << 16));
4440 I915_WRITE(VBLANK(pipe),
4441 (adjusted_mode->crtc_vblank_start - 1) |
4442 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4443 I915_WRITE(VSYNC(pipe),
4444 (adjusted_mode->crtc_vsync_start - 1) |
4445 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4447 /* pipesrc and dspsize control the size that is scaled from,
4448 * which should always be the user's requested size.
4450 I915_WRITE(DSPSIZE(plane),
4451 ((mode->vdisplay - 1) << 16) |
4452 (mode->hdisplay - 1));
4453 I915_WRITE(DSPPOS(plane), 0);
4454 I915_WRITE(PIPESRC(pipe),
4455 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4457 I915_WRITE(PIPECONF(pipe), pipeconf);
4458 POSTING_READ(PIPECONF(pipe));
4459 intel_enable_pipe(dev_priv, pipe, false);
4461 intel_wait_for_vblank(dev, pipe);
4463 I915_WRITE(DSPCNTR(plane), dspcntr);
4464 POSTING_READ(DSPCNTR(plane));
4466 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4468 intel_update_watermarks(dev);
4474 * Initialize reference clocks when the driver loads
4476 void ironlake_init_pch_refclk(struct drm_device *dev)
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479 struct drm_mode_config *mode_config = &dev->mode_config;
4480 struct intel_encoder *encoder;
4482 bool has_lvds = false;
4483 bool has_cpu_edp = false;
4484 bool has_pch_edp = false;
4485 bool has_panel = false;
4486 bool has_ck505 = false;
4487 bool can_ssc = false;
4489 /* We need to take the global config into account */
4490 list_for_each_entry(encoder, &mode_config->encoder_list,
4492 switch (encoder->type) {
4493 case INTEL_OUTPUT_LVDS:
4497 case INTEL_OUTPUT_EDP:
4499 if (intel_encoder_is_pch_edp(&encoder->base))
4507 if (HAS_PCH_IBX(dev)) {
4508 has_ck505 = dev_priv->display_clock_mode;
4509 can_ssc = has_ck505;
4515 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4516 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4519 /* Ironlake: try to setup display ref clock before DPLL
4520 * enabling. This is only under driver's control after
4521 * PCH B stepping, previous chipset stepping should be
4522 * ignoring this setting.
4524 temp = I915_READ(PCH_DREF_CONTROL);
4525 /* Always enable nonspread source */
4526 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4529 temp |= DREF_NONSPREAD_CK505_ENABLE;
4531 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4534 temp &= ~DREF_SSC_SOURCE_MASK;
4535 temp |= DREF_SSC_SOURCE_ENABLE;
4537 /* SSC must be turned on before enabling the CPU output */
4538 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4539 DRM_DEBUG_KMS("Using SSC on panel\n");
4540 temp |= DREF_SSC1_ENABLE;
4542 temp &= ~DREF_SSC1_ENABLE;
4544 /* Get SSC going before enabling the outputs */
4545 I915_WRITE(PCH_DREF_CONTROL, temp);
4546 POSTING_READ(PCH_DREF_CONTROL);
4549 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4551 /* Enable CPU source on CPU attached eDP */
4553 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4554 DRM_DEBUG_KMS("Using SSC on eDP\n");
4555 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4558 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4560 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4562 I915_WRITE(PCH_DREF_CONTROL, temp);
4563 POSTING_READ(PCH_DREF_CONTROL);
4566 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4568 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4570 /* Turn off CPU output */
4571 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4573 I915_WRITE(PCH_DREF_CONTROL, temp);
4574 POSTING_READ(PCH_DREF_CONTROL);
4577 /* Turn off the SSC source */
4578 temp &= ~DREF_SSC_SOURCE_MASK;
4579 temp |= DREF_SSC_SOURCE_DISABLE;
4582 temp &= ~ DREF_SSC1_ENABLE;
4584 I915_WRITE(PCH_DREF_CONTROL, temp);
4585 POSTING_READ(PCH_DREF_CONTROL);
4590 static int ironlake_get_refclk(struct drm_crtc *crtc)
4592 struct drm_device *dev = crtc->dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 struct intel_encoder *encoder;
4595 struct intel_encoder *edp_encoder = NULL;
4596 int num_connectors = 0;
4597 bool is_lvds = false;
4599 for_each_encoder_on_crtc(dev, crtc, encoder) {
4600 switch (encoder->type) {
4601 case INTEL_OUTPUT_LVDS:
4604 case INTEL_OUTPUT_EDP:
4605 edp_encoder = encoder;
4611 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4612 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4613 dev_priv->lvds_ssc_freq);
4614 return dev_priv->lvds_ssc_freq * 1000;
4620 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4621 struct drm_display_mode *mode,
4622 struct drm_display_mode *adjusted_mode,
4624 struct drm_framebuffer *old_fb)
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 int pipe = intel_crtc->pipe;
4630 int plane = intel_crtc->plane;
4631 int refclk, num_connectors = 0;
4632 intel_clock_t clock, reduced_clock;
4633 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4634 bool ok, has_reduced_clock = false, is_sdvo = false;
4635 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4636 struct intel_encoder *encoder, *edp_encoder = NULL;
4637 const intel_limit_t *limit;
4639 struct fdi_m_n m_n = {0};
4641 int target_clock, pixel_multiplier, lane, link_bw, factor;
4642 unsigned int pipe_bpp;
4644 bool is_cpu_edp = false, is_pch_edp = false;
4646 for_each_encoder_on_crtc(dev, crtc, encoder) {
4647 switch (encoder->type) {
4648 case INTEL_OUTPUT_LVDS:
4651 case INTEL_OUTPUT_SDVO:
4652 case INTEL_OUTPUT_HDMI:
4654 if (encoder->needs_tv_clock)
4657 case INTEL_OUTPUT_TVOUT:
4660 case INTEL_OUTPUT_ANALOG:
4663 case INTEL_OUTPUT_DISPLAYPORT:
4666 case INTEL_OUTPUT_EDP:
4668 if (intel_encoder_is_pch_edp(&encoder->base))
4672 edp_encoder = encoder;
4679 refclk = ironlake_get_refclk(crtc);
4682 * Returns a set of divisors for the desired target clock with the given
4683 * refclk, or FALSE. The returned values represent the clock equation:
4684 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4686 limit = intel_limit(crtc, refclk);
4687 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4690 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4694 /* Ensure that the cursor is valid for the new mode before changing... */
4695 intel_crtc_update_cursor(crtc, true);
4697 if (is_lvds && dev_priv->lvds_downclock_avail) {
4699 * Ensure we match the reduced clock's P to the target clock.
4700 * If the clocks don't match, we can't switch the display clock
4701 * by using the FP0/FP1. In such case we will disable the LVDS
4702 * downclock feature.
4704 has_reduced_clock = limit->find_pll(limit, crtc,
4705 dev_priv->lvds_downclock,
4711 if (is_sdvo && is_tv)
4712 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4716 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4718 /* CPU eDP doesn't require FDI link, so just set DP M/N
4719 according to current link config */
4721 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4723 /* FDI is a binary signal running at ~2.7GHz, encoding
4724 * each output octet as 10 bits. The actual frequency
4725 * is stored as a divider into a 100MHz clock, and the
4726 * mode pixel clock is stored in units of 1KHz.
4727 * Hence the bw of each lane in terms of the mode signal
4730 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4733 /* [e]DP over FDI requires target mode clock instead of link clock. */
4735 target_clock = intel_edp_target_clock(edp_encoder, mode);
4737 target_clock = mode->clock;
4739 target_clock = adjusted_mode->clock;
4741 /* determine panel color depth */
4742 temp = I915_READ(PIPECONF(pipe));
4743 temp &= ~PIPE_BPC_MASK;
4744 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4759 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4766 intel_crtc->bpp = pipe_bpp;
4767 I915_WRITE(PIPECONF(pipe), temp);
4771 * Account for spread spectrum to avoid
4772 * oversubscribing the link. Max center spread
4773 * is 2.5%; use 5% for safety's sake.
4775 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4776 lane = bps / (link_bw * 8) + 1;
4779 intel_crtc->fdi_lanes = lane;
4781 if (pixel_multiplier > 1)
4782 link_bw *= pixel_multiplier;
4783 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4786 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4787 if (has_reduced_clock)
4788 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4791 /* Enable autotuning of the PLL clock (if permissible) */
4794 if ((intel_panel_use_ssc(dev_priv) &&
4795 dev_priv->lvds_ssc_freq == 100) ||
4796 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4798 } else if (is_sdvo && is_tv)
4801 if (clock.m < factor * clock.n)
4807 dpll |= DPLLB_MODE_LVDS;
4809 dpll |= DPLLB_MODE_DAC_SERIAL;
4811 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4812 if (pixel_multiplier > 1) {
4813 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4815 dpll |= DPLL_DVO_HIGH_SPEED;
4817 if (is_dp && !is_cpu_edp)
4818 dpll |= DPLL_DVO_HIGH_SPEED;
4820 /* compute bitmask from p1 value */
4821 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4823 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4827 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4830 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4833 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4836 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4840 if (is_sdvo && is_tv)
4841 dpll |= PLL_REF_INPUT_TVCLKINBC;
4843 /* XXX: just matching BIOS for now */
4844 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4846 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4847 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4849 dpll |= PLL_REF_INPUT_DREFCLK;
4851 /* setup pipeconf */
4852 pipeconf = I915_READ(PIPECONF(pipe));
4854 /* Set up the display plane register */
4855 dspcntr = DISPPLANE_GAMMA_ENABLE;
4857 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4858 drm_mode_debug_printmodeline(mode);
4860 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4861 * pre-Haswell/LPT generation */
4862 if (HAS_PCH_LPT(dev)) {
4863 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4865 } else if (!is_cpu_edp) {
4866 struct intel_pch_pll *pll;
4868 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4870 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4875 intel_put_pch_pll(intel_crtc);
4877 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4878 * This is an exception to the general rule that mode_set doesn't turn
4882 temp = I915_READ(PCH_LVDS);
4883 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4884 if (HAS_PCH_CPT(dev)) {
4885 temp &= ~PORT_TRANS_SEL_MASK;
4886 temp |= PORT_TRANS_SEL_CPT(pipe);
4889 temp |= LVDS_PIPEB_SELECT;
4891 temp &= ~LVDS_PIPEB_SELECT;
4894 /* set the corresponsding LVDS_BORDER bit */
4895 temp |= dev_priv->lvds_border_bits;
4896 /* Set the B0-B3 data pairs corresponding to whether we're going to
4897 * set the DPLLs for dual-channel mode or not.
4900 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4902 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4904 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4905 * appropriately here, but we need to look more thoroughly into how
4906 * panels behave in the two modes.
4908 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4909 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4910 temp |= LVDS_HSYNC_POLARITY;
4911 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4912 temp |= LVDS_VSYNC_POLARITY;
4913 I915_WRITE(PCH_LVDS, temp);
4916 pipeconf &= ~PIPECONF_DITHER_EN;
4917 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4918 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4919 pipeconf |= PIPECONF_DITHER_EN;
4920 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4922 if (is_dp && !is_cpu_edp) {
4923 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4925 /* For non-DP output, clear any trans DP clock recovery setting.*/
4926 I915_WRITE(TRANSDATA_M1(pipe), 0);
4927 I915_WRITE(TRANSDATA_N1(pipe), 0);
4928 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4929 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4932 if (intel_crtc->pch_pll) {
4933 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4935 /* Wait for the clocks to stabilize. */
4936 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4939 /* The pixel multiplier can only be updated once the
4940 * DPLL is enabled and the clocks are stable.
4942 * So write it again.
4944 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4947 intel_crtc->lowfreq_avail = false;
4948 if (intel_crtc->pch_pll) {
4949 if (is_lvds && has_reduced_clock && i915_powersave) {
4950 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4951 intel_crtc->lowfreq_avail = true;
4953 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4957 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4958 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4959 pipeconf |= PIPECONF_INTERLACED_ILK;
4960 /* the chip adds 2 halflines automatically */
4961 adjusted_mode->crtc_vtotal -= 1;
4962 adjusted_mode->crtc_vblank_end -= 1;
4963 I915_WRITE(VSYNCSHIFT(pipe),
4964 adjusted_mode->crtc_hsync_start
4965 - adjusted_mode->crtc_htotal/2);
4967 pipeconf |= PIPECONF_PROGRESSIVE;
4968 I915_WRITE(VSYNCSHIFT(pipe), 0);
4971 I915_WRITE(HTOTAL(pipe),
4972 (adjusted_mode->crtc_hdisplay - 1) |
4973 ((adjusted_mode->crtc_htotal - 1) << 16));
4974 I915_WRITE(HBLANK(pipe),
4975 (adjusted_mode->crtc_hblank_start - 1) |
4976 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4977 I915_WRITE(HSYNC(pipe),
4978 (adjusted_mode->crtc_hsync_start - 1) |
4979 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4981 I915_WRITE(VTOTAL(pipe),
4982 (adjusted_mode->crtc_vdisplay - 1) |
4983 ((adjusted_mode->crtc_vtotal - 1) << 16));
4984 I915_WRITE(VBLANK(pipe),
4985 (adjusted_mode->crtc_vblank_start - 1) |
4986 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4987 I915_WRITE(VSYNC(pipe),
4988 (adjusted_mode->crtc_vsync_start - 1) |
4989 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4991 /* pipesrc controls the size that is scaled from, which should
4992 * always be the user's requested size.
4994 I915_WRITE(PIPESRC(pipe),
4995 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4997 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4998 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4999 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5000 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5003 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5005 I915_WRITE(PIPECONF(pipe), pipeconf);
5006 POSTING_READ(PIPECONF(pipe));
5008 intel_wait_for_vblank(dev, pipe);
5010 I915_WRITE(DSPCNTR(plane), dspcntr);
5011 POSTING_READ(DSPCNTR(plane));
5013 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5015 intel_update_watermarks(dev);
5017 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5022 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5023 struct drm_display_mode *mode,
5024 struct drm_display_mode *adjusted_mode,
5026 struct drm_framebuffer *old_fb)
5028 struct drm_device *dev = crtc->dev;
5029 struct drm_i915_private *dev_priv = dev->dev_private;
5030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5031 int pipe = intel_crtc->pipe;
5034 drm_vblank_pre_modeset(dev, pipe);
5036 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5038 drm_vblank_post_modeset(dev, pipe);
5041 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5043 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5048 static bool intel_eld_uptodate(struct drm_connector *connector,
5049 int reg_eldv, uint32_t bits_eldv,
5050 int reg_elda, uint32_t bits_elda,
5053 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5054 uint8_t *eld = connector->eld;
5057 i = I915_READ(reg_eldv);
5066 i = I915_READ(reg_elda);
5068 I915_WRITE(reg_elda, i);
5070 for (i = 0; i < eld[2]; i++)
5071 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5077 static void g4x_write_eld(struct drm_connector *connector,
5078 struct drm_crtc *crtc)
5080 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5081 uint8_t *eld = connector->eld;
5086 i = I915_READ(G4X_AUD_VID_DID);
5088 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5089 eldv = G4X_ELDV_DEVCL_DEVBLC;
5091 eldv = G4X_ELDV_DEVCTG;
5093 if (intel_eld_uptodate(connector,
5094 G4X_AUD_CNTL_ST, eldv,
5095 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5096 G4X_HDMIW_HDMIEDID))
5099 i = I915_READ(G4X_AUD_CNTL_ST);
5100 i &= ~(eldv | G4X_ELD_ADDR);
5101 len = (i >> 9) & 0x1f; /* ELD buffer size */
5102 I915_WRITE(G4X_AUD_CNTL_ST, i);
5107 len = min_t(uint8_t, eld[2], len);
5108 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5109 for (i = 0; i < len; i++)
5110 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5112 i = I915_READ(G4X_AUD_CNTL_ST);
5114 I915_WRITE(G4X_AUD_CNTL_ST, i);
5117 static void haswell_write_eld(struct drm_connector *connector,
5118 struct drm_crtc *crtc)
5120 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5121 uint8_t *eld = connector->eld;
5122 struct drm_device *dev = crtc->dev;
5126 int pipe = to_intel_crtc(crtc)->pipe;
5129 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5130 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5131 int aud_config = HSW_AUD_CFG(pipe);
5132 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5135 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5137 /* Audio output enable */
5138 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5139 tmp = I915_READ(aud_cntrl_st2);
5140 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5141 I915_WRITE(aud_cntrl_st2, tmp);
5143 /* Wait for 1 vertical blank */
5144 intel_wait_for_vblank(dev, pipe);
5146 /* Set ELD valid state */
5147 tmp = I915_READ(aud_cntrl_st2);
5148 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5149 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5150 I915_WRITE(aud_cntrl_st2, tmp);
5151 tmp = I915_READ(aud_cntrl_st2);
5152 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5154 /* Enable HDMI mode */
5155 tmp = I915_READ(aud_config);
5156 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5157 /* clear N_programing_enable and N_value_index */
5158 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5159 I915_WRITE(aud_config, tmp);
5161 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5163 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5166 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5167 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5168 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5170 I915_WRITE(aud_config, 0);
5172 if (intel_eld_uptodate(connector,
5173 aud_cntrl_st2, eldv,
5174 aud_cntl_st, IBX_ELD_ADDRESS,
5178 i = I915_READ(aud_cntrl_st2);
5180 I915_WRITE(aud_cntrl_st2, i);
5185 i = I915_READ(aud_cntl_st);
5186 i &= ~IBX_ELD_ADDRESS;
5187 I915_WRITE(aud_cntl_st, i);
5188 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5189 DRM_DEBUG_DRIVER("port num:%d\n", i);
5191 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5192 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5193 for (i = 0; i < len; i++)
5194 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5196 i = I915_READ(aud_cntrl_st2);
5198 I915_WRITE(aud_cntrl_st2, i);
5202 static void ironlake_write_eld(struct drm_connector *connector,
5203 struct drm_crtc *crtc)
5205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5206 uint8_t *eld = connector->eld;
5214 int pipe = to_intel_crtc(crtc)->pipe;
5216 if (HAS_PCH_IBX(connector->dev)) {
5217 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5218 aud_config = IBX_AUD_CFG(pipe);
5219 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5220 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5222 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5223 aud_config = CPT_AUD_CFG(pipe);
5224 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5225 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5230 i = I915_READ(aud_cntl_st);
5231 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5234 /* operate blindly on all ports */
5235 eldv = IBX_ELD_VALIDB;
5236 eldv |= IBX_ELD_VALIDB << 4;
5237 eldv |= IBX_ELD_VALIDB << 8;
5239 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5248 I915_WRITE(aud_config, 0);
5250 if (intel_eld_uptodate(connector,
5251 aud_cntrl_st2, eldv,
5252 aud_cntl_st, IBX_ELD_ADDRESS,
5256 i = I915_READ(aud_cntrl_st2);
5258 I915_WRITE(aud_cntrl_st2, i);
5263 i = I915_READ(aud_cntl_st);
5264 i &= ~IBX_ELD_ADDRESS;
5265 I915_WRITE(aud_cntl_st, i);
5267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5269 for (i = 0; i < len; i++)
5270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5272 i = I915_READ(aud_cntrl_st2);
5274 I915_WRITE(aud_cntrl_st2, i);
5277 void intel_write_eld(struct drm_encoder *encoder,
5278 struct drm_display_mode *mode)
5280 struct drm_crtc *crtc = encoder->crtc;
5281 struct drm_connector *connector;
5282 struct drm_device *dev = encoder->dev;
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5285 connector = drm_select_eld(encoder, mode);
5289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5291 drm_get_connector_name(connector),
5292 connector->encoder->base.id,
5293 drm_get_encoder_name(connector->encoder));
5295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5297 if (dev_priv->display.write_eld)
5298 dev_priv->display.write_eld(connector, crtc);
5301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5302 void intel_crtc_load_lut(struct drm_crtc *crtc)
5304 struct drm_device *dev = crtc->dev;
5305 struct drm_i915_private *dev_priv = dev->dev_private;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5307 int palreg = PALETTE(intel_crtc->pipe);
5310 /* The clocks have to be on to load the palette. */
5311 if (!crtc->enabled || !intel_crtc->active)
5314 /* use legacy palette for Ironlake */
5315 if (HAS_PCH_SPLIT(dev))
5316 palreg = LGC_PALETTE(intel_crtc->pipe);
5318 for (i = 0; i < 256; i++) {
5319 I915_WRITE(palreg + 4 * i,
5320 (intel_crtc->lut_r[i] << 16) |
5321 (intel_crtc->lut_g[i] << 8) |
5322 intel_crtc->lut_b[i]);
5326 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5328 struct drm_device *dev = crtc->dev;
5329 struct drm_i915_private *dev_priv = dev->dev_private;
5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331 bool visible = base != 0;
5334 if (intel_crtc->cursor_visible == visible)
5337 cntl = I915_READ(_CURACNTR);
5339 /* On these chipsets we can only modify the base whilst
5340 * the cursor is disabled.
5342 I915_WRITE(_CURABASE, base);
5344 cntl &= ~(CURSOR_FORMAT_MASK);
5345 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5346 cntl |= CURSOR_ENABLE |
5347 CURSOR_GAMMA_ENABLE |
5350 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5351 I915_WRITE(_CURACNTR, cntl);
5353 intel_crtc->cursor_visible = visible;
5356 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5358 struct drm_device *dev = crtc->dev;
5359 struct drm_i915_private *dev_priv = dev->dev_private;
5360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5361 int pipe = intel_crtc->pipe;
5362 bool visible = base != 0;
5364 if (intel_crtc->cursor_visible != visible) {
5365 uint32_t cntl = I915_READ(CURCNTR(pipe));
5367 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5369 cntl |= pipe << 28; /* Connect to correct pipe */
5371 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5372 cntl |= CURSOR_MODE_DISABLE;
5374 I915_WRITE(CURCNTR(pipe), cntl);
5376 intel_crtc->cursor_visible = visible;
5378 /* and commit changes on next vblank */
5379 I915_WRITE(CURBASE(pipe), base);
5382 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5384 struct drm_device *dev = crtc->dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387 int pipe = intel_crtc->pipe;
5388 bool visible = base != 0;
5390 if (intel_crtc->cursor_visible != visible) {
5391 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5393 cntl &= ~CURSOR_MODE;
5394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5396 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5397 cntl |= CURSOR_MODE_DISABLE;
5399 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5401 intel_crtc->cursor_visible = visible;
5403 /* and commit changes on next vblank */
5404 I915_WRITE(CURBASE_IVB(pipe), base);
5407 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5408 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5411 struct drm_device *dev = crtc->dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414 int pipe = intel_crtc->pipe;
5415 int x = intel_crtc->cursor_x;
5416 int y = intel_crtc->cursor_y;
5422 if (on && crtc->enabled && crtc->fb) {
5423 base = intel_crtc->cursor_addr;
5424 if (x > (int) crtc->fb->width)
5427 if (y > (int) crtc->fb->height)
5433 if (x + intel_crtc->cursor_width < 0)
5436 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5439 pos |= x << CURSOR_X_SHIFT;
5442 if (y + intel_crtc->cursor_height < 0)
5445 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5448 pos |= y << CURSOR_Y_SHIFT;
5450 visible = base != 0;
5451 if (!visible && !intel_crtc->cursor_visible)
5454 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5455 I915_WRITE(CURPOS_IVB(pipe), pos);
5456 ivb_update_cursor(crtc, base);
5458 I915_WRITE(CURPOS(pipe), pos);
5459 if (IS_845G(dev) || IS_I865G(dev))
5460 i845_update_cursor(crtc, base);
5462 i9xx_update_cursor(crtc, base);
5466 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5467 struct drm_file *file,
5469 uint32_t width, uint32_t height)
5471 struct drm_device *dev = crtc->dev;
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5474 struct drm_i915_gem_object *obj;
5478 DRM_DEBUG_KMS("\n");
5480 /* if we want to turn off the cursor ignore width and height */
5482 DRM_DEBUG_KMS("cursor off\n");
5485 mutex_lock(&dev->struct_mutex);
5489 /* Currently we only support 64x64 cursors */
5490 if (width != 64 || height != 64) {
5491 DRM_ERROR("we currently only support 64x64 cursors\n");
5495 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5496 if (&obj->base == NULL)
5499 if (obj->base.size < width * height * 4) {
5500 DRM_ERROR("buffer is to small\n");
5505 /* we only need to pin inside GTT if cursor is non-phy */
5506 mutex_lock(&dev->struct_mutex);
5507 if (!dev_priv->info->cursor_needs_physical) {
5508 if (obj->tiling_mode) {
5509 DRM_ERROR("cursor cannot be tiled\n");
5514 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5516 DRM_ERROR("failed to move cursor bo into the GTT\n");
5520 ret = i915_gem_object_put_fence(obj);
5522 DRM_ERROR("failed to release fence for cursor");
5526 addr = obj->gtt_offset;
5528 int align = IS_I830(dev) ? 16 * 1024 : 256;
5529 ret = i915_gem_attach_phys_object(dev, obj,
5530 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5533 DRM_ERROR("failed to attach phys object\n");
5536 addr = obj->phys_obj->handle->busaddr;
5540 I915_WRITE(CURSIZE, (height << 12) | width);
5543 if (intel_crtc->cursor_bo) {
5544 if (dev_priv->info->cursor_needs_physical) {
5545 if (intel_crtc->cursor_bo != obj)
5546 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5548 i915_gem_object_unpin(intel_crtc->cursor_bo);
5549 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5552 mutex_unlock(&dev->struct_mutex);
5554 intel_crtc->cursor_addr = addr;
5555 intel_crtc->cursor_bo = obj;
5556 intel_crtc->cursor_width = width;
5557 intel_crtc->cursor_height = height;
5559 intel_crtc_update_cursor(crtc, true);
5563 i915_gem_object_unpin(obj);
5565 mutex_unlock(&dev->struct_mutex);
5567 drm_gem_object_unreference_unlocked(&obj->base);
5571 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575 intel_crtc->cursor_x = x;
5576 intel_crtc->cursor_y = y;
5578 intel_crtc_update_cursor(crtc, true);
5583 /** Sets the color ramps on behalf of RandR */
5584 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5585 u16 blue, int regno)
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589 intel_crtc->lut_r[regno] = red >> 8;
5590 intel_crtc->lut_g[regno] = green >> 8;
5591 intel_crtc->lut_b[regno] = blue >> 8;
5594 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5595 u16 *blue, int regno)
5597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5599 *red = intel_crtc->lut_r[regno] << 8;
5600 *green = intel_crtc->lut_g[regno] << 8;
5601 *blue = intel_crtc->lut_b[regno] << 8;
5604 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5605 u16 *blue, uint32_t start, uint32_t size)
5607 int end = (start + size > 256) ? 256 : start + size, i;
5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5610 for (i = start; i < end; i++) {
5611 intel_crtc->lut_r[i] = red[i] >> 8;
5612 intel_crtc->lut_g[i] = green[i] >> 8;
5613 intel_crtc->lut_b[i] = blue[i] >> 8;
5616 intel_crtc_load_lut(crtc);
5620 * Get a pipe with a simple mode set on it for doing load-based monitor
5623 * It will be up to the load-detect code to adjust the pipe as appropriate for
5624 * its requirements. The pipe will be connected to no other encoders.
5626 * Currently this code will only succeed if there is a pipe with no encoders
5627 * configured for it. In the future, it could choose to temporarily disable
5628 * some outputs to free up a pipe for its use.
5630 * \return crtc, or NULL if no pipes are available.
5633 /* VESA 640x480x72Hz mode to set on the pipe */
5634 static struct drm_display_mode load_detect_mode = {
5635 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5636 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5639 static struct drm_framebuffer *
5640 intel_framebuffer_create(struct drm_device *dev,
5641 struct drm_mode_fb_cmd2 *mode_cmd,
5642 struct drm_i915_gem_object *obj)
5644 struct intel_framebuffer *intel_fb;
5647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5649 drm_gem_object_unreference_unlocked(&obj->base);
5650 return ERR_PTR(-ENOMEM);
5653 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5655 drm_gem_object_unreference_unlocked(&obj->base);
5657 return ERR_PTR(ret);
5660 return &intel_fb->base;
5664 intel_framebuffer_pitch_for_width(int width, int bpp)
5666 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5667 return ALIGN(pitch, 64);
5671 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5673 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5674 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5677 static struct drm_framebuffer *
5678 intel_framebuffer_create_for_mode(struct drm_device *dev,
5679 struct drm_display_mode *mode,
5682 struct drm_i915_gem_object *obj;
5683 struct drm_mode_fb_cmd2 mode_cmd;
5685 obj = i915_gem_alloc_object(dev,
5686 intel_framebuffer_size_for_mode(mode, bpp));
5688 return ERR_PTR(-ENOMEM);
5690 mode_cmd.width = mode->hdisplay;
5691 mode_cmd.height = mode->vdisplay;
5692 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5694 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5696 return intel_framebuffer_create(dev, &mode_cmd, obj);
5699 static struct drm_framebuffer *
5700 mode_fits_in_fbdev(struct drm_device *dev,
5701 struct drm_display_mode *mode)
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 struct drm_i915_gem_object *obj;
5705 struct drm_framebuffer *fb;
5707 if (dev_priv->fbdev == NULL)
5710 obj = dev_priv->fbdev->ifb.obj;
5714 fb = &dev_priv->fbdev->ifb.base;
5715 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5716 fb->bits_per_pixel))
5719 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5725 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5726 struct drm_display_mode *mode,
5727 struct intel_load_detect_pipe *old)
5729 struct intel_crtc *intel_crtc;
5730 struct intel_encoder *intel_encoder =
5731 intel_attached_encoder(connector);
5732 struct drm_crtc *possible_crtc;
5733 struct drm_encoder *encoder = &intel_encoder->base;
5734 struct drm_crtc *crtc = NULL;
5735 struct drm_device *dev = encoder->dev;
5736 struct drm_framebuffer *old_fb;
5739 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5740 connector->base.id, drm_get_connector_name(connector),
5741 encoder->base.id, drm_get_encoder_name(encoder));
5744 * Algorithm gets a little messy:
5746 * - if the connector already has an assigned crtc, use it (but make
5747 * sure it's on first)
5749 * - try to find the first unused crtc that can drive this connector,
5750 * and use that if we find one
5753 /* See if we already have a CRTC for this connector */
5754 if (encoder->crtc) {
5755 crtc = encoder->crtc;
5757 old->dpms_mode = connector->dpms;
5758 old->load_detect_temp = false;
5760 /* Make sure the crtc and connector are running */
5761 if (connector->dpms != DRM_MODE_DPMS_ON)
5762 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5767 /* Find an unused one (if possible) */
5768 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5770 if (!(encoder->possible_crtcs & (1 << i)))
5772 if (!possible_crtc->enabled) {
5773 crtc = possible_crtc;
5779 * If we didn't find an unused CRTC, don't use any.
5782 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5786 encoder->crtc = crtc;
5787 connector->encoder = encoder;
5789 intel_crtc = to_intel_crtc(crtc);
5790 old->dpms_mode = connector->dpms;
5791 old->load_detect_temp = true;
5792 old->release_fb = NULL;
5795 mode = &load_detect_mode;
5799 /* We need a framebuffer large enough to accommodate all accesses
5800 * that the plane may generate whilst we perform load detection.
5801 * We can not rely on the fbcon either being present (we get called
5802 * during its initialisation to detect all boot displays, or it may
5803 * not even exist) or that it is large enough to satisfy the
5806 crtc->fb = mode_fits_in_fbdev(dev, mode);
5807 if (crtc->fb == NULL) {
5808 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5809 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5810 old->release_fb = crtc->fb;
5812 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5813 if (IS_ERR(crtc->fb)) {
5814 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5818 if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
5819 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5820 if (old->release_fb)
5821 old->release_fb->funcs->destroy(old->release_fb);
5825 /* let the connector get through one full cycle before testing */
5826 intel_wait_for_vblank(dev, intel_crtc->pipe);
5830 connector->encoder = NULL;
5831 encoder->crtc = NULL;
5836 void intel_release_load_detect_pipe(struct drm_connector *connector,
5837 struct intel_load_detect_pipe *old)
5839 struct intel_encoder *intel_encoder =
5840 intel_attached_encoder(connector);
5841 struct drm_encoder *encoder = &intel_encoder->base;
5842 struct drm_device *dev = encoder->dev;
5844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5845 connector->base.id, drm_get_connector_name(connector),
5846 encoder->base.id, drm_get_encoder_name(encoder));
5848 if (old->load_detect_temp) {
5849 connector->encoder = NULL;
5850 encoder->crtc = NULL;
5851 drm_helper_disable_unused_functions(dev);
5853 if (old->release_fb)
5854 old->release_fb->funcs->destroy(old->release_fb);
5859 /* Switch crtc and encoder back off if necessary */
5860 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5861 connector->funcs->dpms(connector, old->dpms_mode);
5864 /* Returns the clock of the currently programmed mode of the given pipe. */
5865 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869 int pipe = intel_crtc->pipe;
5870 u32 dpll = I915_READ(DPLL(pipe));
5872 intel_clock_t clock;
5874 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5875 fp = I915_READ(FP0(pipe));
5877 fp = I915_READ(FP1(pipe));
5879 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5880 if (IS_PINEVIEW(dev)) {
5881 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5882 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5884 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5885 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5888 if (!IS_GEN2(dev)) {
5889 if (IS_PINEVIEW(dev))
5890 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5891 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5893 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5894 DPLL_FPA01_P1_POST_DIV_SHIFT);
5896 switch (dpll & DPLL_MODE_MASK) {
5897 case DPLLB_MODE_DAC_SERIAL:
5898 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5901 case DPLLB_MODE_LVDS:
5902 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5906 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5907 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5911 /* XXX: Handle the 100Mhz refclk */
5912 intel_clock(dev, 96000, &clock);
5914 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5917 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5918 DPLL_FPA01_P1_POST_DIV_SHIFT);
5921 if ((dpll & PLL_REF_INPUT_MASK) ==
5922 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5923 /* XXX: might not be 66MHz */
5924 intel_clock(dev, 66000, &clock);
5926 intel_clock(dev, 48000, &clock);
5928 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5931 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5932 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5934 if (dpll & PLL_P2_DIVIDE_BY_4)
5939 intel_clock(dev, 48000, &clock);
5943 /* XXX: It would be nice to validate the clocks, but we can't reuse
5944 * i830PllIsValid() because it relies on the xf86_config connector
5945 * configuration being accurate, which it isn't necessarily.
5951 /** Returns the currently programmed mode of the given pipe. */
5952 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5953 struct drm_crtc *crtc)
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 int pipe = intel_crtc->pipe;
5958 struct drm_display_mode *mode;
5959 int htot = I915_READ(HTOTAL(pipe));
5960 int hsync = I915_READ(HSYNC(pipe));
5961 int vtot = I915_READ(VTOTAL(pipe));
5962 int vsync = I915_READ(VSYNC(pipe));
5964 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5968 mode->clock = intel_crtc_clock_get(dev, crtc);
5969 mode->hdisplay = (htot & 0xffff) + 1;
5970 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5971 mode->hsync_start = (hsync & 0xffff) + 1;
5972 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5973 mode->vdisplay = (vtot & 0xffff) + 1;
5974 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5975 mode->vsync_start = (vsync & 0xffff) + 1;
5976 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5978 drm_mode_set_name(mode);
5983 static void intel_increase_pllclock(struct drm_crtc *crtc)
5985 struct drm_device *dev = crtc->dev;
5986 drm_i915_private_t *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
5989 int dpll_reg = DPLL(pipe);
5992 if (HAS_PCH_SPLIT(dev))
5995 if (!dev_priv->lvds_downclock_avail)
5998 dpll = I915_READ(dpll_reg);
5999 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6000 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6002 assert_panel_unlocked(dev_priv, pipe);
6004 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6005 I915_WRITE(dpll_reg, dpll);
6006 intel_wait_for_vblank(dev, pipe);
6008 dpll = I915_READ(dpll_reg);
6009 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6010 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6014 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6016 struct drm_device *dev = crtc->dev;
6017 drm_i915_private_t *dev_priv = dev->dev_private;
6018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6020 if (HAS_PCH_SPLIT(dev))
6023 if (!dev_priv->lvds_downclock_avail)
6027 * Since this is called by a timer, we should never get here in
6030 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6031 int pipe = intel_crtc->pipe;
6032 int dpll_reg = DPLL(pipe);
6035 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6037 assert_panel_unlocked(dev_priv, pipe);
6039 dpll = I915_READ(dpll_reg);
6040 dpll |= DISPLAY_RATE_SELECT_FPA1;
6041 I915_WRITE(dpll_reg, dpll);
6042 intel_wait_for_vblank(dev, pipe);
6043 dpll = I915_READ(dpll_reg);
6044 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6045 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6050 void intel_mark_busy(struct drm_device *dev)
6052 i915_update_gfx_val(dev->dev_private);
6055 void intel_mark_idle(struct drm_device *dev)
6059 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6061 struct drm_device *dev = obj->base.dev;
6062 struct drm_crtc *crtc;
6064 if (!i915_powersave)
6067 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6071 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6072 intel_increase_pllclock(crtc);
6076 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6078 struct drm_device *dev = obj->base.dev;
6079 struct drm_crtc *crtc;
6081 if (!i915_powersave)
6084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6088 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6089 intel_decrease_pllclock(crtc);
6093 static void intel_crtc_destroy(struct drm_crtc *crtc)
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 struct drm_device *dev = crtc->dev;
6097 struct intel_unpin_work *work;
6098 unsigned long flags;
6100 spin_lock_irqsave(&dev->event_lock, flags);
6101 work = intel_crtc->unpin_work;
6102 intel_crtc->unpin_work = NULL;
6103 spin_unlock_irqrestore(&dev->event_lock, flags);
6106 cancel_work_sync(&work->work);
6110 drm_crtc_cleanup(crtc);
6115 static void intel_unpin_work_fn(struct work_struct *__work)
6117 struct intel_unpin_work *work =
6118 container_of(__work, struct intel_unpin_work, work);
6120 mutex_lock(&work->dev->struct_mutex);
6121 intel_unpin_fb_obj(work->old_fb_obj);
6122 drm_gem_object_unreference(&work->pending_flip_obj->base);
6123 drm_gem_object_unreference(&work->old_fb_obj->base);
6125 intel_update_fbc(work->dev);
6126 mutex_unlock(&work->dev->struct_mutex);
6130 static void do_intel_finish_page_flip(struct drm_device *dev,
6131 struct drm_crtc *crtc)
6133 drm_i915_private_t *dev_priv = dev->dev_private;
6134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135 struct intel_unpin_work *work;
6136 struct drm_i915_gem_object *obj;
6137 struct drm_pending_vblank_event *e;
6138 struct timeval tnow, tvbl;
6139 unsigned long flags;
6141 /* Ignore early vblank irqs */
6142 if (intel_crtc == NULL)
6145 do_gettimeofday(&tnow);
6147 spin_lock_irqsave(&dev->event_lock, flags);
6148 work = intel_crtc->unpin_work;
6149 if (work == NULL || !work->pending) {
6150 spin_unlock_irqrestore(&dev->event_lock, flags);
6154 intel_crtc->unpin_work = NULL;
6158 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6160 /* Called before vblank count and timestamps have
6161 * been updated for the vblank interval of flip
6162 * completion? Need to increment vblank count and
6163 * add one videorefresh duration to returned timestamp
6164 * to account for this. We assume this happened if we
6165 * get called over 0.9 frame durations after the last
6166 * timestamped vblank.
6168 * This calculation can not be used with vrefresh rates
6169 * below 5Hz (10Hz to be on the safe side) without
6170 * promoting to 64 integers.
6172 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6173 9 * crtc->framedur_ns) {
6174 e->event.sequence++;
6175 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6179 e->event.tv_sec = tvbl.tv_sec;
6180 e->event.tv_usec = tvbl.tv_usec;
6182 list_add_tail(&e->base.link,
6183 &e->base.file_priv->event_list);
6184 wake_up_interruptible(&e->base.file_priv->event_wait);
6187 drm_vblank_put(dev, intel_crtc->pipe);
6189 spin_unlock_irqrestore(&dev->event_lock, flags);
6191 obj = work->old_fb_obj;
6193 atomic_clear_mask(1 << intel_crtc->plane,
6194 &obj->pending_flip.counter);
6195 if (atomic_read(&obj->pending_flip) == 0)
6196 wake_up(&dev_priv->pending_flip_queue);
6198 schedule_work(&work->work);
6200 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6203 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6205 drm_i915_private_t *dev_priv = dev->dev_private;
6206 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6208 do_intel_finish_page_flip(dev, crtc);
6211 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6213 drm_i915_private_t *dev_priv = dev->dev_private;
6214 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6216 do_intel_finish_page_flip(dev, crtc);
6219 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6221 drm_i915_private_t *dev_priv = dev->dev_private;
6222 struct intel_crtc *intel_crtc =
6223 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6224 unsigned long flags;
6226 spin_lock_irqsave(&dev->event_lock, flags);
6227 if (intel_crtc->unpin_work) {
6228 if ((++intel_crtc->unpin_work->pending) > 1)
6229 DRM_ERROR("Prepared flip multiple times\n");
6231 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6233 spin_unlock_irqrestore(&dev->event_lock, flags);
6236 static int intel_gen2_queue_flip(struct drm_device *dev,
6237 struct drm_crtc *crtc,
6238 struct drm_framebuffer *fb,
6239 struct drm_i915_gem_object *obj)
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6244 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6247 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6251 ret = intel_ring_begin(ring, 6);
6255 /* Can't queue multiple flips, so wait for the previous
6256 * one to finish before executing the next.
6258 if (intel_crtc->plane)
6259 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6261 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6262 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6263 intel_ring_emit(ring, MI_NOOP);
6264 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6265 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6266 intel_ring_emit(ring, fb->pitches[0]);
6267 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6268 intel_ring_emit(ring, 0); /* aux display base address, unused */
6269 intel_ring_advance(ring);
6273 intel_unpin_fb_obj(obj);
6278 static int intel_gen3_queue_flip(struct drm_device *dev,
6279 struct drm_crtc *crtc,
6280 struct drm_framebuffer *fb,
6281 struct drm_i915_gem_object *obj)
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6289 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6293 ret = intel_ring_begin(ring, 6);
6297 if (intel_crtc->plane)
6298 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6300 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6301 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6302 intel_ring_emit(ring, MI_NOOP);
6303 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6305 intel_ring_emit(ring, fb->pitches[0]);
6306 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6307 intel_ring_emit(ring, MI_NOOP);
6309 intel_ring_advance(ring);
6313 intel_unpin_fb_obj(obj);
6318 static int intel_gen4_queue_flip(struct drm_device *dev,
6319 struct drm_crtc *crtc,
6320 struct drm_framebuffer *fb,
6321 struct drm_i915_gem_object *obj)
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325 uint32_t pf, pipesrc;
6326 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6329 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6333 ret = intel_ring_begin(ring, 4);
6337 /* i965+ uses the linear or tiled offsets from the
6338 * Display Registers (which do not change across a page-flip)
6339 * so we need only reprogram the base address.
6341 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6343 intel_ring_emit(ring, fb->pitches[0]);
6344 intel_ring_emit(ring,
6345 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6348 /* XXX Enabling the panel-fitter across page-flip is so far
6349 * untested on non-native modes, so ignore it for now.
6350 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6353 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6354 intel_ring_emit(ring, pf | pipesrc);
6355 intel_ring_advance(ring);
6359 intel_unpin_fb_obj(obj);
6364 static int intel_gen6_queue_flip(struct drm_device *dev,
6365 struct drm_crtc *crtc,
6366 struct drm_framebuffer *fb,
6367 struct drm_i915_gem_object *obj)
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6372 uint32_t pf, pipesrc;
6375 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6379 ret = intel_ring_begin(ring, 4);
6383 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6385 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6386 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6388 /* Contrary to the suggestions in the documentation,
6389 * "Enable Panel Fitter" does not seem to be required when page
6390 * flipping with a non-native mode, and worse causes a normal
6392 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6395 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6396 intel_ring_emit(ring, pf | pipesrc);
6397 intel_ring_advance(ring);
6401 intel_unpin_fb_obj(obj);
6407 * On gen7 we currently use the blit ring because (in early silicon at least)
6408 * the render ring doesn't give us interrpts for page flip completion, which
6409 * means clients will hang after the first flip is queued. Fortunately the
6410 * blit ring generates interrupts properly, so use it instead.
6412 static int intel_gen7_queue_flip(struct drm_device *dev,
6413 struct drm_crtc *crtc,
6414 struct drm_framebuffer *fb,
6415 struct drm_i915_gem_object *obj)
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6420 uint32_t plane_bit = 0;
6423 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6427 switch(intel_crtc->plane) {
6429 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6432 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6435 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6438 WARN_ONCE(1, "unknown plane in flip command\n");
6443 ret = intel_ring_begin(ring, 4);
6447 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6448 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6449 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6450 intel_ring_emit(ring, (MI_NOOP));
6451 intel_ring_advance(ring);
6455 intel_unpin_fb_obj(obj);
6460 static int intel_default_queue_flip(struct drm_device *dev,
6461 struct drm_crtc *crtc,
6462 struct drm_framebuffer *fb,
6463 struct drm_i915_gem_object *obj)
6468 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6469 struct drm_framebuffer *fb,
6470 struct drm_pending_vblank_event *event)
6472 struct drm_device *dev = crtc->dev;
6473 struct drm_i915_private *dev_priv = dev->dev_private;
6474 struct intel_framebuffer *intel_fb;
6475 struct drm_i915_gem_object *obj;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477 struct intel_unpin_work *work;
6478 unsigned long flags;
6481 /* Can't change pixel format via MI display flips. */
6482 if (fb->pixel_format != crtc->fb->pixel_format)
6486 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6487 * Note that pitch changes could also affect these register.
6489 if (INTEL_INFO(dev)->gen > 3 &&
6490 (fb->offsets[0] != crtc->fb->offsets[0] ||
6491 fb->pitches[0] != crtc->fb->pitches[0]))
6494 work = kzalloc(sizeof *work, GFP_KERNEL);
6498 work->event = event;
6499 work->dev = crtc->dev;
6500 intel_fb = to_intel_framebuffer(crtc->fb);
6501 work->old_fb_obj = intel_fb->obj;
6502 INIT_WORK(&work->work, intel_unpin_work_fn);
6504 ret = drm_vblank_get(dev, intel_crtc->pipe);
6508 /* We borrow the event spin lock for protecting unpin_work */
6509 spin_lock_irqsave(&dev->event_lock, flags);
6510 if (intel_crtc->unpin_work) {
6511 spin_unlock_irqrestore(&dev->event_lock, flags);
6513 drm_vblank_put(dev, intel_crtc->pipe);
6515 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6518 intel_crtc->unpin_work = work;
6519 spin_unlock_irqrestore(&dev->event_lock, flags);
6521 intel_fb = to_intel_framebuffer(fb);
6522 obj = intel_fb->obj;
6524 ret = i915_mutex_lock_interruptible(dev);
6528 /* Reference the objects for the scheduled work. */
6529 drm_gem_object_reference(&work->old_fb_obj->base);
6530 drm_gem_object_reference(&obj->base);
6534 work->pending_flip_obj = obj;
6536 work->enable_stall_check = true;
6538 /* Block clients from rendering to the new back buffer until
6539 * the flip occurs and the object is no longer visible.
6541 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6543 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6545 goto cleanup_pending;
6547 intel_disable_fbc(dev);
6548 intel_mark_fb_busy(obj);
6549 mutex_unlock(&dev->struct_mutex);
6551 trace_i915_flip_request(intel_crtc->plane, obj);
6556 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6557 drm_gem_object_unreference(&work->old_fb_obj->base);
6558 drm_gem_object_unreference(&obj->base);
6559 mutex_unlock(&dev->struct_mutex);
6562 spin_lock_irqsave(&dev->event_lock, flags);
6563 intel_crtc->unpin_work = NULL;
6564 spin_unlock_irqrestore(&dev->event_lock, flags);
6566 drm_vblank_put(dev, intel_crtc->pipe);
6573 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6574 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6575 .load_lut = intel_crtc_load_lut,
6576 .disable = intel_crtc_disable,
6579 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6580 struct drm_crtc *crtc)
6582 struct drm_device *dev;
6583 struct drm_crtc *tmp;
6586 WARN(!crtc, "checking null crtc?\n");
6590 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6596 if (encoder->possible_crtcs & crtc_mask)
6602 intel_crtc_helper_disable(struct drm_crtc *crtc)
6604 struct drm_device *dev = crtc->dev;
6605 struct drm_connector *connector;
6606 struct drm_encoder *encoder;
6608 /* Decouple all encoders and their attached connectors from this crtc */
6609 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6610 if (encoder->crtc != crtc)
6613 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6614 if (connector->encoder != encoder)
6617 connector->encoder = NULL;
6621 drm_helper_disable_unused_functions(dev);
6626 intel_crtc_prepare_encoders(struct drm_device *dev)
6628 struct intel_encoder *encoder;
6630 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6631 /* Disable unused encoders */
6632 if (encoder->base.crtc == NULL)
6633 encoder->disable(encoder);
6637 bool intel_set_mode(struct drm_crtc *crtc,
6638 struct drm_display_mode *mode,
6639 int x, int y, struct drm_framebuffer *old_fb)
6641 struct drm_device *dev = crtc->dev;
6642 drm_i915_private_t *dev_priv = dev->dev_private;
6643 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6644 struct drm_encoder_helper_funcs *encoder_funcs;
6645 int saved_x, saved_y;
6646 struct drm_encoder *encoder;
6649 crtc->enabled = drm_helper_crtc_in_use(crtc);
6653 adjusted_mode = drm_mode_duplicate(dev, mode);
6657 saved_hwmode = crtc->hwmode;
6658 saved_mode = crtc->mode;
6662 /* Update crtc values up front so the driver can rely on them for mode
6669 /* Pass our mode to the connectors and the CRTC to give them a chance to
6670 * adjust it according to limitations or connector properties, and also
6671 * a chance to reject the mode entirely.
6673 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6675 if (encoder->crtc != crtc)
6677 encoder_funcs = encoder->helper_private;
6678 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6680 DRM_DEBUG_KMS("Encoder fixup failed\n");
6685 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6686 DRM_DEBUG_KMS("CRTC fixup failed\n");
6689 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6691 intel_crtc_prepare_encoders(dev);
6693 dev_priv->display.crtc_disable(crtc);
6695 /* Set up the DPLL and any encoders state that needs to adjust or depend
6698 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
6702 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6704 if (encoder->crtc != crtc)
6707 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6708 encoder->base.id, drm_get_encoder_name(encoder),
6709 mode->base.id, mode->name);
6710 encoder_funcs = encoder->helper_private;
6711 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6714 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6715 dev_priv->display.crtc_enable(crtc);
6717 /* Store real post-adjustment hardware mode. */
6718 crtc->hwmode = *adjusted_mode;
6720 /* Calculate and store various constants which
6721 * are later needed by vblank and swap-completion
6722 * timestamping. They are derived from true hwmode.
6724 drm_calc_timestamping_constants(crtc);
6726 /* FIXME: add subpixel order */
6728 drm_mode_destroy(dev, adjusted_mode);
6730 crtc->hwmode = saved_hwmode;
6731 crtc->mode = saved_mode;
6739 static int intel_crtc_set_config(struct drm_mode_set *set)
6741 struct drm_device *dev;
6742 struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6743 struct drm_encoder *save_encoders, *new_encoder, *encoder;
6744 struct drm_framebuffer *old_fb = NULL;
6745 bool mode_changed = false; /* if true do a full mode set */
6746 bool fb_changed = false; /* if true and !mode_changed just do a flip */
6747 struct drm_connector *save_connectors, *connector;
6749 struct drm_mode_set save_set;
6753 DRM_DEBUG_KMS("\n");
6761 if (!set->crtc->helper_private)
6768 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6769 set->crtc->base.id, set->fb->base.id,
6770 (int)set->num_connectors, set->x, set->y);
6772 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6773 return intel_crtc_helper_disable(set->crtc);
6776 dev = set->crtc->dev;
6778 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6779 * connector data. */
6780 save_crtcs = kzalloc(dev->mode_config.num_crtc *
6781 sizeof(struct drm_crtc), GFP_KERNEL);
6785 save_encoders = kzalloc(dev->mode_config.num_encoder *
6786 sizeof(struct drm_encoder), GFP_KERNEL);
6787 if (!save_encoders) {
6792 save_connectors = kzalloc(dev->mode_config.num_connector *
6793 sizeof(struct drm_connector), GFP_KERNEL);
6794 if (!save_connectors) {
6796 kfree(save_encoders);
6800 /* Copy data. Note that driver private data is not affected.
6801 * Should anything bad happen only the expected state is
6802 * restored, not the drivers personal bookkeeping.
6805 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6806 save_crtcs[count++] = *crtc;
6810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6811 save_encoders[count++] = *encoder;
6815 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6816 save_connectors[count++] = *connector;
6819 save_set.crtc = set->crtc;
6820 save_set.mode = &set->crtc->mode;
6821 save_set.x = set->crtc->x;
6822 save_set.y = set->crtc->y;
6823 save_set.fb = set->crtc->fb;
6825 /* We should be able to check here if the fb has the same properties
6826 * and then just flip_or_move it */
6827 if (set->crtc->fb != set->fb) {
6828 /* If we have no fb then treat it as a full mode set */
6829 if (set->crtc->fb == NULL) {
6830 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6831 mode_changed = true;
6832 } else if (set->fb == NULL) {
6833 mode_changed = true;
6834 } else if (set->fb->depth != set->crtc->fb->depth) {
6835 mode_changed = true;
6836 } else if (set->fb->bits_per_pixel !=
6837 set->crtc->fb->bits_per_pixel) {
6838 mode_changed = true;
6843 if (set->x != set->crtc->x || set->y != set->crtc->y)
6846 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6847 DRM_DEBUG_KMS("modes are different, full mode set\n");
6848 drm_mode_debug_printmodeline(&set->crtc->mode);
6849 drm_mode_debug_printmodeline(set->mode);
6850 mode_changed = true;
6853 /* a) traverse passed in connector list and get encoders for them */
6855 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6856 new_encoder = connector->encoder;
6857 for (ro = 0; ro < set->num_connectors; ro++) {
6858 if (set->connectors[ro] == connector) {
6860 &intel_attached_encoder(connector)->base;
6865 if (new_encoder != connector->encoder) {
6866 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6867 mode_changed = true;
6868 /* If the encoder is reused for another connector, then
6869 * the appropriate crtc will be set later.
6871 if (connector->encoder)
6872 connector->encoder->crtc = NULL;
6873 connector->encoder = new_encoder;
6878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6879 if (!connector->encoder)
6882 if (connector->encoder->crtc == set->crtc)
6885 new_crtc = connector->encoder->crtc;
6887 for (ro = 0; ro < set->num_connectors; ro++) {
6888 if (set->connectors[ro] == connector)
6889 new_crtc = set->crtc;
6892 /* Make sure the new CRTC will work with the encoder */
6894 !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6898 if (new_crtc != connector->encoder->crtc) {
6899 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6900 mode_changed = true;
6901 connector->encoder->crtc = new_crtc;
6904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6905 connector->base.id, drm_get_connector_name(connector),
6908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6909 connector->base.id, drm_get_connector_name(connector));
6914 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6915 if (set->crtc->enabled) {
6916 DRM_DEBUG_KMS("attempting to set mode from"
6918 drm_mode_debug_printmodeline(set->mode);
6919 old_fb = set->crtc->fb;
6920 set->crtc->fb = set->fb;
6921 if (!intel_set_mode(set->crtc, set->mode,
6922 set->x, set->y, old_fb)) {
6923 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6924 set->crtc->base.id);
6925 set->crtc->fb = old_fb;
6929 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6930 for (i = 0; i < set->num_connectors; i++) {
6931 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6932 drm_get_connector_name(set->connectors[i]));
6933 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6936 drm_helper_disable_unused_functions(dev);
6937 } else if (fb_changed) {
6938 set->crtc->x = set->x;
6939 set->crtc->y = set->y;
6941 old_fb = set->crtc->fb;
6942 if (set->crtc->fb != set->fb)
6943 set->crtc->fb = set->fb;
6944 ret = intel_pipe_set_base(set->crtc,
6945 set->x, set->y, old_fb);
6947 set->crtc->fb = old_fb;
6952 kfree(save_connectors);
6953 kfree(save_encoders);
6958 /* Restore all previous data. */
6960 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6961 *crtc = save_crtcs[count++];
6965 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6966 *encoder = save_encoders[count++];
6970 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6971 *connector = save_connectors[count++];
6974 /* Try to restore the config */
6976 !intel_set_mode(save_set.crtc, save_set.mode,
6977 save_set.x, save_set.y, save_set.fb))
6978 DRM_ERROR("failed to restore config after modeset failure\n");
6980 kfree(save_connectors);
6981 kfree(save_encoders);
6986 static const struct drm_crtc_funcs intel_crtc_funcs = {
6987 .cursor_set = intel_crtc_cursor_set,
6988 .cursor_move = intel_crtc_cursor_move,
6989 .gamma_set = intel_crtc_gamma_set,
6990 .set_config = intel_crtc_set_config,
6991 .destroy = intel_crtc_destroy,
6992 .page_flip = intel_crtc_page_flip,
6995 static void intel_pch_pll_init(struct drm_device *dev)
6997 drm_i915_private_t *dev_priv = dev->dev_private;
7000 if (dev_priv->num_pch_pll == 0) {
7001 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7005 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7006 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7007 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7008 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7012 static void intel_crtc_init(struct drm_device *dev, int pipe)
7014 drm_i915_private_t *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc;
7018 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7019 if (intel_crtc == NULL)
7022 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7024 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7025 for (i = 0; i < 256; i++) {
7026 intel_crtc->lut_r[i] = i;
7027 intel_crtc->lut_g[i] = i;
7028 intel_crtc->lut_b[i] = i;
7031 /* Swap pipes & planes for FBC on pre-965 */
7032 intel_crtc->pipe = pipe;
7033 intel_crtc->plane = pipe;
7034 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7035 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7036 intel_crtc->plane = !pipe;
7039 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7040 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7041 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7042 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7044 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7046 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7049 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7050 struct drm_file *file)
7052 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7053 struct drm_mode_object *drmmode_obj;
7054 struct intel_crtc *crtc;
7056 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7059 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7060 DRM_MODE_OBJECT_CRTC);
7063 DRM_ERROR("no such CRTC id\n");
7067 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7068 pipe_from_crtc_id->pipe = crtc->pipe;
7073 static int intel_encoder_clones(struct intel_encoder *encoder)
7075 struct drm_device *dev = encoder->base.dev;
7076 struct intel_encoder *source_encoder;
7080 list_for_each_entry(source_encoder,
7081 &dev->mode_config.encoder_list, base.head) {
7083 if (encoder == source_encoder)
7084 index_mask |= (1 << entry);
7086 /* Intel hw has only one MUX where enocoders could be cloned. */
7087 if (encoder->cloneable && source_encoder->cloneable)
7088 index_mask |= (1 << entry);
7096 static bool has_edp_a(struct drm_device *dev)
7098 struct drm_i915_private *dev_priv = dev->dev_private;
7100 if (!IS_MOBILE(dev))
7103 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7107 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7113 static void intel_setup_outputs(struct drm_device *dev)
7115 struct drm_i915_private *dev_priv = dev->dev_private;
7116 struct intel_encoder *encoder;
7117 bool dpd_is_edp = false;
7120 has_lvds = intel_lvds_init(dev);
7121 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7122 /* disable the panel fitter on everything but LVDS */
7123 I915_WRITE(PFIT_CONTROL, 0);
7126 if (HAS_PCH_SPLIT(dev)) {
7127 dpd_is_edp = intel_dpd_is_edp(dev);
7130 intel_dp_init(dev, DP_A, PORT_A);
7132 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7133 intel_dp_init(dev, PCH_DP_D, PORT_D);
7136 intel_crt_init(dev);
7138 if (IS_HASWELL(dev)) {
7141 /* Haswell uses DDI functions to detect digital outputs */
7142 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7143 /* DDI A only supports eDP */
7145 intel_ddi_init(dev, PORT_A);
7147 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7149 found = I915_READ(SFUSE_STRAP);
7151 if (found & SFUSE_STRAP_DDIB_DETECTED)
7152 intel_ddi_init(dev, PORT_B);
7153 if (found & SFUSE_STRAP_DDIC_DETECTED)
7154 intel_ddi_init(dev, PORT_C);
7155 if (found & SFUSE_STRAP_DDID_DETECTED)
7156 intel_ddi_init(dev, PORT_D);
7157 } else if (HAS_PCH_SPLIT(dev)) {
7160 if (I915_READ(HDMIB) & PORT_DETECTED) {
7161 /* PCH SDVOB multiplex with HDMIB */
7162 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7164 intel_hdmi_init(dev, HDMIB, PORT_B);
7165 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7166 intel_dp_init(dev, PCH_DP_B, PORT_B);
7169 if (I915_READ(HDMIC) & PORT_DETECTED)
7170 intel_hdmi_init(dev, HDMIC, PORT_C);
7172 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7173 intel_hdmi_init(dev, HDMID, PORT_D);
7175 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7176 intel_dp_init(dev, PCH_DP_C, PORT_C);
7178 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7179 intel_dp_init(dev, PCH_DP_D, PORT_D);
7180 } else if (IS_VALLEYVIEW(dev)) {
7183 if (I915_READ(SDVOB) & PORT_DETECTED) {
7184 /* SDVOB multiplex with HDMIB */
7185 found = intel_sdvo_init(dev, SDVOB, true);
7187 intel_hdmi_init(dev, SDVOB, PORT_B);
7188 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7189 intel_dp_init(dev, DP_B, PORT_B);
7192 if (I915_READ(SDVOC) & PORT_DETECTED)
7193 intel_hdmi_init(dev, SDVOC, PORT_C);
7195 /* Shares lanes with HDMI on SDVOC */
7196 if (I915_READ(DP_C) & DP_DETECTED)
7197 intel_dp_init(dev, DP_C, PORT_C);
7198 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7201 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7202 DRM_DEBUG_KMS("probing SDVOB\n");
7203 found = intel_sdvo_init(dev, SDVOB, true);
7204 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7205 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7206 intel_hdmi_init(dev, SDVOB, PORT_B);
7209 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7210 DRM_DEBUG_KMS("probing DP_B\n");
7211 intel_dp_init(dev, DP_B, PORT_B);
7215 /* Before G4X SDVOC doesn't have its own detect register */
7217 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7218 DRM_DEBUG_KMS("probing SDVOC\n");
7219 found = intel_sdvo_init(dev, SDVOC, false);
7222 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7224 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7225 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7226 intel_hdmi_init(dev, SDVOC, PORT_C);
7228 if (SUPPORTS_INTEGRATED_DP(dev)) {
7229 DRM_DEBUG_KMS("probing DP_C\n");
7230 intel_dp_init(dev, DP_C, PORT_C);
7234 if (SUPPORTS_INTEGRATED_DP(dev) &&
7235 (I915_READ(DP_D) & DP_DETECTED)) {
7236 DRM_DEBUG_KMS("probing DP_D\n");
7237 intel_dp_init(dev, DP_D, PORT_D);
7239 } else if (IS_GEN2(dev))
7240 intel_dvo_init(dev);
7242 if (SUPPORTS_TV(dev))
7245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7246 encoder->base.possible_crtcs = encoder->crtc_mask;
7247 encoder->base.possible_clones =
7248 intel_encoder_clones(encoder);
7251 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7252 ironlake_init_pch_refclk(dev);
7255 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7259 drm_framebuffer_cleanup(fb);
7260 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7265 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7266 struct drm_file *file,
7267 unsigned int *handle)
7269 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7270 struct drm_i915_gem_object *obj = intel_fb->obj;
7272 return drm_gem_handle_create(file, &obj->base, handle);
7275 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7276 .destroy = intel_user_framebuffer_destroy,
7277 .create_handle = intel_user_framebuffer_create_handle,
7280 int intel_framebuffer_init(struct drm_device *dev,
7281 struct intel_framebuffer *intel_fb,
7282 struct drm_mode_fb_cmd2 *mode_cmd,
7283 struct drm_i915_gem_object *obj)
7287 if (obj->tiling_mode == I915_TILING_Y)
7290 if (mode_cmd->pitches[0] & 63)
7293 switch (mode_cmd->pixel_format) {
7294 case DRM_FORMAT_RGB332:
7295 case DRM_FORMAT_RGB565:
7296 case DRM_FORMAT_XRGB8888:
7297 case DRM_FORMAT_XBGR8888:
7298 case DRM_FORMAT_ARGB8888:
7299 case DRM_FORMAT_XRGB2101010:
7300 case DRM_FORMAT_ARGB2101010:
7301 /* RGB formats are common across chipsets */
7303 case DRM_FORMAT_YUYV:
7304 case DRM_FORMAT_UYVY:
7305 case DRM_FORMAT_YVYU:
7306 case DRM_FORMAT_VYUY:
7309 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7310 mode_cmd->pixel_format);
7314 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7316 DRM_ERROR("framebuffer init failed %d\n", ret);
7320 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7321 intel_fb->obj = obj;
7325 static struct drm_framebuffer *
7326 intel_user_framebuffer_create(struct drm_device *dev,
7327 struct drm_file *filp,
7328 struct drm_mode_fb_cmd2 *mode_cmd)
7330 struct drm_i915_gem_object *obj;
7332 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7333 mode_cmd->handles[0]));
7334 if (&obj->base == NULL)
7335 return ERR_PTR(-ENOENT);
7337 return intel_framebuffer_create(dev, mode_cmd, obj);
7340 static const struct drm_mode_config_funcs intel_mode_funcs = {
7341 .fb_create = intel_user_framebuffer_create,
7342 .output_poll_changed = intel_fb_output_poll_changed,
7345 /* Set up chip specific display functions */
7346 static void intel_init_display(struct drm_device *dev)
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7350 /* We always want a DPMS function */
7351 if (HAS_PCH_SPLIT(dev)) {
7352 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7353 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7354 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7355 dev_priv->display.off = ironlake_crtc_off;
7356 dev_priv->display.update_plane = ironlake_update_plane;
7358 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7359 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7360 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7361 dev_priv->display.off = i9xx_crtc_off;
7362 dev_priv->display.update_plane = i9xx_update_plane;
7365 /* Returns the core display clock speed */
7366 if (IS_VALLEYVIEW(dev))
7367 dev_priv->display.get_display_clock_speed =
7368 valleyview_get_display_clock_speed;
7369 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7370 dev_priv->display.get_display_clock_speed =
7371 i945_get_display_clock_speed;
7372 else if (IS_I915G(dev))
7373 dev_priv->display.get_display_clock_speed =
7374 i915_get_display_clock_speed;
7375 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7376 dev_priv->display.get_display_clock_speed =
7377 i9xx_misc_get_display_clock_speed;
7378 else if (IS_I915GM(dev))
7379 dev_priv->display.get_display_clock_speed =
7380 i915gm_get_display_clock_speed;
7381 else if (IS_I865G(dev))
7382 dev_priv->display.get_display_clock_speed =
7383 i865_get_display_clock_speed;
7384 else if (IS_I85X(dev))
7385 dev_priv->display.get_display_clock_speed =
7386 i855_get_display_clock_speed;
7388 dev_priv->display.get_display_clock_speed =
7389 i830_get_display_clock_speed;
7391 if (HAS_PCH_SPLIT(dev)) {
7393 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7394 dev_priv->display.write_eld = ironlake_write_eld;
7395 } else if (IS_GEN6(dev)) {
7396 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7397 dev_priv->display.write_eld = ironlake_write_eld;
7398 } else if (IS_IVYBRIDGE(dev)) {
7399 /* FIXME: detect B0+ stepping and use auto training */
7400 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7401 dev_priv->display.write_eld = ironlake_write_eld;
7402 } else if (IS_HASWELL(dev)) {
7403 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7404 dev_priv->display.write_eld = haswell_write_eld;
7406 dev_priv->display.update_wm = NULL;
7407 } else if (IS_G4X(dev)) {
7408 dev_priv->display.write_eld = g4x_write_eld;
7411 /* Default just returns -ENODEV to indicate unsupported */
7412 dev_priv->display.queue_flip = intel_default_queue_flip;
7414 switch (INTEL_INFO(dev)->gen) {
7416 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7420 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7425 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7429 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7432 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7438 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7439 * resume, or other times. This quirk makes sure that's the case for
7442 static void quirk_pipea_force(struct drm_device *dev)
7444 struct drm_i915_private *dev_priv = dev->dev_private;
7446 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7447 DRM_INFO("applying pipe a force quirk\n");
7451 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7453 static void quirk_ssc_force_disable(struct drm_device *dev)
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7457 DRM_INFO("applying lvds SSC disable quirk\n");
7461 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7464 static void quirk_invert_brightness(struct drm_device *dev)
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7468 DRM_INFO("applying inverted panel brightness quirk\n");
7471 struct intel_quirk {
7473 int subsystem_vendor;
7474 int subsystem_device;
7475 void (*hook)(struct drm_device *dev);
7478 static struct intel_quirk intel_quirks[] = {
7479 /* HP Mini needs pipe A force quirk (LP: #322104) */
7480 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7482 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7483 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7485 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7486 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7488 /* 855 & before need to leave pipe A & dpll A up */
7489 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7490 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7491 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7493 /* Lenovo U160 cannot use SSC on LVDS */
7494 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7496 /* Sony Vaio Y cannot use SSC on LVDS */
7497 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7499 /* Acer Aspire 5734Z must invert backlight brightness */
7500 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7503 static void intel_init_quirks(struct drm_device *dev)
7505 struct pci_dev *d = dev->pdev;
7508 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7509 struct intel_quirk *q = &intel_quirks[i];
7511 if (d->device == q->device &&
7512 (d->subsystem_vendor == q->subsystem_vendor ||
7513 q->subsystem_vendor == PCI_ANY_ID) &&
7514 (d->subsystem_device == q->subsystem_device ||
7515 q->subsystem_device == PCI_ANY_ID))
7520 /* Disable the VGA plane that we never use */
7521 static void i915_disable_vga(struct drm_device *dev)
7523 struct drm_i915_private *dev_priv = dev->dev_private;
7527 if (HAS_PCH_SPLIT(dev))
7528 vga_reg = CPU_VGACNTRL;
7532 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7533 outb(SR01, VGA_SR_INDEX);
7534 sr1 = inb(VGA_SR_DATA);
7535 outb(sr1 | 1<<5, VGA_SR_DATA);
7536 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7539 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7540 POSTING_READ(vga_reg);
7543 void intel_modeset_init_hw(struct drm_device *dev)
7545 /* We attempt to init the necessary power wells early in the initialization
7546 * time, so the subsystems that expect power to be enabled can work.
7548 intel_init_power_wells(dev);
7550 intel_prepare_ddi(dev);
7552 intel_init_clock_gating(dev);
7554 mutex_lock(&dev->struct_mutex);
7555 intel_enable_gt_powersave(dev);
7556 mutex_unlock(&dev->struct_mutex);
7559 void intel_modeset_init(struct drm_device *dev)
7561 struct drm_i915_private *dev_priv = dev->dev_private;
7564 drm_mode_config_init(dev);
7566 dev->mode_config.min_width = 0;
7567 dev->mode_config.min_height = 0;
7569 dev->mode_config.preferred_depth = 24;
7570 dev->mode_config.prefer_shadow = 1;
7572 dev->mode_config.funcs = &intel_mode_funcs;
7574 intel_init_quirks(dev);
7578 intel_init_display(dev);
7581 dev->mode_config.max_width = 2048;
7582 dev->mode_config.max_height = 2048;
7583 } else if (IS_GEN3(dev)) {
7584 dev->mode_config.max_width = 4096;
7585 dev->mode_config.max_height = 4096;
7587 dev->mode_config.max_width = 8192;
7588 dev->mode_config.max_height = 8192;
7590 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7592 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7593 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7595 for (i = 0; i < dev_priv->num_pipe; i++) {
7596 intel_crtc_init(dev, i);
7597 ret = intel_plane_init(dev, i);
7599 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7602 intel_pch_pll_init(dev);
7604 /* Just disable it once at startup */
7605 i915_disable_vga(dev);
7606 intel_setup_outputs(dev);
7610 intel_connector_break_all_links(struct intel_connector *connector)
7612 connector->base.dpms = DRM_MODE_DPMS_OFF;
7613 connector->base.encoder = NULL;
7614 connector->encoder->connectors_active = false;
7615 connector->encoder->base.crtc = NULL;
7618 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = dev->dev_private;
7624 /* Clear the dpms state for compatibility with code still using that
7625 * deprecated state variable. */
7626 crtc->dpms_mode = -1;
7628 /* Clear any frame start delays used for debugging left by the BIOS */
7629 reg = PIPECONF(crtc->pipe);
7630 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7632 /* We need to sanitize the plane -> pipe mapping first because this will
7633 * disable the crtc (and hence change the state) if it is wrong. */
7634 if (!HAS_PCH_SPLIT(dev)) {
7635 struct intel_connector *connector;
7638 reg = DSPCNTR(crtc->plane);
7639 val = I915_READ(reg);
7641 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7642 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7645 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7646 crtc->base.base.id);
7648 /* Pipe has the wrong plane attached and the plane is active.
7649 * Temporarily change the plane mapping and disable everything
7651 plane = crtc->plane;
7652 crtc->plane = !plane;
7653 dev_priv->display.crtc_disable(&crtc->base);
7654 crtc->plane = plane;
7656 /* ... and break all links. */
7657 list_for_each_entry(connector, &dev->mode_config.connector_list,
7659 if (connector->encoder->base.crtc != &crtc->base)
7662 intel_connector_break_all_links(connector);
7665 WARN_ON(crtc->active);
7666 crtc->base.enabled = false;
7670 /* Adjust the state of the output pipe according to whether we
7671 * have active connectors/encoders. */
7672 intel_crtc_update_dpms(&crtc->base);
7674 if (crtc->active != crtc->base.enabled) {
7675 struct intel_encoder *encoder;
7677 /* This can happen either due to bugs in the get_hw_state
7678 * functions or because the pipe is force-enabled due to the
7680 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7682 crtc->base.enabled ? "enabled" : "disabled",
7683 crtc->active ? "enabled" : "disabled");
7685 crtc->base.enabled = crtc->active;
7687 /* Because we only establish the connector -> encoder ->
7688 * crtc links if something is active, this means the
7689 * crtc is now deactivated. Break the links. connector
7690 * -> encoder links are only establish when things are
7691 * actually up, hence no need to break them. */
7692 WARN_ON(crtc->active);
7694 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7695 WARN_ON(encoder->connectors_active);
7696 encoder->base.crtc = NULL;
7701 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7703 struct intel_connector *connector;
7704 struct drm_device *dev = encoder->base.dev;
7706 /* We need to check both for a crtc link (meaning that the
7707 * encoder is active and trying to read from a pipe) and the
7708 * pipe itself being active. */
7709 bool has_active_crtc = encoder->base.crtc &&
7710 to_intel_crtc(encoder->base.crtc)->active;
7712 if (encoder->connectors_active && !has_active_crtc) {
7713 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7714 encoder->base.base.id,
7715 drm_get_encoder_name(&encoder->base));
7717 /* Connector is active, but has no active pipe. This is
7718 * fallout from our resume register restoring. Disable
7719 * the encoder manually again. */
7720 if (encoder->base.crtc) {
7721 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7722 encoder->base.base.id,
7723 drm_get_encoder_name(&encoder->base));
7724 encoder->disable(encoder);
7727 /* Inconsistent output/port/pipe state happens presumably due to
7728 * a bug in one of the get_hw_state functions. Or someplace else
7729 * in our code, like the register restore mess on resume. Clamp
7730 * things to off as a safer default. */
7731 list_for_each_entry(connector,
7732 &dev->mode_config.connector_list,
7734 if (connector->encoder != encoder)
7737 intel_connector_break_all_links(connector);
7740 /* Enabled encoders without active connectors will be fixed in
7741 * the crtc fixup. */
7744 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7745 * and i915 state tracking structures. */
7746 void intel_modeset_setup_hw_state(struct drm_device *dev)
7748 struct drm_i915_private *dev_priv = dev->dev_private;
7751 struct intel_crtc *crtc;
7752 struct intel_encoder *encoder;
7753 struct intel_connector *connector;
7755 for_each_pipe(pipe) {
7756 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7758 tmp = I915_READ(PIPECONF(pipe));
7759 if (tmp & PIPECONF_ENABLE)
7760 crtc->active = true;
7762 crtc->active = false;
7764 crtc->base.enabled = crtc->active;
7766 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7768 crtc->active ? "enabled" : "disabled");
7771 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7775 if (encoder->get_hw_state(encoder, &pipe)) {
7776 encoder->base.crtc =
7777 dev_priv->pipe_to_crtc_mapping[pipe];
7779 encoder->base.crtc = NULL;
7782 encoder->connectors_active = false;
7783 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7784 encoder->base.base.id,
7785 drm_get_encoder_name(&encoder->base),
7786 encoder->base.crtc ? "enabled" : "disabled",
7790 list_for_each_entry(connector, &dev->mode_config.connector_list,
7792 if (connector->get_hw_state(connector)) {
7793 connector->base.dpms = DRM_MODE_DPMS_ON;
7794 connector->encoder->connectors_active = true;
7795 connector->base.encoder = &connector->encoder->base;
7797 connector->base.dpms = DRM_MODE_DPMS_OFF;
7798 connector->base.encoder = NULL;
7800 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7801 connector->base.base.id,
7802 drm_get_connector_name(&connector->base),
7803 connector->base.encoder ? "enabled" : "disabled");
7806 /* HW state is read out, now we need to sanitize this mess. */
7807 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7809 intel_sanitize_encoder(encoder);
7812 for_each_pipe(pipe) {
7813 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7814 intel_sanitize_crtc(crtc);
7818 void intel_modeset_gem_init(struct drm_device *dev)
7820 intel_modeset_init_hw(dev);
7822 intel_setup_overlay(dev);
7824 intel_modeset_setup_hw_state(dev);
7827 void intel_modeset_cleanup(struct drm_device *dev)
7829 struct drm_i915_private *dev_priv = dev->dev_private;
7830 struct drm_crtc *crtc;
7831 struct intel_crtc *intel_crtc;
7833 drm_kms_helper_poll_fini(dev);
7834 mutex_lock(&dev->struct_mutex);
7836 intel_unregister_dsm_handler();
7839 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7840 /* Skip inactive CRTCs */
7844 intel_crtc = to_intel_crtc(crtc);
7845 intel_increase_pllclock(crtc);
7848 intel_disable_fbc(dev);
7850 intel_disable_gt_powersave(dev);
7852 ironlake_teardown_rc6(dev);
7854 if (IS_VALLEYVIEW(dev))
7857 mutex_unlock(&dev->struct_mutex);
7859 /* Disable the irq before mode object teardown, for the irq might
7860 * enqueue unpin/hotplug work. */
7861 drm_irq_uninstall(dev);
7862 cancel_work_sync(&dev_priv->hotplug_work);
7863 cancel_work_sync(&dev_priv->rps.work);
7865 /* flush any delayed tasks or pending work */
7866 flush_scheduled_work();
7868 drm_mode_config_cleanup(dev);
7872 * Return which encoder is currently attached for connector.
7874 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7876 return &intel_attached_encoder(connector)->base;
7879 void intel_connector_attach_encoder(struct intel_connector *connector,
7880 struct intel_encoder *encoder)
7882 connector->encoder = encoder;
7883 drm_mode_connector_attach_encoder(&connector->base,
7888 * set vga decode state - true == enable VGA decode
7890 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7895 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7897 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7899 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7900 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7904 #ifdef CONFIG_DEBUG_FS
7905 #include <linux/seq_file.h>
7907 struct intel_display_error_state {
7908 struct intel_cursor_error_state {
7913 } cursor[I915_MAX_PIPES];
7915 struct intel_pipe_error_state {
7925 } pipe[I915_MAX_PIPES];
7927 struct intel_plane_error_state {
7935 } plane[I915_MAX_PIPES];
7938 struct intel_display_error_state *
7939 intel_display_capture_error_state(struct drm_device *dev)
7941 drm_i915_private_t *dev_priv = dev->dev_private;
7942 struct intel_display_error_state *error;
7945 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7950 error->cursor[i].control = I915_READ(CURCNTR(i));
7951 error->cursor[i].position = I915_READ(CURPOS(i));
7952 error->cursor[i].base = I915_READ(CURBASE(i));
7954 error->plane[i].control = I915_READ(DSPCNTR(i));
7955 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7956 error->plane[i].size = I915_READ(DSPSIZE(i));
7957 error->plane[i].pos = I915_READ(DSPPOS(i));
7958 error->plane[i].addr = I915_READ(DSPADDR(i));
7959 if (INTEL_INFO(dev)->gen >= 4) {
7960 error->plane[i].surface = I915_READ(DSPSURF(i));
7961 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7964 error->pipe[i].conf = I915_READ(PIPECONF(i));
7965 error->pipe[i].source = I915_READ(PIPESRC(i));
7966 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7967 error->pipe[i].hblank = I915_READ(HBLANK(i));
7968 error->pipe[i].hsync = I915_READ(HSYNC(i));
7969 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7970 error->pipe[i].vblank = I915_READ(VBLANK(i));
7971 error->pipe[i].vsync = I915_READ(VSYNC(i));
7978 intel_display_print_error_state(struct seq_file *m,
7979 struct drm_device *dev,
7980 struct intel_display_error_state *error)
7982 drm_i915_private_t *dev_priv = dev->dev_private;
7985 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7987 seq_printf(m, "Pipe [%d]:\n", i);
7988 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7989 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7990 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7991 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7992 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7993 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7994 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7995 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7997 seq_printf(m, "Plane [%d]:\n", i);
7998 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7999 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8000 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8001 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8002 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8003 if (INTEL_INFO(dev)->gen >= 4) {
8004 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8005 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8008 seq_printf(m, "Cursor [%d]:\n", i);
8009 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8010 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8011 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);