2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device *dev)
84 struct drm_i915_private *dev_priv = dev->dev_private;
86 WARN_ON(!HAS_PCH_SPLIT(dev));
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
194 .find_pll = intel_g4x_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
238 .find_pll = intel_g4x_find_best_PLL,
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
435 val = I915_READ(DPIO_DATA);
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464 static void vlv_init_dpio(struct drm_device *dev)
466 struct drm_i915_private *dev_priv = dev->dev_private;
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 { } /* terminating entry */
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
502 if (dmi_check_system(intel_dual_link_lvds))
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
534 limit = &intel_limits_ironlake_dual_lvds;
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
539 limit = &intel_limits_ironlake_single_lvds;
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
545 limit = &intel_limits_ironlake_dac;
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
601 limit = &intel_limits_i9xx_sdvo;
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
606 limit = &intel_limits_i8xx_dvo;
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
633 * Returns whether any output on the specified pipe is of the specified type
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
704 clock.p2 = limit->p2.p2_slow;
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
709 clock.p2 = limit->p2.p2_fast;
712 memset(best_clock, 0, sizeof(*best_clock));
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
732 clock.p != match_clock->p)
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
745 return (err != target);
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765 if (HAS_PCH_SPLIT(dev))
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
771 clock.p2 = limit->p2.p2_fast;
773 clock.p2 = limit->p2.p2_slow;
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
778 clock.p2 = limit->p2.p2_fast;
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
799 clock.p != match_clock->p)
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
821 struct drm_device *dev = crtc->dev;
824 if (target < 200000) {
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
849 if (target < 200000) {
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
881 dotclk = target * 1000;
884 fastclk = dotclk / (2*100);
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
912 if (absppm < bestppm - 10) {
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
944 return intel_crtc->cpu_transcoder;
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
952 frame = I915_READ(frame_reg);
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
959 * intel_wait_for_vblank - wait for vblank on a given pipe
961 * @pipe: pipe to wait for
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
996 DRM_DEBUG_KMS("vblank wait timed out\n");
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1002 * @pipe: pipe to wait for
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1028 WARN(1, "pipe_off wait timed out\n");
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035 line_mask = DSL_LINEMASK_GEN2;
1037 line_mask = DSL_LINEMASK_GEN3;
1039 /* Wait for the display line to settle */
1041 last_line = I915_READ(reg) & line_mask;
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1050 static const char *state_string(bool enabled)
1052 return enabled ? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1152 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1153 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_ENABLE);
1160 WARN(cur_state != state,
1161 "FDI RX state assertion failure (expected %s, current %s)\n",
1162 state_string(state), state_string(cur_state));
1164 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1165 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1167 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1173 /* ILK FDI PLL is always enabled */
1174 if (dev_priv->info->gen == 5)
1177 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1178 if (IS_HASWELL(dev_priv->dev))
1181 reg = FDI_TX_CTL(pipe);
1182 val = I915_READ(reg);
1183 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1192 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg);
1198 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 int pp_reg, lvds_reg;
1206 enum pipe panel_pipe = PIPE_A;
1209 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1210 pp_reg = PCH_PP_CONTROL;
1211 lvds_reg = PCH_LVDS;
1213 pp_reg = PP_CONTROL;
1217 val = I915_READ(pp_reg);
1218 if (!(val & PANEL_POWER_ON) ||
1219 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1225 WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1230 void assert_pipe(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1236 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 /* if we need the pipe A quirk it must be always on */
1240 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 reg = PIPECONF(cpu_transcoder);
1244 val = I915_READ(reg);
1245 cur_state = !!(val & PIPECONF_ENABLE);
1246 WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1276 /* Planes are fixed to pipes on ILK+ */
1277 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1278 reg = DSPCNTR(pipe);
1279 val = I915_READ(reg);
1280 WARN((val & DISPLAY_PLANE_ENABLE),
1281 "plane %c assertion failure, should be disabled but not\n",
1286 /* Need to check both planes against the pipe */
1287 for (i = 0; i < 2; i++) {
1289 val = I915_READ(reg);
1290 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1291 DISPPLANE_SEL_PIPE_SHIFT;
1292 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1293 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1294 plane_name(i), pipe_name(pipe));
1298 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1332 if ((val & DP_PORT_EN) == 0)
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1350 if ((val & PORT_ENABLE) == 0)
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
1354 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1366 if ((val & LVDS_PORT_EN) == 0)
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, int reg, u32 port_sel)
1397 u32 val = I915_READ(reg);
1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400 reg, pipe_name(pipe));
1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
1404 "IBX PCH dp port still using transcoder B\n");
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1410 u32 val = I915_READ(reg);
1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1416 && (val & SDVO_PIPE_B_SELECT),
1417 "IBX PCH hdmi port still using transcoder B\n");
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431 val = I915_READ(reg);
1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
1437 val = I915_READ(reg);
1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1456 * Note! This is for pre-ILK only.
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1460 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1465 /* No really, not for ILK+ */
1466 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1468 /* PLL is protected by panel, make sure we can write it */
1469 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1470 assert_panel_unlocked(dev_priv, pipe);
1473 val = I915_READ(reg);
1474 val |= DPLL_VCO_ENABLE;
1476 /* We do this three times for luck */
1477 I915_WRITE(reg, val);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, val);
1482 udelay(150); /* wait for warmup */
1483 I915_WRITE(reg, val);
1485 udelay(150); /* wait for warmup */
1489 * intel_disable_pll - disable a PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to disable
1493 * Disable the PLL for @pipe, making sure the pipe is off first.
1495 * Note! This is for pre-ILK only.
1497 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1502 /* Don't disable pipe A or pipe A PLLs if needed */
1503 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 /* Make sure the pipe isn't still relying on us */
1507 assert_pipe_disabled(dev_priv, pipe);
1510 val = I915_READ(reg);
1511 val &= ~DPLL_VCO_ENABLE;
1512 I915_WRITE(reg, val);
1518 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1520 unsigned long flags;
1522 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1523 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1525 DRM_ERROR("timeout waiting for SBI to become ready\n");
1529 I915_WRITE(SBI_ADDR,
1531 I915_WRITE(SBI_DATA,
1533 I915_WRITE(SBI_CTL_STAT,
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1539 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1544 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1548 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1550 unsigned long flags;
1553 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1554 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1556 DRM_ERROR("timeout waiting for SBI to become ready\n");
1560 I915_WRITE(SBI_ADDR,
1562 I915_WRITE(SBI_CTL_STAT,
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1568 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1572 value = I915_READ(SBI_DATA);
1575 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1580 * ironlake_enable_pch_pll - enable PCH PLL
1581 * @dev_priv: i915 private structure
1582 * @pipe: pipe PLL to enable
1584 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1585 * drives the transcoder clock.
1587 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1589 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1590 struct intel_pch_pll *pll;
1594 /* PCH PLLs only available on ILK, SNB and IVB */
1595 BUG_ON(dev_priv->info->gen < 5);
1596 pll = intel_crtc->pch_pll;
1600 if (WARN_ON(pll->refcount == 0))
1603 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1604 pll->pll_reg, pll->active, pll->on,
1605 intel_crtc->base.base.id);
1607 /* PCH refclock must be enabled first */
1608 assert_pch_refclk_enabled(dev_priv);
1610 if (pll->active++ && pll->on) {
1611 assert_pch_pll_enabled(dev_priv, pll, NULL);
1615 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618 val = I915_READ(reg);
1619 val |= DPLL_VCO_ENABLE;
1620 I915_WRITE(reg, val);
1627 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1629 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1630 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1634 /* PCH only available on ILK+ */
1635 BUG_ON(dev_priv->info->gen < 5);
1639 if (WARN_ON(pll->refcount == 0))
1642 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1643 pll->pll_reg, pll->active, pll->on,
1644 intel_crtc->base.base.id);
1646 if (WARN_ON(pll->active == 0)) {
1647 assert_pch_pll_disabled(dev_priv, pll, NULL);
1651 if (--pll->active) {
1652 assert_pch_pll_enabled(dev_priv, pll, NULL);
1656 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1658 /* Make sure transcoder isn't still depending on us */
1659 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662 val = I915_READ(reg);
1663 val &= ~DPLL_VCO_ENABLE;
1664 I915_WRITE(reg, val);
1671 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 struct drm_device *dev = dev_priv->dev;
1675 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1676 uint32_t reg, val, pipeconf_val;
1678 /* PCH only available on ILK+ */
1679 BUG_ON(dev_priv->info->gen < 5);
1681 /* Make sure PCH DPLL is enabled */
1682 assert_pch_pll_enabled(dev_priv,
1683 to_intel_crtc(crtc)->pch_pll,
1684 to_intel_crtc(crtc));
1686 /* FDI must be feeding us bits for PCH ports */
1687 assert_fdi_tx_enabled(dev_priv, pipe);
1688 assert_fdi_rx_enabled(dev_priv, pipe);
1690 if (HAS_PCH_CPT(dev)) {
1691 /* Workaround: Set the timing override bit before enabling the
1692 * pch transcoder. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1699 reg = TRANSCONF(pipe);
1700 val = I915_READ(reg);
1701 pipeconf_val = I915_READ(PIPECONF(pipe));
1703 if (HAS_PCH_IBX(dev_priv->dev)) {
1705 * make the BPC in transcoder be consistent with
1706 * that in pipeconf reg.
1708 val &= ~PIPE_BPC_MASK;
1709 val |= pipeconf_val & PIPE_BPC_MASK;
1712 val &= ~TRANS_INTERLACE_MASK;
1713 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1714 if (HAS_PCH_IBX(dev_priv->dev) &&
1715 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1716 val |= TRANS_LEGACY_INTERLACED_ILK;
1718 val |= TRANS_INTERLACED;
1720 val |= TRANS_PROGRESSIVE;
1722 I915_WRITE(reg, val | TRANS_ENABLE);
1723 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1724 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728 enum transcoder cpu_transcoder)
1730 u32 val, pipeconf_val;
1732 /* PCH only available on ILK+ */
1733 BUG_ON(dev_priv->info->gen < 5);
1735 /* FDI must be feeding us bits for PCH ports */
1736 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1737 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1739 /* Workaround: set timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
1741 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1742 I915_WRITE(_TRANSA_CHICKEN2, val);
1745 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1747 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748 PIPECONF_INTERLACED_ILK)
1749 val |= TRANS_INTERLACED;
1751 val |= TRANS_PROGRESSIVE;
1753 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1754 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1761 struct drm_device *dev = dev_priv->dev;
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1771 reg = TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1777 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1779 if (!HAS_PCH_IBX(dev)) {
1780 /* Workaround: Clear the timing override chicken bit again. */
1781 reg = TRANS_CHICKEN2(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784 I915_WRITE(reg, val);
1788 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1792 val = I915_READ(_TRANSACONF);
1793 val &= ~TRANS_ENABLE;
1794 I915_WRITE(_TRANSACONF, val);
1795 /* wait for PCH transcoder off, transcoder state */
1796 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1797 DRM_ERROR("Failed to disable PCH transcoder\n");
1799 /* Workaround: clear timing override bit. */
1800 val = I915_READ(_TRANSA_CHICKEN2);
1801 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1802 I915_WRITE(_TRANSA_CHICKEN2, val);
1806 * intel_enable_pipe - enable a pipe, asserting requirements
1807 * @dev_priv: i915 private structure
1808 * @pipe: pipe to enable
1809 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1811 * Enable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1814 * @pipe should be %PIPE_A or %PIPE_B.
1816 * Will wait until the pipe is actually running (i.e. first vblank) before
1819 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1822 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1828 * A pipe without a PLL won't actually be able to drive bits from
1829 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1832 if (!HAS_PCH_SPLIT(dev_priv->dev))
1833 assert_pll_enabled(dev_priv, pipe);
1836 /* if driving the PCH, we need FDI enabled */
1837 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1838 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1840 /* FIXME: assert CPU port conditions for SNB+ */
1843 reg = PIPECONF(cpu_transcoder);
1844 val = I915_READ(reg);
1845 if (val & PIPECONF_ENABLE)
1848 I915_WRITE(reg, val | PIPECONF_ENABLE);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1853 * intel_disable_pipe - disable a pipe, asserting requirements
1854 * @dev_priv: i915 private structure
1855 * @pipe: pipe to disable
1857 * Disable @pipe, making sure that various hardware specific requirements
1858 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860 * @pipe should be %PIPE_A or %PIPE_B.
1862 * Will wait until the pipe has shut down before returning.
1864 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1867 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1873 * Make sure planes won't keep trying to pump pixels to us,
1874 * or we might hang the display.
1876 assert_planes_disabled(dev_priv, pipe);
1878 /* Don't disable pipe A or pipe A PLLs if needed */
1879 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1882 reg = PIPECONF(cpu_transcoder);
1883 val = I915_READ(reg);
1884 if ((val & PIPECONF_ENABLE) == 0)
1887 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1888 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1892 * Plane regs are double buffered, going from enabled->disabled needs a
1893 * trigger in order to latch. The display address reg provides this.
1895 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1898 if (dev_priv->info->gen >= 4)
1899 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1905 * intel_enable_plane - enable a display plane on a given pipe
1906 * @dev_priv: i915 private structure
1907 * @plane: plane to enable
1908 * @pipe: pipe being fed
1910 * Enable @plane on @pipe, making sure that @pipe is running first.
1912 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1913 enum plane plane, enum pipe pipe)
1918 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1919 assert_pipe_enabled(dev_priv, pipe);
1921 reg = DSPCNTR(plane);
1922 val = I915_READ(reg);
1923 if (val & DISPLAY_PLANE_ENABLE)
1926 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1927 intel_flush_display_plane(dev_priv, plane);
1928 intel_wait_for_vblank(dev_priv->dev, pipe);
1932 * intel_disable_plane - disable a display plane
1933 * @dev_priv: i915 private structure
1934 * @plane: plane to disable
1935 * @pipe: pipe consuming the data
1937 * Disable @plane; should be an independent operation.
1939 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1940 enum plane plane, enum pipe pipe)
1945 reg = DSPCNTR(plane);
1946 val = I915_READ(reg);
1947 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1950 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1951 intel_flush_display_plane(dev_priv, plane);
1952 intel_wait_for_vblank(dev_priv->dev, pipe);
1956 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1957 struct drm_i915_gem_object *obj,
1958 struct intel_ring_buffer *pipelined)
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1964 switch (obj->tiling_mode) {
1965 case I915_TILING_NONE:
1966 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1967 alignment = 128 * 1024;
1968 else if (INTEL_INFO(dev)->gen >= 4)
1969 alignment = 4 * 1024;
1971 alignment = 64 * 1024;
1974 /* pin() will align the object as required by fence */
1978 /* FIXME: Is this true? */
1979 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1985 dev_priv->mm.interruptible = false;
1986 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1988 goto err_interruptible;
1990 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1991 * fence, whereas 965+ only requires a fence if using
1992 * framebuffer compression. For simplicity, we always install
1993 * a fence as the cost is not that onerous.
1995 ret = i915_gem_object_get_fence(obj);
1999 i915_gem_object_pin_fence(obj);
2001 dev_priv->mm.interruptible = true;
2005 i915_gem_object_unpin(obj);
2007 dev_priv->mm.interruptible = true;
2011 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013 i915_gem_object_unpin_fence(obj);
2014 i915_gem_object_unpin(obj);
2017 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2018 * is assumed to be a power-of-two. */
2019 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2023 int tile_rows, tiles;
2027 tiles = *x / (512/bpp);
2030 return tile_rows * pitch * 8 + tiles * 4096;
2033 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2039 struct intel_framebuffer *intel_fb;
2040 struct drm_i915_gem_object *obj;
2041 int plane = intel_crtc->plane;
2042 unsigned long linear_offset;
2051 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2055 intel_fb = to_intel_framebuffer(fb);
2056 obj = intel_fb->obj;
2058 reg = DSPCNTR(plane);
2059 dspcntr = I915_READ(reg);
2060 /* Mask out pixel format bits in case we change it */
2061 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2062 switch (fb->pixel_format) {
2064 dspcntr |= DISPPLANE_8BPP;
2066 case DRM_FORMAT_XRGB1555:
2067 case DRM_FORMAT_ARGB1555:
2068 dspcntr |= DISPPLANE_BGRX555;
2070 case DRM_FORMAT_RGB565:
2071 dspcntr |= DISPPLANE_BGRX565;
2073 case DRM_FORMAT_XRGB8888:
2074 case DRM_FORMAT_ARGB8888:
2075 dspcntr |= DISPPLANE_BGRX888;
2077 case DRM_FORMAT_XBGR8888:
2078 case DRM_FORMAT_ABGR8888:
2079 dspcntr |= DISPPLANE_RGBX888;
2081 case DRM_FORMAT_XRGB2101010:
2082 case DRM_FORMAT_ARGB2101010:
2083 dspcntr |= DISPPLANE_BGRX101010;
2085 case DRM_FORMAT_XBGR2101010:
2086 case DRM_FORMAT_ABGR2101010:
2087 dspcntr |= DISPPLANE_RGBX101010;
2090 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2094 if (INTEL_INFO(dev)->gen >= 4) {
2095 if (obj->tiling_mode != I915_TILING_NONE)
2096 dspcntr |= DISPPLANE_TILED;
2098 dspcntr &= ~DISPPLANE_TILED;
2101 I915_WRITE(reg, dspcntr);
2103 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2105 if (INTEL_INFO(dev)->gen >= 4) {
2106 intel_crtc->dspaddr_offset =
2107 intel_gen4_compute_offset_xtiled(&x, &y,
2108 fb->bits_per_pixel / 8,
2110 linear_offset -= intel_crtc->dspaddr_offset;
2112 intel_crtc->dspaddr_offset = linear_offset;
2115 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2116 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2117 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2118 if (INTEL_INFO(dev)->gen >= 4) {
2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
2120 obj->gtt_offset + intel_crtc->dspaddr_offset);
2121 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2122 I915_WRITE(DSPLINOFF(plane), linear_offset);
2124 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2130 static int ironlake_update_plane(struct drm_crtc *crtc,
2131 struct drm_framebuffer *fb, int x, int y)
2133 struct drm_device *dev = crtc->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136 struct intel_framebuffer *intel_fb;
2137 struct drm_i915_gem_object *obj;
2138 int plane = intel_crtc->plane;
2139 unsigned long linear_offset;
2149 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2153 intel_fb = to_intel_framebuffer(fb);
2154 obj = intel_fb->obj;
2156 reg = DSPCNTR(plane);
2157 dspcntr = I915_READ(reg);
2158 /* Mask out pixel format bits in case we change it */
2159 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2160 switch (fb->pixel_format) {
2162 dspcntr |= DISPPLANE_8BPP;
2164 case DRM_FORMAT_RGB565:
2165 dspcntr |= DISPPLANE_BGRX565;
2167 case DRM_FORMAT_XRGB8888:
2168 case DRM_FORMAT_ARGB8888:
2169 dspcntr |= DISPPLANE_BGRX888;
2171 case DRM_FORMAT_XBGR8888:
2172 case DRM_FORMAT_ABGR8888:
2173 dspcntr |= DISPPLANE_RGBX888;
2175 case DRM_FORMAT_XRGB2101010:
2176 case DRM_FORMAT_ARGB2101010:
2177 dspcntr |= DISPPLANE_BGRX101010;
2179 case DRM_FORMAT_XBGR2101010:
2180 case DRM_FORMAT_ABGR2101010:
2181 dspcntr |= DISPPLANE_RGBX101010;
2184 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2188 if (obj->tiling_mode != I915_TILING_NONE)
2189 dspcntr |= DISPPLANE_TILED;
2191 dspcntr &= ~DISPPLANE_TILED;
2194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196 I915_WRITE(reg, dspcntr);
2198 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2199 intel_crtc->dspaddr_offset =
2200 intel_gen4_compute_offset_xtiled(&x, &y,
2201 fb->bits_per_pixel / 8,
2203 linear_offset -= intel_crtc->dspaddr_offset;
2205 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2206 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208 I915_MODIFY_DISPBASE(DSPSURF(plane),
2209 obj->gtt_offset + intel_crtc->dspaddr_offset);
2210 if (IS_HASWELL(dev)) {
2211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
2231 intel_increase_pllclock(crtc);
2233 return dev_priv->display.update_plane(crtc, fb, x, y);
2237 intel_finish_fb(struct drm_framebuffer *old_fb)
2239 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 bool was_interruptible = dev_priv->mm.interruptible;
2244 wait_event(dev_priv->pending_flip_queue,
2245 atomic_read(&dev_priv->mm.wedged) ||
2246 atomic_read(&obj->pending_flip) == 0);
2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_finish_gpu(obj);
2258 dev_priv->mm.interruptible = was_interruptible;
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 struct drm_device *dev = crtc->dev;
2266 struct drm_i915_master_private *master_priv;
2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269 if (!dev->primary->master)
2272 master_priv = dev->primary->master->driver_priv;
2273 if (!master_priv->sarea_priv)
2276 switch (intel_crtc->pipe) {
2278 master_priv->sarea_priv->pipeA_x = x;
2279 master_priv->sarea_priv->pipeA_y = y;
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2291 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2292 struct drm_framebuffer *fb)
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 struct drm_framebuffer *old_fb;
2302 DRM_ERROR("No FB bound\n");
2306 if(intel_crtc->plane > dev_priv->num_pipe) {
2307 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2309 dev_priv->num_pipe);
2313 mutex_lock(&dev->struct_mutex);
2314 ret = intel_pin_and_fence_fb_obj(dev,
2315 to_intel_framebuffer(fb)->obj,
2318 mutex_unlock(&dev->struct_mutex);
2319 DRM_ERROR("pin & fence failed\n");
2324 intel_finish_fb(crtc->fb);
2326 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2328 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2329 mutex_unlock(&dev->struct_mutex);
2330 DRM_ERROR("failed to update base address\n");
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2344 intel_update_fbc(dev);
2345 mutex_unlock(&dev->struct_mutex);
2347 intel_crtc_update_sarea_pos(crtc, x, y);
2352 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2359 dpa_ctl = I915_READ(DP_A);
2360 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2362 if (clock < 200000) {
2364 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2365 /* workaround for 160Mhz:
2366 1) program 0x4600c bits 15:0 = 0x8124
2367 2) program 0x46010 bit 0 = 1
2368 3) program 0x46034 bit 24 = 1
2369 4) program 0x64000 bit 14 = 1
2371 temp = I915_READ(0x4600c);
2373 I915_WRITE(0x4600c, temp | 0x8124);
2375 temp = I915_READ(0x46010);
2376 I915_WRITE(0x46010, temp | 1);
2378 temp = I915_READ(0x46034);
2379 I915_WRITE(0x46034, temp | (1 << 24));
2381 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2383 I915_WRITE(DP_A, dpa_ctl);
2389 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2391 struct drm_device *dev = crtc->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 int pipe = intel_crtc->pipe;
2397 /* enable normal train */
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 if (IS_IVYBRIDGE(dev)) {
2401 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2402 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2407 I915_WRITE(reg, temp);
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 if (HAS_PCH_CPT(dev)) {
2412 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2413 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_NONE;
2418 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2420 /* wait one idle pattern time */
2424 /* IVB wants error correction enabled */
2425 if (IS_IVYBRIDGE(dev))
2426 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2427 FDI_FE_ERRC_ENABLE);
2430 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 u32 flags = I915_READ(SOUTH_CHICKEN1);
2435 flags |= FDI_PHASE_SYNC_OVR(pipe);
2436 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2437 flags |= FDI_PHASE_SYNC_EN(pipe);
2438 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2439 POSTING_READ(SOUTH_CHICKEN1);
2442 static void ivb_modeset_global_resources(struct drm_device *dev)
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_crtc *pipe_B_crtc =
2446 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2447 struct intel_crtc *pipe_C_crtc =
2448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2451 /* When everything is off disable fdi C so that we could enable fdi B
2452 * with all lanes. XXX: This misses the case where a pipe is not using
2453 * any pch resources and so doesn't need any fdi lanes. */
2454 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2455 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2456 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2458 temp = I915_READ(SOUTH_CHICKEN1);
2459 temp &= ~FDI_BC_BIFURCATION_SELECT;
2460 DRM_DEBUG_KMS("disabling fdi C rx\n");
2461 I915_WRITE(SOUTH_CHICKEN1, temp);
2465 /* The FDI link training functions for ILK/Ibexpeak. */
2466 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 int pipe = intel_crtc->pipe;
2472 int plane = intel_crtc->plane;
2473 u32 reg, temp, tries;
2475 /* FDI needs bits from pipe & plane first */
2476 assert_pipe_enabled(dev_priv, pipe);
2477 assert_plane_enabled(dev_priv, plane);
2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
2485 I915_WRITE(reg, temp);
2489 /* enable CPU FDI TX and PCH FDI RX */
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2494 temp &= ~FDI_LINK_TRAIN_NONE;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507 /* Ironlake workaround, enable clock pointer after FDI enable*/
2508 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2509 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2510 FDI_RX_PHASE_SYNC_POINTER_EN);
2512 reg = FDI_RX_IIR(pipe);
2513 for (tries = 0; tries < 5; tries++) {
2514 temp = I915_READ(reg);
2515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517 if ((temp & FDI_RX_BIT_LOCK)) {
2518 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524 DRM_ERROR("FDI train 1 fail!\n");
2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
2531 I915_WRITE(reg, temp);
2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 I915_WRITE(reg, temp);
2542 reg = FDI_RX_IIR(pipe);
2543 for (tries = 0; tries < 5; tries++) {
2544 temp = I915_READ(reg);
2545 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547 if (temp & FDI_RX_SYMBOL_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549 DRM_DEBUG_KMS("FDI train 2 done.\n");
2554 DRM_ERROR("FDI train 2 fail!\n");
2556 DRM_DEBUG_KMS("FDI train done\n");
2560 static const int snb_b_fdi_train_param[] = {
2561 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2562 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2563 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2564 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2567 /* The FDI link training functions for SNB/Cougarpoint. */
2568 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2573 int pipe = intel_crtc->pipe;
2574 u32 reg, temp, i, retry;
2576 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2578 reg = FDI_RX_IMR(pipe);
2579 temp = I915_READ(reg);
2580 temp &= ~FDI_RX_SYMBOL_LOCK;
2581 temp &= ~FDI_RX_BIT_LOCK;
2582 I915_WRITE(reg, temp);
2587 /* enable CPU FDI TX and PCH FDI RX */
2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
2591 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2599 I915_WRITE(FDI_RX_MISC(pipe),
2600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2602 reg = FDI_RX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 if (HAS_PCH_CPT(dev)) {
2605 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2608 temp &= ~FDI_LINK_TRAIN_NONE;
2609 temp |= FDI_LINK_TRAIN_PATTERN_1;
2611 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2616 cpt_phase_pointer_enable(dev, pipe);
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2628 for (retry = 0; retry < 5; retry++) {
2629 reg = FDI_RX_IIR(pipe);
2630 temp = I915_READ(reg);
2631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632 if (temp & FDI_RX_BIT_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2634 DRM_DEBUG_KMS("FDI train 1 done.\n");
2643 DRM_ERROR("FDI train 1 fail!\n");
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2653 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2655 I915_WRITE(reg, temp);
2657 reg = FDI_RX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 if (HAS_PCH_CPT(dev)) {
2660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2663 temp &= ~FDI_LINK_TRAIN_NONE;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2;
2666 I915_WRITE(reg, temp);
2671 for (i = 0; i < 4; i++) {
2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= snb_b_fdi_train_param[i];
2676 I915_WRITE(reg, temp);
2681 for (retry = 0; retry < 5; retry++) {
2682 reg = FDI_RX_IIR(pipe);
2683 temp = I915_READ(reg);
2684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685 if (temp & FDI_RX_SYMBOL_LOCK) {
2686 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687 DRM_DEBUG_KMS("FDI train 2 done.\n");
2696 DRM_ERROR("FDI train 2 fail!\n");
2698 DRM_DEBUG_KMS("FDI train done.\n");
2701 /* Manual link training for Ivy Bridge A0 parts */
2702 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2710 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2712 reg = FDI_RX_IMR(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~FDI_RX_SYMBOL_LOCK;
2715 temp &= ~FDI_RX_BIT_LOCK;
2716 I915_WRITE(reg, temp);
2721 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2722 I915_READ(FDI_RX_IIR(pipe)));
2724 /* enable CPU FDI TX and PCH FDI RX */
2725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2736 I915_WRITE(FDI_RX_MISC(pipe),
2737 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_AUTO;
2742 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2743 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2744 temp |= FDI_COMPOSITE_SYNC;
2745 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2750 cpt_phase_pointer_enable(dev, pipe);
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= snb_b_fdi_train_param[i];
2757 I915_WRITE(reg, temp);
2762 reg = FDI_RX_IIR(pipe);
2763 temp = I915_READ(reg);
2764 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2766 if (temp & FDI_RX_BIT_LOCK ||
2767 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2768 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2769 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2774 DRM_ERROR("FDI train 1 fail!\n");
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2780 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2782 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2783 I915_WRITE(reg, temp);
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2789 I915_WRITE(reg, temp);
2794 for (i = 0; i < 4; i++) {
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2798 temp |= snb_b_fdi_train_param[i];
2799 I915_WRITE(reg, temp);
2804 reg = FDI_RX_IIR(pipe);
2805 temp = I915_READ(reg);
2806 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2808 if (temp & FDI_RX_SYMBOL_LOCK) {
2809 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2810 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2815 DRM_ERROR("FDI train 2 fail!\n");
2817 DRM_DEBUG_KMS("FDI train done.\n");
2820 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2822 struct drm_device *dev = intel_crtc->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 int pipe = intel_crtc->pipe;
2828 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~((0x7 << 19) | (0x7 << 16));
2832 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2833 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2834 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2839 /* Switch from Rawclk to PCDclk */
2840 temp = I915_READ(reg);
2841 I915_WRITE(reg, temp | FDI_PCDCLK);
2846 /* On Haswell, the PLL configuration for ports and pipes is handled
2847 * separately, as part of DDI setup */
2848 if (!IS_HASWELL(dev)) {
2849 /* Enable CPU FDI TX PLL, always on for Ironlake */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2853 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2861 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2885 /* Wait for the clocks to turn off. */
2890 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 u32 flags = I915_READ(SOUTH_CHICKEN1);
2895 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2896 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2897 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2898 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2899 POSTING_READ(SOUTH_CHICKEN1);
2901 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2909 /* disable CPU FDI tx and PCH FDI rx */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2915 reg = FDI_RX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 temp &= ~(0x7 << 16);
2918 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2919 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2924 /* Ironlake workaround, disable clock pointer after downing FDI */
2925 if (HAS_PCH_IBX(dev)) {
2926 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2927 I915_WRITE(FDI_RX_CHICKEN(pipe),
2928 I915_READ(FDI_RX_CHICKEN(pipe) &
2929 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2930 } else if (HAS_PCH_CPT(dev)) {
2931 cpt_phase_pointer_disable(dev, pipe);
2934 /* still set train pattern 1 */
2935 reg = FDI_TX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 temp &= ~FDI_LINK_TRAIN_NONE;
2938 temp |= FDI_LINK_TRAIN_PATTERN_1;
2939 I915_WRITE(reg, temp);
2941 reg = FDI_RX_CTL(pipe);
2942 temp = I915_READ(reg);
2943 if (HAS_PCH_CPT(dev)) {
2944 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2947 temp &= ~FDI_LINK_TRAIN_NONE;
2948 temp |= FDI_LINK_TRAIN_PATTERN_1;
2950 /* BPC in FDI rx is consistent with that in PIPECONF */
2951 temp &= ~(0x07 << 16);
2952 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2953 I915_WRITE(reg, temp);
2959 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 unsigned long flags;
2966 if (atomic_read(&dev_priv->mm.wedged))
2969 spin_lock_irqsave(&dev->event_lock, flags);
2970 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2971 spin_unlock_irqrestore(&dev->event_lock, flags);
2976 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2978 struct drm_device *dev = crtc->dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2981 if (crtc->fb == NULL)
2984 wait_event(dev_priv->pending_flip_queue,
2985 !intel_crtc_has_pending_flip(crtc));
2987 mutex_lock(&dev->struct_mutex);
2988 intel_finish_fb(crtc->fb);
2989 mutex_unlock(&dev->struct_mutex);
2992 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2994 struct drm_device *dev = crtc->dev;
2995 struct intel_encoder *intel_encoder;
2998 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2999 * must be driven by its own crtc; no sharing is possible.
3001 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3002 switch (intel_encoder->type) {
3003 case INTEL_OUTPUT_EDP:
3004 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3013 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3015 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3018 /* Program iCLKIP clock to the desired frequency */
3019 static void lpt_program_iclkip(struct drm_crtc *crtc)
3021 struct drm_device *dev = crtc->dev;
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3026 /* It is necessary to ungate the pixclk gate prior to programming
3027 * the divisors, and gate it back when it is done.
3029 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3031 /* Disable SSCCTL */
3032 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3033 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3034 SBI_SSCCTL_DISABLE);
3036 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3037 if (crtc->mode.clock == 20000) {
3042 /* The iCLK virtual clock root frequency is in MHz,
3043 * but the crtc->mode.clock in in KHz. To get the divisors,
3044 * it is necessary to divide one by another, so we
3045 * convert the virtual clock precision to KHz here for higher
3048 u32 iclk_virtual_root_freq = 172800 * 1000;
3049 u32 iclk_pi_range = 64;
3050 u32 desired_divisor, msb_divisor_value, pi_value;
3052 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3053 msb_divisor_value = desired_divisor / iclk_pi_range;
3054 pi_value = desired_divisor % iclk_pi_range;
3057 divsel = msb_divisor_value - 2;
3058 phaseinc = pi_value;
3061 /* This should not happen with any sane values */
3062 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3063 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3064 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3065 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3067 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3074 /* Program SSCDIVINTPHASE6 */
3075 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3076 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3077 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3078 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3079 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3080 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3081 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3083 intel_sbi_write(dev_priv,
3084 SBI_SSCDIVINTPHASE6,
3087 /* Program SSCAUXDIV */
3088 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3089 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3090 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3091 intel_sbi_write(dev_priv,
3096 /* Enable modulator and associated divider */
3097 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3098 temp &= ~SBI_SSCCTL_DISABLE;
3099 intel_sbi_write(dev_priv,
3103 /* Wait for initialization time */
3106 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3110 * Enable PCH resources required for PCH ports:
3112 * - FDI training & RX/TX
3113 * - update transcoder timings
3114 * - DP transcoding bits
3117 static void ironlake_pch_enable(struct drm_crtc *crtc)
3119 struct drm_device *dev = crtc->dev;
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3122 int pipe = intel_crtc->pipe;
3125 assert_transcoder_disabled(dev_priv, pipe);
3127 /* Write the TU size bits before fdi link training, so that error
3128 * detection works. */
3129 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3130 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3132 /* For PCH output, training FDI link */
3133 dev_priv->display.fdi_link_train(crtc);
3135 /* XXX: pch pll's can be enabled any time before we enable the PCH
3136 * transcoder, and we actually should do this to not upset any PCH
3137 * transcoder that already use the clock when we share it.
3139 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3140 * unconditionally resets the pll - we need that to have the right LVDS
3141 * enable sequence. */
3142 ironlake_enable_pch_pll(intel_crtc);
3144 if (HAS_PCH_CPT(dev)) {
3147 temp = I915_READ(PCH_DPLL_SEL);
3151 temp |= TRANSA_DPLL_ENABLE;
3152 sel = TRANSA_DPLLB_SEL;
3155 temp |= TRANSB_DPLL_ENABLE;
3156 sel = TRANSB_DPLLB_SEL;
3159 temp |= TRANSC_DPLL_ENABLE;
3160 sel = TRANSC_DPLLB_SEL;
3163 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3167 I915_WRITE(PCH_DPLL_SEL, temp);
3170 /* set transcoder timing, panel must allow it */
3171 assert_panel_unlocked(dev_priv, pipe);
3172 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3173 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3174 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3176 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3177 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3178 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3179 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3181 intel_fdi_normal_train(crtc);
3183 /* For PCH DP, enable TRANS_DP_CTL */
3184 if (HAS_PCH_CPT(dev) &&
3185 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3186 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3187 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3188 reg = TRANS_DP_CTL(pipe);
3189 temp = I915_READ(reg);
3190 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3191 TRANS_DP_SYNC_MASK |
3193 temp |= (TRANS_DP_OUTPUT_ENABLE |
3194 TRANS_DP_ENH_FRAMING);
3195 temp |= bpc << 9; /* same format but at 11:9 */
3197 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3198 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3199 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3200 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3202 switch (intel_trans_dp_port_sel(crtc)) {
3204 temp |= TRANS_DP_PORT_SEL_B;
3207 temp |= TRANS_DP_PORT_SEL_C;
3210 temp |= TRANS_DP_PORT_SEL_D;
3216 I915_WRITE(reg, temp);
3219 ironlake_enable_pch_transcoder(dev_priv, pipe);
3222 static void lpt_pch_enable(struct drm_crtc *crtc)
3224 struct drm_device *dev = crtc->dev;
3225 struct drm_i915_private *dev_priv = dev->dev_private;
3226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3227 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3229 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3231 lpt_program_iclkip(crtc);
3233 /* Set transcoder timing. */
3234 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3235 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3236 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3238 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3239 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3240 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3241 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3243 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3246 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3248 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3253 if (pll->refcount == 0) {
3254 WARN(1, "bad PCH PLL refcount\n");
3259 intel_crtc->pch_pll = NULL;
3262 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3264 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3265 struct intel_pch_pll *pll;
3268 pll = intel_crtc->pch_pll;
3270 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3271 intel_crtc->base.base.id, pll->pll_reg);
3275 if (HAS_PCH_IBX(dev_priv->dev)) {
3276 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3277 i = intel_crtc->pipe;
3278 pll = &dev_priv->pch_plls[i];
3280 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3281 intel_crtc->base.base.id, pll->pll_reg);
3286 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3287 pll = &dev_priv->pch_plls[i];
3289 /* Only want to check enabled timings first */
3290 if (pll->refcount == 0)
3293 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3294 fp == I915_READ(pll->fp0_reg)) {
3295 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3296 intel_crtc->base.base.id,
3297 pll->pll_reg, pll->refcount, pll->active);
3303 /* Ok no matching timings, maybe there's a free one? */
3304 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3305 pll = &dev_priv->pch_plls[i];
3306 if (pll->refcount == 0) {
3307 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3308 intel_crtc->base.base.id, pll->pll_reg);
3316 intel_crtc->pch_pll = pll;
3318 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3319 prepare: /* separate function? */
3320 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3322 /* Wait for the clocks to stabilize before rewriting the regs */
3323 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3324 POSTING_READ(pll->pll_reg);
3327 I915_WRITE(pll->fp0_reg, fp);
3328 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3333 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 int dslreg = PIPEDSL(pipe);
3339 temp = I915_READ(dslreg);
3341 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3342 if (wait_for(I915_READ(dslreg) != temp, 5))
3343 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3347 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352 struct intel_encoder *encoder;
3353 int pipe = intel_crtc->pipe;
3354 int plane = intel_crtc->plane;
3358 WARN_ON(!crtc->enabled);
3360 if (intel_crtc->active)
3363 intel_crtc->active = true;
3364 intel_update_watermarks(dev);
3366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3367 temp = I915_READ(PCH_LVDS);
3368 if ((temp & LVDS_PORT_EN) == 0)
3369 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3372 is_pch_port = ironlake_crtc_driving_pch(crtc);
3375 /* Note: FDI PLL enabling _must_ be done before we enable the
3376 * cpu pipes, hence this is separate from all the other fdi/pch
3378 ironlake_fdi_pll_enable(intel_crtc);
3380 assert_fdi_tx_disabled(dev_priv, pipe);
3381 assert_fdi_rx_disabled(dev_priv, pipe);
3384 for_each_encoder_on_crtc(dev, crtc, encoder)
3385 if (encoder->pre_enable)
3386 encoder->pre_enable(encoder);
3388 /* Enable panel fitting for LVDS */
3389 if (dev_priv->pch_pf_size &&
3390 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3391 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3392 /* Force use of hard-coded filter coefficients
3393 * as some pre-programmed values are broken,
3396 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3397 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3398 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3402 * On ILK+ LUT must be loaded before the pipe is running but with
3405 intel_crtc_load_lut(crtc);
3407 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3408 intel_enable_plane(dev_priv, plane, pipe);
3411 ironlake_pch_enable(crtc);
3413 mutex_lock(&dev->struct_mutex);
3414 intel_update_fbc(dev);
3415 mutex_unlock(&dev->struct_mutex);
3417 intel_crtc_update_cursor(crtc, true);
3419 for_each_encoder_on_crtc(dev, crtc, encoder)
3420 encoder->enable(encoder);
3422 if (HAS_PCH_CPT(dev))
3423 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3426 * There seems to be a race in PCH platform hw (at least on some
3427 * outputs) where an enabled pipe still completes any pageflip right
3428 * away (as if the pipe is off) instead of waiting for vblank. As soon
3429 * as the first vblank happend, everything works as expected. Hence just
3430 * wait for one vblank before returning to avoid strange things
3433 intel_wait_for_vblank(dev, intel_crtc->pipe);
3436 static void haswell_crtc_enable(struct drm_crtc *crtc)
3438 struct drm_device *dev = crtc->dev;
3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3441 struct intel_encoder *encoder;
3442 int pipe = intel_crtc->pipe;
3443 int plane = intel_crtc->plane;
3446 WARN_ON(!crtc->enabled);
3448 if (intel_crtc->active)
3451 intel_crtc->active = true;
3452 intel_update_watermarks(dev);
3454 is_pch_port = haswell_crtc_driving_pch(crtc);
3457 dev_priv->display.fdi_link_train(crtc);
3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->pre_enable)
3461 encoder->pre_enable(encoder);
3463 intel_ddi_enable_pipe_clock(intel_crtc);
3465 /* Enable panel fitting for eDP */
3466 if (dev_priv->pch_pf_size &&
3467 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3468 /* Force use of hard-coded filter coefficients
3469 * as some pre-programmed values are broken,
3472 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3473 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3474 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3478 * On ILK+ LUT must be loaded before the pipe is running but with
3481 intel_crtc_load_lut(crtc);
3483 intel_ddi_set_pipe_settings(crtc);
3484 intel_ddi_enable_pipe_func(crtc);
3486 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3487 intel_enable_plane(dev_priv, plane, pipe);
3490 lpt_pch_enable(crtc);
3492 mutex_lock(&dev->struct_mutex);
3493 intel_update_fbc(dev);
3494 mutex_unlock(&dev->struct_mutex);
3496 intel_crtc_update_cursor(crtc, true);
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->enable(encoder);
3502 * There seems to be a race in PCH platform hw (at least on some
3503 * outputs) where an enabled pipe still completes any pageflip right
3504 * away (as if the pipe is off) instead of waiting for vblank. As soon
3505 * as the first vblank happend, everything works as expected. Hence just
3506 * wait for one vblank before returning to avoid strange things
3509 intel_wait_for_vblank(dev, intel_crtc->pipe);
3512 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 struct intel_encoder *encoder;
3518 int pipe = intel_crtc->pipe;
3519 int plane = intel_crtc->plane;
3523 if (!intel_crtc->active)
3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 encoder->disable(encoder);
3529 intel_crtc_wait_for_pending_flips(crtc);
3530 drm_vblank_off(dev, pipe);
3531 intel_crtc_update_cursor(crtc, false);
3533 intel_disable_plane(dev_priv, plane, pipe);
3535 if (dev_priv->cfb_plane == plane)
3536 intel_disable_fbc(dev);
3538 intel_disable_pipe(dev_priv, pipe);
3541 I915_WRITE(PF_CTL(pipe), 0);
3542 I915_WRITE(PF_WIN_SZ(pipe), 0);
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3548 ironlake_fdi_disable(crtc);
3550 ironlake_disable_pch_transcoder(dev_priv, pipe);
3552 if (HAS_PCH_CPT(dev)) {
3553 /* disable TRANS_DP_CTL */
3554 reg = TRANS_DP_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3557 temp |= TRANS_DP_PORT_SEL_NONE;
3558 I915_WRITE(reg, temp);
3560 /* disable DPLL_SEL */
3561 temp = I915_READ(PCH_DPLL_SEL);
3564 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3567 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3570 /* C shares PLL A or B */
3571 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3576 I915_WRITE(PCH_DPLL_SEL, temp);
3579 /* disable PCH DPLL */
3580 intel_disable_pch_pll(intel_crtc);
3582 ironlake_fdi_pll_disable(intel_crtc);
3584 intel_crtc->active = false;
3585 intel_update_watermarks(dev);
3587 mutex_lock(&dev->struct_mutex);
3588 intel_update_fbc(dev);
3589 mutex_unlock(&dev->struct_mutex);
3592 static void haswell_crtc_disable(struct drm_crtc *crtc)
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 struct intel_encoder *encoder;
3598 int pipe = intel_crtc->pipe;
3599 int plane = intel_crtc->plane;
3600 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3603 if (!intel_crtc->active)
3606 is_pch_port = haswell_crtc_driving_pch(crtc);
3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->disable(encoder);
3611 intel_crtc_wait_for_pending_flips(crtc);
3612 drm_vblank_off(dev, pipe);
3613 intel_crtc_update_cursor(crtc, false);
3615 intel_disable_plane(dev_priv, plane, pipe);
3617 if (dev_priv->cfb_plane == plane)
3618 intel_disable_fbc(dev);
3620 intel_disable_pipe(dev_priv, pipe);
3622 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3625 I915_WRITE(PF_CTL(pipe), 0);
3626 I915_WRITE(PF_WIN_SZ(pipe), 0);
3628 intel_ddi_disable_pipe_clock(intel_crtc);
3630 for_each_encoder_on_crtc(dev, crtc, encoder)
3631 if (encoder->post_disable)
3632 encoder->post_disable(encoder);
3635 ironlake_fdi_disable(crtc);
3636 lpt_disable_pch_transcoder(dev_priv);
3637 ironlake_fdi_pll_disable(intel_crtc);
3640 intel_crtc->active = false;
3641 intel_update_watermarks(dev);
3643 mutex_lock(&dev->struct_mutex);
3644 intel_update_fbc(dev);
3645 mutex_unlock(&dev->struct_mutex);
3648 static void ironlake_crtc_off(struct drm_crtc *crtc)
3650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3651 intel_put_pch_pll(intel_crtc);
3654 static void haswell_crtc_off(struct drm_crtc *crtc)
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3658 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3659 * start using it. */
3660 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3662 intel_ddi_put_crtc_pll(crtc);
3665 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3667 if (!enable && intel_crtc->overlay) {
3668 struct drm_device *dev = intel_crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3671 mutex_lock(&dev->struct_mutex);
3672 dev_priv->mm.interruptible = false;
3673 (void) intel_overlay_switch_off(intel_crtc->overlay);
3674 dev_priv->mm.interruptible = true;
3675 mutex_unlock(&dev->struct_mutex);
3678 /* Let userspace switch the overlay on again. In most cases userspace
3679 * has to recompute where to put it anyway.
3683 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3685 struct drm_device *dev = crtc->dev;
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688 struct intel_encoder *encoder;
3689 int pipe = intel_crtc->pipe;
3690 int plane = intel_crtc->plane;
3692 WARN_ON(!crtc->enabled);
3694 if (intel_crtc->active)
3697 intel_crtc->active = true;
3698 intel_update_watermarks(dev);
3700 intel_enable_pll(dev_priv, pipe);
3701 intel_enable_pipe(dev_priv, pipe, false);
3702 intel_enable_plane(dev_priv, plane, pipe);
3704 intel_crtc_load_lut(crtc);
3705 intel_update_fbc(dev);
3707 /* Give the overlay scaler a chance to enable if it's on this pipe */
3708 intel_crtc_dpms_overlay(intel_crtc, true);
3709 intel_crtc_update_cursor(crtc, true);
3711 for_each_encoder_on_crtc(dev, crtc, encoder)
3712 encoder->enable(encoder);
3715 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3717 struct drm_device *dev = crtc->dev;
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3720 struct intel_encoder *encoder;
3721 int pipe = intel_crtc->pipe;
3722 int plane = intel_crtc->plane;
3725 if (!intel_crtc->active)
3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->disable(encoder);
3731 /* Give the overlay scaler a chance to disable if it's on this pipe */
3732 intel_crtc_wait_for_pending_flips(crtc);
3733 drm_vblank_off(dev, pipe);
3734 intel_crtc_dpms_overlay(intel_crtc, false);
3735 intel_crtc_update_cursor(crtc, false);
3737 if (dev_priv->cfb_plane == plane)
3738 intel_disable_fbc(dev);
3740 intel_disable_plane(dev_priv, plane, pipe);
3741 intel_disable_pipe(dev_priv, pipe);
3742 intel_disable_pll(dev_priv, pipe);
3744 intel_crtc->active = false;
3745 intel_update_fbc(dev);
3746 intel_update_watermarks(dev);
3749 static void i9xx_crtc_off(struct drm_crtc *crtc)
3753 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_master_private *master_priv;
3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759 int pipe = intel_crtc->pipe;
3761 if (!dev->primary->master)
3764 master_priv = dev->primary->master->driver_priv;
3765 if (!master_priv->sarea_priv)
3770 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3771 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3775 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3784 * Sets the power management mode of the pipe and plane.
3786 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3788 struct drm_device *dev = crtc->dev;
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_encoder *intel_encoder;
3791 bool enable = false;
3793 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3794 enable |= intel_encoder->connectors_active;
3797 dev_priv->display.crtc_enable(crtc);
3799 dev_priv->display.crtc_disable(crtc);
3801 intel_crtc_update_sarea(crtc, enable);
3804 static void intel_crtc_noop(struct drm_crtc *crtc)
3808 static void intel_crtc_disable(struct drm_crtc *crtc)
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_connector *connector;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3814 /* crtc should still be enabled when we disable it. */
3815 WARN_ON(!crtc->enabled);
3817 dev_priv->display.crtc_disable(crtc);
3818 intel_crtc_update_sarea(crtc, false);
3819 dev_priv->display.off(crtc);
3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3825 mutex_lock(&dev->struct_mutex);
3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3827 mutex_unlock(&dev->struct_mutex);
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3836 if (connector->encoder->crtc != crtc)
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
3844 void intel_modeset_disable(struct drm_device *dev)
3846 struct drm_crtc *crtc;
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3850 intel_crtc_disable(crtc);
3854 void intel_encoder_noop(struct drm_encoder *encoder)
3858 void intel_encoder_destroy(struct drm_encoder *encoder)
3860 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3862 drm_encoder_cleanup(encoder);
3863 kfree(intel_encoder);
3866 /* Simple dpms helper for encodres with just one connector, no cloning and only
3867 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3868 * state of the entire output pipe. */
3869 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3871 if (mode == DRM_MODE_DPMS_ON) {
3872 encoder->connectors_active = true;
3874 intel_crtc_update_dpms(encoder->base.crtc);
3876 encoder->connectors_active = false;
3878 intel_crtc_update_dpms(encoder->base.crtc);
3882 /* Cross check the actual hw state with our own modeset state tracking (and it's
3883 * internal consistency). */
3884 static void intel_connector_check_state(struct intel_connector *connector)
3886 if (connector->get_hw_state(connector)) {
3887 struct intel_encoder *encoder = connector->encoder;
3888 struct drm_crtc *crtc;
3889 bool encoder_enabled;
3892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3893 connector->base.base.id,
3894 drm_get_connector_name(&connector->base));
3896 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3897 "wrong connector dpms state\n");
3898 WARN(connector->base.encoder != &encoder->base,
3899 "active connector not linked to encoder\n");
3900 WARN(!encoder->connectors_active,
3901 "encoder->connectors_active not set\n");
3903 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3904 WARN(!encoder_enabled, "encoder not enabled\n");
3905 if (WARN_ON(!encoder->base.crtc))
3908 crtc = encoder->base.crtc;
3910 WARN(!crtc->enabled, "crtc not enabled\n");
3911 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3912 WARN(pipe != to_intel_crtc(crtc)->pipe,
3913 "encoder active on the wrong pipe\n");
3917 /* Even simpler default implementation, if there's really no special case to
3919 void intel_connector_dpms(struct drm_connector *connector, int mode)
3921 struct intel_encoder *encoder = intel_attached_encoder(connector);
3923 /* All the simple cases only support two dpms states. */
3924 if (mode != DRM_MODE_DPMS_ON)
3925 mode = DRM_MODE_DPMS_OFF;
3927 if (mode == connector->dpms)
3930 connector->dpms = mode;
3932 /* Only need to change hw state when actually enabled */
3933 if (encoder->base.crtc)
3934 intel_encoder_dpms(encoder, mode);
3936 WARN_ON(encoder->connectors_active != false);
3938 intel_modeset_check_state(connector->dev);
3941 /* Simple connector->get_hw_state implementation for encoders that support only
3942 * one connector and no cloning and hence the encoder state determines the state
3943 * of the connector. */
3944 bool intel_connector_get_hw_state(struct intel_connector *connector)
3947 struct intel_encoder *encoder = connector->encoder;
3949 return encoder->get_hw_state(encoder, &pipe);
3952 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3953 const struct drm_display_mode *mode,
3954 struct drm_display_mode *adjusted_mode)
3956 struct drm_device *dev = crtc->dev;
3958 if (HAS_PCH_SPLIT(dev)) {
3959 /* FDI link clock is fixed at 2.7G */
3960 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3964 /* All interlaced capable intel hw wants timings in frames. Note though
3965 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3966 * timings, so we need to be careful not to clobber these.*/
3967 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3968 drm_mode_set_crtcinfo(adjusted_mode, 0);
3970 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3971 * with a hsync front porch of 0.
3973 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3974 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3980 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3982 return 400000; /* FIXME */
3985 static int i945_get_display_clock_speed(struct drm_device *dev)
3990 static int i915_get_display_clock_speed(struct drm_device *dev)
3995 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4000 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4004 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4006 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4009 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4010 case GC_DISPLAY_CLOCK_333_MHZ:
4013 case GC_DISPLAY_CLOCK_190_200_MHZ:
4019 static int i865_get_display_clock_speed(struct drm_device *dev)
4024 static int i855_get_display_clock_speed(struct drm_device *dev)
4027 /* Assume that the hardware is in the high speed state. This
4028 * should be the default.
4030 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4031 case GC_CLOCK_133_200:
4032 case GC_CLOCK_100_200:
4034 case GC_CLOCK_166_250:
4036 case GC_CLOCK_100_133:
4040 /* Shouldn't happen */
4044 static int i830_get_display_clock_speed(struct drm_device *dev)
4058 fdi_reduce_ratio(u32 *num, u32 *den)
4060 while (*num > 0xffffff || *den > 0xffffff) {
4067 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4068 int link_clock, struct fdi_m_n *m_n)
4070 m_n->tu = 64; /* default size */
4072 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4073 m_n->gmch_m = bits_per_pixel * pixel_clock;
4074 m_n->gmch_n = link_clock * nlanes * 8;
4075 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4077 m_n->link_m = pixel_clock;
4078 m_n->link_n = link_clock;
4079 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4082 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4084 if (i915_panel_use_ssc >= 0)
4085 return i915_panel_use_ssc != 0;
4086 return dev_priv->lvds_use_ssc
4087 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4091 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4092 * @crtc: CRTC structure
4093 * @mode: requested mode
4095 * A pipe may be connected to one or more outputs. Based on the depth of the
4096 * attached framebuffer, choose a good color depth to use on the pipe.
4098 * If possible, match the pipe depth to the fb depth. In some cases, this
4099 * isn't ideal, because the connected output supports a lesser or restricted
4100 * set of depths. Resolve that here:
4101 * LVDS typically supports only 6bpc, so clamp down in that case
4102 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4103 * Displays may support a restricted set as well, check EDID and clamp as
4105 * DP may want to dither down to 6bpc to fit larger modes
4108 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4109 * true if they don't match).
4111 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4112 struct drm_framebuffer *fb,
4113 unsigned int *pipe_bpp,
4114 struct drm_display_mode *mode)
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 struct drm_connector *connector;
4119 struct intel_encoder *intel_encoder;
4120 unsigned int display_bpc = UINT_MAX, bpc;
4122 /* Walk the encoders & connectors on this crtc, get min bpc */
4123 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4125 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4126 unsigned int lvds_bpc;
4128 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4134 if (lvds_bpc < display_bpc) {
4135 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4136 display_bpc = lvds_bpc;
4141 /* Not one of the known troublemakers, check the EDID */
4142 list_for_each_entry(connector, &dev->mode_config.connector_list,
4144 if (connector->encoder != &intel_encoder->base)
4147 /* Don't use an invalid EDID bpc value */
4148 if (connector->display_info.bpc &&
4149 connector->display_info.bpc < display_bpc) {
4150 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4151 display_bpc = connector->display_info.bpc;
4156 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4157 * through, clamp it down. (Note: >12bpc will be caught below.)
4159 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4160 if (display_bpc > 8 && display_bpc < 12) {
4161 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4164 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4170 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4171 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4176 * We could just drive the pipe at the highest bpc all the time and
4177 * enable dithering as needed, but that costs bandwidth. So choose
4178 * the minimum value that expresses the full color range of the fb but
4179 * also stays within the max display bpc discovered above.
4182 switch (fb->depth) {
4184 bpc = 8; /* since we go through a colormap */
4188 bpc = 6; /* min is 18bpp */
4200 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4201 bpc = min((unsigned int)8, display_bpc);
4205 display_bpc = min(display_bpc, bpc);
4207 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4210 *pipe_bpp = display_bpc * 3;
4212 return display_bpc != bpc;
4215 static int vlv_get_refclk(struct drm_crtc *crtc)
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 int refclk = 27000; /* for DP & HDMI */
4221 return 100000; /* only one validated so far */
4223 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4226 if (intel_panel_use_ssc(dev_priv))
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4237 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4239 struct drm_device *dev = crtc->dev;
4240 struct drm_i915_private *dev_priv = dev->dev_private;
4243 if (IS_VALLEYVIEW(dev)) {
4244 refclk = vlv_get_refclk(crtc);
4245 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4246 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4247 refclk = dev_priv->lvds_ssc_freq * 1000;
4248 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4250 } else if (!IS_GEN2(dev)) {
4259 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4260 intel_clock_t *clock)
4262 /* SDVO TV has fixed PLL values depend on its clock range,
4263 this mirrors vbios setting. */
4264 if (adjusted_mode->clock >= 100000
4265 && adjusted_mode->clock < 140500) {
4271 } else if (adjusted_mode->clock >= 140500
4272 && adjusted_mode->clock <= 200000) {
4281 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4282 intel_clock_t *clock,
4283 intel_clock_t *reduced_clock)
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4288 int pipe = intel_crtc->pipe;
4291 if (IS_PINEVIEW(dev)) {
4292 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4294 fp2 = (1 << reduced_clock->n) << 16 |
4295 reduced_clock->m1 << 8 | reduced_clock->m2;
4297 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4299 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4303 I915_WRITE(FP0(pipe), fp);
4305 intel_crtc->lowfreq_avail = false;
4306 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4307 reduced_clock && i915_powersave) {
4308 I915_WRITE(FP1(pipe), fp2);
4309 intel_crtc->lowfreq_avail = true;
4311 I915_WRITE(FP1(pipe), fp);
4315 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4316 struct drm_display_mode *adjusted_mode)
4318 struct drm_device *dev = crtc->dev;
4319 struct drm_i915_private *dev_priv = dev->dev_private;
4320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321 int pipe = intel_crtc->pipe;
4324 temp = I915_READ(LVDS);
4325 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4327 temp |= LVDS_PIPEB_SELECT;
4329 temp &= ~LVDS_PIPEB_SELECT;
4331 /* set the corresponsding LVDS_BORDER bit */
4332 temp |= dev_priv->lvds_border_bits;
4333 /* Set the B0-B3 data pairs corresponding to whether we're going to
4334 * set the DPLLs for dual-channel mode or not.
4337 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4339 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4341 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4342 * appropriately here, but we need to look more thoroughly into how
4343 * panels behave in the two modes.
4345 /* set the dithering flag on LVDS as needed */
4346 if (INTEL_INFO(dev)->gen >= 4) {
4347 if (dev_priv->lvds_dither)
4348 temp |= LVDS_ENABLE_DITHER;
4350 temp &= ~LVDS_ENABLE_DITHER;
4352 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4353 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4354 temp |= LVDS_HSYNC_POLARITY;
4355 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4356 temp |= LVDS_VSYNC_POLARITY;
4357 I915_WRITE(LVDS, temp);
4360 static void vlv_update_pll(struct drm_crtc *crtc,
4361 struct drm_display_mode *mode,
4362 struct drm_display_mode *adjusted_mode,
4363 intel_clock_t *clock, intel_clock_t *reduced_clock,
4366 struct drm_device *dev = crtc->dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369 int pipe = intel_crtc->pipe;
4370 u32 dpll, mdiv, pdiv;
4371 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4375 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4376 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4378 dpll = DPLL_VGA_MODE_DIS;
4379 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4380 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4381 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4383 I915_WRITE(DPLL(pipe), dpll);
4384 POSTING_READ(DPLL(pipe));
4393 * In Valleyview PLL and program lane counter registers are exposed
4394 * through DPIO interface
4396 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4397 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4398 mdiv |= ((bestn << DPIO_N_SHIFT));
4399 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4400 mdiv |= (1 << DPIO_K_SHIFT);
4401 mdiv |= DPIO_ENABLE_CALIBRATION;
4402 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4404 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4406 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4407 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4408 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4409 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4410 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4412 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4414 dpll |= DPLL_VCO_ENABLE;
4415 I915_WRITE(DPLL(pipe), dpll);
4416 POSTING_READ(DPLL(pipe));
4417 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4418 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4420 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4423 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4425 I915_WRITE(DPLL(pipe), dpll);
4427 /* Wait for the clocks to stabilize. */
4428 POSTING_READ(DPLL(pipe));
4433 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4435 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4439 I915_WRITE(DPLL_MD(pipe), temp);
4440 POSTING_READ(DPLL_MD(pipe));
4442 /* Now program lane control registers */
4443 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4444 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4449 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4451 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4456 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4460 static void i9xx_update_pll(struct drm_crtc *crtc,
4461 struct drm_display_mode *mode,
4462 struct drm_display_mode *adjusted_mode,
4463 intel_clock_t *clock, intel_clock_t *reduced_clock,
4466 struct drm_device *dev = crtc->dev;
4467 struct drm_i915_private *dev_priv = dev->dev_private;
4468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4469 int pipe = intel_crtc->pipe;
4473 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4475 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4476 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4478 dpll = DPLL_VGA_MODE_DIS;
4480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4481 dpll |= DPLLB_MODE_LVDS;
4483 dpll |= DPLLB_MODE_DAC_SERIAL;
4485 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4486 if (pixel_multiplier > 1) {
4487 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4488 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4490 dpll |= DPLL_DVO_HIGH_SPEED;
4492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4493 dpll |= DPLL_DVO_HIGH_SPEED;
4495 /* compute bitmask from p1 value */
4496 if (IS_PINEVIEW(dev))
4497 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4499 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4500 if (IS_G4X(dev) && reduced_clock)
4501 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4503 switch (clock->p2) {
4505 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4508 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4511 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4514 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4517 if (INTEL_INFO(dev)->gen >= 4)
4518 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4520 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4521 dpll |= PLL_REF_INPUT_TVCLKINBC;
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4523 /* XXX: just matching BIOS for now */
4524 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4526 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4527 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4528 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4530 dpll |= PLL_REF_INPUT_DREFCLK;
4532 dpll |= DPLL_VCO_ENABLE;
4533 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4534 POSTING_READ(DPLL(pipe));
4537 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4538 * This is an exception to the general rule that mode_set doesn't turn
4541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4542 intel_update_lvds(crtc, clock, adjusted_mode);
4544 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4545 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4547 I915_WRITE(DPLL(pipe), dpll);
4549 /* Wait for the clocks to stabilize. */
4550 POSTING_READ(DPLL(pipe));
4553 if (INTEL_INFO(dev)->gen >= 4) {
4556 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4558 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4562 I915_WRITE(DPLL_MD(pipe), temp);
4564 /* The pixel multiplier can only be updated once the
4565 * DPLL is enabled and the clocks are stable.
4567 * So write it again.
4569 I915_WRITE(DPLL(pipe), dpll);
4573 static void i8xx_update_pll(struct drm_crtc *crtc,
4574 struct drm_display_mode *adjusted_mode,
4575 intel_clock_t *clock, intel_clock_t *reduced_clock,
4578 struct drm_device *dev = crtc->dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4581 int pipe = intel_crtc->pipe;
4584 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4586 dpll = DPLL_VGA_MODE_DIS;
4588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4589 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4592 dpll |= PLL_P1_DIVIDE_BY_TWO;
4594 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596 dpll |= PLL_P2_DIVIDE_BY_4;
4599 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4600 /* XXX: just matching BIOS for now */
4601 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4603 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4604 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4605 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4607 dpll |= PLL_REF_INPUT_DREFCLK;
4609 dpll |= DPLL_VCO_ENABLE;
4610 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4611 POSTING_READ(DPLL(pipe));
4614 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4615 * This is an exception to the general rule that mode_set doesn't turn
4618 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4619 intel_update_lvds(crtc, clock, adjusted_mode);
4621 I915_WRITE(DPLL(pipe), dpll);
4623 /* Wait for the clocks to stabilize. */
4624 POSTING_READ(DPLL(pipe));
4627 /* The pixel multiplier can only be updated once the
4628 * DPLL is enabled and the clocks are stable.
4630 * So write it again.
4632 I915_WRITE(DPLL(pipe), dpll);
4635 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4636 struct drm_display_mode *mode,
4637 struct drm_display_mode *adjusted_mode)
4639 struct drm_device *dev = intel_crtc->base.dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 enum pipe pipe = intel_crtc->pipe;
4642 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4643 uint32_t vsyncshift;
4645 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4646 /* the chip adds 2 halflines automatically */
4647 adjusted_mode->crtc_vtotal -= 1;
4648 adjusted_mode->crtc_vblank_end -= 1;
4649 vsyncshift = adjusted_mode->crtc_hsync_start
4650 - adjusted_mode->crtc_htotal / 2;
4655 if (INTEL_INFO(dev)->gen > 3)
4656 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4658 I915_WRITE(HTOTAL(cpu_transcoder),
4659 (adjusted_mode->crtc_hdisplay - 1) |
4660 ((adjusted_mode->crtc_htotal - 1) << 16));
4661 I915_WRITE(HBLANK(cpu_transcoder),
4662 (adjusted_mode->crtc_hblank_start - 1) |
4663 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4664 I915_WRITE(HSYNC(cpu_transcoder),
4665 (adjusted_mode->crtc_hsync_start - 1) |
4666 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668 I915_WRITE(VTOTAL(cpu_transcoder),
4669 (adjusted_mode->crtc_vdisplay - 1) |
4670 ((adjusted_mode->crtc_vtotal - 1) << 16));
4671 I915_WRITE(VBLANK(cpu_transcoder),
4672 (adjusted_mode->crtc_vblank_start - 1) |
4673 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4674 I915_WRITE(VSYNC(cpu_transcoder),
4675 (adjusted_mode->crtc_vsync_start - 1) |
4676 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4679 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4680 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4683 (pipe == PIPE_B || pipe == PIPE_C))
4684 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686 /* pipesrc controls the size that is scaled from, which should
4687 * always be the user's requested size.
4689 I915_WRITE(PIPESRC(pipe),
4690 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4693 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4694 struct drm_display_mode *mode,
4695 struct drm_display_mode *adjusted_mode,
4697 struct drm_framebuffer *fb)
4699 struct drm_device *dev = crtc->dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702 int pipe = intel_crtc->pipe;
4703 int plane = intel_crtc->plane;
4704 int refclk, num_connectors = 0;
4705 intel_clock_t clock, reduced_clock;
4706 u32 dspcntr, pipeconf;
4707 bool ok, has_reduced_clock = false, is_sdvo = false;
4708 bool is_lvds = false, is_tv = false, is_dp = false;
4709 struct intel_encoder *encoder;
4710 const intel_limit_t *limit;
4713 for_each_encoder_on_crtc(dev, crtc, encoder) {
4714 switch (encoder->type) {
4715 case INTEL_OUTPUT_LVDS:
4718 case INTEL_OUTPUT_SDVO:
4719 case INTEL_OUTPUT_HDMI:
4721 if (encoder->needs_tv_clock)
4724 case INTEL_OUTPUT_TVOUT:
4727 case INTEL_OUTPUT_DISPLAYPORT:
4735 refclk = i9xx_get_refclk(crtc, num_connectors);
4738 * Returns a set of divisors for the desired target clock with the given
4739 * refclk, or FALSE. The returned values represent the clock equation:
4740 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4742 limit = intel_limit(crtc, refclk);
4743 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4746 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4750 /* Ensure that the cursor is valid for the new mode before changing... */
4751 intel_crtc_update_cursor(crtc, true);
4753 if (is_lvds && dev_priv->lvds_downclock_avail) {
4755 * Ensure we match the reduced clock's P to the target clock.
4756 * If the clocks don't match, we can't switch the display clock
4757 * by using the FP0/FP1. In such case we will disable the LVDS
4758 * downclock feature.
4760 has_reduced_clock = limit->find_pll(limit, crtc,
4761 dev_priv->lvds_downclock,
4767 if (is_sdvo && is_tv)
4768 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4771 i8xx_update_pll(crtc, adjusted_mode, &clock,
4772 has_reduced_clock ? &reduced_clock : NULL,
4774 else if (IS_VALLEYVIEW(dev))
4775 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4776 has_reduced_clock ? &reduced_clock : NULL,
4779 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4780 has_reduced_clock ? &reduced_clock : NULL,
4783 /* setup pipeconf */
4784 pipeconf = I915_READ(PIPECONF(pipe));
4786 /* Set up the display plane register */
4787 dspcntr = DISPPLANE_GAMMA_ENABLE;
4790 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4792 dspcntr |= DISPPLANE_SEL_PIPE_B;
4794 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4795 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4798 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4802 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4803 pipeconf |= PIPECONF_DOUBLE_WIDE;
4805 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4808 /* default to 8bpc */
4809 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4811 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4812 pipeconf |= PIPECONF_BPP_6 |
4813 PIPECONF_DITHER_EN |
4814 PIPECONF_DITHER_TYPE_SP;
4818 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4819 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4820 pipeconf |= PIPECONF_BPP_6 |
4822 I965_PIPECONF_ACTIVE;
4826 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4827 drm_mode_debug_printmodeline(mode);
4829 if (HAS_PIPE_CXSR(dev)) {
4830 if (intel_crtc->lowfreq_avail) {
4831 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4832 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4834 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4835 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4839 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4840 if (!IS_GEN2(dev) &&
4841 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4842 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4844 pipeconf |= PIPECONF_PROGRESSIVE;
4846 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4848 /* pipesrc and dspsize control the size that is scaled from,
4849 * which should always be the user's requested size.
4851 I915_WRITE(DSPSIZE(plane),
4852 ((mode->vdisplay - 1) << 16) |
4853 (mode->hdisplay - 1));
4854 I915_WRITE(DSPPOS(plane), 0);
4856 I915_WRITE(PIPECONF(pipe), pipeconf);
4857 POSTING_READ(PIPECONF(pipe));
4858 intel_enable_pipe(dev_priv, pipe, false);
4860 intel_wait_for_vblank(dev, pipe);
4862 I915_WRITE(DSPCNTR(plane), dspcntr);
4863 POSTING_READ(DSPCNTR(plane));
4865 ret = intel_pipe_set_base(crtc, x, y, fb);
4867 intel_update_watermarks(dev);
4873 * Initialize reference clocks when the driver loads
4875 void ironlake_init_pch_refclk(struct drm_device *dev)
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct drm_mode_config *mode_config = &dev->mode_config;
4879 struct intel_encoder *encoder;
4881 bool has_lvds = false;
4882 bool has_cpu_edp = false;
4883 bool has_pch_edp = false;
4884 bool has_panel = false;
4885 bool has_ck505 = false;
4886 bool can_ssc = false;
4888 /* We need to take the global config into account */
4889 list_for_each_entry(encoder, &mode_config->encoder_list,
4891 switch (encoder->type) {
4892 case INTEL_OUTPUT_LVDS:
4896 case INTEL_OUTPUT_EDP:
4898 if (intel_encoder_is_pch_edp(&encoder->base))
4906 if (HAS_PCH_IBX(dev)) {
4907 has_ck505 = dev_priv->display_clock_mode;
4908 can_ssc = has_ck505;
4914 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4915 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4918 /* Ironlake: try to setup display ref clock before DPLL
4919 * enabling. This is only under driver's control after
4920 * PCH B stepping, previous chipset stepping should be
4921 * ignoring this setting.
4923 temp = I915_READ(PCH_DREF_CONTROL);
4924 /* Always enable nonspread source */
4925 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4928 temp |= DREF_NONSPREAD_CK505_ENABLE;
4930 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4933 temp &= ~DREF_SSC_SOURCE_MASK;
4934 temp |= DREF_SSC_SOURCE_ENABLE;
4936 /* SSC must be turned on before enabling the CPU output */
4937 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4938 DRM_DEBUG_KMS("Using SSC on panel\n");
4939 temp |= DREF_SSC1_ENABLE;
4941 temp &= ~DREF_SSC1_ENABLE;
4943 /* Get SSC going before enabling the outputs */
4944 I915_WRITE(PCH_DREF_CONTROL, temp);
4945 POSTING_READ(PCH_DREF_CONTROL);
4948 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4950 /* Enable CPU source on CPU attached eDP */
4952 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4953 DRM_DEBUG_KMS("Using SSC on eDP\n");
4954 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4957 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4959 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4961 I915_WRITE(PCH_DREF_CONTROL, temp);
4962 POSTING_READ(PCH_DREF_CONTROL);
4965 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4967 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4969 /* Turn off CPU output */
4970 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4972 I915_WRITE(PCH_DREF_CONTROL, temp);
4973 POSTING_READ(PCH_DREF_CONTROL);
4976 /* Turn off the SSC source */
4977 temp &= ~DREF_SSC_SOURCE_MASK;
4978 temp |= DREF_SSC_SOURCE_DISABLE;
4981 temp &= ~ DREF_SSC1_ENABLE;
4983 I915_WRITE(PCH_DREF_CONTROL, temp);
4984 POSTING_READ(PCH_DREF_CONTROL);
4989 static int ironlake_get_refclk(struct drm_crtc *crtc)
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_encoder *encoder;
4994 struct intel_encoder *edp_encoder = NULL;
4995 int num_connectors = 0;
4996 bool is_lvds = false;
4998 for_each_encoder_on_crtc(dev, crtc, encoder) {
4999 switch (encoder->type) {
5000 case INTEL_OUTPUT_LVDS:
5003 case INTEL_OUTPUT_EDP:
5004 edp_encoder = encoder;
5010 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5011 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5012 dev_priv->lvds_ssc_freq);
5013 return dev_priv->lvds_ssc_freq * 1000;
5019 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5020 struct drm_display_mode *adjusted_mode,
5023 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025 int pipe = intel_crtc->pipe;
5028 val = I915_READ(PIPECONF(pipe));
5030 val &= ~PIPE_BPC_MASK;
5031 switch (intel_crtc->bpp) {
5045 /* Case prevented by intel_choose_pipe_bpp_dither. */
5049 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5051 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5053 val &= ~PIPECONF_INTERLACE_MASK;
5054 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5055 val |= PIPECONF_INTERLACED_ILK;
5057 val |= PIPECONF_PROGRESSIVE;
5059 I915_WRITE(PIPECONF(pipe), val);
5060 POSTING_READ(PIPECONF(pipe));
5063 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5064 struct drm_display_mode *adjusted_mode,
5067 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5069 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5072 val = I915_READ(PIPECONF(cpu_transcoder));
5074 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5076 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5078 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5079 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5080 val |= PIPECONF_INTERLACED_ILK;
5082 val |= PIPECONF_PROGRESSIVE;
5084 I915_WRITE(PIPECONF(cpu_transcoder), val);
5085 POSTING_READ(PIPECONF(cpu_transcoder));
5088 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5089 struct drm_display_mode *adjusted_mode,
5090 intel_clock_t *clock,
5091 bool *has_reduced_clock,
5092 intel_clock_t *reduced_clock)
5094 struct drm_device *dev = crtc->dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_encoder *intel_encoder;
5098 const intel_limit_t *limit;
5099 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5101 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5102 switch (intel_encoder->type) {
5103 case INTEL_OUTPUT_LVDS:
5106 case INTEL_OUTPUT_SDVO:
5107 case INTEL_OUTPUT_HDMI:
5109 if (intel_encoder->needs_tv_clock)
5112 case INTEL_OUTPUT_TVOUT:
5118 refclk = ironlake_get_refclk(crtc);
5121 * Returns a set of divisors for the desired target clock with the given
5122 * refclk, or FALSE. The returned values represent the clock equation:
5123 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5125 limit = intel_limit(crtc, refclk);
5126 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5131 if (is_lvds && dev_priv->lvds_downclock_avail) {
5133 * Ensure we match the reduced clock's P to the target clock.
5134 * If the clocks don't match, we can't switch the display clock
5135 * by using the FP0/FP1. In such case we will disable the LVDS
5136 * downclock feature.
5138 *has_reduced_clock = limit->find_pll(limit, crtc,
5139 dev_priv->lvds_downclock,
5145 if (is_sdvo && is_tv)
5146 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5151 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5153 struct drm_i915_private *dev_priv = dev->dev_private;
5156 temp = I915_READ(SOUTH_CHICKEN1);
5157 if (temp & FDI_BC_BIFURCATION_SELECT)
5160 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5161 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5163 temp |= FDI_BC_BIFURCATION_SELECT;
5164 DRM_DEBUG_KMS("enabling fdi C rx\n");
5165 I915_WRITE(SOUTH_CHICKEN1, temp);
5166 POSTING_READ(SOUTH_CHICKEN1);
5169 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5171 struct drm_device *dev = intel_crtc->base.dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 struct intel_crtc *pipe_B_crtc =
5174 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5176 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5177 intel_crtc->pipe, intel_crtc->fdi_lanes);
5178 if (intel_crtc->fdi_lanes > 4) {
5179 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5180 intel_crtc->pipe, intel_crtc->fdi_lanes);
5181 /* Clamp lanes to avoid programming the hw with bogus values. */
5182 intel_crtc->fdi_lanes = 4;
5187 if (dev_priv->num_pipe == 2)
5190 switch (intel_crtc->pipe) {
5194 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5195 intel_crtc->fdi_lanes > 2) {
5196 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5197 intel_crtc->pipe, intel_crtc->fdi_lanes);
5198 /* Clamp lanes to avoid programming the hw with bogus values. */
5199 intel_crtc->fdi_lanes = 2;
5204 if (intel_crtc->fdi_lanes > 2)
5205 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5207 cpt_enable_fdi_bc_bifurcation(dev);
5211 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5212 if (intel_crtc->fdi_lanes > 2) {
5213 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5214 intel_crtc->pipe, intel_crtc->fdi_lanes);
5215 /* Clamp lanes to avoid programming the hw with bogus values. */
5216 intel_crtc->fdi_lanes = 2;
5221 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5225 cpt_enable_fdi_bc_bifurcation(dev);
5233 static void ironlake_set_m_n(struct drm_crtc *crtc,
5234 struct drm_display_mode *mode,
5235 struct drm_display_mode *adjusted_mode)
5237 struct drm_device *dev = crtc->dev;
5238 struct drm_i915_private *dev_priv = dev->dev_private;
5239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5241 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5242 struct fdi_m_n m_n = {0};
5243 int target_clock, pixel_multiplier, lane, link_bw;
5244 bool is_dp = false, is_cpu_edp = false;
5246 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5247 switch (intel_encoder->type) {
5248 case INTEL_OUTPUT_DISPLAYPORT:
5251 case INTEL_OUTPUT_EDP:
5253 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5255 edp_encoder = intel_encoder;
5261 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5263 /* CPU eDP doesn't require FDI link, so just set DP M/N
5264 according to current link config */
5266 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5268 /* FDI is a binary signal running at ~2.7GHz, encoding
5269 * each output octet as 10 bits. The actual frequency
5270 * is stored as a divider into a 100MHz clock, and the
5271 * mode pixel clock is stored in units of 1KHz.
5272 * Hence the bw of each lane in terms of the mode signal
5275 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5278 /* [e]DP over FDI requires target mode clock instead of link clock. */
5280 target_clock = intel_edp_target_clock(edp_encoder, mode);
5282 target_clock = mode->clock;
5284 target_clock = adjusted_mode->clock;
5288 * Account for spread spectrum to avoid
5289 * oversubscribing the link. Max center spread
5290 * is 2.5%; use 5% for safety's sake.
5292 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5293 lane = bps / (link_bw * 8) + 1;
5296 intel_crtc->fdi_lanes = lane;
5298 if (pixel_multiplier > 1)
5299 link_bw *= pixel_multiplier;
5300 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5303 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5304 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5305 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5306 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5309 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5310 struct drm_display_mode *adjusted_mode,
5311 intel_clock_t *clock, u32 fp)
5313 struct drm_crtc *crtc = &intel_crtc->base;
5314 struct drm_device *dev = crtc->dev;
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 struct intel_encoder *intel_encoder;
5318 int factor, pixel_multiplier, num_connectors = 0;
5319 bool is_lvds = false, is_sdvo = false, is_tv = false;
5320 bool is_dp = false, is_cpu_edp = false;
5322 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5323 switch (intel_encoder->type) {
5324 case INTEL_OUTPUT_LVDS:
5327 case INTEL_OUTPUT_SDVO:
5328 case INTEL_OUTPUT_HDMI:
5330 if (intel_encoder->needs_tv_clock)
5333 case INTEL_OUTPUT_TVOUT:
5336 case INTEL_OUTPUT_DISPLAYPORT:
5339 case INTEL_OUTPUT_EDP:
5341 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5349 /* Enable autotuning of the PLL clock (if permissible) */
5352 if ((intel_panel_use_ssc(dev_priv) &&
5353 dev_priv->lvds_ssc_freq == 100) ||
5354 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5356 } else if (is_sdvo && is_tv)
5359 if (clock->m < factor * clock->n)
5365 dpll |= DPLLB_MODE_LVDS;
5367 dpll |= DPLLB_MODE_DAC_SERIAL;
5369 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5370 if (pixel_multiplier > 1) {
5371 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5373 dpll |= DPLL_DVO_HIGH_SPEED;
5375 if (is_dp && !is_cpu_edp)
5376 dpll |= DPLL_DVO_HIGH_SPEED;
5378 /* compute bitmask from p1 value */
5379 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5381 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5383 switch (clock->p2) {
5385 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5388 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5398 if (is_sdvo && is_tv)
5399 dpll |= PLL_REF_INPUT_TVCLKINBC;
5401 /* XXX: just matching BIOS for now */
5402 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5404 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5405 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5407 dpll |= PLL_REF_INPUT_DREFCLK;
5412 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5413 struct drm_display_mode *mode,
5414 struct drm_display_mode *adjusted_mode,
5416 struct drm_framebuffer *fb)
5418 struct drm_device *dev = crtc->dev;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5421 int pipe = intel_crtc->pipe;
5422 int plane = intel_crtc->plane;
5423 int num_connectors = 0;
5424 intel_clock_t clock, reduced_clock;
5425 u32 dpll, fp = 0, fp2 = 0;
5426 bool ok, has_reduced_clock = false;
5427 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5428 struct intel_encoder *encoder;
5431 bool dither, fdi_config_ok;
5433 for_each_encoder_on_crtc(dev, crtc, encoder) {
5434 switch (encoder->type) {
5435 case INTEL_OUTPUT_LVDS:
5438 case INTEL_OUTPUT_DISPLAYPORT:
5441 case INTEL_OUTPUT_EDP:
5443 if (!intel_encoder_is_pch_edp(&encoder->base))
5451 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5452 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5454 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5455 &has_reduced_clock, &reduced_clock);
5457 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5461 /* Ensure that the cursor is valid for the new mode before changing... */
5462 intel_crtc_update_cursor(crtc, true);
5464 /* determine panel color depth */
5465 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5467 if (is_lvds && dev_priv->lvds_dither)
5470 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5471 if (has_reduced_clock)
5472 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5475 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5477 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5478 drm_mode_debug_printmodeline(mode);
5480 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5482 struct intel_pch_pll *pll;
5484 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5486 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5491 intel_put_pch_pll(intel_crtc);
5493 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5494 * This is an exception to the general rule that mode_set doesn't turn
5498 temp = I915_READ(PCH_LVDS);
5499 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5500 if (HAS_PCH_CPT(dev)) {
5501 temp &= ~PORT_TRANS_SEL_MASK;
5502 temp |= PORT_TRANS_SEL_CPT(pipe);
5505 temp |= LVDS_PIPEB_SELECT;
5507 temp &= ~LVDS_PIPEB_SELECT;
5510 /* set the corresponsding LVDS_BORDER bit */
5511 temp |= dev_priv->lvds_border_bits;
5512 /* Set the B0-B3 data pairs corresponding to whether we're going to
5513 * set the DPLLs for dual-channel mode or not.
5516 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5518 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5520 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5521 * appropriately here, but we need to look more thoroughly into how
5522 * panels behave in the two modes.
5524 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5525 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5526 temp |= LVDS_HSYNC_POLARITY;
5527 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5528 temp |= LVDS_VSYNC_POLARITY;
5529 I915_WRITE(PCH_LVDS, temp);
5532 if (is_dp && !is_cpu_edp) {
5533 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5535 /* For non-DP output, clear any trans DP clock recovery setting.*/
5536 I915_WRITE(TRANSDATA_M1(pipe), 0);
5537 I915_WRITE(TRANSDATA_N1(pipe), 0);
5538 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5539 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5542 if (intel_crtc->pch_pll) {
5543 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5545 /* Wait for the clocks to stabilize. */
5546 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5549 /* The pixel multiplier can only be updated once the
5550 * DPLL is enabled and the clocks are stable.
5552 * So write it again.
5554 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5557 intel_crtc->lowfreq_avail = false;
5558 if (intel_crtc->pch_pll) {
5559 if (is_lvds && has_reduced_clock && i915_powersave) {
5560 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5561 intel_crtc->lowfreq_avail = true;
5563 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5567 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5569 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5570 * ironlake_check_fdi_lanes. */
5571 ironlake_set_m_n(crtc, mode, adjusted_mode);
5573 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5576 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5578 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5580 intel_wait_for_vblank(dev, pipe);
5582 /* Set up the display plane register */
5583 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5584 POSTING_READ(DSPCNTR(plane));
5586 ret = intel_pipe_set_base(crtc, x, y, fb);
5588 intel_update_watermarks(dev);
5590 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5592 return fdi_config_ok ? ret : -EINVAL;
5595 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5596 struct drm_display_mode *mode,
5597 struct drm_display_mode *adjusted_mode,
5599 struct drm_framebuffer *fb)
5601 struct drm_device *dev = crtc->dev;
5602 struct drm_i915_private *dev_priv = dev->dev_private;
5603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5604 int pipe = intel_crtc->pipe;
5605 int plane = intel_crtc->plane;
5606 int num_connectors = 0;
5607 intel_clock_t clock, reduced_clock;
5608 u32 dpll = 0, fp = 0, fp2 = 0;
5609 bool ok, has_reduced_clock = false;
5610 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5611 struct intel_encoder *encoder;
5616 for_each_encoder_on_crtc(dev, crtc, encoder) {
5617 switch (encoder->type) {
5618 case INTEL_OUTPUT_LVDS:
5621 case INTEL_OUTPUT_DISPLAYPORT:
5624 case INTEL_OUTPUT_EDP:
5626 if (!intel_encoder_is_pch_edp(&encoder->base))
5635 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5637 intel_crtc->cpu_transcoder = pipe;
5639 /* We are not sure yet this won't happen. */
5640 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5641 INTEL_PCH_TYPE(dev));
5643 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5644 num_connectors, pipe_name(pipe));
5646 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5647 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5649 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5651 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5654 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5655 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5659 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5664 /* Ensure that the cursor is valid for the new mode before changing... */
5665 intel_crtc_update_cursor(crtc, true);
5667 /* determine panel color depth */
5668 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5670 if (is_lvds && dev_priv->lvds_dither)
5673 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5674 drm_mode_debug_printmodeline(mode);
5676 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5677 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5678 if (has_reduced_clock)
5679 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5682 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5685 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5686 * own on pre-Haswell/LPT generation */
5688 struct intel_pch_pll *pll;
5690 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5692 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5697 intel_put_pch_pll(intel_crtc);
5699 /* The LVDS pin pair needs to be on before the DPLLs are
5700 * enabled. This is an exception to the general rule that
5701 * mode_set doesn't turn things on.
5704 temp = I915_READ(PCH_LVDS);
5705 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5706 if (HAS_PCH_CPT(dev)) {
5707 temp &= ~PORT_TRANS_SEL_MASK;
5708 temp |= PORT_TRANS_SEL_CPT(pipe);
5711 temp |= LVDS_PIPEB_SELECT;
5713 temp &= ~LVDS_PIPEB_SELECT;
5716 /* set the corresponsding LVDS_BORDER bit */
5717 temp |= dev_priv->lvds_border_bits;
5718 /* Set the B0-B3 data pairs corresponding to whether
5719 * we're going to set the DPLLs for dual-channel mode or
5723 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5725 temp &= ~(LVDS_B0B3_POWER_UP |
5726 LVDS_CLKB_POWER_UP);
5728 /* It would be nice to set 24 vs 18-bit mode
5729 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5730 * look more thoroughly into how panels behave in the
5733 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5734 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5735 temp |= LVDS_HSYNC_POLARITY;
5736 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5737 temp |= LVDS_VSYNC_POLARITY;
5738 I915_WRITE(PCH_LVDS, temp);
5742 if (is_dp && !is_cpu_edp) {
5743 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5745 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5746 /* For non-DP output, clear any trans DP clock recovery
5748 I915_WRITE(TRANSDATA_M1(pipe), 0);
5749 I915_WRITE(TRANSDATA_N1(pipe), 0);
5750 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5751 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5755 intel_crtc->lowfreq_avail = false;
5756 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5757 if (intel_crtc->pch_pll) {
5758 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5760 /* Wait for the clocks to stabilize. */
5761 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5764 /* The pixel multiplier can only be updated once the
5765 * DPLL is enabled and the clocks are stable.
5767 * So write it again.
5769 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5772 if (intel_crtc->pch_pll) {
5773 if (is_lvds && has_reduced_clock && i915_powersave) {
5774 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5775 intel_crtc->lowfreq_avail = true;
5777 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5782 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5784 if (!is_dp || is_cpu_edp)
5785 ironlake_set_m_n(crtc, mode, adjusted_mode);
5787 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5789 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5791 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5793 /* Set up the display plane register */
5794 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5795 POSTING_READ(DSPCNTR(plane));
5797 ret = intel_pipe_set_base(crtc, x, y, fb);
5799 intel_update_watermarks(dev);
5801 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5806 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5807 struct drm_display_mode *mode,
5808 struct drm_display_mode *adjusted_mode,
5810 struct drm_framebuffer *fb)
5812 struct drm_device *dev = crtc->dev;
5813 struct drm_i915_private *dev_priv = dev->dev_private;
5814 struct drm_encoder_helper_funcs *encoder_funcs;
5815 struct intel_encoder *encoder;
5816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817 int pipe = intel_crtc->pipe;
5820 drm_vblank_pre_modeset(dev, pipe);
5822 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5824 drm_vblank_post_modeset(dev, pipe);
5829 for_each_encoder_on_crtc(dev, crtc, encoder) {
5830 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5831 encoder->base.base.id,
5832 drm_get_encoder_name(&encoder->base),
5833 mode->base.id, mode->name);
5834 encoder_funcs = encoder->base.helper_private;
5835 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5841 static bool intel_eld_uptodate(struct drm_connector *connector,
5842 int reg_eldv, uint32_t bits_eldv,
5843 int reg_elda, uint32_t bits_elda,
5846 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5847 uint8_t *eld = connector->eld;
5850 i = I915_READ(reg_eldv);
5859 i = I915_READ(reg_elda);
5861 I915_WRITE(reg_elda, i);
5863 for (i = 0; i < eld[2]; i++)
5864 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5870 static void g4x_write_eld(struct drm_connector *connector,
5871 struct drm_crtc *crtc)
5873 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5874 uint8_t *eld = connector->eld;
5879 i = I915_READ(G4X_AUD_VID_DID);
5881 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5882 eldv = G4X_ELDV_DEVCL_DEVBLC;
5884 eldv = G4X_ELDV_DEVCTG;
5886 if (intel_eld_uptodate(connector,
5887 G4X_AUD_CNTL_ST, eldv,
5888 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5889 G4X_HDMIW_HDMIEDID))
5892 i = I915_READ(G4X_AUD_CNTL_ST);
5893 i &= ~(eldv | G4X_ELD_ADDR);
5894 len = (i >> 9) & 0x1f; /* ELD buffer size */
5895 I915_WRITE(G4X_AUD_CNTL_ST, i);
5900 len = min_t(uint8_t, eld[2], len);
5901 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5902 for (i = 0; i < len; i++)
5903 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5905 i = I915_READ(G4X_AUD_CNTL_ST);
5907 I915_WRITE(G4X_AUD_CNTL_ST, i);
5910 static void haswell_write_eld(struct drm_connector *connector,
5911 struct drm_crtc *crtc)
5913 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5914 uint8_t *eld = connector->eld;
5915 struct drm_device *dev = crtc->dev;
5919 int pipe = to_intel_crtc(crtc)->pipe;
5922 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5923 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5924 int aud_config = HSW_AUD_CFG(pipe);
5925 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5928 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5930 /* Audio output enable */
5931 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5932 tmp = I915_READ(aud_cntrl_st2);
5933 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5934 I915_WRITE(aud_cntrl_st2, tmp);
5936 /* Wait for 1 vertical blank */
5937 intel_wait_for_vblank(dev, pipe);
5939 /* Set ELD valid state */
5940 tmp = I915_READ(aud_cntrl_st2);
5941 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5942 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5943 I915_WRITE(aud_cntrl_st2, tmp);
5944 tmp = I915_READ(aud_cntrl_st2);
5945 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5947 /* Enable HDMI mode */
5948 tmp = I915_READ(aud_config);
5949 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5950 /* clear N_programing_enable and N_value_index */
5951 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5952 I915_WRITE(aud_config, tmp);
5954 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5956 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5958 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5959 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5960 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5961 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5963 I915_WRITE(aud_config, 0);
5965 if (intel_eld_uptodate(connector,
5966 aud_cntrl_st2, eldv,
5967 aud_cntl_st, IBX_ELD_ADDRESS,
5971 i = I915_READ(aud_cntrl_st2);
5973 I915_WRITE(aud_cntrl_st2, i);
5978 i = I915_READ(aud_cntl_st);
5979 i &= ~IBX_ELD_ADDRESS;
5980 I915_WRITE(aud_cntl_st, i);
5981 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5982 DRM_DEBUG_DRIVER("port num:%d\n", i);
5984 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5985 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5986 for (i = 0; i < len; i++)
5987 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5989 i = I915_READ(aud_cntrl_st2);
5991 I915_WRITE(aud_cntrl_st2, i);
5995 static void ironlake_write_eld(struct drm_connector *connector,
5996 struct drm_crtc *crtc)
5998 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5999 uint8_t *eld = connector->eld;
6007 int pipe = to_intel_crtc(crtc)->pipe;
6009 if (HAS_PCH_IBX(connector->dev)) {
6010 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6011 aud_config = IBX_AUD_CFG(pipe);
6012 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6013 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6015 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6016 aud_config = CPT_AUD_CFG(pipe);
6017 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6018 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6021 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6023 i = I915_READ(aud_cntl_st);
6024 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6026 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6027 /* operate blindly on all ports */
6028 eldv = IBX_ELD_VALIDB;
6029 eldv |= IBX_ELD_VALIDB << 4;
6030 eldv |= IBX_ELD_VALIDB << 8;
6032 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6033 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6036 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6037 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6038 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6039 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6041 I915_WRITE(aud_config, 0);
6043 if (intel_eld_uptodate(connector,
6044 aud_cntrl_st2, eldv,
6045 aud_cntl_st, IBX_ELD_ADDRESS,
6049 i = I915_READ(aud_cntrl_st2);
6051 I915_WRITE(aud_cntrl_st2, i);
6056 i = I915_READ(aud_cntl_st);
6057 i &= ~IBX_ELD_ADDRESS;
6058 I915_WRITE(aud_cntl_st, i);
6060 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6061 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6062 for (i = 0; i < len; i++)
6063 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6065 i = I915_READ(aud_cntrl_st2);
6067 I915_WRITE(aud_cntrl_st2, i);
6070 void intel_write_eld(struct drm_encoder *encoder,
6071 struct drm_display_mode *mode)
6073 struct drm_crtc *crtc = encoder->crtc;
6074 struct drm_connector *connector;
6075 struct drm_device *dev = encoder->dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6078 connector = drm_select_eld(encoder, mode);
6082 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6084 drm_get_connector_name(connector),
6085 connector->encoder->base.id,
6086 drm_get_encoder_name(connector->encoder));
6088 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6090 if (dev_priv->display.write_eld)
6091 dev_priv->display.write_eld(connector, crtc);
6094 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6095 void intel_crtc_load_lut(struct drm_crtc *crtc)
6097 struct drm_device *dev = crtc->dev;
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6100 int palreg = PALETTE(intel_crtc->pipe);
6103 /* The clocks have to be on to load the palette. */
6104 if (!crtc->enabled || !intel_crtc->active)
6107 /* use legacy palette for Ironlake */
6108 if (HAS_PCH_SPLIT(dev))
6109 palreg = LGC_PALETTE(intel_crtc->pipe);
6111 for (i = 0; i < 256; i++) {
6112 I915_WRITE(palreg + 4 * i,
6113 (intel_crtc->lut_r[i] << 16) |
6114 (intel_crtc->lut_g[i] << 8) |
6115 intel_crtc->lut_b[i]);
6119 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6121 struct drm_device *dev = crtc->dev;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124 bool visible = base != 0;
6127 if (intel_crtc->cursor_visible == visible)
6130 cntl = I915_READ(_CURACNTR);
6132 /* On these chipsets we can only modify the base whilst
6133 * the cursor is disabled.
6135 I915_WRITE(_CURABASE, base);
6137 cntl &= ~(CURSOR_FORMAT_MASK);
6138 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6139 cntl |= CURSOR_ENABLE |
6140 CURSOR_GAMMA_ENABLE |
6143 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6144 I915_WRITE(_CURACNTR, cntl);
6146 intel_crtc->cursor_visible = visible;
6149 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6151 struct drm_device *dev = crtc->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154 int pipe = intel_crtc->pipe;
6155 bool visible = base != 0;
6157 if (intel_crtc->cursor_visible != visible) {
6158 uint32_t cntl = I915_READ(CURCNTR(pipe));
6160 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6161 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6162 cntl |= pipe << 28; /* Connect to correct pipe */
6164 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6165 cntl |= CURSOR_MODE_DISABLE;
6167 I915_WRITE(CURCNTR(pipe), cntl);
6169 intel_crtc->cursor_visible = visible;
6171 /* and commit changes on next vblank */
6172 I915_WRITE(CURBASE(pipe), base);
6175 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 int pipe = intel_crtc->pipe;
6181 bool visible = base != 0;
6183 if (intel_crtc->cursor_visible != visible) {
6184 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6186 cntl &= ~CURSOR_MODE;
6187 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6189 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6190 cntl |= CURSOR_MODE_DISABLE;
6192 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6194 intel_crtc->cursor_visible = visible;
6196 /* and commit changes on next vblank */
6197 I915_WRITE(CURBASE_IVB(pipe), base);
6200 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6201 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6204 struct drm_device *dev = crtc->dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private;
6206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6207 int pipe = intel_crtc->pipe;
6208 int x = intel_crtc->cursor_x;
6209 int y = intel_crtc->cursor_y;
6215 if (on && crtc->enabled && crtc->fb) {
6216 base = intel_crtc->cursor_addr;
6217 if (x > (int) crtc->fb->width)
6220 if (y > (int) crtc->fb->height)
6226 if (x + intel_crtc->cursor_width < 0)
6229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6232 pos |= x << CURSOR_X_SHIFT;
6235 if (y + intel_crtc->cursor_height < 0)
6238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6241 pos |= y << CURSOR_Y_SHIFT;
6243 visible = base != 0;
6244 if (!visible && !intel_crtc->cursor_visible)
6247 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6248 I915_WRITE(CURPOS_IVB(pipe), pos);
6249 ivb_update_cursor(crtc, base);
6251 I915_WRITE(CURPOS(pipe), pos);
6252 if (IS_845G(dev) || IS_I865G(dev))
6253 i845_update_cursor(crtc, base);
6255 i9xx_update_cursor(crtc, base);
6259 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6260 struct drm_file *file,
6262 uint32_t width, uint32_t height)
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 struct drm_i915_gem_object *obj;
6271 /* if we want to turn off the cursor ignore width and height */
6273 DRM_DEBUG_KMS("cursor off\n");
6276 mutex_lock(&dev->struct_mutex);
6280 /* Currently we only support 64x64 cursors */
6281 if (width != 64 || height != 64) {
6282 DRM_ERROR("we currently only support 64x64 cursors\n");
6286 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6287 if (&obj->base == NULL)
6290 if (obj->base.size < width * height * 4) {
6291 DRM_ERROR("buffer is to small\n");
6296 /* we only need to pin inside GTT if cursor is non-phy */
6297 mutex_lock(&dev->struct_mutex);
6298 if (!dev_priv->info->cursor_needs_physical) {
6299 if (obj->tiling_mode) {
6300 DRM_ERROR("cursor cannot be tiled\n");
6305 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6307 DRM_ERROR("failed to move cursor bo into the GTT\n");
6311 ret = i915_gem_object_put_fence(obj);
6313 DRM_ERROR("failed to release fence for cursor");
6317 addr = obj->gtt_offset;
6319 int align = IS_I830(dev) ? 16 * 1024 : 256;
6320 ret = i915_gem_attach_phys_object(dev, obj,
6321 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6324 DRM_ERROR("failed to attach phys object\n");
6327 addr = obj->phys_obj->handle->busaddr;
6331 I915_WRITE(CURSIZE, (height << 12) | width);
6334 if (intel_crtc->cursor_bo) {
6335 if (dev_priv->info->cursor_needs_physical) {
6336 if (intel_crtc->cursor_bo != obj)
6337 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6339 i915_gem_object_unpin(intel_crtc->cursor_bo);
6340 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6343 mutex_unlock(&dev->struct_mutex);
6345 intel_crtc->cursor_addr = addr;
6346 intel_crtc->cursor_bo = obj;
6347 intel_crtc->cursor_width = width;
6348 intel_crtc->cursor_height = height;
6350 intel_crtc_update_cursor(crtc, true);
6354 i915_gem_object_unpin(obj);
6356 mutex_unlock(&dev->struct_mutex);
6358 drm_gem_object_unreference_unlocked(&obj->base);
6362 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 intel_crtc->cursor_x = x;
6367 intel_crtc->cursor_y = y;
6369 intel_crtc_update_cursor(crtc, true);
6374 /** Sets the color ramps on behalf of RandR */
6375 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6376 u16 blue, int regno)
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380 intel_crtc->lut_r[regno] = red >> 8;
6381 intel_crtc->lut_g[regno] = green >> 8;
6382 intel_crtc->lut_b[regno] = blue >> 8;
6385 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6386 u16 *blue, int regno)
6388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 *red = intel_crtc->lut_r[regno] << 8;
6391 *green = intel_crtc->lut_g[regno] << 8;
6392 *blue = intel_crtc->lut_b[regno] << 8;
6395 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6396 u16 *blue, uint32_t start, uint32_t size)
6398 int end = (start + size > 256) ? 256 : start + size, i;
6399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6401 for (i = start; i < end; i++) {
6402 intel_crtc->lut_r[i] = red[i] >> 8;
6403 intel_crtc->lut_g[i] = green[i] >> 8;
6404 intel_crtc->lut_b[i] = blue[i] >> 8;
6407 intel_crtc_load_lut(crtc);
6411 * Get a pipe with a simple mode set on it for doing load-based monitor
6414 * It will be up to the load-detect code to adjust the pipe as appropriate for
6415 * its requirements. The pipe will be connected to no other encoders.
6417 * Currently this code will only succeed if there is a pipe with no encoders
6418 * configured for it. In the future, it could choose to temporarily disable
6419 * some outputs to free up a pipe for its use.
6421 * \return crtc, or NULL if no pipes are available.
6424 /* VESA 640x480x72Hz mode to set on the pipe */
6425 static struct drm_display_mode load_detect_mode = {
6426 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6427 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6430 static struct drm_framebuffer *
6431 intel_framebuffer_create(struct drm_device *dev,
6432 struct drm_mode_fb_cmd2 *mode_cmd,
6433 struct drm_i915_gem_object *obj)
6435 struct intel_framebuffer *intel_fb;
6438 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6440 drm_gem_object_unreference_unlocked(&obj->base);
6441 return ERR_PTR(-ENOMEM);
6444 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6446 drm_gem_object_unreference_unlocked(&obj->base);
6448 return ERR_PTR(ret);
6451 return &intel_fb->base;
6455 intel_framebuffer_pitch_for_width(int width, int bpp)
6457 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6458 return ALIGN(pitch, 64);
6462 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6464 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6465 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6468 static struct drm_framebuffer *
6469 intel_framebuffer_create_for_mode(struct drm_device *dev,
6470 struct drm_display_mode *mode,
6473 struct drm_i915_gem_object *obj;
6474 struct drm_mode_fb_cmd2 mode_cmd;
6476 obj = i915_gem_alloc_object(dev,
6477 intel_framebuffer_size_for_mode(mode, bpp));
6479 return ERR_PTR(-ENOMEM);
6481 mode_cmd.width = mode->hdisplay;
6482 mode_cmd.height = mode->vdisplay;
6483 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6485 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6487 return intel_framebuffer_create(dev, &mode_cmd, obj);
6490 static struct drm_framebuffer *
6491 mode_fits_in_fbdev(struct drm_device *dev,
6492 struct drm_display_mode *mode)
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495 struct drm_i915_gem_object *obj;
6496 struct drm_framebuffer *fb;
6498 if (dev_priv->fbdev == NULL)
6501 obj = dev_priv->fbdev->ifb.obj;
6505 fb = &dev_priv->fbdev->ifb.base;
6506 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6507 fb->bits_per_pixel))
6510 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6516 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6517 struct drm_display_mode *mode,
6518 struct intel_load_detect_pipe *old)
6520 struct intel_crtc *intel_crtc;
6521 struct intel_encoder *intel_encoder =
6522 intel_attached_encoder(connector);
6523 struct drm_crtc *possible_crtc;
6524 struct drm_encoder *encoder = &intel_encoder->base;
6525 struct drm_crtc *crtc = NULL;
6526 struct drm_device *dev = encoder->dev;
6527 struct drm_framebuffer *fb;
6530 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6531 connector->base.id, drm_get_connector_name(connector),
6532 encoder->base.id, drm_get_encoder_name(encoder));
6535 * Algorithm gets a little messy:
6537 * - if the connector already has an assigned crtc, use it (but make
6538 * sure it's on first)
6540 * - try to find the first unused crtc that can drive this connector,
6541 * and use that if we find one
6544 /* See if we already have a CRTC for this connector */
6545 if (encoder->crtc) {
6546 crtc = encoder->crtc;
6548 old->dpms_mode = connector->dpms;
6549 old->load_detect_temp = false;
6551 /* Make sure the crtc and connector are running */
6552 if (connector->dpms != DRM_MODE_DPMS_ON)
6553 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6558 /* Find an unused one (if possible) */
6559 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6561 if (!(encoder->possible_crtcs & (1 << i)))
6563 if (!possible_crtc->enabled) {
6564 crtc = possible_crtc;
6570 * If we didn't find an unused CRTC, don't use any.
6573 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6577 intel_encoder->new_crtc = to_intel_crtc(crtc);
6578 to_intel_connector(connector)->new_encoder = intel_encoder;
6580 intel_crtc = to_intel_crtc(crtc);
6581 old->dpms_mode = connector->dpms;
6582 old->load_detect_temp = true;
6583 old->release_fb = NULL;
6586 mode = &load_detect_mode;
6588 /* We need a framebuffer large enough to accommodate all accesses
6589 * that the plane may generate whilst we perform load detection.
6590 * We can not rely on the fbcon either being present (we get called
6591 * during its initialisation to detect all boot displays, or it may
6592 * not even exist) or that it is large enough to satisfy the
6595 fb = mode_fits_in_fbdev(dev, mode);
6597 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6598 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6599 old->release_fb = fb;
6601 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6603 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6607 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6608 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6609 if (old->release_fb)
6610 old->release_fb->funcs->destroy(old->release_fb);
6614 /* let the connector get through one full cycle before testing */
6615 intel_wait_for_vblank(dev, intel_crtc->pipe);
6619 connector->encoder = NULL;
6620 encoder->crtc = NULL;
6624 void intel_release_load_detect_pipe(struct drm_connector *connector,
6625 struct intel_load_detect_pipe *old)
6627 struct intel_encoder *intel_encoder =
6628 intel_attached_encoder(connector);
6629 struct drm_encoder *encoder = &intel_encoder->base;
6631 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6632 connector->base.id, drm_get_connector_name(connector),
6633 encoder->base.id, drm_get_encoder_name(encoder));
6635 if (old->load_detect_temp) {
6636 struct drm_crtc *crtc = encoder->crtc;
6638 to_intel_connector(connector)->new_encoder = NULL;
6639 intel_encoder->new_crtc = NULL;
6640 intel_set_mode(crtc, NULL, 0, 0, NULL);
6642 if (old->release_fb)
6643 old->release_fb->funcs->destroy(old->release_fb);
6648 /* Switch crtc and encoder back off if necessary */
6649 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6650 connector->funcs->dpms(connector, old->dpms_mode);
6653 /* Returns the clock of the currently programmed mode of the given pipe. */
6654 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6658 int pipe = intel_crtc->pipe;
6659 u32 dpll = I915_READ(DPLL(pipe));
6661 intel_clock_t clock;
6663 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6664 fp = I915_READ(FP0(pipe));
6666 fp = I915_READ(FP1(pipe));
6668 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6669 if (IS_PINEVIEW(dev)) {
6670 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6671 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6673 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6674 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6677 if (!IS_GEN2(dev)) {
6678 if (IS_PINEVIEW(dev))
6679 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6680 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6682 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6683 DPLL_FPA01_P1_POST_DIV_SHIFT);
6685 switch (dpll & DPLL_MODE_MASK) {
6686 case DPLLB_MODE_DAC_SERIAL:
6687 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6690 case DPLLB_MODE_LVDS:
6691 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6695 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6696 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6700 /* XXX: Handle the 100Mhz refclk */
6701 intel_clock(dev, 96000, &clock);
6703 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6706 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6707 DPLL_FPA01_P1_POST_DIV_SHIFT);
6710 if ((dpll & PLL_REF_INPUT_MASK) ==
6711 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6712 /* XXX: might not be 66MHz */
6713 intel_clock(dev, 66000, &clock);
6715 intel_clock(dev, 48000, &clock);
6717 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6720 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6721 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6723 if (dpll & PLL_P2_DIVIDE_BY_4)
6728 intel_clock(dev, 48000, &clock);
6732 /* XXX: It would be nice to validate the clocks, but we can't reuse
6733 * i830PllIsValid() because it relies on the xf86_config connector
6734 * configuration being accurate, which it isn't necessarily.
6740 /** Returns the currently programmed mode of the given pipe. */
6741 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6742 struct drm_crtc *crtc)
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6746 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6747 struct drm_display_mode *mode;
6748 int htot = I915_READ(HTOTAL(cpu_transcoder));
6749 int hsync = I915_READ(HSYNC(cpu_transcoder));
6750 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6751 int vsync = I915_READ(VSYNC(cpu_transcoder));
6753 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6757 mode->clock = intel_crtc_clock_get(dev, crtc);
6758 mode->hdisplay = (htot & 0xffff) + 1;
6759 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6760 mode->hsync_start = (hsync & 0xffff) + 1;
6761 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6762 mode->vdisplay = (vtot & 0xffff) + 1;
6763 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6764 mode->vsync_start = (vsync & 0xffff) + 1;
6765 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6767 drm_mode_set_name(mode);
6772 static void intel_increase_pllclock(struct drm_crtc *crtc)
6774 struct drm_device *dev = crtc->dev;
6775 drm_i915_private_t *dev_priv = dev->dev_private;
6776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6777 int pipe = intel_crtc->pipe;
6778 int dpll_reg = DPLL(pipe);
6781 if (HAS_PCH_SPLIT(dev))
6784 if (!dev_priv->lvds_downclock_avail)
6787 dpll = I915_READ(dpll_reg);
6788 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6789 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6791 assert_panel_unlocked(dev_priv, pipe);
6793 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6794 I915_WRITE(dpll_reg, dpll);
6795 intel_wait_for_vblank(dev, pipe);
6797 dpll = I915_READ(dpll_reg);
6798 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6799 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6803 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6805 struct drm_device *dev = crtc->dev;
6806 drm_i915_private_t *dev_priv = dev->dev_private;
6807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6809 if (HAS_PCH_SPLIT(dev))
6812 if (!dev_priv->lvds_downclock_avail)
6816 * Since this is called by a timer, we should never get here in
6819 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6820 int pipe = intel_crtc->pipe;
6821 int dpll_reg = DPLL(pipe);
6824 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6826 assert_panel_unlocked(dev_priv, pipe);
6828 dpll = I915_READ(dpll_reg);
6829 dpll |= DISPLAY_RATE_SELECT_FPA1;
6830 I915_WRITE(dpll_reg, dpll);
6831 intel_wait_for_vblank(dev, pipe);
6832 dpll = I915_READ(dpll_reg);
6833 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6834 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6839 void intel_mark_busy(struct drm_device *dev)
6841 i915_update_gfx_val(dev->dev_private);
6844 void intel_mark_idle(struct drm_device *dev)
6848 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6850 struct drm_device *dev = obj->base.dev;
6851 struct drm_crtc *crtc;
6853 if (!i915_powersave)
6856 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6860 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6861 intel_increase_pllclock(crtc);
6865 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6867 struct drm_device *dev = obj->base.dev;
6868 struct drm_crtc *crtc;
6870 if (!i915_powersave)
6873 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6877 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6878 intel_decrease_pllclock(crtc);
6882 static void intel_crtc_destroy(struct drm_crtc *crtc)
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 struct drm_device *dev = crtc->dev;
6886 struct intel_unpin_work *work;
6887 unsigned long flags;
6889 spin_lock_irqsave(&dev->event_lock, flags);
6890 work = intel_crtc->unpin_work;
6891 intel_crtc->unpin_work = NULL;
6892 spin_unlock_irqrestore(&dev->event_lock, flags);
6895 cancel_work_sync(&work->work);
6899 drm_crtc_cleanup(crtc);
6904 static void intel_unpin_work_fn(struct work_struct *__work)
6906 struct intel_unpin_work *work =
6907 container_of(__work, struct intel_unpin_work, work);
6909 mutex_lock(&work->dev->struct_mutex);
6910 intel_unpin_fb_obj(work->old_fb_obj);
6911 drm_gem_object_unreference(&work->pending_flip_obj->base);
6912 drm_gem_object_unreference(&work->old_fb_obj->base);
6914 intel_update_fbc(work->dev);
6915 mutex_unlock(&work->dev->struct_mutex);
6919 static void do_intel_finish_page_flip(struct drm_device *dev,
6920 struct drm_crtc *crtc)
6922 drm_i915_private_t *dev_priv = dev->dev_private;
6923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924 struct intel_unpin_work *work;
6925 struct drm_i915_gem_object *obj;
6926 struct drm_pending_vblank_event *e;
6927 struct timeval tvbl;
6928 unsigned long flags;
6930 /* Ignore early vblank irqs */
6931 if (intel_crtc == NULL)
6934 spin_lock_irqsave(&dev->event_lock, flags);
6935 work = intel_crtc->unpin_work;
6936 if (work == NULL || !work->pending) {
6937 spin_unlock_irqrestore(&dev->event_lock, flags);
6941 intel_crtc->unpin_work = NULL;
6945 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6947 e->event.tv_sec = tvbl.tv_sec;
6948 e->event.tv_usec = tvbl.tv_usec;
6950 list_add_tail(&e->base.link,
6951 &e->base.file_priv->event_list);
6952 wake_up_interruptible(&e->base.file_priv->event_wait);
6955 drm_vblank_put(dev, intel_crtc->pipe);
6957 spin_unlock_irqrestore(&dev->event_lock, flags);
6959 obj = work->old_fb_obj;
6961 atomic_clear_mask(1 << intel_crtc->plane,
6962 &obj->pending_flip.counter);
6964 wake_up(&dev_priv->pending_flip_queue);
6965 schedule_work(&work->work);
6967 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6970 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6972 drm_i915_private_t *dev_priv = dev->dev_private;
6973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6975 do_intel_finish_page_flip(dev, crtc);
6978 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6980 drm_i915_private_t *dev_priv = dev->dev_private;
6981 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6983 do_intel_finish_page_flip(dev, crtc);
6986 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6988 drm_i915_private_t *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc =
6990 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6991 unsigned long flags;
6993 spin_lock_irqsave(&dev->event_lock, flags);
6994 if (intel_crtc->unpin_work) {
6995 if ((++intel_crtc->unpin_work->pending) > 1)
6996 DRM_ERROR("Prepared flip multiple times\n");
6998 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7000 spin_unlock_irqrestore(&dev->event_lock, flags);
7003 static int intel_gen2_queue_flip(struct drm_device *dev,
7004 struct drm_crtc *crtc,
7005 struct drm_framebuffer *fb,
7006 struct drm_i915_gem_object *obj)
7008 struct drm_i915_private *dev_priv = dev->dev_private;
7009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7011 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7014 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7018 ret = intel_ring_begin(ring, 6);
7022 /* Can't queue multiple flips, so wait for the previous
7023 * one to finish before executing the next.
7025 if (intel_crtc->plane)
7026 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7028 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7029 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7030 intel_ring_emit(ring, MI_NOOP);
7031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7033 intel_ring_emit(ring, fb->pitches[0]);
7034 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7035 intel_ring_emit(ring, 0); /* aux display base address, unused */
7036 intel_ring_advance(ring);
7040 intel_unpin_fb_obj(obj);
7045 static int intel_gen3_queue_flip(struct drm_device *dev,
7046 struct drm_crtc *crtc,
7047 struct drm_framebuffer *fb,
7048 struct drm_i915_gem_object *obj)
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7056 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7060 ret = intel_ring_begin(ring, 6);
7064 if (intel_crtc->plane)
7065 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7067 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7068 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7069 intel_ring_emit(ring, MI_NOOP);
7070 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7071 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7072 intel_ring_emit(ring, fb->pitches[0]);
7073 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7074 intel_ring_emit(ring, MI_NOOP);
7076 intel_ring_advance(ring);
7080 intel_unpin_fb_obj(obj);
7085 static int intel_gen4_queue_flip(struct drm_device *dev,
7086 struct drm_crtc *crtc,
7087 struct drm_framebuffer *fb,
7088 struct drm_i915_gem_object *obj)
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092 uint32_t pf, pipesrc;
7093 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7096 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7100 ret = intel_ring_begin(ring, 4);
7104 /* i965+ uses the linear or tiled offsets from the
7105 * Display Registers (which do not change across a page-flip)
7106 * so we need only reprogram the base address.
7108 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7110 intel_ring_emit(ring, fb->pitches[0]);
7111 intel_ring_emit(ring,
7112 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7115 /* XXX Enabling the panel-fitter across page-flip is so far
7116 * untested on non-native modes, so ignore it for now.
7117 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7120 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7121 intel_ring_emit(ring, pf | pipesrc);
7122 intel_ring_advance(ring);
7126 intel_unpin_fb_obj(obj);
7131 static int intel_gen6_queue_flip(struct drm_device *dev,
7132 struct drm_crtc *crtc,
7133 struct drm_framebuffer *fb,
7134 struct drm_i915_gem_object *obj)
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7139 uint32_t pf, pipesrc;
7142 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7146 ret = intel_ring_begin(ring, 4);
7150 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7151 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7152 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7153 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7155 /* Contrary to the suggestions in the documentation,
7156 * "Enable Panel Fitter" does not seem to be required when page
7157 * flipping with a non-native mode, and worse causes a normal
7159 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7162 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7163 intel_ring_emit(ring, pf | pipesrc);
7164 intel_ring_advance(ring);
7168 intel_unpin_fb_obj(obj);
7174 * On gen7 we currently use the blit ring because (in early silicon at least)
7175 * the render ring doesn't give us interrpts for page flip completion, which
7176 * means clients will hang after the first flip is queued. Fortunately the
7177 * blit ring generates interrupts properly, so use it instead.
7179 static int intel_gen7_queue_flip(struct drm_device *dev,
7180 struct drm_crtc *crtc,
7181 struct drm_framebuffer *fb,
7182 struct drm_i915_gem_object *obj)
7184 struct drm_i915_private *dev_priv = dev->dev_private;
7185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7187 uint32_t plane_bit = 0;
7190 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7194 switch(intel_crtc->plane) {
7196 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7199 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7202 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7205 WARN_ONCE(1, "unknown plane in flip command\n");
7210 ret = intel_ring_begin(ring, 4);
7214 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7215 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7216 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7217 intel_ring_emit(ring, (MI_NOOP));
7218 intel_ring_advance(ring);
7222 intel_unpin_fb_obj(obj);
7227 static int intel_default_queue_flip(struct drm_device *dev,
7228 struct drm_crtc *crtc,
7229 struct drm_framebuffer *fb,
7230 struct drm_i915_gem_object *obj)
7235 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7236 struct drm_framebuffer *fb,
7237 struct drm_pending_vblank_event *event)
7239 struct drm_device *dev = crtc->dev;
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 struct intel_framebuffer *intel_fb;
7242 struct drm_i915_gem_object *obj;
7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7244 struct intel_unpin_work *work;
7245 unsigned long flags;
7248 /* Can't change pixel format via MI display flips. */
7249 if (fb->pixel_format != crtc->fb->pixel_format)
7253 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7254 * Note that pitch changes could also affect these register.
7256 if (INTEL_INFO(dev)->gen > 3 &&
7257 (fb->offsets[0] != crtc->fb->offsets[0] ||
7258 fb->pitches[0] != crtc->fb->pitches[0]))
7261 work = kzalloc(sizeof *work, GFP_KERNEL);
7265 work->event = event;
7266 work->dev = crtc->dev;
7267 intel_fb = to_intel_framebuffer(crtc->fb);
7268 work->old_fb_obj = intel_fb->obj;
7269 INIT_WORK(&work->work, intel_unpin_work_fn);
7271 ret = drm_vblank_get(dev, intel_crtc->pipe);
7275 /* We borrow the event spin lock for protecting unpin_work */
7276 spin_lock_irqsave(&dev->event_lock, flags);
7277 if (intel_crtc->unpin_work) {
7278 spin_unlock_irqrestore(&dev->event_lock, flags);
7280 drm_vblank_put(dev, intel_crtc->pipe);
7282 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7285 intel_crtc->unpin_work = work;
7286 spin_unlock_irqrestore(&dev->event_lock, flags);
7288 intel_fb = to_intel_framebuffer(fb);
7289 obj = intel_fb->obj;
7291 ret = i915_mutex_lock_interruptible(dev);
7295 /* Reference the objects for the scheduled work. */
7296 drm_gem_object_reference(&work->old_fb_obj->base);
7297 drm_gem_object_reference(&obj->base);
7301 work->pending_flip_obj = obj;
7303 work->enable_stall_check = true;
7305 /* Block clients from rendering to the new back buffer until
7306 * the flip occurs and the object is no longer visible.
7308 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7310 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7312 goto cleanup_pending;
7314 intel_disable_fbc(dev);
7315 intel_mark_fb_busy(obj);
7316 mutex_unlock(&dev->struct_mutex);
7318 trace_i915_flip_request(intel_crtc->plane, obj);
7323 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7324 drm_gem_object_unreference(&work->old_fb_obj->base);
7325 drm_gem_object_unreference(&obj->base);
7326 mutex_unlock(&dev->struct_mutex);
7329 spin_lock_irqsave(&dev->event_lock, flags);
7330 intel_crtc->unpin_work = NULL;
7331 spin_unlock_irqrestore(&dev->event_lock, flags);
7333 drm_vblank_put(dev, intel_crtc->pipe);
7340 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7341 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7342 .load_lut = intel_crtc_load_lut,
7343 .disable = intel_crtc_noop,
7346 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7348 struct intel_encoder *other_encoder;
7349 struct drm_crtc *crtc = &encoder->new_crtc->base;
7354 list_for_each_entry(other_encoder,
7355 &crtc->dev->mode_config.encoder_list,
7358 if (&other_encoder->new_crtc->base != crtc ||
7359 encoder == other_encoder)
7368 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7369 struct drm_crtc *crtc)
7371 struct drm_device *dev;
7372 struct drm_crtc *tmp;
7375 WARN(!crtc, "checking null crtc?\n");
7379 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7385 if (encoder->possible_crtcs & crtc_mask)
7391 * intel_modeset_update_staged_output_state
7393 * Updates the staged output configuration state, e.g. after we've read out the
7396 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7398 struct intel_encoder *encoder;
7399 struct intel_connector *connector;
7401 list_for_each_entry(connector, &dev->mode_config.connector_list,
7403 connector->new_encoder =
7404 to_intel_encoder(connector->base.encoder);
7407 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7410 to_intel_crtc(encoder->base.crtc);
7415 * intel_modeset_commit_output_state
7417 * This function copies the stage display pipe configuration to the real one.
7419 static void intel_modeset_commit_output_state(struct drm_device *dev)
7421 struct intel_encoder *encoder;
7422 struct intel_connector *connector;
7424 list_for_each_entry(connector, &dev->mode_config.connector_list,
7426 connector->base.encoder = &connector->new_encoder->base;
7429 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7431 encoder->base.crtc = &encoder->new_crtc->base;
7435 static struct drm_display_mode *
7436 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7437 struct drm_display_mode *mode)
7439 struct drm_device *dev = crtc->dev;
7440 struct drm_display_mode *adjusted_mode;
7441 struct drm_encoder_helper_funcs *encoder_funcs;
7442 struct intel_encoder *encoder;
7444 adjusted_mode = drm_mode_duplicate(dev, mode);
7446 return ERR_PTR(-ENOMEM);
7448 /* Pass our mode to the connectors and the CRTC to give them a chance to
7449 * adjust it according to limitations or connector properties, and also
7450 * a chance to reject the mode entirely.
7452 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7455 if (&encoder->new_crtc->base != crtc)
7457 encoder_funcs = encoder->base.helper_private;
7458 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7460 DRM_DEBUG_KMS("Encoder fixup failed\n");
7465 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7466 DRM_DEBUG_KMS("CRTC fixup failed\n");
7469 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7471 return adjusted_mode;
7473 drm_mode_destroy(dev, adjusted_mode);
7474 return ERR_PTR(-EINVAL);
7477 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7478 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7480 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7481 unsigned *prepare_pipes, unsigned *disable_pipes)
7483 struct intel_crtc *intel_crtc;
7484 struct drm_device *dev = crtc->dev;
7485 struct intel_encoder *encoder;
7486 struct intel_connector *connector;
7487 struct drm_crtc *tmp_crtc;
7489 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7491 /* Check which crtcs have changed outputs connected to them, these need
7492 * to be part of the prepare_pipes mask. We don't (yet) support global
7493 * modeset across multiple crtcs, so modeset_pipes will only have one
7494 * bit set at most. */
7495 list_for_each_entry(connector, &dev->mode_config.connector_list,
7497 if (connector->base.encoder == &connector->new_encoder->base)
7500 if (connector->base.encoder) {
7501 tmp_crtc = connector->base.encoder->crtc;
7503 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7506 if (connector->new_encoder)
7508 1 << connector->new_encoder->new_crtc->pipe;
7511 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7513 if (encoder->base.crtc == &encoder->new_crtc->base)
7516 if (encoder->base.crtc) {
7517 tmp_crtc = encoder->base.crtc;
7519 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7522 if (encoder->new_crtc)
7523 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7526 /* Check for any pipes that will be fully disabled ... */
7527 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7531 /* Don't try to disable disabled crtcs. */
7532 if (!intel_crtc->base.enabled)
7535 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7537 if (encoder->new_crtc == intel_crtc)
7542 *disable_pipes |= 1 << intel_crtc->pipe;
7546 /* set_mode is also used to update properties on life display pipes. */
7547 intel_crtc = to_intel_crtc(crtc);
7549 *prepare_pipes |= 1 << intel_crtc->pipe;
7551 /* We only support modeset on one single crtc, hence we need to do that
7552 * only for the passed in crtc iff we change anything else than just
7555 * This is actually not true, to be fully compatible with the old crtc
7556 * helper we automatically disable _any_ output (i.e. doesn't need to be
7557 * connected to the crtc we're modesetting on) if it's disconnected.
7558 * Which is a rather nutty api (since changed the output configuration
7559 * without userspace's explicit request can lead to confusion), but
7560 * alas. Hence we currently need to modeset on all pipes we prepare. */
7562 *modeset_pipes = *prepare_pipes;
7564 /* ... and mask these out. */
7565 *modeset_pipes &= ~(*disable_pipes);
7566 *prepare_pipes &= ~(*disable_pipes);
7569 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7571 struct drm_encoder *encoder;
7572 struct drm_device *dev = crtc->dev;
7574 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7575 if (encoder->crtc == crtc)
7582 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7584 struct intel_encoder *intel_encoder;
7585 struct intel_crtc *intel_crtc;
7586 struct drm_connector *connector;
7588 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7590 if (!intel_encoder->base.crtc)
7593 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7595 if (prepare_pipes & (1 << intel_crtc->pipe))
7596 intel_encoder->connectors_active = false;
7599 intel_modeset_commit_output_state(dev);
7601 /* Update computed state. */
7602 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7604 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7607 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7608 if (!connector->encoder || !connector->encoder->crtc)
7611 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7613 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7614 struct drm_property *dpms_property =
7615 dev->mode_config.dpms_property;
7617 connector->dpms = DRM_MODE_DPMS_ON;
7618 drm_connector_property_set_value(connector,
7622 intel_encoder = to_intel_encoder(connector->encoder);
7623 intel_encoder->connectors_active = true;
7629 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7630 list_for_each_entry((intel_crtc), \
7631 &(dev)->mode_config.crtc_list, \
7633 if (mask & (1 <<(intel_crtc)->pipe)) \
7636 intel_modeset_check_state(struct drm_device *dev)
7638 struct intel_crtc *crtc;
7639 struct intel_encoder *encoder;
7640 struct intel_connector *connector;
7642 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 /* This also checks the encoder/connector hw state with the
7645 * ->get_hw_state callbacks. */
7646 intel_connector_check_state(connector);
7648 WARN(&connector->new_encoder->base != connector->base.encoder,
7649 "connector's staged encoder doesn't match current encoder\n");
7652 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7654 bool enabled = false;
7655 bool active = false;
7656 enum pipe pipe, tracked_pipe;
7658 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7659 encoder->base.base.id,
7660 drm_get_encoder_name(&encoder->base));
7662 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7663 "encoder's stage crtc doesn't match current crtc\n");
7664 WARN(encoder->connectors_active && !encoder->base.crtc,
7665 "encoder's active_connectors set, but no crtc\n");
7667 list_for_each_entry(connector, &dev->mode_config.connector_list,
7669 if (connector->base.encoder != &encoder->base)
7672 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7675 WARN(!!encoder->base.crtc != enabled,
7676 "encoder's enabled state mismatch "
7677 "(expected %i, found %i)\n",
7678 !!encoder->base.crtc, enabled);
7679 WARN(active && !encoder->base.crtc,
7680 "active encoder with no crtc\n");
7682 WARN(encoder->connectors_active != active,
7683 "encoder's computed active state doesn't match tracked active state "
7684 "(expected %i, found %i)\n", active, encoder->connectors_active);
7686 active = encoder->get_hw_state(encoder, &pipe);
7687 WARN(active != encoder->connectors_active,
7688 "encoder's hw state doesn't match sw tracking "
7689 "(expected %i, found %i)\n",
7690 encoder->connectors_active, active);
7692 if (!encoder->base.crtc)
7695 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7696 WARN(active && pipe != tracked_pipe,
7697 "active encoder's pipe doesn't match"
7698 "(expected %i, found %i)\n",
7699 tracked_pipe, pipe);
7703 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7705 bool enabled = false;
7706 bool active = false;
7708 DRM_DEBUG_KMS("[CRTC:%d]\n",
7709 crtc->base.base.id);
7711 WARN(crtc->active && !crtc->base.enabled,
7712 "active crtc, but not enabled in sw tracking\n");
7714 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7716 if (encoder->base.crtc != &crtc->base)
7719 if (encoder->connectors_active)
7722 WARN(active != crtc->active,
7723 "crtc's computed active state doesn't match tracked active state "
7724 "(expected %i, found %i)\n", active, crtc->active);
7725 WARN(enabled != crtc->base.enabled,
7726 "crtc's computed enabled state doesn't match tracked enabled state "
7727 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7729 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7733 bool intel_set_mode(struct drm_crtc *crtc,
7734 struct drm_display_mode *mode,
7735 int x, int y, struct drm_framebuffer *fb)
7737 struct drm_device *dev = crtc->dev;
7738 drm_i915_private_t *dev_priv = dev->dev_private;
7739 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7740 struct intel_crtc *intel_crtc;
7741 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7744 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7745 &prepare_pipes, &disable_pipes);
7747 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7748 modeset_pipes, prepare_pipes, disable_pipes);
7750 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7751 intel_crtc_disable(&intel_crtc->base);
7753 saved_hwmode = crtc->hwmode;
7754 saved_mode = crtc->mode;
7756 /* Hack: Because we don't (yet) support global modeset on multiple
7757 * crtcs, we don't keep track of the new mode for more than one crtc.
7758 * Hence simply check whether any bit is set in modeset_pipes in all the
7759 * pieces of code that are not yet converted to deal with mutliple crtcs
7760 * changing their mode at the same time. */
7761 adjusted_mode = NULL;
7762 if (modeset_pipes) {
7763 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7764 if (IS_ERR(adjusted_mode)) {
7769 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7770 if (intel_crtc->base.enabled)
7771 dev_priv->display.crtc_disable(&intel_crtc->base);
7774 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7775 * to set it here already despite that we pass it down the callchain.
7780 /* Only after disabling all output pipelines that will be changed can we
7781 * update the the output configuration. */
7782 intel_modeset_update_state(dev, prepare_pipes);
7784 if (dev_priv->display.modeset_global_resources)
7785 dev_priv->display.modeset_global_resources(dev);
7787 /* Set up the DPLL and any encoders state that needs to adjust or depend
7790 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7791 ret = !intel_crtc_mode_set(&intel_crtc->base,
7792 mode, adjusted_mode,
7798 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7799 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7800 dev_priv->display.crtc_enable(&intel_crtc->base);
7802 if (modeset_pipes) {
7803 /* Store real post-adjustment hardware mode. */
7804 crtc->hwmode = *adjusted_mode;
7806 /* Calculate and store various constants which
7807 * are later needed by vblank and swap-completion
7808 * timestamping. They are derived from true hwmode.
7810 drm_calc_timestamping_constants(crtc);
7813 /* FIXME: add subpixel order */
7815 drm_mode_destroy(dev, adjusted_mode);
7816 if (!ret && crtc->enabled) {
7817 crtc->hwmode = saved_hwmode;
7818 crtc->mode = saved_mode;
7820 intel_modeset_check_state(dev);
7826 #undef for_each_intel_crtc_masked
7828 static void intel_set_config_free(struct intel_set_config *config)
7833 kfree(config->save_connector_encoders);
7834 kfree(config->save_encoder_crtcs);
7838 static int intel_set_config_save_state(struct drm_device *dev,
7839 struct intel_set_config *config)
7841 struct drm_encoder *encoder;
7842 struct drm_connector *connector;
7845 config->save_encoder_crtcs =
7846 kcalloc(dev->mode_config.num_encoder,
7847 sizeof(struct drm_crtc *), GFP_KERNEL);
7848 if (!config->save_encoder_crtcs)
7851 config->save_connector_encoders =
7852 kcalloc(dev->mode_config.num_connector,
7853 sizeof(struct drm_encoder *), GFP_KERNEL);
7854 if (!config->save_connector_encoders)
7857 /* Copy data. Note that driver private data is not affected.
7858 * Should anything bad happen only the expected state is
7859 * restored, not the drivers personal bookkeeping.
7862 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7863 config->save_encoder_crtcs[count++] = encoder->crtc;
7867 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7868 config->save_connector_encoders[count++] = connector->encoder;
7874 static void intel_set_config_restore_state(struct drm_device *dev,
7875 struct intel_set_config *config)
7877 struct intel_encoder *encoder;
7878 struct intel_connector *connector;
7882 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7884 to_intel_crtc(config->save_encoder_crtcs[count++]);
7888 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7889 connector->new_encoder =
7890 to_intel_encoder(config->save_connector_encoders[count++]);
7895 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7896 struct intel_set_config *config)
7899 /* We should be able to check here if the fb has the same properties
7900 * and then just flip_or_move it */
7901 if (set->crtc->fb != set->fb) {
7902 /* If we have no fb then treat it as a full mode set */
7903 if (set->crtc->fb == NULL) {
7904 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7905 config->mode_changed = true;
7906 } else if (set->fb == NULL) {
7907 config->mode_changed = true;
7908 } else if (set->fb->depth != set->crtc->fb->depth) {
7909 config->mode_changed = true;
7910 } else if (set->fb->bits_per_pixel !=
7911 set->crtc->fb->bits_per_pixel) {
7912 config->mode_changed = true;
7914 config->fb_changed = true;
7917 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7918 config->fb_changed = true;
7920 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7921 DRM_DEBUG_KMS("modes are different, full mode set\n");
7922 drm_mode_debug_printmodeline(&set->crtc->mode);
7923 drm_mode_debug_printmodeline(set->mode);
7924 config->mode_changed = true;
7929 intel_modeset_stage_output_state(struct drm_device *dev,
7930 struct drm_mode_set *set,
7931 struct intel_set_config *config)
7933 struct drm_crtc *new_crtc;
7934 struct intel_connector *connector;
7935 struct intel_encoder *encoder;
7938 /* The upper layers ensure that we either disabl a crtc or have a list
7939 * of connectors. For paranoia, double-check this. */
7940 WARN_ON(!set->fb && (set->num_connectors != 0));
7941 WARN_ON(set->fb && (set->num_connectors == 0));
7944 list_for_each_entry(connector, &dev->mode_config.connector_list,
7946 /* Otherwise traverse passed in connector list and get encoders
7948 for (ro = 0; ro < set->num_connectors; ro++) {
7949 if (set->connectors[ro] == &connector->base) {
7950 connector->new_encoder = connector->encoder;
7955 /* If we disable the crtc, disable all its connectors. Also, if
7956 * the connector is on the changing crtc but not on the new
7957 * connector list, disable it. */
7958 if ((!set->fb || ro == set->num_connectors) &&
7959 connector->base.encoder &&
7960 connector->base.encoder->crtc == set->crtc) {
7961 connector->new_encoder = NULL;
7963 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7964 connector->base.base.id,
7965 drm_get_connector_name(&connector->base));
7969 if (&connector->new_encoder->base != connector->base.encoder) {
7970 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7971 config->mode_changed = true;
7974 /* Disable all disconnected encoders. */
7975 if (connector->base.status == connector_status_disconnected)
7976 connector->new_encoder = NULL;
7978 /* connector->new_encoder is now updated for all connectors. */
7980 /* Update crtc of enabled connectors. */
7982 list_for_each_entry(connector, &dev->mode_config.connector_list,
7984 if (!connector->new_encoder)
7987 new_crtc = connector->new_encoder->base.crtc;
7989 for (ro = 0; ro < set->num_connectors; ro++) {
7990 if (set->connectors[ro] == &connector->base)
7991 new_crtc = set->crtc;
7994 /* Make sure the new CRTC will work with the encoder */
7995 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7999 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8001 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8002 connector->base.base.id,
8003 drm_get_connector_name(&connector->base),
8007 /* Check for any encoders that needs to be disabled. */
8008 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8010 list_for_each_entry(connector,
8011 &dev->mode_config.connector_list,
8013 if (connector->new_encoder == encoder) {
8014 WARN_ON(!connector->new_encoder->new_crtc);
8019 encoder->new_crtc = NULL;
8021 /* Only now check for crtc changes so we don't miss encoders
8022 * that will be disabled. */
8023 if (&encoder->new_crtc->base != encoder->base.crtc) {
8024 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8025 config->mode_changed = true;
8028 /* Now we've also updated encoder->new_crtc for all encoders. */
8033 static int intel_crtc_set_config(struct drm_mode_set *set)
8035 struct drm_device *dev;
8036 struct drm_mode_set save_set;
8037 struct intel_set_config *config;
8042 BUG_ON(!set->crtc->helper_private);
8047 /* The fb helper likes to play gross jokes with ->mode_set_config.
8048 * Unfortunately the crtc helper doesn't do much at all for this case,
8049 * so we have to cope with this madness until the fb helper is fixed up. */
8050 if (set->fb && set->num_connectors == 0)
8054 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8055 set->crtc->base.id, set->fb->base.id,
8056 (int)set->num_connectors, set->x, set->y);
8058 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8061 dev = set->crtc->dev;
8064 config = kzalloc(sizeof(*config), GFP_KERNEL);
8068 ret = intel_set_config_save_state(dev, config);
8072 save_set.crtc = set->crtc;
8073 save_set.mode = &set->crtc->mode;
8074 save_set.x = set->crtc->x;
8075 save_set.y = set->crtc->y;
8076 save_set.fb = set->crtc->fb;
8078 /* Compute whether we need a full modeset, only an fb base update or no
8079 * change at all. In the future we might also check whether only the
8080 * mode changed, e.g. for LVDS where we only change the panel fitter in
8082 intel_set_config_compute_mode_changes(set, config);
8084 ret = intel_modeset_stage_output_state(dev, set, config);
8088 if (config->mode_changed) {
8090 DRM_DEBUG_KMS("attempting to set mode from"
8092 drm_mode_debug_printmodeline(set->mode);
8095 if (!intel_set_mode(set->crtc, set->mode,
8096 set->x, set->y, set->fb)) {
8097 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8098 set->crtc->base.id);
8102 } else if (config->fb_changed) {
8103 ret = intel_pipe_set_base(set->crtc,
8104 set->x, set->y, set->fb);
8107 intel_set_config_free(config);
8112 intel_set_config_restore_state(dev, config);
8114 /* Try to restore the config */
8115 if (config->mode_changed &&
8116 !intel_set_mode(save_set.crtc, save_set.mode,
8117 save_set.x, save_set.y, save_set.fb))
8118 DRM_ERROR("failed to restore config after modeset failure\n");
8121 intel_set_config_free(config);
8125 static const struct drm_crtc_funcs intel_crtc_funcs = {
8126 .cursor_set = intel_crtc_cursor_set,
8127 .cursor_move = intel_crtc_cursor_move,
8128 .gamma_set = intel_crtc_gamma_set,
8129 .set_config = intel_crtc_set_config,
8130 .destroy = intel_crtc_destroy,
8131 .page_flip = intel_crtc_page_flip,
8134 static void intel_cpu_pll_init(struct drm_device *dev)
8136 if (IS_HASWELL(dev))
8137 intel_ddi_pll_init(dev);
8140 static void intel_pch_pll_init(struct drm_device *dev)
8142 drm_i915_private_t *dev_priv = dev->dev_private;
8145 if (dev_priv->num_pch_pll == 0) {
8146 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8150 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8151 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8152 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8153 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8157 static void intel_crtc_init(struct drm_device *dev, int pipe)
8159 drm_i915_private_t *dev_priv = dev->dev_private;
8160 struct intel_crtc *intel_crtc;
8163 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8164 if (intel_crtc == NULL)
8167 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8169 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8170 for (i = 0; i < 256; i++) {
8171 intel_crtc->lut_r[i] = i;
8172 intel_crtc->lut_g[i] = i;
8173 intel_crtc->lut_b[i] = i;
8176 /* Swap pipes & planes for FBC on pre-965 */
8177 intel_crtc->pipe = pipe;
8178 intel_crtc->plane = pipe;
8179 intel_crtc->cpu_transcoder = pipe;
8180 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8181 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8182 intel_crtc->plane = !pipe;
8185 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8186 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8187 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8188 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8190 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8192 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8195 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8196 struct drm_file *file)
8198 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8199 struct drm_mode_object *drmmode_obj;
8200 struct intel_crtc *crtc;
8202 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8205 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8206 DRM_MODE_OBJECT_CRTC);
8209 DRM_ERROR("no such CRTC id\n");
8213 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8214 pipe_from_crtc_id->pipe = crtc->pipe;
8219 static int intel_encoder_clones(struct intel_encoder *encoder)
8221 struct drm_device *dev = encoder->base.dev;
8222 struct intel_encoder *source_encoder;
8226 list_for_each_entry(source_encoder,
8227 &dev->mode_config.encoder_list, base.head) {
8229 if (encoder == source_encoder)
8230 index_mask |= (1 << entry);
8232 /* Intel hw has only one MUX where enocoders could be cloned. */
8233 if (encoder->cloneable && source_encoder->cloneable)
8234 index_mask |= (1 << entry);
8242 static bool has_edp_a(struct drm_device *dev)
8244 struct drm_i915_private *dev_priv = dev->dev_private;
8246 if (!IS_MOBILE(dev))
8249 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8253 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8259 static void intel_setup_outputs(struct drm_device *dev)
8261 struct drm_i915_private *dev_priv = dev->dev_private;
8262 struct intel_encoder *encoder;
8263 bool dpd_is_edp = false;
8266 has_lvds = intel_lvds_init(dev);
8267 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8268 /* disable the panel fitter on everything but LVDS */
8269 I915_WRITE(PFIT_CONTROL, 0);
8272 intel_crt_init(dev);
8274 if (IS_HASWELL(dev)) {
8277 /* Haswell uses DDI functions to detect digital outputs */
8278 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8279 /* DDI A only supports eDP */
8281 intel_ddi_init(dev, PORT_A);
8283 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8285 found = I915_READ(SFUSE_STRAP);
8287 if (found & SFUSE_STRAP_DDIB_DETECTED)
8288 intel_ddi_init(dev, PORT_B);
8289 if (found & SFUSE_STRAP_DDIC_DETECTED)
8290 intel_ddi_init(dev, PORT_C);
8291 if (found & SFUSE_STRAP_DDID_DETECTED)
8292 intel_ddi_init(dev, PORT_D);
8293 } else if (HAS_PCH_SPLIT(dev)) {
8295 dpd_is_edp = intel_dpd_is_edp(dev);
8298 intel_dp_init(dev, DP_A, PORT_A);
8300 if (I915_READ(HDMIB) & PORT_DETECTED) {
8301 /* PCH SDVOB multiplex with HDMIB */
8302 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8304 intel_hdmi_init(dev, HDMIB, PORT_B);
8305 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8306 intel_dp_init(dev, PCH_DP_B, PORT_B);
8309 if (I915_READ(HDMIC) & PORT_DETECTED)
8310 intel_hdmi_init(dev, HDMIC, PORT_C);
8312 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8313 intel_hdmi_init(dev, HDMID, PORT_D);
8315 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8316 intel_dp_init(dev, PCH_DP_C, PORT_C);
8318 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8319 intel_dp_init(dev, PCH_DP_D, PORT_D);
8320 } else if (IS_VALLEYVIEW(dev)) {
8323 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8324 if (I915_READ(DP_C) & DP_DETECTED)
8325 intel_dp_init(dev, DP_C, PORT_C);
8327 if (I915_READ(SDVOB) & PORT_DETECTED) {
8328 /* SDVOB multiplex with HDMIB */
8329 found = intel_sdvo_init(dev, SDVOB, true);
8331 intel_hdmi_init(dev, SDVOB, PORT_B);
8332 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8333 intel_dp_init(dev, DP_B, PORT_B);
8336 if (I915_READ(SDVOC) & PORT_DETECTED)
8337 intel_hdmi_init(dev, SDVOC, PORT_C);
8339 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8342 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8343 DRM_DEBUG_KMS("probing SDVOB\n");
8344 found = intel_sdvo_init(dev, SDVOB, true);
8345 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8346 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8347 intel_hdmi_init(dev, SDVOB, PORT_B);
8350 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8351 DRM_DEBUG_KMS("probing DP_B\n");
8352 intel_dp_init(dev, DP_B, PORT_B);
8356 /* Before G4X SDVOC doesn't have its own detect register */
8358 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8359 DRM_DEBUG_KMS("probing SDVOC\n");
8360 found = intel_sdvo_init(dev, SDVOC, false);
8363 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8365 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8366 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8367 intel_hdmi_init(dev, SDVOC, PORT_C);
8369 if (SUPPORTS_INTEGRATED_DP(dev)) {
8370 DRM_DEBUG_KMS("probing DP_C\n");
8371 intel_dp_init(dev, DP_C, PORT_C);
8375 if (SUPPORTS_INTEGRATED_DP(dev) &&
8376 (I915_READ(DP_D) & DP_DETECTED)) {
8377 DRM_DEBUG_KMS("probing DP_D\n");
8378 intel_dp_init(dev, DP_D, PORT_D);
8380 } else if (IS_GEN2(dev))
8381 intel_dvo_init(dev);
8383 if (SUPPORTS_TV(dev))
8386 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8387 encoder->base.possible_crtcs = encoder->crtc_mask;
8388 encoder->base.possible_clones =
8389 intel_encoder_clones(encoder);
8392 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8393 ironlake_init_pch_refclk(dev);
8395 drm_helper_move_panel_connectors_to_head(dev);
8398 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8400 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8402 drm_framebuffer_cleanup(fb);
8403 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8408 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8409 struct drm_file *file,
8410 unsigned int *handle)
8412 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8413 struct drm_i915_gem_object *obj = intel_fb->obj;
8415 return drm_gem_handle_create(file, &obj->base, handle);
8418 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8419 .destroy = intel_user_framebuffer_destroy,
8420 .create_handle = intel_user_framebuffer_create_handle,
8423 int intel_framebuffer_init(struct drm_device *dev,
8424 struct intel_framebuffer *intel_fb,
8425 struct drm_mode_fb_cmd2 *mode_cmd,
8426 struct drm_i915_gem_object *obj)
8430 if (obj->tiling_mode == I915_TILING_Y)
8433 if (mode_cmd->pitches[0] & 63)
8436 /* FIXME <= Gen4 stride limits are bit unclear */
8437 if (mode_cmd->pitches[0] > 32768)
8440 if (obj->tiling_mode != I915_TILING_NONE &&
8441 mode_cmd->pitches[0] != obj->stride)
8444 /* Reject formats not supported by any plane early. */
8445 switch (mode_cmd->pixel_format) {
8447 case DRM_FORMAT_RGB565:
8448 case DRM_FORMAT_XRGB8888:
8449 case DRM_FORMAT_ARGB8888:
8451 case DRM_FORMAT_XRGB1555:
8452 case DRM_FORMAT_ARGB1555:
8453 if (INTEL_INFO(dev)->gen > 3)
8456 case DRM_FORMAT_XBGR8888:
8457 case DRM_FORMAT_ABGR8888:
8458 case DRM_FORMAT_XRGB2101010:
8459 case DRM_FORMAT_ARGB2101010:
8460 case DRM_FORMAT_XBGR2101010:
8461 case DRM_FORMAT_ABGR2101010:
8462 if (INTEL_INFO(dev)->gen < 4)
8465 case DRM_FORMAT_YUYV:
8466 case DRM_FORMAT_UYVY:
8467 case DRM_FORMAT_YVYU:
8468 case DRM_FORMAT_VYUY:
8469 if (INTEL_INFO(dev)->gen < 6)
8473 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8477 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8478 if (mode_cmd->offsets[0] != 0)
8481 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8483 DRM_ERROR("framebuffer init failed %d\n", ret);
8487 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8488 intel_fb->obj = obj;
8492 static struct drm_framebuffer *
8493 intel_user_framebuffer_create(struct drm_device *dev,
8494 struct drm_file *filp,
8495 struct drm_mode_fb_cmd2 *mode_cmd)
8497 struct drm_i915_gem_object *obj;
8499 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8500 mode_cmd->handles[0]));
8501 if (&obj->base == NULL)
8502 return ERR_PTR(-ENOENT);
8504 return intel_framebuffer_create(dev, mode_cmd, obj);
8507 static const struct drm_mode_config_funcs intel_mode_funcs = {
8508 .fb_create = intel_user_framebuffer_create,
8509 .output_poll_changed = intel_fb_output_poll_changed,
8512 /* Set up chip specific display functions */
8513 static void intel_init_display(struct drm_device *dev)
8515 struct drm_i915_private *dev_priv = dev->dev_private;
8517 /* We always want a DPMS function */
8518 if (IS_HASWELL(dev)) {
8519 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8520 dev_priv->display.crtc_enable = haswell_crtc_enable;
8521 dev_priv->display.crtc_disable = haswell_crtc_disable;
8522 dev_priv->display.off = haswell_crtc_off;
8523 dev_priv->display.update_plane = ironlake_update_plane;
8524 } else if (HAS_PCH_SPLIT(dev)) {
8525 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8526 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8527 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8528 dev_priv->display.off = ironlake_crtc_off;
8529 dev_priv->display.update_plane = ironlake_update_plane;
8531 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8532 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8533 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8534 dev_priv->display.off = i9xx_crtc_off;
8535 dev_priv->display.update_plane = i9xx_update_plane;
8538 /* Returns the core display clock speed */
8539 if (IS_VALLEYVIEW(dev))
8540 dev_priv->display.get_display_clock_speed =
8541 valleyview_get_display_clock_speed;
8542 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8543 dev_priv->display.get_display_clock_speed =
8544 i945_get_display_clock_speed;
8545 else if (IS_I915G(dev))
8546 dev_priv->display.get_display_clock_speed =
8547 i915_get_display_clock_speed;
8548 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8549 dev_priv->display.get_display_clock_speed =
8550 i9xx_misc_get_display_clock_speed;
8551 else if (IS_I915GM(dev))
8552 dev_priv->display.get_display_clock_speed =
8553 i915gm_get_display_clock_speed;
8554 else if (IS_I865G(dev))
8555 dev_priv->display.get_display_clock_speed =
8556 i865_get_display_clock_speed;
8557 else if (IS_I85X(dev))
8558 dev_priv->display.get_display_clock_speed =
8559 i855_get_display_clock_speed;
8561 dev_priv->display.get_display_clock_speed =
8562 i830_get_display_clock_speed;
8564 if (HAS_PCH_SPLIT(dev)) {
8566 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8567 dev_priv->display.write_eld = ironlake_write_eld;
8568 } else if (IS_GEN6(dev)) {
8569 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8570 dev_priv->display.write_eld = ironlake_write_eld;
8571 } else if (IS_IVYBRIDGE(dev)) {
8572 /* FIXME: detect B0+ stepping and use auto training */
8573 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8574 dev_priv->display.write_eld = ironlake_write_eld;
8575 dev_priv->display.modeset_global_resources =
8576 ivb_modeset_global_resources;
8577 } else if (IS_HASWELL(dev)) {
8578 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8579 dev_priv->display.write_eld = haswell_write_eld;
8581 dev_priv->display.update_wm = NULL;
8582 } else if (IS_G4X(dev)) {
8583 dev_priv->display.write_eld = g4x_write_eld;
8586 /* Default just returns -ENODEV to indicate unsupported */
8587 dev_priv->display.queue_flip = intel_default_queue_flip;
8589 switch (INTEL_INFO(dev)->gen) {
8591 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8595 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8600 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8604 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8607 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8613 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8614 * resume, or other times. This quirk makes sure that's the case for
8617 static void quirk_pipea_force(struct drm_device *dev)
8619 struct drm_i915_private *dev_priv = dev->dev_private;
8621 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8622 DRM_INFO("applying pipe a force quirk\n");
8626 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8628 static void quirk_ssc_force_disable(struct drm_device *dev)
8630 struct drm_i915_private *dev_priv = dev->dev_private;
8631 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8632 DRM_INFO("applying lvds SSC disable quirk\n");
8636 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8639 static void quirk_invert_brightness(struct drm_device *dev)
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8643 DRM_INFO("applying inverted panel brightness quirk\n");
8646 struct intel_quirk {
8648 int subsystem_vendor;
8649 int subsystem_device;
8650 void (*hook)(struct drm_device *dev);
8653 static struct intel_quirk intel_quirks[] = {
8654 /* HP Mini needs pipe A force quirk (LP: #322104) */
8655 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8657 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8658 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8660 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8661 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8663 /* 830/845 need to leave pipe A & dpll A up */
8664 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8665 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8667 /* Lenovo U160 cannot use SSC on LVDS */
8668 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8670 /* Sony Vaio Y cannot use SSC on LVDS */
8671 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8673 /* Acer Aspire 5734Z must invert backlight brightness */
8674 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8677 static void intel_init_quirks(struct drm_device *dev)
8679 struct pci_dev *d = dev->pdev;
8682 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8683 struct intel_quirk *q = &intel_quirks[i];
8685 if (d->device == q->device &&
8686 (d->subsystem_vendor == q->subsystem_vendor ||
8687 q->subsystem_vendor == PCI_ANY_ID) &&
8688 (d->subsystem_device == q->subsystem_device ||
8689 q->subsystem_device == PCI_ANY_ID))
8694 /* Disable the VGA plane that we never use */
8695 static void i915_disable_vga(struct drm_device *dev)
8697 struct drm_i915_private *dev_priv = dev->dev_private;
8701 if (HAS_PCH_SPLIT(dev))
8702 vga_reg = CPU_VGACNTRL;
8706 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8707 outb(SR01, VGA_SR_INDEX);
8708 sr1 = inb(VGA_SR_DATA);
8709 outb(sr1 | 1<<5, VGA_SR_DATA);
8710 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8713 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8714 POSTING_READ(vga_reg);
8717 void intel_modeset_init_hw(struct drm_device *dev)
8719 /* We attempt to init the necessary power wells early in the initialization
8720 * time, so the subsystems that expect power to be enabled can work.
8722 intel_init_power_wells(dev);
8724 intel_prepare_ddi(dev);
8726 intel_init_clock_gating(dev);
8728 mutex_lock(&dev->struct_mutex);
8729 intel_enable_gt_powersave(dev);
8730 mutex_unlock(&dev->struct_mutex);
8733 void intel_modeset_init(struct drm_device *dev)
8735 struct drm_i915_private *dev_priv = dev->dev_private;
8738 drm_mode_config_init(dev);
8740 dev->mode_config.min_width = 0;
8741 dev->mode_config.min_height = 0;
8743 dev->mode_config.preferred_depth = 24;
8744 dev->mode_config.prefer_shadow = 1;
8746 dev->mode_config.funcs = &intel_mode_funcs;
8748 intel_init_quirks(dev);
8752 intel_init_display(dev);
8755 dev->mode_config.max_width = 2048;
8756 dev->mode_config.max_height = 2048;
8757 } else if (IS_GEN3(dev)) {
8758 dev->mode_config.max_width = 4096;
8759 dev->mode_config.max_height = 4096;
8761 dev->mode_config.max_width = 8192;
8762 dev->mode_config.max_height = 8192;
8764 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8766 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8767 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8769 for (i = 0; i < dev_priv->num_pipe; i++) {
8770 intel_crtc_init(dev, i);
8771 ret = intel_plane_init(dev, i);
8773 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8776 intel_cpu_pll_init(dev);
8777 intel_pch_pll_init(dev);
8779 /* Just disable it once at startup */
8780 i915_disable_vga(dev);
8781 intel_setup_outputs(dev);
8785 intel_connector_break_all_links(struct intel_connector *connector)
8787 connector->base.dpms = DRM_MODE_DPMS_OFF;
8788 connector->base.encoder = NULL;
8789 connector->encoder->connectors_active = false;
8790 connector->encoder->base.crtc = NULL;
8793 static void intel_enable_pipe_a(struct drm_device *dev)
8795 struct intel_connector *connector;
8796 struct drm_connector *crt = NULL;
8797 struct intel_load_detect_pipe load_detect_temp;
8799 /* We can't just switch on the pipe A, we need to set things up with a
8800 * proper mode and output configuration. As a gross hack, enable pipe A
8801 * by enabling the load detect pipe once. */
8802 list_for_each_entry(connector,
8803 &dev->mode_config.connector_list,
8805 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8806 crt = &connector->base;
8814 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8815 intel_release_load_detect_pipe(crt, &load_detect_temp);
8821 intel_check_plane_mapping(struct intel_crtc *crtc)
8823 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8826 if (dev_priv->num_pipe == 1)
8829 reg = DSPCNTR(!crtc->plane);
8830 val = I915_READ(reg);
8832 if ((val & DISPLAY_PLANE_ENABLE) &&
8833 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8839 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8841 struct drm_device *dev = crtc->base.dev;
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8845 /* Clear any frame start delays used for debugging left by the BIOS */
8846 reg = PIPECONF(crtc->cpu_transcoder);
8847 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8849 /* We need to sanitize the plane -> pipe mapping first because this will
8850 * disable the crtc (and hence change the state) if it is wrong. Note
8851 * that gen4+ has a fixed plane -> pipe mapping. */
8852 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8853 struct intel_connector *connector;
8856 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8857 crtc->base.base.id);
8859 /* Pipe has the wrong plane attached and the plane is active.
8860 * Temporarily change the plane mapping and disable everything
8862 plane = crtc->plane;
8863 crtc->plane = !plane;
8864 dev_priv->display.crtc_disable(&crtc->base);
8865 crtc->plane = plane;
8867 /* ... and break all links. */
8868 list_for_each_entry(connector, &dev->mode_config.connector_list,
8870 if (connector->encoder->base.crtc != &crtc->base)
8873 intel_connector_break_all_links(connector);
8876 WARN_ON(crtc->active);
8877 crtc->base.enabled = false;
8880 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8881 crtc->pipe == PIPE_A && !crtc->active) {
8882 /* BIOS forgot to enable pipe A, this mostly happens after
8883 * resume. Force-enable the pipe to fix this, the update_dpms
8884 * call below we restore the pipe to the right state, but leave
8885 * the required bits on. */
8886 intel_enable_pipe_a(dev);
8889 /* Adjust the state of the output pipe according to whether we
8890 * have active connectors/encoders. */
8891 intel_crtc_update_dpms(&crtc->base);
8893 if (crtc->active != crtc->base.enabled) {
8894 struct intel_encoder *encoder;
8896 /* This can happen either due to bugs in the get_hw_state
8897 * functions or because the pipe is force-enabled due to the
8899 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8901 crtc->base.enabled ? "enabled" : "disabled",
8902 crtc->active ? "enabled" : "disabled");
8904 crtc->base.enabled = crtc->active;
8906 /* Because we only establish the connector -> encoder ->
8907 * crtc links if something is active, this means the
8908 * crtc is now deactivated. Break the links. connector
8909 * -> encoder links are only establish when things are
8910 * actually up, hence no need to break them. */
8911 WARN_ON(crtc->active);
8913 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8914 WARN_ON(encoder->connectors_active);
8915 encoder->base.crtc = NULL;
8920 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8922 struct intel_connector *connector;
8923 struct drm_device *dev = encoder->base.dev;
8925 /* We need to check both for a crtc link (meaning that the
8926 * encoder is active and trying to read from a pipe) and the
8927 * pipe itself being active. */
8928 bool has_active_crtc = encoder->base.crtc &&
8929 to_intel_crtc(encoder->base.crtc)->active;
8931 if (encoder->connectors_active && !has_active_crtc) {
8932 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8933 encoder->base.base.id,
8934 drm_get_encoder_name(&encoder->base));
8936 /* Connector is active, but has no active pipe. This is
8937 * fallout from our resume register restoring. Disable
8938 * the encoder manually again. */
8939 if (encoder->base.crtc) {
8940 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8941 encoder->base.base.id,
8942 drm_get_encoder_name(&encoder->base));
8943 encoder->disable(encoder);
8946 /* Inconsistent output/port/pipe state happens presumably due to
8947 * a bug in one of the get_hw_state functions. Or someplace else
8948 * in our code, like the register restore mess on resume. Clamp
8949 * things to off as a safer default. */
8950 list_for_each_entry(connector,
8951 &dev->mode_config.connector_list,
8953 if (connector->encoder != encoder)
8956 intel_connector_break_all_links(connector);
8959 /* Enabled encoders without active connectors will be fixed in
8960 * the crtc fixup. */
8963 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8964 * and i915 state tracking structures. */
8965 void intel_modeset_setup_hw_state(struct drm_device *dev)
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8970 struct intel_crtc *crtc;
8971 struct intel_encoder *encoder;
8972 struct intel_connector *connector;
8974 if (IS_HASWELL(dev)) {
8975 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8977 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8978 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8979 case TRANS_DDI_EDP_INPUT_A_ON:
8980 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8983 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8986 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8991 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8992 crtc->cpu_transcoder = TRANSCODER_EDP;
8994 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8999 for_each_pipe(pipe) {
9000 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9002 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9003 if (tmp & PIPECONF_ENABLE)
9004 crtc->active = true;
9006 crtc->active = false;
9008 crtc->base.enabled = crtc->active;
9010 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9012 crtc->active ? "enabled" : "disabled");
9015 if (IS_HASWELL(dev))
9016 intel_ddi_setup_hw_pll_state(dev);
9018 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9022 if (encoder->get_hw_state(encoder, &pipe)) {
9023 encoder->base.crtc =
9024 dev_priv->pipe_to_crtc_mapping[pipe];
9026 encoder->base.crtc = NULL;
9029 encoder->connectors_active = false;
9030 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9031 encoder->base.base.id,
9032 drm_get_encoder_name(&encoder->base),
9033 encoder->base.crtc ? "enabled" : "disabled",
9037 list_for_each_entry(connector, &dev->mode_config.connector_list,
9039 if (connector->get_hw_state(connector)) {
9040 connector->base.dpms = DRM_MODE_DPMS_ON;
9041 connector->encoder->connectors_active = true;
9042 connector->base.encoder = &connector->encoder->base;
9044 connector->base.dpms = DRM_MODE_DPMS_OFF;
9045 connector->base.encoder = NULL;
9047 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9048 connector->base.base.id,
9049 drm_get_connector_name(&connector->base),
9050 connector->base.encoder ? "enabled" : "disabled");
9053 /* HW state is read out, now we need to sanitize this mess. */
9054 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056 intel_sanitize_encoder(encoder);
9059 for_each_pipe(pipe) {
9060 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9061 intel_sanitize_crtc(crtc);
9064 intel_modeset_update_staged_output_state(dev);
9066 intel_modeset_check_state(dev);
9068 drm_mode_config_reset(dev);
9071 void intel_modeset_gem_init(struct drm_device *dev)
9073 intel_modeset_init_hw(dev);
9075 intel_setup_overlay(dev);
9077 intel_modeset_setup_hw_state(dev);
9080 void intel_modeset_cleanup(struct drm_device *dev)
9082 struct drm_i915_private *dev_priv = dev->dev_private;
9083 struct drm_crtc *crtc;
9084 struct intel_crtc *intel_crtc;
9086 drm_kms_helper_poll_fini(dev);
9087 mutex_lock(&dev->struct_mutex);
9089 intel_unregister_dsm_handler();
9092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9093 /* Skip inactive CRTCs */
9097 intel_crtc = to_intel_crtc(crtc);
9098 intel_increase_pllclock(crtc);
9101 intel_disable_fbc(dev);
9103 intel_disable_gt_powersave(dev);
9105 ironlake_teardown_rc6(dev);
9107 if (IS_VALLEYVIEW(dev))
9110 mutex_unlock(&dev->struct_mutex);
9112 /* Disable the irq before mode object teardown, for the irq might
9113 * enqueue unpin/hotplug work. */
9114 drm_irq_uninstall(dev);
9115 cancel_work_sync(&dev_priv->hotplug_work);
9116 cancel_work_sync(&dev_priv->rps.work);
9118 /* flush any delayed tasks or pending work */
9119 flush_scheduled_work();
9121 drm_mode_config_cleanup(dev);
9125 * Return which encoder is currently attached for connector.
9127 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9129 return &intel_attached_encoder(connector)->base;
9132 void intel_connector_attach_encoder(struct intel_connector *connector,
9133 struct intel_encoder *encoder)
9135 connector->encoder = encoder;
9136 drm_mode_connector_attach_encoder(&connector->base,
9141 * set vga decode state - true == enable VGA decode
9143 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9145 struct drm_i915_private *dev_priv = dev->dev_private;
9148 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9150 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9152 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9153 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9157 #ifdef CONFIG_DEBUG_FS
9158 #include <linux/seq_file.h>
9160 struct intel_display_error_state {
9161 struct intel_cursor_error_state {
9166 } cursor[I915_MAX_PIPES];
9168 struct intel_pipe_error_state {
9178 } pipe[I915_MAX_PIPES];
9180 struct intel_plane_error_state {
9188 } plane[I915_MAX_PIPES];
9191 struct intel_display_error_state *
9192 intel_display_capture_error_state(struct drm_device *dev)
9194 drm_i915_private_t *dev_priv = dev->dev_private;
9195 struct intel_display_error_state *error;
9196 enum transcoder cpu_transcoder;
9199 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9204 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9206 error->cursor[i].control = I915_READ(CURCNTR(i));
9207 error->cursor[i].position = I915_READ(CURPOS(i));
9208 error->cursor[i].base = I915_READ(CURBASE(i));
9210 error->plane[i].control = I915_READ(DSPCNTR(i));
9211 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9212 error->plane[i].size = I915_READ(DSPSIZE(i));
9213 error->plane[i].pos = I915_READ(DSPPOS(i));
9214 error->plane[i].addr = I915_READ(DSPADDR(i));
9215 if (INTEL_INFO(dev)->gen >= 4) {
9216 error->plane[i].surface = I915_READ(DSPSURF(i));
9217 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9220 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9221 error->pipe[i].source = I915_READ(PIPESRC(i));
9222 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9223 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9224 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9225 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9226 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9227 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9234 intel_display_print_error_state(struct seq_file *m,
9235 struct drm_device *dev,
9236 struct intel_display_error_state *error)
9238 drm_i915_private_t *dev_priv = dev->dev_private;
9241 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9243 seq_printf(m, "Pipe [%d]:\n", i);
9244 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9245 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9246 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9247 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9248 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9249 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9250 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9251 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9253 seq_printf(m, "Plane [%d]:\n", i);
9254 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9255 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9256 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9257 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9258 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9259 if (INTEL_INFO(dev)->gen >= 4) {
9260 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9261 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9264 seq_printf(m, "Cursor [%d]:\n", i);
9265 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9266 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9267 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);