Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021
1022         if (INTEL_INFO(dev)->gen >= 4) {
1023                 int reg = PIPECONF(pipe);
1024
1025                 /* Wait for the Pipe State to go off */
1026                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027                              100))
1028                         WARN(1, "pipe_off wait timed out\n");
1029         } else {
1030                 u32 last_line, line_mask;
1031                 int reg = PIPEDSL(pipe);
1032                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034                 if (IS_GEN2(dev))
1035                         line_mask = DSL_LINEMASK_GEN2;
1036                 else
1037                         line_mask = DSL_LINEMASK_GEN3;
1038
1039                 /* Wait for the display line to settle */
1040                 do {
1041                         last_line = I915_READ(reg) & line_mask;
1042                         mdelay(5);
1043                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044                          time_after(timeout, jiffies));
1045                 if (time_after(jiffies, timeout))
1046                         WARN(1, "pipe_off wait timed out\n");
1047         }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052         return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057                        enum pipe pipe, bool state)
1058 {
1059         int reg;
1060         u32 val;
1061         bool cur_state;
1062
1063         reg = DPLL(pipe);
1064         val = I915_READ(reg);
1065         cur_state = !!(val & DPLL_VCO_ENABLE);
1066         WARN(cur_state != state,
1067              "PLL state assertion failure (expected %s, current %s)\n",
1068              state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075                            struct intel_pch_pll *pll,
1076                            struct intel_crtc *crtc,
1077                            bool state)
1078 {
1079         u32 val;
1080         bool cur_state;
1081
1082         if (HAS_PCH_LPT(dev_priv->dev)) {
1083                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084                 return;
1085         }
1086
1087         if (WARN (!pll,
1088                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089                 return;
1090
1091         val = I915_READ(pll->pll_reg);
1092         cur_state = !!(val & DPLL_VCO_ENABLE);
1093         WARN(cur_state != state,
1094              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095              pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097         /* Make sure the selected PLL is correctly attached to the transcoder */
1098         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099                 u32 pch_dpll;
1100
1101                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1105                           cur_state, crtc->pipe, pch_dpll)) {
1106                         cur_state = !!(val >> (4*crtc->pipe + 3));
1107                         WARN(cur_state != state,
1108                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1109                              pll->pll_reg == _PCH_DPLL_B,
1110                              state_string(state),
1111                              crtc->pipe,
1112                              val);
1113                 }
1114         }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120                           enum pipe pipe, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126                                                                       pipe);
1127
1128         if (IS_HASWELL(dev_priv->dev)) {
1129                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131                 val = I915_READ(reg);
1132                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133         } else {
1134                 reg = FDI_TX_CTL(pipe);
1135                 val = I915_READ(reg);
1136                 cur_state = !!(val & FDI_TX_ENABLE);
1137         }
1138         WARN(cur_state != state,
1139              "FDI TX state assertion failure (expected %s, current %s)\n",
1140              state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146                           enum pipe pipe, bool state)
1147 {
1148         int reg;
1149         u32 val;
1150         bool cur_state;
1151
1152         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1153                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1154                         return;
1155         } else {
1156                 reg = FDI_RX_CTL(pipe);
1157                 val = I915_READ(reg);
1158                 cur_state = !!(val & FDI_RX_ENABLE);
1159         }
1160         WARN(cur_state != state,
1161              "FDI RX state assertion failure (expected %s, current %s)\n",
1162              state_string(state), state_string(cur_state));
1163 }
1164 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1165 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1166
1167 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1168                                       enum pipe pipe)
1169 {
1170         int reg;
1171         u32 val;
1172
1173         /* ILK FDI PLL is always enabled */
1174         if (dev_priv->info->gen == 5)
1175                 return;
1176
1177         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1178         if (IS_HASWELL(dev_priv->dev))
1179                 return;
1180
1181         reg = FDI_TX_CTL(pipe);
1182         val = I915_READ(reg);
1183         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1184 }
1185
1186 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1187                                       enum pipe pipe)
1188 {
1189         int reg;
1190         u32 val;
1191
1192         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1194                 return;
1195         }
1196         reg = FDI_RX_CTL(pipe);
1197         val = I915_READ(reg);
1198         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1199 }
1200
1201 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1202                                   enum pipe pipe)
1203 {
1204         int pp_reg, lvds_reg;
1205         u32 val;
1206         enum pipe panel_pipe = PIPE_A;
1207         bool locked = true;
1208
1209         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1210                 pp_reg = PCH_PP_CONTROL;
1211                 lvds_reg = PCH_LVDS;
1212         } else {
1213                 pp_reg = PP_CONTROL;
1214                 lvds_reg = LVDS;
1215         }
1216
1217         val = I915_READ(pp_reg);
1218         if (!(val & PANEL_POWER_ON) ||
1219             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1220                 locked = false;
1221
1222         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1223                 panel_pipe = PIPE_B;
1224
1225         WARN(panel_pipe == pipe && locked,
1226              "panel assertion failure, pipe %c regs locked\n",
1227              pipe_name(pipe));
1228 }
1229
1230 void assert_pipe(struct drm_i915_private *dev_priv,
1231                  enum pipe pipe, bool state)
1232 {
1233         int reg;
1234         u32 val;
1235         bool cur_state;
1236
1237         /* if we need the pipe A quirk it must be always on */
1238         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1239                 state = true;
1240
1241         reg = PIPECONF(pipe);
1242         val = I915_READ(reg);
1243         cur_state = !!(val & PIPECONF_ENABLE);
1244         WARN(cur_state != state,
1245              "pipe %c assertion failure (expected %s, current %s)\n",
1246              pipe_name(pipe), state_string(state), state_string(cur_state));
1247 }
1248
1249 static void assert_plane(struct drm_i915_private *dev_priv,
1250                          enum plane plane, bool state)
1251 {
1252         int reg;
1253         u32 val;
1254         bool cur_state;
1255
1256         reg = DSPCNTR(plane);
1257         val = I915_READ(reg);
1258         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1259         WARN(cur_state != state,
1260              "plane %c assertion failure (expected %s, current %s)\n",
1261              plane_name(plane), state_string(state), state_string(cur_state));
1262 }
1263
1264 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1265 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1266
1267 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1268                                    enum pipe pipe)
1269 {
1270         int reg, i;
1271         u32 val;
1272         int cur_pipe;
1273
1274         /* Planes are fixed to pipes on ILK+ */
1275         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1276                 reg = DSPCNTR(pipe);
1277                 val = I915_READ(reg);
1278                 WARN((val & DISPLAY_PLANE_ENABLE),
1279                      "plane %c assertion failure, should be disabled but not\n",
1280                      plane_name(pipe));
1281                 return;
1282         }
1283
1284         /* Need to check both planes against the pipe */
1285         for (i = 0; i < 2; i++) {
1286                 reg = DSPCNTR(i);
1287                 val = I915_READ(reg);
1288                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1289                         DISPPLANE_SEL_PIPE_SHIFT;
1290                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1291                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1292                      plane_name(i), pipe_name(pipe));
1293         }
1294 }
1295
1296 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1297 {
1298         u32 val;
1299         bool enabled;
1300
1301         if (HAS_PCH_LPT(dev_priv->dev)) {
1302                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1303                 return;
1304         }
1305
1306         val = I915_READ(PCH_DREF_CONTROL);
1307         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1308                             DREF_SUPERSPREAD_SOURCE_MASK));
1309         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1310 }
1311
1312 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1313                                        enum pipe pipe)
1314 {
1315         int reg;
1316         u32 val;
1317         bool enabled;
1318
1319         reg = TRANSCONF(pipe);
1320         val = I915_READ(reg);
1321         enabled = !!(val & TRANS_ENABLE);
1322         WARN(enabled,
1323              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1324              pipe_name(pipe));
1325 }
1326
1327 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1328                             enum pipe pipe, u32 port_sel, u32 val)
1329 {
1330         if ((val & DP_PORT_EN) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv->dev)) {
1334                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1335                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1336                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1337                         return false;
1338         } else {
1339                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1340                         return false;
1341         }
1342         return true;
1343 }
1344
1345 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1346                               enum pipe pipe, u32 val)
1347 {
1348         if ((val & PORT_ENABLE) == 0)
1349                 return false;
1350
1351         if (HAS_PCH_CPT(dev_priv->dev)) {
1352                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1353                         return false;
1354         } else {
1355                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1356                         return false;
1357         }
1358         return true;
1359 }
1360
1361 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1362                               enum pipe pipe, u32 val)
1363 {
1364         if ((val & LVDS_PORT_EN) == 0)
1365                 return false;
1366
1367         if (HAS_PCH_CPT(dev_priv->dev)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1378                               enum pipe pipe, u32 val)
1379 {
1380         if ((val & ADPA_DAC_ENABLE) == 0)
1381                 return false;
1382         if (HAS_PCH_CPT(dev_priv->dev)) {
1383                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1393                                    enum pipe pipe, int reg, u32 port_sel)
1394 {
1395         u32 val = I915_READ(reg);
1396         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1397              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1398              reg, pipe_name(pipe));
1399
1400         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1401              && (val & DP_PIPEB_SELECT),
1402              "IBX PCH dp port still using transcoder B\n");
1403 }
1404
1405 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1406                                      enum pipe pipe, int reg)
1407 {
1408         u32 val = I915_READ(reg);
1409         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1410              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1411              reg, pipe_name(pipe));
1412
1413         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1414              && (val & SDVO_PIPE_B_SELECT),
1415              "IBX PCH hdmi port still using transcoder B\n");
1416 }
1417
1418 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1419                                       enum pipe pipe)
1420 {
1421         int reg;
1422         u32 val;
1423
1424         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1425         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1426         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1427
1428         reg = PCH_ADPA;
1429         val = I915_READ(reg);
1430         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1431              "PCH VGA enabled on transcoder %c, should be disabled\n",
1432              pipe_name(pipe));
1433
1434         reg = PCH_LVDS;
1435         val = I915_READ(reg);
1436         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1437              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1438              pipe_name(pipe));
1439
1440         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1441         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1442         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1443 }
1444
1445 /**
1446  * intel_enable_pll - enable a PLL
1447  * @dev_priv: i915 private structure
1448  * @pipe: pipe PLL to enable
1449  *
1450  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1451  * make sure the PLL reg is writable first though, since the panel write
1452  * protect mechanism may be enabled.
1453  *
1454  * Note!  This is for pre-ILK only.
1455  *
1456  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1457  */
1458 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1459 {
1460         int reg;
1461         u32 val;
1462
1463         /* No really, not for ILK+ */
1464         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1465
1466         /* PLL is protected by panel, make sure we can write it */
1467         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1468                 assert_panel_unlocked(dev_priv, pipe);
1469
1470         reg = DPLL(pipe);
1471         val = I915_READ(reg);
1472         val |= DPLL_VCO_ENABLE;
1473
1474         /* We do this three times for luck */
1475         I915_WRITE(reg, val);
1476         POSTING_READ(reg);
1477         udelay(150); /* wait for warmup */
1478         I915_WRITE(reg, val);
1479         POSTING_READ(reg);
1480         udelay(150); /* wait for warmup */
1481         I915_WRITE(reg, val);
1482         POSTING_READ(reg);
1483         udelay(150); /* wait for warmup */
1484 }
1485
1486 /**
1487  * intel_disable_pll - disable a PLL
1488  * @dev_priv: i915 private structure
1489  * @pipe: pipe PLL to disable
1490  *
1491  * Disable the PLL for @pipe, making sure the pipe is off first.
1492  *
1493  * Note!  This is for pre-ILK only.
1494  */
1495 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1496 {
1497         int reg;
1498         u32 val;
1499
1500         /* Don't disable pipe A or pipe A PLLs if needed */
1501         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1502                 return;
1503
1504         /* Make sure the pipe isn't still relying on us */
1505         assert_pipe_disabled(dev_priv, pipe);
1506
1507         reg = DPLL(pipe);
1508         val = I915_READ(reg);
1509         val &= ~DPLL_VCO_ENABLE;
1510         I915_WRITE(reg, val);
1511         POSTING_READ(reg);
1512 }
1513
1514 /* SBI access */
1515 static void
1516 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1517 {
1518         unsigned long flags;
1519
1520         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1521         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1522                                 100)) {
1523                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524                 goto out_unlock;
1525         }
1526
1527         I915_WRITE(SBI_ADDR,
1528                         (reg << 16));
1529         I915_WRITE(SBI_DATA,
1530                         value);
1531         I915_WRITE(SBI_CTL_STAT,
1532                         SBI_BUSY |
1533                         SBI_CTL_OP_CRWR);
1534
1535         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1536                                 100)) {
1537                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1538                 goto out_unlock;
1539         }
1540
1541 out_unlock:
1542         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1543 }
1544
1545 static u32
1546 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1547 {
1548         unsigned long flags;
1549         u32 value = 0;
1550
1551         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1552         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1553                                 100)) {
1554                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1555                 goto out_unlock;
1556         }
1557
1558         I915_WRITE(SBI_ADDR,
1559                         (reg << 16));
1560         I915_WRITE(SBI_CTL_STAT,
1561                         SBI_BUSY |
1562                         SBI_CTL_OP_CRRD);
1563
1564         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1565                                 100)) {
1566                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567                 goto out_unlock;
1568         }
1569
1570         value = I915_READ(SBI_DATA);
1571
1572 out_unlock:
1573         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1574         return value;
1575 }
1576
1577 /**
1578  * intel_enable_pch_pll - enable PCH PLL
1579  * @dev_priv: i915 private structure
1580  * @pipe: pipe PLL to enable
1581  *
1582  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1583  * drives the transcoder clock.
1584  */
1585 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1586 {
1587         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1588         struct intel_pch_pll *pll;
1589         int reg;
1590         u32 val;
1591
1592         /* PCH PLLs only available on ILK, SNB and IVB */
1593         BUG_ON(dev_priv->info->gen < 5);
1594         pll = intel_crtc->pch_pll;
1595         if (pll == NULL)
1596                 return;
1597
1598         if (WARN_ON(pll->refcount == 0))
1599                 return;
1600
1601         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1602                       pll->pll_reg, pll->active, pll->on,
1603                       intel_crtc->base.base.id);
1604
1605         /* PCH refclock must be enabled first */
1606         assert_pch_refclk_enabled(dev_priv);
1607
1608         if (pll->active++ && pll->on) {
1609                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1610                 return;
1611         }
1612
1613         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1614
1615         reg = pll->pll_reg;
1616         val = I915_READ(reg);
1617         val |= DPLL_VCO_ENABLE;
1618         I915_WRITE(reg, val);
1619         POSTING_READ(reg);
1620         udelay(200);
1621
1622         pll->on = true;
1623 }
1624
1625 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1626 {
1627         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1628         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1629         int reg;
1630         u32 val;
1631
1632         /* PCH only available on ILK+ */
1633         BUG_ON(dev_priv->info->gen < 5);
1634         if (pll == NULL)
1635                return;
1636
1637         if (WARN_ON(pll->refcount == 0))
1638                 return;
1639
1640         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1641                       pll->pll_reg, pll->active, pll->on,
1642                       intel_crtc->base.base.id);
1643
1644         if (WARN_ON(pll->active == 0)) {
1645                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1646                 return;
1647         }
1648
1649         if (--pll->active) {
1650                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1651                 return;
1652         }
1653
1654         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1655
1656         /* Make sure transcoder isn't still depending on us */
1657         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1658
1659         reg = pll->pll_reg;
1660         val = I915_READ(reg);
1661         val &= ~DPLL_VCO_ENABLE;
1662         I915_WRITE(reg, val);
1663         POSTING_READ(reg);
1664         udelay(200);
1665
1666         pll->on = false;
1667 }
1668
1669 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1670                                     enum pipe pipe)
1671 {
1672         int reg;
1673         u32 val, pipeconf_val;
1674         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1675
1676         /* PCH only available on ILK+ */
1677         BUG_ON(dev_priv->info->gen < 5);
1678
1679         /* Make sure PCH DPLL is enabled */
1680         assert_pch_pll_enabled(dev_priv,
1681                                to_intel_crtc(crtc)->pch_pll,
1682                                to_intel_crtc(crtc));
1683
1684         /* FDI must be feeding us bits for PCH ports */
1685         assert_fdi_tx_enabled(dev_priv, pipe);
1686         assert_fdi_rx_enabled(dev_priv, pipe);
1687
1688         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1689                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1690                 return;
1691         }
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1721                                      enum pipe pipe)
1722 {
1723         int reg;
1724         u32 val;
1725
1726         /* FDI relies on the transcoder */
1727         assert_fdi_tx_disabled(dev_priv, pipe);
1728         assert_fdi_rx_disabled(dev_priv, pipe);
1729
1730         /* Ports must be off as well */
1731         assert_pch_ports_disabled(dev_priv, pipe);
1732
1733         reg = TRANSCONF(pipe);
1734         val = I915_READ(reg);
1735         val &= ~TRANS_ENABLE;
1736         I915_WRITE(reg, val);
1737         /* wait for PCH transcoder off, transcoder state */
1738         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1739                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1740 }
1741
1742 /**
1743  * intel_enable_pipe - enable a pipe, asserting requirements
1744  * @dev_priv: i915 private structure
1745  * @pipe: pipe to enable
1746  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1747  *
1748  * Enable @pipe, making sure that various hardware specific requirements
1749  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1750  *
1751  * @pipe should be %PIPE_A or %PIPE_B.
1752  *
1753  * Will wait until the pipe is actually running (i.e. first vblank) before
1754  * returning.
1755  */
1756 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1757                               bool pch_port)
1758 {
1759         int reg;
1760         u32 val;
1761
1762         /*
1763          * A pipe without a PLL won't actually be able to drive bits from
1764          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1765          * need the check.
1766          */
1767         if (!HAS_PCH_SPLIT(dev_priv->dev))
1768                 assert_pll_enabled(dev_priv, pipe);
1769         else {
1770                 if (pch_port) {
1771                         /* if driving the PCH, we need FDI enabled */
1772                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1773                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1774                 }
1775                 /* FIXME: assert CPU port conditions for SNB+ */
1776         }
1777
1778         reg = PIPECONF(pipe);
1779         val = I915_READ(reg);
1780         if (val & PIPECONF_ENABLE)
1781                 return;
1782
1783         I915_WRITE(reg, val | PIPECONF_ENABLE);
1784         intel_wait_for_vblank(dev_priv->dev, pipe);
1785 }
1786
1787 /**
1788  * intel_disable_pipe - disable a pipe, asserting requirements
1789  * @dev_priv: i915 private structure
1790  * @pipe: pipe to disable
1791  *
1792  * Disable @pipe, making sure that various hardware specific requirements
1793  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1794  *
1795  * @pipe should be %PIPE_A or %PIPE_B.
1796  *
1797  * Will wait until the pipe has shut down before returning.
1798  */
1799 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1800                                enum pipe pipe)
1801 {
1802         int reg;
1803         u32 val;
1804
1805         /*
1806          * Make sure planes won't keep trying to pump pixels to us,
1807          * or we might hang the display.
1808          */
1809         assert_planes_disabled(dev_priv, pipe);
1810
1811         /* Don't disable pipe A or pipe A PLLs if needed */
1812         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1813                 return;
1814
1815         reg = PIPECONF(pipe);
1816         val = I915_READ(reg);
1817         if ((val & PIPECONF_ENABLE) == 0)
1818                 return;
1819
1820         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1821         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1822 }
1823
1824 /*
1825  * Plane regs are double buffered, going from enabled->disabled needs a
1826  * trigger in order to latch.  The display address reg provides this.
1827  */
1828 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1829                                       enum plane plane)
1830 {
1831         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1832         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1833 }
1834
1835 /**
1836  * intel_enable_plane - enable a display plane on a given pipe
1837  * @dev_priv: i915 private structure
1838  * @plane: plane to enable
1839  * @pipe: pipe being fed
1840  *
1841  * Enable @plane on @pipe, making sure that @pipe is running first.
1842  */
1843 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1844                                enum plane plane, enum pipe pipe)
1845 {
1846         int reg;
1847         u32 val;
1848
1849         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1850         assert_pipe_enabled(dev_priv, pipe);
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_display_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_plane - disable a display plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1871                                 enum plane plane, enum pipe pipe)
1872 {
1873         int reg;
1874         u32 val;
1875
1876         reg = DSPCNTR(plane);
1877         val = I915_READ(reg);
1878         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1879                 return;
1880
1881         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1882         intel_flush_display_plane(dev_priv, plane);
1883         intel_wait_for_vblank(dev_priv->dev, pipe);
1884 }
1885
1886 int
1887 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1888                            struct drm_i915_gem_object *obj,
1889                            struct intel_ring_buffer *pipelined)
1890 {
1891         struct drm_i915_private *dev_priv = dev->dev_private;
1892         u32 alignment;
1893         int ret;
1894
1895         switch (obj->tiling_mode) {
1896         case I915_TILING_NONE:
1897                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1898                         alignment = 128 * 1024;
1899                 else if (INTEL_INFO(dev)->gen >= 4)
1900                         alignment = 4 * 1024;
1901                 else
1902                         alignment = 64 * 1024;
1903                 break;
1904         case I915_TILING_X:
1905                 /* pin() will align the object as required by fence */
1906                 alignment = 0;
1907                 break;
1908         case I915_TILING_Y:
1909                 /* FIXME: Is this true? */
1910                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1911                 return -EINVAL;
1912         default:
1913                 BUG();
1914         }
1915
1916         dev_priv->mm.interruptible = false;
1917         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1918         if (ret)
1919                 goto err_interruptible;
1920
1921         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1922          * fence, whereas 965+ only requires a fence if using
1923          * framebuffer compression.  For simplicity, we always install
1924          * a fence as the cost is not that onerous.
1925          */
1926         ret = i915_gem_object_get_fence(obj);
1927         if (ret)
1928                 goto err_unpin;
1929
1930         i915_gem_object_pin_fence(obj);
1931
1932         dev_priv->mm.interruptible = true;
1933         return 0;
1934
1935 err_unpin:
1936         i915_gem_object_unpin(obj);
1937 err_interruptible:
1938         dev_priv->mm.interruptible = true;
1939         return ret;
1940 }
1941
1942 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1943 {
1944         i915_gem_object_unpin_fence(obj);
1945         i915_gem_object_unpin(obj);
1946 }
1947
1948 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1949  * is assumed to be a power-of-two. */
1950 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1951                                                         unsigned int bpp,
1952                                                         unsigned int pitch)
1953 {
1954         int tile_rows, tiles;
1955
1956         tile_rows = *y / 8;
1957         *y %= 8;
1958         tiles = *x / (512/bpp);
1959         *x %= 512/bpp;
1960
1961         return tile_rows * pitch * 8 + tiles * 4096;
1962 }
1963
1964 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1965                              int x, int y)
1966 {
1967         struct drm_device *dev = crtc->dev;
1968         struct drm_i915_private *dev_priv = dev->dev_private;
1969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1970         struct intel_framebuffer *intel_fb;
1971         struct drm_i915_gem_object *obj;
1972         int plane = intel_crtc->plane;
1973         unsigned long linear_offset;
1974         u32 dspcntr;
1975         u32 reg;
1976
1977         switch (plane) {
1978         case 0:
1979         case 1:
1980                 break;
1981         default:
1982                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1983                 return -EINVAL;
1984         }
1985
1986         intel_fb = to_intel_framebuffer(fb);
1987         obj = intel_fb->obj;
1988
1989         reg = DSPCNTR(plane);
1990         dspcntr = I915_READ(reg);
1991         /* Mask out pixel format bits in case we change it */
1992         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1993         switch (fb->bits_per_pixel) {
1994         case 8:
1995                 dspcntr |= DISPPLANE_8BPP;
1996                 break;
1997         case 16:
1998                 if (fb->depth == 15)
1999                         dspcntr |= DISPPLANE_15_16BPP;
2000                 else
2001                         dspcntr |= DISPPLANE_16BPP;
2002                 break;
2003         case 24:
2004         case 32:
2005                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2006                 break;
2007         default:
2008                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2009                 return -EINVAL;
2010         }
2011         if (INTEL_INFO(dev)->gen >= 4) {
2012                 if (obj->tiling_mode != I915_TILING_NONE)
2013                         dspcntr |= DISPPLANE_TILED;
2014                 else
2015                         dspcntr &= ~DISPPLANE_TILED;
2016         }
2017
2018         I915_WRITE(reg, dspcntr);
2019
2020         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2021
2022         if (INTEL_INFO(dev)->gen >= 4) {
2023                 intel_crtc->dspaddr_offset =
2024                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2025                                                            fb->bits_per_pixel / 8,
2026                                                            fb->pitches[0]);
2027                 linear_offset -= intel_crtc->dspaddr_offset;
2028         } else {
2029                 intel_crtc->dspaddr_offset = linear_offset;
2030         }
2031
2032         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2033                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2034         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2035         if (INTEL_INFO(dev)->gen >= 4) {
2036                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2037                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2038                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2039                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2040         } else
2041                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2042         POSTING_READ(reg);
2043
2044         return 0;
2045 }
2046
2047 static int ironlake_update_plane(struct drm_crtc *crtc,
2048                                  struct drm_framebuffer *fb, int x, int y)
2049 {
2050         struct drm_device *dev = crtc->dev;
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053         struct intel_framebuffer *intel_fb;
2054         struct drm_i915_gem_object *obj;
2055         int plane = intel_crtc->plane;
2056         unsigned long linear_offset;
2057         u32 dspcntr;
2058         u32 reg;
2059
2060         switch (plane) {
2061         case 0:
2062         case 1:
2063         case 2:
2064                 break;
2065         default:
2066                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2067                 return -EINVAL;
2068         }
2069
2070         intel_fb = to_intel_framebuffer(fb);
2071         obj = intel_fb->obj;
2072
2073         reg = DSPCNTR(plane);
2074         dspcntr = I915_READ(reg);
2075         /* Mask out pixel format bits in case we change it */
2076         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2077         switch (fb->bits_per_pixel) {
2078         case 8:
2079                 dspcntr |= DISPPLANE_8BPP;
2080                 break;
2081         case 16:
2082                 if (fb->depth != 16)
2083                         return -EINVAL;
2084
2085                 dspcntr |= DISPPLANE_16BPP;
2086                 break;
2087         case 24:
2088         case 32:
2089                 if (fb->depth == 24)
2090                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2091                 else if (fb->depth == 30)
2092                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2093                 else
2094                         return -EINVAL;
2095                 break;
2096         default:
2097                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2098                 return -EINVAL;
2099         }
2100
2101         if (obj->tiling_mode != I915_TILING_NONE)
2102                 dspcntr |= DISPPLANE_TILED;
2103         else
2104                 dspcntr &= ~DISPPLANE_TILED;
2105
2106         /* must disable */
2107         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2108
2109         I915_WRITE(reg, dspcntr);
2110
2111         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2112         intel_crtc->dspaddr_offset =
2113                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2114                                                    fb->bits_per_pixel / 8,
2115                                                    fb->pitches[0]);
2116         linear_offset -= intel_crtc->dspaddr_offset;
2117
2118         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2119                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2120         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2121         I915_MODIFY_DISPBASE(DSPSURF(plane),
2122                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2123         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2124         I915_WRITE(DSPLINOFF(plane), linear_offset);
2125         POSTING_READ(reg);
2126
2127         return 0;
2128 }
2129
2130 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2131 static int
2132 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2133                            int x, int y, enum mode_set_atomic state)
2134 {
2135         struct drm_device *dev = crtc->dev;
2136         struct drm_i915_private *dev_priv = dev->dev_private;
2137
2138         if (dev_priv->display.disable_fbc)
2139                 dev_priv->display.disable_fbc(dev);
2140         intel_increase_pllclock(crtc);
2141
2142         return dev_priv->display.update_plane(crtc, fb, x, y);
2143 }
2144
2145 static int
2146 intel_finish_fb(struct drm_framebuffer *old_fb)
2147 {
2148         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2149         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2150         bool was_interruptible = dev_priv->mm.interruptible;
2151         int ret;
2152
2153         wait_event(dev_priv->pending_flip_queue,
2154                    atomic_read(&dev_priv->mm.wedged) ||
2155                    atomic_read(&obj->pending_flip) == 0);
2156
2157         /* Big Hammer, we also need to ensure that any pending
2158          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2159          * current scanout is retired before unpinning the old
2160          * framebuffer.
2161          *
2162          * This should only fail upon a hung GPU, in which case we
2163          * can safely continue.
2164          */
2165         dev_priv->mm.interruptible = false;
2166         ret = i915_gem_object_finish_gpu(obj);
2167         dev_priv->mm.interruptible = was_interruptible;
2168
2169         return ret;
2170 }
2171
2172 static int
2173 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2174                     struct drm_framebuffer *fb)
2175 {
2176         struct drm_device *dev = crtc->dev;
2177         struct drm_i915_private *dev_priv = dev->dev_private;
2178         struct drm_i915_master_private *master_priv;
2179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180         struct drm_framebuffer *old_fb;
2181         int ret;
2182
2183         /* no fb bound */
2184         if (!fb) {
2185                 DRM_ERROR("No FB bound\n");
2186                 return 0;
2187         }
2188
2189         if(intel_crtc->plane > dev_priv->num_pipe) {
2190                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2191                                 intel_crtc->plane,
2192                                 dev_priv->num_pipe);
2193                 return -EINVAL;
2194         }
2195
2196         mutex_lock(&dev->struct_mutex);
2197         ret = intel_pin_and_fence_fb_obj(dev,
2198                                          to_intel_framebuffer(fb)->obj,
2199                                          NULL);
2200         if (ret != 0) {
2201                 mutex_unlock(&dev->struct_mutex);
2202                 DRM_ERROR("pin & fence failed\n");
2203                 return ret;
2204         }
2205
2206         if (crtc->fb)
2207                 intel_finish_fb(crtc->fb);
2208
2209         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2210         if (ret) {
2211                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2212                 mutex_unlock(&dev->struct_mutex);
2213                 DRM_ERROR("failed to update base address\n");
2214                 return ret;
2215         }
2216
2217         old_fb = crtc->fb;
2218         crtc->fb = fb;
2219         crtc->x = x;
2220         crtc->y = y;
2221
2222         if (old_fb) {
2223                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2224                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2225         }
2226
2227         intel_update_fbc(dev);
2228         mutex_unlock(&dev->struct_mutex);
2229
2230         if (!dev->primary->master)
2231                 return 0;
2232
2233         master_priv = dev->primary->master->driver_priv;
2234         if (!master_priv->sarea_priv)
2235                 return 0;
2236
2237         if (intel_crtc->pipe) {
2238                 master_priv->sarea_priv->pipeB_x = x;
2239                 master_priv->sarea_priv->pipeB_y = y;
2240         } else {
2241                 master_priv->sarea_priv->pipeA_x = x;
2242                 master_priv->sarea_priv->pipeA_y = y;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2249 {
2250         struct drm_device *dev = crtc->dev;
2251         struct drm_i915_private *dev_priv = dev->dev_private;
2252         u32 dpa_ctl;
2253
2254         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2255         dpa_ctl = I915_READ(DP_A);
2256         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2257
2258         if (clock < 200000) {
2259                 u32 temp;
2260                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2261                 /* workaround for 160Mhz:
2262                    1) program 0x4600c bits 15:0 = 0x8124
2263                    2) program 0x46010 bit 0 = 1
2264                    3) program 0x46034 bit 24 = 1
2265                    4) program 0x64000 bit 14 = 1
2266                    */
2267                 temp = I915_READ(0x4600c);
2268                 temp &= 0xffff0000;
2269                 I915_WRITE(0x4600c, temp | 0x8124);
2270
2271                 temp = I915_READ(0x46010);
2272                 I915_WRITE(0x46010, temp | 1);
2273
2274                 temp = I915_READ(0x46034);
2275                 I915_WRITE(0x46034, temp | (1 << 24));
2276         } else {
2277                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2278         }
2279         I915_WRITE(DP_A, dpa_ctl);
2280
2281         POSTING_READ(DP_A);
2282         udelay(500);
2283 }
2284
2285 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290         int pipe = intel_crtc->pipe;
2291         u32 reg, temp;
2292
2293         /* enable normal train */
2294         reg = FDI_TX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (IS_IVYBRIDGE(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2302         }
2303         I915_WRITE(reg, temp);
2304
2305         reg = FDI_RX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         if (HAS_PCH_CPT(dev)) {
2308                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310         } else {
2311                 temp &= ~FDI_LINK_TRAIN_NONE;
2312                 temp |= FDI_LINK_TRAIN_NONE;
2313         }
2314         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316         /* wait one idle pattern time */
2317         POSTING_READ(reg);
2318         udelay(1000);
2319
2320         /* IVB wants error correction enabled */
2321         if (IS_IVYBRIDGE(dev))
2322                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323                            FDI_FE_ERRC_ENABLE);
2324 }
2325
2326 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2327 {
2328         struct drm_i915_private *dev_priv = dev->dev_private;
2329         u32 flags = I915_READ(SOUTH_CHICKEN1);
2330
2331         flags |= FDI_PHASE_SYNC_OVR(pipe);
2332         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2333         flags |= FDI_PHASE_SYNC_EN(pipe);
2334         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2335         POSTING_READ(SOUTH_CHICKEN1);
2336 }
2337
2338 /* The FDI link training functions for ILK/Ibexpeak. */
2339 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2340 {
2341         struct drm_device *dev = crtc->dev;
2342         struct drm_i915_private *dev_priv = dev->dev_private;
2343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344         int pipe = intel_crtc->pipe;
2345         int plane = intel_crtc->plane;
2346         u32 reg, temp, tries;
2347
2348         /* FDI needs bits from pipe & plane first */
2349         assert_pipe_enabled(dev_priv, pipe);
2350         assert_plane_enabled(dev_priv, plane);
2351
2352         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2353            for train result */
2354         reg = FDI_RX_IMR(pipe);
2355         temp = I915_READ(reg);
2356         temp &= ~FDI_RX_SYMBOL_LOCK;
2357         temp &= ~FDI_RX_BIT_LOCK;
2358         I915_WRITE(reg, temp);
2359         I915_READ(reg);
2360         udelay(150);
2361
2362         /* enable CPU FDI TX and PCH FDI RX */
2363         reg = FDI_TX_CTL(pipe);
2364         temp = I915_READ(reg);
2365         temp &= ~(7 << 19);
2366         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2367         temp &= ~FDI_LINK_TRAIN_NONE;
2368         temp |= FDI_LINK_TRAIN_PATTERN_1;
2369         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2370
2371         reg = FDI_RX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~FDI_LINK_TRAIN_NONE;
2374         temp |= FDI_LINK_TRAIN_PATTERN_1;
2375         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2376
2377         POSTING_READ(reg);
2378         udelay(150);
2379
2380         /* Ironlake workaround, enable clock pointer after FDI enable*/
2381         if (HAS_PCH_IBX(dev)) {
2382                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384                            FDI_RX_PHASE_SYNC_POINTER_EN);
2385         }
2386
2387         reg = FDI_RX_IIR(pipe);
2388         for (tries = 0; tries < 5; tries++) {
2389                 temp = I915_READ(reg);
2390                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2391
2392                 if ((temp & FDI_RX_BIT_LOCK)) {
2393                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2394                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2395                         break;
2396                 }
2397         }
2398         if (tries == 5)
2399                 DRM_ERROR("FDI train 1 fail!\n");
2400
2401         /* Train 2 */
2402         reg = FDI_TX_CTL(pipe);
2403         temp = I915_READ(reg);
2404         temp &= ~FDI_LINK_TRAIN_NONE;
2405         temp |= FDI_LINK_TRAIN_PATTERN_2;
2406         I915_WRITE(reg, temp);
2407
2408         reg = FDI_RX_CTL(pipe);
2409         temp = I915_READ(reg);
2410         temp &= ~FDI_LINK_TRAIN_NONE;
2411         temp |= FDI_LINK_TRAIN_PATTERN_2;
2412         I915_WRITE(reg, temp);
2413
2414         POSTING_READ(reg);
2415         udelay(150);
2416
2417         reg = FDI_RX_IIR(pipe);
2418         for (tries = 0; tries < 5; tries++) {
2419                 temp = I915_READ(reg);
2420                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2421
2422                 if (temp & FDI_RX_SYMBOL_LOCK) {
2423                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2424                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2425                         break;
2426                 }
2427         }
2428         if (tries == 5)
2429                 DRM_ERROR("FDI train 2 fail!\n");
2430
2431         DRM_DEBUG_KMS("FDI train done\n");
2432
2433 }
2434
2435 static const int snb_b_fdi_train_param[] = {
2436         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2437         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2438         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2439         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2440 };
2441
2442 /* The FDI link training functions for SNB/Cougarpoint. */
2443 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2444 {
2445         struct drm_device *dev = crtc->dev;
2446         struct drm_i915_private *dev_priv = dev->dev_private;
2447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2448         int pipe = intel_crtc->pipe;
2449         u32 reg, temp, i, retry;
2450
2451         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2452            for train result */
2453         reg = FDI_RX_IMR(pipe);
2454         temp = I915_READ(reg);
2455         temp &= ~FDI_RX_SYMBOL_LOCK;
2456         temp &= ~FDI_RX_BIT_LOCK;
2457         I915_WRITE(reg, temp);
2458
2459         POSTING_READ(reg);
2460         udelay(150);
2461
2462         /* enable CPU FDI TX and PCH FDI RX */
2463         reg = FDI_TX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         temp &= ~(7 << 19);
2466         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_1;
2469         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470         /* SNB-B */
2471         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2473
2474         reg = FDI_RX_CTL(pipe);
2475         temp = I915_READ(reg);
2476         if (HAS_PCH_CPT(dev)) {
2477                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479         } else {
2480                 temp &= ~FDI_LINK_TRAIN_NONE;
2481                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         }
2483         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485         POSTING_READ(reg);
2486         udelay(150);
2487
2488         if (HAS_PCH_CPT(dev))
2489                 cpt_phase_pointer_enable(dev, pipe);
2490
2491         for (i = 0; i < 4; i++) {
2492                 reg = FDI_TX_CTL(pipe);
2493                 temp = I915_READ(reg);
2494                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2495                 temp |= snb_b_fdi_train_param[i];
2496                 I915_WRITE(reg, temp);
2497
2498                 POSTING_READ(reg);
2499                 udelay(500);
2500
2501                 for (retry = 0; retry < 5; retry++) {
2502                         reg = FDI_RX_IIR(pipe);
2503                         temp = I915_READ(reg);
2504                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2505                         if (temp & FDI_RX_BIT_LOCK) {
2506                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2508                                 break;
2509                         }
2510                         udelay(50);
2511                 }
2512                 if (retry < 5)
2513                         break;
2514         }
2515         if (i == 4)
2516                 DRM_ERROR("FDI train 1 fail!\n");
2517
2518         /* Train 2 */
2519         reg = FDI_TX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         temp &= ~FDI_LINK_TRAIN_NONE;
2522         temp |= FDI_LINK_TRAIN_PATTERN_2;
2523         if (IS_GEN6(dev)) {
2524                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525                 /* SNB-B */
2526                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2527         }
2528         I915_WRITE(reg, temp);
2529
2530         reg = FDI_RX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         if (HAS_PCH_CPT(dev)) {
2533                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2534                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2535         } else {
2536                 temp &= ~FDI_LINK_TRAIN_NONE;
2537                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2538         }
2539         I915_WRITE(reg, temp);
2540
2541         POSTING_READ(reg);
2542         udelay(150);
2543
2544         for (i = 0; i < 4; i++) {
2545                 reg = FDI_TX_CTL(pipe);
2546                 temp = I915_READ(reg);
2547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548                 temp |= snb_b_fdi_train_param[i];
2549                 I915_WRITE(reg, temp);
2550
2551                 POSTING_READ(reg);
2552                 udelay(500);
2553
2554                 for (retry = 0; retry < 5; retry++) {
2555                         reg = FDI_RX_IIR(pipe);
2556                         temp = I915_READ(reg);
2557                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2558                         if (temp & FDI_RX_SYMBOL_LOCK) {
2559                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2560                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2561                                 break;
2562                         }
2563                         udelay(50);
2564                 }
2565                 if (retry < 5)
2566                         break;
2567         }
2568         if (i == 4)
2569                 DRM_ERROR("FDI train 2 fail!\n");
2570
2571         DRM_DEBUG_KMS("FDI train done.\n");
2572 }
2573
2574 /* Manual link training for Ivy Bridge A0 parts */
2575 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2576 {
2577         struct drm_device *dev = crtc->dev;
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580         int pipe = intel_crtc->pipe;
2581         u32 reg, temp, i;
2582
2583         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2584            for train result */
2585         reg = FDI_RX_IMR(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~FDI_RX_SYMBOL_LOCK;
2588         temp &= ~FDI_RX_BIT_LOCK;
2589         I915_WRITE(reg, temp);
2590
2591         POSTING_READ(reg);
2592         udelay(150);
2593
2594         /* enable CPU FDI TX and PCH FDI RX */
2595         reg = FDI_TX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~(7 << 19);
2598         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2599         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603         temp |= FDI_COMPOSITE_SYNC;
2604         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
2606         reg = FDI_RX_CTL(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~FDI_LINK_TRAIN_AUTO;
2609         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2610         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2611         temp |= FDI_COMPOSITE_SYNC;
2612         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2613
2614         POSTING_READ(reg);
2615         udelay(150);
2616
2617         if (HAS_PCH_CPT(dev))
2618                 cpt_phase_pointer_enable(dev, pipe);
2619
2620         for (i = 0; i < 4; i++) {
2621                 reg = FDI_TX_CTL(pipe);
2622                 temp = I915_READ(reg);
2623                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624                 temp |= snb_b_fdi_train_param[i];
2625                 I915_WRITE(reg, temp);
2626
2627                 POSTING_READ(reg);
2628                 udelay(500);
2629
2630                 reg = FDI_RX_IIR(pipe);
2631                 temp = I915_READ(reg);
2632                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634                 if (temp & FDI_RX_BIT_LOCK ||
2635                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2638                         break;
2639                 }
2640         }
2641         if (i == 4)
2642                 DRM_ERROR("FDI train 1 fail!\n");
2643
2644         /* Train 2 */
2645         reg = FDI_TX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651         I915_WRITE(reg, temp);
2652
2653         reg = FDI_RX_CTL(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         for (i = 0; i < 4; i++) {
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[i];
2667                 I915_WRITE(reg, temp);
2668
2669                 POSTING_READ(reg);
2670                 udelay(500);
2671
2672                 reg = FDI_RX_IIR(pipe);
2673                 temp = I915_READ(reg);
2674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676                 if (temp & FDI_RX_SYMBOL_LOCK) {
2677                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2679                         break;
2680                 }
2681         }
2682         if (i == 4)
2683                 DRM_ERROR("FDI train 2 fail!\n");
2684
2685         DRM_DEBUG_KMS("FDI train done.\n");
2686 }
2687
2688 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2689 {
2690         struct drm_device *dev = intel_crtc->base.dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp;
2694
2695         /* Write the TU size bits so error detection works */
2696         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2697                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2698
2699         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2700         reg = FDI_RX_CTL(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~((0x7 << 19) | (0x7 << 16));
2703         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2704         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2705         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2706
2707         POSTING_READ(reg);
2708         udelay(200);
2709
2710         /* Switch from Rawclk to PCDclk */
2711         temp = I915_READ(reg);
2712         I915_WRITE(reg, temp | FDI_PCDCLK);
2713
2714         POSTING_READ(reg);
2715         udelay(200);
2716
2717         /* On Haswell, the PLL configuration for ports and pipes is handled
2718          * separately, as part of DDI setup */
2719         if (!IS_HASWELL(dev)) {
2720                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2721                 reg = FDI_TX_CTL(pipe);
2722                 temp = I915_READ(reg);
2723                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2724                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2725
2726                         POSTING_READ(reg);
2727                         udelay(100);
2728                 }
2729         }
2730 }
2731
2732 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2733 {
2734         struct drm_device *dev = intel_crtc->base.dev;
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         int pipe = intel_crtc->pipe;
2737         u32 reg, temp;
2738
2739         /* Switch from PCDclk to Rawclk */
2740         reg = FDI_RX_CTL(pipe);
2741         temp = I915_READ(reg);
2742         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2743
2744         /* Disable CPU FDI TX PLL */
2745         reg = FDI_TX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2748
2749         POSTING_READ(reg);
2750         udelay(100);
2751
2752         reg = FDI_RX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2755
2756         /* Wait for the clocks to turn off. */
2757         POSTING_READ(reg);
2758         udelay(100);
2759 }
2760
2761 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2762 {
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         u32 flags = I915_READ(SOUTH_CHICKEN1);
2765
2766         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2767         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2768         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2769         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2770         POSTING_READ(SOUTH_CHICKEN1);
2771 }
2772 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2773 {
2774         struct drm_device *dev = crtc->dev;
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777         int pipe = intel_crtc->pipe;
2778         u32 reg, temp;
2779
2780         /* disable CPU FDI tx and PCH FDI rx */
2781         reg = FDI_TX_CTL(pipe);
2782         temp = I915_READ(reg);
2783         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2784         POSTING_READ(reg);
2785
2786         reg = FDI_RX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         temp &= ~(0x7 << 16);
2789         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2790         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2791
2792         POSTING_READ(reg);
2793         udelay(100);
2794
2795         /* Ironlake workaround, disable clock pointer after downing FDI */
2796         if (HAS_PCH_IBX(dev)) {
2797                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2799                            I915_READ(FDI_RX_CHICKEN(pipe) &
2800                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2801         } else if (HAS_PCH_CPT(dev)) {
2802                 cpt_phase_pointer_disable(dev, pipe);
2803         }
2804
2805         /* still set train pattern 1 */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_LINK_TRAIN_NONE;
2809         temp |= FDI_LINK_TRAIN_PATTERN_1;
2810         I915_WRITE(reg, temp);
2811
2812         reg = FDI_RX_CTL(pipe);
2813         temp = I915_READ(reg);
2814         if (HAS_PCH_CPT(dev)) {
2815                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2816                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2817         } else {
2818                 temp &= ~FDI_LINK_TRAIN_NONE;
2819                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2820         }
2821         /* BPC in FDI rx is consistent with that in PIPECONF */
2822         temp &= ~(0x07 << 16);
2823         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2824         I915_WRITE(reg, temp);
2825
2826         POSTING_READ(reg);
2827         udelay(100);
2828 }
2829
2830 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2831 {
2832         struct drm_device *dev = crtc->dev;
2833         struct drm_i915_private *dev_priv = dev->dev_private;
2834         unsigned long flags;
2835         bool pending;
2836
2837         if (atomic_read(&dev_priv->mm.wedged))
2838                 return false;
2839
2840         spin_lock_irqsave(&dev->event_lock, flags);
2841         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2842         spin_unlock_irqrestore(&dev->event_lock, flags);
2843
2844         return pending;
2845 }
2846
2847 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2848 {
2849         struct drm_device *dev = crtc->dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851
2852         if (crtc->fb == NULL)
2853                 return;
2854
2855         wait_event(dev_priv->pending_flip_queue,
2856                    !intel_crtc_has_pending_flip(crtc));
2857
2858         mutex_lock(&dev->struct_mutex);
2859         intel_finish_fb(crtc->fb);
2860         mutex_unlock(&dev->struct_mutex);
2861 }
2862
2863 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2864 {
2865         struct drm_device *dev = crtc->dev;
2866         struct intel_encoder *intel_encoder;
2867
2868         /*
2869          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2870          * must be driven by its own crtc; no sharing is possible.
2871          */
2872         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2873                 switch (intel_encoder->type) {
2874                 case INTEL_OUTPUT_EDP:
2875                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2876                                 return false;
2877                         continue;
2878                 }
2879         }
2880
2881         return true;
2882 }
2883
2884 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2885 {
2886         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2887 }
2888
2889 /* Program iCLKIP clock to the desired frequency */
2890 static void lpt_program_iclkip(struct drm_crtc *crtc)
2891 {
2892         struct drm_device *dev = crtc->dev;
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2895         u32 temp;
2896
2897         /* It is necessary to ungate the pixclk gate prior to programming
2898          * the divisors, and gate it back when it is done.
2899          */
2900         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2901
2902         /* Disable SSCCTL */
2903         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2904                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2905                                         SBI_SSCCTL_DISABLE);
2906
2907         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2908         if (crtc->mode.clock == 20000) {
2909                 auxdiv = 1;
2910                 divsel = 0x41;
2911                 phaseinc = 0x20;
2912         } else {
2913                 /* The iCLK virtual clock root frequency is in MHz,
2914                  * but the crtc->mode.clock in in KHz. To get the divisors,
2915                  * it is necessary to divide one by another, so we
2916                  * convert the virtual clock precision to KHz here for higher
2917                  * precision.
2918                  */
2919                 u32 iclk_virtual_root_freq = 172800 * 1000;
2920                 u32 iclk_pi_range = 64;
2921                 u32 desired_divisor, msb_divisor_value, pi_value;
2922
2923                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2924                 msb_divisor_value = desired_divisor / iclk_pi_range;
2925                 pi_value = desired_divisor % iclk_pi_range;
2926
2927                 auxdiv = 0;
2928                 divsel = msb_divisor_value - 2;
2929                 phaseinc = pi_value;
2930         }
2931
2932         /* This should not happen with any sane values */
2933         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2934                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2935         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2936                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2937
2938         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2939                         crtc->mode.clock,
2940                         auxdiv,
2941                         divsel,
2942                         phasedir,
2943                         phaseinc);
2944
2945         /* Program SSCDIVINTPHASE6 */
2946         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2947         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2948         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2949         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2950         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2951         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2952         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2953
2954         intel_sbi_write(dev_priv,
2955                         SBI_SSCDIVINTPHASE6,
2956                         temp);
2957
2958         /* Program SSCAUXDIV */
2959         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2960         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2961         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2962         intel_sbi_write(dev_priv,
2963                         SBI_SSCAUXDIV6,
2964                         temp);
2965
2966
2967         /* Enable modulator and associated divider */
2968         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2969         temp &= ~SBI_SSCCTL_DISABLE;
2970         intel_sbi_write(dev_priv,
2971                         SBI_SSCCTL6,
2972                         temp);
2973
2974         /* Wait for initialization time */
2975         udelay(24);
2976
2977         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2978 }
2979
2980 /*
2981  * Enable PCH resources required for PCH ports:
2982  *   - PCH PLLs
2983  *   - FDI training & RX/TX
2984  *   - update transcoder timings
2985  *   - DP transcoding bits
2986  *   - transcoder
2987  */
2988 static void ironlake_pch_enable(struct drm_crtc *crtc)
2989 {
2990         struct drm_device *dev = crtc->dev;
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2993         int pipe = intel_crtc->pipe;
2994         u32 reg, temp;
2995
2996         assert_transcoder_disabled(dev_priv, pipe);
2997
2998         /* For PCH output, training FDI link */
2999         dev_priv->display.fdi_link_train(crtc);
3000
3001         intel_enable_pch_pll(intel_crtc);
3002
3003         if (HAS_PCH_LPT(dev)) {
3004                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3005                 lpt_program_iclkip(crtc);
3006         } else if (HAS_PCH_CPT(dev)) {
3007                 u32 sel;
3008
3009                 temp = I915_READ(PCH_DPLL_SEL);
3010                 switch (pipe) {
3011                 default:
3012                 case 0:
3013                         temp |= TRANSA_DPLL_ENABLE;
3014                         sel = TRANSA_DPLLB_SEL;
3015                         break;
3016                 case 1:
3017                         temp |= TRANSB_DPLL_ENABLE;
3018                         sel = TRANSB_DPLLB_SEL;
3019                         break;
3020                 case 2:
3021                         temp |= TRANSC_DPLL_ENABLE;
3022                         sel = TRANSC_DPLLB_SEL;
3023                         break;
3024                 }
3025                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3026                         temp |= sel;
3027                 else
3028                         temp &= ~sel;
3029                 I915_WRITE(PCH_DPLL_SEL, temp);
3030         }
3031
3032         /* set transcoder timing, panel must allow it */
3033         assert_panel_unlocked(dev_priv, pipe);
3034         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3035         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3036         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3037
3038         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3039         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3040         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3041         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3042
3043         if (!IS_HASWELL(dev))
3044                 intel_fdi_normal_train(crtc);
3045
3046         /* For PCH DP, enable TRANS_DP_CTL */
3047         if (HAS_PCH_CPT(dev) &&
3048             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3049              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3050                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3051                 reg = TRANS_DP_CTL(pipe);
3052                 temp = I915_READ(reg);
3053                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3054                           TRANS_DP_SYNC_MASK |
3055                           TRANS_DP_BPC_MASK);
3056                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3057                          TRANS_DP_ENH_FRAMING);
3058                 temp |= bpc << 9; /* same format but at 11:9 */
3059
3060                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3061                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3062                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3063                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3064
3065                 switch (intel_trans_dp_port_sel(crtc)) {
3066                 case PCH_DP_B:
3067                         temp |= TRANS_DP_PORT_SEL_B;
3068                         break;
3069                 case PCH_DP_C:
3070                         temp |= TRANS_DP_PORT_SEL_C;
3071                         break;
3072                 case PCH_DP_D:
3073                         temp |= TRANS_DP_PORT_SEL_D;
3074                         break;
3075                 default:
3076                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3077                         temp |= TRANS_DP_PORT_SEL_B;
3078                         break;
3079                 }
3080
3081                 I915_WRITE(reg, temp);
3082         }
3083
3084         intel_enable_transcoder(dev_priv, pipe);
3085 }
3086
3087 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3088 {
3089         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3090
3091         if (pll == NULL)
3092                 return;
3093
3094         if (pll->refcount == 0) {
3095                 WARN(1, "bad PCH PLL refcount\n");
3096                 return;
3097         }
3098
3099         --pll->refcount;
3100         intel_crtc->pch_pll = NULL;
3101 }
3102
3103 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3104 {
3105         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3106         struct intel_pch_pll *pll;
3107         int i;
3108
3109         pll = intel_crtc->pch_pll;
3110         if (pll) {
3111                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3112                               intel_crtc->base.base.id, pll->pll_reg);
3113                 goto prepare;
3114         }
3115
3116         if (HAS_PCH_IBX(dev_priv->dev)) {
3117                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3118                 i = intel_crtc->pipe;
3119                 pll = &dev_priv->pch_plls[i];
3120
3121                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3122                               intel_crtc->base.base.id, pll->pll_reg);
3123
3124                 goto found;
3125         }
3126
3127         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3128                 pll = &dev_priv->pch_plls[i];
3129
3130                 /* Only want to check enabled timings first */
3131                 if (pll->refcount == 0)
3132                         continue;
3133
3134                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3135                     fp == I915_READ(pll->fp0_reg)) {
3136                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3137                                       intel_crtc->base.base.id,
3138                                       pll->pll_reg, pll->refcount, pll->active);
3139
3140                         goto found;
3141                 }
3142         }
3143
3144         /* Ok no matching timings, maybe there's a free one? */
3145         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3146                 pll = &dev_priv->pch_plls[i];
3147                 if (pll->refcount == 0) {
3148                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3149                                       intel_crtc->base.base.id, pll->pll_reg);
3150                         goto found;
3151                 }
3152         }
3153
3154         return NULL;
3155
3156 found:
3157         intel_crtc->pch_pll = pll;
3158         pll->refcount++;
3159         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3160 prepare: /* separate function? */
3161         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3162
3163         /* Wait for the clocks to stabilize before rewriting the regs */
3164         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3165         POSTING_READ(pll->pll_reg);
3166         udelay(150);
3167
3168         I915_WRITE(pll->fp0_reg, fp);
3169         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3170         pll->on = false;
3171         return pll;
3172 }
3173
3174 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3175 {
3176         struct drm_i915_private *dev_priv = dev->dev_private;
3177         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3178         u32 temp;
3179
3180         temp = I915_READ(dslreg);
3181         udelay(500);
3182         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3183                 /* Without this, mode sets may fail silently on FDI */
3184                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3185                 udelay(250);
3186                 I915_WRITE(tc2reg, 0);
3187                 if (wait_for(I915_READ(dslreg) != temp, 5))
3188                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3189         }
3190 }
3191
3192 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3193 {
3194         struct drm_device *dev = crtc->dev;
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3197         struct intel_encoder *encoder;
3198         int pipe = intel_crtc->pipe;
3199         int plane = intel_crtc->plane;
3200         u32 temp;
3201         bool is_pch_port;
3202
3203         WARN_ON(!crtc->enabled);
3204
3205         if (intel_crtc->active)
3206                 return;
3207
3208         intel_crtc->active = true;
3209         intel_update_watermarks(dev);
3210
3211         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3212                 temp = I915_READ(PCH_LVDS);
3213                 if ((temp & LVDS_PORT_EN) == 0)
3214                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3215         }
3216
3217         is_pch_port = ironlake_crtc_driving_pch(crtc);
3218
3219         if (is_pch_port) {
3220                 ironlake_fdi_pll_enable(intel_crtc);
3221         } else {
3222                 assert_fdi_tx_disabled(dev_priv, pipe);
3223                 assert_fdi_rx_disabled(dev_priv, pipe);
3224         }
3225
3226         for_each_encoder_on_crtc(dev, crtc, encoder)
3227                 if (encoder->pre_enable)
3228                         encoder->pre_enable(encoder);
3229
3230         /* Enable panel fitting for LVDS */
3231         if (dev_priv->pch_pf_size &&
3232             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3233                 /* Force use of hard-coded filter coefficients
3234                  * as some pre-programmed values are broken,
3235                  * e.g. x201.
3236                  */
3237                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3238                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3239                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3240         }
3241
3242         /*
3243          * On ILK+ LUT must be loaded before the pipe is running but with
3244          * clocks enabled
3245          */
3246         intel_crtc_load_lut(crtc);
3247
3248         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3249         intel_enable_plane(dev_priv, plane, pipe);
3250
3251         if (is_pch_port)
3252                 ironlake_pch_enable(crtc);
3253
3254         mutex_lock(&dev->struct_mutex);
3255         intel_update_fbc(dev);
3256         mutex_unlock(&dev->struct_mutex);
3257
3258         intel_crtc_update_cursor(crtc, true);
3259
3260         for_each_encoder_on_crtc(dev, crtc, encoder)
3261                 encoder->enable(encoder);
3262
3263         if (HAS_PCH_CPT(dev))
3264                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3265
3266         /*
3267          * There seems to be a race in PCH platform hw (at least on some
3268          * outputs) where an enabled pipe still completes any pageflip right
3269          * away (as if the pipe is off) instead of waiting for vblank. As soon
3270          * as the first vblank happend, everything works as expected. Hence just
3271          * wait for one vblank before returning to avoid strange things
3272          * happening.
3273          */
3274         intel_wait_for_vblank(dev, intel_crtc->pipe);
3275 }
3276
3277 static void haswell_crtc_enable(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282         struct intel_encoder *encoder;
3283         int pipe = intel_crtc->pipe;
3284         int plane = intel_crtc->plane;
3285         bool is_pch_port;
3286
3287         WARN_ON(!crtc->enabled);
3288
3289         if (intel_crtc->active)
3290                 return;
3291
3292         intel_crtc->active = true;
3293         intel_update_watermarks(dev);
3294
3295         is_pch_port = haswell_crtc_driving_pch(crtc);
3296
3297         if (is_pch_port)
3298                 ironlake_fdi_pll_enable(intel_crtc);
3299
3300         for_each_encoder_on_crtc(dev, crtc, encoder)
3301                 if (encoder->pre_enable)
3302                         encoder->pre_enable(encoder);
3303
3304         intel_ddi_enable_pipe_clock(intel_crtc);
3305
3306         /* Enable panel fitting for eDP */
3307         if (dev_priv->pch_pf_size && HAS_eDP) {
3308                 /* Force use of hard-coded filter coefficients
3309                  * as some pre-programmed values are broken,
3310                  * e.g. x201.
3311                  */
3312                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3313                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3314                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3315         }
3316
3317         /*
3318          * On ILK+ LUT must be loaded before the pipe is running but with
3319          * clocks enabled
3320          */
3321         intel_crtc_load_lut(crtc);
3322
3323         intel_ddi_set_pipe_settings(crtc);
3324         intel_ddi_enable_pipe_func(crtc);
3325
3326         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3327         intel_enable_plane(dev_priv, plane, pipe);
3328
3329         if (is_pch_port)
3330                 ironlake_pch_enable(crtc);
3331
3332         mutex_lock(&dev->struct_mutex);
3333         intel_update_fbc(dev);
3334         mutex_unlock(&dev->struct_mutex);
3335
3336         intel_crtc_update_cursor(crtc, true);
3337
3338         for_each_encoder_on_crtc(dev, crtc, encoder)
3339                 encoder->enable(encoder);
3340
3341         /*
3342          * There seems to be a race in PCH platform hw (at least on some
3343          * outputs) where an enabled pipe still completes any pageflip right
3344          * away (as if the pipe is off) instead of waiting for vblank. As soon
3345          * as the first vblank happend, everything works as expected. Hence just
3346          * wait for one vblank before returning to avoid strange things
3347          * happening.
3348          */
3349         intel_wait_for_vblank(dev, intel_crtc->pipe);
3350 }
3351
3352 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3353 {
3354         struct drm_device *dev = crtc->dev;
3355         struct drm_i915_private *dev_priv = dev->dev_private;
3356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357         struct intel_encoder *encoder;
3358         int pipe = intel_crtc->pipe;
3359         int plane = intel_crtc->plane;
3360         u32 reg, temp;
3361
3362
3363         if (!intel_crtc->active)
3364                 return;
3365
3366         for_each_encoder_on_crtc(dev, crtc, encoder)
3367                 encoder->disable(encoder);
3368
3369         intel_crtc_wait_for_pending_flips(crtc);
3370         drm_vblank_off(dev, pipe);
3371         intel_crtc_update_cursor(crtc, false);
3372
3373         intel_disable_plane(dev_priv, plane, pipe);
3374
3375         if (dev_priv->cfb_plane == plane)
3376                 intel_disable_fbc(dev);
3377
3378         intel_disable_pipe(dev_priv, pipe);
3379
3380         /* Disable PF */
3381         I915_WRITE(PF_CTL(pipe), 0);
3382         I915_WRITE(PF_WIN_SZ(pipe), 0);
3383
3384         for_each_encoder_on_crtc(dev, crtc, encoder)
3385                 if (encoder->post_disable)
3386                         encoder->post_disable(encoder);
3387
3388         ironlake_fdi_disable(crtc);
3389
3390         intel_disable_transcoder(dev_priv, pipe);
3391
3392         if (HAS_PCH_CPT(dev)) {
3393                 /* disable TRANS_DP_CTL */
3394                 reg = TRANS_DP_CTL(pipe);
3395                 temp = I915_READ(reg);
3396                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3397                 temp |= TRANS_DP_PORT_SEL_NONE;
3398                 I915_WRITE(reg, temp);
3399
3400                 /* disable DPLL_SEL */
3401                 temp = I915_READ(PCH_DPLL_SEL);
3402                 switch (pipe) {
3403                 case 0:
3404                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3405                         break;
3406                 case 1:
3407                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3408                         break;
3409                 case 2:
3410                         /* C shares PLL A or B */
3411                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3412                         break;
3413                 default:
3414                         BUG(); /* wtf */
3415                 }
3416                 I915_WRITE(PCH_DPLL_SEL, temp);
3417         }
3418
3419         /* disable PCH DPLL */
3420         intel_disable_pch_pll(intel_crtc);
3421
3422         ironlake_fdi_pll_disable(intel_crtc);
3423
3424         intel_crtc->active = false;
3425         intel_update_watermarks(dev);
3426
3427         mutex_lock(&dev->struct_mutex);
3428         intel_update_fbc(dev);
3429         mutex_unlock(&dev->struct_mutex);
3430 }
3431
3432 static void haswell_crtc_disable(struct drm_crtc *crtc)
3433 {
3434         struct drm_device *dev = crtc->dev;
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437         struct intel_encoder *encoder;
3438         int pipe = intel_crtc->pipe;
3439         int plane = intel_crtc->plane;
3440         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3441         bool is_pch_port;
3442
3443         if (!intel_crtc->active)
3444                 return;
3445
3446         is_pch_port = haswell_crtc_driving_pch(crtc);
3447
3448         for_each_encoder_on_crtc(dev, crtc, encoder)
3449                 encoder->disable(encoder);
3450
3451         intel_crtc_wait_for_pending_flips(crtc);
3452         drm_vblank_off(dev, pipe);
3453         intel_crtc_update_cursor(crtc, false);
3454
3455         intel_disable_plane(dev_priv, plane, pipe);
3456
3457         if (dev_priv->cfb_plane == plane)
3458                 intel_disable_fbc(dev);
3459
3460         intel_disable_pipe(dev_priv, pipe);
3461
3462         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3463
3464         /* Disable PF */
3465         I915_WRITE(PF_CTL(pipe), 0);
3466         I915_WRITE(PF_WIN_SZ(pipe), 0);
3467
3468         intel_ddi_disable_pipe_clock(intel_crtc);
3469
3470         for_each_encoder_on_crtc(dev, crtc, encoder)
3471                 if (encoder->post_disable)
3472                         encoder->post_disable(encoder);
3473
3474         if (is_pch_port) {
3475                 ironlake_fdi_disable(crtc);
3476                 intel_disable_transcoder(dev_priv, pipe);
3477                 intel_disable_pch_pll(intel_crtc);
3478                 ironlake_fdi_pll_disable(intel_crtc);
3479         }
3480
3481         intel_crtc->active = false;
3482         intel_update_watermarks(dev);
3483
3484         mutex_lock(&dev->struct_mutex);
3485         intel_update_fbc(dev);
3486         mutex_unlock(&dev->struct_mutex);
3487 }
3488
3489 static void ironlake_crtc_off(struct drm_crtc *crtc)
3490 {
3491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492         intel_put_pch_pll(intel_crtc);
3493 }
3494
3495 static void haswell_crtc_off(struct drm_crtc *crtc)
3496 {
3497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3498
3499         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3500          * start using it. */
3501         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3502
3503         intel_ddi_put_crtc_pll(crtc);
3504 }
3505
3506 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3507 {
3508         if (!enable && intel_crtc->overlay) {
3509                 struct drm_device *dev = intel_crtc->base.dev;
3510                 struct drm_i915_private *dev_priv = dev->dev_private;
3511
3512                 mutex_lock(&dev->struct_mutex);
3513                 dev_priv->mm.interruptible = false;
3514                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3515                 dev_priv->mm.interruptible = true;
3516                 mutex_unlock(&dev->struct_mutex);
3517         }
3518
3519         /* Let userspace switch the overlay on again. In most cases userspace
3520          * has to recompute where to put it anyway.
3521          */
3522 }
3523
3524 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3525 {
3526         struct drm_device *dev = crtc->dev;
3527         struct drm_i915_private *dev_priv = dev->dev_private;
3528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3529         struct intel_encoder *encoder;
3530         int pipe = intel_crtc->pipe;
3531         int plane = intel_crtc->plane;
3532
3533         WARN_ON(!crtc->enabled);
3534
3535         if (intel_crtc->active)
3536                 return;
3537
3538         intel_crtc->active = true;
3539         intel_update_watermarks(dev);
3540
3541         intel_enable_pll(dev_priv, pipe);
3542         intel_enable_pipe(dev_priv, pipe, false);
3543         intel_enable_plane(dev_priv, plane, pipe);
3544
3545         intel_crtc_load_lut(crtc);
3546         intel_update_fbc(dev);
3547
3548         /* Give the overlay scaler a chance to enable if it's on this pipe */
3549         intel_crtc_dpms_overlay(intel_crtc, true);
3550         intel_crtc_update_cursor(crtc, true);
3551
3552         for_each_encoder_on_crtc(dev, crtc, encoder)
3553                 encoder->enable(encoder);
3554 }
3555
3556 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3557 {
3558         struct drm_device *dev = crtc->dev;
3559         struct drm_i915_private *dev_priv = dev->dev_private;
3560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561         struct intel_encoder *encoder;
3562         int pipe = intel_crtc->pipe;
3563         int plane = intel_crtc->plane;
3564
3565
3566         if (!intel_crtc->active)
3567                 return;
3568
3569         for_each_encoder_on_crtc(dev, crtc, encoder)
3570                 encoder->disable(encoder);
3571
3572         /* Give the overlay scaler a chance to disable if it's on this pipe */
3573         intel_crtc_wait_for_pending_flips(crtc);
3574         drm_vblank_off(dev, pipe);
3575         intel_crtc_dpms_overlay(intel_crtc, false);
3576         intel_crtc_update_cursor(crtc, false);
3577
3578         if (dev_priv->cfb_plane == plane)
3579                 intel_disable_fbc(dev);
3580
3581         intel_disable_plane(dev_priv, plane, pipe);
3582         intel_disable_pipe(dev_priv, pipe);
3583         intel_disable_pll(dev_priv, pipe);
3584
3585         intel_crtc->active = false;
3586         intel_update_fbc(dev);
3587         intel_update_watermarks(dev);
3588 }
3589
3590 static void i9xx_crtc_off(struct drm_crtc *crtc)
3591 {
3592 }
3593
3594 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3595                                     bool enabled)
3596 {
3597         struct drm_device *dev = crtc->dev;
3598         struct drm_i915_master_private *master_priv;
3599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600         int pipe = intel_crtc->pipe;
3601
3602         if (!dev->primary->master)
3603                 return;
3604
3605         master_priv = dev->primary->master->driver_priv;
3606         if (!master_priv->sarea_priv)
3607                 return;
3608
3609         switch (pipe) {
3610         case 0:
3611                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3612                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3613                 break;
3614         case 1:
3615                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3616                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3617                 break;
3618         default:
3619                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3620                 break;
3621         }
3622 }
3623
3624 /**
3625  * Sets the power management mode of the pipe and plane.
3626  */
3627 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3628 {
3629         struct drm_device *dev = crtc->dev;
3630         struct drm_i915_private *dev_priv = dev->dev_private;
3631         struct intel_encoder *intel_encoder;
3632         bool enable = false;
3633
3634         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3635                 enable |= intel_encoder->connectors_active;
3636
3637         if (enable)
3638                 dev_priv->display.crtc_enable(crtc);
3639         else
3640                 dev_priv->display.crtc_disable(crtc);
3641
3642         intel_crtc_update_sarea(crtc, enable);
3643 }
3644
3645 static void intel_crtc_noop(struct drm_crtc *crtc)
3646 {
3647 }
3648
3649 static void intel_crtc_disable(struct drm_crtc *crtc)
3650 {
3651         struct drm_device *dev = crtc->dev;
3652         struct drm_connector *connector;
3653         struct drm_i915_private *dev_priv = dev->dev_private;
3654
3655         /* crtc should still be enabled when we disable it. */
3656         WARN_ON(!crtc->enabled);
3657
3658         dev_priv->display.crtc_disable(crtc);
3659         intel_crtc_update_sarea(crtc, false);
3660         dev_priv->display.off(crtc);
3661
3662         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3663         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3664
3665         if (crtc->fb) {
3666                 mutex_lock(&dev->struct_mutex);
3667                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3668                 mutex_unlock(&dev->struct_mutex);
3669                 crtc->fb = NULL;
3670         }
3671
3672         /* Update computed state. */
3673         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3674                 if (!connector->encoder || !connector->encoder->crtc)
3675                         continue;
3676
3677                 if (connector->encoder->crtc != crtc)
3678                         continue;
3679
3680                 connector->dpms = DRM_MODE_DPMS_OFF;
3681                 to_intel_encoder(connector->encoder)->connectors_active = false;
3682         }
3683 }
3684
3685 void intel_modeset_disable(struct drm_device *dev)
3686 {
3687         struct drm_crtc *crtc;
3688
3689         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3690                 if (crtc->enabled)
3691                         intel_crtc_disable(crtc);
3692         }
3693 }
3694
3695 void intel_encoder_noop(struct drm_encoder *encoder)
3696 {
3697 }
3698
3699 void intel_encoder_destroy(struct drm_encoder *encoder)
3700 {
3701         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3702
3703         drm_encoder_cleanup(encoder);
3704         kfree(intel_encoder);
3705 }
3706
3707 /* Simple dpms helper for encodres with just one connector, no cloning and only
3708  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3709  * state of the entire output pipe. */
3710 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3711 {
3712         if (mode == DRM_MODE_DPMS_ON) {
3713                 encoder->connectors_active = true;
3714
3715                 intel_crtc_update_dpms(encoder->base.crtc);
3716         } else {
3717                 encoder->connectors_active = false;
3718
3719                 intel_crtc_update_dpms(encoder->base.crtc);
3720         }
3721 }
3722
3723 /* Cross check the actual hw state with our own modeset state tracking (and it's
3724  * internal consistency). */
3725 static void intel_connector_check_state(struct intel_connector *connector)
3726 {
3727         if (connector->get_hw_state(connector)) {
3728                 struct intel_encoder *encoder = connector->encoder;
3729                 struct drm_crtc *crtc;
3730                 bool encoder_enabled;
3731                 enum pipe pipe;
3732
3733                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3734                               connector->base.base.id,
3735                               drm_get_connector_name(&connector->base));
3736
3737                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3738                      "wrong connector dpms state\n");
3739                 WARN(connector->base.encoder != &encoder->base,
3740                      "active connector not linked to encoder\n");
3741                 WARN(!encoder->connectors_active,
3742                      "encoder->connectors_active not set\n");
3743
3744                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3745                 WARN(!encoder_enabled, "encoder not enabled\n");
3746                 if (WARN_ON(!encoder->base.crtc))
3747                         return;
3748
3749                 crtc = encoder->base.crtc;
3750
3751                 WARN(!crtc->enabled, "crtc not enabled\n");
3752                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3753                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3754                      "encoder active on the wrong pipe\n");
3755         }
3756 }
3757
3758 /* Even simpler default implementation, if there's really no special case to
3759  * consider. */
3760 void intel_connector_dpms(struct drm_connector *connector, int mode)
3761 {
3762         struct intel_encoder *encoder = intel_attached_encoder(connector);
3763
3764         /* All the simple cases only support two dpms states. */
3765         if (mode != DRM_MODE_DPMS_ON)
3766                 mode = DRM_MODE_DPMS_OFF;
3767
3768         if (mode == connector->dpms)
3769                 return;
3770
3771         connector->dpms = mode;
3772
3773         /* Only need to change hw state when actually enabled */
3774         if (encoder->base.crtc)
3775                 intel_encoder_dpms(encoder, mode);
3776         else
3777                 WARN_ON(encoder->connectors_active != false);
3778
3779         intel_modeset_check_state(connector->dev);
3780 }
3781
3782 /* Simple connector->get_hw_state implementation for encoders that support only
3783  * one connector and no cloning and hence the encoder state determines the state
3784  * of the connector. */
3785 bool intel_connector_get_hw_state(struct intel_connector *connector)
3786 {
3787         enum pipe pipe = 0;
3788         struct intel_encoder *encoder = connector->encoder;
3789
3790         return encoder->get_hw_state(encoder, &pipe);
3791 }
3792
3793 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3794                                   const struct drm_display_mode *mode,
3795                                   struct drm_display_mode *adjusted_mode)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798
3799         if (HAS_PCH_SPLIT(dev)) {
3800                 /* FDI link clock is fixed at 2.7G */
3801                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3802                         return false;
3803         }
3804
3805         /* All interlaced capable intel hw wants timings in frames. Note though
3806          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3807          * timings, so we need to be careful not to clobber these.*/
3808         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3809                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3810
3811         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3812          * with a hsync front porch of 0.
3813          */
3814         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3815                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3816                 return false;
3817
3818         return true;
3819 }
3820
3821 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3822 {
3823         return 400000; /* FIXME */
3824 }
3825
3826 static int i945_get_display_clock_speed(struct drm_device *dev)
3827 {
3828         return 400000;
3829 }
3830
3831 static int i915_get_display_clock_speed(struct drm_device *dev)
3832 {
3833         return 333000;
3834 }
3835
3836 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3837 {
3838         return 200000;
3839 }
3840
3841 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3842 {
3843         u16 gcfgc = 0;
3844
3845         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3846
3847         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3848                 return 133000;
3849         else {
3850                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3851                 case GC_DISPLAY_CLOCK_333_MHZ:
3852                         return 333000;
3853                 default:
3854                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3855                         return 190000;
3856                 }
3857         }
3858 }
3859
3860 static int i865_get_display_clock_speed(struct drm_device *dev)
3861 {
3862         return 266000;
3863 }
3864
3865 static int i855_get_display_clock_speed(struct drm_device *dev)
3866 {
3867         u16 hpllcc = 0;
3868         /* Assume that the hardware is in the high speed state.  This
3869          * should be the default.
3870          */
3871         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3872         case GC_CLOCK_133_200:
3873         case GC_CLOCK_100_200:
3874                 return 200000;
3875         case GC_CLOCK_166_250:
3876                 return 250000;
3877         case GC_CLOCK_100_133:
3878                 return 133000;
3879         }
3880
3881         /* Shouldn't happen */
3882         return 0;
3883 }
3884
3885 static int i830_get_display_clock_speed(struct drm_device *dev)
3886 {
3887         return 133000;
3888 }
3889
3890 struct fdi_m_n {
3891         u32        tu;
3892         u32        gmch_m;
3893         u32        gmch_n;
3894         u32        link_m;
3895         u32        link_n;
3896 };
3897
3898 static void
3899 fdi_reduce_ratio(u32 *num, u32 *den)
3900 {
3901         while (*num > 0xffffff || *den > 0xffffff) {
3902                 *num >>= 1;
3903                 *den >>= 1;
3904         }
3905 }
3906
3907 static void
3908 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3909                      int link_clock, struct fdi_m_n *m_n)
3910 {
3911         m_n->tu = 64; /* default size */
3912
3913         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3914         m_n->gmch_m = bits_per_pixel * pixel_clock;
3915         m_n->gmch_n = link_clock * nlanes * 8;
3916         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3917
3918         m_n->link_m = pixel_clock;
3919         m_n->link_n = link_clock;
3920         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3921 }
3922
3923 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3924 {
3925         if (i915_panel_use_ssc >= 0)
3926                 return i915_panel_use_ssc != 0;
3927         return dev_priv->lvds_use_ssc
3928                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3929 }
3930
3931 /**
3932  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3933  * @crtc: CRTC structure
3934  * @mode: requested mode
3935  *
3936  * A pipe may be connected to one or more outputs.  Based on the depth of the
3937  * attached framebuffer, choose a good color depth to use on the pipe.
3938  *
3939  * If possible, match the pipe depth to the fb depth.  In some cases, this
3940  * isn't ideal, because the connected output supports a lesser or restricted
3941  * set of depths.  Resolve that here:
3942  *    LVDS typically supports only 6bpc, so clamp down in that case
3943  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3944  *    Displays may support a restricted set as well, check EDID and clamp as
3945  *      appropriate.
3946  *    DP may want to dither down to 6bpc to fit larger modes
3947  *
3948  * RETURNS:
3949  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3950  * true if they don't match).
3951  */
3952 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3953                                          struct drm_framebuffer *fb,
3954                                          unsigned int *pipe_bpp,
3955                                          struct drm_display_mode *mode)
3956 {
3957         struct drm_device *dev = crtc->dev;
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         struct drm_connector *connector;
3960         struct intel_encoder *intel_encoder;
3961         unsigned int display_bpc = UINT_MAX, bpc;
3962
3963         /* Walk the encoders & connectors on this crtc, get min bpc */
3964         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3965
3966                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3967                         unsigned int lvds_bpc;
3968
3969                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3970                             LVDS_A3_POWER_UP)
3971                                 lvds_bpc = 8;
3972                         else
3973                                 lvds_bpc = 6;
3974
3975                         if (lvds_bpc < display_bpc) {
3976                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3977                                 display_bpc = lvds_bpc;
3978                         }
3979                         continue;
3980                 }
3981
3982                 /* Not one of the known troublemakers, check the EDID */
3983                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3984                                     head) {
3985                         if (connector->encoder != &intel_encoder->base)
3986                                 continue;
3987
3988                         /* Don't use an invalid EDID bpc value */
3989                         if (connector->display_info.bpc &&
3990                             connector->display_info.bpc < display_bpc) {
3991                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3992                                 display_bpc = connector->display_info.bpc;
3993                         }
3994                 }
3995
3996                 /*
3997                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3998                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3999                  */
4000                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4001                         if (display_bpc > 8 && display_bpc < 12) {
4002                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4003                                 display_bpc = 12;
4004                         } else {
4005                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4006                                 display_bpc = 8;
4007                         }
4008                 }
4009         }
4010
4011         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4012                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4013                 display_bpc = 6;
4014         }
4015
4016         /*
4017          * We could just drive the pipe at the highest bpc all the time and
4018          * enable dithering as needed, but that costs bandwidth.  So choose
4019          * the minimum value that expresses the full color range of the fb but
4020          * also stays within the max display bpc discovered above.
4021          */
4022
4023         switch (fb->depth) {
4024         case 8:
4025                 bpc = 8; /* since we go through a colormap */
4026                 break;
4027         case 15:
4028         case 16:
4029                 bpc = 6; /* min is 18bpp */
4030                 break;
4031         case 24:
4032                 bpc = 8;
4033                 break;
4034         case 30:
4035                 bpc = 10;
4036                 break;
4037         case 48:
4038                 bpc = 12;
4039                 break;
4040         default:
4041                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4042                 bpc = min((unsigned int)8, display_bpc);
4043                 break;
4044         }
4045
4046         display_bpc = min(display_bpc, bpc);
4047
4048         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4049                       bpc, display_bpc);
4050
4051         *pipe_bpp = display_bpc * 3;
4052
4053         return display_bpc != bpc;
4054 }
4055
4056 static int vlv_get_refclk(struct drm_crtc *crtc)
4057 {
4058         struct drm_device *dev = crtc->dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         int refclk = 27000; /* for DP & HDMI */
4061
4062         return 100000; /* only one validated so far */
4063
4064         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4065                 refclk = 96000;
4066         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4067                 if (intel_panel_use_ssc(dev_priv))
4068                         refclk = 100000;
4069                 else
4070                         refclk = 96000;
4071         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4072                 refclk = 100000;
4073         }
4074
4075         return refclk;
4076 }
4077
4078 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4079 {
4080         struct drm_device *dev = crtc->dev;
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         int refclk;
4083
4084         if (IS_VALLEYVIEW(dev)) {
4085                 refclk = vlv_get_refclk(crtc);
4086         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4087             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4088                 refclk = dev_priv->lvds_ssc_freq * 1000;
4089                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4090                               refclk / 1000);
4091         } else if (!IS_GEN2(dev)) {
4092                 refclk = 96000;
4093         } else {
4094                 refclk = 48000;
4095         }
4096
4097         return refclk;
4098 }
4099
4100 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4101                                       intel_clock_t *clock)
4102 {
4103         /* SDVO TV has fixed PLL values depend on its clock range,
4104            this mirrors vbios setting. */
4105         if (adjusted_mode->clock >= 100000
4106             && adjusted_mode->clock < 140500) {
4107                 clock->p1 = 2;
4108                 clock->p2 = 10;
4109                 clock->n = 3;
4110                 clock->m1 = 16;
4111                 clock->m2 = 8;
4112         } else if (adjusted_mode->clock >= 140500
4113                    && adjusted_mode->clock <= 200000) {
4114                 clock->p1 = 1;
4115                 clock->p2 = 10;
4116                 clock->n = 6;
4117                 clock->m1 = 12;
4118                 clock->m2 = 8;
4119         }
4120 }
4121
4122 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4123                                      intel_clock_t *clock,
4124                                      intel_clock_t *reduced_clock)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         int pipe = intel_crtc->pipe;
4130         u32 fp, fp2 = 0;
4131
4132         if (IS_PINEVIEW(dev)) {
4133                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4134                 if (reduced_clock)
4135                         fp2 = (1 << reduced_clock->n) << 16 |
4136                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4137         } else {
4138                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4139                 if (reduced_clock)
4140                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4141                                 reduced_clock->m2;
4142         }
4143
4144         I915_WRITE(FP0(pipe), fp);
4145
4146         intel_crtc->lowfreq_avail = false;
4147         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4148             reduced_clock && i915_powersave) {
4149                 I915_WRITE(FP1(pipe), fp2);
4150                 intel_crtc->lowfreq_avail = true;
4151         } else {
4152                 I915_WRITE(FP1(pipe), fp);
4153         }
4154 }
4155
4156 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4157                               struct drm_display_mode *adjusted_mode)
4158 {
4159         struct drm_device *dev = crtc->dev;
4160         struct drm_i915_private *dev_priv = dev->dev_private;
4161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4162         int pipe = intel_crtc->pipe;
4163         u32 temp;
4164
4165         temp = I915_READ(LVDS);
4166         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4167         if (pipe == 1) {
4168                 temp |= LVDS_PIPEB_SELECT;
4169         } else {
4170                 temp &= ~LVDS_PIPEB_SELECT;
4171         }
4172         /* set the corresponsding LVDS_BORDER bit */
4173         temp |= dev_priv->lvds_border_bits;
4174         /* Set the B0-B3 data pairs corresponding to whether we're going to
4175          * set the DPLLs for dual-channel mode or not.
4176          */
4177         if (clock->p2 == 7)
4178                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4179         else
4180                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4181
4182         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4183          * appropriately here, but we need to look more thoroughly into how
4184          * panels behave in the two modes.
4185          */
4186         /* set the dithering flag on LVDS as needed */
4187         if (INTEL_INFO(dev)->gen >= 4) {
4188                 if (dev_priv->lvds_dither)
4189                         temp |= LVDS_ENABLE_DITHER;
4190                 else
4191                         temp &= ~LVDS_ENABLE_DITHER;
4192         }
4193         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4194         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4195                 temp |= LVDS_HSYNC_POLARITY;
4196         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4197                 temp |= LVDS_VSYNC_POLARITY;
4198         I915_WRITE(LVDS, temp);
4199 }
4200
4201 static void vlv_update_pll(struct drm_crtc *crtc,
4202                            struct drm_display_mode *mode,
4203                            struct drm_display_mode *adjusted_mode,
4204                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4205                            int num_connectors)
4206 {
4207         struct drm_device *dev = crtc->dev;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210         int pipe = intel_crtc->pipe;
4211         u32 dpll, mdiv, pdiv;
4212         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4213         bool is_sdvo;
4214         u32 temp;
4215
4216         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4217                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4218
4219         dpll = DPLL_VGA_MODE_DIS;
4220         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4221         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4222         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4223
4224         I915_WRITE(DPLL(pipe), dpll);
4225         POSTING_READ(DPLL(pipe));
4226
4227         bestn = clock->n;
4228         bestm1 = clock->m1;
4229         bestm2 = clock->m2;
4230         bestp1 = clock->p1;
4231         bestp2 = clock->p2;
4232
4233         /*
4234          * In Valleyview PLL and program lane counter registers are exposed
4235          * through DPIO interface
4236          */
4237         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4238         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4239         mdiv |= ((bestn << DPIO_N_SHIFT));
4240         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4241         mdiv |= (1 << DPIO_K_SHIFT);
4242         mdiv |= DPIO_ENABLE_CALIBRATION;
4243         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4244
4245         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4246
4247         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4248                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4249                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4250                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4251         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4252
4253         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4254
4255         dpll |= DPLL_VCO_ENABLE;
4256         I915_WRITE(DPLL(pipe), dpll);
4257         POSTING_READ(DPLL(pipe));
4258         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4259                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4260
4261         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4262
4263         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4264                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4265
4266         I915_WRITE(DPLL(pipe), dpll);
4267
4268         /* Wait for the clocks to stabilize. */
4269         POSTING_READ(DPLL(pipe));
4270         udelay(150);
4271
4272         temp = 0;
4273         if (is_sdvo) {
4274                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4275                 if (temp > 1)
4276                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4277                 else
4278                         temp = 0;
4279         }
4280         I915_WRITE(DPLL_MD(pipe), temp);
4281         POSTING_READ(DPLL_MD(pipe));
4282
4283         /* Now program lane control registers */
4284         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4285                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4286         {
4287                 temp = 0x1000C4;
4288                 if(pipe == 1)
4289                         temp |= (1 << 21);
4290                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4291         }
4292         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4293         {
4294                 temp = 0x1000C4;
4295                 if(pipe == 1)
4296                         temp |= (1 << 21);
4297                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4298         }
4299 }
4300
4301 static void i9xx_update_pll(struct drm_crtc *crtc,
4302                             struct drm_display_mode *mode,
4303                             struct drm_display_mode *adjusted_mode,
4304                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4305                             int num_connectors)
4306 {
4307         struct drm_device *dev = crtc->dev;
4308         struct drm_i915_private *dev_priv = dev->dev_private;
4309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4310         int pipe = intel_crtc->pipe;
4311         u32 dpll;
4312         bool is_sdvo;
4313
4314         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4315
4316         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4317                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4318
4319         dpll = DPLL_VGA_MODE_DIS;
4320
4321         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4322                 dpll |= DPLLB_MODE_LVDS;
4323         else
4324                 dpll |= DPLLB_MODE_DAC_SERIAL;
4325         if (is_sdvo) {
4326                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4327                 if (pixel_multiplier > 1) {
4328                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4329                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4330                 }
4331                 dpll |= DPLL_DVO_HIGH_SPEED;
4332         }
4333         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4334                 dpll |= DPLL_DVO_HIGH_SPEED;
4335
4336         /* compute bitmask from p1 value */
4337         if (IS_PINEVIEW(dev))
4338                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4339         else {
4340                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4341                 if (IS_G4X(dev) && reduced_clock)
4342                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4343         }
4344         switch (clock->p2) {
4345         case 5:
4346                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4347                 break;
4348         case 7:
4349                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4350                 break;
4351         case 10:
4352                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4353                 break;
4354         case 14:
4355                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4356                 break;
4357         }
4358         if (INTEL_INFO(dev)->gen >= 4)
4359                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4360
4361         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4362                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4363         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4364                 /* XXX: just matching BIOS for now */
4365                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4366                 dpll |= 3;
4367         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4368                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4369                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4370         else
4371                 dpll |= PLL_REF_INPUT_DREFCLK;
4372
4373         dpll |= DPLL_VCO_ENABLE;
4374         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4375         POSTING_READ(DPLL(pipe));
4376         udelay(150);
4377
4378         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4379          * This is an exception to the general rule that mode_set doesn't turn
4380          * things on.
4381          */
4382         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4383                 intel_update_lvds(crtc, clock, adjusted_mode);
4384
4385         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4386                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4387
4388         I915_WRITE(DPLL(pipe), dpll);
4389
4390         /* Wait for the clocks to stabilize. */
4391         POSTING_READ(DPLL(pipe));
4392         udelay(150);
4393
4394         if (INTEL_INFO(dev)->gen >= 4) {
4395                 u32 temp = 0;
4396                 if (is_sdvo) {
4397                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4398                         if (temp > 1)
4399                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4400                         else
4401                                 temp = 0;
4402                 }
4403                 I915_WRITE(DPLL_MD(pipe), temp);
4404         } else {
4405                 /* The pixel multiplier can only be updated once the
4406                  * DPLL is enabled and the clocks are stable.
4407                  *
4408                  * So write it again.
4409                  */
4410                 I915_WRITE(DPLL(pipe), dpll);
4411         }
4412 }
4413
4414 static void i8xx_update_pll(struct drm_crtc *crtc,
4415                             struct drm_display_mode *adjusted_mode,
4416                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4417                             int num_connectors)
4418 {
4419         struct drm_device *dev = crtc->dev;
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4422         int pipe = intel_crtc->pipe;
4423         u32 dpll;
4424
4425         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4426
4427         dpll = DPLL_VGA_MODE_DIS;
4428
4429         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4430                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4431         } else {
4432                 if (clock->p1 == 2)
4433                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4434                 else
4435                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4436                 if (clock->p2 == 4)
4437                         dpll |= PLL_P2_DIVIDE_BY_4;
4438         }
4439
4440         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4441                 /* XXX: just matching BIOS for now */
4442                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4443                 dpll |= 3;
4444         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4445                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4446                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4447         else
4448                 dpll |= PLL_REF_INPUT_DREFCLK;
4449
4450         dpll |= DPLL_VCO_ENABLE;
4451         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4452         POSTING_READ(DPLL(pipe));
4453         udelay(150);
4454
4455         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4456          * This is an exception to the general rule that mode_set doesn't turn
4457          * things on.
4458          */
4459         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4460                 intel_update_lvds(crtc, clock, adjusted_mode);
4461
4462         I915_WRITE(DPLL(pipe), dpll);
4463
4464         /* Wait for the clocks to stabilize. */
4465         POSTING_READ(DPLL(pipe));
4466         udelay(150);
4467
4468         /* The pixel multiplier can only be updated once the
4469          * DPLL is enabled and the clocks are stable.
4470          *
4471          * So write it again.
4472          */
4473         I915_WRITE(DPLL(pipe), dpll);
4474 }
4475
4476 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4477                                    struct drm_display_mode *mode,
4478                                    struct drm_display_mode *adjusted_mode)
4479 {
4480         struct drm_device *dev = intel_crtc->base.dev;
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482         enum pipe pipe = intel_crtc->pipe;
4483         uint32_t vsyncshift;
4484
4485         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4486                 /* the chip adds 2 halflines automatically */
4487                 adjusted_mode->crtc_vtotal -= 1;
4488                 adjusted_mode->crtc_vblank_end -= 1;
4489                 vsyncshift = adjusted_mode->crtc_hsync_start
4490                              - adjusted_mode->crtc_htotal / 2;
4491         } else {
4492                 vsyncshift = 0;
4493         }
4494
4495         if (INTEL_INFO(dev)->gen > 3)
4496                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4497
4498         I915_WRITE(HTOTAL(pipe),
4499                    (adjusted_mode->crtc_hdisplay - 1) |
4500                    ((adjusted_mode->crtc_htotal - 1) << 16));
4501         I915_WRITE(HBLANK(pipe),
4502                    (adjusted_mode->crtc_hblank_start - 1) |
4503                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4504         I915_WRITE(HSYNC(pipe),
4505                    (adjusted_mode->crtc_hsync_start - 1) |
4506                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4507
4508         I915_WRITE(VTOTAL(pipe),
4509                    (adjusted_mode->crtc_vdisplay - 1) |
4510                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4511         I915_WRITE(VBLANK(pipe),
4512                    (adjusted_mode->crtc_vblank_start - 1) |
4513                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4514         I915_WRITE(VSYNC(pipe),
4515                    (adjusted_mode->crtc_vsync_start - 1) |
4516                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4517
4518         /* pipesrc controls the size that is scaled from, which should
4519          * always be the user's requested size.
4520          */
4521         I915_WRITE(PIPESRC(pipe),
4522                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4523 }
4524
4525 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4526                               struct drm_display_mode *mode,
4527                               struct drm_display_mode *adjusted_mode,
4528                               int x, int y,
4529                               struct drm_framebuffer *fb)
4530 {
4531         struct drm_device *dev = crtc->dev;
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4534         int pipe = intel_crtc->pipe;
4535         int plane = intel_crtc->plane;
4536         int refclk, num_connectors = 0;
4537         intel_clock_t clock, reduced_clock;
4538         u32 dspcntr, pipeconf;
4539         bool ok, has_reduced_clock = false, is_sdvo = false;
4540         bool is_lvds = false, is_tv = false, is_dp = false;
4541         struct intel_encoder *encoder;
4542         const intel_limit_t *limit;
4543         int ret;
4544
4545         for_each_encoder_on_crtc(dev, crtc, encoder) {
4546                 switch (encoder->type) {
4547                 case INTEL_OUTPUT_LVDS:
4548                         is_lvds = true;
4549                         break;
4550                 case INTEL_OUTPUT_SDVO:
4551                 case INTEL_OUTPUT_HDMI:
4552                         is_sdvo = true;
4553                         if (encoder->needs_tv_clock)
4554                                 is_tv = true;
4555                         break;
4556                 case INTEL_OUTPUT_TVOUT:
4557                         is_tv = true;
4558                         break;
4559                 case INTEL_OUTPUT_DISPLAYPORT:
4560                         is_dp = true;
4561                         break;
4562                 }
4563
4564                 num_connectors++;
4565         }
4566
4567         refclk = i9xx_get_refclk(crtc, num_connectors);
4568
4569         /*
4570          * Returns a set of divisors for the desired target clock with the given
4571          * refclk, or FALSE.  The returned values represent the clock equation:
4572          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4573          */
4574         limit = intel_limit(crtc, refclk);
4575         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4576                              &clock);
4577         if (!ok) {
4578                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4579                 return -EINVAL;
4580         }
4581
4582         /* Ensure that the cursor is valid for the new mode before changing... */
4583         intel_crtc_update_cursor(crtc, true);
4584
4585         if (is_lvds && dev_priv->lvds_downclock_avail) {
4586                 /*
4587                  * Ensure we match the reduced clock's P to the target clock.
4588                  * If the clocks don't match, we can't switch the display clock
4589                  * by using the FP0/FP1. In such case we will disable the LVDS
4590                  * downclock feature.
4591                 */
4592                 has_reduced_clock = limit->find_pll(limit, crtc,
4593                                                     dev_priv->lvds_downclock,
4594                                                     refclk,
4595                                                     &clock,
4596                                                     &reduced_clock);
4597         }
4598
4599         if (is_sdvo && is_tv)
4600                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4601
4602         if (IS_GEN2(dev))
4603                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4604                                 has_reduced_clock ? &reduced_clock : NULL,
4605                                 num_connectors);
4606         else if (IS_VALLEYVIEW(dev))
4607                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4608                                 has_reduced_clock ? &reduced_clock : NULL,
4609                                 num_connectors);
4610         else
4611                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4612                                 has_reduced_clock ? &reduced_clock : NULL,
4613                                 num_connectors);
4614
4615         /* setup pipeconf */
4616         pipeconf = I915_READ(PIPECONF(pipe));
4617
4618         /* Set up the display plane register */
4619         dspcntr = DISPPLANE_GAMMA_ENABLE;
4620
4621         if (pipe == 0)
4622                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4623         else
4624                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4625
4626         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4627                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4628                  * core speed.
4629                  *
4630                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4631                  * pipe == 0 check?
4632                  */
4633                 if (mode->clock >
4634                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4635                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4636                 else
4637                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4638         }
4639
4640         /* default to 8bpc */
4641         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4642         if (is_dp) {
4643                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4644                         pipeconf |= PIPECONF_BPP_6 |
4645                                     PIPECONF_DITHER_EN |
4646                                     PIPECONF_DITHER_TYPE_SP;
4647                 }
4648         }
4649
4650         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4651                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4652                         pipeconf |= PIPECONF_BPP_6 |
4653                                         PIPECONF_ENABLE |
4654                                         I965_PIPECONF_ACTIVE;
4655                 }
4656         }
4657
4658         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4659         drm_mode_debug_printmodeline(mode);
4660
4661         if (HAS_PIPE_CXSR(dev)) {
4662                 if (intel_crtc->lowfreq_avail) {
4663                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4664                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4665                 } else {
4666                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4667                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4668                 }
4669         }
4670
4671         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4672         if (!IS_GEN2(dev) &&
4673             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4674                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4675         else
4676                 pipeconf |= PIPECONF_PROGRESSIVE;
4677
4678         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4679
4680         /* pipesrc and dspsize control the size that is scaled from,
4681          * which should always be the user's requested size.
4682          */
4683         I915_WRITE(DSPSIZE(plane),
4684                    ((mode->vdisplay - 1) << 16) |
4685                    (mode->hdisplay - 1));
4686         I915_WRITE(DSPPOS(plane), 0);
4687
4688         I915_WRITE(PIPECONF(pipe), pipeconf);
4689         POSTING_READ(PIPECONF(pipe));
4690         intel_enable_pipe(dev_priv, pipe, false);
4691
4692         intel_wait_for_vblank(dev, pipe);
4693
4694         I915_WRITE(DSPCNTR(plane), dspcntr);
4695         POSTING_READ(DSPCNTR(plane));
4696
4697         ret = intel_pipe_set_base(crtc, x, y, fb);
4698
4699         intel_update_watermarks(dev);
4700
4701         return ret;
4702 }
4703
4704 /*
4705  * Initialize reference clocks when the driver loads
4706  */
4707 void ironlake_init_pch_refclk(struct drm_device *dev)
4708 {
4709         struct drm_i915_private *dev_priv = dev->dev_private;
4710         struct drm_mode_config *mode_config = &dev->mode_config;
4711         struct intel_encoder *encoder;
4712         u32 temp;
4713         bool has_lvds = false;
4714         bool has_cpu_edp = false;
4715         bool has_pch_edp = false;
4716         bool has_panel = false;
4717         bool has_ck505 = false;
4718         bool can_ssc = false;
4719
4720         /* We need to take the global config into account */
4721         list_for_each_entry(encoder, &mode_config->encoder_list,
4722                             base.head) {
4723                 switch (encoder->type) {
4724                 case INTEL_OUTPUT_LVDS:
4725                         has_panel = true;
4726                         has_lvds = true;
4727                         break;
4728                 case INTEL_OUTPUT_EDP:
4729                         has_panel = true;
4730                         if (intel_encoder_is_pch_edp(&encoder->base))
4731                                 has_pch_edp = true;
4732                         else
4733                                 has_cpu_edp = true;
4734                         break;
4735                 }
4736         }
4737
4738         if (HAS_PCH_IBX(dev)) {
4739                 has_ck505 = dev_priv->display_clock_mode;
4740                 can_ssc = has_ck505;
4741         } else {
4742                 has_ck505 = false;
4743                 can_ssc = true;
4744         }
4745
4746         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4747                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4748                       has_ck505);
4749
4750         /* Ironlake: try to setup display ref clock before DPLL
4751          * enabling. This is only under driver's control after
4752          * PCH B stepping, previous chipset stepping should be
4753          * ignoring this setting.
4754          */
4755         temp = I915_READ(PCH_DREF_CONTROL);
4756         /* Always enable nonspread source */
4757         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4758
4759         if (has_ck505)
4760                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4761         else
4762                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4763
4764         if (has_panel) {
4765                 temp &= ~DREF_SSC_SOURCE_MASK;
4766                 temp |= DREF_SSC_SOURCE_ENABLE;
4767
4768                 /* SSC must be turned on before enabling the CPU output  */
4769                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4770                         DRM_DEBUG_KMS("Using SSC on panel\n");
4771                         temp |= DREF_SSC1_ENABLE;
4772                 } else
4773                         temp &= ~DREF_SSC1_ENABLE;
4774
4775                 /* Get SSC going before enabling the outputs */
4776                 I915_WRITE(PCH_DREF_CONTROL, temp);
4777                 POSTING_READ(PCH_DREF_CONTROL);
4778                 udelay(200);
4779
4780                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4781
4782                 /* Enable CPU source on CPU attached eDP */
4783                 if (has_cpu_edp) {
4784                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4785                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4786                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4787                         }
4788                         else
4789                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4790                 } else
4791                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4792
4793                 I915_WRITE(PCH_DREF_CONTROL, temp);
4794                 POSTING_READ(PCH_DREF_CONTROL);
4795                 udelay(200);
4796         } else {
4797                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4798
4799                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4800
4801                 /* Turn off CPU output */
4802                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4803
4804                 I915_WRITE(PCH_DREF_CONTROL, temp);
4805                 POSTING_READ(PCH_DREF_CONTROL);
4806                 udelay(200);
4807
4808                 /* Turn off the SSC source */
4809                 temp &= ~DREF_SSC_SOURCE_MASK;
4810                 temp |= DREF_SSC_SOURCE_DISABLE;
4811
4812                 /* Turn off SSC1 */
4813                 temp &= ~ DREF_SSC1_ENABLE;
4814
4815                 I915_WRITE(PCH_DREF_CONTROL, temp);
4816                 POSTING_READ(PCH_DREF_CONTROL);
4817                 udelay(200);
4818         }
4819 }
4820
4821 static int ironlake_get_refclk(struct drm_crtc *crtc)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         struct intel_encoder *encoder;
4826         struct intel_encoder *edp_encoder = NULL;
4827         int num_connectors = 0;
4828         bool is_lvds = false;
4829
4830         for_each_encoder_on_crtc(dev, crtc, encoder) {
4831                 switch (encoder->type) {
4832                 case INTEL_OUTPUT_LVDS:
4833                         is_lvds = true;
4834                         break;
4835                 case INTEL_OUTPUT_EDP:
4836                         edp_encoder = encoder;
4837                         break;
4838                 }
4839                 num_connectors++;
4840         }
4841
4842         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4843                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4844                               dev_priv->lvds_ssc_freq);
4845                 return dev_priv->lvds_ssc_freq * 1000;
4846         }
4847
4848         return 120000;
4849 }
4850
4851 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4852                                   struct drm_display_mode *adjusted_mode,
4853                                   bool dither)
4854 {
4855         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4857         int pipe = intel_crtc->pipe;
4858         uint32_t val;
4859
4860         val = I915_READ(PIPECONF(pipe));
4861
4862         val &= ~PIPE_BPC_MASK;
4863         switch (intel_crtc->bpp) {
4864         case 18:
4865                 val |= PIPE_6BPC;
4866                 break;
4867         case 24:
4868                 val |= PIPE_8BPC;
4869                 break;
4870         case 30:
4871                 val |= PIPE_10BPC;
4872                 break;
4873         case 36:
4874                 val |= PIPE_12BPC;
4875                 break;
4876         default:
4877                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4878                 BUG();
4879         }
4880
4881         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4882         if (dither)
4883                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4884
4885         val &= ~PIPECONF_INTERLACE_MASK;
4886         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4887                 val |= PIPECONF_INTERLACED_ILK;
4888         else
4889                 val |= PIPECONF_PROGRESSIVE;
4890
4891         I915_WRITE(PIPECONF(pipe), val);
4892         POSTING_READ(PIPECONF(pipe));
4893 }
4894
4895 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4896                                  struct drm_display_mode *adjusted_mode,
4897                                  bool dither)
4898 {
4899         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4901         int pipe = intel_crtc->pipe;
4902         uint32_t val;
4903
4904         val = I915_READ(PIPECONF(pipe));
4905
4906         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4907         if (dither)
4908                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4909
4910         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4911         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4912                 val |= PIPECONF_INTERLACED_ILK;
4913         else
4914                 val |= PIPECONF_PROGRESSIVE;
4915
4916         I915_WRITE(PIPECONF(pipe), val);
4917         POSTING_READ(PIPECONF(pipe));
4918 }
4919
4920 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4921                                     struct drm_display_mode *adjusted_mode,
4922                                     intel_clock_t *clock,
4923                                     bool *has_reduced_clock,
4924                                     intel_clock_t *reduced_clock)
4925 {
4926         struct drm_device *dev = crtc->dev;
4927         struct drm_i915_private *dev_priv = dev->dev_private;
4928         struct intel_encoder *intel_encoder;
4929         int refclk;
4930         const intel_limit_t *limit;
4931         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4932
4933         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4934                 switch (intel_encoder->type) {
4935                 case INTEL_OUTPUT_LVDS:
4936                         is_lvds = true;
4937                         break;
4938                 case INTEL_OUTPUT_SDVO:
4939                 case INTEL_OUTPUT_HDMI:
4940                         is_sdvo = true;
4941                         if (intel_encoder->needs_tv_clock)
4942                                 is_tv = true;
4943                         break;
4944                 case INTEL_OUTPUT_TVOUT:
4945                         is_tv = true;
4946                         break;
4947                 }
4948         }
4949
4950         refclk = ironlake_get_refclk(crtc);
4951
4952         /*
4953          * Returns a set of divisors for the desired target clock with the given
4954          * refclk, or FALSE.  The returned values represent the clock equation:
4955          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4956          */
4957         limit = intel_limit(crtc, refclk);
4958         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4959                               clock);
4960         if (!ret)
4961                 return false;
4962
4963         if (is_lvds && dev_priv->lvds_downclock_avail) {
4964                 /*
4965                  * Ensure we match the reduced clock's P to the target clock.
4966                  * If the clocks don't match, we can't switch the display clock
4967                  * by using the FP0/FP1. In such case we will disable the LVDS
4968                  * downclock feature.
4969                 */
4970                 *has_reduced_clock = limit->find_pll(limit, crtc,
4971                                                      dev_priv->lvds_downclock,
4972                                                      refclk,
4973                                                      clock,
4974                                                      reduced_clock);
4975         }
4976
4977         if (is_sdvo && is_tv)
4978                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4979
4980         return true;
4981 }
4982
4983 static void ironlake_set_m_n(struct drm_crtc *crtc,
4984                              struct drm_display_mode *mode,
4985                              struct drm_display_mode *adjusted_mode)
4986 {
4987         struct drm_device *dev = crtc->dev;
4988         struct drm_i915_private *dev_priv = dev->dev_private;
4989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4990         enum pipe pipe = intel_crtc->pipe;
4991         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4992         struct fdi_m_n m_n = {0};
4993         int target_clock, pixel_multiplier, lane, link_bw;
4994         bool is_dp = false, is_cpu_edp = false;
4995
4996         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4997                 switch (intel_encoder->type) {
4998                 case INTEL_OUTPUT_DISPLAYPORT:
4999                         is_dp = true;
5000                         break;
5001                 case INTEL_OUTPUT_EDP:
5002                         is_dp = true;
5003                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5004                                 is_cpu_edp = true;
5005                         edp_encoder = intel_encoder;
5006                         break;
5007                 }
5008         }
5009
5010         /* FDI link */
5011         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5012         lane = 0;
5013         /* CPU eDP doesn't require FDI link, so just set DP M/N
5014            according to current link config */
5015         if (is_cpu_edp) {
5016                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5017         } else {
5018                 /* FDI is a binary signal running at ~2.7GHz, encoding
5019                  * each output octet as 10 bits. The actual frequency
5020                  * is stored as a divider into a 100MHz clock, and the
5021                  * mode pixel clock is stored in units of 1KHz.
5022                  * Hence the bw of each lane in terms of the mode signal
5023                  * is:
5024                  */
5025                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5026         }
5027
5028         /* [e]DP over FDI requires target mode clock instead of link clock. */
5029         if (edp_encoder)
5030                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5031         else if (is_dp)
5032                 target_clock = mode->clock;
5033         else
5034                 target_clock = adjusted_mode->clock;
5035
5036         if (!lane) {
5037                 /*
5038                  * Account for spread spectrum to avoid
5039                  * oversubscribing the link. Max center spread
5040                  * is 2.5%; use 5% for safety's sake.
5041                  */
5042                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5043                 lane = bps / (link_bw * 8) + 1;
5044         }
5045
5046         intel_crtc->fdi_lanes = lane;
5047
5048         if (pixel_multiplier > 1)
5049                 link_bw *= pixel_multiplier;
5050         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5051                              &m_n);
5052
5053         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5054         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5055         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5056         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5057 }
5058
5059 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5060                                       struct drm_display_mode *adjusted_mode,
5061                                       intel_clock_t *clock, u32 fp)
5062 {
5063         struct drm_crtc *crtc = &intel_crtc->base;
5064         struct drm_device *dev = crtc->dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066         struct intel_encoder *intel_encoder;
5067         uint32_t dpll;
5068         int factor, pixel_multiplier, num_connectors = 0;
5069         bool is_lvds = false, is_sdvo = false, is_tv = false;
5070         bool is_dp = false, is_cpu_edp = false;
5071
5072         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5073                 switch (intel_encoder->type) {
5074                 case INTEL_OUTPUT_LVDS:
5075                         is_lvds = true;
5076                         break;
5077                 case INTEL_OUTPUT_SDVO:
5078                 case INTEL_OUTPUT_HDMI:
5079                         is_sdvo = true;
5080                         if (intel_encoder->needs_tv_clock)
5081                                 is_tv = true;
5082                         break;
5083                 case INTEL_OUTPUT_TVOUT:
5084                         is_tv = true;
5085                         break;
5086                 case INTEL_OUTPUT_DISPLAYPORT:
5087                         is_dp = true;
5088                         break;
5089                 case INTEL_OUTPUT_EDP:
5090                         is_dp = true;
5091                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5092                                 is_cpu_edp = true;
5093                         break;
5094                 }
5095
5096                 num_connectors++;
5097         }
5098
5099         /* Enable autotuning of the PLL clock (if permissible) */
5100         factor = 21;
5101         if (is_lvds) {
5102                 if ((intel_panel_use_ssc(dev_priv) &&
5103                      dev_priv->lvds_ssc_freq == 100) ||
5104                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5105                         factor = 25;
5106         } else if (is_sdvo && is_tv)
5107                 factor = 20;
5108
5109         if (clock->m < factor * clock->n)
5110                 fp |= FP_CB_TUNE;
5111
5112         dpll = 0;
5113
5114         if (is_lvds)
5115                 dpll |= DPLLB_MODE_LVDS;
5116         else
5117                 dpll |= DPLLB_MODE_DAC_SERIAL;
5118         if (is_sdvo) {
5119                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5120                 if (pixel_multiplier > 1) {
5121                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5122                 }
5123                 dpll |= DPLL_DVO_HIGH_SPEED;
5124         }
5125         if (is_dp && !is_cpu_edp)
5126                 dpll |= DPLL_DVO_HIGH_SPEED;
5127
5128         /* compute bitmask from p1 value */
5129         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5130         /* also FPA1 */
5131         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5132
5133         switch (clock->p2) {
5134         case 5:
5135                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5136                 break;
5137         case 7:
5138                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5139                 break;
5140         case 10:
5141                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5142                 break;
5143         case 14:
5144                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5145                 break;
5146         }
5147
5148         if (is_sdvo && is_tv)
5149                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5150         else if (is_tv)
5151                 /* XXX: just matching BIOS for now */
5152                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5153                 dpll |= 3;
5154         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5155                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5156         else
5157                 dpll |= PLL_REF_INPUT_DREFCLK;
5158
5159         return dpll;
5160 }
5161
5162 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5163                                   struct drm_display_mode *mode,
5164                                   struct drm_display_mode *adjusted_mode,
5165                                   int x, int y,
5166                                   struct drm_framebuffer *fb)
5167 {
5168         struct drm_device *dev = crtc->dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5171         int pipe = intel_crtc->pipe;
5172         int plane = intel_crtc->plane;
5173         int num_connectors = 0;
5174         intel_clock_t clock, reduced_clock;
5175         u32 dpll, fp = 0, fp2 = 0;
5176         bool ok, has_reduced_clock = false;
5177         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5178         struct intel_encoder *encoder;
5179         u32 temp;
5180         int ret;
5181         bool dither;
5182
5183         for_each_encoder_on_crtc(dev, crtc, encoder) {
5184                 switch (encoder->type) {
5185                 case INTEL_OUTPUT_LVDS:
5186                         is_lvds = true;
5187                         break;
5188                 case INTEL_OUTPUT_DISPLAYPORT:
5189                         is_dp = true;
5190                         break;
5191                 case INTEL_OUTPUT_EDP:
5192                         is_dp = true;
5193                         if (!intel_encoder_is_pch_edp(&encoder->base))
5194                                 is_cpu_edp = true;
5195                         break;
5196                 }
5197
5198                 num_connectors++;
5199         }
5200
5201         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5202              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5203
5204         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5205                                      &has_reduced_clock, &reduced_clock);
5206         if (!ok) {
5207                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5208                 return -EINVAL;
5209         }
5210
5211         /* Ensure that the cursor is valid for the new mode before changing... */
5212         intel_crtc_update_cursor(crtc, true);
5213
5214         /* determine panel color depth */
5215         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5216         if (is_lvds && dev_priv->lvds_dither)
5217                 dither = true;
5218
5219         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5220         if (has_reduced_clock)
5221                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5222                         reduced_clock.m2;
5223
5224         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5225
5226         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5227         drm_mode_debug_printmodeline(mode);
5228
5229         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5230         if (!is_cpu_edp) {
5231                 struct intel_pch_pll *pll;
5232
5233                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5234                 if (pll == NULL) {
5235                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5236                                          pipe);
5237                         return -EINVAL;
5238                 }
5239         } else
5240                 intel_put_pch_pll(intel_crtc);
5241
5242         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5243          * This is an exception to the general rule that mode_set doesn't turn
5244          * things on.
5245          */
5246         if (is_lvds) {
5247                 temp = I915_READ(PCH_LVDS);
5248                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5249                 if (HAS_PCH_CPT(dev)) {
5250                         temp &= ~PORT_TRANS_SEL_MASK;
5251                         temp |= PORT_TRANS_SEL_CPT(pipe);
5252                 } else {
5253                         if (pipe == 1)
5254                                 temp |= LVDS_PIPEB_SELECT;
5255                         else
5256                                 temp &= ~LVDS_PIPEB_SELECT;
5257                 }
5258
5259                 /* set the corresponsding LVDS_BORDER bit */
5260                 temp |= dev_priv->lvds_border_bits;
5261                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5262                  * set the DPLLs for dual-channel mode or not.
5263                  */
5264                 if (clock.p2 == 7)
5265                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5266                 else
5267                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5268
5269                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5270                  * appropriately here, but we need to look more thoroughly into how
5271                  * panels behave in the two modes.
5272                  */
5273                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5274                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5275                         temp |= LVDS_HSYNC_POLARITY;
5276                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5277                         temp |= LVDS_VSYNC_POLARITY;
5278                 I915_WRITE(PCH_LVDS, temp);
5279         }
5280
5281         if (is_dp && !is_cpu_edp) {
5282                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5283         } else {
5284                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5285                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5286                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5287                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5288                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5289         }
5290
5291         if (intel_crtc->pch_pll) {
5292                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5293
5294                 /* Wait for the clocks to stabilize. */
5295                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5296                 udelay(150);
5297
5298                 /* The pixel multiplier can only be updated once the
5299                  * DPLL is enabled and the clocks are stable.
5300                  *
5301                  * So write it again.
5302                  */
5303                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5304         }
5305
5306         intel_crtc->lowfreq_avail = false;
5307         if (intel_crtc->pch_pll) {
5308                 if (is_lvds && has_reduced_clock && i915_powersave) {
5309                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5310                         intel_crtc->lowfreq_avail = true;
5311                 } else {
5312                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5313                 }
5314         }
5315
5316         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5317
5318         ironlake_set_m_n(crtc, mode, adjusted_mode);
5319
5320         if (is_cpu_edp)
5321                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5322
5323         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5324
5325         intel_wait_for_vblank(dev, pipe);
5326
5327         /* Set up the display plane register */
5328         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5329         POSTING_READ(DSPCNTR(plane));
5330
5331         ret = intel_pipe_set_base(crtc, x, y, fb);
5332
5333         intel_update_watermarks(dev);
5334
5335         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5336
5337         return ret;
5338 }
5339
5340 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5341                                  struct drm_display_mode *mode,
5342                                  struct drm_display_mode *adjusted_mode,
5343                                  int x, int y,
5344                                  struct drm_framebuffer *fb)
5345 {
5346         struct drm_device *dev = crtc->dev;
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5349         int pipe = intel_crtc->pipe;
5350         int plane = intel_crtc->plane;
5351         int num_connectors = 0;
5352         intel_clock_t clock, reduced_clock;
5353         u32 dpll = 0, fp = 0, fp2 = 0;
5354         bool ok, has_reduced_clock = false;
5355         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5356         struct intel_encoder *encoder;
5357         u32 temp;
5358         int ret;
5359         bool dither;
5360
5361         for_each_encoder_on_crtc(dev, crtc, encoder) {
5362                 switch (encoder->type) {
5363                 case INTEL_OUTPUT_LVDS:
5364                         is_lvds = true;
5365                         break;
5366                 case INTEL_OUTPUT_DISPLAYPORT:
5367                         is_dp = true;
5368                         break;
5369                 case INTEL_OUTPUT_EDP:
5370                         is_dp = true;
5371                         if (!intel_encoder_is_pch_edp(&encoder->base))
5372                                 is_cpu_edp = true;
5373                         break;
5374                 }
5375
5376                 num_connectors++;
5377         }
5378
5379         if (is_cpu_edp)
5380                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5381         else
5382                 intel_crtc->cpu_transcoder = pipe;
5383
5384         /* We are not sure yet this won't happen. */
5385         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5386              INTEL_PCH_TYPE(dev));
5387
5388         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5389              num_connectors, pipe_name(pipe));
5390
5391         WARN_ON(I915_READ(PIPECONF(pipe)) &
5392                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5393
5394         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5395
5396         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5397                 return -EINVAL;
5398
5399         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5400                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5401                                              &has_reduced_clock,
5402                                              &reduced_clock);
5403                 if (!ok) {
5404                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5405                         return -EINVAL;
5406                 }
5407         }
5408
5409         /* Ensure that the cursor is valid for the new mode before changing... */
5410         intel_crtc_update_cursor(crtc, true);
5411
5412         /* determine panel color depth */
5413         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5414         if (is_lvds && dev_priv->lvds_dither)
5415                 dither = true;
5416
5417         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5418         drm_mode_debug_printmodeline(mode);
5419
5420         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5421                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5422                 if (has_reduced_clock)
5423                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5424                               reduced_clock.m2;
5425
5426                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5427                                              fp);
5428
5429                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5430                  * own on pre-Haswell/LPT generation */
5431                 if (!is_cpu_edp) {
5432                         struct intel_pch_pll *pll;
5433
5434                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5435                         if (pll == NULL) {
5436                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5437                                                  pipe);
5438                                 return -EINVAL;
5439                         }
5440                 } else
5441                         intel_put_pch_pll(intel_crtc);
5442
5443                 /* The LVDS pin pair needs to be on before the DPLLs are
5444                  * enabled.  This is an exception to the general rule that
5445                  * mode_set doesn't turn things on.
5446                  */
5447                 if (is_lvds) {
5448                         temp = I915_READ(PCH_LVDS);
5449                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5450                         if (HAS_PCH_CPT(dev)) {
5451                                 temp &= ~PORT_TRANS_SEL_MASK;
5452                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5453                         } else {
5454                                 if (pipe == 1)
5455                                         temp |= LVDS_PIPEB_SELECT;
5456                                 else
5457                                         temp &= ~LVDS_PIPEB_SELECT;
5458                         }
5459
5460                         /* set the corresponsding LVDS_BORDER bit */
5461                         temp |= dev_priv->lvds_border_bits;
5462                         /* Set the B0-B3 data pairs corresponding to whether
5463                          * we're going to set the DPLLs for dual-channel mode or
5464                          * not.
5465                          */
5466                         if (clock.p2 == 7)
5467                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5468                         else
5469                                 temp &= ~(LVDS_B0B3_POWER_UP |
5470                                           LVDS_CLKB_POWER_UP);
5471
5472                         /* It would be nice to set 24 vs 18-bit mode
5473                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5474                          * look more thoroughly into how panels behave in the
5475                          * two modes.
5476                          */
5477                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5478                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5479                                 temp |= LVDS_HSYNC_POLARITY;
5480                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5481                                 temp |= LVDS_VSYNC_POLARITY;
5482                         I915_WRITE(PCH_LVDS, temp);
5483                 }
5484         }
5485
5486         if (is_dp && !is_cpu_edp) {
5487                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5488         } else {
5489                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5490                         /* For non-DP output, clear any trans DP clock recovery
5491                          * setting.*/
5492                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5493                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5494                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5495                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5496                 }
5497         }
5498
5499         intel_crtc->lowfreq_avail = false;
5500         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5501                 if (intel_crtc->pch_pll) {
5502                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5503
5504                         /* Wait for the clocks to stabilize. */
5505                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5506                         udelay(150);
5507
5508                         /* The pixel multiplier can only be updated once the
5509                          * DPLL is enabled and the clocks are stable.
5510                          *
5511                          * So write it again.
5512                          */
5513                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5514                 }
5515
5516                 if (intel_crtc->pch_pll) {
5517                         if (is_lvds && has_reduced_clock && i915_powersave) {
5518                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5519                                 intel_crtc->lowfreq_avail = true;
5520                         } else {
5521                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5522                         }
5523                 }
5524         }
5525
5526         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5527
5528         if (!is_dp || is_cpu_edp)
5529                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5530
5531         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5532                 if (is_cpu_edp)
5533                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5534
5535         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5536
5537         /* Set up the display plane register */
5538         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5539         POSTING_READ(DSPCNTR(plane));
5540
5541         ret = intel_pipe_set_base(crtc, x, y, fb);
5542
5543         intel_update_watermarks(dev);
5544
5545         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5546
5547         return ret;
5548 }
5549
5550 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5551                                struct drm_display_mode *mode,
5552                                struct drm_display_mode *adjusted_mode,
5553                                int x, int y,
5554                                struct drm_framebuffer *fb)
5555 {
5556         struct drm_device *dev = crtc->dev;
5557         struct drm_i915_private *dev_priv = dev->dev_private;
5558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5559         int pipe = intel_crtc->pipe;
5560         int ret;
5561
5562         drm_vblank_pre_modeset(dev, pipe);
5563
5564         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5565                                               x, y, fb);
5566         drm_vblank_post_modeset(dev, pipe);
5567
5568         return ret;
5569 }
5570
5571 static bool intel_eld_uptodate(struct drm_connector *connector,
5572                                int reg_eldv, uint32_t bits_eldv,
5573                                int reg_elda, uint32_t bits_elda,
5574                                int reg_edid)
5575 {
5576         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5577         uint8_t *eld = connector->eld;
5578         uint32_t i;
5579
5580         i = I915_READ(reg_eldv);
5581         i &= bits_eldv;
5582
5583         if (!eld[0])
5584                 return !i;
5585
5586         if (!i)
5587                 return false;
5588
5589         i = I915_READ(reg_elda);
5590         i &= ~bits_elda;
5591         I915_WRITE(reg_elda, i);
5592
5593         for (i = 0; i < eld[2]; i++)
5594                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5595                         return false;
5596
5597         return true;
5598 }
5599
5600 static void g4x_write_eld(struct drm_connector *connector,
5601                           struct drm_crtc *crtc)
5602 {
5603         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5604         uint8_t *eld = connector->eld;
5605         uint32_t eldv;
5606         uint32_t len;
5607         uint32_t i;
5608
5609         i = I915_READ(G4X_AUD_VID_DID);
5610
5611         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5612                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5613         else
5614                 eldv = G4X_ELDV_DEVCTG;
5615
5616         if (intel_eld_uptodate(connector,
5617                                G4X_AUD_CNTL_ST, eldv,
5618                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5619                                G4X_HDMIW_HDMIEDID))
5620                 return;
5621
5622         i = I915_READ(G4X_AUD_CNTL_ST);
5623         i &= ~(eldv | G4X_ELD_ADDR);
5624         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5625         I915_WRITE(G4X_AUD_CNTL_ST, i);
5626
5627         if (!eld[0])
5628                 return;
5629
5630         len = min_t(uint8_t, eld[2], len);
5631         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5632         for (i = 0; i < len; i++)
5633                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5634
5635         i = I915_READ(G4X_AUD_CNTL_ST);
5636         i |= eldv;
5637         I915_WRITE(G4X_AUD_CNTL_ST, i);
5638 }
5639
5640 static void haswell_write_eld(struct drm_connector *connector,
5641                                      struct drm_crtc *crtc)
5642 {
5643         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5644         uint8_t *eld = connector->eld;
5645         struct drm_device *dev = crtc->dev;
5646         uint32_t eldv;
5647         uint32_t i;
5648         int len;
5649         int pipe = to_intel_crtc(crtc)->pipe;
5650         int tmp;
5651
5652         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5653         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5654         int aud_config = HSW_AUD_CFG(pipe);
5655         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5656
5657
5658         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5659
5660         /* Audio output enable */
5661         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5662         tmp = I915_READ(aud_cntrl_st2);
5663         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5664         I915_WRITE(aud_cntrl_st2, tmp);
5665
5666         /* Wait for 1 vertical blank */
5667         intel_wait_for_vblank(dev, pipe);
5668
5669         /* Set ELD valid state */
5670         tmp = I915_READ(aud_cntrl_st2);
5671         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5672         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5673         I915_WRITE(aud_cntrl_st2, tmp);
5674         tmp = I915_READ(aud_cntrl_st2);
5675         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5676
5677         /* Enable HDMI mode */
5678         tmp = I915_READ(aud_config);
5679         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5680         /* clear N_programing_enable and N_value_index */
5681         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5682         I915_WRITE(aud_config, tmp);
5683
5684         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5685
5686         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5687
5688         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5689                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5690                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5691                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5692         } else
5693                 I915_WRITE(aud_config, 0);
5694
5695         if (intel_eld_uptodate(connector,
5696                                aud_cntrl_st2, eldv,
5697                                aud_cntl_st, IBX_ELD_ADDRESS,
5698                                hdmiw_hdmiedid))
5699                 return;
5700
5701         i = I915_READ(aud_cntrl_st2);
5702         i &= ~eldv;
5703         I915_WRITE(aud_cntrl_st2, i);
5704
5705         if (!eld[0])
5706                 return;
5707
5708         i = I915_READ(aud_cntl_st);
5709         i &= ~IBX_ELD_ADDRESS;
5710         I915_WRITE(aud_cntl_st, i);
5711         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5712         DRM_DEBUG_DRIVER("port num:%d\n", i);
5713
5714         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5715         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5716         for (i = 0; i < len; i++)
5717                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5718
5719         i = I915_READ(aud_cntrl_st2);
5720         i |= eldv;
5721         I915_WRITE(aud_cntrl_st2, i);
5722
5723 }
5724
5725 static void ironlake_write_eld(struct drm_connector *connector,
5726                                      struct drm_crtc *crtc)
5727 {
5728         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5729         uint8_t *eld = connector->eld;
5730         uint32_t eldv;
5731         uint32_t i;
5732         int len;
5733         int hdmiw_hdmiedid;
5734         int aud_config;
5735         int aud_cntl_st;
5736         int aud_cntrl_st2;
5737         int pipe = to_intel_crtc(crtc)->pipe;
5738
5739         if (HAS_PCH_IBX(connector->dev)) {
5740                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5741                 aud_config = IBX_AUD_CFG(pipe);
5742                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5743                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5744         } else {
5745                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5746                 aud_config = CPT_AUD_CFG(pipe);
5747                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5748                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5749         }
5750
5751         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5752
5753         i = I915_READ(aud_cntl_st);
5754         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5755         if (!i) {
5756                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5757                 /* operate blindly on all ports */
5758                 eldv = IBX_ELD_VALIDB;
5759                 eldv |= IBX_ELD_VALIDB << 4;
5760                 eldv |= IBX_ELD_VALIDB << 8;
5761         } else {
5762                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5763                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5764         }
5765
5766         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5767                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5768                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5769                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5770         } else
5771                 I915_WRITE(aud_config, 0);
5772
5773         if (intel_eld_uptodate(connector,
5774                                aud_cntrl_st2, eldv,
5775                                aud_cntl_st, IBX_ELD_ADDRESS,
5776                                hdmiw_hdmiedid))
5777                 return;
5778
5779         i = I915_READ(aud_cntrl_st2);
5780         i &= ~eldv;
5781         I915_WRITE(aud_cntrl_st2, i);
5782
5783         if (!eld[0])
5784                 return;
5785
5786         i = I915_READ(aud_cntl_st);
5787         i &= ~IBX_ELD_ADDRESS;
5788         I915_WRITE(aud_cntl_st, i);
5789
5790         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5791         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5792         for (i = 0; i < len; i++)
5793                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5794
5795         i = I915_READ(aud_cntrl_st2);
5796         i |= eldv;
5797         I915_WRITE(aud_cntrl_st2, i);
5798 }
5799
5800 void intel_write_eld(struct drm_encoder *encoder,
5801                      struct drm_display_mode *mode)
5802 {
5803         struct drm_crtc *crtc = encoder->crtc;
5804         struct drm_connector *connector;
5805         struct drm_device *dev = encoder->dev;
5806         struct drm_i915_private *dev_priv = dev->dev_private;
5807
5808         connector = drm_select_eld(encoder, mode);
5809         if (!connector)
5810                 return;
5811
5812         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5813                          connector->base.id,
5814                          drm_get_connector_name(connector),
5815                          connector->encoder->base.id,
5816                          drm_get_encoder_name(connector->encoder));
5817
5818         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5819
5820         if (dev_priv->display.write_eld)
5821                 dev_priv->display.write_eld(connector, crtc);
5822 }
5823
5824 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5825 void intel_crtc_load_lut(struct drm_crtc *crtc)
5826 {
5827         struct drm_device *dev = crtc->dev;
5828         struct drm_i915_private *dev_priv = dev->dev_private;
5829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5830         int palreg = PALETTE(intel_crtc->pipe);
5831         int i;
5832
5833         /* The clocks have to be on to load the palette. */
5834         if (!crtc->enabled || !intel_crtc->active)
5835                 return;
5836
5837         /* use legacy palette for Ironlake */
5838         if (HAS_PCH_SPLIT(dev))
5839                 palreg = LGC_PALETTE(intel_crtc->pipe);
5840
5841         for (i = 0; i < 256; i++) {
5842                 I915_WRITE(palreg + 4 * i,
5843                            (intel_crtc->lut_r[i] << 16) |
5844                            (intel_crtc->lut_g[i] << 8) |
5845                            intel_crtc->lut_b[i]);
5846         }
5847 }
5848
5849 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5850 {
5851         struct drm_device *dev = crtc->dev;
5852         struct drm_i915_private *dev_priv = dev->dev_private;
5853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5854         bool visible = base != 0;
5855         u32 cntl;
5856
5857         if (intel_crtc->cursor_visible == visible)
5858                 return;
5859
5860         cntl = I915_READ(_CURACNTR);
5861         if (visible) {
5862                 /* On these chipsets we can only modify the base whilst
5863                  * the cursor is disabled.
5864                  */
5865                 I915_WRITE(_CURABASE, base);
5866
5867                 cntl &= ~(CURSOR_FORMAT_MASK);
5868                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5869                 cntl |= CURSOR_ENABLE |
5870                         CURSOR_GAMMA_ENABLE |
5871                         CURSOR_FORMAT_ARGB;
5872         } else
5873                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5874         I915_WRITE(_CURACNTR, cntl);
5875
5876         intel_crtc->cursor_visible = visible;
5877 }
5878
5879 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5880 {
5881         struct drm_device *dev = crtc->dev;
5882         struct drm_i915_private *dev_priv = dev->dev_private;
5883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5884         int pipe = intel_crtc->pipe;
5885         bool visible = base != 0;
5886
5887         if (intel_crtc->cursor_visible != visible) {
5888                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5889                 if (base) {
5890                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5891                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5892                         cntl |= pipe << 28; /* Connect to correct pipe */
5893                 } else {
5894                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5895                         cntl |= CURSOR_MODE_DISABLE;
5896                 }
5897                 I915_WRITE(CURCNTR(pipe), cntl);
5898
5899                 intel_crtc->cursor_visible = visible;
5900         }
5901         /* and commit changes on next vblank */
5902         I915_WRITE(CURBASE(pipe), base);
5903 }
5904
5905 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5906 {
5907         struct drm_device *dev = crtc->dev;
5908         struct drm_i915_private *dev_priv = dev->dev_private;
5909         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5910         int pipe = intel_crtc->pipe;
5911         bool visible = base != 0;
5912
5913         if (intel_crtc->cursor_visible != visible) {
5914                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5915                 if (base) {
5916                         cntl &= ~CURSOR_MODE;
5917                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5918                 } else {
5919                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5920                         cntl |= CURSOR_MODE_DISABLE;
5921                 }
5922                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5923
5924                 intel_crtc->cursor_visible = visible;
5925         }
5926         /* and commit changes on next vblank */
5927         I915_WRITE(CURBASE_IVB(pipe), base);
5928 }
5929
5930 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5931 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5932                                      bool on)
5933 {
5934         struct drm_device *dev = crtc->dev;
5935         struct drm_i915_private *dev_priv = dev->dev_private;
5936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5937         int pipe = intel_crtc->pipe;
5938         int x = intel_crtc->cursor_x;
5939         int y = intel_crtc->cursor_y;
5940         u32 base, pos;
5941         bool visible;
5942
5943         pos = 0;
5944
5945         if (on && crtc->enabled && crtc->fb) {
5946                 base = intel_crtc->cursor_addr;
5947                 if (x > (int) crtc->fb->width)
5948                         base = 0;
5949
5950                 if (y > (int) crtc->fb->height)
5951                         base = 0;
5952         } else
5953                 base = 0;
5954
5955         if (x < 0) {
5956                 if (x + intel_crtc->cursor_width < 0)
5957                         base = 0;
5958
5959                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5960                 x = -x;
5961         }
5962         pos |= x << CURSOR_X_SHIFT;
5963
5964         if (y < 0) {
5965                 if (y + intel_crtc->cursor_height < 0)
5966                         base = 0;
5967
5968                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5969                 y = -y;
5970         }
5971         pos |= y << CURSOR_Y_SHIFT;
5972
5973         visible = base != 0;
5974         if (!visible && !intel_crtc->cursor_visible)
5975                 return;
5976
5977         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5978                 I915_WRITE(CURPOS_IVB(pipe), pos);
5979                 ivb_update_cursor(crtc, base);
5980         } else {
5981                 I915_WRITE(CURPOS(pipe), pos);
5982                 if (IS_845G(dev) || IS_I865G(dev))
5983                         i845_update_cursor(crtc, base);
5984                 else
5985                         i9xx_update_cursor(crtc, base);
5986         }
5987 }
5988
5989 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5990                                  struct drm_file *file,
5991                                  uint32_t handle,
5992                                  uint32_t width, uint32_t height)
5993 {
5994         struct drm_device *dev = crtc->dev;
5995         struct drm_i915_private *dev_priv = dev->dev_private;
5996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5997         struct drm_i915_gem_object *obj;
5998         uint32_t addr;
5999         int ret;
6000
6001         /* if we want to turn off the cursor ignore width and height */
6002         if (!handle) {
6003                 DRM_DEBUG_KMS("cursor off\n");
6004                 addr = 0;
6005                 obj = NULL;
6006                 mutex_lock(&dev->struct_mutex);
6007                 goto finish;
6008         }
6009
6010         /* Currently we only support 64x64 cursors */
6011         if (width != 64 || height != 64) {
6012                 DRM_ERROR("we currently only support 64x64 cursors\n");
6013                 return -EINVAL;
6014         }
6015
6016         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6017         if (&obj->base == NULL)
6018                 return -ENOENT;
6019
6020         if (obj->base.size < width * height * 4) {
6021                 DRM_ERROR("buffer is to small\n");
6022                 ret = -ENOMEM;
6023                 goto fail;
6024         }
6025
6026         /* we only need to pin inside GTT if cursor is non-phy */
6027         mutex_lock(&dev->struct_mutex);
6028         if (!dev_priv->info->cursor_needs_physical) {
6029                 if (obj->tiling_mode) {
6030                         DRM_ERROR("cursor cannot be tiled\n");
6031                         ret = -EINVAL;
6032                         goto fail_locked;
6033                 }
6034
6035                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6036                 if (ret) {
6037                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6038                         goto fail_locked;
6039                 }
6040
6041                 ret = i915_gem_object_put_fence(obj);
6042                 if (ret) {
6043                         DRM_ERROR("failed to release fence for cursor");
6044                         goto fail_unpin;
6045                 }
6046
6047                 addr = obj->gtt_offset;
6048         } else {
6049                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6050                 ret = i915_gem_attach_phys_object(dev, obj,
6051                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6052                                                   align);
6053                 if (ret) {
6054                         DRM_ERROR("failed to attach phys object\n");
6055                         goto fail_locked;
6056                 }
6057                 addr = obj->phys_obj->handle->busaddr;
6058         }
6059
6060         if (IS_GEN2(dev))
6061                 I915_WRITE(CURSIZE, (height << 12) | width);
6062
6063  finish:
6064         if (intel_crtc->cursor_bo) {
6065                 if (dev_priv->info->cursor_needs_physical) {
6066                         if (intel_crtc->cursor_bo != obj)
6067                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6068                 } else
6069                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6070                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6071         }
6072
6073         mutex_unlock(&dev->struct_mutex);
6074
6075         intel_crtc->cursor_addr = addr;
6076         intel_crtc->cursor_bo = obj;
6077         intel_crtc->cursor_width = width;
6078         intel_crtc->cursor_height = height;
6079
6080         intel_crtc_update_cursor(crtc, true);
6081
6082         return 0;
6083 fail_unpin:
6084         i915_gem_object_unpin(obj);
6085 fail_locked:
6086         mutex_unlock(&dev->struct_mutex);
6087 fail:
6088         drm_gem_object_unreference_unlocked(&obj->base);
6089         return ret;
6090 }
6091
6092 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6093 {
6094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6095
6096         intel_crtc->cursor_x = x;
6097         intel_crtc->cursor_y = y;
6098
6099         intel_crtc_update_cursor(crtc, true);
6100
6101         return 0;
6102 }
6103
6104 /** Sets the color ramps on behalf of RandR */
6105 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6106                                  u16 blue, int regno)
6107 {
6108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6109
6110         intel_crtc->lut_r[regno] = red >> 8;
6111         intel_crtc->lut_g[regno] = green >> 8;
6112         intel_crtc->lut_b[regno] = blue >> 8;
6113 }
6114
6115 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6116                              u16 *blue, int regno)
6117 {
6118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119
6120         *red = intel_crtc->lut_r[regno] << 8;
6121         *green = intel_crtc->lut_g[regno] << 8;
6122         *blue = intel_crtc->lut_b[regno] << 8;
6123 }
6124
6125 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6126                                  u16 *blue, uint32_t start, uint32_t size)
6127 {
6128         int end = (start + size > 256) ? 256 : start + size, i;
6129         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130
6131         for (i = start; i < end; i++) {
6132                 intel_crtc->lut_r[i] = red[i] >> 8;
6133                 intel_crtc->lut_g[i] = green[i] >> 8;
6134                 intel_crtc->lut_b[i] = blue[i] >> 8;
6135         }
6136
6137         intel_crtc_load_lut(crtc);
6138 }
6139
6140 /**
6141  * Get a pipe with a simple mode set on it for doing load-based monitor
6142  * detection.
6143  *
6144  * It will be up to the load-detect code to adjust the pipe as appropriate for
6145  * its requirements.  The pipe will be connected to no other encoders.
6146  *
6147  * Currently this code will only succeed if there is a pipe with no encoders
6148  * configured for it.  In the future, it could choose to temporarily disable
6149  * some outputs to free up a pipe for its use.
6150  *
6151  * \return crtc, or NULL if no pipes are available.
6152  */
6153
6154 /* VESA 640x480x72Hz mode to set on the pipe */
6155 static struct drm_display_mode load_detect_mode = {
6156         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6157                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6158 };
6159
6160 static struct drm_framebuffer *
6161 intel_framebuffer_create(struct drm_device *dev,
6162                          struct drm_mode_fb_cmd2 *mode_cmd,
6163                          struct drm_i915_gem_object *obj)
6164 {
6165         struct intel_framebuffer *intel_fb;
6166         int ret;
6167
6168         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6169         if (!intel_fb) {
6170                 drm_gem_object_unreference_unlocked(&obj->base);
6171                 return ERR_PTR(-ENOMEM);
6172         }
6173
6174         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6175         if (ret) {
6176                 drm_gem_object_unreference_unlocked(&obj->base);
6177                 kfree(intel_fb);
6178                 return ERR_PTR(ret);
6179         }
6180
6181         return &intel_fb->base;
6182 }
6183
6184 static u32
6185 intel_framebuffer_pitch_for_width(int width, int bpp)
6186 {
6187         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6188         return ALIGN(pitch, 64);
6189 }
6190
6191 static u32
6192 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6193 {
6194         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6195         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6196 }
6197
6198 static struct drm_framebuffer *
6199 intel_framebuffer_create_for_mode(struct drm_device *dev,
6200                                   struct drm_display_mode *mode,
6201                                   int depth, int bpp)
6202 {
6203         struct drm_i915_gem_object *obj;
6204         struct drm_mode_fb_cmd2 mode_cmd;
6205
6206         obj = i915_gem_alloc_object(dev,
6207                                     intel_framebuffer_size_for_mode(mode, bpp));
6208         if (obj == NULL)
6209                 return ERR_PTR(-ENOMEM);
6210
6211         mode_cmd.width = mode->hdisplay;
6212         mode_cmd.height = mode->vdisplay;
6213         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6214                                                                 bpp);
6215         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6216
6217         return intel_framebuffer_create(dev, &mode_cmd, obj);
6218 }
6219
6220 static struct drm_framebuffer *
6221 mode_fits_in_fbdev(struct drm_device *dev,
6222                    struct drm_display_mode *mode)
6223 {
6224         struct drm_i915_private *dev_priv = dev->dev_private;
6225         struct drm_i915_gem_object *obj;
6226         struct drm_framebuffer *fb;
6227
6228         if (dev_priv->fbdev == NULL)
6229                 return NULL;
6230
6231         obj = dev_priv->fbdev->ifb.obj;
6232         if (obj == NULL)
6233                 return NULL;
6234
6235         fb = &dev_priv->fbdev->ifb.base;
6236         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6237                                                                fb->bits_per_pixel))
6238                 return NULL;
6239
6240         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6241                 return NULL;
6242
6243         return fb;
6244 }
6245
6246 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6247                                 struct drm_display_mode *mode,
6248                                 struct intel_load_detect_pipe *old)
6249 {
6250         struct intel_crtc *intel_crtc;
6251         struct intel_encoder *intel_encoder =
6252                 intel_attached_encoder(connector);
6253         struct drm_crtc *possible_crtc;
6254         struct drm_encoder *encoder = &intel_encoder->base;
6255         struct drm_crtc *crtc = NULL;
6256         struct drm_device *dev = encoder->dev;
6257         struct drm_framebuffer *fb;
6258         int i = -1;
6259
6260         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6261                       connector->base.id, drm_get_connector_name(connector),
6262                       encoder->base.id, drm_get_encoder_name(encoder));
6263
6264         /*
6265          * Algorithm gets a little messy:
6266          *
6267          *   - if the connector already has an assigned crtc, use it (but make
6268          *     sure it's on first)
6269          *
6270          *   - try to find the first unused crtc that can drive this connector,
6271          *     and use that if we find one
6272          */
6273
6274         /* See if we already have a CRTC for this connector */
6275         if (encoder->crtc) {
6276                 crtc = encoder->crtc;
6277
6278                 old->dpms_mode = connector->dpms;
6279                 old->load_detect_temp = false;
6280
6281                 /* Make sure the crtc and connector are running */
6282                 if (connector->dpms != DRM_MODE_DPMS_ON)
6283                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6284
6285                 return true;
6286         }
6287
6288         /* Find an unused one (if possible) */
6289         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6290                 i++;
6291                 if (!(encoder->possible_crtcs & (1 << i)))
6292                         continue;
6293                 if (!possible_crtc->enabled) {
6294                         crtc = possible_crtc;
6295                         break;
6296                 }
6297         }
6298
6299         /*
6300          * If we didn't find an unused CRTC, don't use any.
6301          */
6302         if (!crtc) {
6303                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6304                 return false;
6305         }
6306
6307         intel_encoder->new_crtc = to_intel_crtc(crtc);
6308         to_intel_connector(connector)->new_encoder = intel_encoder;
6309
6310         intel_crtc = to_intel_crtc(crtc);
6311         old->dpms_mode = connector->dpms;
6312         old->load_detect_temp = true;
6313         old->release_fb = NULL;
6314
6315         if (!mode)
6316                 mode = &load_detect_mode;
6317
6318         /* We need a framebuffer large enough to accommodate all accesses
6319          * that the plane may generate whilst we perform load detection.
6320          * We can not rely on the fbcon either being present (we get called
6321          * during its initialisation to detect all boot displays, or it may
6322          * not even exist) or that it is large enough to satisfy the
6323          * requested mode.
6324          */
6325         fb = mode_fits_in_fbdev(dev, mode);
6326         if (fb == NULL) {
6327                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6328                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6329                 old->release_fb = fb;
6330         } else
6331                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6332         if (IS_ERR(fb)) {
6333                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6334                 goto fail;
6335         }
6336
6337         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6338                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6339                 if (old->release_fb)
6340                         old->release_fb->funcs->destroy(old->release_fb);
6341                 goto fail;
6342         }
6343
6344         /* let the connector get through one full cycle before testing */
6345         intel_wait_for_vblank(dev, intel_crtc->pipe);
6346
6347         return true;
6348 fail:
6349         connector->encoder = NULL;
6350         encoder->crtc = NULL;
6351         return false;
6352 }
6353
6354 void intel_release_load_detect_pipe(struct drm_connector *connector,
6355                                     struct intel_load_detect_pipe *old)
6356 {
6357         struct intel_encoder *intel_encoder =
6358                 intel_attached_encoder(connector);
6359         struct drm_encoder *encoder = &intel_encoder->base;
6360
6361         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6362                       connector->base.id, drm_get_connector_name(connector),
6363                       encoder->base.id, drm_get_encoder_name(encoder));
6364
6365         if (old->load_detect_temp) {
6366                 struct drm_crtc *crtc = encoder->crtc;
6367
6368                 to_intel_connector(connector)->new_encoder = NULL;
6369                 intel_encoder->new_crtc = NULL;
6370                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6371
6372                 if (old->release_fb)
6373                         old->release_fb->funcs->destroy(old->release_fb);
6374
6375                 return;
6376         }
6377
6378         /* Switch crtc and encoder back off if necessary */
6379         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6380                 connector->funcs->dpms(connector, old->dpms_mode);
6381 }
6382
6383 /* Returns the clock of the currently programmed mode of the given pipe. */
6384 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6385 {
6386         struct drm_i915_private *dev_priv = dev->dev_private;
6387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388         int pipe = intel_crtc->pipe;
6389         u32 dpll = I915_READ(DPLL(pipe));
6390         u32 fp;
6391         intel_clock_t clock;
6392
6393         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6394                 fp = I915_READ(FP0(pipe));
6395         else
6396                 fp = I915_READ(FP1(pipe));
6397
6398         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6399         if (IS_PINEVIEW(dev)) {
6400                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6401                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6402         } else {
6403                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6404                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6405         }
6406
6407         if (!IS_GEN2(dev)) {
6408                 if (IS_PINEVIEW(dev))
6409                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6410                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6411                 else
6412                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6413                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6414
6415                 switch (dpll & DPLL_MODE_MASK) {
6416                 case DPLLB_MODE_DAC_SERIAL:
6417                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6418                                 5 : 10;
6419                         break;
6420                 case DPLLB_MODE_LVDS:
6421                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6422                                 7 : 14;
6423                         break;
6424                 default:
6425                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6426                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6427                         return 0;
6428                 }
6429
6430                 /* XXX: Handle the 100Mhz refclk */
6431                 intel_clock(dev, 96000, &clock);
6432         } else {
6433                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6434
6435                 if (is_lvds) {
6436                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6437                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6438                         clock.p2 = 14;
6439
6440                         if ((dpll & PLL_REF_INPUT_MASK) ==
6441                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6442                                 /* XXX: might not be 66MHz */
6443                                 intel_clock(dev, 66000, &clock);
6444                         } else
6445                                 intel_clock(dev, 48000, &clock);
6446                 } else {
6447                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6448                                 clock.p1 = 2;
6449                         else {
6450                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6451                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6452                         }
6453                         if (dpll & PLL_P2_DIVIDE_BY_4)
6454                                 clock.p2 = 4;
6455                         else
6456                                 clock.p2 = 2;
6457
6458                         intel_clock(dev, 48000, &clock);
6459                 }
6460         }
6461
6462         /* XXX: It would be nice to validate the clocks, but we can't reuse
6463          * i830PllIsValid() because it relies on the xf86_config connector
6464          * configuration being accurate, which it isn't necessarily.
6465          */
6466
6467         return clock.dot;
6468 }
6469
6470 /** Returns the currently programmed mode of the given pipe. */
6471 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6472                                              struct drm_crtc *crtc)
6473 {
6474         struct drm_i915_private *dev_priv = dev->dev_private;
6475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6476         int pipe = intel_crtc->pipe;
6477         struct drm_display_mode *mode;
6478         int htot = I915_READ(HTOTAL(pipe));
6479         int hsync = I915_READ(HSYNC(pipe));
6480         int vtot = I915_READ(VTOTAL(pipe));
6481         int vsync = I915_READ(VSYNC(pipe));
6482
6483         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6484         if (!mode)
6485                 return NULL;
6486
6487         mode->clock = intel_crtc_clock_get(dev, crtc);
6488         mode->hdisplay = (htot & 0xffff) + 1;
6489         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6490         mode->hsync_start = (hsync & 0xffff) + 1;
6491         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6492         mode->vdisplay = (vtot & 0xffff) + 1;
6493         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6494         mode->vsync_start = (vsync & 0xffff) + 1;
6495         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6496
6497         drm_mode_set_name(mode);
6498
6499         return mode;
6500 }
6501
6502 static void intel_increase_pllclock(struct drm_crtc *crtc)
6503 {
6504         struct drm_device *dev = crtc->dev;
6505         drm_i915_private_t *dev_priv = dev->dev_private;
6506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6507         int pipe = intel_crtc->pipe;
6508         int dpll_reg = DPLL(pipe);
6509         int dpll;
6510
6511         if (HAS_PCH_SPLIT(dev))
6512                 return;
6513
6514         if (!dev_priv->lvds_downclock_avail)
6515                 return;
6516
6517         dpll = I915_READ(dpll_reg);
6518         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6519                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6520
6521                 assert_panel_unlocked(dev_priv, pipe);
6522
6523                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6524                 I915_WRITE(dpll_reg, dpll);
6525                 intel_wait_for_vblank(dev, pipe);
6526
6527                 dpll = I915_READ(dpll_reg);
6528                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6529                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6530         }
6531 }
6532
6533 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6534 {
6535         struct drm_device *dev = crtc->dev;
6536         drm_i915_private_t *dev_priv = dev->dev_private;
6537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6538
6539         if (HAS_PCH_SPLIT(dev))
6540                 return;
6541
6542         if (!dev_priv->lvds_downclock_avail)
6543                 return;
6544
6545         /*
6546          * Since this is called by a timer, we should never get here in
6547          * the manual case.
6548          */
6549         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6550                 int pipe = intel_crtc->pipe;
6551                 int dpll_reg = DPLL(pipe);
6552                 int dpll;
6553
6554                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6555
6556                 assert_panel_unlocked(dev_priv, pipe);
6557
6558                 dpll = I915_READ(dpll_reg);
6559                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6560                 I915_WRITE(dpll_reg, dpll);
6561                 intel_wait_for_vblank(dev, pipe);
6562                 dpll = I915_READ(dpll_reg);
6563                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6564                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6565         }
6566
6567 }
6568
6569 void intel_mark_busy(struct drm_device *dev)
6570 {
6571         i915_update_gfx_val(dev->dev_private);
6572 }
6573
6574 void intel_mark_idle(struct drm_device *dev)
6575 {
6576 }
6577
6578 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6579 {
6580         struct drm_device *dev = obj->base.dev;
6581         struct drm_crtc *crtc;
6582
6583         if (!i915_powersave)
6584                 return;
6585
6586         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6587                 if (!crtc->fb)
6588                         continue;
6589
6590                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6591                         intel_increase_pllclock(crtc);
6592         }
6593 }
6594
6595 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6596 {
6597         struct drm_device *dev = obj->base.dev;
6598         struct drm_crtc *crtc;
6599
6600         if (!i915_powersave)
6601                 return;
6602
6603         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6604                 if (!crtc->fb)
6605                         continue;
6606
6607                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6608                         intel_decrease_pllclock(crtc);
6609         }
6610 }
6611
6612 static void intel_crtc_destroy(struct drm_crtc *crtc)
6613 {
6614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615         struct drm_device *dev = crtc->dev;
6616         struct intel_unpin_work *work;
6617         unsigned long flags;
6618
6619         spin_lock_irqsave(&dev->event_lock, flags);
6620         work = intel_crtc->unpin_work;
6621         intel_crtc->unpin_work = NULL;
6622         spin_unlock_irqrestore(&dev->event_lock, flags);
6623
6624         if (work) {
6625                 cancel_work_sync(&work->work);
6626                 kfree(work);
6627         }
6628
6629         drm_crtc_cleanup(crtc);
6630
6631         kfree(intel_crtc);
6632 }
6633
6634 static void intel_unpin_work_fn(struct work_struct *__work)
6635 {
6636         struct intel_unpin_work *work =
6637                 container_of(__work, struct intel_unpin_work, work);
6638
6639         mutex_lock(&work->dev->struct_mutex);
6640         intel_unpin_fb_obj(work->old_fb_obj);
6641         drm_gem_object_unreference(&work->pending_flip_obj->base);
6642         drm_gem_object_unreference(&work->old_fb_obj->base);
6643
6644         intel_update_fbc(work->dev);
6645         mutex_unlock(&work->dev->struct_mutex);
6646         kfree(work);
6647 }
6648
6649 static void do_intel_finish_page_flip(struct drm_device *dev,
6650                                       struct drm_crtc *crtc)
6651 {
6652         drm_i915_private_t *dev_priv = dev->dev_private;
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654         struct intel_unpin_work *work;
6655         struct drm_i915_gem_object *obj;
6656         struct drm_pending_vblank_event *e;
6657         struct timeval tvbl;
6658         unsigned long flags;
6659
6660         /* Ignore early vblank irqs */
6661         if (intel_crtc == NULL)
6662                 return;
6663
6664         spin_lock_irqsave(&dev->event_lock, flags);
6665         work = intel_crtc->unpin_work;
6666         if (work == NULL || !work->pending) {
6667                 spin_unlock_irqrestore(&dev->event_lock, flags);
6668                 return;
6669         }
6670
6671         intel_crtc->unpin_work = NULL;
6672
6673         if (work->event) {
6674                 e = work->event;
6675                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6676
6677                 e->event.tv_sec = tvbl.tv_sec;
6678                 e->event.tv_usec = tvbl.tv_usec;
6679
6680                 list_add_tail(&e->base.link,
6681                               &e->base.file_priv->event_list);
6682                 wake_up_interruptible(&e->base.file_priv->event_wait);
6683         }
6684
6685         drm_vblank_put(dev, intel_crtc->pipe);
6686
6687         spin_unlock_irqrestore(&dev->event_lock, flags);
6688
6689         obj = work->old_fb_obj;
6690
6691         atomic_clear_mask(1 << intel_crtc->plane,
6692                           &obj->pending_flip.counter);
6693
6694         wake_up(&dev_priv->pending_flip_queue);
6695         schedule_work(&work->work);
6696
6697         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6698 }
6699
6700 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6701 {
6702         drm_i915_private_t *dev_priv = dev->dev_private;
6703         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6704
6705         do_intel_finish_page_flip(dev, crtc);
6706 }
6707
6708 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6709 {
6710         drm_i915_private_t *dev_priv = dev->dev_private;
6711         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6712
6713         do_intel_finish_page_flip(dev, crtc);
6714 }
6715
6716 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6717 {
6718         drm_i915_private_t *dev_priv = dev->dev_private;
6719         struct intel_crtc *intel_crtc =
6720                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6721         unsigned long flags;
6722
6723         spin_lock_irqsave(&dev->event_lock, flags);
6724         if (intel_crtc->unpin_work) {
6725                 if ((++intel_crtc->unpin_work->pending) > 1)
6726                         DRM_ERROR("Prepared flip multiple times\n");
6727         } else {
6728                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6729         }
6730         spin_unlock_irqrestore(&dev->event_lock, flags);
6731 }
6732
6733 static int intel_gen2_queue_flip(struct drm_device *dev,
6734                                  struct drm_crtc *crtc,
6735                                  struct drm_framebuffer *fb,
6736                                  struct drm_i915_gem_object *obj)
6737 {
6738         struct drm_i915_private *dev_priv = dev->dev_private;
6739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6740         u32 flip_mask;
6741         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6742         int ret;
6743
6744         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6745         if (ret)
6746                 goto err;
6747
6748         ret = intel_ring_begin(ring, 6);
6749         if (ret)
6750                 goto err_unpin;
6751
6752         /* Can't queue multiple flips, so wait for the previous
6753          * one to finish before executing the next.
6754          */
6755         if (intel_crtc->plane)
6756                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6757         else
6758                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6759         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6760         intel_ring_emit(ring, MI_NOOP);
6761         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6762                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6763         intel_ring_emit(ring, fb->pitches[0]);
6764         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6765         intel_ring_emit(ring, 0); /* aux display base address, unused */
6766         intel_ring_advance(ring);
6767         return 0;
6768
6769 err_unpin:
6770         intel_unpin_fb_obj(obj);
6771 err:
6772         return ret;
6773 }
6774
6775 static int intel_gen3_queue_flip(struct drm_device *dev,
6776                                  struct drm_crtc *crtc,
6777                                  struct drm_framebuffer *fb,
6778                                  struct drm_i915_gem_object *obj)
6779 {
6780         struct drm_i915_private *dev_priv = dev->dev_private;
6781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6782         u32 flip_mask;
6783         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6784         int ret;
6785
6786         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6787         if (ret)
6788                 goto err;
6789
6790         ret = intel_ring_begin(ring, 6);
6791         if (ret)
6792                 goto err_unpin;
6793
6794         if (intel_crtc->plane)
6795                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6796         else
6797                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6798         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6799         intel_ring_emit(ring, MI_NOOP);
6800         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6801                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6802         intel_ring_emit(ring, fb->pitches[0]);
6803         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6804         intel_ring_emit(ring, MI_NOOP);
6805
6806         intel_ring_advance(ring);
6807         return 0;
6808
6809 err_unpin:
6810         intel_unpin_fb_obj(obj);
6811 err:
6812         return ret;
6813 }
6814
6815 static int intel_gen4_queue_flip(struct drm_device *dev,
6816                                  struct drm_crtc *crtc,
6817                                  struct drm_framebuffer *fb,
6818                                  struct drm_i915_gem_object *obj)
6819 {
6820         struct drm_i915_private *dev_priv = dev->dev_private;
6821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6822         uint32_t pf, pipesrc;
6823         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6824         int ret;
6825
6826         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6827         if (ret)
6828                 goto err;
6829
6830         ret = intel_ring_begin(ring, 4);
6831         if (ret)
6832                 goto err_unpin;
6833
6834         /* i965+ uses the linear or tiled offsets from the
6835          * Display Registers (which do not change across a page-flip)
6836          * so we need only reprogram the base address.
6837          */
6838         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6839                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6840         intel_ring_emit(ring, fb->pitches[0]);
6841         intel_ring_emit(ring,
6842                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6843                         obj->tiling_mode);
6844
6845         /* XXX Enabling the panel-fitter across page-flip is so far
6846          * untested on non-native modes, so ignore it for now.
6847          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6848          */
6849         pf = 0;
6850         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6851         intel_ring_emit(ring, pf | pipesrc);
6852         intel_ring_advance(ring);
6853         return 0;
6854
6855 err_unpin:
6856         intel_unpin_fb_obj(obj);
6857 err:
6858         return ret;
6859 }
6860
6861 static int intel_gen6_queue_flip(struct drm_device *dev,
6862                                  struct drm_crtc *crtc,
6863                                  struct drm_framebuffer *fb,
6864                                  struct drm_i915_gem_object *obj)
6865 {
6866         struct drm_i915_private *dev_priv = dev->dev_private;
6867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6868         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6869         uint32_t pf, pipesrc;
6870         int ret;
6871
6872         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6873         if (ret)
6874                 goto err;
6875
6876         ret = intel_ring_begin(ring, 4);
6877         if (ret)
6878                 goto err_unpin;
6879
6880         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6881                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6882         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6883         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6884
6885         /* Contrary to the suggestions in the documentation,
6886          * "Enable Panel Fitter" does not seem to be required when page
6887          * flipping with a non-native mode, and worse causes a normal
6888          * modeset to fail.
6889          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6890          */
6891         pf = 0;
6892         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6893         intel_ring_emit(ring, pf | pipesrc);
6894         intel_ring_advance(ring);
6895         return 0;
6896
6897 err_unpin:
6898         intel_unpin_fb_obj(obj);
6899 err:
6900         return ret;
6901 }
6902
6903 /*
6904  * On gen7 we currently use the blit ring because (in early silicon at least)
6905  * the render ring doesn't give us interrpts for page flip completion, which
6906  * means clients will hang after the first flip is queued.  Fortunately the
6907  * blit ring generates interrupts properly, so use it instead.
6908  */
6909 static int intel_gen7_queue_flip(struct drm_device *dev,
6910                                  struct drm_crtc *crtc,
6911                                  struct drm_framebuffer *fb,
6912                                  struct drm_i915_gem_object *obj)
6913 {
6914         struct drm_i915_private *dev_priv = dev->dev_private;
6915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6917         uint32_t plane_bit = 0;
6918         int ret;
6919
6920         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6921         if (ret)
6922                 goto err;
6923
6924         switch(intel_crtc->plane) {
6925         case PLANE_A:
6926                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6927                 break;
6928         case PLANE_B:
6929                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6930                 break;
6931         case PLANE_C:
6932                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6933                 break;
6934         default:
6935                 WARN_ONCE(1, "unknown plane in flip command\n");
6936                 ret = -ENODEV;
6937                 goto err_unpin;
6938         }
6939
6940         ret = intel_ring_begin(ring, 4);
6941         if (ret)
6942                 goto err_unpin;
6943
6944         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6945         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6946         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6947         intel_ring_emit(ring, (MI_NOOP));
6948         intel_ring_advance(ring);
6949         return 0;
6950
6951 err_unpin:
6952         intel_unpin_fb_obj(obj);
6953 err:
6954         return ret;
6955 }
6956
6957 static int intel_default_queue_flip(struct drm_device *dev,
6958                                     struct drm_crtc *crtc,
6959                                     struct drm_framebuffer *fb,
6960                                     struct drm_i915_gem_object *obj)
6961 {
6962         return -ENODEV;
6963 }
6964
6965 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6966                                 struct drm_framebuffer *fb,
6967                                 struct drm_pending_vblank_event *event)
6968 {
6969         struct drm_device *dev = crtc->dev;
6970         struct drm_i915_private *dev_priv = dev->dev_private;
6971         struct intel_framebuffer *intel_fb;
6972         struct drm_i915_gem_object *obj;
6973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974         struct intel_unpin_work *work;
6975         unsigned long flags;
6976         int ret;
6977
6978         /* Can't change pixel format via MI display flips. */
6979         if (fb->pixel_format != crtc->fb->pixel_format)
6980                 return -EINVAL;
6981
6982         /*
6983          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6984          * Note that pitch changes could also affect these register.
6985          */
6986         if (INTEL_INFO(dev)->gen > 3 &&
6987             (fb->offsets[0] != crtc->fb->offsets[0] ||
6988              fb->pitches[0] != crtc->fb->pitches[0]))
6989                 return -EINVAL;
6990
6991         work = kzalloc(sizeof *work, GFP_KERNEL);
6992         if (work == NULL)
6993                 return -ENOMEM;
6994
6995         work->event = event;
6996         work->dev = crtc->dev;
6997         intel_fb = to_intel_framebuffer(crtc->fb);
6998         work->old_fb_obj = intel_fb->obj;
6999         INIT_WORK(&work->work, intel_unpin_work_fn);
7000
7001         ret = drm_vblank_get(dev, intel_crtc->pipe);
7002         if (ret)
7003                 goto free_work;
7004
7005         /* We borrow the event spin lock for protecting unpin_work */
7006         spin_lock_irqsave(&dev->event_lock, flags);
7007         if (intel_crtc->unpin_work) {
7008                 spin_unlock_irqrestore(&dev->event_lock, flags);
7009                 kfree(work);
7010                 drm_vblank_put(dev, intel_crtc->pipe);
7011
7012                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7013                 return -EBUSY;
7014         }
7015         intel_crtc->unpin_work = work;
7016         spin_unlock_irqrestore(&dev->event_lock, flags);
7017
7018         intel_fb = to_intel_framebuffer(fb);
7019         obj = intel_fb->obj;
7020
7021         ret = i915_mutex_lock_interruptible(dev);
7022         if (ret)
7023                 goto cleanup;
7024
7025         /* Reference the objects for the scheduled work. */
7026         drm_gem_object_reference(&work->old_fb_obj->base);
7027         drm_gem_object_reference(&obj->base);
7028
7029         crtc->fb = fb;
7030
7031         work->pending_flip_obj = obj;
7032
7033         work->enable_stall_check = true;
7034
7035         /* Block clients from rendering to the new back buffer until
7036          * the flip occurs and the object is no longer visible.
7037          */
7038         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7039
7040         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7041         if (ret)
7042                 goto cleanup_pending;
7043
7044         intel_disable_fbc(dev);
7045         intel_mark_fb_busy(obj);
7046         mutex_unlock(&dev->struct_mutex);
7047
7048         trace_i915_flip_request(intel_crtc->plane, obj);
7049
7050         return 0;
7051
7052 cleanup_pending:
7053         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7054         drm_gem_object_unreference(&work->old_fb_obj->base);
7055         drm_gem_object_unreference(&obj->base);
7056         mutex_unlock(&dev->struct_mutex);
7057
7058 cleanup:
7059         spin_lock_irqsave(&dev->event_lock, flags);
7060         intel_crtc->unpin_work = NULL;
7061         spin_unlock_irqrestore(&dev->event_lock, flags);
7062
7063         drm_vblank_put(dev, intel_crtc->pipe);
7064 free_work:
7065         kfree(work);
7066
7067         return ret;
7068 }
7069
7070 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7071         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7072         .load_lut = intel_crtc_load_lut,
7073         .disable = intel_crtc_noop,
7074 };
7075
7076 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7077 {
7078         struct intel_encoder *other_encoder;
7079         struct drm_crtc *crtc = &encoder->new_crtc->base;
7080
7081         if (WARN_ON(!crtc))
7082                 return false;
7083
7084         list_for_each_entry(other_encoder,
7085                             &crtc->dev->mode_config.encoder_list,
7086                             base.head) {
7087
7088                 if (&other_encoder->new_crtc->base != crtc ||
7089                     encoder == other_encoder)
7090                         continue;
7091                 else
7092                         return true;
7093         }
7094
7095         return false;
7096 }
7097
7098 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7099                                   struct drm_crtc *crtc)
7100 {
7101         struct drm_device *dev;
7102         struct drm_crtc *tmp;
7103         int crtc_mask = 1;
7104
7105         WARN(!crtc, "checking null crtc?\n");
7106
7107         dev = crtc->dev;
7108
7109         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7110                 if (tmp == crtc)
7111                         break;
7112                 crtc_mask <<= 1;
7113         }
7114
7115         if (encoder->possible_crtcs & crtc_mask)
7116                 return true;
7117         return false;
7118 }
7119
7120 /**
7121  * intel_modeset_update_staged_output_state
7122  *
7123  * Updates the staged output configuration state, e.g. after we've read out the
7124  * current hw state.
7125  */
7126 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7127 {
7128         struct intel_encoder *encoder;
7129         struct intel_connector *connector;
7130
7131         list_for_each_entry(connector, &dev->mode_config.connector_list,
7132                             base.head) {
7133                 connector->new_encoder =
7134                         to_intel_encoder(connector->base.encoder);
7135         }
7136
7137         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7138                             base.head) {
7139                 encoder->new_crtc =
7140                         to_intel_crtc(encoder->base.crtc);
7141         }
7142 }
7143
7144 /**
7145  * intel_modeset_commit_output_state
7146  *
7147  * This function copies the stage display pipe configuration to the real one.
7148  */
7149 static void intel_modeset_commit_output_state(struct drm_device *dev)
7150 {
7151         struct intel_encoder *encoder;
7152         struct intel_connector *connector;
7153
7154         list_for_each_entry(connector, &dev->mode_config.connector_list,
7155                             base.head) {
7156                 connector->base.encoder = &connector->new_encoder->base;
7157         }
7158
7159         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7160                             base.head) {
7161                 encoder->base.crtc = &encoder->new_crtc->base;
7162         }
7163 }
7164
7165 static struct drm_display_mode *
7166 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7167                             struct drm_display_mode *mode)
7168 {
7169         struct drm_device *dev = crtc->dev;
7170         struct drm_display_mode *adjusted_mode;
7171         struct drm_encoder_helper_funcs *encoder_funcs;
7172         struct intel_encoder *encoder;
7173
7174         adjusted_mode = drm_mode_duplicate(dev, mode);
7175         if (!adjusted_mode)
7176                 return ERR_PTR(-ENOMEM);
7177
7178         /* Pass our mode to the connectors and the CRTC to give them a chance to
7179          * adjust it according to limitations or connector properties, and also
7180          * a chance to reject the mode entirely.
7181          */
7182         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7183                             base.head) {
7184
7185                 if (&encoder->new_crtc->base != crtc)
7186                         continue;
7187                 encoder_funcs = encoder->base.helper_private;
7188                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7189                                                 adjusted_mode))) {
7190                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7191                         goto fail;
7192                 }
7193         }
7194
7195         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7196                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7197                 goto fail;
7198         }
7199         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7200
7201         return adjusted_mode;
7202 fail:
7203         drm_mode_destroy(dev, adjusted_mode);
7204         return ERR_PTR(-EINVAL);
7205 }
7206
7207 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7208  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7209 static void
7210 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7211                              unsigned *prepare_pipes, unsigned *disable_pipes)
7212 {
7213         struct intel_crtc *intel_crtc;
7214         struct drm_device *dev = crtc->dev;
7215         struct intel_encoder *encoder;
7216         struct intel_connector *connector;
7217         struct drm_crtc *tmp_crtc;
7218
7219         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7220
7221         /* Check which crtcs have changed outputs connected to them, these need
7222          * to be part of the prepare_pipes mask. We don't (yet) support global
7223          * modeset across multiple crtcs, so modeset_pipes will only have one
7224          * bit set at most. */
7225         list_for_each_entry(connector, &dev->mode_config.connector_list,
7226                             base.head) {
7227                 if (connector->base.encoder == &connector->new_encoder->base)
7228                         continue;
7229
7230                 if (connector->base.encoder) {
7231                         tmp_crtc = connector->base.encoder->crtc;
7232
7233                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7234                 }
7235
7236                 if (connector->new_encoder)
7237                         *prepare_pipes |=
7238                                 1 << connector->new_encoder->new_crtc->pipe;
7239         }
7240
7241         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7242                             base.head) {
7243                 if (encoder->base.crtc == &encoder->new_crtc->base)
7244                         continue;
7245
7246                 if (encoder->base.crtc) {
7247                         tmp_crtc = encoder->base.crtc;
7248
7249                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7250                 }
7251
7252                 if (encoder->new_crtc)
7253                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7254         }
7255
7256         /* Check for any pipes that will be fully disabled ... */
7257         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7258                             base.head) {
7259                 bool used = false;
7260
7261                 /* Don't try to disable disabled crtcs. */
7262                 if (!intel_crtc->base.enabled)
7263                         continue;
7264
7265                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7266                                     base.head) {
7267                         if (encoder->new_crtc == intel_crtc)
7268                                 used = true;
7269                 }
7270
7271                 if (!used)
7272                         *disable_pipes |= 1 << intel_crtc->pipe;
7273         }
7274
7275
7276         /* set_mode is also used to update properties on life display pipes. */
7277         intel_crtc = to_intel_crtc(crtc);
7278         if (crtc->enabled)
7279                 *prepare_pipes |= 1 << intel_crtc->pipe;
7280
7281         /* We only support modeset on one single crtc, hence we need to do that
7282          * only for the passed in crtc iff we change anything else than just
7283          * disable crtcs.
7284          *
7285          * This is actually not true, to be fully compatible with the old crtc
7286          * helper we automatically disable _any_ output (i.e. doesn't need to be
7287          * connected to the crtc we're modesetting on) if it's disconnected.
7288          * Which is a rather nutty api (since changed the output configuration
7289          * without userspace's explicit request can lead to confusion), but
7290          * alas. Hence we currently need to modeset on all pipes we prepare. */
7291         if (*prepare_pipes)
7292                 *modeset_pipes = *prepare_pipes;
7293
7294         /* ... and mask these out. */
7295         *modeset_pipes &= ~(*disable_pipes);
7296         *prepare_pipes &= ~(*disable_pipes);
7297 }
7298
7299 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7300 {
7301         struct drm_encoder *encoder;
7302         struct drm_device *dev = crtc->dev;
7303
7304         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7305                 if (encoder->crtc == crtc)
7306                         return true;
7307
7308         return false;
7309 }
7310
7311 static void
7312 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7313 {
7314         struct intel_encoder *intel_encoder;
7315         struct intel_crtc *intel_crtc;
7316         struct drm_connector *connector;
7317
7318         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7319                             base.head) {
7320                 if (!intel_encoder->base.crtc)
7321                         continue;
7322
7323                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7324
7325                 if (prepare_pipes & (1 << intel_crtc->pipe))
7326                         intel_encoder->connectors_active = false;
7327         }
7328
7329         intel_modeset_commit_output_state(dev);
7330
7331         /* Update computed state. */
7332         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7333                             base.head) {
7334                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7335         }
7336
7337         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7338                 if (!connector->encoder || !connector->encoder->crtc)
7339                         continue;
7340
7341                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7342
7343                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7344                         struct drm_property *dpms_property =
7345                                 dev->mode_config.dpms_property;
7346
7347                         connector->dpms = DRM_MODE_DPMS_ON;
7348                         drm_connector_property_set_value(connector,
7349                                                          dpms_property,
7350                                                          DRM_MODE_DPMS_ON);
7351
7352                         intel_encoder = to_intel_encoder(connector->encoder);
7353                         intel_encoder->connectors_active = true;
7354                 }
7355         }
7356
7357 }
7358
7359 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7360         list_for_each_entry((intel_crtc), \
7361                             &(dev)->mode_config.crtc_list, \
7362                             base.head) \
7363                 if (mask & (1 <<(intel_crtc)->pipe)) \
7364
7365 void
7366 intel_modeset_check_state(struct drm_device *dev)
7367 {
7368         struct intel_crtc *crtc;
7369         struct intel_encoder *encoder;
7370         struct intel_connector *connector;
7371
7372         list_for_each_entry(connector, &dev->mode_config.connector_list,
7373                             base.head) {
7374                 /* This also checks the encoder/connector hw state with the
7375                  * ->get_hw_state callbacks. */
7376                 intel_connector_check_state(connector);
7377
7378                 WARN(&connector->new_encoder->base != connector->base.encoder,
7379                      "connector's staged encoder doesn't match current encoder\n");
7380         }
7381
7382         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7383                             base.head) {
7384                 bool enabled = false;
7385                 bool active = false;
7386                 enum pipe pipe, tracked_pipe;
7387
7388                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7389                               encoder->base.base.id,
7390                               drm_get_encoder_name(&encoder->base));
7391
7392                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7393                      "encoder's stage crtc doesn't match current crtc\n");
7394                 WARN(encoder->connectors_active && !encoder->base.crtc,
7395                      "encoder's active_connectors set, but no crtc\n");
7396
7397                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7398                                     base.head) {
7399                         if (connector->base.encoder != &encoder->base)
7400                                 continue;
7401                         enabled = true;
7402                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7403                                 active = true;
7404                 }
7405                 WARN(!!encoder->base.crtc != enabled,
7406                      "encoder's enabled state mismatch "
7407                      "(expected %i, found %i)\n",
7408                      !!encoder->base.crtc, enabled);
7409                 WARN(active && !encoder->base.crtc,
7410                      "active encoder with no crtc\n");
7411
7412                 WARN(encoder->connectors_active != active,
7413                      "encoder's computed active state doesn't match tracked active state "
7414                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7415
7416                 active = encoder->get_hw_state(encoder, &pipe);
7417                 WARN(active != encoder->connectors_active,
7418                      "encoder's hw state doesn't match sw tracking "
7419                      "(expected %i, found %i)\n",
7420                      encoder->connectors_active, active);
7421
7422                 if (!encoder->base.crtc)
7423                         continue;
7424
7425                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7426                 WARN(active && pipe != tracked_pipe,
7427                      "active encoder's pipe doesn't match"
7428                      "(expected %i, found %i)\n",
7429                      tracked_pipe, pipe);
7430
7431         }
7432
7433         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7434                             base.head) {
7435                 bool enabled = false;
7436                 bool active = false;
7437
7438                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7439                               crtc->base.base.id);
7440
7441                 WARN(crtc->active && !crtc->base.enabled,
7442                      "active crtc, but not enabled in sw tracking\n");
7443
7444                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7445                                     base.head) {
7446                         if (encoder->base.crtc != &crtc->base)
7447                                 continue;
7448                         enabled = true;
7449                         if (encoder->connectors_active)
7450                                 active = true;
7451                 }
7452                 WARN(active != crtc->active,
7453                      "crtc's computed active state doesn't match tracked active state "
7454                      "(expected %i, found %i)\n", active, crtc->active);
7455                 WARN(enabled != crtc->base.enabled,
7456                      "crtc's computed enabled state doesn't match tracked enabled state "
7457                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7458
7459                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7460         }
7461 }
7462
7463 bool intel_set_mode(struct drm_crtc *crtc,
7464                     struct drm_display_mode *mode,
7465                     int x, int y, struct drm_framebuffer *fb)
7466 {
7467         struct drm_device *dev = crtc->dev;
7468         drm_i915_private_t *dev_priv = dev->dev_private;
7469         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7470         struct drm_encoder_helper_funcs *encoder_funcs;
7471         struct drm_encoder *encoder;
7472         struct intel_crtc *intel_crtc;
7473         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7474         bool ret = true;
7475
7476         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7477                                      &prepare_pipes, &disable_pipes);
7478
7479         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7480                       modeset_pipes, prepare_pipes, disable_pipes);
7481
7482         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7483                 intel_crtc_disable(&intel_crtc->base);
7484
7485         saved_hwmode = crtc->hwmode;
7486         saved_mode = crtc->mode;
7487
7488         /* Hack: Because we don't (yet) support global modeset on multiple
7489          * crtcs, we don't keep track of the new mode for more than one crtc.
7490          * Hence simply check whether any bit is set in modeset_pipes in all the
7491          * pieces of code that are not yet converted to deal with mutliple crtcs
7492          * changing their mode at the same time. */
7493         adjusted_mode = NULL;
7494         if (modeset_pipes) {
7495                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7496                 if (IS_ERR(adjusted_mode)) {
7497                         return false;
7498                 }
7499         }
7500
7501         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7502                 if (intel_crtc->base.enabled)
7503                         dev_priv->display.crtc_disable(&intel_crtc->base);
7504         }
7505
7506         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7507          * to set it here already despite that we pass it down the callchain.
7508          */
7509         if (modeset_pipes)
7510                 crtc->mode = *mode;
7511
7512         /* Only after disabling all output pipelines that will be changed can we
7513          * update the the output configuration. */
7514         intel_modeset_update_state(dev, prepare_pipes);
7515
7516         /* Set up the DPLL and any encoders state that needs to adjust or depend
7517          * on the DPLL.
7518          */
7519         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7520                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7521                                            mode, adjusted_mode,
7522                                            x, y, fb);
7523                 if (!ret)
7524                     goto done;
7525
7526                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7527
7528                         if (encoder->crtc != &intel_crtc->base)
7529                                 continue;
7530
7531                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7532                                 encoder->base.id, drm_get_encoder_name(encoder),
7533                                 mode->base.id, mode->name);
7534                         encoder_funcs = encoder->helper_private;
7535                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7536                 }
7537         }
7538
7539         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7540         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7541                 dev_priv->display.crtc_enable(&intel_crtc->base);
7542
7543         if (modeset_pipes) {
7544                 /* Store real post-adjustment hardware mode. */
7545                 crtc->hwmode = *adjusted_mode;
7546
7547                 /* Calculate and store various constants which
7548                  * are later needed by vblank and swap-completion
7549                  * timestamping. They are derived from true hwmode.
7550                  */
7551                 drm_calc_timestamping_constants(crtc);
7552         }
7553
7554         /* FIXME: add subpixel order */
7555 done:
7556         drm_mode_destroy(dev, adjusted_mode);
7557         if (!ret && crtc->enabled) {
7558                 crtc->hwmode = saved_hwmode;
7559                 crtc->mode = saved_mode;
7560         } else {
7561                 intel_modeset_check_state(dev);
7562         }
7563
7564         return ret;
7565 }
7566
7567 #undef for_each_intel_crtc_masked
7568
7569 static void intel_set_config_free(struct intel_set_config *config)
7570 {
7571         if (!config)
7572                 return;
7573
7574         kfree(config->save_connector_encoders);
7575         kfree(config->save_encoder_crtcs);
7576         kfree(config);
7577 }
7578
7579 static int intel_set_config_save_state(struct drm_device *dev,
7580                                        struct intel_set_config *config)
7581 {
7582         struct drm_encoder *encoder;
7583         struct drm_connector *connector;
7584         int count;
7585
7586         config->save_encoder_crtcs =
7587                 kcalloc(dev->mode_config.num_encoder,
7588                         sizeof(struct drm_crtc *), GFP_KERNEL);
7589         if (!config->save_encoder_crtcs)
7590                 return -ENOMEM;
7591
7592         config->save_connector_encoders =
7593                 kcalloc(dev->mode_config.num_connector,
7594                         sizeof(struct drm_encoder *), GFP_KERNEL);
7595         if (!config->save_connector_encoders)
7596                 return -ENOMEM;
7597
7598         /* Copy data. Note that driver private data is not affected.
7599          * Should anything bad happen only the expected state is
7600          * restored, not the drivers personal bookkeeping.
7601          */
7602         count = 0;
7603         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7604                 config->save_encoder_crtcs[count++] = encoder->crtc;
7605         }
7606
7607         count = 0;
7608         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7609                 config->save_connector_encoders[count++] = connector->encoder;
7610         }
7611
7612         return 0;
7613 }
7614
7615 static void intel_set_config_restore_state(struct drm_device *dev,
7616                                            struct intel_set_config *config)
7617 {
7618         struct intel_encoder *encoder;
7619         struct intel_connector *connector;
7620         int count;
7621
7622         count = 0;
7623         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7624                 encoder->new_crtc =
7625                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7626         }
7627
7628         count = 0;
7629         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7630                 connector->new_encoder =
7631                         to_intel_encoder(config->save_connector_encoders[count++]);
7632         }
7633 }
7634
7635 static void
7636 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7637                                       struct intel_set_config *config)
7638 {
7639
7640         /* We should be able to check here if the fb has the same properties
7641          * and then just flip_or_move it */
7642         if (set->crtc->fb != set->fb) {
7643                 /* If we have no fb then treat it as a full mode set */
7644                 if (set->crtc->fb == NULL) {
7645                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7646                         config->mode_changed = true;
7647                 } else if (set->fb == NULL) {
7648                         config->mode_changed = true;
7649                 } else if (set->fb->depth != set->crtc->fb->depth) {
7650                         config->mode_changed = true;
7651                 } else if (set->fb->bits_per_pixel !=
7652                            set->crtc->fb->bits_per_pixel) {
7653                         config->mode_changed = true;
7654                 } else
7655                         config->fb_changed = true;
7656         }
7657
7658         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7659                 config->fb_changed = true;
7660
7661         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7662                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7663                 drm_mode_debug_printmodeline(&set->crtc->mode);
7664                 drm_mode_debug_printmodeline(set->mode);
7665                 config->mode_changed = true;
7666         }
7667 }
7668
7669 static int
7670 intel_modeset_stage_output_state(struct drm_device *dev,
7671                                  struct drm_mode_set *set,
7672                                  struct intel_set_config *config)
7673 {
7674         struct drm_crtc *new_crtc;
7675         struct intel_connector *connector;
7676         struct intel_encoder *encoder;
7677         int count, ro;
7678
7679         /* The upper layers ensure that we either disabl a crtc or have a list
7680          * of connectors. For paranoia, double-check this. */
7681         WARN_ON(!set->fb && (set->num_connectors != 0));
7682         WARN_ON(set->fb && (set->num_connectors == 0));
7683
7684         count = 0;
7685         list_for_each_entry(connector, &dev->mode_config.connector_list,
7686                             base.head) {
7687                 /* Otherwise traverse passed in connector list and get encoders
7688                  * for them. */
7689                 for (ro = 0; ro < set->num_connectors; ro++) {
7690                         if (set->connectors[ro] == &connector->base) {
7691                                 connector->new_encoder = connector->encoder;
7692                                 break;
7693                         }
7694                 }
7695
7696                 /* If we disable the crtc, disable all its connectors. Also, if
7697                  * the connector is on the changing crtc but not on the new
7698                  * connector list, disable it. */
7699                 if ((!set->fb || ro == set->num_connectors) &&
7700                     connector->base.encoder &&
7701                     connector->base.encoder->crtc == set->crtc) {
7702                         connector->new_encoder = NULL;
7703
7704                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7705                                 connector->base.base.id,
7706                                 drm_get_connector_name(&connector->base));
7707                 }
7708
7709
7710                 if (&connector->new_encoder->base != connector->base.encoder) {
7711                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7712                         config->mode_changed = true;
7713                 }
7714
7715                 /* Disable all disconnected encoders. */
7716                 if (connector->base.status == connector_status_disconnected)
7717                         connector->new_encoder = NULL;
7718         }
7719         /* connector->new_encoder is now updated for all connectors. */
7720
7721         /* Update crtc of enabled connectors. */
7722         count = 0;
7723         list_for_each_entry(connector, &dev->mode_config.connector_list,
7724                             base.head) {
7725                 if (!connector->new_encoder)
7726                         continue;
7727
7728                 new_crtc = connector->new_encoder->base.crtc;
7729
7730                 for (ro = 0; ro < set->num_connectors; ro++) {
7731                         if (set->connectors[ro] == &connector->base)
7732                                 new_crtc = set->crtc;
7733                 }
7734
7735                 /* Make sure the new CRTC will work with the encoder */
7736                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7737                                            new_crtc)) {
7738                         return -EINVAL;
7739                 }
7740                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7741
7742                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7743                         connector->base.base.id,
7744                         drm_get_connector_name(&connector->base),
7745                         new_crtc->base.id);
7746         }
7747
7748         /* Check for any encoders that needs to be disabled. */
7749         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7750                             base.head) {
7751                 list_for_each_entry(connector,
7752                                     &dev->mode_config.connector_list,
7753                                     base.head) {
7754                         if (connector->new_encoder == encoder) {
7755                                 WARN_ON(!connector->new_encoder->new_crtc);
7756
7757                                 goto next_encoder;
7758                         }
7759                 }
7760                 encoder->new_crtc = NULL;
7761 next_encoder:
7762                 /* Only now check for crtc changes so we don't miss encoders
7763                  * that will be disabled. */
7764                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7765                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7766                         config->mode_changed = true;
7767                 }
7768         }
7769         /* Now we've also updated encoder->new_crtc for all encoders. */
7770
7771         return 0;
7772 }
7773
7774 static int intel_crtc_set_config(struct drm_mode_set *set)
7775 {
7776         struct drm_device *dev;
7777         struct drm_mode_set save_set;
7778         struct intel_set_config *config;
7779         int ret;
7780
7781         BUG_ON(!set);
7782         BUG_ON(!set->crtc);
7783         BUG_ON(!set->crtc->helper_private);
7784
7785         if (!set->mode)
7786                 set->fb = NULL;
7787
7788         /* The fb helper likes to play gross jokes with ->mode_set_config.
7789          * Unfortunately the crtc helper doesn't do much at all for this case,
7790          * so we have to cope with this madness until the fb helper is fixed up. */
7791         if (set->fb && set->num_connectors == 0)
7792                 return 0;
7793
7794         if (set->fb) {
7795                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7796                                 set->crtc->base.id, set->fb->base.id,
7797                                 (int)set->num_connectors, set->x, set->y);
7798         } else {
7799                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7800         }
7801
7802         dev = set->crtc->dev;
7803
7804         ret = -ENOMEM;
7805         config = kzalloc(sizeof(*config), GFP_KERNEL);
7806         if (!config)
7807                 goto out_config;
7808
7809         ret = intel_set_config_save_state(dev, config);
7810         if (ret)
7811                 goto out_config;
7812
7813         save_set.crtc = set->crtc;
7814         save_set.mode = &set->crtc->mode;
7815         save_set.x = set->crtc->x;
7816         save_set.y = set->crtc->y;
7817         save_set.fb = set->crtc->fb;
7818
7819         /* Compute whether we need a full modeset, only an fb base update or no
7820          * change at all. In the future we might also check whether only the
7821          * mode changed, e.g. for LVDS where we only change the panel fitter in
7822          * such cases. */
7823         intel_set_config_compute_mode_changes(set, config);
7824
7825         ret = intel_modeset_stage_output_state(dev, set, config);
7826         if (ret)
7827                 goto fail;
7828
7829         if (config->mode_changed) {
7830                 if (set->mode) {
7831                         DRM_DEBUG_KMS("attempting to set mode from"
7832                                         " userspace\n");
7833                         drm_mode_debug_printmodeline(set->mode);
7834                 }
7835
7836                 if (!intel_set_mode(set->crtc, set->mode,
7837                                     set->x, set->y, set->fb)) {
7838                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7839                                   set->crtc->base.id);
7840                         ret = -EINVAL;
7841                         goto fail;
7842                 }
7843         } else if (config->fb_changed) {
7844                 ret = intel_pipe_set_base(set->crtc,
7845                                           set->x, set->y, set->fb);
7846         }
7847
7848         intel_set_config_free(config);
7849
7850         return 0;
7851
7852 fail:
7853         intel_set_config_restore_state(dev, config);
7854
7855         /* Try to restore the config */
7856         if (config->mode_changed &&
7857             !intel_set_mode(save_set.crtc, save_set.mode,
7858                             save_set.x, save_set.y, save_set.fb))
7859                 DRM_ERROR("failed to restore config after modeset failure\n");
7860
7861 out_config:
7862         intel_set_config_free(config);
7863         return ret;
7864 }
7865
7866 static const struct drm_crtc_funcs intel_crtc_funcs = {
7867         .cursor_set = intel_crtc_cursor_set,
7868         .cursor_move = intel_crtc_cursor_move,
7869         .gamma_set = intel_crtc_gamma_set,
7870         .set_config = intel_crtc_set_config,
7871         .destroy = intel_crtc_destroy,
7872         .page_flip = intel_crtc_page_flip,
7873 };
7874
7875 static void intel_cpu_pll_init(struct drm_device *dev)
7876 {
7877         if (IS_HASWELL(dev))
7878                 intel_ddi_pll_init(dev);
7879 }
7880
7881 static void intel_pch_pll_init(struct drm_device *dev)
7882 {
7883         drm_i915_private_t *dev_priv = dev->dev_private;
7884         int i;
7885
7886         if (dev_priv->num_pch_pll == 0) {
7887                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7888                 return;
7889         }
7890
7891         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7892                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7893                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7894                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7895         }
7896 }
7897
7898 static void intel_crtc_init(struct drm_device *dev, int pipe)
7899 {
7900         drm_i915_private_t *dev_priv = dev->dev_private;
7901         struct intel_crtc *intel_crtc;
7902         int i;
7903
7904         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7905         if (intel_crtc == NULL)
7906                 return;
7907
7908         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7909
7910         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7911         for (i = 0; i < 256; i++) {
7912                 intel_crtc->lut_r[i] = i;
7913                 intel_crtc->lut_g[i] = i;
7914                 intel_crtc->lut_b[i] = i;
7915         }
7916
7917         /* Swap pipes & planes for FBC on pre-965 */
7918         intel_crtc->pipe = pipe;
7919         intel_crtc->plane = pipe;
7920         intel_crtc->cpu_transcoder = pipe;
7921         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7922                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7923                 intel_crtc->plane = !pipe;
7924         }
7925
7926         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7927                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7928         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7929         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7930
7931         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7932
7933         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7934 }
7935
7936 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7937                                 struct drm_file *file)
7938 {
7939         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7940         struct drm_mode_object *drmmode_obj;
7941         struct intel_crtc *crtc;
7942
7943         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7944                 return -ENODEV;
7945
7946         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7947                         DRM_MODE_OBJECT_CRTC);
7948
7949         if (!drmmode_obj) {
7950                 DRM_ERROR("no such CRTC id\n");
7951                 return -EINVAL;
7952         }
7953
7954         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7955         pipe_from_crtc_id->pipe = crtc->pipe;
7956
7957         return 0;
7958 }
7959
7960 static int intel_encoder_clones(struct intel_encoder *encoder)
7961 {
7962         struct drm_device *dev = encoder->base.dev;
7963         struct intel_encoder *source_encoder;
7964         int index_mask = 0;
7965         int entry = 0;
7966
7967         list_for_each_entry(source_encoder,
7968                             &dev->mode_config.encoder_list, base.head) {
7969
7970                 if (encoder == source_encoder)
7971                         index_mask |= (1 << entry);
7972
7973                 /* Intel hw has only one MUX where enocoders could be cloned. */
7974                 if (encoder->cloneable && source_encoder->cloneable)
7975                         index_mask |= (1 << entry);
7976
7977                 entry++;
7978         }
7979
7980         return index_mask;
7981 }
7982
7983 static bool has_edp_a(struct drm_device *dev)
7984 {
7985         struct drm_i915_private *dev_priv = dev->dev_private;
7986
7987         if (!IS_MOBILE(dev))
7988                 return false;
7989
7990         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7991                 return false;
7992
7993         if (IS_GEN5(dev) &&
7994             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7995                 return false;
7996
7997         return true;
7998 }
7999
8000 static void intel_setup_outputs(struct drm_device *dev)
8001 {
8002         struct drm_i915_private *dev_priv = dev->dev_private;
8003         struct intel_encoder *encoder;
8004         bool dpd_is_edp = false;
8005         bool has_lvds;
8006
8007         has_lvds = intel_lvds_init(dev);
8008         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8009                 /* disable the panel fitter on everything but LVDS */
8010                 I915_WRITE(PFIT_CONTROL, 0);
8011         }
8012
8013         if (HAS_PCH_SPLIT(dev)) {
8014                 dpd_is_edp = intel_dpd_is_edp(dev);
8015
8016                 if (has_edp_a(dev))
8017                         intel_dp_init(dev, DP_A, PORT_A);
8018
8019                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8020                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8021         }
8022
8023         intel_crt_init(dev);
8024
8025         if (IS_HASWELL(dev)) {
8026                 int found;
8027
8028                 /* Haswell uses DDI functions to detect digital outputs */
8029                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8030                 /* DDI A only supports eDP */
8031                 if (found)
8032                         intel_ddi_init(dev, PORT_A);
8033
8034                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8035                  * register */
8036                 found = I915_READ(SFUSE_STRAP);
8037
8038                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8039                         intel_ddi_init(dev, PORT_B);
8040                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8041                         intel_ddi_init(dev, PORT_C);
8042                 if (found & SFUSE_STRAP_DDID_DETECTED)
8043                         intel_ddi_init(dev, PORT_D);
8044         } else if (HAS_PCH_SPLIT(dev)) {
8045                 int found;
8046
8047                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8048                         /* PCH SDVOB multiplex with HDMIB */
8049                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8050                         if (!found)
8051                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8052                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8053                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8054                 }
8055
8056                 if (I915_READ(HDMIC) & PORT_DETECTED)
8057                         intel_hdmi_init(dev, HDMIC, PORT_C);
8058
8059                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8060                         intel_hdmi_init(dev, HDMID, PORT_D);
8061
8062                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8063                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8064
8065                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8066                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8067         } else if (IS_VALLEYVIEW(dev)) {
8068                 int found;
8069
8070                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8071                 if (I915_READ(DP_C) & DP_DETECTED)
8072                         intel_dp_init(dev, DP_C, PORT_C);
8073
8074                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8075                         /* SDVOB multiplex with HDMIB */
8076                         found = intel_sdvo_init(dev, SDVOB, true);
8077                         if (!found)
8078                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8079                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8080                                 intel_dp_init(dev, DP_B, PORT_B);
8081                 }
8082
8083                 if (I915_READ(SDVOC) & PORT_DETECTED)
8084                         intel_hdmi_init(dev, SDVOC, PORT_C);
8085
8086         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8087                 bool found = false;
8088
8089                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8090                         DRM_DEBUG_KMS("probing SDVOB\n");
8091                         found = intel_sdvo_init(dev, SDVOB, true);
8092                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8093                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8094                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8095                         }
8096
8097                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8098                                 DRM_DEBUG_KMS("probing DP_B\n");
8099                                 intel_dp_init(dev, DP_B, PORT_B);
8100                         }
8101                 }
8102
8103                 /* Before G4X SDVOC doesn't have its own detect register */
8104
8105                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8106                         DRM_DEBUG_KMS("probing SDVOC\n");
8107                         found = intel_sdvo_init(dev, SDVOC, false);
8108                 }
8109
8110                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8111
8112                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8113                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8114                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8115                         }
8116                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8117                                 DRM_DEBUG_KMS("probing DP_C\n");
8118                                 intel_dp_init(dev, DP_C, PORT_C);
8119                         }
8120                 }
8121
8122                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8123                     (I915_READ(DP_D) & DP_DETECTED)) {
8124                         DRM_DEBUG_KMS("probing DP_D\n");
8125                         intel_dp_init(dev, DP_D, PORT_D);
8126                 }
8127         } else if (IS_GEN2(dev))
8128                 intel_dvo_init(dev);
8129
8130         if (SUPPORTS_TV(dev))
8131                 intel_tv_init(dev);
8132
8133         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8134                 encoder->base.possible_crtcs = encoder->crtc_mask;
8135                 encoder->base.possible_clones =
8136                         intel_encoder_clones(encoder);
8137         }
8138
8139         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8140                 ironlake_init_pch_refclk(dev);
8141 }
8142
8143 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8144 {
8145         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8146
8147         drm_framebuffer_cleanup(fb);
8148         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8149
8150         kfree(intel_fb);
8151 }
8152
8153 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8154                                                 struct drm_file *file,
8155                                                 unsigned int *handle)
8156 {
8157         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8158         struct drm_i915_gem_object *obj = intel_fb->obj;
8159
8160         return drm_gem_handle_create(file, &obj->base, handle);
8161 }
8162
8163 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8164         .destroy = intel_user_framebuffer_destroy,
8165         .create_handle = intel_user_framebuffer_create_handle,
8166 };
8167
8168 int intel_framebuffer_init(struct drm_device *dev,
8169                            struct intel_framebuffer *intel_fb,
8170                            struct drm_mode_fb_cmd2 *mode_cmd,
8171                            struct drm_i915_gem_object *obj)
8172 {
8173         int ret;
8174
8175         if (obj->tiling_mode == I915_TILING_Y)
8176                 return -EINVAL;
8177
8178         if (mode_cmd->pitches[0] & 63)
8179                 return -EINVAL;
8180
8181         switch (mode_cmd->pixel_format) {
8182         case DRM_FORMAT_RGB332:
8183         case DRM_FORMAT_RGB565:
8184         case DRM_FORMAT_XRGB8888:
8185         case DRM_FORMAT_XBGR8888:
8186         case DRM_FORMAT_ARGB8888:
8187         case DRM_FORMAT_XRGB2101010:
8188         case DRM_FORMAT_ARGB2101010:
8189                 /* RGB formats are common across chipsets */
8190                 break;
8191         case DRM_FORMAT_YUYV:
8192         case DRM_FORMAT_UYVY:
8193         case DRM_FORMAT_YVYU:
8194         case DRM_FORMAT_VYUY:
8195                 break;
8196         default:
8197                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8198                                 mode_cmd->pixel_format);
8199                 return -EINVAL;
8200         }
8201
8202         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8203         if (ret) {
8204                 DRM_ERROR("framebuffer init failed %d\n", ret);
8205                 return ret;
8206         }
8207
8208         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8209         intel_fb->obj = obj;
8210         return 0;
8211 }
8212
8213 static struct drm_framebuffer *
8214 intel_user_framebuffer_create(struct drm_device *dev,
8215                               struct drm_file *filp,
8216                               struct drm_mode_fb_cmd2 *mode_cmd)
8217 {
8218         struct drm_i915_gem_object *obj;
8219
8220         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8221                                                 mode_cmd->handles[0]));
8222         if (&obj->base == NULL)
8223                 return ERR_PTR(-ENOENT);
8224
8225         return intel_framebuffer_create(dev, mode_cmd, obj);
8226 }
8227
8228 static const struct drm_mode_config_funcs intel_mode_funcs = {
8229         .fb_create = intel_user_framebuffer_create,
8230         .output_poll_changed = intel_fb_output_poll_changed,
8231 };
8232
8233 /* Set up chip specific display functions */
8234 static void intel_init_display(struct drm_device *dev)
8235 {
8236         struct drm_i915_private *dev_priv = dev->dev_private;
8237
8238         /* We always want a DPMS function */
8239         if (IS_HASWELL(dev)) {
8240                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8241                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8242                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8243                 dev_priv->display.off = haswell_crtc_off;
8244                 dev_priv->display.update_plane = ironlake_update_plane;
8245         } else if (HAS_PCH_SPLIT(dev)) {
8246                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8247                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8248                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8249                 dev_priv->display.off = ironlake_crtc_off;
8250                 dev_priv->display.update_plane = ironlake_update_plane;
8251         } else {
8252                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8253                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8254                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8255                 dev_priv->display.off = i9xx_crtc_off;
8256                 dev_priv->display.update_plane = i9xx_update_plane;
8257         }
8258
8259         /* Returns the core display clock speed */
8260         if (IS_VALLEYVIEW(dev))
8261                 dev_priv->display.get_display_clock_speed =
8262                         valleyview_get_display_clock_speed;
8263         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8264                 dev_priv->display.get_display_clock_speed =
8265                         i945_get_display_clock_speed;
8266         else if (IS_I915G(dev))
8267                 dev_priv->display.get_display_clock_speed =
8268                         i915_get_display_clock_speed;
8269         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8270                 dev_priv->display.get_display_clock_speed =
8271                         i9xx_misc_get_display_clock_speed;
8272         else if (IS_I915GM(dev))
8273                 dev_priv->display.get_display_clock_speed =
8274                         i915gm_get_display_clock_speed;
8275         else if (IS_I865G(dev))
8276                 dev_priv->display.get_display_clock_speed =
8277                         i865_get_display_clock_speed;
8278         else if (IS_I85X(dev))
8279                 dev_priv->display.get_display_clock_speed =
8280                         i855_get_display_clock_speed;
8281         else /* 852, 830 */
8282                 dev_priv->display.get_display_clock_speed =
8283                         i830_get_display_clock_speed;
8284
8285         if (HAS_PCH_SPLIT(dev)) {
8286                 if (IS_GEN5(dev)) {
8287                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8288                         dev_priv->display.write_eld = ironlake_write_eld;
8289                 } else if (IS_GEN6(dev)) {
8290                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8291                         dev_priv->display.write_eld = ironlake_write_eld;
8292                 } else if (IS_IVYBRIDGE(dev)) {
8293                         /* FIXME: detect B0+ stepping and use auto training */
8294                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8295                         dev_priv->display.write_eld = ironlake_write_eld;
8296                 } else if (IS_HASWELL(dev)) {
8297                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8298                         dev_priv->display.write_eld = haswell_write_eld;
8299                 } else
8300                         dev_priv->display.update_wm = NULL;
8301         } else if (IS_G4X(dev)) {
8302                 dev_priv->display.write_eld = g4x_write_eld;
8303         }
8304
8305         /* Default just returns -ENODEV to indicate unsupported */
8306         dev_priv->display.queue_flip = intel_default_queue_flip;
8307
8308         switch (INTEL_INFO(dev)->gen) {
8309         case 2:
8310                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8311                 break;
8312
8313         case 3:
8314                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8315                 break;
8316
8317         case 4:
8318         case 5:
8319                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8320                 break;
8321
8322         case 6:
8323                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8324                 break;
8325         case 7:
8326                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8327                 break;
8328         }
8329 }
8330
8331 /*
8332  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8333  * resume, or other times.  This quirk makes sure that's the case for
8334  * affected systems.
8335  */
8336 static void quirk_pipea_force(struct drm_device *dev)
8337 {
8338         struct drm_i915_private *dev_priv = dev->dev_private;
8339
8340         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8341         DRM_INFO("applying pipe a force quirk\n");
8342 }
8343
8344 /*
8345  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8346  */
8347 static void quirk_ssc_force_disable(struct drm_device *dev)
8348 {
8349         struct drm_i915_private *dev_priv = dev->dev_private;
8350         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8351         DRM_INFO("applying lvds SSC disable quirk\n");
8352 }
8353
8354 /*
8355  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8356  * brightness value
8357  */
8358 static void quirk_invert_brightness(struct drm_device *dev)
8359 {
8360         struct drm_i915_private *dev_priv = dev->dev_private;
8361         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8362         DRM_INFO("applying inverted panel brightness quirk\n");
8363 }
8364
8365 struct intel_quirk {
8366         int device;
8367         int subsystem_vendor;
8368         int subsystem_device;
8369         void (*hook)(struct drm_device *dev);
8370 };
8371
8372 static struct intel_quirk intel_quirks[] = {
8373         /* HP Mini needs pipe A force quirk (LP: #322104) */
8374         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8375
8376         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8377         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8378
8379         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8380         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8381
8382         /* 830/845 need to leave pipe A & dpll A up */
8383         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8384         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8385
8386         /* Lenovo U160 cannot use SSC on LVDS */
8387         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8388
8389         /* Sony Vaio Y cannot use SSC on LVDS */
8390         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8391
8392         /* Acer Aspire 5734Z must invert backlight brightness */
8393         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8394 };
8395
8396 static void intel_init_quirks(struct drm_device *dev)
8397 {
8398         struct pci_dev *d = dev->pdev;
8399         int i;
8400
8401         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8402                 struct intel_quirk *q = &intel_quirks[i];
8403
8404                 if (d->device == q->device &&
8405                     (d->subsystem_vendor == q->subsystem_vendor ||
8406                      q->subsystem_vendor == PCI_ANY_ID) &&
8407                     (d->subsystem_device == q->subsystem_device ||
8408                      q->subsystem_device == PCI_ANY_ID))
8409                         q->hook(dev);
8410         }
8411 }
8412
8413 /* Disable the VGA plane that we never use */
8414 static void i915_disable_vga(struct drm_device *dev)
8415 {
8416         struct drm_i915_private *dev_priv = dev->dev_private;
8417         u8 sr1;
8418         u32 vga_reg;
8419
8420         if (HAS_PCH_SPLIT(dev))
8421                 vga_reg = CPU_VGACNTRL;
8422         else
8423                 vga_reg = VGACNTRL;
8424
8425         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8426         outb(SR01, VGA_SR_INDEX);
8427         sr1 = inb(VGA_SR_DATA);
8428         outb(sr1 | 1<<5, VGA_SR_DATA);
8429         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8430         udelay(300);
8431
8432         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8433         POSTING_READ(vga_reg);
8434 }
8435
8436 void intel_modeset_init_hw(struct drm_device *dev)
8437 {
8438         /* We attempt to init the necessary power wells early in the initialization
8439          * time, so the subsystems that expect power to be enabled can work.
8440          */
8441         intel_init_power_wells(dev);
8442
8443         intel_prepare_ddi(dev);
8444
8445         intel_init_clock_gating(dev);
8446
8447         mutex_lock(&dev->struct_mutex);
8448         intel_enable_gt_powersave(dev);
8449         mutex_unlock(&dev->struct_mutex);
8450 }
8451
8452 void intel_modeset_init(struct drm_device *dev)
8453 {
8454         struct drm_i915_private *dev_priv = dev->dev_private;
8455         int i, ret;
8456
8457         drm_mode_config_init(dev);
8458
8459         dev->mode_config.min_width = 0;
8460         dev->mode_config.min_height = 0;
8461
8462         dev->mode_config.preferred_depth = 24;
8463         dev->mode_config.prefer_shadow = 1;
8464
8465         dev->mode_config.funcs = &intel_mode_funcs;
8466
8467         intel_init_quirks(dev);
8468
8469         intel_init_pm(dev);
8470
8471         intel_init_display(dev);
8472
8473         if (IS_GEN2(dev)) {
8474                 dev->mode_config.max_width = 2048;
8475                 dev->mode_config.max_height = 2048;
8476         } else if (IS_GEN3(dev)) {
8477                 dev->mode_config.max_width = 4096;
8478                 dev->mode_config.max_height = 4096;
8479         } else {
8480                 dev->mode_config.max_width = 8192;
8481                 dev->mode_config.max_height = 8192;
8482         }
8483         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8484
8485         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8486                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8487
8488         for (i = 0; i < dev_priv->num_pipe; i++) {
8489                 intel_crtc_init(dev, i);
8490                 ret = intel_plane_init(dev, i);
8491                 if (ret)
8492                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8493         }
8494
8495         intel_cpu_pll_init(dev);
8496         intel_pch_pll_init(dev);
8497
8498         /* Just disable it once at startup */
8499         i915_disable_vga(dev);
8500         intel_setup_outputs(dev);
8501 }
8502
8503 static void
8504 intel_connector_break_all_links(struct intel_connector *connector)
8505 {
8506         connector->base.dpms = DRM_MODE_DPMS_OFF;
8507         connector->base.encoder = NULL;
8508         connector->encoder->connectors_active = false;
8509         connector->encoder->base.crtc = NULL;
8510 }
8511
8512 static void intel_enable_pipe_a(struct drm_device *dev)
8513 {
8514         struct intel_connector *connector;
8515         struct drm_connector *crt = NULL;
8516         struct intel_load_detect_pipe load_detect_temp;
8517
8518         /* We can't just switch on the pipe A, we need to set things up with a
8519          * proper mode and output configuration. As a gross hack, enable pipe A
8520          * by enabling the load detect pipe once. */
8521         list_for_each_entry(connector,
8522                             &dev->mode_config.connector_list,
8523                             base.head) {
8524                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8525                         crt = &connector->base;
8526                         break;
8527                 }
8528         }
8529
8530         if (!crt)
8531                 return;
8532
8533         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8534                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8535
8536
8537 }
8538
8539 static bool
8540 intel_check_plane_mapping(struct intel_crtc *crtc)
8541 {
8542         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8543         u32 reg, val;
8544
8545         if (dev_priv->num_pipe == 1)
8546                 return true;
8547
8548         reg = DSPCNTR(!crtc->plane);
8549         val = I915_READ(reg);
8550
8551         if ((val & DISPLAY_PLANE_ENABLE) &&
8552             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8553                 return false;
8554
8555         return true;
8556 }
8557
8558 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8559 {
8560         struct drm_device *dev = crtc->base.dev;
8561         struct drm_i915_private *dev_priv = dev->dev_private;
8562         u32 reg;
8563
8564         /* Clear any frame start delays used for debugging left by the BIOS */
8565         reg = PIPECONF(crtc->pipe);
8566         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8567
8568         /* We need to sanitize the plane -> pipe mapping first because this will
8569          * disable the crtc (and hence change the state) if it is wrong. Note
8570          * that gen4+ has a fixed plane -> pipe mapping.  */
8571         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8572                 struct intel_connector *connector;
8573                 bool plane;
8574
8575                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8576                               crtc->base.base.id);
8577
8578                 /* Pipe has the wrong plane attached and the plane is active.
8579                  * Temporarily change the plane mapping and disable everything
8580                  * ...  */
8581                 plane = crtc->plane;
8582                 crtc->plane = !plane;
8583                 dev_priv->display.crtc_disable(&crtc->base);
8584                 crtc->plane = plane;
8585
8586                 /* ... and break all links. */
8587                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8588                                     base.head) {
8589                         if (connector->encoder->base.crtc != &crtc->base)
8590                                 continue;
8591
8592                         intel_connector_break_all_links(connector);
8593                 }
8594
8595                 WARN_ON(crtc->active);
8596                 crtc->base.enabled = false;
8597         }
8598
8599         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8600             crtc->pipe == PIPE_A && !crtc->active) {
8601                 /* BIOS forgot to enable pipe A, this mostly happens after
8602                  * resume. Force-enable the pipe to fix this, the update_dpms
8603                  * call below we restore the pipe to the right state, but leave
8604                  * the required bits on. */
8605                 intel_enable_pipe_a(dev);
8606         }
8607
8608         /* Adjust the state of the output pipe according to whether we
8609          * have active connectors/encoders. */
8610         intel_crtc_update_dpms(&crtc->base);
8611
8612         if (crtc->active != crtc->base.enabled) {
8613                 struct intel_encoder *encoder;
8614
8615                 /* This can happen either due to bugs in the get_hw_state
8616                  * functions or because the pipe is force-enabled due to the
8617                  * pipe A quirk. */
8618                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8619                               crtc->base.base.id,
8620                               crtc->base.enabled ? "enabled" : "disabled",
8621                               crtc->active ? "enabled" : "disabled");
8622
8623                 crtc->base.enabled = crtc->active;
8624
8625                 /* Because we only establish the connector -> encoder ->
8626                  * crtc links if something is active, this means the
8627                  * crtc is now deactivated. Break the links. connector
8628                  * -> encoder links are only establish when things are
8629                  *  actually up, hence no need to break them. */
8630                 WARN_ON(crtc->active);
8631
8632                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8633                         WARN_ON(encoder->connectors_active);
8634                         encoder->base.crtc = NULL;
8635                 }
8636         }
8637 }
8638
8639 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8640 {
8641         struct intel_connector *connector;
8642         struct drm_device *dev = encoder->base.dev;
8643
8644         /* We need to check both for a crtc link (meaning that the
8645          * encoder is active and trying to read from a pipe) and the
8646          * pipe itself being active. */
8647         bool has_active_crtc = encoder->base.crtc &&
8648                 to_intel_crtc(encoder->base.crtc)->active;
8649
8650         if (encoder->connectors_active && !has_active_crtc) {
8651                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8652                               encoder->base.base.id,
8653                               drm_get_encoder_name(&encoder->base));
8654
8655                 /* Connector is active, but has no active pipe. This is
8656                  * fallout from our resume register restoring. Disable
8657                  * the encoder manually again. */
8658                 if (encoder->base.crtc) {
8659                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8660                                       encoder->base.base.id,
8661                                       drm_get_encoder_name(&encoder->base));
8662                         encoder->disable(encoder);
8663                 }
8664
8665                 /* Inconsistent output/port/pipe state happens presumably due to
8666                  * a bug in one of the get_hw_state functions. Or someplace else
8667                  * in our code, like the register restore mess on resume. Clamp
8668                  * things to off as a safer default. */
8669                 list_for_each_entry(connector,
8670                                     &dev->mode_config.connector_list,
8671                                     base.head) {
8672                         if (connector->encoder != encoder)
8673                                 continue;
8674
8675                         intel_connector_break_all_links(connector);
8676                 }
8677         }
8678         /* Enabled encoders without active connectors will be fixed in
8679          * the crtc fixup. */
8680 }
8681
8682 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8683  * and i915 state tracking structures. */
8684 void intel_modeset_setup_hw_state(struct drm_device *dev)
8685 {
8686         struct drm_i915_private *dev_priv = dev->dev_private;
8687         enum pipe pipe;
8688         u32 tmp;
8689         struct intel_crtc *crtc;
8690         struct intel_encoder *encoder;
8691         struct intel_connector *connector;
8692
8693         for_each_pipe(pipe) {
8694                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8695
8696                 tmp = I915_READ(PIPECONF(pipe));
8697                 if (tmp & PIPECONF_ENABLE)
8698                         crtc->active = true;
8699                 else
8700                         crtc->active = false;
8701
8702                 crtc->base.enabled = crtc->active;
8703
8704                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8705                               crtc->base.base.id,
8706                               crtc->active ? "enabled" : "disabled");
8707         }
8708
8709         if (IS_HASWELL(dev))
8710                 intel_ddi_setup_hw_pll_state(dev);
8711
8712         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8713                             base.head) {
8714                 pipe = 0;
8715
8716                 if (encoder->get_hw_state(encoder, &pipe)) {
8717                         encoder->base.crtc =
8718                                 dev_priv->pipe_to_crtc_mapping[pipe];
8719                 } else {
8720                         encoder->base.crtc = NULL;
8721                 }
8722
8723                 encoder->connectors_active = false;
8724                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8725                               encoder->base.base.id,
8726                               drm_get_encoder_name(&encoder->base),
8727                               encoder->base.crtc ? "enabled" : "disabled",
8728                               pipe);
8729         }
8730
8731         list_for_each_entry(connector, &dev->mode_config.connector_list,
8732                             base.head) {
8733                 if (connector->get_hw_state(connector)) {
8734                         connector->base.dpms = DRM_MODE_DPMS_ON;
8735                         connector->encoder->connectors_active = true;
8736                         connector->base.encoder = &connector->encoder->base;
8737                 } else {
8738                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8739                         connector->base.encoder = NULL;
8740                 }
8741                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8742                               connector->base.base.id,
8743                               drm_get_connector_name(&connector->base),
8744                               connector->base.encoder ? "enabled" : "disabled");
8745         }
8746
8747         /* HW state is read out, now we need to sanitize this mess. */
8748         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8749                             base.head) {
8750                 intel_sanitize_encoder(encoder);
8751         }
8752
8753         for_each_pipe(pipe) {
8754                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8755                 intel_sanitize_crtc(crtc);
8756         }
8757
8758         intel_modeset_update_staged_output_state(dev);
8759
8760         intel_modeset_check_state(dev);
8761
8762         drm_mode_config_reset(dev);
8763 }
8764
8765 void intel_modeset_gem_init(struct drm_device *dev)
8766 {
8767         intel_modeset_init_hw(dev);
8768
8769         intel_setup_overlay(dev);
8770
8771         intel_modeset_setup_hw_state(dev);
8772 }
8773
8774 void intel_modeset_cleanup(struct drm_device *dev)
8775 {
8776         struct drm_i915_private *dev_priv = dev->dev_private;
8777         struct drm_crtc *crtc;
8778         struct intel_crtc *intel_crtc;
8779
8780         drm_kms_helper_poll_fini(dev);
8781         mutex_lock(&dev->struct_mutex);
8782
8783         intel_unregister_dsm_handler();
8784
8785
8786         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8787                 /* Skip inactive CRTCs */
8788                 if (!crtc->fb)
8789                         continue;
8790
8791                 intel_crtc = to_intel_crtc(crtc);
8792                 intel_increase_pllclock(crtc);
8793         }
8794
8795         intel_disable_fbc(dev);
8796
8797         intel_disable_gt_powersave(dev);
8798
8799         ironlake_teardown_rc6(dev);
8800
8801         if (IS_VALLEYVIEW(dev))
8802                 vlv_init_dpio(dev);
8803
8804         mutex_unlock(&dev->struct_mutex);
8805
8806         /* Disable the irq before mode object teardown, for the irq might
8807          * enqueue unpin/hotplug work. */
8808         drm_irq_uninstall(dev);
8809         cancel_work_sync(&dev_priv->hotplug_work);
8810         cancel_work_sync(&dev_priv->rps.work);
8811
8812         /* flush any delayed tasks or pending work */
8813         flush_scheduled_work();
8814
8815         drm_mode_config_cleanup(dev);
8816 }
8817
8818 /*
8819  * Return which encoder is currently attached for connector.
8820  */
8821 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8822 {
8823         return &intel_attached_encoder(connector)->base;
8824 }
8825
8826 void intel_connector_attach_encoder(struct intel_connector *connector,
8827                                     struct intel_encoder *encoder)
8828 {
8829         connector->encoder = encoder;
8830         drm_mode_connector_attach_encoder(&connector->base,
8831                                           &encoder->base);
8832 }
8833
8834 /*
8835  * set vga decode state - true == enable VGA decode
8836  */
8837 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8838 {
8839         struct drm_i915_private *dev_priv = dev->dev_private;
8840         u16 gmch_ctrl;
8841
8842         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8843         if (state)
8844                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8845         else
8846                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8847         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8848         return 0;
8849 }
8850
8851 #ifdef CONFIG_DEBUG_FS
8852 #include <linux/seq_file.h>
8853
8854 struct intel_display_error_state {
8855         struct intel_cursor_error_state {
8856                 u32 control;
8857                 u32 position;
8858                 u32 base;
8859                 u32 size;
8860         } cursor[I915_MAX_PIPES];
8861
8862         struct intel_pipe_error_state {
8863                 u32 conf;
8864                 u32 source;
8865
8866                 u32 htotal;
8867                 u32 hblank;
8868                 u32 hsync;
8869                 u32 vtotal;
8870                 u32 vblank;
8871                 u32 vsync;
8872         } pipe[I915_MAX_PIPES];
8873
8874         struct intel_plane_error_state {
8875                 u32 control;
8876                 u32 stride;
8877                 u32 size;
8878                 u32 pos;
8879                 u32 addr;
8880                 u32 surface;
8881                 u32 tile_offset;
8882         } plane[I915_MAX_PIPES];
8883 };
8884
8885 struct intel_display_error_state *
8886 intel_display_capture_error_state(struct drm_device *dev)
8887 {
8888         drm_i915_private_t *dev_priv = dev->dev_private;
8889         struct intel_display_error_state *error;
8890         int i;
8891
8892         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8893         if (error == NULL)
8894                 return NULL;
8895
8896         for_each_pipe(i) {
8897                 error->cursor[i].control = I915_READ(CURCNTR(i));
8898                 error->cursor[i].position = I915_READ(CURPOS(i));
8899                 error->cursor[i].base = I915_READ(CURBASE(i));
8900
8901                 error->plane[i].control = I915_READ(DSPCNTR(i));
8902                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8903                 error->plane[i].size = I915_READ(DSPSIZE(i));
8904                 error->plane[i].pos = I915_READ(DSPPOS(i));
8905                 error->plane[i].addr = I915_READ(DSPADDR(i));
8906                 if (INTEL_INFO(dev)->gen >= 4) {
8907                         error->plane[i].surface = I915_READ(DSPSURF(i));
8908                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8909                 }
8910
8911                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8912                 error->pipe[i].source = I915_READ(PIPESRC(i));
8913                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8914                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8915                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8916                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8917                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8918                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8919         }
8920
8921         return error;
8922 }
8923
8924 void
8925 intel_display_print_error_state(struct seq_file *m,
8926                                 struct drm_device *dev,
8927                                 struct intel_display_error_state *error)
8928 {
8929         drm_i915_private_t *dev_priv = dev->dev_private;
8930         int i;
8931
8932         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8933         for_each_pipe(i) {
8934                 seq_printf(m, "Pipe [%d]:\n", i);
8935                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8936                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8937                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8938                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8939                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8940                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8941                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8942                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8943
8944                 seq_printf(m, "Plane [%d]:\n", i);
8945                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8946                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8947                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8948                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8949                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8950                 if (INTEL_INFO(dev)->gen >= 4) {
8951                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8952                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8953                 }
8954
8955                 seq_printf(m, "Cursor [%d]:\n", i);
8956                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8957                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8958                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8959         }
8960 }
8961 #endif