Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 4000000, .max = 5994000},
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 25000, .max = 270000 },
 397         .vco = { .min = 4000000, .max = 6000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 22, .max = 450 },
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct intel_encoder *encoder;
 631
 632         for_each_encoder_on_crtc(dev, crtc, encoder)
 633                 if (encoder->type == type)
 634                         return true;
 635
 636         return false;
 637 }
 638
 639 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 640 /**
 641  * Returns whether the given set of divisors are valid for a given refclk with
 642  * the given connectors.
 643  */
 644
 645 static bool intel_PLL_is_valid(struct drm_device *dev,
 646                                const intel_limit_t *limit,
 647                                const intel_clock_t *clock)
 648 {
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 652                 INTELPllInvalid("p out of range\n");
 653         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 654                 INTELPllInvalid("m2 out of range\n");
 655         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 656                 INTELPllInvalid("m1 out of range\n");
 657         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 658                 INTELPllInvalid("m1 <= m2\n");
 659         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 660                 INTELPllInvalid("m out of range\n");
 661         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 662                 INTELPllInvalid("n out of range\n");
 663         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 664                 INTELPllInvalid("vco out of range\n");
 665         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 666          * connector, etc., rather than just a single range.
 667          */
 668         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 669                 INTELPllInvalid("dot out of range\n");
 670
 671         return true;
 672 }
 673
 674 static bool
 675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 676                     int target, int refclk, intel_clock_t *match_clock,
 677                     intel_clock_t *best_clock)
 678
 679 {
 680         struct drm_device *dev = crtc->dev;
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         intel_clock_t clock;
 683         int err = target;
 684
 685         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 686             (I915_READ(LVDS)) != 0) {
 687                 /*
 688                  * For LVDS, if the panel is on, just rely on its current
 689                  * settings for dual-channel.  We haven't figured out how to
 690                  * reliably set up different single/dual channel state, if we
 691                  * even can.
 692                  */
 693                 if (is_dual_link_lvds(dev_priv, LVDS))
 694                         clock.p2 = limit->p2.p2_fast;
 695                 else
 696                         clock.p2 = limit->p2.p2_slow;
 697         } else {
 698                 if (target < limit->p2.dot_limit)
 699                         clock.p2 = limit->p2.p2_slow;
 700                 else
 701                         clock.p2 = limit->p2.p2_fast;
 702         }
 703
 704         memset(best_clock, 0, sizeof(*best_clock));
 705
 706         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 707              clock.m1++) {
 708                 for (clock.m2 = limit->m2.min;
 709                      clock.m2 <= limit->m2.max; clock.m2++) {
 710                         /* m1 is always 0 in Pineview */
 711                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 712                                 break;
 713                         for (clock.n = limit->n.min;
 714                              clock.n <= limit->n.max; clock.n++) {
 715                                 for (clock.p1 = limit->p1.min;
 716                                         clock.p1 <= limit->p1.max; clock.p1++) {
 717                                         int this_err;
 718
 719                                         intel_clock(dev, refclk, &clock);
 720                                         if (!intel_PLL_is_valid(dev, limit,
 721                                                                 &clock))
 722                                                 continue;
 723                                         if (match_clock &&
 724                                             clock.p != match_clock->p)
 725                                                 continue;
 726
 727                                         this_err = abs(clock.dot - target);
 728                                         if (this_err < err) {
 729                                                 *best_clock = clock;
 730                                                 err = this_err;
 731                                         }
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         return (err != target);
 738 }
 739
 740 static bool
 741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 742                         int target, int refclk, intel_clock_t *match_clock,
 743                         intel_clock_t *best_clock)
 744 {
 745         struct drm_device *dev = crtc->dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         intel_clock_t clock;
 748         int max_n;
 749         bool found;
 750         /* approximately equals target * 0.00585 */
 751         int err_most = (target >> 8) + (target >> 9);
 752         found = false;
 753
 754         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 755                 int lvds_reg;
 756
 757                 if (HAS_PCH_SPLIT(dev))
 758                         lvds_reg = PCH_LVDS;
 759                 else
 760                         lvds_reg = LVDS;
 761                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 762                     LVDS_CLKB_POWER_UP)
 763                         clock.p2 = limit->p2.p2_fast;
 764                 else
 765                         clock.p2 = limit->p2.p2_slow;
 766         } else {
 767                 if (target < limit->p2.dot_limit)
 768                         clock.p2 = limit->p2.p2_slow;
 769                 else
 770                         clock.p2 = limit->p2.p2_fast;
 771         }
 772
 773         memset(best_clock, 0, sizeof(*best_clock));
 774         max_n = limit->n.max;
 775         /* based on hardware requirement, prefer smaller n to precision */
 776         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 777                 /* based on hardware requirement, prefere larger m1,m2 */
 778                 for (clock.m1 = limit->m1.max;
 779                      clock.m1 >= limit->m1.min; clock.m1--) {
 780                         for (clock.m2 = limit->m2.max;
 781                              clock.m2 >= limit->m2.min; clock.m2--) {
 782                                 for (clock.p1 = limit->p1.max;
 783                                      clock.p1 >= limit->p1.min; clock.p1--) {
 784                                         int this_err;
 785
 786                                         intel_clock(dev, refclk, &clock);
 787                                         if (!intel_PLL_is_valid(dev, limit,
 788                                                                 &clock))
 789                                                 continue;
 790                                         if (match_clock &&
 791                                             clock.p != match_clock->p)
 792                                                 continue;
 793
 794                                         this_err = abs(clock.dot - target);
 795                                         if (this_err < err_most) {
 796                                                 *best_clock = clock;
 797                                                 err_most = this_err;
 798                                                 max_n = clock.n;
 799                                                 found = true;
 800                                         }
 801                                 }
 802                         }
 803                 }
 804         }
 805         return found;
 806 }
 807
 808 static bool
 809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 810                            int target, int refclk, intel_clock_t *match_clock,
 811                            intel_clock_t *best_clock)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         intel_clock_t clock;
 815
 816         if (target < 200000) {
 817                 clock.n = 1;
 818                 clock.p1 = 2;
 819                 clock.p2 = 10;
 820                 clock.m1 = 12;
 821                 clock.m2 = 9;
 822         } else {
 823                 clock.n = 2;
 824                 clock.p1 = 1;
 825                 clock.p2 = 10;
 826                 clock.m1 = 14;
 827                 clock.m2 = 8;
 828         }
 829         intel_clock(dev, refclk, &clock);
 830         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 831         return true;
 832 }
 833
 834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 835 static bool
 836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 837                       int target, int refclk, intel_clock_t *match_clock,
 838                       intel_clock_t *best_clock)
 839 {
 840         intel_clock_t clock;
 841         if (target < 200000) {
 842                 clock.p1 = 2;
 843                 clock.p2 = 10;
 844                 clock.n = 2;
 845                 clock.m1 = 23;
 846                 clock.m2 = 8;
 847         } else {
 848                 clock.p1 = 1;
 849                 clock.p2 = 10;
 850                 clock.n = 1;
 851                 clock.m1 = 14;
 852                 clock.m2 = 2;
 853         }
 854         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 855         clock.p = (clock.p1 * clock.p2);
 856         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 857         clock.vco = 0;
 858         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 859         return true;
 860 }
 861 static bool
 862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 863                         int target, int refclk, intel_clock_t *match_clock,
 864                         intel_clock_t *best_clock)
 865 {
 866         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 867         u32 m, n, fastclk;
 868         u32 updrate, minupdate, fracbits, p;
 869         unsigned long bestppm, ppm, absppm;
 870         int dotclk, flag;
 871
 872         flag = 0;
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         WARN(1, "pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         WARN(1, "pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380              && (val & DP_PIPEB_SELECT),
1381              "IBX PCH dp port still using transcoder B\n");
1382 }
1383
1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1385                                      enum pipe pipe, int reg)
1386 {
1387         u32 val = I915_READ(reg);
1388         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1389              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1390              reg, pipe_name(pipe));
1391
1392         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393              && (val & SDVO_PIPE_B_SELECT),
1394              "IBX PCH hdmi port still using transcoder B\n");
1395 }
1396
1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1398                                       enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1404         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1405         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1406
1407         reg = PCH_ADPA;
1408         val = I915_READ(reg);
1409         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1410              "PCH VGA enabled on transcoder %c, should be disabled\n",
1411              pipe_name(pipe));
1412
1413         reg = PCH_LVDS;
1414         val = I915_READ(reg);
1415         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1416              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417              pipe_name(pipe));
1418
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1420         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1421         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1422 }
1423
1424 /**
1425  * intel_enable_pll - enable a PLL
1426  * @dev_priv: i915 private structure
1427  * @pipe: pipe PLL to enable
1428  *
1429  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1430  * make sure the PLL reg is writable first though, since the panel write
1431  * protect mechanism may be enabled.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  *
1435  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1436  */
1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439         int reg;
1440         u32 val;
1441
1442         /* No really, not for ILK+ */
1443         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1444
1445         /* PLL is protected by panel, make sure we can write it */
1446         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1447                 assert_panel_unlocked(dev_priv, pipe);
1448
1449         reg = DPLL(pipe);
1450         val = I915_READ(reg);
1451         val |= DPLL_VCO_ENABLE;
1452
1453         /* We do this three times for luck */
1454         I915_WRITE(reg, val);
1455         POSTING_READ(reg);
1456         udelay(150); /* wait for warmup */
1457         I915_WRITE(reg, val);
1458         POSTING_READ(reg);
1459         udelay(150); /* wait for warmup */
1460         I915_WRITE(reg, val);
1461         POSTING_READ(reg);
1462         udelay(150); /* wait for warmup */
1463 }
1464
1465 /**
1466  * intel_disable_pll - disable a PLL
1467  * @dev_priv: i915 private structure
1468  * @pipe: pipe PLL to disable
1469  *
1470  * Disable the PLL for @pipe, making sure the pipe is off first.
1471  *
1472  * Note!  This is for pre-ILK only.
1473  */
1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1475 {
1476         int reg;
1477         u32 val;
1478
1479         /* Don't disable pipe A or pipe A PLLs if needed */
1480         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1481                 return;
1482
1483         /* Make sure the pipe isn't still relying on us */
1484         assert_pipe_disabled(dev_priv, pipe);
1485
1486         reg = DPLL(pipe);
1487         val = I915_READ(reg);
1488         val &= ~DPLL_VCO_ENABLE;
1489         I915_WRITE(reg, val);
1490         POSTING_READ(reg);
1491 }
1492
1493 /* SBI access */
1494 static void
1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1496 {
1497         unsigned long flags;
1498
1499         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1500         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1501                                 100)) {
1502                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1503                 goto out_unlock;
1504         }
1505
1506         I915_WRITE(SBI_ADDR,
1507                         (reg << 16));
1508         I915_WRITE(SBI_DATA,
1509                         value);
1510         I915_WRITE(SBI_CTL_STAT,
1511                         SBI_BUSY |
1512                         SBI_CTL_OP_CRWR);
1513
1514         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1515                                 100)) {
1516                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517                 goto out_unlock;
1518         }
1519
1520 out_unlock:
1521         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1522 }
1523
1524 static u32
1525 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1526 {
1527         unsigned long flags;
1528         u32 value = 0;
1529
1530         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1531         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1532                                 100)) {
1533                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1534                 goto out_unlock;
1535         }
1536
1537         I915_WRITE(SBI_ADDR,
1538                         (reg << 16));
1539         I915_WRITE(SBI_CTL_STAT,
1540                         SBI_BUSY |
1541                         SBI_CTL_OP_CRRD);
1542
1543         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544                                 100)) {
1545                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1546                 goto out_unlock;
1547         }
1548
1549         value = I915_READ(SBI_DATA);
1550
1551 out_unlock:
1552         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1553         return value;
1554 }
1555
1556 /**
1557  * intel_enable_pch_pll - enable PCH PLL
1558  * @dev_priv: i915 private structure
1559  * @pipe: pipe PLL to enable
1560  *
1561  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1562  * drives the transcoder clock.
1563  */
1564 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1565 {
1566         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1567         struct intel_pch_pll *pll;
1568         int reg;
1569         u32 val;
1570
1571         /* PCH PLLs only available on ILK, SNB and IVB */
1572         BUG_ON(dev_priv->info->gen < 5);
1573         pll = intel_crtc->pch_pll;
1574         if (pll == NULL)
1575                 return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         /* PCH refclock must be enabled first */
1585         assert_pch_refclk_enabled(dev_priv);
1586
1587         if (pll->active++ && pll->on) {
1588                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1589                 return;
1590         }
1591
1592         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1593
1594         reg = pll->pll_reg;
1595         val = I915_READ(reg);
1596         val |= DPLL_VCO_ENABLE;
1597         I915_WRITE(reg, val);
1598         POSTING_READ(reg);
1599         udelay(200);
1600
1601         pll->on = true;
1602 }
1603
1604 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1605 {
1606         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1607         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1608         int reg;
1609         u32 val;
1610
1611         /* PCH only available on ILK+ */
1612         BUG_ON(dev_priv->info->gen < 5);
1613         if (pll == NULL)
1614                return;
1615
1616         if (WARN_ON(pll->refcount == 0))
1617                 return;
1618
1619         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1620                       pll->pll_reg, pll->active, pll->on,
1621                       intel_crtc->base.base.id);
1622
1623         if (WARN_ON(pll->active == 0)) {
1624                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1625                 return;
1626         }
1627
1628         if (--pll->active) {
1629                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1630                 return;
1631         }
1632
1633         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1634
1635         /* Make sure transcoder isn't still depending on us */
1636         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1637
1638         reg = pll->pll_reg;
1639         val = I915_READ(reg);
1640         val &= ~DPLL_VCO_ENABLE;
1641         I915_WRITE(reg, val);
1642         POSTING_READ(reg);
1643         udelay(200);
1644
1645         pll->on = false;
1646 }
1647
1648 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1649                                     enum pipe pipe)
1650 {
1651         int reg;
1652         u32 val, pipeconf_val;
1653         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1654
1655         /* PCH only available on ILK+ */
1656         BUG_ON(dev_priv->info->gen < 5);
1657
1658         /* Make sure PCH DPLL is enabled */
1659         assert_pch_pll_enabled(dev_priv,
1660                                to_intel_crtc(crtc)->pch_pll,
1661                                to_intel_crtc(crtc));
1662
1663         /* FDI must be feeding us bits for PCH ports */
1664         assert_fdi_tx_enabled(dev_priv, pipe);
1665         assert_fdi_rx_enabled(dev_priv, pipe);
1666
1667         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1668                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1669                 return;
1670         }
1671         reg = TRANSCONF(pipe);
1672         val = I915_READ(reg);
1673         pipeconf_val = I915_READ(PIPECONF(pipe));
1674
1675         if (HAS_PCH_IBX(dev_priv->dev)) {
1676                 /*
1677                  * make the BPC in transcoder be consistent with
1678                  * that in pipeconf reg.
1679                  */
1680                 val &= ~PIPE_BPC_MASK;
1681                 val |= pipeconf_val & PIPE_BPC_MASK;
1682         }
1683
1684         val &= ~TRANS_INTERLACE_MASK;
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1686                 if (HAS_PCH_IBX(dev_priv->dev) &&
1687                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688                         val |= TRANS_LEGACY_INTERLACED_ILK;
1689                 else
1690                         val |= TRANS_INTERLACED;
1691         else
1692                 val |= TRANS_PROGRESSIVE;
1693
1694         I915_WRITE(reg, val | TRANS_ENABLE);
1695         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697 }
1698
1699 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1700                                      enum pipe pipe)
1701 {
1702         int reg;
1703         u32 val;
1704
1705         /* FDI relies on the transcoder */
1706         assert_fdi_tx_disabled(dev_priv, pipe);
1707         assert_fdi_rx_disabled(dev_priv, pipe);
1708
1709         /* Ports must be off as well */
1710         assert_pch_ports_disabled(dev_priv, pipe);
1711
1712         reg = TRANSCONF(pipe);
1713         val = I915_READ(reg);
1714         val &= ~TRANS_ENABLE;
1715         I915_WRITE(reg, val);
1716         /* wait for PCH transcoder off, transcoder state */
1717         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1718                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1719 }
1720
1721 /**
1722  * intel_enable_pipe - enable a pipe, asserting requirements
1723  * @dev_priv: i915 private structure
1724  * @pipe: pipe to enable
1725  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1726  *
1727  * Enable @pipe, making sure that various hardware specific requirements
1728  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1729  *
1730  * @pipe should be %PIPE_A or %PIPE_B.
1731  *
1732  * Will wait until the pipe is actually running (i.e. first vblank) before
1733  * returning.
1734  */
1735 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1736                               bool pch_port)
1737 {
1738         int reg;
1739         u32 val;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 assert_pll_enabled(dev_priv, pipe);
1748         else {
1749                 if (pch_port) {
1750                         /* if driving the PCH, we need FDI enabled */
1751                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1752                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1753                 }
1754                 /* FIXME: assert CPU port conditions for SNB+ */
1755         }
1756
1757         reg = PIPECONF(pipe);
1758         val = I915_READ(reg);
1759         if (val & PIPECONF_ENABLE)
1760                 return;
1761
1762         I915_WRITE(reg, val | PIPECONF_ENABLE);
1763         intel_wait_for_vblank(dev_priv->dev, pipe);
1764 }
1765
1766 /**
1767  * intel_disable_pipe - disable a pipe, asserting requirements
1768  * @dev_priv: i915 private structure
1769  * @pipe: pipe to disable
1770  *
1771  * Disable @pipe, making sure that various hardware specific requirements
1772  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773  *
1774  * @pipe should be %PIPE_A or %PIPE_B.
1775  *
1776  * Will wait until the pipe has shut down before returning.
1777  */
1778 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1779                                enum pipe pipe)
1780 {
1781         int reg;
1782         u32 val;
1783
1784         /*
1785          * Make sure planes won't keep trying to pump pixels to us,
1786          * or we might hang the display.
1787          */
1788         assert_planes_disabled(dev_priv, pipe);
1789
1790         /* Don't disable pipe A or pipe A PLLs if needed */
1791         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1792                 return;
1793
1794         reg = PIPECONF(pipe);
1795         val = I915_READ(reg);
1796         if ((val & PIPECONF_ENABLE) == 0)
1797                 return;
1798
1799         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1800         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1801 }
1802
1803 /*
1804  * Plane regs are double buffered, going from enabled->disabled needs a
1805  * trigger in order to latch.  The display address reg provides this.
1806  */
1807 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1808                                       enum plane plane)
1809 {
1810         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1811         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1812 }
1813
1814 /**
1815  * intel_enable_plane - enable a display plane on a given pipe
1816  * @dev_priv: i915 private structure
1817  * @plane: plane to enable
1818  * @pipe: pipe being fed
1819  *
1820  * Enable @plane on @pipe, making sure that @pipe is running first.
1821  */
1822 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1823                                enum plane plane, enum pipe pipe)
1824 {
1825         int reg;
1826         u32 val;
1827
1828         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1829         assert_pipe_enabled(dev_priv, pipe);
1830
1831         reg = DSPCNTR(plane);
1832         val = I915_READ(reg);
1833         if (val & DISPLAY_PLANE_ENABLE)
1834                 return;
1835
1836         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1837         intel_flush_display_plane(dev_priv, plane);
1838         intel_wait_for_vblank(dev_priv->dev, pipe);
1839 }
1840
1841 /**
1842  * intel_disable_plane - disable a display plane
1843  * @dev_priv: i915 private structure
1844  * @plane: plane to disable
1845  * @pipe: pipe consuming the data
1846  *
1847  * Disable @plane; should be an independent operation.
1848  */
1849 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1850                                 enum plane plane, enum pipe pipe)
1851 {
1852         int reg;
1853         u32 val;
1854
1855         reg = DSPCNTR(plane);
1856         val = I915_READ(reg);
1857         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1858                 return;
1859
1860         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1861         intel_flush_display_plane(dev_priv, plane);
1862         intel_wait_for_vblank(dev_priv->dev, pipe);
1863 }
1864
1865 int
1866 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1867                            struct drm_i915_gem_object *obj,
1868                            struct intel_ring_buffer *pipelined)
1869 {
1870         struct drm_i915_private *dev_priv = dev->dev_private;
1871         u32 alignment;
1872         int ret;
1873
1874         switch (obj->tiling_mode) {
1875         case I915_TILING_NONE:
1876                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1877                         alignment = 128 * 1024;
1878                 else if (INTEL_INFO(dev)->gen >= 4)
1879                         alignment = 4 * 1024;
1880                 else
1881                         alignment = 64 * 1024;
1882                 break;
1883         case I915_TILING_X:
1884                 /* pin() will align the object as required by fence */
1885                 alignment = 0;
1886                 break;
1887         case I915_TILING_Y:
1888                 /* FIXME: Is this true? */
1889                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1890                 return -EINVAL;
1891         default:
1892                 BUG();
1893         }
1894
1895         dev_priv->mm.interruptible = false;
1896         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1897         if (ret)
1898                 goto err_interruptible;
1899
1900         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1901          * fence, whereas 965+ only requires a fence if using
1902          * framebuffer compression.  For simplicity, we always install
1903          * a fence as the cost is not that onerous.
1904          */
1905         ret = i915_gem_object_get_fence(obj);
1906         if (ret)
1907                 goto err_unpin;
1908
1909         i915_gem_object_pin_fence(obj);
1910
1911         dev_priv->mm.interruptible = true;
1912         return 0;
1913
1914 err_unpin:
1915         i915_gem_object_unpin(obj);
1916 err_interruptible:
1917         dev_priv->mm.interruptible = true;
1918         return ret;
1919 }
1920
1921 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1922 {
1923         i915_gem_object_unpin_fence(obj);
1924         i915_gem_object_unpin(obj);
1925 }
1926
1927 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1928  * is assumed to be a power-of-two. */
1929 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1930                                                         unsigned int bpp,
1931                                                         unsigned int pitch)
1932 {
1933         int tile_rows, tiles;
1934
1935         tile_rows = *y / 8;
1936         *y %= 8;
1937         tiles = *x / (512/bpp);
1938         *x %= 512/bpp;
1939
1940         return tile_rows * pitch * 8 + tiles * 4096;
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long linear_offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->bits_per_pixel) {
1973         case 8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case 16:
1977                 if (fb->depth == 15)
1978                         dspcntr |= DISPPLANE_15_16BPP;
1979                 else
1980                         dspcntr |= DISPPLANE_16BPP;
1981                 break;
1982         case 24:
1983         case 32:
1984                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1985                 break;
1986         default:
1987                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1988                 return -EINVAL;
1989         }
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 if (obj->tiling_mode != I915_TILING_NONE)
1992                         dspcntr |= DISPPLANE_TILED;
1993                 else
1994                         dspcntr &= ~DISPPLANE_TILED;
1995         }
1996
1997         I915_WRITE(reg, dspcntr);
1998
1999         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2000
2001         if (INTEL_INFO(dev)->gen >= 4) {
2002                 intel_crtc->dspaddr_offset =
2003                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2004                                                            fb->bits_per_pixel / 8,
2005                                                            fb->pitches[0]);
2006                 linear_offset -= intel_crtc->dspaddr_offset;
2007         } else {
2008                 intel_crtc->dspaddr_offset = linear_offset;
2009         }
2010
2011         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2012                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2013         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2014         if (INTEL_INFO(dev)->gen >= 4) {
2015                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2016                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2017                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2018                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2019         } else
2020                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2021         POSTING_READ(reg);
2022
2023         return 0;
2024 }
2025
2026 static int ironlake_update_plane(struct drm_crtc *crtc,
2027                                  struct drm_framebuffer *fb, int x, int y)
2028 {
2029         struct drm_device *dev = crtc->dev;
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2032         struct intel_framebuffer *intel_fb;
2033         struct drm_i915_gem_object *obj;
2034         int plane = intel_crtc->plane;
2035         unsigned long linear_offset;
2036         u32 dspcntr;
2037         u32 reg;
2038
2039         switch (plane) {
2040         case 0:
2041         case 1:
2042         case 2:
2043                 break;
2044         default:
2045                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046                 return -EINVAL;
2047         }
2048
2049         intel_fb = to_intel_framebuffer(fb);
2050         obj = intel_fb->obj;
2051
2052         reg = DSPCNTR(plane);
2053         dspcntr = I915_READ(reg);
2054         /* Mask out pixel format bits in case we change it */
2055         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056         switch (fb->bits_per_pixel) {
2057         case 8:
2058                 dspcntr |= DISPPLANE_8BPP;
2059                 break;
2060         case 16:
2061                 if (fb->depth != 16)
2062                         return -EINVAL;
2063
2064                 dspcntr |= DISPPLANE_16BPP;
2065                 break;
2066         case 24:
2067         case 32:
2068                 if (fb->depth == 24)
2069                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2070                 else if (fb->depth == 30)
2071                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2072                 else
2073                         return -EINVAL;
2074                 break;
2075         default:
2076                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2077                 return -EINVAL;
2078         }
2079
2080         if (obj->tiling_mode != I915_TILING_NONE)
2081                 dspcntr |= DISPPLANE_TILED;
2082         else
2083                 dspcntr &= ~DISPPLANE_TILED;
2084
2085         /* must disable */
2086         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2087
2088         I915_WRITE(reg, dspcntr);
2089
2090         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2091         intel_crtc->dspaddr_offset =
2092                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2093                                                    fb->bits_per_pixel / 8,
2094                                                    fb->pitches[0]);
2095         linear_offset -= intel_crtc->dspaddr_offset;
2096
2097         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2098                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2099         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2100         I915_MODIFY_DISPBASE(DSPSURF(plane),
2101                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2102         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2103         I915_WRITE(DSPLINOFF(plane), linear_offset);
2104         POSTING_READ(reg);
2105
2106         return 0;
2107 }
2108
2109 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2110 static int
2111 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2112                            int x, int y, enum mode_set_atomic state)
2113 {
2114         struct drm_device *dev = crtc->dev;
2115         struct drm_i915_private *dev_priv = dev->dev_private;
2116
2117         if (dev_priv->display.disable_fbc)
2118                 dev_priv->display.disable_fbc(dev);
2119         intel_increase_pllclock(crtc);
2120
2121         return dev_priv->display.update_plane(crtc, fb, x, y);
2122 }
2123
2124 static int
2125 intel_finish_fb(struct drm_framebuffer *old_fb)
2126 {
2127         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2128         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2129         bool was_interruptible = dev_priv->mm.interruptible;
2130         int ret;
2131
2132         wait_event(dev_priv->pending_flip_queue,
2133                    atomic_read(&dev_priv->mm.wedged) ||
2134                    atomic_read(&obj->pending_flip) == 0);
2135
2136         /* Big Hammer, we also need to ensure that any pending
2137          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2138          * current scanout is retired before unpinning the old
2139          * framebuffer.
2140          *
2141          * This should only fail upon a hung GPU, in which case we
2142          * can safely continue.
2143          */
2144         dev_priv->mm.interruptible = false;
2145         ret = i915_gem_object_finish_gpu(obj);
2146         dev_priv->mm.interruptible = was_interruptible;
2147
2148         return ret;
2149 }
2150
2151 static int
2152 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2153                     struct drm_framebuffer *fb)
2154 {
2155         struct drm_device *dev = crtc->dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct drm_i915_master_private *master_priv;
2158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159         struct drm_framebuffer *old_fb;
2160         int ret;
2161
2162         /* no fb bound */
2163         if (!fb) {
2164                 DRM_ERROR("No FB bound\n");
2165                 return 0;
2166         }
2167
2168         if(intel_crtc->plane > dev_priv->num_pipe) {
2169                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2170                                 intel_crtc->plane,
2171                                 dev_priv->num_pipe);
2172                 return -EINVAL;
2173         }
2174
2175         mutex_lock(&dev->struct_mutex);
2176         ret = intel_pin_and_fence_fb_obj(dev,
2177                                          to_intel_framebuffer(fb)->obj,
2178                                          NULL);
2179         if (ret != 0) {
2180                 mutex_unlock(&dev->struct_mutex);
2181                 DRM_ERROR("pin & fence failed\n");
2182                 return ret;
2183         }
2184
2185         if (crtc->fb)
2186                 intel_finish_fb(crtc->fb);
2187
2188         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2189         if (ret) {
2190                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2191                 mutex_unlock(&dev->struct_mutex);
2192                 DRM_ERROR("failed to update base address\n");
2193                 return ret;
2194         }
2195
2196         old_fb = crtc->fb;
2197         crtc->fb = fb;
2198         crtc->x = x;
2199         crtc->y = y;
2200
2201         if (old_fb) {
2202                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2203                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2204         }
2205
2206         intel_update_fbc(dev);
2207         mutex_unlock(&dev->struct_mutex);
2208
2209         if (!dev->primary->master)
2210                 return 0;
2211
2212         master_priv = dev->primary->master->driver_priv;
2213         if (!master_priv->sarea_priv)
2214                 return 0;
2215
2216         if (intel_crtc->pipe) {
2217                 master_priv->sarea_priv->pipeB_x = x;
2218                 master_priv->sarea_priv->pipeB_y = y;
2219         } else {
2220                 master_priv->sarea_priv->pipeA_x = x;
2221                 master_priv->sarea_priv->pipeA_y = y;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         u32 dpa_ctl;
2232
2233         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2234         dpa_ctl = I915_READ(DP_A);
2235         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2236
2237         if (clock < 200000) {
2238                 u32 temp;
2239                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2240                 /* workaround for 160Mhz:
2241                    1) program 0x4600c bits 15:0 = 0x8124
2242                    2) program 0x46010 bit 0 = 1
2243                    3) program 0x46034 bit 24 = 1
2244                    4) program 0x64000 bit 14 = 1
2245                    */
2246                 temp = I915_READ(0x4600c);
2247                 temp &= 0xffff0000;
2248                 I915_WRITE(0x4600c, temp | 0x8124);
2249
2250                 temp = I915_READ(0x46010);
2251                 I915_WRITE(0x46010, temp | 1);
2252
2253                 temp = I915_READ(0x46034);
2254                 I915_WRITE(0x46034, temp | (1 << 24));
2255         } else {
2256                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2257         }
2258         I915_WRITE(DP_A, dpa_ctl);
2259
2260         POSTING_READ(DP_A);
2261         udelay(500);
2262 }
2263
2264 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269         int pipe = intel_crtc->pipe;
2270         u32 reg, temp;
2271
2272         /* enable normal train */
2273         reg = FDI_TX_CTL(pipe);
2274         temp = I915_READ(reg);
2275         if (IS_IVYBRIDGE(dev)) {
2276                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2277                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2278         } else {
2279                 temp &= ~FDI_LINK_TRAIN_NONE;
2280                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2281         }
2282         I915_WRITE(reg, temp);
2283
2284         reg = FDI_RX_CTL(pipe);
2285         temp = I915_READ(reg);
2286         if (HAS_PCH_CPT(dev)) {
2287                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2288                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2289         } else {
2290                 temp &= ~FDI_LINK_TRAIN_NONE;
2291                 temp |= FDI_LINK_TRAIN_NONE;
2292         }
2293         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2294
2295         /* wait one idle pattern time */
2296         POSTING_READ(reg);
2297         udelay(1000);
2298
2299         /* IVB wants error correction enabled */
2300         if (IS_IVYBRIDGE(dev))
2301                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2302                            FDI_FE_ERRC_ENABLE);
2303 }
2304
2305 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2306 {
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         u32 flags = I915_READ(SOUTH_CHICKEN1);
2309
2310         flags |= FDI_PHASE_SYNC_OVR(pipe);
2311         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2312         flags |= FDI_PHASE_SYNC_EN(pipe);
2313         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2314         POSTING_READ(SOUTH_CHICKEN1);
2315 }
2316
2317 /* The FDI link training functions for ILK/Ibexpeak. */
2318 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2319 {
2320         struct drm_device *dev = crtc->dev;
2321         struct drm_i915_private *dev_priv = dev->dev_private;
2322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323         int pipe = intel_crtc->pipe;
2324         int plane = intel_crtc->plane;
2325         u32 reg, temp, tries;
2326
2327         /* FDI needs bits from pipe & plane first */
2328         assert_pipe_enabled(dev_priv, pipe);
2329         assert_plane_enabled(dev_priv, plane);
2330
2331         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2332            for train result */
2333         reg = FDI_RX_IMR(pipe);
2334         temp = I915_READ(reg);
2335         temp &= ~FDI_RX_SYMBOL_LOCK;
2336         temp &= ~FDI_RX_BIT_LOCK;
2337         I915_WRITE(reg, temp);
2338         I915_READ(reg);
2339         udelay(150);
2340
2341         /* enable CPU FDI TX and PCH FDI RX */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         temp &= ~(7 << 19);
2345         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2346         temp &= ~FDI_LINK_TRAIN_NONE;
2347         temp |= FDI_LINK_TRAIN_PATTERN_1;
2348         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         temp &= ~FDI_LINK_TRAIN_NONE;
2353         temp |= FDI_LINK_TRAIN_PATTERN_1;
2354         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2355
2356         POSTING_READ(reg);
2357         udelay(150);
2358
2359         /* Ironlake workaround, enable clock pointer after FDI enable*/
2360         if (HAS_PCH_IBX(dev)) {
2361                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                            FDI_RX_PHASE_SYNC_POINTER_EN);
2364         }
2365
2366         reg = FDI_RX_IIR(pipe);
2367         for (tries = 0; tries < 5; tries++) {
2368                 temp = I915_READ(reg);
2369                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2370
2371                 if ((temp & FDI_RX_BIT_LOCK)) {
2372                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2373                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2374                         break;
2375                 }
2376         }
2377         if (tries == 5)
2378                 DRM_ERROR("FDI train 1 fail!\n");
2379
2380         /* Train 2 */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_LINK_TRAIN_NONE;
2384         temp |= FDI_LINK_TRAIN_PATTERN_2;
2385         I915_WRITE(reg, temp);
2386
2387         reg = FDI_RX_CTL(pipe);
2388         temp = I915_READ(reg);
2389         temp &= ~FDI_LINK_TRAIN_NONE;
2390         temp |= FDI_LINK_TRAIN_PATTERN_2;
2391         I915_WRITE(reg, temp);
2392
2393         POSTING_READ(reg);
2394         udelay(150);
2395
2396         reg = FDI_RX_IIR(pipe);
2397         for (tries = 0; tries < 5; tries++) {
2398                 temp = I915_READ(reg);
2399                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2400
2401                 if (temp & FDI_RX_SYMBOL_LOCK) {
2402                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2403                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2404                         break;
2405                 }
2406         }
2407         if (tries == 5)
2408                 DRM_ERROR("FDI train 2 fail!\n");
2409
2410         DRM_DEBUG_KMS("FDI train done\n");
2411
2412 }
2413
2414 static const int snb_b_fdi_train_param[] = {
2415         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2416         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2417         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2418         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2419 };
2420
2421 /* The FDI link training functions for SNB/Cougarpoint. */
2422 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2423 {
2424         struct drm_device *dev = crtc->dev;
2425         struct drm_i915_private *dev_priv = dev->dev_private;
2426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2427         int pipe = intel_crtc->pipe;
2428         u32 reg, temp, i, retry;
2429
2430         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431            for train result */
2432         reg = FDI_RX_IMR(pipe);
2433         temp = I915_READ(reg);
2434         temp &= ~FDI_RX_SYMBOL_LOCK;
2435         temp &= ~FDI_RX_BIT_LOCK;
2436         I915_WRITE(reg, temp);
2437
2438         POSTING_READ(reg);
2439         udelay(150);
2440
2441         /* enable CPU FDI TX and PCH FDI RX */
2442         reg = FDI_TX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~(7 << 19);
2445         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2446         temp &= ~FDI_LINK_TRAIN_NONE;
2447         temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2449         /* SNB-B */
2450         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2451         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2452
2453         reg = FDI_RX_CTL(pipe);
2454         temp = I915_READ(reg);
2455         if (HAS_PCH_CPT(dev)) {
2456                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2457                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2458         } else {
2459                 temp &= ~FDI_LINK_TRAIN_NONE;
2460                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2461         }
2462         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2463
2464         POSTING_READ(reg);
2465         udelay(150);
2466
2467         if (HAS_PCH_CPT(dev))
2468                 cpt_phase_pointer_enable(dev, pipe);
2469
2470         for (i = 0; i < 4; i++) {
2471                 reg = FDI_TX_CTL(pipe);
2472                 temp = I915_READ(reg);
2473                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2474                 temp |= snb_b_fdi_train_param[i];
2475                 I915_WRITE(reg, temp);
2476
2477                 POSTING_READ(reg);
2478                 udelay(500);
2479
2480                 for (retry = 0; retry < 5; retry++) {
2481                         reg = FDI_RX_IIR(pipe);
2482                         temp = I915_READ(reg);
2483                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484                         if (temp & FDI_RX_BIT_LOCK) {
2485                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2486                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2487                                 break;
2488                         }
2489                         udelay(50);
2490                 }
2491                 if (retry < 5)
2492                         break;
2493         }
2494         if (i == 4)
2495                 DRM_ERROR("FDI train 1 fail!\n");
2496
2497         /* Train 2 */
2498         reg = FDI_TX_CTL(pipe);
2499         temp = I915_READ(reg);
2500         temp &= ~FDI_LINK_TRAIN_NONE;
2501         temp |= FDI_LINK_TRAIN_PATTERN_2;
2502         if (IS_GEN6(dev)) {
2503                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2504                 /* SNB-B */
2505                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2506         }
2507         I915_WRITE(reg, temp);
2508
2509         reg = FDI_RX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         if (HAS_PCH_CPT(dev)) {
2512                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2513                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2514         } else {
2515                 temp &= ~FDI_LINK_TRAIN_NONE;
2516                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2517         }
2518         I915_WRITE(reg, temp);
2519
2520         POSTING_READ(reg);
2521         udelay(150);
2522
2523         for (i = 0; i < 4; i++) {
2524                 reg = FDI_TX_CTL(pipe);
2525                 temp = I915_READ(reg);
2526                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527                 temp |= snb_b_fdi_train_param[i];
2528                 I915_WRITE(reg, temp);
2529
2530                 POSTING_READ(reg);
2531                 udelay(500);
2532
2533                 for (retry = 0; retry < 5; retry++) {
2534                         reg = FDI_RX_IIR(pipe);
2535                         temp = I915_READ(reg);
2536                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537                         if (temp & FDI_RX_SYMBOL_LOCK) {
2538                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                                 break;
2541                         }
2542                         udelay(50);
2543                 }
2544                 if (retry < 5)
2545                         break;
2546         }
2547         if (i == 4)
2548                 DRM_ERROR("FDI train 2 fail!\n");
2549
2550         DRM_DEBUG_KMS("FDI train done.\n");
2551 }
2552
2553 /* Manual link training for Ivy Bridge A0 parts */
2554 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2555 {
2556         struct drm_device *dev = crtc->dev;
2557         struct drm_i915_private *dev_priv = dev->dev_private;
2558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559         int pipe = intel_crtc->pipe;
2560         u32 reg, temp, i;
2561
2562         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2563            for train result */
2564         reg = FDI_RX_IMR(pipe);
2565         temp = I915_READ(reg);
2566         temp &= ~FDI_RX_SYMBOL_LOCK;
2567         temp &= ~FDI_RX_BIT_LOCK;
2568         I915_WRITE(reg, temp);
2569
2570         POSTING_READ(reg);
2571         udelay(150);
2572
2573         /* enable CPU FDI TX and PCH FDI RX */
2574         reg = FDI_TX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~(7 << 19);
2577         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2578         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2580         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2581         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582         temp |= FDI_COMPOSITE_SYNC;
2583         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         temp &= ~FDI_LINK_TRAIN_AUTO;
2588         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         temp |= FDI_COMPOSITE_SYNC;
2591         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2592
2593         POSTING_READ(reg);
2594         udelay(150);
2595
2596         if (HAS_PCH_CPT(dev))
2597                 cpt_phase_pointer_enable(dev, pipe);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 reg = FDI_RX_IIR(pipe);
2610                 temp = I915_READ(reg);
2611                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612
2613                 if (temp & FDI_RX_BIT_LOCK ||
2614                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2615                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2617                         break;
2618                 }
2619         }
2620         if (i == 4)
2621                 DRM_ERROR("FDI train 1 fail!\n");
2622
2623         /* Train 2 */
2624         reg = FDI_TX_CTL(pipe);
2625         temp = I915_READ(reg);
2626         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2627         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2628         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630         I915_WRITE(reg, temp);
2631
2632         reg = FDI_RX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636         I915_WRITE(reg, temp);
2637
2638         POSTING_READ(reg);
2639         udelay(150);
2640
2641         for (i = 0; i < 4; i++) {
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645                 temp |= snb_b_fdi_train_param[i];
2646                 I915_WRITE(reg, temp);
2647
2648                 POSTING_READ(reg);
2649                 udelay(500);
2650
2651                 reg = FDI_RX_IIR(pipe);
2652                 temp = I915_READ(reg);
2653                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2654
2655                 if (temp & FDI_RX_SYMBOL_LOCK) {
2656                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 2 fail!\n");
2663
2664         DRM_DEBUG_KMS("FDI train done.\n");
2665 }
2666
2667 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2668 {
2669         struct drm_device *dev = intel_crtc->base.dev;
2670         struct drm_i915_private *dev_priv = dev->dev_private;
2671         int pipe = intel_crtc->pipe;
2672         u32 reg, temp;
2673
2674         /* Write the TU size bits so error detection works */
2675         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2676                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2677
2678         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2679         reg = FDI_RX_CTL(pipe);
2680         temp = I915_READ(reg);
2681         temp &= ~((0x7 << 19) | (0x7 << 16));
2682         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2683         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2684         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2685
2686         POSTING_READ(reg);
2687         udelay(200);
2688
2689         /* Switch from Rawclk to PCDclk */
2690         temp = I915_READ(reg);
2691         I915_WRITE(reg, temp | FDI_PCDCLK);
2692
2693         POSTING_READ(reg);
2694         udelay(200);
2695
2696         /* On Haswell, the PLL configuration for ports and pipes is handled
2697          * separately, as part of DDI setup */
2698         if (!IS_HASWELL(dev)) {
2699                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2700                 reg = FDI_TX_CTL(pipe);
2701                 temp = I915_READ(reg);
2702                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2703                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2704
2705                         POSTING_READ(reg);
2706                         udelay(100);
2707                 }
2708         }
2709 }
2710
2711 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712 {
2713         struct drm_device *dev = intel_crtc->base.dev;
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* Switch from PCDclk to Rawclk */
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723         /* Disable CPU FDI TX PLL */
2724         reg = FDI_TX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728         POSTING_READ(reg);
2729         udelay(100);
2730
2731         reg = FDI_RX_CTL(pipe);
2732         temp = I915_READ(reg);
2733         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735         /* Wait for the clocks to turn off. */
2736         POSTING_READ(reg);
2737         udelay(100);
2738 }
2739
2740 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2741 {
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         u32 flags = I915_READ(SOUTH_CHICKEN1);
2744
2745         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2746         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2747         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2748         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2749         POSTING_READ(SOUTH_CHICKEN1);
2750 }
2751 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2752 {
2753         struct drm_device *dev = crtc->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2756         int pipe = intel_crtc->pipe;
2757         u32 reg, temp;
2758
2759         /* disable CPU FDI tx and PCH FDI rx */
2760         reg = FDI_TX_CTL(pipe);
2761         temp = I915_READ(reg);
2762         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2763         POSTING_READ(reg);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         temp &= ~(0x7 << 16);
2768         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2769         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2770
2771         POSTING_READ(reg);
2772         udelay(100);
2773
2774         /* Ironlake workaround, disable clock pointer after downing FDI */
2775         if (HAS_PCH_IBX(dev)) {
2776                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2777                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2778                            I915_READ(FDI_RX_CHICKEN(pipe) &
2779                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2780         } else if (HAS_PCH_CPT(dev)) {
2781                 cpt_phase_pointer_disable(dev, pipe);
2782         }
2783
2784         /* still set train pattern 1 */
2785         reg = FDI_TX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         temp &= ~FDI_LINK_TRAIN_NONE;
2788         temp |= FDI_LINK_TRAIN_PATTERN_1;
2789         I915_WRITE(reg, temp);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         if (HAS_PCH_CPT(dev)) {
2794                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796         } else {
2797                 temp &= ~FDI_LINK_TRAIN_NONE;
2798                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         }
2800         /* BPC in FDI rx is consistent with that in PIPECONF */
2801         temp &= ~(0x07 << 16);
2802         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2803         I915_WRITE(reg, temp);
2804
2805         POSTING_READ(reg);
2806         udelay(100);
2807 }
2808
2809 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2810 {
2811         struct drm_device *dev = crtc->dev;
2812
2813         if (crtc->fb == NULL)
2814                 return;
2815
2816         mutex_lock(&dev->struct_mutex);
2817         intel_finish_fb(crtc->fb);
2818         mutex_unlock(&dev->struct_mutex);
2819 }
2820
2821 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2822 {
2823         struct drm_device *dev = crtc->dev;
2824         struct intel_encoder *intel_encoder;
2825
2826         /*
2827          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2828          * must be driven by its own crtc; no sharing is possible.
2829          */
2830         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2831
2832                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2833                  * CPU handles all others */
2834                 if (IS_HASWELL(dev)) {
2835                         /* It is still unclear how this will work on PPT, so throw up a warning */
2836                         WARN_ON(!HAS_PCH_LPT(dev));
2837
2838                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2839                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2840                                 return true;
2841                         } else {
2842                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2843                                               intel_encoder->type);
2844                                 return false;
2845                         }
2846                 }
2847
2848                 switch (intel_encoder->type) {
2849                 case INTEL_OUTPUT_EDP:
2850                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2851                                 return false;
2852                         continue;
2853                 }
2854         }
2855
2856         return true;
2857 }
2858
2859 /* Program iCLKIP clock to the desired frequency */
2860 static void lpt_program_iclkip(struct drm_crtc *crtc)
2861 {
2862         struct drm_device *dev = crtc->dev;
2863         struct drm_i915_private *dev_priv = dev->dev_private;
2864         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2865         u32 temp;
2866
2867         /* It is necessary to ungate the pixclk gate prior to programming
2868          * the divisors, and gate it back when it is done.
2869          */
2870         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2871
2872         /* Disable SSCCTL */
2873         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2874                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2875                                         SBI_SSCCTL_DISABLE);
2876
2877         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2878         if (crtc->mode.clock == 20000) {
2879                 auxdiv = 1;
2880                 divsel = 0x41;
2881                 phaseinc = 0x20;
2882         } else {
2883                 /* The iCLK virtual clock root frequency is in MHz,
2884                  * but the crtc->mode.clock in in KHz. To get the divisors,
2885                  * it is necessary to divide one by another, so we
2886                  * convert the virtual clock precision to KHz here for higher
2887                  * precision.
2888                  */
2889                 u32 iclk_virtual_root_freq = 172800 * 1000;
2890                 u32 iclk_pi_range = 64;
2891                 u32 desired_divisor, msb_divisor_value, pi_value;
2892
2893                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2894                 msb_divisor_value = desired_divisor / iclk_pi_range;
2895                 pi_value = desired_divisor % iclk_pi_range;
2896
2897                 auxdiv = 0;
2898                 divsel = msb_divisor_value - 2;
2899                 phaseinc = pi_value;
2900         }
2901
2902         /* This should not happen with any sane values */
2903         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2904                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2905         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2906                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2907
2908         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2909                         crtc->mode.clock,
2910                         auxdiv,
2911                         divsel,
2912                         phasedir,
2913                         phaseinc);
2914
2915         /* Program SSCDIVINTPHASE6 */
2916         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2917         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2918         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2919         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2920         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2921         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2922         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2923
2924         intel_sbi_write(dev_priv,
2925                         SBI_SSCDIVINTPHASE6,
2926                         temp);
2927
2928         /* Program SSCAUXDIV */
2929         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2930         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2931         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2932         intel_sbi_write(dev_priv,
2933                         SBI_SSCAUXDIV6,
2934                         temp);
2935
2936
2937         /* Enable modulator and associated divider */
2938         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2939         temp &= ~SBI_SSCCTL_DISABLE;
2940         intel_sbi_write(dev_priv,
2941                         SBI_SSCCTL6,
2942                         temp);
2943
2944         /* Wait for initialization time */
2945         udelay(24);
2946
2947         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948 }
2949
2950 /*
2951  * Enable PCH resources required for PCH ports:
2952  *   - PCH PLLs
2953  *   - FDI training & RX/TX
2954  *   - update transcoder timings
2955  *   - DP transcoding bits
2956  *   - transcoder
2957  */
2958 static void ironlake_pch_enable(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp;
2965
2966         assert_transcoder_disabled(dev_priv, pipe);
2967
2968         /* For PCH output, training FDI link */
2969         dev_priv->display.fdi_link_train(crtc);
2970
2971         intel_enable_pch_pll(intel_crtc);
2972
2973         if (HAS_PCH_LPT(dev)) {
2974                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2975                 lpt_program_iclkip(crtc);
2976         } else if (HAS_PCH_CPT(dev)) {
2977                 u32 sel;
2978
2979                 temp = I915_READ(PCH_DPLL_SEL);
2980                 switch (pipe) {
2981                 default:
2982                 case 0:
2983                         temp |= TRANSA_DPLL_ENABLE;
2984                         sel = TRANSA_DPLLB_SEL;
2985                         break;
2986                 case 1:
2987                         temp |= TRANSB_DPLL_ENABLE;
2988                         sel = TRANSB_DPLLB_SEL;
2989                         break;
2990                 case 2:
2991                         temp |= TRANSC_DPLL_ENABLE;
2992                         sel = TRANSC_DPLLB_SEL;
2993                         break;
2994                 }
2995                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2996                         temp |= sel;
2997                 else
2998                         temp &= ~sel;
2999                 I915_WRITE(PCH_DPLL_SEL, temp);
3000         }
3001
3002         /* set transcoder timing, panel must allow it */
3003         assert_panel_unlocked(dev_priv, pipe);
3004         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3005         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3006         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3007
3008         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3009         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3010         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3011         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3012
3013         if (!IS_HASWELL(dev))
3014                 intel_fdi_normal_train(crtc);
3015
3016         /* For PCH DP, enable TRANS_DP_CTL */
3017         if (HAS_PCH_CPT(dev) &&
3018             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3019              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3020                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3021                 reg = TRANS_DP_CTL(pipe);
3022                 temp = I915_READ(reg);
3023                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3024                           TRANS_DP_SYNC_MASK |
3025                           TRANS_DP_BPC_MASK);
3026                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3027                          TRANS_DP_ENH_FRAMING);
3028                 temp |= bpc << 9; /* same format but at 11:9 */
3029
3030                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3031                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3032                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3033                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3034
3035                 switch (intel_trans_dp_port_sel(crtc)) {
3036                 case PCH_DP_B:
3037                         temp |= TRANS_DP_PORT_SEL_B;
3038                         break;
3039                 case PCH_DP_C:
3040                         temp |= TRANS_DP_PORT_SEL_C;
3041                         break;
3042                 case PCH_DP_D:
3043                         temp |= TRANS_DP_PORT_SEL_D;
3044                         break;
3045                 default:
3046                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3047                         temp |= TRANS_DP_PORT_SEL_B;
3048                         break;
3049                 }
3050
3051                 I915_WRITE(reg, temp);
3052         }
3053
3054         intel_enable_transcoder(dev_priv, pipe);
3055 }
3056
3057 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058 {
3059         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061         if (pll == NULL)
3062                 return;
3063
3064         if (pll->refcount == 0) {
3065                 WARN(1, "bad PCH PLL refcount\n");
3066                 return;
3067         }
3068
3069         --pll->refcount;
3070         intel_crtc->pch_pll = NULL;
3071 }
3072
3073 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074 {
3075         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076         struct intel_pch_pll *pll;
3077         int i;
3078
3079         pll = intel_crtc->pch_pll;
3080         if (pll) {
3081                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082                               intel_crtc->base.base.id, pll->pll_reg);
3083                 goto prepare;
3084         }
3085
3086         if (HAS_PCH_IBX(dev_priv->dev)) {
3087                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088                 i = intel_crtc->pipe;
3089                 pll = &dev_priv->pch_plls[i];
3090
3091                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092                               intel_crtc->base.base.id, pll->pll_reg);
3093
3094                 goto found;
3095         }
3096
3097         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098                 pll = &dev_priv->pch_plls[i];
3099
3100                 /* Only want to check enabled timings first */
3101                 if (pll->refcount == 0)
3102                         continue;
3103
3104                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105                     fp == I915_READ(pll->fp0_reg)) {
3106                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107                                       intel_crtc->base.base.id,
3108                                       pll->pll_reg, pll->refcount, pll->active);
3109
3110                         goto found;
3111                 }
3112         }
3113
3114         /* Ok no matching timings, maybe there's a free one? */
3115         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116                 pll = &dev_priv->pch_plls[i];
3117                 if (pll->refcount == 0) {
3118                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119                                       intel_crtc->base.base.id, pll->pll_reg);
3120                         goto found;
3121                 }
3122         }
3123
3124         return NULL;
3125
3126 found:
3127         intel_crtc->pch_pll = pll;
3128         pll->refcount++;
3129         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3130 prepare: /* separate function? */
3131         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3132
3133         /* Wait for the clocks to stabilize before rewriting the regs */
3134         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3135         POSTING_READ(pll->pll_reg);
3136         udelay(150);
3137
3138         I915_WRITE(pll->fp0_reg, fp);
3139         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3140         pll->on = false;
3141         return pll;
3142 }
3143
3144 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3148         u32 temp;
3149
3150         temp = I915_READ(dslreg);
3151         udelay(500);
3152         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153                 /* Without this, mode sets may fail silently on FDI */
3154                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3155                 udelay(250);
3156                 I915_WRITE(tc2reg, 0);
3157                 if (wait_for(I915_READ(dslreg) != temp, 5))
3158                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3159         }
3160 }
3161
3162 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3163 {
3164         struct drm_device *dev = crtc->dev;
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167         struct intel_encoder *encoder;
3168         int pipe = intel_crtc->pipe;
3169         int plane = intel_crtc->plane;
3170         u32 temp;
3171         bool is_pch_port;
3172
3173         WARN_ON(!crtc->enabled);
3174
3175         if (intel_crtc->active)
3176                 return;
3177
3178         intel_crtc->active = true;
3179         intel_update_watermarks(dev);
3180
3181         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3182                 temp = I915_READ(PCH_LVDS);
3183                 if ((temp & LVDS_PORT_EN) == 0)
3184                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3185         }
3186
3187         is_pch_port = intel_crtc_driving_pch(crtc);
3188
3189         if (is_pch_port) {
3190                 ironlake_fdi_pll_enable(intel_crtc);
3191         } else {
3192                 assert_fdi_tx_disabled(dev_priv, pipe);
3193                 assert_fdi_rx_disabled(dev_priv, pipe);
3194         }
3195
3196         for_each_encoder_on_crtc(dev, crtc, encoder)
3197                 if (encoder->pre_enable)
3198                         encoder->pre_enable(encoder);
3199
3200         if (IS_HASWELL(dev))
3201                 intel_ddi_enable_pipe_clock(intel_crtc);
3202
3203         /* Enable panel fitting for LVDS */
3204         if (dev_priv->pch_pf_size &&
3205             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3206                 /* Force use of hard-coded filter coefficients
3207                  * as some pre-programmed values are broken,
3208                  * e.g. x201.
3209                  */
3210                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3211                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3212                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3213         }
3214
3215         /*
3216          * On ILK+ LUT must be loaded before the pipe is running but with
3217          * clocks enabled
3218          */
3219         intel_crtc_load_lut(crtc);
3220
3221         if (IS_HASWELL(dev))
3222                 intel_ddi_enable_pipe_func(crtc);
3223
3224         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3225         intel_enable_plane(dev_priv, plane, pipe);
3226
3227         if (is_pch_port)
3228                 ironlake_pch_enable(crtc);
3229
3230         mutex_lock(&dev->struct_mutex);
3231         intel_update_fbc(dev);
3232         mutex_unlock(&dev->struct_mutex);
3233
3234         intel_crtc_update_cursor(crtc, true);
3235
3236         for_each_encoder_on_crtc(dev, crtc, encoder)
3237                 encoder->enable(encoder);
3238
3239         if (HAS_PCH_CPT(dev))
3240                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3241 }
3242
3243 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3244 {
3245         struct drm_device *dev = crtc->dev;
3246         struct drm_i915_private *dev_priv = dev->dev_private;
3247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3248         struct intel_encoder *encoder;
3249         int pipe = intel_crtc->pipe;
3250         int plane = intel_crtc->plane;
3251         u32 reg, temp;
3252
3253
3254         if (!intel_crtc->active)
3255                 return;
3256
3257         for_each_encoder_on_crtc(dev, crtc, encoder)
3258                 encoder->disable(encoder);
3259
3260         intel_crtc_wait_for_pending_flips(crtc);
3261         drm_vblank_off(dev, pipe);
3262         intel_crtc_update_cursor(crtc, false);
3263
3264         intel_disable_plane(dev_priv, plane, pipe);
3265
3266         if (dev_priv->cfb_plane == plane)
3267                 intel_disable_fbc(dev);
3268
3269         intel_disable_pipe(dev_priv, pipe);
3270
3271         if (IS_HASWELL(dev))
3272                 intel_ddi_disable_pipe_func(dev_priv, pipe);
3273
3274         /* Disable PF */
3275         I915_WRITE(PF_CTL(pipe), 0);
3276         I915_WRITE(PF_WIN_SZ(pipe), 0);
3277
3278         if (IS_HASWELL(dev))
3279                 intel_ddi_disable_pipe_clock(intel_crtc);
3280
3281         for_each_encoder_on_crtc(dev, crtc, encoder)
3282                 if (encoder->post_disable)
3283                         encoder->post_disable(encoder);
3284
3285         ironlake_fdi_disable(crtc);
3286
3287         intel_disable_transcoder(dev_priv, pipe);
3288
3289         if (HAS_PCH_CPT(dev)) {
3290                 /* disable TRANS_DP_CTL */
3291                 reg = TRANS_DP_CTL(pipe);
3292                 temp = I915_READ(reg);
3293                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3294                 temp |= TRANS_DP_PORT_SEL_NONE;
3295                 I915_WRITE(reg, temp);
3296
3297                 /* disable DPLL_SEL */
3298                 temp = I915_READ(PCH_DPLL_SEL);
3299                 switch (pipe) {
3300                 case 0:
3301                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3302                         break;
3303                 case 1:
3304                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3305                         break;
3306                 case 2:
3307                         /* C shares PLL A or B */
3308                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3309                         break;
3310                 default:
3311                         BUG(); /* wtf */
3312                 }
3313                 I915_WRITE(PCH_DPLL_SEL, temp);
3314         }
3315
3316         /* disable PCH DPLL */
3317         intel_disable_pch_pll(intel_crtc);
3318
3319         ironlake_fdi_pll_disable(intel_crtc);
3320
3321         intel_crtc->active = false;
3322         intel_update_watermarks(dev);
3323
3324         mutex_lock(&dev->struct_mutex);
3325         intel_update_fbc(dev);
3326         mutex_unlock(&dev->struct_mutex);
3327 }
3328
3329 static void ironlake_crtc_off(struct drm_crtc *crtc)
3330 {
3331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3332         intel_put_pch_pll(intel_crtc);
3333 }
3334
3335 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3336 {
3337         if (!enable && intel_crtc->overlay) {
3338                 struct drm_device *dev = intel_crtc->base.dev;
3339                 struct drm_i915_private *dev_priv = dev->dev_private;
3340
3341                 mutex_lock(&dev->struct_mutex);
3342                 dev_priv->mm.interruptible = false;
3343                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3344                 dev_priv->mm.interruptible = true;
3345                 mutex_unlock(&dev->struct_mutex);
3346         }
3347
3348         /* Let userspace switch the overlay on again. In most cases userspace
3349          * has to recompute where to put it anyway.
3350          */
3351 }
3352
3353 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3354 {
3355         struct drm_device *dev = crtc->dev;
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3358         struct intel_encoder *encoder;
3359         int pipe = intel_crtc->pipe;
3360         int plane = intel_crtc->plane;
3361
3362         WARN_ON(!crtc->enabled);
3363
3364         if (intel_crtc->active)
3365                 return;
3366
3367         intel_crtc->active = true;
3368         intel_update_watermarks(dev);
3369
3370         intel_enable_pll(dev_priv, pipe);
3371         intel_enable_pipe(dev_priv, pipe, false);
3372         intel_enable_plane(dev_priv, plane, pipe);
3373
3374         intel_crtc_load_lut(crtc);
3375         intel_update_fbc(dev);
3376
3377         /* Give the overlay scaler a chance to enable if it's on this pipe */
3378         intel_crtc_dpms_overlay(intel_crtc, true);
3379         intel_crtc_update_cursor(crtc, true);
3380
3381         for_each_encoder_on_crtc(dev, crtc, encoder)
3382                 encoder->enable(encoder);
3383 }
3384
3385 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3386 {
3387         struct drm_device *dev = crtc->dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390         struct intel_encoder *encoder;
3391         int pipe = intel_crtc->pipe;
3392         int plane = intel_crtc->plane;
3393
3394
3395         if (!intel_crtc->active)
3396                 return;
3397
3398         for_each_encoder_on_crtc(dev, crtc, encoder)
3399                 encoder->disable(encoder);
3400
3401         /* Give the overlay scaler a chance to disable if it's on this pipe */
3402         intel_crtc_wait_for_pending_flips(crtc);
3403         drm_vblank_off(dev, pipe);
3404         intel_crtc_dpms_overlay(intel_crtc, false);
3405         intel_crtc_update_cursor(crtc, false);
3406
3407         if (dev_priv->cfb_plane == plane)
3408                 intel_disable_fbc(dev);
3409
3410         intel_disable_plane(dev_priv, plane, pipe);
3411         intel_disable_pipe(dev_priv, pipe);
3412         intel_disable_pll(dev_priv, pipe);
3413
3414         intel_crtc->active = false;
3415         intel_update_fbc(dev);
3416         intel_update_watermarks(dev);
3417 }
3418
3419 static void i9xx_crtc_off(struct drm_crtc *crtc)
3420 {
3421 }
3422
3423 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3424                                     bool enabled)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         struct drm_i915_master_private *master_priv;
3428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429         int pipe = intel_crtc->pipe;
3430
3431         if (!dev->primary->master)
3432                 return;
3433
3434         master_priv = dev->primary->master->driver_priv;
3435         if (!master_priv->sarea_priv)
3436                 return;
3437
3438         switch (pipe) {
3439         case 0:
3440                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3441                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3442                 break;
3443         case 1:
3444                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3445                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3446                 break;
3447         default:
3448                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3449                 break;
3450         }
3451 }
3452
3453 /**
3454  * Sets the power management mode of the pipe and plane.
3455  */
3456 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3457 {
3458         struct drm_device *dev = crtc->dev;
3459         struct drm_i915_private *dev_priv = dev->dev_private;
3460         struct intel_encoder *intel_encoder;
3461         bool enable = false;
3462
3463         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3464                 enable |= intel_encoder->connectors_active;
3465
3466         if (enable)
3467                 dev_priv->display.crtc_enable(crtc);
3468         else
3469                 dev_priv->display.crtc_disable(crtc);
3470
3471         intel_crtc_update_sarea(crtc, enable);
3472 }
3473
3474 static void intel_crtc_noop(struct drm_crtc *crtc)
3475 {
3476 }
3477
3478 static void intel_crtc_disable(struct drm_crtc *crtc)
3479 {
3480         struct drm_device *dev = crtc->dev;
3481         struct drm_connector *connector;
3482         struct drm_i915_private *dev_priv = dev->dev_private;
3483
3484         /* crtc should still be enabled when we disable it. */
3485         WARN_ON(!crtc->enabled);
3486
3487         dev_priv->display.crtc_disable(crtc);
3488         intel_crtc_update_sarea(crtc, false);
3489         dev_priv->display.off(crtc);
3490
3491         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3492         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3493
3494         if (crtc->fb) {
3495                 mutex_lock(&dev->struct_mutex);
3496                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3497                 mutex_unlock(&dev->struct_mutex);
3498                 crtc->fb = NULL;
3499         }
3500
3501         /* Update computed state. */
3502         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3503                 if (!connector->encoder || !connector->encoder->crtc)
3504                         continue;
3505
3506                 if (connector->encoder->crtc != crtc)
3507                         continue;
3508
3509                 connector->dpms = DRM_MODE_DPMS_OFF;
3510                 to_intel_encoder(connector->encoder)->connectors_active = false;
3511         }
3512 }
3513
3514 void intel_modeset_disable(struct drm_device *dev)
3515 {
3516         struct drm_crtc *crtc;
3517
3518         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3519                 if (crtc->enabled)
3520                         intel_crtc_disable(crtc);
3521         }
3522 }
3523
3524 void intel_encoder_noop(struct drm_encoder *encoder)
3525 {
3526 }
3527
3528 void intel_encoder_destroy(struct drm_encoder *encoder)
3529 {
3530         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3531
3532         drm_encoder_cleanup(encoder);
3533         kfree(intel_encoder);
3534 }
3535
3536 /* Simple dpms helper for encodres with just one connector, no cloning and only
3537  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3538  * state of the entire output pipe. */
3539 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3540 {
3541         if (mode == DRM_MODE_DPMS_ON) {
3542                 encoder->connectors_active = true;
3543
3544                 intel_crtc_update_dpms(encoder->base.crtc);
3545         } else {
3546                 encoder->connectors_active = false;
3547
3548                 intel_crtc_update_dpms(encoder->base.crtc);
3549         }
3550 }
3551
3552 /* Cross check the actual hw state with our own modeset state tracking (and it's
3553  * internal consistency). */
3554 static void intel_connector_check_state(struct intel_connector *connector)
3555 {
3556         if (connector->get_hw_state(connector)) {
3557                 struct intel_encoder *encoder = connector->encoder;
3558                 struct drm_crtc *crtc;
3559                 bool encoder_enabled;
3560                 enum pipe pipe;
3561
3562                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3563                               connector->base.base.id,
3564                               drm_get_connector_name(&connector->base));
3565
3566                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3567                      "wrong connector dpms state\n");
3568                 WARN(connector->base.encoder != &encoder->base,
3569                      "active connector not linked to encoder\n");
3570                 WARN(!encoder->connectors_active,
3571                      "encoder->connectors_active not set\n");
3572
3573                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3574                 WARN(!encoder_enabled, "encoder not enabled\n");
3575                 if (WARN_ON(!encoder->base.crtc))
3576                         return;
3577
3578                 crtc = encoder->base.crtc;
3579
3580                 WARN(!crtc->enabled, "crtc not enabled\n");
3581                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3582                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3583                      "encoder active on the wrong pipe\n");
3584         }
3585 }
3586
3587 /* Even simpler default implementation, if there's really no special case to
3588  * consider. */
3589 void intel_connector_dpms(struct drm_connector *connector, int mode)
3590 {
3591         struct intel_encoder *encoder = intel_attached_encoder(connector);
3592
3593         /* All the simple cases only support two dpms states. */
3594         if (mode != DRM_MODE_DPMS_ON)
3595                 mode = DRM_MODE_DPMS_OFF;
3596
3597         if (mode == connector->dpms)
3598                 return;
3599
3600         connector->dpms = mode;
3601
3602         /* Only need to change hw state when actually enabled */
3603         if (encoder->base.crtc)
3604                 intel_encoder_dpms(encoder, mode);
3605         else
3606                 WARN_ON(encoder->connectors_active != false);
3607
3608         intel_modeset_check_state(connector->dev);
3609 }
3610
3611 /* Simple connector->get_hw_state implementation for encoders that support only
3612  * one connector and no cloning and hence the encoder state determines the state
3613  * of the connector. */
3614 bool intel_connector_get_hw_state(struct intel_connector *connector)
3615 {
3616         enum pipe pipe = 0;
3617         struct intel_encoder *encoder = connector->encoder;
3618
3619         return encoder->get_hw_state(encoder, &pipe);
3620 }
3621
3622 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3623                                   const struct drm_display_mode *mode,
3624                                   struct drm_display_mode *adjusted_mode)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627
3628         if (HAS_PCH_SPLIT(dev)) {
3629                 /* FDI link clock is fixed at 2.7G */
3630                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3631                         return false;
3632         }
3633
3634         /* All interlaced capable intel hw wants timings in frames. Note though
3635          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3636          * timings, so we need to be careful not to clobber these.*/
3637         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3638                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3639
3640         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3641          * with a hsync front porch of 0.
3642          */
3643         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3644                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3645                 return false;
3646
3647         return true;
3648 }
3649
3650 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3651 {
3652         return 400000; /* FIXME */
3653 }
3654
3655 static int i945_get_display_clock_speed(struct drm_device *dev)
3656 {
3657         return 400000;
3658 }
3659
3660 static int i915_get_display_clock_speed(struct drm_device *dev)
3661 {
3662         return 333000;
3663 }
3664
3665 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3666 {
3667         return 200000;
3668 }
3669
3670 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3671 {
3672         u16 gcfgc = 0;
3673
3674         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3675
3676         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3677                 return 133000;
3678         else {
3679                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3680                 case GC_DISPLAY_CLOCK_333_MHZ:
3681                         return 333000;
3682                 default:
3683                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3684                         return 190000;
3685                 }
3686         }
3687 }
3688
3689 static int i865_get_display_clock_speed(struct drm_device *dev)
3690 {
3691         return 266000;
3692 }
3693
3694 static int i855_get_display_clock_speed(struct drm_device *dev)
3695 {
3696         u16 hpllcc = 0;
3697         /* Assume that the hardware is in the high speed state.  This
3698          * should be the default.
3699          */
3700         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3701         case GC_CLOCK_133_200:
3702         case GC_CLOCK_100_200:
3703                 return 200000;
3704         case GC_CLOCK_166_250:
3705                 return 250000;
3706         case GC_CLOCK_100_133:
3707                 return 133000;
3708         }
3709
3710         /* Shouldn't happen */
3711         return 0;
3712 }
3713
3714 static int i830_get_display_clock_speed(struct drm_device *dev)
3715 {
3716         return 133000;
3717 }
3718
3719 struct fdi_m_n {
3720         u32        tu;
3721         u32        gmch_m;
3722         u32        gmch_n;
3723         u32        link_m;
3724         u32        link_n;
3725 };
3726
3727 static void
3728 fdi_reduce_ratio(u32 *num, u32 *den)
3729 {
3730         while (*num > 0xffffff || *den > 0xffffff) {
3731                 *num >>= 1;
3732                 *den >>= 1;
3733         }
3734 }
3735
3736 static void
3737 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3738                      int link_clock, struct fdi_m_n *m_n)
3739 {
3740         m_n->tu = 64; /* default size */
3741
3742         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3743         m_n->gmch_m = bits_per_pixel * pixel_clock;
3744         m_n->gmch_n = link_clock * nlanes * 8;
3745         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3746
3747         m_n->link_m = pixel_clock;
3748         m_n->link_n = link_clock;
3749         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3750 }
3751
3752 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3753 {
3754         if (i915_panel_use_ssc >= 0)
3755                 return i915_panel_use_ssc != 0;
3756         return dev_priv->lvds_use_ssc
3757                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3758 }
3759
3760 /**
3761  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3762  * @crtc: CRTC structure
3763  * @mode: requested mode
3764  *
3765  * A pipe may be connected to one or more outputs.  Based on the depth of the
3766  * attached framebuffer, choose a good color depth to use on the pipe.
3767  *
3768  * If possible, match the pipe depth to the fb depth.  In some cases, this
3769  * isn't ideal, because the connected output supports a lesser or restricted
3770  * set of depths.  Resolve that here:
3771  *    LVDS typically supports only 6bpc, so clamp down in that case
3772  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3773  *    Displays may support a restricted set as well, check EDID and clamp as
3774  *      appropriate.
3775  *    DP may want to dither down to 6bpc to fit larger modes
3776  *
3777  * RETURNS:
3778  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3779  * true if they don't match).
3780  */
3781 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3782                                          struct drm_framebuffer *fb,
3783                                          unsigned int *pipe_bpp,
3784                                          struct drm_display_mode *mode)
3785 {
3786         struct drm_device *dev = crtc->dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         struct drm_connector *connector;
3789         struct intel_encoder *intel_encoder;
3790         unsigned int display_bpc = UINT_MAX, bpc;
3791
3792         /* Walk the encoders & connectors on this crtc, get min bpc */
3793         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3794
3795                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3796                         unsigned int lvds_bpc;
3797
3798                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3799                             LVDS_A3_POWER_UP)
3800                                 lvds_bpc = 8;
3801                         else
3802                                 lvds_bpc = 6;
3803
3804                         if (lvds_bpc < display_bpc) {
3805                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3806                                 display_bpc = lvds_bpc;
3807                         }
3808                         continue;
3809                 }
3810
3811                 /* Not one of the known troublemakers, check the EDID */
3812                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3813                                     head) {
3814                         if (connector->encoder != &intel_encoder->base)
3815                                 continue;
3816
3817                         /* Don't use an invalid EDID bpc value */
3818                         if (connector->display_info.bpc &&
3819                             connector->display_info.bpc < display_bpc) {
3820                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3821                                 display_bpc = connector->display_info.bpc;
3822                         }
3823                 }
3824
3825                 /*
3826                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3827                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3828                  */
3829                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3830                         if (display_bpc > 8 && display_bpc < 12) {
3831                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3832                                 display_bpc = 12;
3833                         } else {
3834                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3835                                 display_bpc = 8;
3836                         }
3837                 }
3838         }
3839
3840         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3841                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3842                 display_bpc = 6;
3843         }
3844
3845         /*
3846          * We could just drive the pipe at the highest bpc all the time and
3847          * enable dithering as needed, but that costs bandwidth.  So choose
3848          * the minimum value that expresses the full color range of the fb but
3849          * also stays within the max display bpc discovered above.
3850          */
3851
3852         switch (fb->depth) {
3853         case 8:
3854                 bpc = 8; /* since we go through a colormap */
3855                 break;
3856         case 15:
3857         case 16:
3858                 bpc = 6; /* min is 18bpp */
3859                 break;
3860         case 24:
3861                 bpc = 8;
3862                 break;
3863         case 30:
3864                 bpc = 10;
3865                 break;
3866         case 48:
3867                 bpc = 12;
3868                 break;
3869         default:
3870                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3871                 bpc = min((unsigned int)8, display_bpc);
3872                 break;
3873         }
3874
3875         display_bpc = min(display_bpc, bpc);
3876
3877         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3878                       bpc, display_bpc);
3879
3880         *pipe_bpp = display_bpc * 3;
3881
3882         return display_bpc != bpc;
3883 }
3884
3885 static int vlv_get_refclk(struct drm_crtc *crtc)
3886 {
3887         struct drm_device *dev = crtc->dev;
3888         struct drm_i915_private *dev_priv = dev->dev_private;
3889         int refclk = 27000; /* for DP & HDMI */
3890
3891         return 100000; /* only one validated so far */
3892
3893         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3894                 refclk = 96000;
3895         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3896                 if (intel_panel_use_ssc(dev_priv))
3897                         refclk = 100000;
3898                 else
3899                         refclk = 96000;
3900         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3901                 refclk = 100000;
3902         }
3903
3904         return refclk;
3905 }
3906
3907 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3908 {
3909         struct drm_device *dev = crtc->dev;
3910         struct drm_i915_private *dev_priv = dev->dev_private;
3911         int refclk;
3912
3913         if (IS_VALLEYVIEW(dev)) {
3914                 refclk = vlv_get_refclk(crtc);
3915         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3916             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3917                 refclk = dev_priv->lvds_ssc_freq * 1000;
3918                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3919                               refclk / 1000);
3920         } else if (!IS_GEN2(dev)) {
3921                 refclk = 96000;
3922         } else {
3923                 refclk = 48000;
3924         }
3925
3926         return refclk;
3927 }
3928
3929 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3930                                       intel_clock_t *clock)
3931 {
3932         /* SDVO TV has fixed PLL values depend on its clock range,
3933            this mirrors vbios setting. */
3934         if (adjusted_mode->clock >= 100000
3935             && adjusted_mode->clock < 140500) {
3936                 clock->p1 = 2;
3937                 clock->p2 = 10;
3938                 clock->n = 3;
3939                 clock->m1 = 16;
3940                 clock->m2 = 8;
3941         } else if (adjusted_mode->clock >= 140500
3942                    && adjusted_mode->clock <= 200000) {
3943                 clock->p1 = 1;
3944                 clock->p2 = 10;
3945                 clock->n = 6;
3946                 clock->m1 = 12;
3947                 clock->m2 = 8;
3948         }
3949 }
3950
3951 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3952                                      intel_clock_t *clock,
3953                                      intel_clock_t *reduced_clock)
3954 {
3955         struct drm_device *dev = crtc->dev;
3956         struct drm_i915_private *dev_priv = dev->dev_private;
3957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3958         int pipe = intel_crtc->pipe;
3959         u32 fp, fp2 = 0;
3960
3961         if (IS_PINEVIEW(dev)) {
3962                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3963                 if (reduced_clock)
3964                         fp2 = (1 << reduced_clock->n) << 16 |
3965                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3966         } else {
3967                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3968                 if (reduced_clock)
3969                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3970                                 reduced_clock->m2;
3971         }
3972
3973         I915_WRITE(FP0(pipe), fp);
3974
3975         intel_crtc->lowfreq_avail = false;
3976         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3977             reduced_clock && i915_powersave) {
3978                 I915_WRITE(FP1(pipe), fp2);
3979                 intel_crtc->lowfreq_avail = true;
3980         } else {
3981                 I915_WRITE(FP1(pipe), fp);
3982         }
3983 }
3984
3985 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3986                               struct drm_display_mode *adjusted_mode)
3987 {
3988         struct drm_device *dev = crtc->dev;
3989         struct drm_i915_private *dev_priv = dev->dev_private;
3990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3991         int pipe = intel_crtc->pipe;
3992         u32 temp;
3993
3994         temp = I915_READ(LVDS);
3995         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3996         if (pipe == 1) {
3997                 temp |= LVDS_PIPEB_SELECT;
3998         } else {
3999                 temp &= ~LVDS_PIPEB_SELECT;
4000         }
4001         /* set the corresponsding LVDS_BORDER bit */
4002         temp |= dev_priv->lvds_border_bits;
4003         /* Set the B0-B3 data pairs corresponding to whether we're going to
4004          * set the DPLLs for dual-channel mode or not.
4005          */
4006         if (clock->p2 == 7)
4007                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4008         else
4009                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4010
4011         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4012          * appropriately here, but we need to look more thoroughly into how
4013          * panels behave in the two modes.
4014          */
4015         /* set the dithering flag on LVDS as needed */
4016         if (INTEL_INFO(dev)->gen >= 4) {
4017                 if (dev_priv->lvds_dither)
4018                         temp |= LVDS_ENABLE_DITHER;
4019                 else
4020                         temp &= ~LVDS_ENABLE_DITHER;
4021         }
4022         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4023         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4024                 temp |= LVDS_HSYNC_POLARITY;
4025         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4026                 temp |= LVDS_VSYNC_POLARITY;
4027         I915_WRITE(LVDS, temp);
4028 }
4029
4030 static void vlv_update_pll(struct drm_crtc *crtc,
4031                            struct drm_display_mode *mode,
4032                            struct drm_display_mode *adjusted_mode,
4033                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4034                            int num_connectors)
4035 {
4036         struct drm_device *dev = crtc->dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         int pipe = intel_crtc->pipe;
4040         u32 dpll, mdiv, pdiv;
4041         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4042         bool is_sdvo;
4043         u32 temp;
4044
4045         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4046                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4047
4048         dpll = DPLL_VGA_MODE_DIS;
4049         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4050         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4051         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4052
4053         I915_WRITE(DPLL(pipe), dpll);
4054         POSTING_READ(DPLL(pipe));
4055
4056         bestn = clock->n;
4057         bestm1 = clock->m1;
4058         bestm2 = clock->m2;
4059         bestp1 = clock->p1;
4060         bestp2 = clock->p2;
4061
4062         /*
4063          * In Valleyview PLL and program lane counter registers are exposed
4064          * through DPIO interface
4065          */
4066         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4067         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4068         mdiv |= ((bestn << DPIO_N_SHIFT));
4069         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4070         mdiv |= (1 << DPIO_K_SHIFT);
4071         mdiv |= DPIO_ENABLE_CALIBRATION;
4072         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4073
4074         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4075
4076         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4077                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4078                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4079                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4080         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4081
4082         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4083
4084         dpll |= DPLL_VCO_ENABLE;
4085         I915_WRITE(DPLL(pipe), dpll);
4086         POSTING_READ(DPLL(pipe));
4087         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4088                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4089
4090         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4091
4092         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4093                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4094
4095         I915_WRITE(DPLL(pipe), dpll);
4096
4097         /* Wait for the clocks to stabilize. */
4098         POSTING_READ(DPLL(pipe));
4099         udelay(150);
4100
4101         temp = 0;
4102         if (is_sdvo) {
4103                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4104                 if (temp > 1)
4105                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4106                 else
4107                         temp = 0;
4108         }
4109         I915_WRITE(DPLL_MD(pipe), temp);
4110         POSTING_READ(DPLL_MD(pipe));
4111
4112         /* Now program lane control registers */
4113         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4114                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4115         {
4116                 temp = 0x1000C4;
4117                 if(pipe == 1)
4118                         temp |= (1 << 21);
4119                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4120         }
4121         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4122         {
4123                 temp = 0x1000C4;
4124                 if(pipe == 1)
4125                         temp |= (1 << 21);
4126                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4127         }
4128 }
4129
4130 static void i9xx_update_pll(struct drm_crtc *crtc,
4131                             struct drm_display_mode *mode,
4132                             struct drm_display_mode *adjusted_mode,
4133                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4134                             int num_connectors)
4135 {
4136         struct drm_device *dev = crtc->dev;
4137         struct drm_i915_private *dev_priv = dev->dev_private;
4138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139         int pipe = intel_crtc->pipe;
4140         u32 dpll;
4141         bool is_sdvo;
4142
4143         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4144
4145         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4146                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4147
4148         dpll = DPLL_VGA_MODE_DIS;
4149
4150         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4151                 dpll |= DPLLB_MODE_LVDS;
4152         else
4153                 dpll |= DPLLB_MODE_DAC_SERIAL;
4154         if (is_sdvo) {
4155                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4156                 if (pixel_multiplier > 1) {
4157                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4158                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4159                 }
4160                 dpll |= DPLL_DVO_HIGH_SPEED;
4161         }
4162         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4163                 dpll |= DPLL_DVO_HIGH_SPEED;
4164
4165         /* compute bitmask from p1 value */
4166         if (IS_PINEVIEW(dev))
4167                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4168         else {
4169                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170                 if (IS_G4X(dev) && reduced_clock)
4171                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4172         }
4173         switch (clock->p2) {
4174         case 5:
4175                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4176                 break;
4177         case 7:
4178                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4179                 break;
4180         case 10:
4181                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4182                 break;
4183         case 14:
4184                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4185                 break;
4186         }
4187         if (INTEL_INFO(dev)->gen >= 4)
4188                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4189
4190         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4191                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4192         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4193                 /* XXX: just matching BIOS for now */
4194                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4195                 dpll |= 3;
4196         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4197                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4198                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4199         else
4200                 dpll |= PLL_REF_INPUT_DREFCLK;
4201
4202         dpll |= DPLL_VCO_ENABLE;
4203         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4204         POSTING_READ(DPLL(pipe));
4205         udelay(150);
4206
4207         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4208          * This is an exception to the general rule that mode_set doesn't turn
4209          * things on.
4210          */
4211         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4212                 intel_update_lvds(crtc, clock, adjusted_mode);
4213
4214         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4215                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4216
4217         I915_WRITE(DPLL(pipe), dpll);
4218
4219         /* Wait for the clocks to stabilize. */
4220         POSTING_READ(DPLL(pipe));
4221         udelay(150);
4222
4223         if (INTEL_INFO(dev)->gen >= 4) {
4224                 u32 temp = 0;
4225                 if (is_sdvo) {
4226                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4227                         if (temp > 1)
4228                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4229                         else
4230                                 temp = 0;
4231                 }
4232                 I915_WRITE(DPLL_MD(pipe), temp);
4233         } else {
4234                 /* The pixel multiplier can only be updated once the
4235                  * DPLL is enabled and the clocks are stable.
4236                  *
4237                  * So write it again.
4238                  */
4239                 I915_WRITE(DPLL(pipe), dpll);
4240         }
4241 }
4242
4243 static void i8xx_update_pll(struct drm_crtc *crtc,
4244                             struct drm_display_mode *adjusted_mode,
4245                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4246                             int num_connectors)
4247 {
4248         struct drm_device *dev = crtc->dev;
4249         struct drm_i915_private *dev_priv = dev->dev_private;
4250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251         int pipe = intel_crtc->pipe;
4252         u32 dpll;
4253
4254         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4255
4256         dpll = DPLL_VGA_MODE_DIS;
4257
4258         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4259                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4260         } else {
4261                 if (clock->p1 == 2)
4262                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4263                 else
4264                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4265                 if (clock->p2 == 4)
4266                         dpll |= PLL_P2_DIVIDE_BY_4;
4267         }
4268
4269         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4270                 /* XXX: just matching BIOS for now */
4271                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4272                 dpll |= 3;
4273         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4274                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4275                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4276         else
4277                 dpll |= PLL_REF_INPUT_DREFCLK;
4278
4279         dpll |= DPLL_VCO_ENABLE;
4280         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4281         POSTING_READ(DPLL(pipe));
4282         udelay(150);
4283
4284         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4285          * This is an exception to the general rule that mode_set doesn't turn
4286          * things on.
4287          */
4288         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4289                 intel_update_lvds(crtc, clock, adjusted_mode);
4290
4291         I915_WRITE(DPLL(pipe), dpll);
4292
4293         /* Wait for the clocks to stabilize. */
4294         POSTING_READ(DPLL(pipe));
4295         udelay(150);
4296
4297         /* The pixel multiplier can only be updated once the
4298          * DPLL is enabled and the clocks are stable.
4299          *
4300          * So write it again.
4301          */
4302         I915_WRITE(DPLL(pipe), dpll);
4303 }
4304
4305 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4306                                    struct drm_display_mode *mode,
4307                                    struct drm_display_mode *adjusted_mode)
4308 {
4309         struct drm_device *dev = intel_crtc->base.dev;
4310         struct drm_i915_private *dev_priv = dev->dev_private;
4311         enum pipe pipe = intel_crtc->pipe;
4312         uint32_t vsyncshift;
4313
4314         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4315                 /* the chip adds 2 halflines automatically */
4316                 adjusted_mode->crtc_vtotal -= 1;
4317                 adjusted_mode->crtc_vblank_end -= 1;
4318                 vsyncshift = adjusted_mode->crtc_hsync_start
4319                              - adjusted_mode->crtc_htotal / 2;
4320         } else {
4321                 vsyncshift = 0;
4322         }
4323
4324         if (INTEL_INFO(dev)->gen > 3)
4325                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4326
4327         I915_WRITE(HTOTAL(pipe),
4328                    (adjusted_mode->crtc_hdisplay - 1) |
4329                    ((adjusted_mode->crtc_htotal - 1) << 16));
4330         I915_WRITE(HBLANK(pipe),
4331                    (adjusted_mode->crtc_hblank_start - 1) |
4332                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4333         I915_WRITE(HSYNC(pipe),
4334                    (adjusted_mode->crtc_hsync_start - 1) |
4335                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4336
4337         I915_WRITE(VTOTAL(pipe),
4338                    (adjusted_mode->crtc_vdisplay - 1) |
4339                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4340         I915_WRITE(VBLANK(pipe),
4341                    (adjusted_mode->crtc_vblank_start - 1) |
4342                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4343         I915_WRITE(VSYNC(pipe),
4344                    (adjusted_mode->crtc_vsync_start - 1) |
4345                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4346
4347         /* pipesrc controls the size that is scaled from, which should
4348          * always be the user's requested size.
4349          */
4350         I915_WRITE(PIPESRC(pipe),
4351                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4352 }
4353
4354 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4355                               struct drm_display_mode *mode,
4356                               struct drm_display_mode *adjusted_mode,
4357                               int x, int y,
4358                               struct drm_framebuffer *fb)
4359 {
4360         struct drm_device *dev = crtc->dev;
4361         struct drm_i915_private *dev_priv = dev->dev_private;
4362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363         int pipe = intel_crtc->pipe;
4364         int plane = intel_crtc->plane;
4365         int refclk, num_connectors = 0;
4366         intel_clock_t clock, reduced_clock;
4367         u32 dspcntr, pipeconf;
4368         bool ok, has_reduced_clock = false, is_sdvo = false;
4369         bool is_lvds = false, is_tv = false, is_dp = false;
4370         struct intel_encoder *encoder;
4371         const intel_limit_t *limit;
4372         int ret;
4373
4374         for_each_encoder_on_crtc(dev, crtc, encoder) {
4375                 switch (encoder->type) {
4376                 case INTEL_OUTPUT_LVDS:
4377                         is_lvds = true;
4378                         break;
4379                 case INTEL_OUTPUT_SDVO:
4380                 case INTEL_OUTPUT_HDMI:
4381                         is_sdvo = true;
4382                         if (encoder->needs_tv_clock)
4383                                 is_tv = true;
4384                         break;
4385                 case INTEL_OUTPUT_TVOUT:
4386                         is_tv = true;
4387                         break;
4388                 case INTEL_OUTPUT_DISPLAYPORT:
4389                         is_dp = true;
4390                         break;
4391                 }
4392
4393                 num_connectors++;
4394         }
4395
4396         refclk = i9xx_get_refclk(crtc, num_connectors);
4397
4398         /*
4399          * Returns a set of divisors for the desired target clock with the given
4400          * refclk, or FALSE.  The returned values represent the clock equation:
4401          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4402          */
4403         limit = intel_limit(crtc, refclk);
4404         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4405                              &clock);
4406         if (!ok) {
4407                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4408                 return -EINVAL;
4409         }
4410
4411         /* Ensure that the cursor is valid for the new mode before changing... */
4412         intel_crtc_update_cursor(crtc, true);
4413
4414         if (is_lvds && dev_priv->lvds_downclock_avail) {
4415                 /*
4416                  * Ensure we match the reduced clock's P to the target clock.
4417                  * If the clocks don't match, we can't switch the display clock
4418                  * by using the FP0/FP1. In such case we will disable the LVDS
4419                  * downclock feature.
4420                 */
4421                 has_reduced_clock = limit->find_pll(limit, crtc,
4422                                                     dev_priv->lvds_downclock,
4423                                                     refclk,
4424                                                     &clock,
4425                                                     &reduced_clock);
4426         }
4427
4428         if (is_sdvo && is_tv)
4429                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4430
4431         if (IS_GEN2(dev))
4432                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4433                                 has_reduced_clock ? &reduced_clock : NULL,
4434                                 num_connectors);
4435         else if (IS_VALLEYVIEW(dev))
4436                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4437                                 has_reduced_clock ? &reduced_clock : NULL,
4438                                 num_connectors);
4439         else
4440                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4441                                 has_reduced_clock ? &reduced_clock : NULL,
4442                                 num_connectors);
4443
4444         /* setup pipeconf */
4445         pipeconf = I915_READ(PIPECONF(pipe));
4446
4447         /* Set up the display plane register */
4448         dspcntr = DISPPLANE_GAMMA_ENABLE;
4449
4450         if (pipe == 0)
4451                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4452         else
4453                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4454
4455         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4456                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4457                  * core speed.
4458                  *
4459                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4460                  * pipe == 0 check?
4461                  */
4462                 if (mode->clock >
4463                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4464                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4465                 else
4466                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4467         }
4468
4469         /* default to 8bpc */
4470         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4471         if (is_dp) {
4472                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4473                         pipeconf |= PIPECONF_BPP_6 |
4474                                     PIPECONF_DITHER_EN |
4475                                     PIPECONF_DITHER_TYPE_SP;
4476                 }
4477         }
4478
4479         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4480                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4481                         pipeconf |= PIPECONF_BPP_6 |
4482                                         PIPECONF_ENABLE |
4483                                         I965_PIPECONF_ACTIVE;
4484                 }
4485         }
4486
4487         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4488         drm_mode_debug_printmodeline(mode);
4489
4490         if (HAS_PIPE_CXSR(dev)) {
4491                 if (intel_crtc->lowfreq_avail) {
4492                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4493                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4494                 } else {
4495                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4496                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4497                 }
4498         }
4499
4500         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4501         if (!IS_GEN2(dev) &&
4502             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4503                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4504         else
4505                 pipeconf |= PIPECONF_PROGRESSIVE;
4506
4507         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4508
4509         /* pipesrc and dspsize control the size that is scaled from,
4510          * which should always be the user's requested size.
4511          */
4512         I915_WRITE(DSPSIZE(plane),
4513                    ((mode->vdisplay - 1) << 16) |
4514                    (mode->hdisplay - 1));
4515         I915_WRITE(DSPPOS(plane), 0);
4516
4517         I915_WRITE(PIPECONF(pipe), pipeconf);
4518         POSTING_READ(PIPECONF(pipe));
4519         intel_enable_pipe(dev_priv, pipe, false);
4520
4521         intel_wait_for_vblank(dev, pipe);
4522
4523         I915_WRITE(DSPCNTR(plane), dspcntr);
4524         POSTING_READ(DSPCNTR(plane));
4525
4526         ret = intel_pipe_set_base(crtc, x, y, fb);
4527
4528         intel_update_watermarks(dev);
4529
4530         return ret;
4531 }
4532
4533 /*
4534  * Initialize reference clocks when the driver loads
4535  */
4536 void ironlake_init_pch_refclk(struct drm_device *dev)
4537 {
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539         struct drm_mode_config *mode_config = &dev->mode_config;
4540         struct intel_encoder *encoder;
4541         u32 temp;
4542         bool has_lvds = false;
4543         bool has_cpu_edp = false;
4544         bool has_pch_edp = false;
4545         bool has_panel = false;
4546         bool has_ck505 = false;
4547         bool can_ssc = false;
4548
4549         /* We need to take the global config into account */
4550         list_for_each_entry(encoder, &mode_config->encoder_list,
4551                             base.head) {
4552                 switch (encoder->type) {
4553                 case INTEL_OUTPUT_LVDS:
4554                         has_panel = true;
4555                         has_lvds = true;
4556                         break;
4557                 case INTEL_OUTPUT_EDP:
4558                         has_panel = true;
4559                         if (intel_encoder_is_pch_edp(&encoder->base))
4560                                 has_pch_edp = true;
4561                         else
4562                                 has_cpu_edp = true;
4563                         break;
4564                 }
4565         }
4566
4567         if (HAS_PCH_IBX(dev)) {
4568                 has_ck505 = dev_priv->display_clock_mode;
4569                 can_ssc = has_ck505;
4570         } else {
4571                 has_ck505 = false;
4572                 can_ssc = true;
4573         }
4574
4575         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4576                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4577                       has_ck505);
4578
4579         /* Ironlake: try to setup display ref clock before DPLL
4580          * enabling. This is only under driver's control after
4581          * PCH B stepping, previous chipset stepping should be
4582          * ignoring this setting.
4583          */
4584         temp = I915_READ(PCH_DREF_CONTROL);
4585         /* Always enable nonspread source */
4586         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4587
4588         if (has_ck505)
4589                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4590         else
4591                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4592
4593         if (has_panel) {
4594                 temp &= ~DREF_SSC_SOURCE_MASK;
4595                 temp |= DREF_SSC_SOURCE_ENABLE;
4596
4597                 /* SSC must be turned on before enabling the CPU output  */
4598                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4599                         DRM_DEBUG_KMS("Using SSC on panel\n");
4600                         temp |= DREF_SSC1_ENABLE;
4601                 } else
4602                         temp &= ~DREF_SSC1_ENABLE;
4603
4604                 /* Get SSC going before enabling the outputs */
4605                 I915_WRITE(PCH_DREF_CONTROL, temp);
4606                 POSTING_READ(PCH_DREF_CONTROL);
4607                 udelay(200);
4608
4609                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4610
4611                 /* Enable CPU source on CPU attached eDP */
4612                 if (has_cpu_edp) {
4613                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4614                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4615                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4616                         }
4617                         else
4618                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4619                 } else
4620                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4621
4622                 I915_WRITE(PCH_DREF_CONTROL, temp);
4623                 POSTING_READ(PCH_DREF_CONTROL);
4624                 udelay(200);
4625         } else {
4626                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4627
4628                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4629
4630                 /* Turn off CPU output */
4631                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4632
4633                 I915_WRITE(PCH_DREF_CONTROL, temp);
4634                 POSTING_READ(PCH_DREF_CONTROL);
4635                 udelay(200);
4636
4637                 /* Turn off the SSC source */
4638                 temp &= ~DREF_SSC_SOURCE_MASK;
4639                 temp |= DREF_SSC_SOURCE_DISABLE;
4640
4641                 /* Turn off SSC1 */
4642                 temp &= ~ DREF_SSC1_ENABLE;
4643
4644                 I915_WRITE(PCH_DREF_CONTROL, temp);
4645                 POSTING_READ(PCH_DREF_CONTROL);
4646                 udelay(200);
4647         }
4648 }
4649
4650 static int ironlake_get_refclk(struct drm_crtc *crtc)
4651 {
4652         struct drm_device *dev = crtc->dev;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         struct intel_encoder *encoder;
4655         struct intel_encoder *edp_encoder = NULL;
4656         int num_connectors = 0;
4657         bool is_lvds = false;
4658
4659         for_each_encoder_on_crtc(dev, crtc, encoder) {
4660                 switch (encoder->type) {
4661                 case INTEL_OUTPUT_LVDS:
4662                         is_lvds = true;
4663                         break;
4664                 case INTEL_OUTPUT_EDP:
4665                         edp_encoder = encoder;
4666                         break;
4667                 }
4668                 num_connectors++;
4669         }
4670
4671         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4672                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4673                               dev_priv->lvds_ssc_freq);
4674                 return dev_priv->lvds_ssc_freq * 1000;
4675         }
4676
4677         return 120000;
4678 }
4679
4680 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4681                                   struct drm_display_mode *adjusted_mode,
4682                                   bool dither)
4683 {
4684         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686         int pipe = intel_crtc->pipe;
4687         uint32_t val;
4688
4689         val = I915_READ(PIPECONF(pipe));
4690
4691         val &= ~PIPE_BPC_MASK;
4692         switch (intel_crtc->bpp) {
4693         case 18:
4694                 val |= PIPE_6BPC;
4695                 break;
4696         case 24:
4697                 val |= PIPE_8BPC;
4698                 break;
4699         case 30:
4700                 val |= PIPE_10BPC;
4701                 break;
4702         case 36:
4703                 val |= PIPE_12BPC;
4704                 break;
4705         default:
4706                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4707                 BUG();
4708         }
4709
4710         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4711         if (dither)
4712                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4713
4714         val &= ~PIPECONF_INTERLACE_MASK;
4715         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4716                 val |= PIPECONF_INTERLACED_ILK;
4717         else
4718                 val |= PIPECONF_PROGRESSIVE;
4719
4720         I915_WRITE(PIPECONF(pipe), val);
4721         POSTING_READ(PIPECONF(pipe));
4722 }
4723
4724 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4725                                     struct drm_display_mode *adjusted_mode,
4726                                     intel_clock_t *clock,
4727                                     bool *has_reduced_clock,
4728                                     intel_clock_t *reduced_clock)
4729 {
4730         struct drm_device *dev = crtc->dev;
4731         struct drm_i915_private *dev_priv = dev->dev_private;
4732         struct intel_encoder *intel_encoder;
4733         int refclk;
4734         const intel_limit_t *limit;
4735         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4736
4737         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4738                 switch (intel_encoder->type) {
4739                 case INTEL_OUTPUT_LVDS:
4740                         is_lvds = true;
4741                         break;
4742                 case INTEL_OUTPUT_SDVO:
4743                 case INTEL_OUTPUT_HDMI:
4744                         is_sdvo = true;
4745                         if (intel_encoder->needs_tv_clock)
4746                                 is_tv = true;
4747                         break;
4748                 case INTEL_OUTPUT_TVOUT:
4749                         is_tv = true;
4750                         break;
4751                 }
4752         }
4753
4754         refclk = ironlake_get_refclk(crtc);
4755
4756         /*
4757          * Returns a set of divisors for the desired target clock with the given
4758          * refclk, or FALSE.  The returned values represent the clock equation:
4759          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4760          */
4761         limit = intel_limit(crtc, refclk);
4762         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4763                               clock);
4764         if (!ret)
4765                 return false;
4766
4767         if (is_lvds && dev_priv->lvds_downclock_avail) {
4768                 /*
4769                  * Ensure we match the reduced clock's P to the target clock.
4770                  * If the clocks don't match, we can't switch the display clock
4771                  * by using the FP0/FP1. In such case we will disable the LVDS
4772                  * downclock feature.
4773                 */
4774                 *has_reduced_clock = limit->find_pll(limit, crtc,
4775                                                      dev_priv->lvds_downclock,
4776                                                      refclk,
4777                                                      clock,
4778                                                      reduced_clock);
4779         }
4780
4781         if (is_sdvo && is_tv)
4782                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4783
4784         return true;
4785 }
4786
4787 static void ironlake_set_m_n(struct drm_crtc *crtc,
4788                              struct drm_display_mode *mode,
4789                              struct drm_display_mode *adjusted_mode)
4790 {
4791         struct drm_device *dev = crtc->dev;
4792         struct drm_i915_private *dev_priv = dev->dev_private;
4793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4794         enum pipe pipe = intel_crtc->pipe;
4795         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4796         struct fdi_m_n m_n = {0};
4797         int target_clock, pixel_multiplier, lane, link_bw;
4798         bool is_dp = false, is_cpu_edp = false;
4799
4800         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4801                 switch (intel_encoder->type) {
4802                 case INTEL_OUTPUT_DISPLAYPORT:
4803                         is_dp = true;
4804                         break;
4805                 case INTEL_OUTPUT_EDP:
4806                         is_dp = true;
4807                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4808                                 is_cpu_edp = true;
4809                         edp_encoder = intel_encoder;
4810                         break;
4811                 }
4812         }
4813
4814         /* FDI link */
4815         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4816         lane = 0;
4817         /* CPU eDP doesn't require FDI link, so just set DP M/N
4818            according to current link config */
4819         if (is_cpu_edp) {
4820                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4821         } else {
4822                 /* FDI is a binary signal running at ~2.7GHz, encoding
4823                  * each output octet as 10 bits. The actual frequency
4824                  * is stored as a divider into a 100MHz clock, and the
4825                  * mode pixel clock is stored in units of 1KHz.
4826                  * Hence the bw of each lane in terms of the mode signal
4827                  * is:
4828                  */
4829                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4830         }
4831
4832         /* [e]DP over FDI requires target mode clock instead of link clock. */
4833         if (edp_encoder)
4834                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4835         else if (is_dp)
4836                 target_clock = mode->clock;
4837         else
4838                 target_clock = adjusted_mode->clock;
4839
4840         if (!lane) {
4841                 /*
4842                  * Account for spread spectrum to avoid
4843                  * oversubscribing the link. Max center spread
4844                  * is 2.5%; use 5% for safety's sake.
4845                  */
4846                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4847                 lane = bps / (link_bw * 8) + 1;
4848         }
4849
4850         intel_crtc->fdi_lanes = lane;
4851
4852         if (pixel_multiplier > 1)
4853                 link_bw *= pixel_multiplier;
4854         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4855                              &m_n);
4856
4857         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4858         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4859         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4860         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4861 }
4862
4863 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4864                                       struct drm_display_mode *adjusted_mode,
4865                                       intel_clock_t *clock, u32 fp)
4866 {
4867         struct drm_crtc *crtc = &intel_crtc->base;
4868         struct drm_device *dev = crtc->dev;
4869         struct drm_i915_private *dev_priv = dev->dev_private;
4870         struct intel_encoder *intel_encoder;
4871         uint32_t dpll;
4872         int factor, pixel_multiplier, num_connectors = 0;
4873         bool is_lvds = false, is_sdvo = false, is_tv = false;
4874         bool is_dp = false, is_cpu_edp = false;
4875
4876         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4877                 switch (intel_encoder->type) {
4878                 case INTEL_OUTPUT_LVDS:
4879                         is_lvds = true;
4880                         break;
4881                 case INTEL_OUTPUT_SDVO:
4882                 case INTEL_OUTPUT_HDMI:
4883                         is_sdvo = true;
4884                         if (intel_encoder->needs_tv_clock)
4885                                 is_tv = true;
4886                         break;
4887                 case INTEL_OUTPUT_TVOUT:
4888                         is_tv = true;
4889                         break;
4890                 case INTEL_OUTPUT_DISPLAYPORT:
4891                         is_dp = true;
4892                         break;
4893                 case INTEL_OUTPUT_EDP:
4894                         is_dp = true;
4895                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4896                                 is_cpu_edp = true;
4897                         break;
4898                 }
4899
4900                 num_connectors++;
4901         }
4902
4903         /* Enable autotuning of the PLL clock (if permissible) */
4904         factor = 21;
4905         if (is_lvds) {
4906                 if ((intel_panel_use_ssc(dev_priv) &&
4907                      dev_priv->lvds_ssc_freq == 100) ||
4908                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4909                         factor = 25;
4910         } else if (is_sdvo && is_tv)
4911                 factor = 20;
4912
4913         if (clock->m < factor * clock->n)
4914                 fp |= FP_CB_TUNE;
4915
4916         dpll = 0;
4917
4918         if (is_lvds)
4919                 dpll |= DPLLB_MODE_LVDS;
4920         else
4921                 dpll |= DPLLB_MODE_DAC_SERIAL;
4922         if (is_sdvo) {
4923                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4924                 if (pixel_multiplier > 1) {
4925                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4926                 }
4927                 dpll |= DPLL_DVO_HIGH_SPEED;
4928         }
4929         if (is_dp && !is_cpu_edp)
4930                 dpll |= DPLL_DVO_HIGH_SPEED;
4931
4932         /* compute bitmask from p1 value */
4933         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4934         /* also FPA1 */
4935         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4936
4937         switch (clock->p2) {
4938         case 5:
4939                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4940                 break;
4941         case 7:
4942                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4943                 break;
4944         case 10:
4945                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4946                 break;
4947         case 14:
4948                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4949                 break;
4950         }
4951
4952         if (is_sdvo && is_tv)
4953                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4954         else if (is_tv)
4955                 /* XXX: just matching BIOS for now */
4956                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4957                 dpll |= 3;
4958         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4959                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4960         else
4961                 dpll |= PLL_REF_INPUT_DREFCLK;
4962
4963         return dpll;
4964 }
4965
4966 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4967                                   struct drm_display_mode *mode,
4968                                   struct drm_display_mode *adjusted_mode,
4969                                   int x, int y,
4970                                   struct drm_framebuffer *fb)
4971 {
4972         struct drm_device *dev = crtc->dev;
4973         struct drm_i915_private *dev_priv = dev->dev_private;
4974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4975         int pipe = intel_crtc->pipe;
4976         int plane = intel_crtc->plane;
4977         int num_connectors = 0;
4978         intel_clock_t clock, reduced_clock;
4979         u32 dpll, fp = 0, fp2 = 0;
4980         bool ok, has_reduced_clock = false;
4981         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
4982         struct intel_encoder *encoder;
4983         u32 temp;
4984         int ret;
4985         bool dither;
4986
4987         for_each_encoder_on_crtc(dev, crtc, encoder) {
4988                 switch (encoder->type) {
4989                 case INTEL_OUTPUT_LVDS:
4990                         is_lvds = true;
4991                         break;
4992                 case INTEL_OUTPUT_DISPLAYPORT:
4993                         is_dp = true;
4994                         break;
4995                 case INTEL_OUTPUT_EDP:
4996                         is_dp = true;
4997                         if (!intel_encoder_is_pch_edp(&encoder->base))
4998                                 is_cpu_edp = true;
4999                         break;
5000                 }
5001
5002                 num_connectors++;
5003         }
5004
5005         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5006                                      &has_reduced_clock, &reduced_clock);
5007         if (!ok) {
5008                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5009                 return -EINVAL;
5010         }
5011
5012         /* Ensure that the cursor is valid for the new mode before changing... */
5013         intel_crtc_update_cursor(crtc, true);
5014
5015         /* determine panel color depth */
5016         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5017         if (is_lvds && dev_priv->lvds_dither)
5018                 dither = true;
5019
5020         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5021         if (has_reduced_clock)
5022                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5023                         reduced_clock.m2;
5024
5025         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5026
5027         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5028         drm_mode_debug_printmodeline(mode);
5029
5030         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
5031          * pre-Haswell/LPT generation */
5032         if (HAS_PCH_LPT(dev)) {
5033                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
5034                                 pipe);
5035         } else if (!is_cpu_edp) {
5036                 struct intel_pch_pll *pll;
5037
5038                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5039                 if (pll == NULL) {
5040                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5041                                          pipe);
5042                         return -EINVAL;
5043                 }
5044         } else
5045                 intel_put_pch_pll(intel_crtc);
5046
5047         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5048          * This is an exception to the general rule that mode_set doesn't turn
5049          * things on.
5050          */
5051         if (is_lvds) {
5052                 temp = I915_READ(PCH_LVDS);
5053                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5054                 if (HAS_PCH_CPT(dev)) {
5055                         temp &= ~PORT_TRANS_SEL_MASK;
5056                         temp |= PORT_TRANS_SEL_CPT(pipe);
5057                 } else {
5058                         if (pipe == 1)
5059                                 temp |= LVDS_PIPEB_SELECT;
5060                         else
5061                                 temp &= ~LVDS_PIPEB_SELECT;
5062                 }
5063
5064                 /* set the corresponsding LVDS_BORDER bit */
5065                 temp |= dev_priv->lvds_border_bits;
5066                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5067                  * set the DPLLs for dual-channel mode or not.
5068                  */
5069                 if (clock.p2 == 7)
5070                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5071                 else
5072                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5073
5074                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5075                  * appropriately here, but we need to look more thoroughly into how
5076                  * panels behave in the two modes.
5077                  */
5078                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5079                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5080                         temp |= LVDS_HSYNC_POLARITY;
5081                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5082                         temp |= LVDS_VSYNC_POLARITY;
5083                 I915_WRITE(PCH_LVDS, temp);
5084         }
5085
5086         if (is_dp && !is_cpu_edp) {
5087                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5088         } else {
5089                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5090                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5091                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5092                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5093                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5094         }
5095
5096         if (intel_crtc->pch_pll) {
5097                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5098
5099                 /* Wait for the clocks to stabilize. */
5100                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5101                 udelay(150);
5102
5103                 /* The pixel multiplier can only be updated once the
5104                  * DPLL is enabled and the clocks are stable.
5105                  *
5106                  * So write it again.
5107                  */
5108                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5109         }
5110
5111         intel_crtc->lowfreq_avail = false;
5112         if (intel_crtc->pch_pll) {
5113                 if (is_lvds && has_reduced_clock && i915_powersave) {
5114                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5115                         intel_crtc->lowfreq_avail = true;
5116                 } else {
5117                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5118                 }
5119         }
5120
5121         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5122
5123         ironlake_set_m_n(crtc, mode, adjusted_mode);
5124
5125         if (is_cpu_edp)
5126                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5127
5128         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5129
5130         intel_wait_for_vblank(dev, pipe);
5131
5132         /* Set up the display plane register */
5133         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5134         POSTING_READ(DSPCNTR(plane));
5135
5136         ret = intel_pipe_set_base(crtc, x, y, fb);
5137
5138         intel_update_watermarks(dev);
5139
5140         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5141
5142         return ret;
5143 }
5144
5145 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5146                                  struct drm_display_mode *mode,
5147                                  struct drm_display_mode *adjusted_mode,
5148                                  int x, int y,
5149                                  struct drm_framebuffer *fb)
5150 {
5151         struct drm_device *dev = crtc->dev;
5152         struct drm_i915_private *dev_priv = dev->dev_private;
5153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154         int pipe = intel_crtc->pipe;
5155         int plane = intel_crtc->plane;
5156         int num_connectors = 0;
5157         intel_clock_t clock, reduced_clock;
5158         u32 dpll, fp = 0, fp2 = 0;
5159         bool ok, has_reduced_clock = false;
5160         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5161         struct intel_encoder *encoder;
5162         u32 temp;
5163         int ret;
5164         bool dither;
5165
5166         for_each_encoder_on_crtc(dev, crtc, encoder) {
5167                 switch (encoder->type) {
5168                 case INTEL_OUTPUT_LVDS:
5169                         is_lvds = true;
5170                         break;
5171                 case INTEL_OUTPUT_DISPLAYPORT:
5172                         is_dp = true;
5173                         break;
5174                 case INTEL_OUTPUT_EDP:
5175                         is_dp = true;
5176                         if (!intel_encoder_is_pch_edp(&encoder->base))
5177                                 is_cpu_edp = true;
5178                         break;
5179                 }
5180
5181                 num_connectors++;
5182         }
5183
5184         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5185                                      &has_reduced_clock, &reduced_clock);
5186         if (!ok) {
5187                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5188                 return -EINVAL;
5189         }
5190
5191         /* Ensure that the cursor is valid for the new mode before changing... */
5192         intel_crtc_update_cursor(crtc, true);
5193
5194         /* determine panel color depth */
5195         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5196         if (is_lvds && dev_priv->lvds_dither)
5197                 dither = true;
5198
5199         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5200         if (has_reduced_clock)
5201                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5202                         reduced_clock.m2;
5203
5204         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5205
5206         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5207         drm_mode_debug_printmodeline(mode);
5208
5209         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
5210          * pre-Haswell/LPT generation */
5211         if (HAS_PCH_LPT(dev)) {
5212                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
5213                                 pipe);
5214         } else if (!is_cpu_edp) {
5215                 struct intel_pch_pll *pll;
5216
5217                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5218                 if (pll == NULL) {
5219                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5220                                          pipe);
5221                         return -EINVAL;
5222                 }
5223         } else
5224                 intel_put_pch_pll(intel_crtc);
5225
5226         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5227          * This is an exception to the general rule that mode_set doesn't turn
5228          * things on.
5229          */
5230         if (is_lvds) {
5231                 temp = I915_READ(PCH_LVDS);
5232                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5233                 if (HAS_PCH_CPT(dev)) {
5234                         temp &= ~PORT_TRANS_SEL_MASK;
5235                         temp |= PORT_TRANS_SEL_CPT(pipe);
5236                 } else {
5237                         if (pipe == 1)
5238                                 temp |= LVDS_PIPEB_SELECT;
5239                         else
5240                                 temp &= ~LVDS_PIPEB_SELECT;
5241                 }
5242
5243                 /* set the corresponsding LVDS_BORDER bit */
5244                 temp |= dev_priv->lvds_border_bits;
5245                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5246                  * set the DPLLs for dual-channel mode or not.
5247                  */
5248                 if (clock.p2 == 7)
5249                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5250                 else
5251                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5252
5253                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5254                  * appropriately here, but we need to look more thoroughly into how
5255                  * panels behave in the two modes.
5256                  */
5257                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5258                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5259                         temp |= LVDS_HSYNC_POLARITY;
5260                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5261                         temp |= LVDS_VSYNC_POLARITY;
5262                 I915_WRITE(PCH_LVDS, temp);
5263         }
5264
5265         if (is_dp && !is_cpu_edp) {
5266                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5267         } else {
5268                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5269                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5270                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5271                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5272                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5273         }
5274
5275         if (intel_crtc->pch_pll) {
5276                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5277
5278                 /* Wait for the clocks to stabilize. */
5279                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5280                 udelay(150);
5281
5282                 /* The pixel multiplier can only be updated once the
5283                  * DPLL is enabled and the clocks are stable.
5284                  *
5285                  * So write it again.
5286                  */
5287                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5288         }
5289
5290         intel_crtc->lowfreq_avail = false;
5291         if (intel_crtc->pch_pll) {
5292                 if (is_lvds && has_reduced_clock && i915_powersave) {
5293                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5294                         intel_crtc->lowfreq_avail = true;
5295                 } else {
5296                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5297                 }
5298         }
5299
5300         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5301
5302         ironlake_set_m_n(crtc, mode, adjusted_mode);
5303
5304         if (is_cpu_edp)
5305                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5306
5307         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5308
5309         intel_wait_for_vblank(dev, pipe);
5310
5311         /* Set up the display plane register */
5312         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5313         POSTING_READ(DSPCNTR(plane));
5314
5315         ret = intel_pipe_set_base(crtc, x, y, fb);
5316
5317         intel_update_watermarks(dev);
5318
5319         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5320
5321         return ret;
5322 }
5323
5324 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5325                                struct drm_display_mode *mode,
5326                                struct drm_display_mode *adjusted_mode,
5327                                int x, int y,
5328                                struct drm_framebuffer *fb)
5329 {
5330         struct drm_device *dev = crtc->dev;
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         int pipe = intel_crtc->pipe;
5334         int ret;
5335
5336         drm_vblank_pre_modeset(dev, pipe);
5337
5338         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5339                                               x, y, fb);
5340         drm_vblank_post_modeset(dev, pipe);
5341
5342         return ret;
5343 }
5344
5345 static bool intel_eld_uptodate(struct drm_connector *connector,
5346                                int reg_eldv, uint32_t bits_eldv,
5347                                int reg_elda, uint32_t bits_elda,
5348                                int reg_edid)
5349 {
5350         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5351         uint8_t *eld = connector->eld;
5352         uint32_t i;
5353
5354         i = I915_READ(reg_eldv);
5355         i &= bits_eldv;
5356
5357         if (!eld[0])
5358                 return !i;
5359
5360         if (!i)
5361                 return false;
5362
5363         i = I915_READ(reg_elda);
5364         i &= ~bits_elda;
5365         I915_WRITE(reg_elda, i);
5366
5367         for (i = 0; i < eld[2]; i++)
5368                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5369                         return false;
5370
5371         return true;
5372 }
5373
5374 static void g4x_write_eld(struct drm_connector *connector,
5375                           struct drm_crtc *crtc)
5376 {
5377         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5378         uint8_t *eld = connector->eld;
5379         uint32_t eldv;
5380         uint32_t len;
5381         uint32_t i;
5382
5383         i = I915_READ(G4X_AUD_VID_DID);
5384
5385         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5386                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5387         else
5388                 eldv = G4X_ELDV_DEVCTG;
5389
5390         if (intel_eld_uptodate(connector,
5391                                G4X_AUD_CNTL_ST, eldv,
5392                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5393                                G4X_HDMIW_HDMIEDID))
5394                 return;
5395
5396         i = I915_READ(G4X_AUD_CNTL_ST);
5397         i &= ~(eldv | G4X_ELD_ADDR);
5398         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5399         I915_WRITE(G4X_AUD_CNTL_ST, i);
5400
5401         if (!eld[0])
5402                 return;
5403
5404         len = min_t(uint8_t, eld[2], len);
5405         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5406         for (i = 0; i < len; i++)
5407                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5408
5409         i = I915_READ(G4X_AUD_CNTL_ST);
5410         i |= eldv;
5411         I915_WRITE(G4X_AUD_CNTL_ST, i);
5412 }
5413
5414 static void haswell_write_eld(struct drm_connector *connector,
5415                                      struct drm_crtc *crtc)
5416 {
5417         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5418         uint8_t *eld = connector->eld;
5419         struct drm_device *dev = crtc->dev;
5420         uint32_t eldv;
5421         uint32_t i;
5422         int len;
5423         int pipe = to_intel_crtc(crtc)->pipe;
5424         int tmp;
5425
5426         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5427         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5428         int aud_config = HSW_AUD_CFG(pipe);
5429         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5430
5431
5432         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5433
5434         /* Audio output enable */
5435         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5436         tmp = I915_READ(aud_cntrl_st2);
5437         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5438         I915_WRITE(aud_cntrl_st2, tmp);
5439
5440         /* Wait for 1 vertical blank */
5441         intel_wait_for_vblank(dev, pipe);
5442
5443         /* Set ELD valid state */
5444         tmp = I915_READ(aud_cntrl_st2);
5445         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5446         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5447         I915_WRITE(aud_cntrl_st2, tmp);
5448         tmp = I915_READ(aud_cntrl_st2);
5449         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5450
5451         /* Enable HDMI mode */
5452         tmp = I915_READ(aud_config);
5453         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5454         /* clear N_programing_enable and N_value_index */
5455         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5456         I915_WRITE(aud_config, tmp);
5457
5458         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5459
5460         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5461
5462         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5463                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5464                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5465                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5466         } else
5467                 I915_WRITE(aud_config, 0);
5468
5469         if (intel_eld_uptodate(connector,
5470                                aud_cntrl_st2, eldv,
5471                                aud_cntl_st, IBX_ELD_ADDRESS,
5472                                hdmiw_hdmiedid))
5473                 return;
5474
5475         i = I915_READ(aud_cntrl_st2);
5476         i &= ~eldv;
5477         I915_WRITE(aud_cntrl_st2, i);
5478
5479         if (!eld[0])
5480                 return;
5481
5482         i = I915_READ(aud_cntl_st);
5483         i &= ~IBX_ELD_ADDRESS;
5484         I915_WRITE(aud_cntl_st, i);
5485         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5486         DRM_DEBUG_DRIVER("port num:%d\n", i);
5487
5488         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5489         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5490         for (i = 0; i < len; i++)
5491                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5492
5493         i = I915_READ(aud_cntrl_st2);
5494         i |= eldv;
5495         I915_WRITE(aud_cntrl_st2, i);
5496
5497 }
5498
5499 static void ironlake_write_eld(struct drm_connector *connector,
5500                                      struct drm_crtc *crtc)
5501 {
5502         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5503         uint8_t *eld = connector->eld;
5504         uint32_t eldv;
5505         uint32_t i;
5506         int len;
5507         int hdmiw_hdmiedid;
5508         int aud_config;
5509         int aud_cntl_st;
5510         int aud_cntrl_st2;
5511         int pipe = to_intel_crtc(crtc)->pipe;
5512
5513         if (HAS_PCH_IBX(connector->dev)) {
5514                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5515                 aud_config = IBX_AUD_CFG(pipe);
5516                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5517                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5518         } else {
5519                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5520                 aud_config = CPT_AUD_CFG(pipe);
5521                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5522                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5523         }
5524
5525         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5526
5527         i = I915_READ(aud_cntl_st);
5528         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5529         if (!i) {
5530                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5531                 /* operate blindly on all ports */
5532                 eldv = IBX_ELD_VALIDB;
5533                 eldv |= IBX_ELD_VALIDB << 4;
5534                 eldv |= IBX_ELD_VALIDB << 8;
5535         } else {
5536                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5537                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5538         }
5539
5540         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5541                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5542                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5543                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5544         } else
5545                 I915_WRITE(aud_config, 0);
5546
5547         if (intel_eld_uptodate(connector,
5548                                aud_cntrl_st2, eldv,
5549                                aud_cntl_st, IBX_ELD_ADDRESS,
5550                                hdmiw_hdmiedid))
5551                 return;
5552
5553         i = I915_READ(aud_cntrl_st2);
5554         i &= ~eldv;
5555         I915_WRITE(aud_cntrl_st2, i);
5556
5557         if (!eld[0])
5558                 return;
5559
5560         i = I915_READ(aud_cntl_st);
5561         i &= ~IBX_ELD_ADDRESS;
5562         I915_WRITE(aud_cntl_st, i);
5563
5564         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5565         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5566         for (i = 0; i < len; i++)
5567                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5568
5569         i = I915_READ(aud_cntrl_st2);
5570         i |= eldv;
5571         I915_WRITE(aud_cntrl_st2, i);
5572 }
5573
5574 void intel_write_eld(struct drm_encoder *encoder,
5575                      struct drm_display_mode *mode)
5576 {
5577         struct drm_crtc *crtc = encoder->crtc;
5578         struct drm_connector *connector;
5579         struct drm_device *dev = encoder->dev;
5580         struct drm_i915_private *dev_priv = dev->dev_private;
5581
5582         connector = drm_select_eld(encoder, mode);
5583         if (!connector)
5584                 return;
5585
5586         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5587                          connector->base.id,
5588                          drm_get_connector_name(connector),
5589                          connector->encoder->base.id,
5590                          drm_get_encoder_name(connector->encoder));
5591
5592         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5593
5594         if (dev_priv->display.write_eld)
5595                 dev_priv->display.write_eld(connector, crtc);
5596 }
5597
5598 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5599 void intel_crtc_load_lut(struct drm_crtc *crtc)
5600 {
5601         struct drm_device *dev = crtc->dev;
5602         struct drm_i915_private *dev_priv = dev->dev_private;
5603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5604         int palreg = PALETTE(intel_crtc->pipe);
5605         int i;
5606
5607         /* The clocks have to be on to load the palette. */
5608         if (!crtc->enabled || !intel_crtc->active)
5609                 return;
5610
5611         /* use legacy palette for Ironlake */
5612         if (HAS_PCH_SPLIT(dev))
5613                 palreg = LGC_PALETTE(intel_crtc->pipe);
5614
5615         for (i = 0; i < 256; i++) {
5616                 I915_WRITE(palreg + 4 * i,
5617                            (intel_crtc->lut_r[i] << 16) |
5618                            (intel_crtc->lut_g[i] << 8) |
5619                            intel_crtc->lut_b[i]);
5620         }
5621 }
5622
5623 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5624 {
5625         struct drm_device *dev = crtc->dev;
5626         struct drm_i915_private *dev_priv = dev->dev_private;
5627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5628         bool visible = base != 0;
5629         u32 cntl;
5630
5631         if (intel_crtc->cursor_visible == visible)
5632                 return;
5633
5634         cntl = I915_READ(_CURACNTR);
5635         if (visible) {
5636                 /* On these chipsets we can only modify the base whilst
5637                  * the cursor is disabled.
5638                  */
5639                 I915_WRITE(_CURABASE, base);
5640
5641                 cntl &= ~(CURSOR_FORMAT_MASK);
5642                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5643                 cntl |= CURSOR_ENABLE |
5644                         CURSOR_GAMMA_ENABLE |
5645                         CURSOR_FORMAT_ARGB;
5646         } else
5647                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5648         I915_WRITE(_CURACNTR, cntl);
5649
5650         intel_crtc->cursor_visible = visible;
5651 }
5652
5653 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5654 {
5655         struct drm_device *dev = crtc->dev;
5656         struct drm_i915_private *dev_priv = dev->dev_private;
5657         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5658         int pipe = intel_crtc->pipe;
5659         bool visible = base != 0;
5660
5661         if (intel_crtc->cursor_visible != visible) {
5662                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5663                 if (base) {
5664                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5665                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5666                         cntl |= pipe << 28; /* Connect to correct pipe */
5667                 } else {
5668                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5669                         cntl |= CURSOR_MODE_DISABLE;
5670                 }
5671                 I915_WRITE(CURCNTR(pipe), cntl);
5672
5673                 intel_crtc->cursor_visible = visible;
5674         }
5675         /* and commit changes on next vblank */
5676         I915_WRITE(CURBASE(pipe), base);
5677 }
5678
5679 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5680 {
5681         struct drm_device *dev = crtc->dev;
5682         struct drm_i915_private *dev_priv = dev->dev_private;
5683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5684         int pipe = intel_crtc->pipe;
5685         bool visible = base != 0;
5686
5687         if (intel_crtc->cursor_visible != visible) {
5688                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5689                 if (base) {
5690                         cntl &= ~CURSOR_MODE;
5691                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5692                 } else {
5693                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5694                         cntl |= CURSOR_MODE_DISABLE;
5695                 }
5696                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5697
5698                 intel_crtc->cursor_visible = visible;
5699         }
5700         /* and commit changes on next vblank */
5701         I915_WRITE(CURBASE_IVB(pipe), base);
5702 }
5703
5704 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5705 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5706                                      bool on)
5707 {
5708         struct drm_device *dev = crtc->dev;
5709         struct drm_i915_private *dev_priv = dev->dev_private;
5710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5711         int pipe = intel_crtc->pipe;
5712         int x = intel_crtc->cursor_x;
5713         int y = intel_crtc->cursor_y;
5714         u32 base, pos;
5715         bool visible;
5716
5717         pos = 0;
5718
5719         if (on && crtc->enabled && crtc->fb) {
5720                 base = intel_crtc->cursor_addr;
5721                 if (x > (int) crtc->fb->width)
5722                         base = 0;
5723
5724                 if (y > (int) crtc->fb->height)
5725                         base = 0;
5726         } else
5727                 base = 0;
5728
5729         if (x < 0) {
5730                 if (x + intel_crtc->cursor_width < 0)
5731                         base = 0;
5732
5733                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5734                 x = -x;
5735         }
5736         pos |= x << CURSOR_X_SHIFT;
5737
5738         if (y < 0) {
5739                 if (y + intel_crtc->cursor_height < 0)
5740                         base = 0;
5741
5742                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5743                 y = -y;
5744         }
5745         pos |= y << CURSOR_Y_SHIFT;
5746
5747         visible = base != 0;
5748         if (!visible && !intel_crtc->cursor_visible)
5749                 return;
5750
5751         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5752                 I915_WRITE(CURPOS_IVB(pipe), pos);
5753                 ivb_update_cursor(crtc, base);
5754         } else {
5755                 I915_WRITE(CURPOS(pipe), pos);
5756                 if (IS_845G(dev) || IS_I865G(dev))
5757                         i845_update_cursor(crtc, base);
5758                 else
5759                         i9xx_update_cursor(crtc, base);
5760         }
5761 }
5762
5763 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5764                                  struct drm_file *file,
5765                                  uint32_t handle,
5766                                  uint32_t width, uint32_t height)
5767 {
5768         struct drm_device *dev = crtc->dev;
5769         struct drm_i915_private *dev_priv = dev->dev_private;
5770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771         struct drm_i915_gem_object *obj;
5772         uint32_t addr;
5773         int ret;
5774
5775         /* if we want to turn off the cursor ignore width and height */
5776         if (!handle) {
5777                 DRM_DEBUG_KMS("cursor off\n");
5778                 addr = 0;
5779                 obj = NULL;
5780                 mutex_lock(&dev->struct_mutex);
5781                 goto finish;
5782         }
5783
5784         /* Currently we only support 64x64 cursors */
5785         if (width != 64 || height != 64) {
5786                 DRM_ERROR("we currently only support 64x64 cursors\n");
5787                 return -EINVAL;
5788         }
5789
5790         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5791         if (&obj->base == NULL)
5792                 return -ENOENT;
5793
5794         if (obj->base.size < width * height * 4) {
5795                 DRM_ERROR("buffer is to small\n");
5796                 ret = -ENOMEM;
5797                 goto fail;
5798         }
5799
5800         /* we only need to pin inside GTT if cursor is non-phy */
5801         mutex_lock(&dev->struct_mutex);
5802         if (!dev_priv->info->cursor_needs_physical) {
5803                 if (obj->tiling_mode) {
5804                         DRM_ERROR("cursor cannot be tiled\n");
5805                         ret = -EINVAL;
5806                         goto fail_locked;
5807                 }
5808
5809                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5810                 if (ret) {
5811                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5812                         goto fail_locked;
5813                 }
5814
5815                 ret = i915_gem_object_put_fence(obj);
5816                 if (ret) {
5817                         DRM_ERROR("failed to release fence for cursor");
5818                         goto fail_unpin;
5819                 }
5820
5821                 addr = obj->gtt_offset;
5822         } else {
5823                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5824                 ret = i915_gem_attach_phys_object(dev, obj,
5825                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5826                                                   align);
5827                 if (ret) {
5828                         DRM_ERROR("failed to attach phys object\n");
5829                         goto fail_locked;
5830                 }
5831                 addr = obj->phys_obj->handle->busaddr;
5832         }
5833
5834         if (IS_GEN2(dev))
5835                 I915_WRITE(CURSIZE, (height << 12) | width);
5836
5837  finish:
5838         if (intel_crtc->cursor_bo) {
5839                 if (dev_priv->info->cursor_needs_physical) {
5840                         if (intel_crtc->cursor_bo != obj)
5841                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5842                 } else
5843                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5844                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5845         }
5846
5847         mutex_unlock(&dev->struct_mutex);
5848
5849         intel_crtc->cursor_addr = addr;
5850         intel_crtc->cursor_bo = obj;
5851         intel_crtc->cursor_width = width;
5852         intel_crtc->cursor_height = height;
5853
5854         intel_crtc_update_cursor(crtc, true);
5855
5856         return 0;
5857 fail_unpin:
5858         i915_gem_object_unpin(obj);
5859 fail_locked:
5860         mutex_unlock(&dev->struct_mutex);
5861 fail:
5862         drm_gem_object_unreference_unlocked(&obj->base);
5863         return ret;
5864 }
5865
5866 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5867 {
5868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869
5870         intel_crtc->cursor_x = x;
5871         intel_crtc->cursor_y = y;
5872
5873         intel_crtc_update_cursor(crtc, true);
5874
5875         return 0;
5876 }
5877
5878 /** Sets the color ramps on behalf of RandR */
5879 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5880                                  u16 blue, int regno)
5881 {
5882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5883
5884         intel_crtc->lut_r[regno] = red >> 8;
5885         intel_crtc->lut_g[regno] = green >> 8;
5886         intel_crtc->lut_b[regno] = blue >> 8;
5887 }
5888
5889 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5890                              u16 *blue, int regno)
5891 {
5892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5893
5894         *red = intel_crtc->lut_r[regno] << 8;
5895         *green = intel_crtc->lut_g[regno] << 8;
5896         *blue = intel_crtc->lut_b[regno] << 8;
5897 }
5898
5899 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5900                                  u16 *blue, uint32_t start, uint32_t size)
5901 {
5902         int end = (start + size > 256) ? 256 : start + size, i;
5903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5904
5905         for (i = start; i < end; i++) {
5906                 intel_crtc->lut_r[i] = red[i] >> 8;
5907                 intel_crtc->lut_g[i] = green[i] >> 8;
5908                 intel_crtc->lut_b[i] = blue[i] >> 8;
5909         }
5910
5911         intel_crtc_load_lut(crtc);
5912 }
5913
5914 /**
5915  * Get a pipe with a simple mode set on it for doing load-based monitor
5916  * detection.
5917  *
5918  * It will be up to the load-detect code to adjust the pipe as appropriate for
5919  * its requirements.  The pipe will be connected to no other encoders.
5920  *
5921  * Currently this code will only succeed if there is a pipe with no encoders
5922  * configured for it.  In the future, it could choose to temporarily disable
5923  * some outputs to free up a pipe for its use.
5924  *
5925  * \return crtc, or NULL if no pipes are available.
5926  */
5927
5928 /* VESA 640x480x72Hz mode to set on the pipe */
5929 static struct drm_display_mode load_detect_mode = {
5930         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5931                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5932 };
5933
5934 static struct drm_framebuffer *
5935 intel_framebuffer_create(struct drm_device *dev,
5936                          struct drm_mode_fb_cmd2 *mode_cmd,
5937                          struct drm_i915_gem_object *obj)
5938 {
5939         struct intel_framebuffer *intel_fb;
5940         int ret;
5941
5942         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5943         if (!intel_fb) {
5944                 drm_gem_object_unreference_unlocked(&obj->base);
5945                 return ERR_PTR(-ENOMEM);
5946         }
5947
5948         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5949         if (ret) {
5950                 drm_gem_object_unreference_unlocked(&obj->base);
5951                 kfree(intel_fb);
5952                 return ERR_PTR(ret);
5953         }
5954
5955         return &intel_fb->base;
5956 }
5957
5958 static u32
5959 intel_framebuffer_pitch_for_width(int width, int bpp)
5960 {
5961         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5962         return ALIGN(pitch, 64);
5963 }
5964
5965 static u32
5966 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5967 {
5968         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5969         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5970 }
5971
5972 static struct drm_framebuffer *
5973 intel_framebuffer_create_for_mode(struct drm_device *dev,
5974                                   struct drm_display_mode *mode,
5975                                   int depth, int bpp)
5976 {
5977         struct drm_i915_gem_object *obj;
5978         struct drm_mode_fb_cmd2 mode_cmd;
5979
5980         obj = i915_gem_alloc_object(dev,
5981                                     intel_framebuffer_size_for_mode(mode, bpp));
5982         if (obj == NULL)
5983                 return ERR_PTR(-ENOMEM);
5984
5985         mode_cmd.width = mode->hdisplay;
5986         mode_cmd.height = mode->vdisplay;
5987         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5988                                                                 bpp);
5989         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5990
5991         return intel_framebuffer_create(dev, &mode_cmd, obj);
5992 }
5993
5994 static struct drm_framebuffer *
5995 mode_fits_in_fbdev(struct drm_device *dev,
5996                    struct drm_display_mode *mode)
5997 {
5998         struct drm_i915_private *dev_priv = dev->dev_private;
5999         struct drm_i915_gem_object *obj;
6000         struct drm_framebuffer *fb;
6001
6002         if (dev_priv->fbdev == NULL)
6003                 return NULL;
6004
6005         obj = dev_priv->fbdev->ifb.obj;
6006         if (obj == NULL)
6007                 return NULL;
6008
6009         fb = &dev_priv->fbdev->ifb.base;
6010         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6011                                                                fb->bits_per_pixel))
6012                 return NULL;
6013
6014         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6015                 return NULL;
6016
6017         return fb;
6018 }
6019
6020 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6021                                 struct drm_display_mode *mode,
6022                                 struct intel_load_detect_pipe *old)
6023 {
6024         struct intel_crtc *intel_crtc;
6025         struct intel_encoder *intel_encoder =
6026                 intel_attached_encoder(connector);
6027         struct drm_crtc *possible_crtc;
6028         struct drm_encoder *encoder = &intel_encoder->base;
6029         struct drm_crtc *crtc = NULL;
6030         struct drm_device *dev = encoder->dev;
6031         struct drm_framebuffer *fb;
6032         int i = -1;
6033
6034         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6035                       connector->base.id, drm_get_connector_name(connector),
6036                       encoder->base.id, drm_get_encoder_name(encoder));
6037
6038         /*
6039          * Algorithm gets a little messy:
6040          *
6041          *   - if the connector already has an assigned crtc, use it (but make
6042          *     sure it's on first)
6043          *
6044          *   - try to find the first unused crtc that can drive this connector,
6045          *     and use that if we find one
6046          */
6047
6048         /* See if we already have a CRTC for this connector */
6049         if (encoder->crtc) {
6050                 crtc = encoder->crtc;
6051
6052                 old->dpms_mode = connector->dpms;
6053                 old->load_detect_temp = false;
6054
6055                 /* Make sure the crtc and connector are running */
6056                 if (connector->dpms != DRM_MODE_DPMS_ON)
6057                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6058
6059                 return true;
6060         }
6061
6062         /* Find an unused one (if possible) */
6063         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6064                 i++;
6065                 if (!(encoder->possible_crtcs & (1 << i)))
6066                         continue;
6067                 if (!possible_crtc->enabled) {
6068                         crtc = possible_crtc;
6069                         break;
6070                 }
6071         }
6072
6073         /*
6074          * If we didn't find an unused CRTC, don't use any.
6075          */
6076         if (!crtc) {
6077                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6078                 return false;
6079         }
6080
6081         intel_encoder->new_crtc = to_intel_crtc(crtc);
6082         to_intel_connector(connector)->new_encoder = intel_encoder;
6083
6084         intel_crtc = to_intel_crtc(crtc);
6085         old->dpms_mode = connector->dpms;
6086         old->load_detect_temp = true;
6087         old->release_fb = NULL;
6088
6089         if (!mode)
6090                 mode = &load_detect_mode;
6091
6092         /* We need a framebuffer large enough to accommodate all accesses
6093          * that the plane may generate whilst we perform load detection.
6094          * We can not rely on the fbcon either being present (we get called
6095          * during its initialisation to detect all boot displays, or it may
6096          * not even exist) or that it is large enough to satisfy the
6097          * requested mode.
6098          */
6099         fb = mode_fits_in_fbdev(dev, mode);
6100         if (fb == NULL) {
6101                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6102                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6103                 old->release_fb = fb;
6104         } else
6105                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6106         if (IS_ERR(fb)) {
6107                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6108                 goto fail;
6109         }
6110
6111         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6112                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6113                 if (old->release_fb)
6114                         old->release_fb->funcs->destroy(old->release_fb);
6115                 goto fail;
6116         }
6117
6118         /* let the connector get through one full cycle before testing */
6119         intel_wait_for_vblank(dev, intel_crtc->pipe);
6120
6121         return true;
6122 fail:
6123         connector->encoder = NULL;
6124         encoder->crtc = NULL;
6125         return false;
6126 }
6127
6128 void intel_release_load_detect_pipe(struct drm_connector *connector,
6129                                     struct intel_load_detect_pipe *old)
6130 {
6131         struct intel_encoder *intel_encoder =
6132                 intel_attached_encoder(connector);
6133         struct drm_encoder *encoder = &intel_encoder->base;
6134
6135         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6136                       connector->base.id, drm_get_connector_name(connector),
6137                       encoder->base.id, drm_get_encoder_name(encoder));
6138
6139         if (old->load_detect_temp) {
6140                 struct drm_crtc *crtc = encoder->crtc;
6141
6142                 to_intel_connector(connector)->new_encoder = NULL;
6143                 intel_encoder->new_crtc = NULL;
6144                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6145
6146                 if (old->release_fb)
6147                         old->release_fb->funcs->destroy(old->release_fb);
6148
6149                 return;
6150         }
6151
6152         /* Switch crtc and encoder back off if necessary */
6153         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6154                 connector->funcs->dpms(connector, old->dpms_mode);
6155 }
6156
6157 /* Returns the clock of the currently programmed mode of the given pipe. */
6158 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6159 {
6160         struct drm_i915_private *dev_priv = dev->dev_private;
6161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6162         int pipe = intel_crtc->pipe;
6163         u32 dpll = I915_READ(DPLL(pipe));
6164         u32 fp;
6165         intel_clock_t clock;
6166
6167         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6168                 fp = I915_READ(FP0(pipe));
6169         else
6170                 fp = I915_READ(FP1(pipe));
6171
6172         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6173         if (IS_PINEVIEW(dev)) {
6174                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6175                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6176         } else {
6177                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6178                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6179         }
6180
6181         if (!IS_GEN2(dev)) {
6182                 if (IS_PINEVIEW(dev))
6183                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6184                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6185                 else
6186                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6187                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6188
6189                 switch (dpll & DPLL_MODE_MASK) {
6190                 case DPLLB_MODE_DAC_SERIAL:
6191                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6192                                 5 : 10;
6193                         break;
6194                 case DPLLB_MODE_LVDS:
6195                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6196                                 7 : 14;
6197                         break;
6198                 default:
6199                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6200                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6201                         return 0;
6202                 }
6203
6204                 /* XXX: Handle the 100Mhz refclk */
6205                 intel_clock(dev, 96000, &clock);
6206         } else {
6207                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6208
6209                 if (is_lvds) {
6210                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6211                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6212                         clock.p2 = 14;
6213
6214                         if ((dpll & PLL_REF_INPUT_MASK) ==
6215                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6216                                 /* XXX: might not be 66MHz */
6217                                 intel_clock(dev, 66000, &clock);
6218                         } else
6219                                 intel_clock(dev, 48000, &clock);
6220                 } else {
6221                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6222                                 clock.p1 = 2;
6223                         else {
6224                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6225                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6226                         }
6227                         if (dpll & PLL_P2_DIVIDE_BY_4)
6228                                 clock.p2 = 4;
6229                         else
6230                                 clock.p2 = 2;
6231
6232                         intel_clock(dev, 48000, &clock);
6233                 }
6234         }
6235
6236         /* XXX: It would be nice to validate the clocks, but we can't reuse
6237          * i830PllIsValid() because it relies on the xf86_config connector
6238          * configuration being accurate, which it isn't necessarily.
6239          */
6240
6241         return clock.dot;
6242 }
6243
6244 /** Returns the currently programmed mode of the given pipe. */
6245 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6246                                              struct drm_crtc *crtc)
6247 {
6248         struct drm_i915_private *dev_priv = dev->dev_private;
6249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6250         int pipe = intel_crtc->pipe;
6251         struct drm_display_mode *mode;
6252         int htot = I915_READ(HTOTAL(pipe));
6253         int hsync = I915_READ(HSYNC(pipe));
6254         int vtot = I915_READ(VTOTAL(pipe));
6255         int vsync = I915_READ(VSYNC(pipe));
6256
6257         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6258         if (!mode)
6259                 return NULL;
6260
6261         mode->clock = intel_crtc_clock_get(dev, crtc);
6262         mode->hdisplay = (htot & 0xffff) + 1;
6263         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6264         mode->hsync_start = (hsync & 0xffff) + 1;
6265         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6266         mode->vdisplay = (vtot & 0xffff) + 1;
6267         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6268         mode->vsync_start = (vsync & 0xffff) + 1;
6269         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6270
6271         drm_mode_set_name(mode);
6272
6273         return mode;
6274 }
6275
6276 static void intel_increase_pllclock(struct drm_crtc *crtc)
6277 {
6278         struct drm_device *dev = crtc->dev;
6279         drm_i915_private_t *dev_priv = dev->dev_private;
6280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281         int pipe = intel_crtc->pipe;
6282         int dpll_reg = DPLL(pipe);
6283         int dpll;
6284
6285         if (HAS_PCH_SPLIT(dev))
6286                 return;
6287
6288         if (!dev_priv->lvds_downclock_avail)
6289                 return;
6290
6291         dpll = I915_READ(dpll_reg);
6292         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6293                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6294
6295                 assert_panel_unlocked(dev_priv, pipe);
6296
6297                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6298                 I915_WRITE(dpll_reg, dpll);
6299                 intel_wait_for_vblank(dev, pipe);
6300
6301                 dpll = I915_READ(dpll_reg);
6302                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6303                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6304         }
6305 }
6306
6307 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6308 {
6309         struct drm_device *dev = crtc->dev;
6310         drm_i915_private_t *dev_priv = dev->dev_private;
6311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312
6313         if (HAS_PCH_SPLIT(dev))
6314                 return;
6315
6316         if (!dev_priv->lvds_downclock_avail)
6317                 return;
6318
6319         /*
6320          * Since this is called by a timer, we should never get here in
6321          * the manual case.
6322          */
6323         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6324                 int pipe = intel_crtc->pipe;
6325                 int dpll_reg = DPLL(pipe);
6326                 int dpll;
6327
6328                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6329
6330                 assert_panel_unlocked(dev_priv, pipe);
6331
6332                 dpll = I915_READ(dpll_reg);
6333                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6334                 I915_WRITE(dpll_reg, dpll);
6335                 intel_wait_for_vblank(dev, pipe);
6336                 dpll = I915_READ(dpll_reg);
6337                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6338                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6339         }
6340
6341 }
6342
6343 void intel_mark_busy(struct drm_device *dev)
6344 {
6345         i915_update_gfx_val(dev->dev_private);
6346 }
6347
6348 void intel_mark_idle(struct drm_device *dev)
6349 {
6350 }
6351
6352 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6353 {
6354         struct drm_device *dev = obj->base.dev;
6355         struct drm_crtc *crtc;
6356
6357         if (!i915_powersave)
6358                 return;
6359
6360         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6361                 if (!crtc->fb)
6362                         continue;
6363
6364                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6365                         intel_increase_pllclock(crtc);
6366         }
6367 }
6368
6369 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6370 {
6371         struct drm_device *dev = obj->base.dev;
6372         struct drm_crtc *crtc;
6373
6374         if (!i915_powersave)
6375                 return;
6376
6377         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6378                 if (!crtc->fb)
6379                         continue;
6380
6381                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6382                         intel_decrease_pllclock(crtc);
6383         }
6384 }
6385
6386 static void intel_crtc_destroy(struct drm_crtc *crtc)
6387 {
6388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6389         struct drm_device *dev = crtc->dev;
6390         struct intel_unpin_work *work;
6391         unsigned long flags;
6392
6393         spin_lock_irqsave(&dev->event_lock, flags);
6394         work = intel_crtc->unpin_work;
6395         intel_crtc->unpin_work = NULL;
6396         spin_unlock_irqrestore(&dev->event_lock, flags);
6397
6398         if (work) {
6399                 cancel_work_sync(&work->work);
6400                 kfree(work);
6401         }
6402
6403         drm_crtc_cleanup(crtc);
6404
6405         kfree(intel_crtc);
6406 }
6407
6408 static void intel_unpin_work_fn(struct work_struct *__work)
6409 {
6410         struct intel_unpin_work *work =
6411                 container_of(__work, struct intel_unpin_work, work);
6412
6413         mutex_lock(&work->dev->struct_mutex);
6414         intel_unpin_fb_obj(work->old_fb_obj);
6415         drm_gem_object_unreference(&work->pending_flip_obj->base);
6416         drm_gem_object_unreference(&work->old_fb_obj->base);
6417
6418         intel_update_fbc(work->dev);
6419         mutex_unlock(&work->dev->struct_mutex);
6420         kfree(work);
6421 }
6422
6423 static void do_intel_finish_page_flip(struct drm_device *dev,
6424                                       struct drm_crtc *crtc)
6425 {
6426         drm_i915_private_t *dev_priv = dev->dev_private;
6427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6428         struct intel_unpin_work *work;
6429         struct drm_i915_gem_object *obj;
6430         struct drm_pending_vblank_event *e;
6431         struct timeval tnow, tvbl;
6432         unsigned long flags;
6433
6434         /* Ignore early vblank irqs */
6435         if (intel_crtc == NULL)
6436                 return;
6437
6438         do_gettimeofday(&tnow);
6439
6440         spin_lock_irqsave(&dev->event_lock, flags);
6441         work = intel_crtc->unpin_work;
6442         if (work == NULL || !work->pending) {
6443                 spin_unlock_irqrestore(&dev->event_lock, flags);
6444                 return;
6445         }
6446
6447         intel_crtc->unpin_work = NULL;
6448
6449         if (work->event) {
6450                 e = work->event;
6451                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6452
6453                 /* Called before vblank count and timestamps have
6454                  * been updated for the vblank interval of flip
6455                  * completion? Need to increment vblank count and
6456                  * add one videorefresh duration to returned timestamp
6457                  * to account for this. We assume this happened if we
6458                  * get called over 0.9 frame durations after the last
6459                  * timestamped vblank.
6460                  *
6461                  * This calculation can not be used with vrefresh rates
6462                  * below 5Hz (10Hz to be on the safe side) without
6463                  * promoting to 64 integers.
6464                  */
6465                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6466                     9 * crtc->framedur_ns) {
6467                         e->event.sequence++;
6468                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6469                                              crtc->framedur_ns);
6470                 }
6471
6472                 e->event.tv_sec = tvbl.tv_sec;
6473                 e->event.tv_usec = tvbl.tv_usec;
6474
6475                 list_add_tail(&e->base.link,
6476                               &e->base.file_priv->event_list);
6477                 wake_up_interruptible(&e->base.file_priv->event_wait);
6478         }
6479
6480         drm_vblank_put(dev, intel_crtc->pipe);
6481
6482         spin_unlock_irqrestore(&dev->event_lock, flags);
6483
6484         obj = work->old_fb_obj;
6485
6486         atomic_clear_mask(1 << intel_crtc->plane,
6487                           &obj->pending_flip.counter);
6488         if (atomic_read(&obj->pending_flip) == 0)
6489                 wake_up(&dev_priv->pending_flip_queue);
6490
6491         schedule_work(&work->work);
6492
6493         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6494 }
6495
6496 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6497 {
6498         drm_i915_private_t *dev_priv = dev->dev_private;
6499         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6500
6501         do_intel_finish_page_flip(dev, crtc);
6502 }
6503
6504 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6505 {
6506         drm_i915_private_t *dev_priv = dev->dev_private;
6507         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6508
6509         do_intel_finish_page_flip(dev, crtc);
6510 }
6511
6512 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6513 {
6514         drm_i915_private_t *dev_priv = dev->dev_private;
6515         struct intel_crtc *intel_crtc =
6516                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6517         unsigned long flags;
6518
6519         spin_lock_irqsave(&dev->event_lock, flags);
6520         if (intel_crtc->unpin_work) {
6521                 if ((++intel_crtc->unpin_work->pending) > 1)
6522                         DRM_ERROR("Prepared flip multiple times\n");
6523         } else {
6524                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6525         }
6526         spin_unlock_irqrestore(&dev->event_lock, flags);
6527 }
6528
6529 static int intel_gen2_queue_flip(struct drm_device *dev,
6530                                  struct drm_crtc *crtc,
6531                                  struct drm_framebuffer *fb,
6532                                  struct drm_i915_gem_object *obj)
6533 {
6534         struct drm_i915_private *dev_priv = dev->dev_private;
6535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6536         u32 flip_mask;
6537         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6538         int ret;
6539
6540         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6541         if (ret)
6542                 goto err;
6543
6544         ret = intel_ring_begin(ring, 6);
6545         if (ret)
6546                 goto err_unpin;
6547
6548         /* Can't queue multiple flips, so wait for the previous
6549          * one to finish before executing the next.
6550          */
6551         if (intel_crtc->plane)
6552                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6553         else
6554                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6555         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6556         intel_ring_emit(ring, MI_NOOP);
6557         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6558                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6559         intel_ring_emit(ring, fb->pitches[0]);
6560         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6561         intel_ring_emit(ring, 0); /* aux display base address, unused */
6562         intel_ring_advance(ring);
6563         return 0;
6564
6565 err_unpin:
6566         intel_unpin_fb_obj(obj);
6567 err:
6568         return ret;
6569 }
6570
6571 static int intel_gen3_queue_flip(struct drm_device *dev,
6572                                  struct drm_crtc *crtc,
6573                                  struct drm_framebuffer *fb,
6574                                  struct drm_i915_gem_object *obj)
6575 {
6576         struct drm_i915_private *dev_priv = dev->dev_private;
6577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6578         u32 flip_mask;
6579         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6580         int ret;
6581
6582         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6583         if (ret)
6584                 goto err;
6585
6586         ret = intel_ring_begin(ring, 6);
6587         if (ret)
6588                 goto err_unpin;
6589
6590         if (intel_crtc->plane)
6591                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6592         else
6593                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6594         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6595         intel_ring_emit(ring, MI_NOOP);
6596         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6597                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6598         intel_ring_emit(ring, fb->pitches[0]);
6599         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6600         intel_ring_emit(ring, MI_NOOP);
6601
6602         intel_ring_advance(ring);
6603         return 0;
6604
6605 err_unpin:
6606         intel_unpin_fb_obj(obj);
6607 err:
6608         return ret;
6609 }
6610
6611 static int intel_gen4_queue_flip(struct drm_device *dev,
6612                                  struct drm_crtc *crtc,
6613                                  struct drm_framebuffer *fb,
6614                                  struct drm_i915_gem_object *obj)
6615 {
6616         struct drm_i915_private *dev_priv = dev->dev_private;
6617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6618         uint32_t pf, pipesrc;
6619         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6620         int ret;
6621
6622         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6623         if (ret)
6624                 goto err;
6625
6626         ret = intel_ring_begin(ring, 4);
6627         if (ret)
6628                 goto err_unpin;
6629
6630         /* i965+ uses the linear or tiled offsets from the
6631          * Display Registers (which do not change across a page-flip)
6632          * so we need only reprogram the base address.
6633          */
6634         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6635                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6636         intel_ring_emit(ring, fb->pitches[0]);
6637         intel_ring_emit(ring,
6638                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6639                         obj->tiling_mode);
6640
6641         /* XXX Enabling the panel-fitter across page-flip is so far
6642          * untested on non-native modes, so ignore it for now.
6643          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6644          */
6645         pf = 0;
6646         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6647         intel_ring_emit(ring, pf | pipesrc);
6648         intel_ring_advance(ring);
6649         return 0;
6650
6651 err_unpin:
6652         intel_unpin_fb_obj(obj);
6653 err:
6654         return ret;
6655 }
6656
6657 static int intel_gen6_queue_flip(struct drm_device *dev,
6658                                  struct drm_crtc *crtc,
6659                                  struct drm_framebuffer *fb,
6660                                  struct drm_i915_gem_object *obj)
6661 {
6662         struct drm_i915_private *dev_priv = dev->dev_private;
6663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6665         uint32_t pf, pipesrc;
6666         int ret;
6667
6668         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6669         if (ret)
6670                 goto err;
6671
6672         ret = intel_ring_begin(ring, 4);
6673         if (ret)
6674                 goto err_unpin;
6675
6676         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6677                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6678         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6679         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6680
6681         /* Contrary to the suggestions in the documentation,
6682          * "Enable Panel Fitter" does not seem to be required when page
6683          * flipping with a non-native mode, and worse causes a normal
6684          * modeset to fail.
6685          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6686          */
6687         pf = 0;
6688         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6689         intel_ring_emit(ring, pf | pipesrc);
6690         intel_ring_advance(ring);
6691         return 0;
6692
6693 err_unpin:
6694         intel_unpin_fb_obj(obj);
6695 err:
6696         return ret;
6697 }
6698
6699 /*
6700  * On gen7 we currently use the blit ring because (in early silicon at least)
6701  * the render ring doesn't give us interrpts for page flip completion, which
6702  * means clients will hang after the first flip is queued.  Fortunately the
6703  * blit ring generates interrupts properly, so use it instead.
6704  */
6705 static int intel_gen7_queue_flip(struct drm_device *dev,
6706                                  struct drm_crtc *crtc,
6707                                  struct drm_framebuffer *fb,
6708                                  struct drm_i915_gem_object *obj)
6709 {
6710         struct drm_i915_private *dev_priv = dev->dev_private;
6711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6712         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6713         uint32_t plane_bit = 0;
6714         int ret;
6715
6716         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6717         if (ret)
6718                 goto err;
6719
6720         switch(intel_crtc->plane) {
6721         case PLANE_A:
6722                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6723                 break;
6724         case PLANE_B:
6725                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6726                 break;
6727         case PLANE_C:
6728                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6729                 break;
6730         default:
6731                 WARN_ONCE(1, "unknown plane in flip command\n");
6732                 ret = -ENODEV;
6733                 goto err_unpin;
6734         }
6735
6736         ret = intel_ring_begin(ring, 4);
6737         if (ret)
6738                 goto err_unpin;
6739
6740         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6741         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6742         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6743         intel_ring_emit(ring, (MI_NOOP));
6744         intel_ring_advance(ring);
6745         return 0;
6746
6747 err_unpin:
6748         intel_unpin_fb_obj(obj);
6749 err:
6750         return ret;
6751 }
6752
6753 static int intel_default_queue_flip(struct drm_device *dev,
6754                                     struct drm_crtc *crtc,
6755                                     struct drm_framebuffer *fb,
6756                                     struct drm_i915_gem_object *obj)
6757 {
6758         return -ENODEV;
6759 }
6760
6761 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6762                                 struct drm_framebuffer *fb,
6763                                 struct drm_pending_vblank_event *event)
6764 {
6765         struct drm_device *dev = crtc->dev;
6766         struct drm_i915_private *dev_priv = dev->dev_private;
6767         struct intel_framebuffer *intel_fb;
6768         struct drm_i915_gem_object *obj;
6769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6770         struct intel_unpin_work *work;
6771         unsigned long flags;
6772         int ret;
6773
6774         /* Can't change pixel format via MI display flips. */
6775         if (fb->pixel_format != crtc->fb->pixel_format)
6776                 return -EINVAL;
6777
6778         /*
6779          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6780          * Note that pitch changes could also affect these register.
6781          */
6782         if (INTEL_INFO(dev)->gen > 3 &&
6783             (fb->offsets[0] != crtc->fb->offsets[0] ||
6784              fb->pitches[0] != crtc->fb->pitches[0]))
6785                 return -EINVAL;
6786
6787         work = kzalloc(sizeof *work, GFP_KERNEL);
6788         if (work == NULL)
6789                 return -ENOMEM;
6790
6791         work->event = event;
6792         work->dev = crtc->dev;
6793         intel_fb = to_intel_framebuffer(crtc->fb);
6794         work->old_fb_obj = intel_fb->obj;
6795         INIT_WORK(&work->work, intel_unpin_work_fn);
6796
6797         ret = drm_vblank_get(dev, intel_crtc->pipe);
6798         if (ret)
6799                 goto free_work;
6800
6801         /* We borrow the event spin lock for protecting unpin_work */
6802         spin_lock_irqsave(&dev->event_lock, flags);
6803         if (intel_crtc->unpin_work) {
6804                 spin_unlock_irqrestore(&dev->event_lock, flags);
6805                 kfree(work);
6806                 drm_vblank_put(dev, intel_crtc->pipe);
6807
6808                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6809                 return -EBUSY;
6810         }
6811         intel_crtc->unpin_work = work;
6812         spin_unlock_irqrestore(&dev->event_lock, flags);
6813
6814         intel_fb = to_intel_framebuffer(fb);
6815         obj = intel_fb->obj;
6816
6817         ret = i915_mutex_lock_interruptible(dev);
6818         if (ret)
6819                 goto cleanup;
6820
6821         /* Reference the objects for the scheduled work. */
6822         drm_gem_object_reference(&work->old_fb_obj->base);
6823         drm_gem_object_reference(&obj->base);
6824
6825         crtc->fb = fb;
6826
6827         work->pending_flip_obj = obj;
6828
6829         work->enable_stall_check = true;
6830
6831         /* Block clients from rendering to the new back buffer until
6832          * the flip occurs and the object is no longer visible.
6833          */
6834         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6835
6836         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6837         if (ret)
6838                 goto cleanup_pending;
6839
6840         intel_disable_fbc(dev);
6841         intel_mark_fb_busy(obj);
6842         mutex_unlock(&dev->struct_mutex);
6843
6844         trace_i915_flip_request(intel_crtc->plane, obj);
6845
6846         return 0;
6847
6848 cleanup_pending:
6849         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6850         drm_gem_object_unreference(&work->old_fb_obj->base);
6851         drm_gem_object_unreference(&obj->base);
6852         mutex_unlock(&dev->struct_mutex);
6853
6854 cleanup:
6855         spin_lock_irqsave(&dev->event_lock, flags);
6856         intel_crtc->unpin_work = NULL;
6857         spin_unlock_irqrestore(&dev->event_lock, flags);
6858
6859         drm_vblank_put(dev, intel_crtc->pipe);
6860 free_work:
6861         kfree(work);
6862
6863         return ret;
6864 }
6865
6866 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6867         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6868         .load_lut = intel_crtc_load_lut,
6869         .disable = intel_crtc_noop,
6870 };
6871
6872 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6873 {
6874         struct intel_encoder *other_encoder;
6875         struct drm_crtc *crtc = &encoder->new_crtc->base;
6876
6877         if (WARN_ON(!crtc))
6878                 return false;
6879
6880         list_for_each_entry(other_encoder,
6881                             &crtc->dev->mode_config.encoder_list,
6882                             base.head) {
6883
6884                 if (&other_encoder->new_crtc->base != crtc ||
6885                     encoder == other_encoder)
6886                         continue;
6887                 else
6888                         return true;
6889         }
6890
6891         return false;
6892 }
6893
6894 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6895                                   struct drm_crtc *crtc)
6896 {
6897         struct drm_device *dev;
6898         struct drm_crtc *tmp;
6899         int crtc_mask = 1;
6900
6901         WARN(!crtc, "checking null crtc?\n");
6902
6903         dev = crtc->dev;
6904
6905         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6906                 if (tmp == crtc)
6907                         break;
6908                 crtc_mask <<= 1;
6909         }
6910
6911         if (encoder->possible_crtcs & crtc_mask)
6912                 return true;
6913         return false;
6914 }
6915
6916 /**
6917  * intel_modeset_update_staged_output_state
6918  *
6919  * Updates the staged output configuration state, e.g. after we've read out the
6920  * current hw state.
6921  */
6922 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6923 {
6924         struct intel_encoder *encoder;
6925         struct intel_connector *connector;
6926
6927         list_for_each_entry(connector, &dev->mode_config.connector_list,
6928                             base.head) {
6929                 connector->new_encoder =
6930                         to_intel_encoder(connector->base.encoder);
6931         }
6932
6933         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6934                             base.head) {
6935                 encoder->new_crtc =
6936                         to_intel_crtc(encoder->base.crtc);
6937         }
6938 }
6939
6940 /**
6941  * intel_modeset_commit_output_state
6942  *
6943  * This function copies the stage display pipe configuration to the real one.
6944  */
6945 static void intel_modeset_commit_output_state(struct drm_device *dev)
6946 {
6947         struct intel_encoder *encoder;
6948         struct intel_connector *connector;
6949
6950         list_for_each_entry(connector, &dev->mode_config.connector_list,
6951                             base.head) {
6952                 connector->base.encoder = &connector->new_encoder->base;
6953         }
6954
6955         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6956                             base.head) {
6957                 encoder->base.crtc = &encoder->new_crtc->base;
6958         }
6959 }
6960
6961 static struct drm_display_mode *
6962 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6963                             struct drm_display_mode *mode)
6964 {
6965         struct drm_device *dev = crtc->dev;
6966         struct drm_display_mode *adjusted_mode;
6967         struct drm_encoder_helper_funcs *encoder_funcs;
6968         struct intel_encoder *encoder;
6969
6970         adjusted_mode = drm_mode_duplicate(dev, mode);
6971         if (!adjusted_mode)
6972                 return ERR_PTR(-ENOMEM);
6973
6974         /* Pass our mode to the connectors and the CRTC to give them a chance to
6975          * adjust it according to limitations or connector properties, and also
6976          * a chance to reject the mode entirely.
6977          */
6978         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6979                             base.head) {
6980
6981                 if (&encoder->new_crtc->base != crtc)
6982                         continue;
6983                 encoder_funcs = encoder->base.helper_private;
6984                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6985                                                 adjusted_mode))) {
6986                         DRM_DEBUG_KMS("Encoder fixup failed\n");
6987                         goto fail;
6988                 }
6989         }
6990
6991         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6992                 DRM_DEBUG_KMS("CRTC fixup failed\n");
6993                 goto fail;
6994         }
6995         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6996
6997         return adjusted_mode;
6998 fail:
6999         drm_mode_destroy(dev, adjusted_mode);
7000         return ERR_PTR(-EINVAL);
7001 }
7002
7003 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7004  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7005 static void
7006 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7007                              unsigned *prepare_pipes, unsigned *disable_pipes)
7008 {
7009         struct intel_crtc *intel_crtc;
7010         struct drm_device *dev = crtc->dev;
7011         struct intel_encoder *encoder;
7012         struct intel_connector *connector;
7013         struct drm_crtc *tmp_crtc;
7014
7015         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7016
7017         /* Check which crtcs have changed outputs connected to them, these need
7018          * to be part of the prepare_pipes mask. We don't (yet) support global
7019          * modeset across multiple crtcs, so modeset_pipes will only have one
7020          * bit set at most. */
7021         list_for_each_entry(connector, &dev->mode_config.connector_list,
7022                             base.head) {
7023                 if (connector->base.encoder == &connector->new_encoder->base)
7024                         continue;
7025
7026                 if (connector->base.encoder) {
7027                         tmp_crtc = connector->base.encoder->crtc;
7028
7029                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7030                 }
7031
7032                 if (connector->new_encoder)
7033                         *prepare_pipes |=
7034                                 1 << connector->new_encoder->new_crtc->pipe;
7035         }
7036
7037         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7038                             base.head) {
7039                 if (encoder->base.crtc == &encoder->new_crtc->base)
7040                         continue;
7041
7042                 if (encoder->base.crtc) {
7043                         tmp_crtc = encoder->base.crtc;
7044
7045                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7046                 }
7047
7048                 if (encoder->new_crtc)
7049                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7050         }
7051
7052         /* Check for any pipes that will be fully disabled ... */
7053         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7054                             base.head) {
7055                 bool used = false;
7056
7057                 /* Don't try to disable disabled crtcs. */
7058                 if (!intel_crtc->base.enabled)
7059                         continue;
7060
7061                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7062                                     base.head) {
7063                         if (encoder->new_crtc == intel_crtc)
7064                                 used = true;
7065                 }
7066
7067                 if (!used)
7068                         *disable_pipes |= 1 << intel_crtc->pipe;
7069         }
7070
7071
7072         /* set_mode is also used to update properties on life display pipes. */
7073         intel_crtc = to_intel_crtc(crtc);
7074         if (crtc->enabled)
7075                 *prepare_pipes |= 1 << intel_crtc->pipe;
7076
7077         /* We only support modeset on one single crtc, hence we need to do that
7078          * only for the passed in crtc iff we change anything else than just
7079          * disable crtcs.
7080          *
7081          * This is actually not true, to be fully compatible with the old crtc
7082          * helper we automatically disable _any_ output (i.e. doesn't need to be
7083          * connected to the crtc we're modesetting on) if it's disconnected.
7084          * Which is a rather nutty api (since changed the output configuration
7085          * without userspace's explicit request can lead to confusion), but
7086          * alas. Hence we currently need to modeset on all pipes we prepare. */
7087         if (*prepare_pipes)
7088                 *modeset_pipes = *prepare_pipes;
7089
7090         /* ... and mask these out. */
7091         *modeset_pipes &= ~(*disable_pipes);
7092         *prepare_pipes &= ~(*disable_pipes);
7093 }
7094
7095 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7096 {
7097         struct drm_encoder *encoder;
7098         struct drm_device *dev = crtc->dev;
7099
7100         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7101                 if (encoder->crtc == crtc)
7102                         return true;
7103
7104         return false;
7105 }
7106
7107 static void
7108 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7109 {
7110         struct intel_encoder *intel_encoder;
7111         struct intel_crtc *intel_crtc;
7112         struct drm_connector *connector;
7113
7114         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7115                             base.head) {
7116                 if (!intel_encoder->base.crtc)
7117                         continue;
7118
7119                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7120
7121                 if (prepare_pipes & (1 << intel_crtc->pipe))
7122                         intel_encoder->connectors_active = false;
7123         }
7124
7125         intel_modeset_commit_output_state(dev);
7126
7127         /* Update computed state. */
7128         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7129                             base.head) {
7130                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7131         }
7132
7133         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7134                 if (!connector->encoder || !connector->encoder->crtc)
7135                         continue;
7136
7137                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7138
7139                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7140                         struct drm_property *dpms_property =
7141                                 dev->mode_config.dpms_property;
7142
7143                         connector->dpms = DRM_MODE_DPMS_ON;
7144                         drm_connector_property_set_value(connector,
7145                                                          dpms_property,
7146                                                          DRM_MODE_DPMS_ON);
7147
7148                         intel_encoder = to_intel_encoder(connector->encoder);
7149                         intel_encoder->connectors_active = true;
7150                 }
7151         }
7152
7153 }
7154
7155 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7156         list_for_each_entry((intel_crtc), \
7157                             &(dev)->mode_config.crtc_list, \
7158                             base.head) \
7159                 if (mask & (1 <<(intel_crtc)->pipe)) \
7160
7161 void
7162 intel_modeset_check_state(struct drm_device *dev)
7163 {
7164         struct intel_crtc *crtc;
7165         struct intel_encoder *encoder;
7166         struct intel_connector *connector;
7167
7168         list_for_each_entry(connector, &dev->mode_config.connector_list,
7169                             base.head) {
7170                 /* This also checks the encoder/connector hw state with the
7171                  * ->get_hw_state callbacks. */
7172                 intel_connector_check_state(connector);
7173
7174                 WARN(&connector->new_encoder->base != connector->base.encoder,
7175                      "connector's staged encoder doesn't match current encoder\n");
7176         }
7177
7178         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7179                             base.head) {
7180                 bool enabled = false;
7181                 bool active = false;
7182                 enum pipe pipe, tracked_pipe;
7183
7184                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7185                               encoder->base.base.id,
7186                               drm_get_encoder_name(&encoder->base));
7187
7188                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7189                      "encoder's stage crtc doesn't match current crtc\n");
7190                 WARN(encoder->connectors_active && !encoder->base.crtc,
7191                      "encoder's active_connectors set, but no crtc\n");
7192
7193                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7194                                     base.head) {
7195                         if (connector->base.encoder != &encoder->base)
7196                                 continue;
7197                         enabled = true;
7198                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7199                                 active = true;
7200                 }
7201                 WARN(!!encoder->base.crtc != enabled,
7202                      "encoder's enabled state mismatch "
7203                      "(expected %i, found %i)\n",
7204                      !!encoder->base.crtc, enabled);
7205                 WARN(active && !encoder->base.crtc,
7206                      "active encoder with no crtc\n");
7207
7208                 WARN(encoder->connectors_active != active,
7209                      "encoder's computed active state doesn't match tracked active state "
7210                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7211
7212                 active = encoder->get_hw_state(encoder, &pipe);
7213                 WARN(active != encoder->connectors_active,
7214                      "encoder's hw state doesn't match sw tracking "
7215                      "(expected %i, found %i)\n",
7216                      encoder->connectors_active, active);
7217
7218                 if (!encoder->base.crtc)
7219                         continue;
7220
7221                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7222                 WARN(active && pipe != tracked_pipe,
7223                      "active encoder's pipe doesn't match"
7224                      "(expected %i, found %i)\n",
7225                      tracked_pipe, pipe);
7226
7227         }
7228
7229         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7230                             base.head) {
7231                 bool enabled = false;
7232                 bool active = false;
7233
7234                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7235                               crtc->base.base.id);
7236
7237                 WARN(crtc->active && !crtc->base.enabled,
7238                      "active crtc, but not enabled in sw tracking\n");
7239
7240                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7241                                     base.head) {
7242                         if (encoder->base.crtc != &crtc->base)
7243                                 continue;
7244                         enabled = true;
7245                         if (encoder->connectors_active)
7246                                 active = true;
7247                 }
7248                 WARN(active != crtc->active,
7249                      "crtc's computed active state doesn't match tracked active state "
7250                      "(expected %i, found %i)\n", active, crtc->active);
7251                 WARN(enabled != crtc->base.enabled,
7252                      "crtc's computed enabled state doesn't match tracked enabled state "
7253                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7254
7255                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7256         }
7257 }
7258
7259 bool intel_set_mode(struct drm_crtc *crtc,
7260                     struct drm_display_mode *mode,
7261                     int x, int y, struct drm_framebuffer *fb)
7262 {
7263         struct drm_device *dev = crtc->dev;
7264         drm_i915_private_t *dev_priv = dev->dev_private;
7265         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7266         struct drm_encoder_helper_funcs *encoder_funcs;
7267         struct drm_encoder *encoder;
7268         struct intel_crtc *intel_crtc;
7269         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7270         bool ret = true;
7271
7272         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7273                                      &prepare_pipes, &disable_pipes);
7274
7275         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7276                       modeset_pipes, prepare_pipes, disable_pipes);
7277
7278         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7279                 intel_crtc_disable(&intel_crtc->base);
7280
7281         saved_hwmode = crtc->hwmode;
7282         saved_mode = crtc->mode;
7283
7284         /* Hack: Because we don't (yet) support global modeset on multiple
7285          * crtcs, we don't keep track of the new mode for more than one crtc.
7286          * Hence simply check whether any bit is set in modeset_pipes in all the
7287          * pieces of code that are not yet converted to deal with mutliple crtcs
7288          * changing their mode at the same time. */
7289         adjusted_mode = NULL;
7290         if (modeset_pipes) {
7291                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7292                 if (IS_ERR(adjusted_mode)) {
7293                         return false;
7294                 }
7295         }
7296
7297         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7298                 if (intel_crtc->base.enabled)
7299                         dev_priv->display.crtc_disable(&intel_crtc->base);
7300         }
7301
7302         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7303          * to set it here already despite that we pass it down the callchain.
7304          */
7305         if (modeset_pipes)
7306                 crtc->mode = *mode;
7307
7308         /* Only after disabling all output pipelines that will be changed can we
7309          * update the the output configuration. */
7310         intel_modeset_update_state(dev, prepare_pipes);
7311
7312         /* Set up the DPLL and any encoders state that needs to adjust or depend
7313          * on the DPLL.
7314          */
7315         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7316                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7317                                            mode, adjusted_mode,
7318                                            x, y, fb);
7319                 if (!ret)
7320                     goto done;
7321
7322                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7323
7324                         if (encoder->crtc != &intel_crtc->base)
7325                                 continue;
7326
7327                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7328                                 encoder->base.id, drm_get_encoder_name(encoder),
7329                                 mode->base.id, mode->name);
7330                         encoder_funcs = encoder->helper_private;
7331                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7332                 }
7333         }
7334
7335         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7336         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7337                 dev_priv->display.crtc_enable(&intel_crtc->base);
7338
7339         if (modeset_pipes) {
7340                 /* Store real post-adjustment hardware mode. */
7341                 crtc->hwmode = *adjusted_mode;
7342
7343                 /* Calculate and store various constants which
7344                  * are later needed by vblank and swap-completion
7345                  * timestamping. They are derived from true hwmode.
7346                  */
7347                 drm_calc_timestamping_constants(crtc);
7348         }
7349
7350         /* FIXME: add subpixel order */
7351 done:
7352         drm_mode_destroy(dev, adjusted_mode);
7353         if (!ret && crtc->enabled) {
7354                 crtc->hwmode = saved_hwmode;
7355                 crtc->mode = saved_mode;
7356         } else {
7357                 intel_modeset_check_state(dev);
7358         }
7359
7360         return ret;
7361 }
7362
7363 #undef for_each_intel_crtc_masked
7364
7365 static void intel_set_config_free(struct intel_set_config *config)
7366 {
7367         if (!config)
7368                 return;
7369
7370         kfree(config->save_connector_encoders);
7371         kfree(config->save_encoder_crtcs);
7372         kfree(config);
7373 }
7374
7375 static int intel_set_config_save_state(struct drm_device *dev,
7376                                        struct intel_set_config *config)
7377 {
7378         struct drm_encoder *encoder;
7379         struct drm_connector *connector;
7380         int count;
7381
7382         config->save_encoder_crtcs =
7383                 kcalloc(dev->mode_config.num_encoder,
7384                         sizeof(struct drm_crtc *), GFP_KERNEL);
7385         if (!config->save_encoder_crtcs)
7386                 return -ENOMEM;
7387
7388         config->save_connector_encoders =
7389                 kcalloc(dev->mode_config.num_connector,
7390                         sizeof(struct drm_encoder *), GFP_KERNEL);
7391         if (!config->save_connector_encoders)
7392                 return -ENOMEM;
7393
7394         /* Copy data. Note that driver private data is not affected.
7395          * Should anything bad happen only the expected state is
7396          * restored, not the drivers personal bookkeeping.
7397          */
7398         count = 0;
7399         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7400                 config->save_encoder_crtcs[count++] = encoder->crtc;
7401         }
7402
7403         count = 0;
7404         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7405                 config->save_connector_encoders[count++] = connector->encoder;
7406         }
7407
7408         return 0;
7409 }
7410
7411 static void intel_set_config_restore_state(struct drm_device *dev,
7412                                            struct intel_set_config *config)
7413 {
7414         struct intel_encoder *encoder;
7415         struct intel_connector *connector;
7416         int count;
7417
7418         count = 0;
7419         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7420                 encoder->new_crtc =
7421                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7422         }
7423
7424         count = 0;
7425         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7426                 connector->new_encoder =
7427                         to_intel_encoder(config->save_connector_encoders[count++]);
7428         }
7429 }
7430
7431 static void
7432 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7433                                       struct intel_set_config *config)
7434 {
7435
7436         /* We should be able to check here if the fb has the same properties
7437          * and then just flip_or_move it */
7438         if (set->crtc->fb != set->fb) {
7439                 /* If we have no fb then treat it as a full mode set */
7440                 if (set->crtc->fb == NULL) {
7441                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7442                         config->mode_changed = true;
7443                 } else if (set->fb == NULL) {
7444                         config->mode_changed = true;
7445                 } else if (set->fb->depth != set->crtc->fb->depth) {
7446                         config->mode_changed = true;
7447                 } else if (set->fb->bits_per_pixel !=
7448                            set->crtc->fb->bits_per_pixel) {
7449                         config->mode_changed = true;
7450                 } else
7451                         config->fb_changed = true;
7452         }
7453
7454         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7455                 config->fb_changed = true;
7456
7457         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7458                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7459                 drm_mode_debug_printmodeline(&set->crtc->mode);
7460                 drm_mode_debug_printmodeline(set->mode);
7461                 config->mode_changed = true;
7462         }
7463 }
7464
7465 static int
7466 intel_modeset_stage_output_state(struct drm_device *dev,
7467                                  struct drm_mode_set *set,
7468                                  struct intel_set_config *config)
7469 {
7470         struct drm_crtc *new_crtc;
7471         struct intel_connector *connector;
7472         struct intel_encoder *encoder;
7473         int count, ro;
7474
7475         /* The upper layers ensure that we either disabl a crtc or have a list
7476          * of connectors. For paranoia, double-check this. */
7477         WARN_ON(!set->fb && (set->num_connectors != 0));
7478         WARN_ON(set->fb && (set->num_connectors == 0));
7479
7480         count = 0;
7481         list_for_each_entry(connector, &dev->mode_config.connector_list,
7482                             base.head) {
7483                 /* Otherwise traverse passed in connector list and get encoders
7484                  * for them. */
7485                 for (ro = 0; ro < set->num_connectors; ro++) {
7486                         if (set->connectors[ro] == &connector->base) {
7487                                 connector->new_encoder = connector->encoder;
7488                                 break;
7489                         }
7490                 }
7491
7492                 /* If we disable the crtc, disable all its connectors. Also, if
7493                  * the connector is on the changing crtc but not on the new
7494                  * connector list, disable it. */
7495                 if ((!set->fb || ro == set->num_connectors) &&
7496                     connector->base.encoder &&
7497                     connector->base.encoder->crtc == set->crtc) {
7498                         connector->new_encoder = NULL;
7499
7500                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7501                                 connector->base.base.id,
7502                                 drm_get_connector_name(&connector->base));
7503                 }
7504
7505
7506                 if (&connector->new_encoder->base != connector->base.encoder) {
7507                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7508                         config->mode_changed = true;
7509                 }
7510
7511                 /* Disable all disconnected encoders. */
7512                 if (connector->base.status == connector_status_disconnected)
7513                         connector->new_encoder = NULL;
7514         }
7515         /* connector->new_encoder is now updated for all connectors. */
7516
7517         /* Update crtc of enabled connectors. */
7518         count = 0;
7519         list_for_each_entry(connector, &dev->mode_config.connector_list,
7520                             base.head) {
7521                 if (!connector->new_encoder)
7522                         continue;
7523
7524                 new_crtc = connector->new_encoder->base.crtc;
7525
7526                 for (ro = 0; ro < set->num_connectors; ro++) {
7527                         if (set->connectors[ro] == &connector->base)
7528                                 new_crtc = set->crtc;
7529                 }
7530
7531                 /* Make sure the new CRTC will work with the encoder */
7532                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7533                                            new_crtc)) {
7534                         return -EINVAL;
7535                 }
7536                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7537
7538                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7539                         connector->base.base.id,
7540                         drm_get_connector_name(&connector->base),
7541                         new_crtc->base.id);
7542         }
7543
7544         /* Check for any encoders that needs to be disabled. */
7545         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7546                             base.head) {
7547                 list_for_each_entry(connector,
7548                                     &dev->mode_config.connector_list,
7549                                     base.head) {
7550                         if (connector->new_encoder == encoder) {
7551                                 WARN_ON(!connector->new_encoder->new_crtc);
7552
7553                                 goto next_encoder;
7554                         }
7555                 }
7556                 encoder->new_crtc = NULL;
7557 next_encoder:
7558                 /* Only now check for crtc changes so we don't miss encoders
7559                  * that will be disabled. */
7560                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7561                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7562                         config->mode_changed = true;
7563                 }
7564         }
7565         /* Now we've also updated encoder->new_crtc for all encoders. */
7566
7567         return 0;
7568 }
7569
7570 static int intel_crtc_set_config(struct drm_mode_set *set)
7571 {
7572         struct drm_device *dev;
7573         struct drm_mode_set save_set;
7574         struct intel_set_config *config;
7575         int ret;
7576
7577         BUG_ON(!set);
7578         BUG_ON(!set->crtc);
7579         BUG_ON(!set->crtc->helper_private);
7580
7581         if (!set->mode)
7582                 set->fb = NULL;
7583
7584         /* The fb helper likes to play gross jokes with ->mode_set_config.
7585          * Unfortunately the crtc helper doesn't do much at all for this case,
7586          * so we have to cope with this madness until the fb helper is fixed up. */
7587         if (set->fb && set->num_connectors == 0)
7588                 return 0;
7589
7590         if (set->fb) {
7591                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7592                                 set->crtc->base.id, set->fb->base.id,
7593                                 (int)set->num_connectors, set->x, set->y);
7594         } else {
7595                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7596         }
7597
7598         dev = set->crtc->dev;
7599
7600         ret = -ENOMEM;
7601         config = kzalloc(sizeof(*config), GFP_KERNEL);
7602         if (!config)
7603                 goto out_config;
7604
7605         ret = intel_set_config_save_state(dev, config);
7606         if (ret)
7607                 goto out_config;
7608
7609         save_set.crtc = set->crtc;
7610         save_set.mode = &set->crtc->mode;
7611         save_set.x = set->crtc->x;
7612         save_set.y = set->crtc->y;
7613         save_set.fb = set->crtc->fb;
7614
7615         /* Compute whether we need a full modeset, only an fb base update or no
7616          * change at all. In the future we might also check whether only the
7617          * mode changed, e.g. for LVDS where we only change the panel fitter in
7618          * such cases. */
7619         intel_set_config_compute_mode_changes(set, config);
7620
7621         ret = intel_modeset_stage_output_state(dev, set, config);
7622         if (ret)
7623                 goto fail;
7624
7625         if (config->mode_changed) {
7626                 if (set->mode) {
7627                         DRM_DEBUG_KMS("attempting to set mode from"
7628                                         " userspace\n");
7629                         drm_mode_debug_printmodeline(set->mode);
7630                 }
7631
7632                 if (!intel_set_mode(set->crtc, set->mode,
7633                                     set->x, set->y, set->fb)) {
7634                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7635                                   set->crtc->base.id);
7636                         ret = -EINVAL;
7637                         goto fail;
7638                 }
7639         } else if (config->fb_changed) {
7640                 ret = intel_pipe_set_base(set->crtc,
7641                                           set->x, set->y, set->fb);
7642         }
7643
7644         intel_set_config_free(config);
7645
7646         return 0;
7647
7648 fail:
7649         intel_set_config_restore_state(dev, config);
7650
7651         /* Try to restore the config */
7652         if (config->mode_changed &&
7653             !intel_set_mode(save_set.crtc, save_set.mode,
7654                             save_set.x, save_set.y, save_set.fb))
7655                 DRM_ERROR("failed to restore config after modeset failure\n");
7656
7657 out_config:
7658         intel_set_config_free(config);
7659         return ret;
7660 }
7661
7662 static const struct drm_crtc_funcs intel_crtc_funcs = {
7663         .cursor_set = intel_crtc_cursor_set,
7664         .cursor_move = intel_crtc_cursor_move,
7665         .gamma_set = intel_crtc_gamma_set,
7666         .set_config = intel_crtc_set_config,
7667         .destroy = intel_crtc_destroy,
7668         .page_flip = intel_crtc_page_flip,
7669 };
7670
7671 static void intel_cpu_pll_init(struct drm_device *dev)
7672 {
7673         if (IS_HASWELL(dev))
7674                 intel_ddi_pll_init(dev);
7675 }
7676
7677 static void intel_pch_pll_init(struct drm_device *dev)
7678 {
7679         drm_i915_private_t *dev_priv = dev->dev_private;
7680         int i;
7681
7682         if (dev_priv->num_pch_pll == 0) {
7683                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7684                 return;
7685         }
7686
7687         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7688                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7689                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7690                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7691         }
7692 }
7693
7694 static void intel_crtc_init(struct drm_device *dev, int pipe)
7695 {
7696         drm_i915_private_t *dev_priv = dev->dev_private;
7697         struct intel_crtc *intel_crtc;
7698         int i;
7699
7700         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7701         if (intel_crtc == NULL)
7702                 return;
7703
7704         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7705
7706         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7707         for (i = 0; i < 256; i++) {
7708                 intel_crtc->lut_r[i] = i;
7709                 intel_crtc->lut_g[i] = i;
7710                 intel_crtc->lut_b[i] = i;
7711         }
7712
7713         /* Swap pipes & planes for FBC on pre-965 */
7714         intel_crtc->pipe = pipe;
7715         intel_crtc->plane = pipe;
7716         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7717                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7718                 intel_crtc->plane = !pipe;
7719         }
7720
7721         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7722                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7723         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7724         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7725
7726         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7727
7728         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7729 }
7730
7731 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7732                                 struct drm_file *file)
7733 {
7734         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7735         struct drm_mode_object *drmmode_obj;
7736         struct intel_crtc *crtc;
7737
7738         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7739                 return -ENODEV;
7740
7741         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7742                         DRM_MODE_OBJECT_CRTC);
7743
7744         if (!drmmode_obj) {
7745                 DRM_ERROR("no such CRTC id\n");
7746                 return -EINVAL;
7747         }
7748
7749         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7750         pipe_from_crtc_id->pipe = crtc->pipe;
7751
7752         return 0;
7753 }
7754
7755 static int intel_encoder_clones(struct intel_encoder *encoder)
7756 {
7757         struct drm_device *dev = encoder->base.dev;
7758         struct intel_encoder *source_encoder;
7759         int index_mask = 0;
7760         int entry = 0;
7761
7762         list_for_each_entry(source_encoder,
7763                             &dev->mode_config.encoder_list, base.head) {
7764
7765                 if (encoder == source_encoder)
7766                         index_mask |= (1 << entry);
7767
7768                 /* Intel hw has only one MUX where enocoders could be cloned. */
7769                 if (encoder->cloneable && source_encoder->cloneable)
7770                         index_mask |= (1 << entry);
7771
7772                 entry++;
7773         }
7774
7775         return index_mask;
7776 }
7777
7778 static bool has_edp_a(struct drm_device *dev)
7779 {
7780         struct drm_i915_private *dev_priv = dev->dev_private;
7781
7782         if (!IS_MOBILE(dev))
7783                 return false;
7784
7785         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7786                 return false;
7787
7788         if (IS_GEN5(dev) &&
7789             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7790                 return false;
7791
7792         return true;
7793 }
7794
7795 static void intel_setup_outputs(struct drm_device *dev)
7796 {
7797         struct drm_i915_private *dev_priv = dev->dev_private;
7798         struct intel_encoder *encoder;
7799         bool dpd_is_edp = false;
7800         bool has_lvds;
7801
7802         has_lvds = intel_lvds_init(dev);
7803         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7804                 /* disable the panel fitter on everything but LVDS */
7805                 I915_WRITE(PFIT_CONTROL, 0);
7806         }
7807
7808         if (HAS_PCH_SPLIT(dev)) {
7809                 dpd_is_edp = intel_dpd_is_edp(dev);
7810
7811                 if (has_edp_a(dev))
7812                         intel_dp_init(dev, DP_A, PORT_A);
7813
7814                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7815                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7816         }
7817
7818         intel_crt_init(dev);
7819
7820         if (IS_HASWELL(dev)) {
7821                 int found;
7822
7823                 /* Haswell uses DDI functions to detect digital outputs */
7824                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7825                 /* DDI A only supports eDP */
7826                 if (found)
7827                         intel_ddi_init(dev, PORT_A);
7828
7829                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7830                  * register */
7831                 found = I915_READ(SFUSE_STRAP);
7832
7833                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7834                         intel_ddi_init(dev, PORT_B);
7835                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7836                         intel_ddi_init(dev, PORT_C);
7837                 if (found & SFUSE_STRAP_DDID_DETECTED)
7838                         intel_ddi_init(dev, PORT_D);
7839         } else if (HAS_PCH_SPLIT(dev)) {
7840                 int found;
7841
7842                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7843                         /* PCH SDVOB multiplex with HDMIB */
7844                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7845                         if (!found)
7846                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7847                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7848                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7849                 }
7850
7851                 if (I915_READ(HDMIC) & PORT_DETECTED)
7852                         intel_hdmi_init(dev, HDMIC, PORT_C);
7853
7854                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7855                         intel_hdmi_init(dev, HDMID, PORT_D);
7856
7857                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7858                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7859
7860                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7861                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7862         } else if (IS_VALLEYVIEW(dev)) {
7863                 int found;
7864
7865                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7866                 if (I915_READ(DP_C) & DP_DETECTED)
7867                         intel_dp_init(dev, DP_C, PORT_C);
7868
7869                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7870                         /* SDVOB multiplex with HDMIB */
7871                         found = intel_sdvo_init(dev, SDVOB, true);
7872                         if (!found)
7873                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7874                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7875                                 intel_dp_init(dev, DP_B, PORT_B);
7876                 }
7877
7878                 if (I915_READ(SDVOC) & PORT_DETECTED)
7879                         intel_hdmi_init(dev, SDVOC, PORT_C);
7880
7881         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7882                 bool found = false;
7883
7884                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7885                         DRM_DEBUG_KMS("probing SDVOB\n");
7886                         found = intel_sdvo_init(dev, SDVOB, true);
7887                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7888                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7889                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7890                         }
7891
7892                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7893                                 DRM_DEBUG_KMS("probing DP_B\n");
7894                                 intel_dp_init(dev, DP_B, PORT_B);
7895                         }
7896                 }
7897
7898                 /* Before G4X SDVOC doesn't have its own detect register */
7899
7900                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7901                         DRM_DEBUG_KMS("probing SDVOC\n");
7902                         found = intel_sdvo_init(dev, SDVOC, false);
7903                 }
7904
7905                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7906
7907                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7908                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7909                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7910                         }
7911                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7912                                 DRM_DEBUG_KMS("probing DP_C\n");
7913                                 intel_dp_init(dev, DP_C, PORT_C);
7914                         }
7915                 }
7916
7917                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7918                     (I915_READ(DP_D) & DP_DETECTED)) {
7919                         DRM_DEBUG_KMS("probing DP_D\n");
7920                         intel_dp_init(dev, DP_D, PORT_D);
7921                 }
7922         } else if (IS_GEN2(dev))
7923                 intel_dvo_init(dev);
7924
7925         if (SUPPORTS_TV(dev))
7926                 intel_tv_init(dev);
7927
7928         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7929                 encoder->base.possible_crtcs = encoder->crtc_mask;
7930                 encoder->base.possible_clones =
7931                         intel_encoder_clones(encoder);
7932         }
7933
7934         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7935                 ironlake_init_pch_refclk(dev);
7936 }
7937
7938 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7939 {
7940         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7941
7942         drm_framebuffer_cleanup(fb);
7943         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7944
7945         kfree(intel_fb);
7946 }
7947
7948 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7949                                                 struct drm_file *file,
7950                                                 unsigned int *handle)
7951 {
7952         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7953         struct drm_i915_gem_object *obj = intel_fb->obj;
7954
7955         return drm_gem_handle_create(file, &obj->base, handle);
7956 }
7957
7958 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7959         .destroy = intel_user_framebuffer_destroy,
7960         .create_handle = intel_user_framebuffer_create_handle,
7961 };
7962
7963 int intel_framebuffer_init(struct drm_device *dev,
7964                            struct intel_framebuffer *intel_fb,
7965                            struct drm_mode_fb_cmd2 *mode_cmd,
7966                            struct drm_i915_gem_object *obj)
7967 {
7968         int ret;
7969
7970         if (obj->tiling_mode == I915_TILING_Y)
7971                 return -EINVAL;
7972
7973         if (mode_cmd->pitches[0] & 63)
7974                 return -EINVAL;
7975
7976         switch (mode_cmd->pixel_format) {
7977         case DRM_FORMAT_RGB332:
7978         case DRM_FORMAT_RGB565:
7979         case DRM_FORMAT_XRGB8888:
7980         case DRM_FORMAT_XBGR8888:
7981         case DRM_FORMAT_ARGB8888:
7982         case DRM_FORMAT_XRGB2101010:
7983         case DRM_FORMAT_ARGB2101010:
7984                 /* RGB formats are common across chipsets */
7985                 break;
7986         case DRM_FORMAT_YUYV:
7987         case DRM_FORMAT_UYVY:
7988         case DRM_FORMAT_YVYU:
7989         case DRM_FORMAT_VYUY:
7990                 break;
7991         default:
7992                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7993                                 mode_cmd->pixel_format);
7994                 return -EINVAL;
7995         }
7996
7997         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7998         if (ret) {
7999                 DRM_ERROR("framebuffer init failed %d\n", ret);
8000                 return ret;
8001         }
8002
8003         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8004         intel_fb->obj = obj;
8005         return 0;
8006 }
8007
8008 static struct drm_framebuffer *
8009 intel_user_framebuffer_create(struct drm_device *dev,
8010                               struct drm_file *filp,
8011                               struct drm_mode_fb_cmd2 *mode_cmd)
8012 {
8013         struct drm_i915_gem_object *obj;
8014
8015         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8016                                                 mode_cmd->handles[0]));
8017         if (&obj->base == NULL)
8018                 return ERR_PTR(-ENOENT);
8019
8020         return intel_framebuffer_create(dev, mode_cmd, obj);
8021 }
8022
8023 static const struct drm_mode_config_funcs intel_mode_funcs = {
8024         .fb_create = intel_user_framebuffer_create,
8025         .output_poll_changed = intel_fb_output_poll_changed,
8026 };
8027
8028 /* Set up chip specific display functions */
8029 static void intel_init_display(struct drm_device *dev)
8030 {
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032
8033         /* We always want a DPMS function */
8034         if (IS_HASWELL(dev)) {
8035                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8036                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8037                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8038                 dev_priv->display.off = ironlake_crtc_off;
8039                 dev_priv->display.update_plane = ironlake_update_plane;
8040         } else if (HAS_PCH_SPLIT(dev)) {
8041                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8042                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8043                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8044                 dev_priv->display.off = ironlake_crtc_off;
8045                 dev_priv->display.update_plane = ironlake_update_plane;
8046         } else {
8047                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8048                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8049                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8050                 dev_priv->display.off = i9xx_crtc_off;
8051                 dev_priv->display.update_plane = i9xx_update_plane;
8052         }
8053
8054         /* Returns the core display clock speed */
8055         if (IS_VALLEYVIEW(dev))
8056                 dev_priv->display.get_display_clock_speed =
8057                         valleyview_get_display_clock_speed;
8058         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8059                 dev_priv->display.get_display_clock_speed =
8060                         i945_get_display_clock_speed;
8061         else if (IS_I915G(dev))
8062                 dev_priv->display.get_display_clock_speed =
8063                         i915_get_display_clock_speed;
8064         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8065                 dev_priv->display.get_display_clock_speed =
8066                         i9xx_misc_get_display_clock_speed;
8067         else if (IS_I915GM(dev))
8068                 dev_priv->display.get_display_clock_speed =
8069                         i915gm_get_display_clock_speed;
8070         else if (IS_I865G(dev))
8071                 dev_priv->display.get_display_clock_speed =
8072                         i865_get_display_clock_speed;
8073         else if (IS_I85X(dev))
8074                 dev_priv->display.get_display_clock_speed =
8075                         i855_get_display_clock_speed;
8076         else /* 852, 830 */
8077                 dev_priv->display.get_display_clock_speed =
8078                         i830_get_display_clock_speed;
8079
8080         if (HAS_PCH_SPLIT(dev)) {
8081                 if (IS_GEN5(dev)) {
8082                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8083                         dev_priv->display.write_eld = ironlake_write_eld;
8084                 } else if (IS_GEN6(dev)) {
8085                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8086                         dev_priv->display.write_eld = ironlake_write_eld;
8087                 } else if (IS_IVYBRIDGE(dev)) {
8088                         /* FIXME: detect B0+ stepping and use auto training */
8089                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8090                         dev_priv->display.write_eld = ironlake_write_eld;
8091                 } else if (IS_HASWELL(dev)) {
8092                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8093                         dev_priv->display.write_eld = haswell_write_eld;
8094                 } else
8095                         dev_priv->display.update_wm = NULL;
8096         } else if (IS_G4X(dev)) {
8097                 dev_priv->display.write_eld = g4x_write_eld;
8098         }
8099
8100         /* Default just returns -ENODEV to indicate unsupported */
8101         dev_priv->display.queue_flip = intel_default_queue_flip;
8102
8103         switch (INTEL_INFO(dev)->gen) {
8104         case 2:
8105                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8106                 break;
8107
8108         case 3:
8109                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8110                 break;
8111
8112         case 4:
8113         case 5:
8114                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8115                 break;
8116
8117         case 6:
8118                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8119                 break;
8120         case 7:
8121                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8122                 break;
8123         }
8124 }
8125
8126 /*
8127  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8128  * resume, or other times.  This quirk makes sure that's the case for
8129  * affected systems.
8130  */
8131 static void quirk_pipea_force(struct drm_device *dev)
8132 {
8133         struct drm_i915_private *dev_priv = dev->dev_private;
8134
8135         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8136         DRM_INFO("applying pipe a force quirk\n");
8137 }
8138
8139 /*
8140  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8141  */
8142 static void quirk_ssc_force_disable(struct drm_device *dev)
8143 {
8144         struct drm_i915_private *dev_priv = dev->dev_private;
8145         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8146         DRM_INFO("applying lvds SSC disable quirk\n");
8147 }
8148
8149 /*
8150  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8151  * brightness value
8152  */
8153 static void quirk_invert_brightness(struct drm_device *dev)
8154 {
8155         struct drm_i915_private *dev_priv = dev->dev_private;
8156         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8157         DRM_INFO("applying inverted panel brightness quirk\n");
8158 }
8159
8160 struct intel_quirk {
8161         int device;
8162         int subsystem_vendor;
8163         int subsystem_device;
8164         void (*hook)(struct drm_device *dev);
8165 };
8166
8167 static struct intel_quirk intel_quirks[] = {
8168         /* HP Mini needs pipe A force quirk (LP: #322104) */
8169         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8170
8171         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8172         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8173
8174         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8175         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8176
8177         /* 855 & before need to leave pipe A & dpll A up */
8178         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8179         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8180         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8181
8182         /* Lenovo U160 cannot use SSC on LVDS */
8183         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8184
8185         /* Sony Vaio Y cannot use SSC on LVDS */
8186         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8187
8188         /* Acer Aspire 5734Z must invert backlight brightness */
8189         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8190 };
8191
8192 static void intel_init_quirks(struct drm_device *dev)
8193 {
8194         struct pci_dev *d = dev->pdev;
8195         int i;
8196
8197         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8198                 struct intel_quirk *q = &intel_quirks[i];
8199
8200                 if (d->device == q->device &&
8201                     (d->subsystem_vendor == q->subsystem_vendor ||
8202                      q->subsystem_vendor == PCI_ANY_ID) &&
8203                     (d->subsystem_device == q->subsystem_device ||
8204                      q->subsystem_device == PCI_ANY_ID))
8205                         q->hook(dev);
8206         }
8207 }
8208
8209 /* Disable the VGA plane that we never use */
8210 static void i915_disable_vga(struct drm_device *dev)
8211 {
8212         struct drm_i915_private *dev_priv = dev->dev_private;
8213         u8 sr1;
8214         u32 vga_reg;
8215
8216         if (HAS_PCH_SPLIT(dev))
8217                 vga_reg = CPU_VGACNTRL;
8218         else
8219                 vga_reg = VGACNTRL;
8220
8221         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8222         outb(SR01, VGA_SR_INDEX);
8223         sr1 = inb(VGA_SR_DATA);
8224         outb(sr1 | 1<<5, VGA_SR_DATA);
8225         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8226         udelay(300);
8227
8228         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8229         POSTING_READ(vga_reg);
8230 }
8231
8232 void intel_modeset_init_hw(struct drm_device *dev)
8233 {
8234         /* We attempt to init the necessary power wells early in the initialization
8235          * time, so the subsystems that expect power to be enabled can work.
8236          */
8237         intel_init_power_wells(dev);
8238
8239         intel_prepare_ddi(dev);
8240
8241         intel_init_clock_gating(dev);
8242
8243         mutex_lock(&dev->struct_mutex);
8244         intel_enable_gt_powersave(dev);
8245         mutex_unlock(&dev->struct_mutex);
8246 }
8247
8248 void intel_modeset_init(struct drm_device *dev)
8249 {
8250         struct drm_i915_private *dev_priv = dev->dev_private;
8251         int i, ret;
8252
8253         drm_mode_config_init(dev);
8254
8255         dev->mode_config.min_width = 0;
8256         dev->mode_config.min_height = 0;
8257
8258         dev->mode_config.preferred_depth = 24;
8259         dev->mode_config.prefer_shadow = 1;
8260
8261         dev->mode_config.funcs = &intel_mode_funcs;
8262
8263         intel_init_quirks(dev);
8264
8265         intel_init_pm(dev);
8266
8267         intel_init_display(dev);
8268
8269         if (IS_GEN2(dev)) {
8270                 dev->mode_config.max_width = 2048;
8271                 dev->mode_config.max_height = 2048;
8272         } else if (IS_GEN3(dev)) {
8273                 dev->mode_config.max_width = 4096;
8274                 dev->mode_config.max_height = 4096;
8275         } else {
8276                 dev->mode_config.max_width = 8192;
8277                 dev->mode_config.max_height = 8192;
8278         }
8279         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8280
8281         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8282                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8283
8284         for (i = 0; i < dev_priv->num_pipe; i++) {
8285                 intel_crtc_init(dev, i);
8286                 ret = intel_plane_init(dev, i);
8287                 if (ret)
8288                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8289         }
8290
8291         intel_cpu_pll_init(dev);
8292         intel_pch_pll_init(dev);
8293
8294         /* Just disable it once at startup */
8295         i915_disable_vga(dev);
8296         intel_setup_outputs(dev);
8297 }
8298
8299 static void
8300 intel_connector_break_all_links(struct intel_connector *connector)
8301 {
8302         connector->base.dpms = DRM_MODE_DPMS_OFF;
8303         connector->base.encoder = NULL;
8304         connector->encoder->connectors_active = false;
8305         connector->encoder->base.crtc = NULL;
8306 }
8307
8308 static void intel_enable_pipe_a(struct drm_device *dev)
8309 {
8310         struct intel_connector *connector;
8311         struct drm_connector *crt = NULL;
8312         struct intel_load_detect_pipe load_detect_temp;
8313
8314         /* We can't just switch on the pipe A, we need to set things up with a
8315          * proper mode and output configuration. As a gross hack, enable pipe A
8316          * by enabling the load detect pipe once. */
8317         list_for_each_entry(connector,
8318                             &dev->mode_config.connector_list,
8319                             base.head) {
8320                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8321                         crt = &connector->base;
8322                         break;
8323                 }
8324         }
8325
8326         if (!crt)
8327                 return;
8328
8329         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8330                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8331
8332
8333 }
8334
8335 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8336 {
8337         struct drm_device *dev = crtc->base.dev;
8338         struct drm_i915_private *dev_priv = dev->dev_private;
8339         u32 reg, val;
8340
8341         /* Clear any frame start delays used for debugging left by the BIOS */
8342         reg = PIPECONF(crtc->pipe);
8343         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8344
8345         /* We need to sanitize the plane -> pipe mapping first because this will
8346          * disable the crtc (and hence change the state) if it is wrong. */
8347         if (!HAS_PCH_SPLIT(dev)) {
8348                 struct intel_connector *connector;
8349                 bool plane;
8350
8351                 reg = DSPCNTR(crtc->plane);
8352                 val = I915_READ(reg);
8353
8354                 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
8355                     (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8356                         goto ok;
8357
8358                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8359                               crtc->base.base.id);
8360
8361                 /* Pipe has the wrong plane attached and the plane is active.
8362                  * Temporarily change the plane mapping and disable everything
8363                  * ...  */
8364                 plane = crtc->plane;
8365                 crtc->plane = !plane;
8366                 dev_priv->display.crtc_disable(&crtc->base);
8367                 crtc->plane = plane;
8368
8369                 /* ... and break all links. */
8370                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8371                                     base.head) {
8372                         if (connector->encoder->base.crtc != &crtc->base)
8373                                 continue;
8374
8375                         intel_connector_break_all_links(connector);
8376                 }
8377
8378                 WARN_ON(crtc->active);
8379                 crtc->base.enabled = false;
8380         }
8381 ok:
8382
8383         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8384             crtc->pipe == PIPE_A && !crtc->active) {
8385                 /* BIOS forgot to enable pipe A, this mostly happens after
8386                  * resume. Force-enable the pipe to fix this, the update_dpms
8387                  * call below we restore the pipe to the right state, but leave
8388                  * the required bits on. */
8389                 intel_enable_pipe_a(dev);
8390         }
8391
8392         /* Adjust the state of the output pipe according to whether we
8393          * have active connectors/encoders. */
8394         intel_crtc_update_dpms(&crtc->base);
8395
8396         if (crtc->active != crtc->base.enabled) {
8397                 struct intel_encoder *encoder;
8398
8399                 /* This can happen either due to bugs in the get_hw_state
8400                  * functions or because the pipe is force-enabled due to the
8401                  * pipe A quirk. */
8402                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8403                               crtc->base.base.id,
8404                               crtc->base.enabled ? "enabled" : "disabled",
8405                               crtc->active ? "enabled" : "disabled");
8406
8407                 crtc->base.enabled = crtc->active;
8408
8409                 /* Because we only establish the connector -> encoder ->
8410                  * crtc links if something is active, this means the
8411                  * crtc is now deactivated. Break the links. connector
8412                  * -> encoder links are only establish when things are
8413                  *  actually up, hence no need to break them. */
8414                 WARN_ON(crtc->active);
8415
8416                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8417                         WARN_ON(encoder->connectors_active);
8418                         encoder->base.crtc = NULL;
8419                 }
8420         }
8421 }
8422
8423 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8424 {
8425         struct intel_connector *connector;
8426         struct drm_device *dev = encoder->base.dev;
8427
8428         /* We need to check both for a crtc link (meaning that the
8429          * encoder is active and trying to read from a pipe) and the
8430          * pipe itself being active. */
8431         bool has_active_crtc = encoder->base.crtc &&
8432                 to_intel_crtc(encoder->base.crtc)->active;
8433
8434         if (encoder->connectors_active && !has_active_crtc) {
8435                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8436                               encoder->base.base.id,
8437                               drm_get_encoder_name(&encoder->base));
8438
8439                 /* Connector is active, but has no active pipe. This is
8440                  * fallout from our resume register restoring. Disable
8441                  * the encoder manually again. */
8442                 if (encoder->base.crtc) {
8443                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8444                                       encoder->base.base.id,
8445                                       drm_get_encoder_name(&encoder->base));
8446                         encoder->disable(encoder);
8447                 }
8448
8449                 /* Inconsistent output/port/pipe state happens presumably due to
8450                  * a bug in one of the get_hw_state functions. Or someplace else
8451                  * in our code, like the register restore mess on resume. Clamp
8452                  * things to off as a safer default. */
8453                 list_for_each_entry(connector,
8454                                     &dev->mode_config.connector_list,
8455                                     base.head) {
8456                         if (connector->encoder != encoder)
8457                                 continue;
8458
8459                         intel_connector_break_all_links(connector);
8460                 }
8461         }
8462         /* Enabled encoders without active connectors will be fixed in
8463          * the crtc fixup. */
8464 }
8465
8466 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8467  * and i915 state tracking structures. */
8468 void intel_modeset_setup_hw_state(struct drm_device *dev)
8469 {
8470         struct drm_i915_private *dev_priv = dev->dev_private;
8471         enum pipe pipe;
8472         u32 tmp;
8473         struct intel_crtc *crtc;
8474         struct intel_encoder *encoder;
8475         struct intel_connector *connector;
8476
8477         for_each_pipe(pipe) {
8478                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8479
8480                 tmp = I915_READ(PIPECONF(pipe));
8481                 if (tmp & PIPECONF_ENABLE)
8482                         crtc->active = true;
8483                 else
8484                         crtc->active = false;
8485
8486                 crtc->base.enabled = crtc->active;
8487
8488                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8489                               crtc->base.base.id,
8490                               crtc->active ? "enabled" : "disabled");
8491         }
8492
8493         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8494                             base.head) {
8495                 pipe = 0;
8496
8497                 if (encoder->get_hw_state(encoder, &pipe)) {
8498                         encoder->base.crtc =
8499                                 dev_priv->pipe_to_crtc_mapping[pipe];
8500                 } else {
8501                         encoder->base.crtc = NULL;
8502                 }
8503
8504                 encoder->connectors_active = false;
8505                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8506                               encoder->base.base.id,
8507                               drm_get_encoder_name(&encoder->base),
8508                               encoder->base.crtc ? "enabled" : "disabled",
8509                               pipe);
8510         }
8511
8512         list_for_each_entry(connector, &dev->mode_config.connector_list,
8513                             base.head) {
8514                 if (connector->get_hw_state(connector)) {
8515                         connector->base.dpms = DRM_MODE_DPMS_ON;
8516                         connector->encoder->connectors_active = true;
8517                         connector->base.encoder = &connector->encoder->base;
8518                 } else {
8519                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8520                         connector->base.encoder = NULL;
8521                 }
8522                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8523                               connector->base.base.id,
8524                               drm_get_connector_name(&connector->base),
8525                               connector->base.encoder ? "enabled" : "disabled");
8526         }
8527
8528         /* HW state is read out, now we need to sanitize this mess. */
8529         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8530                             base.head) {
8531                 intel_sanitize_encoder(encoder);
8532         }
8533
8534         for_each_pipe(pipe) {
8535                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8536                 intel_sanitize_crtc(crtc);
8537         }
8538
8539         intel_modeset_update_staged_output_state(dev);
8540
8541         intel_modeset_check_state(dev);
8542 }
8543
8544 void intel_modeset_gem_init(struct drm_device *dev)
8545 {
8546         intel_modeset_init_hw(dev);
8547
8548         intel_setup_overlay(dev);
8549
8550         intel_modeset_setup_hw_state(dev);
8551 }
8552
8553 void intel_modeset_cleanup(struct drm_device *dev)
8554 {
8555         struct drm_i915_private *dev_priv = dev->dev_private;
8556         struct drm_crtc *crtc;
8557         struct intel_crtc *intel_crtc;
8558
8559         drm_kms_helper_poll_fini(dev);
8560         mutex_lock(&dev->struct_mutex);
8561
8562         intel_unregister_dsm_handler();
8563
8564
8565         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8566                 /* Skip inactive CRTCs */
8567                 if (!crtc->fb)
8568                         continue;
8569
8570                 intel_crtc = to_intel_crtc(crtc);
8571                 intel_increase_pllclock(crtc);
8572         }
8573
8574         intel_disable_fbc(dev);
8575
8576         intel_disable_gt_powersave(dev);
8577
8578         ironlake_teardown_rc6(dev);
8579
8580         if (IS_VALLEYVIEW(dev))
8581                 vlv_init_dpio(dev);
8582
8583         mutex_unlock(&dev->struct_mutex);
8584
8585         /* Disable the irq before mode object teardown, for the irq might
8586          * enqueue unpin/hotplug work. */
8587         drm_irq_uninstall(dev);
8588         cancel_work_sync(&dev_priv->hotplug_work);
8589         cancel_work_sync(&dev_priv->rps.work);
8590
8591         /* flush any delayed tasks or pending work */
8592         flush_scheduled_work();
8593
8594         drm_mode_config_cleanup(dev);
8595 }
8596
8597 /*
8598  * Return which encoder is currently attached for connector.
8599  */
8600 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8601 {
8602         return &intel_attached_encoder(connector)->base;
8603 }
8604
8605 void intel_connector_attach_encoder(struct intel_connector *connector,
8606                                     struct intel_encoder *encoder)
8607 {
8608         connector->encoder = encoder;
8609         drm_mode_connector_attach_encoder(&connector->base,
8610                                           &encoder->base);
8611 }
8612
8613 /*
8614  * set vga decode state - true == enable VGA decode
8615  */
8616 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8617 {
8618         struct drm_i915_private *dev_priv = dev->dev_private;
8619         u16 gmch_ctrl;
8620
8621         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8622         if (state)
8623                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8624         else
8625                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8626         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8627         return 0;
8628 }
8629
8630 #ifdef CONFIG_DEBUG_FS
8631 #include <linux/seq_file.h>
8632
8633 struct intel_display_error_state {
8634         struct intel_cursor_error_state {
8635                 u32 control;
8636                 u32 position;
8637                 u32 base;
8638                 u32 size;
8639         } cursor[I915_MAX_PIPES];
8640
8641         struct intel_pipe_error_state {
8642                 u32 conf;
8643                 u32 source;
8644
8645                 u32 htotal;
8646                 u32 hblank;
8647                 u32 hsync;
8648                 u32 vtotal;
8649                 u32 vblank;
8650                 u32 vsync;
8651         } pipe[I915_MAX_PIPES];
8652
8653         struct intel_plane_error_state {
8654                 u32 control;
8655                 u32 stride;
8656                 u32 size;
8657                 u32 pos;
8658                 u32 addr;
8659                 u32 surface;
8660                 u32 tile_offset;
8661         } plane[I915_MAX_PIPES];
8662 };
8663
8664 struct intel_display_error_state *
8665 intel_display_capture_error_state(struct drm_device *dev)
8666 {
8667         drm_i915_private_t *dev_priv = dev->dev_private;
8668         struct intel_display_error_state *error;
8669         int i;
8670
8671         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8672         if (error == NULL)
8673                 return NULL;
8674
8675         for_each_pipe(i) {
8676                 error->cursor[i].control = I915_READ(CURCNTR(i));
8677                 error->cursor[i].position = I915_READ(CURPOS(i));
8678                 error->cursor[i].base = I915_READ(CURBASE(i));
8679
8680                 error->plane[i].control = I915_READ(DSPCNTR(i));
8681                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8682                 error->plane[i].size = I915_READ(DSPSIZE(i));
8683                 error->plane[i].pos = I915_READ(DSPPOS(i));
8684                 error->plane[i].addr = I915_READ(DSPADDR(i));
8685                 if (INTEL_INFO(dev)->gen >= 4) {
8686                         error->plane[i].surface = I915_READ(DSPSURF(i));
8687                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8688                 }
8689
8690                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8691                 error->pipe[i].source = I915_READ(PIPESRC(i));
8692                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8693                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8694                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8695                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8696                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8697                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8698         }
8699
8700         return error;
8701 }
8702
8703 void
8704 intel_display_print_error_state(struct seq_file *m,
8705                                 struct drm_device *dev,
8706                                 struct intel_display_error_state *error)
8707 {
8708         drm_i915_private_t *dev_priv = dev->dev_private;
8709         int i;
8710
8711         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8712         for_each_pipe(i) {
8713                 seq_printf(m, "Pipe [%d]:\n", i);
8714                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8715                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8716                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8717                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8718                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8719                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8720                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8721                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8722
8723                 seq_printf(m, "Plane [%d]:\n", i);
8724                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8725                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8726                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8727                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8728                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8729                 if (INTEL_INFO(dev)->gen >= 4) {
8730                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8731                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8732                 }
8733
8734                 seq_printf(m, "Cursor [%d]:\n", i);
8735                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8736                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8737                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8738         }
8739 }
8740 #endif