2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device *dev)
100 struct drm_i915_private *dev_priv = dev->dev_private;
102 WARN_ON(!HAS_PCH_SPLIT(dev));
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
239 .find_pll = intel_g4x_find_best_PLL,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
254 .find_pll = intel_g4x_find_best_PLL,
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
407 .vco = { .min = 4000000, .max = 5994000},
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA);
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device *dev)
473 struct drm_i915_private *dev_priv = dev->dev_private;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 /* LVDS dual channel */
491 if (refclk == 100000)
492 limit = &intel_limits_ironlake_dual_lvds_100m;
494 limit = &intel_limits_ironlake_dual_lvds;
496 if (refclk == 100000)
497 limit = &intel_limits_ironlake_single_lvds_100m;
499 limit = &intel_limits_ironlake_single_lvds;
501 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
502 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
503 limit = &intel_limits_ironlake_display_port;
505 limit = &intel_limits_ironlake_dac;
510 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
512 struct drm_device *dev = crtc->dev;
513 const intel_limit_t *limit;
515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
516 if (intel_is_dual_link_lvds(dev))
517 /* LVDS with dual channel */
518 limit = &intel_limits_g4x_dual_channel_lvds;
520 /* LVDS with dual channel */
521 limit = &intel_limits_g4x_single_channel_lvds;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
523 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
524 limit = &intel_limits_g4x_hdmi;
525 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
526 limit = &intel_limits_g4x_sdvo;
527 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
528 limit = &intel_limits_g4x_display_port;
529 } else /* The option is for other outputs */
530 limit = &intel_limits_i9xx_sdvo;
535 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
537 struct drm_device *dev = crtc->dev;
538 const intel_limit_t *limit;
540 if (HAS_PCH_SPLIT(dev))
541 limit = intel_ironlake_limit(crtc, refclk);
542 else if (IS_G4X(dev)) {
543 limit = intel_g4x_limit(crtc);
544 } else if (IS_PINEVIEW(dev)) {
545 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
546 limit = &intel_limits_pineview_lvds;
548 limit = &intel_limits_pineview_sdvo;
549 } else if (IS_VALLEYVIEW(dev)) {
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
551 limit = &intel_limits_vlv_dac;
552 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
553 limit = &intel_limits_vlv_hdmi;
555 limit = &intel_limits_vlv_dp;
556 } else if (!IS_GEN2(dev)) {
557 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
558 limit = &intel_limits_i9xx_lvds;
560 limit = &intel_limits_i9xx_sdvo;
562 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
563 limit = &intel_limits_i8xx_lvds;
565 limit = &intel_limits_i8xx_dvo;
570 /* m1 is reserved as 0 in Pineview, n is a ring counter */
571 static void pineview_clock(int refclk, intel_clock_t *clock)
573 clock->m = clock->m2 + 2;
574 clock->p = clock->p1 * clock->p2;
575 clock->vco = refclk * clock->m / clock->n;
576 clock->dot = clock->vco / clock->p;
579 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
581 if (IS_PINEVIEW(dev)) {
582 pineview_clock(refclk, clock);
585 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
586 clock->p = clock->p1 * clock->p2;
587 clock->vco = refclk * clock->m / (clock->n + 2);
588 clock->dot = clock->vco / clock->p;
592 * Returns whether any output on the specified pipe is of the specified type
594 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
596 struct drm_device *dev = crtc->dev;
597 struct intel_encoder *encoder;
599 for_each_encoder_on_crtc(dev, crtc, encoder)
600 if (encoder->type == type)
606 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
608 * Returns whether the given set of divisors are valid for a given refclk with
609 * the given connectors.
612 static bool intel_PLL_is_valid(struct drm_device *dev,
613 const intel_limit_t *limit,
614 const intel_clock_t *clock)
616 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
617 INTELPllInvalid("p1 out of range\n");
618 if (clock->p < limit->p.min || limit->p.max < clock->p)
619 INTELPllInvalid("p out of range\n");
620 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
621 INTELPllInvalid("m2 out of range\n");
622 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
623 INTELPllInvalid("m1 out of range\n");
624 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
625 INTELPllInvalid("m1 <= m2\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 if (clock->n < limit->n.min || limit->n.max < clock->n)
629 INTELPllInvalid("n out of range\n");
630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
636 INTELPllInvalid("dot out of range\n");
642 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *match_clock,
644 intel_clock_t *best_clock)
647 struct drm_device *dev = crtc->dev;
651 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 * For LVDS just rely on its current settings for dual-channel.
654 * We haven't figured out how to reliably set up different
655 * single/dual channel state, if we even can.
657 if (intel_is_dual_link_lvds(dev))
658 clock.p2 = limit->p2.p2_fast;
660 clock.p2 = limit->p2.p2_slow;
662 if (target < limit->p2.dot_limit)
663 clock.p2 = limit->p2.p2_slow;
665 clock.p2 = limit->p2.p2_fast;
668 memset(best_clock, 0, sizeof(*best_clock));
670 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 for (clock.m2 = limit->m2.min;
673 clock.m2 <= limit->m2.max; clock.m2++) {
674 /* m1 is always 0 in Pineview */
675 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
683 intel_clock(dev, refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
688 clock.p != match_clock->p)
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
701 return (err != target);
705 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
706 int target, int refclk, intel_clock_t *match_clock,
707 intel_clock_t *best_clock)
709 struct drm_device *dev = crtc->dev;
713 /* approximately equals target * 0.00585 */
714 int err_most = (target >> 8) + (target >> 9);
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
720 if (HAS_PCH_SPLIT(dev))
724 if (intel_is_dual_link_lvds(dev))
725 clock.p2 = limit->p2.p2_fast;
727 clock.p2 = limit->p2.p2_slow;
729 if (target < limit->p2.dot_limit)
730 clock.p2 = limit->p2.p2_slow;
732 clock.p2 = limit->p2.p2_fast;
735 memset(best_clock, 0, sizeof(*best_clock));
736 max_n = limit->n.max;
737 /* based on hardware requirement, prefer smaller n to precision */
738 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
739 /* based on hardware requirement, prefere larger m1,m2 */
740 for (clock.m1 = limit->m1.max;
741 clock.m1 >= limit->m1.min; clock.m1--) {
742 for (clock.m2 = limit->m2.max;
743 clock.m2 >= limit->m2.min; clock.m2--) {
744 for (clock.p1 = limit->p1.max;
745 clock.p1 >= limit->p1.min; clock.p1--) {
748 intel_clock(dev, refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err_most) {
771 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
775 struct drm_device *dev = crtc->dev;
778 if (target < 200000) {
791 intel_clock(dev, refclk, &clock);
792 memcpy(best_clock, &clock, sizeof(intel_clock_t));
796 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
798 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
799 int target, int refclk, intel_clock_t *match_clock,
800 intel_clock_t *best_clock)
803 if (target < 200000) {
816 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
817 clock.p = (clock.p1 * clock.p2);
818 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
820 memcpy(best_clock, &clock, sizeof(intel_clock_t));
824 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
825 int target, int refclk, intel_clock_t *match_clock,
826 intel_clock_t *best_clock)
828 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
830 u32 updrate, minupdate, fracbits, p;
831 unsigned long bestppm, ppm, absppm;
835 dotclk = target * 1000;
838 fastclk = dotclk / (2*100);
842 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
843 bestm1 = bestm2 = bestp1 = bestp2 = 0;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
847 updrate = refclk / n;
848 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
849 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
853 /* based on hardware requirement, prefer bigger m1,m2 values */
854 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
855 m2 = (((2*(fastclk * p * n / m1 )) +
856 refclk) / (2*refclk));
859 if (vco >= limit->vco.min && vco < limit->vco.max) {
860 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
861 absppm = (ppm > 0) ? ppm : (-ppm);
862 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
866 if (absppm < bestppm - 10) {
883 best_clock->n = bestn;
884 best_clock->m1 = bestm1;
885 best_clock->m2 = bestm2;
886 best_clock->p1 = bestp1;
887 best_clock->p2 = bestp2;
892 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
895 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
898 return intel_crtc->cpu_transcoder;
901 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
903 struct drm_i915_private *dev_priv = dev->dev_private;
904 u32 frame, frame_reg = PIPEFRAME(pipe);
906 frame = I915_READ(frame_reg);
908 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
909 DRM_DEBUG_KMS("vblank wait timed out\n");
913 * intel_wait_for_vblank - wait for vblank on a given pipe
915 * @pipe: pipe to wait for
917 * Wait for vblank to occur on a given pipe. Needed for various bits of
920 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 int pipestat_reg = PIPESTAT(pipe);
925 if (INTEL_INFO(dev)->gen >= 5) {
926 ironlake_wait_for_vblank(dev, pipe);
930 /* Clear existing vblank status. Note this will clear any other
931 * sticky status fields as well.
933 * This races with i915_driver_irq_handler() with the result
934 * that either function could miss a vblank event. Here it is not
935 * fatal, as we will either wait upon the next vblank interrupt or
936 * timeout. Generally speaking intel_wait_for_vblank() is only
937 * called during modeset at which time the GPU should be idle and
938 * should *not* be performing page flips and thus not waiting on
940 * Currently, the result of us stealing a vblank from the irq
941 * handler is that a single frame will be skipped during swapbuffers.
943 I915_WRITE(pipestat_reg,
944 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
946 /* Wait for vblank interrupt bit to set */
947 if (wait_for(I915_READ(pipestat_reg) &
948 PIPE_VBLANK_INTERRUPT_STATUS,
950 DRM_DEBUG_KMS("vblank wait timed out\n");
954 * intel_wait_for_pipe_off - wait for pipe to turn off
956 * @pipe: pipe to wait for
958 * After disabling a pipe, we can't wait for vblank in the usual way,
959 * spinning on the vblank interrupt status bit, since we won't actually
960 * see an interrupt when the pipe is disabled.
963 * wait for the pipe register state bit to turn off
966 * wait for the display line value to settle (it usually
967 * ends up stopping at the start of the next frame).
970 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
972 struct drm_i915_private *dev_priv = dev->dev_private;
973 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
976 if (INTEL_INFO(dev)->gen >= 4) {
977 int reg = PIPECONF(cpu_transcoder);
979 /* Wait for the Pipe State to go off */
980 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
982 WARN(1, "pipe_off wait timed out\n");
984 u32 last_line, line_mask;
985 int reg = PIPEDSL(pipe);
986 unsigned long timeout = jiffies + msecs_to_jiffies(100);
989 line_mask = DSL_LINEMASK_GEN2;
991 line_mask = DSL_LINEMASK_GEN3;
993 /* Wait for the display line to settle */
995 last_line = I915_READ(reg) & line_mask;
997 } while (((I915_READ(reg) & line_mask) != last_line) &&
998 time_after(timeout, jiffies));
999 if (time_after(jiffies, timeout))
1000 WARN(1, "pipe_off wait timed out\n");
1005 * ibx_digital_port_connected - is the specified port connected?
1006 * @dev_priv: i915 private structure
1007 * @port: the port to test
1009 * Returns true if @port is connected, false otherwise.
1011 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1012 struct intel_digital_port *port)
1016 if (HAS_PCH_IBX(dev_priv->dev)) {
1017 switch(port->port) {
1019 bit = SDE_PORTB_HOTPLUG;
1022 bit = SDE_PORTC_HOTPLUG;
1025 bit = SDE_PORTD_HOTPLUG;
1031 switch(port->port) {
1033 bit = SDE_PORTB_HOTPLUG_CPT;
1036 bit = SDE_PORTC_HOTPLUG_CPT;
1039 bit = SDE_PORTD_HOTPLUG_CPT;
1046 return I915_READ(SDEISR) & bit;
1049 static const char *state_string(bool enabled)
1051 return enabled ? "on" : "off";
1054 /* Only for pre-ILK configs */
1055 static void assert_pll(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
1063 val = I915_READ(reg);
1064 cur_state = !!(val & DPLL_VCO_ENABLE);
1065 WARN(cur_state != state,
1066 "PLL state assertion failure (expected %s, current %s)\n",
1067 state_string(state), state_string(cur_state));
1069 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1070 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1073 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1074 struct intel_pch_pll *pll,
1075 struct intel_crtc *crtc,
1081 if (HAS_PCH_LPT(dev_priv->dev)) {
1082 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1087 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1090 val = I915_READ(pll->pll_reg);
1091 cur_state = !!(val & DPLL_VCO_ENABLE);
1092 WARN(cur_state != state,
1093 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1094 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096 /* Make sure the selected PLL is correctly attached to the transcoder */
1097 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1100 pch_dpll = I915_READ(PCH_DPLL_SEL);
1101 cur_state = pll->pll_reg == _PCH_DPLL_B;
1102 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1103 "PLL[%d] not attached to this transcoder %d: %08x\n",
1104 cur_state, crtc->pipe, pch_dpll)) {
1105 cur_state = !!(val >> (4*crtc->pipe + 3));
1106 WARN(cur_state != state,
1107 "PLL[%d] not %s on this transcoder %d: %08x\n",
1108 pll->pll_reg == _PCH_DPLL_B,
1109 state_string(state),
1115 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1116 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1167 /* ILK FDI PLL is always enabled */
1168 if (dev_priv->info->gen == 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1186 reg = FDI_RX_CTL(pipe);
1187 val = I915_READ(reg);
1188 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1191 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 int pp_reg, lvds_reg;
1196 enum pipe panel_pipe = PIPE_A;
1199 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1200 pp_reg = PCH_PP_CONTROL;
1201 lvds_reg = PCH_LVDS;
1203 pp_reg = PP_CONTROL;
1207 val = I915_READ(pp_reg);
1208 if (!(val & PANEL_POWER_ON) ||
1209 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1213 panel_pipe = PIPE_B;
1215 WARN(panel_pipe == pipe && locked,
1216 "panel assertion failure, pipe %c regs locked\n",
1220 void assert_pipe(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, bool state)
1226 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1229 /* if we need the pipe A quirk it must be always on */
1230 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1233 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1234 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1242 WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 /* Planes are fixed to pipes on ILK+ */
1273 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1274 reg = DSPCNTR(pipe);
1275 val = I915_READ(reg);
1276 WARN((val & DISPLAY_PLANE_ENABLE),
1277 "plane %c assertion failure, should be disabled but not\n",
1282 /* Need to check both planes against the pipe */
1283 for (i = 0; i < 2; i++) {
1285 val = I915_READ(reg);
1286 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287 DISPPLANE_SEL_PIPE_SHIFT;
1288 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i), pipe_name(pipe));
1294 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1299 if (HAS_PCH_LPT(dev_priv->dev)) {
1300 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1304 val = I915_READ(PCH_DREF_CONTROL);
1305 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1306 DREF_SUPERSPREAD_SOURCE_MASK));
1307 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1310 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 reg = TRANSCONF(pipe);
1318 val = I915_READ(reg);
1319 enabled = !!(val & TRANS_ENABLE);
1321 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1325 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1326 enum pipe pipe, u32 port_sel, u32 val)
1328 if ((val & DP_PORT_EN) == 0)
1331 if (HAS_PCH_CPT(dev_priv->dev)) {
1332 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1333 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1334 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1337 if ((val & DP_PIPE_MASK) != (pipe << 30))
1343 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1346 if ((val & PORT_ENABLE) == 0)
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1353 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1359 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1362 if ((val & LVDS_PORT_EN) == 0)
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
1366 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1375 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1378 if ((val & ADPA_DAC_ENABLE) == 0)
1380 if (HAS_PCH_CPT(dev_priv->dev)) {
1381 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1390 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, int reg, u32 port_sel)
1393 u32 val = I915_READ(reg);
1394 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1395 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1396 reg, pipe_name(pipe));
1398 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1399 && (val & DP_PIPEB_SELECT),
1400 "IBX PCH dp port still using transcoder B\n");
1403 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, int reg)
1406 u32 val = I915_READ(reg);
1407 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1408 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1409 reg, pipe_name(pipe));
1411 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1412 && (val & SDVO_PIPE_B_SELECT),
1413 "IBX PCH hdmi port still using transcoder B\n");
1416 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1422 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1423 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1424 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1427 val = I915_READ(reg);
1428 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1429 "PCH VGA enabled on transcoder %c, should be disabled\n",
1433 val = I915_READ(reg);
1434 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1435 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1438 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1439 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1440 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1444 * intel_enable_pll - enable a PLL
1445 * @dev_priv: i915 private structure
1446 * @pipe: pipe PLL to enable
1448 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1449 * make sure the PLL reg is writable first though, since the panel write
1450 * protect mechanism may be enabled.
1452 * Note! This is for pre-ILK only.
1454 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1456 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1461 /* No really, not for ILK+ */
1462 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1464 /* PLL is protected by panel, make sure we can write it */
1465 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1466 assert_panel_unlocked(dev_priv, pipe);
1469 val = I915_READ(reg);
1470 val |= DPLL_VCO_ENABLE;
1472 /* We do this three times for luck */
1473 I915_WRITE(reg, val);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, val);
1478 udelay(150); /* wait for warmup */
1479 I915_WRITE(reg, val);
1481 udelay(150); /* wait for warmup */
1485 * intel_disable_pll - disable a PLL
1486 * @dev_priv: i915 private structure
1487 * @pipe: pipe PLL to disable
1489 * Disable the PLL for @pipe, making sure the pipe is off first.
1491 * Note! This is for pre-ILK only.
1493 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1498 /* Don't disable pipe A or pipe A PLLs if needed */
1499 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1502 /* Make sure the pipe isn't still relying on us */
1503 assert_pipe_disabled(dev_priv, pipe);
1506 val = I915_READ(reg);
1507 val &= ~DPLL_VCO_ENABLE;
1508 I915_WRITE(reg, val);
1514 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1515 enum intel_sbi_destination destination)
1519 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1521 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1523 DRM_ERROR("timeout waiting for SBI to become ready\n");
1527 I915_WRITE(SBI_ADDR, (reg << 16));
1528 I915_WRITE(SBI_DATA, value);
1530 if (destination == SBI_ICLK)
1531 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1533 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1534 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1536 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1538 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1544 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1545 enum intel_sbi_destination destination)
1548 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1550 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1552 DRM_ERROR("timeout waiting for SBI to become ready\n");
1556 I915_WRITE(SBI_ADDR, (reg << 16));
1558 if (destination == SBI_ICLK)
1559 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1561 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1562 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1564 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1566 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1570 return I915_READ(SBI_DATA);
1574 * ironlake_enable_pch_pll - enable PCH PLL
1575 * @dev_priv: i915 private structure
1576 * @pipe: pipe PLL to enable
1578 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1579 * drives the transcoder clock.
1581 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1583 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1584 struct intel_pch_pll *pll;
1588 /* PCH PLLs only available on ILK, SNB and IVB */
1589 BUG_ON(dev_priv->info->gen < 5);
1590 pll = intel_crtc->pch_pll;
1594 if (WARN_ON(pll->refcount == 0))
1597 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1598 pll->pll_reg, pll->active, pll->on,
1599 intel_crtc->base.base.id);
1601 /* PCH refclock must be enabled first */
1602 assert_pch_refclk_enabled(dev_priv);
1604 if (pll->active++ && pll->on) {
1605 assert_pch_pll_enabled(dev_priv, pll, NULL);
1609 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1612 val = I915_READ(reg);
1613 val |= DPLL_VCO_ENABLE;
1614 I915_WRITE(reg, val);
1621 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1623 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1624 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1628 /* PCH only available on ILK+ */
1629 BUG_ON(dev_priv->info->gen < 5);
1633 if (WARN_ON(pll->refcount == 0))
1636 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1637 pll->pll_reg, pll->active, pll->on,
1638 intel_crtc->base.base.id);
1640 if (WARN_ON(pll->active == 0)) {
1641 assert_pch_pll_disabled(dev_priv, pll, NULL);
1645 if (--pll->active) {
1646 assert_pch_pll_enabled(dev_priv, pll, NULL);
1650 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1652 /* Make sure transcoder isn't still depending on us */
1653 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1656 val = I915_READ(reg);
1657 val &= ~DPLL_VCO_ENABLE;
1658 I915_WRITE(reg, val);
1665 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 struct drm_device *dev = dev_priv->dev;
1669 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1670 uint32_t reg, val, pipeconf_val;
1672 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv->info->gen < 5);
1675 /* Make sure PCH DPLL is enabled */
1676 assert_pch_pll_enabled(dev_priv,
1677 to_intel_crtc(crtc)->pch_pll,
1678 to_intel_crtc(crtc));
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, pipe);
1682 assert_fdi_rx_enabled(dev_priv, pipe);
1684 if (HAS_PCH_CPT(dev)) {
1685 /* Workaround: Set the timing override bit before enabling the
1686 * pch transcoder. */
1687 reg = TRANS_CHICKEN2(pipe);
1688 val = I915_READ(reg);
1689 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1690 I915_WRITE(reg, val);
1693 reg = TRANSCONF(pipe);
1694 val = I915_READ(reg);
1695 pipeconf_val = I915_READ(PIPECONF(pipe));
1697 if (HAS_PCH_IBX(dev_priv->dev)) {
1699 * make the BPC in transcoder be consistent with
1700 * that in pipeconf reg.
1702 val &= ~PIPECONF_BPC_MASK;
1703 val |= pipeconf_val & PIPECONF_BPC_MASK;
1706 val &= ~TRANS_INTERLACE_MASK;
1707 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1708 if (HAS_PCH_IBX(dev_priv->dev) &&
1709 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1710 val |= TRANS_LEGACY_INTERLACED_ILK;
1712 val |= TRANS_INTERLACED;
1714 val |= TRANS_PROGRESSIVE;
1716 I915_WRITE(reg, val | TRANS_ENABLE);
1717 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1718 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1721 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1722 enum transcoder cpu_transcoder)
1724 u32 val, pipeconf_val;
1726 /* PCH only available on ILK+ */
1727 BUG_ON(dev_priv->info->gen < 5);
1729 /* FDI must be feeding us bits for PCH ports */
1730 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1731 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1733 /* Workaround: set timing override bit. */
1734 val = I915_READ(_TRANSA_CHICKEN2);
1735 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736 I915_WRITE(_TRANSA_CHICKEN2, val);
1739 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1741 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1742 PIPECONF_INTERLACED_ILK)
1743 val |= TRANS_INTERLACED;
1745 val |= TRANS_PROGRESSIVE;
1747 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1748 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1749 DRM_ERROR("Failed to enable PCH transcoder\n");
1752 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1755 struct drm_device *dev = dev_priv->dev;
1758 /* FDI relies on the transcoder */
1759 assert_fdi_tx_disabled(dev_priv, pipe);
1760 assert_fdi_rx_disabled(dev_priv, pipe);
1762 /* Ports must be off as well */
1763 assert_pch_ports_disabled(dev_priv, pipe);
1765 reg = TRANSCONF(pipe);
1766 val = I915_READ(reg);
1767 val &= ~TRANS_ENABLE;
1768 I915_WRITE(reg, val);
1769 /* wait for PCH transcoder off, transcoder state */
1770 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1771 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1773 if (!HAS_PCH_IBX(dev)) {
1774 /* Workaround: Clear the timing override chicken bit again. */
1775 reg = TRANS_CHICKEN2(pipe);
1776 val = I915_READ(reg);
1777 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1778 I915_WRITE(reg, val);
1782 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1786 val = I915_READ(_TRANSACONF);
1787 val &= ~TRANS_ENABLE;
1788 I915_WRITE(_TRANSACONF, val);
1789 /* wait for PCH transcoder off, transcoder state */
1790 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1791 DRM_ERROR("Failed to disable PCH transcoder\n");
1793 /* Workaround: clear timing override bit. */
1794 val = I915_READ(_TRANSA_CHICKEN2);
1795 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1796 I915_WRITE(_TRANSA_CHICKEN2, val);
1800 * intel_enable_pipe - enable a pipe, asserting requirements
1801 * @dev_priv: i915 private structure
1802 * @pipe: pipe to enable
1803 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1805 * Enable @pipe, making sure that various hardware specific requirements
1806 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1808 * @pipe should be %PIPE_A or %PIPE_B.
1810 * Will wait until the pipe is actually running (i.e. first vblank) before
1813 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1816 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 enum pipe pch_transcoder;
1822 if (HAS_PCH_LPT(dev_priv->dev))
1823 pch_transcoder = TRANSCODER_A;
1825 pch_transcoder = pipe;
1828 * A pipe without a PLL won't actually be able to drive bits from
1829 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1832 if (!HAS_PCH_SPLIT(dev_priv->dev))
1833 assert_pll_enabled(dev_priv, pipe);
1836 /* if driving the PCH, we need FDI enabled */
1837 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1838 assert_fdi_tx_pll_enabled(dev_priv,
1839 (enum pipe) cpu_transcoder);
1841 /* FIXME: assert CPU port conditions for SNB+ */
1844 reg = PIPECONF(cpu_transcoder);
1845 val = I915_READ(reg);
1846 if (val & PIPECONF_ENABLE)
1849 I915_WRITE(reg, val | PIPECONF_ENABLE);
1850 intel_wait_for_vblank(dev_priv->dev, pipe);
1854 * intel_disable_pipe - disable a pipe, asserting requirements
1855 * @dev_priv: i915 private structure
1856 * @pipe: pipe to disable
1858 * Disable @pipe, making sure that various hardware specific requirements
1859 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1861 * @pipe should be %PIPE_A or %PIPE_B.
1863 * Will wait until the pipe has shut down before returning.
1865 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1868 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1874 * Make sure planes won't keep trying to pump pixels to us,
1875 * or we might hang the display.
1877 assert_planes_disabled(dev_priv, pipe);
1879 /* Don't disable pipe A or pipe A PLLs if needed */
1880 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1883 reg = PIPECONF(cpu_transcoder);
1884 val = I915_READ(reg);
1885 if ((val & PIPECONF_ENABLE) == 0)
1888 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1893 * Plane regs are double buffered, going from enabled->disabled needs a
1894 * trigger in order to latch. The display address reg provides this.
1896 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1899 if (dev_priv->info->gen >= 4)
1900 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1902 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1906 * intel_enable_plane - enable a display plane on a given pipe
1907 * @dev_priv: i915 private structure
1908 * @plane: plane to enable
1909 * @pipe: pipe being fed
1911 * Enable @plane on @pipe, making sure that @pipe is running first.
1913 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914 enum plane plane, enum pipe pipe)
1919 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920 assert_pipe_enabled(dev_priv, pipe);
1922 reg = DSPCNTR(plane);
1923 val = I915_READ(reg);
1924 if (val & DISPLAY_PLANE_ENABLE)
1927 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928 intel_flush_display_plane(dev_priv, plane);
1929 intel_wait_for_vblank(dev_priv->dev, pipe);
1933 * intel_disable_plane - disable a display plane
1934 * @dev_priv: i915 private structure
1935 * @plane: plane to disable
1936 * @pipe: pipe consuming the data
1938 * Disable @plane; should be an independent operation.
1940 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941 enum plane plane, enum pipe pipe)
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
1948 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1951 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1957 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958 struct drm_i915_gem_object *obj,
1959 struct intel_ring_buffer *pipelined)
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1965 switch (obj->tiling_mode) {
1966 case I915_TILING_NONE:
1967 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968 alignment = 128 * 1024;
1969 else if (INTEL_INFO(dev)->gen >= 4)
1970 alignment = 4 * 1024;
1972 alignment = 64 * 1024;
1975 /* pin() will align the object as required by fence */
1979 /* FIXME: Is this true? */
1980 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1986 dev_priv->mm.interruptible = false;
1987 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1989 goto err_interruptible;
1991 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992 * fence, whereas 965+ only requires a fence if using
1993 * framebuffer compression. For simplicity, we always install
1994 * a fence as the cost is not that onerous.
1996 ret = i915_gem_object_get_fence(obj);
2000 i915_gem_object_pin_fence(obj);
2002 dev_priv->mm.interruptible = true;
2006 i915_gem_object_unpin(obj);
2008 dev_priv->mm.interruptible = true;
2012 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2014 i915_gem_object_unpin_fence(obj);
2015 i915_gem_object_unpin(obj);
2018 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019 * is assumed to be a power-of-two. */
2020 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2024 int tile_rows, tiles;
2028 tiles = *x / (512/bpp);
2031 return tile_rows * pitch * 8 + tiles * 4096;
2034 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2037 struct drm_device *dev = crtc->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040 struct intel_framebuffer *intel_fb;
2041 struct drm_i915_gem_object *obj;
2042 int plane = intel_crtc->plane;
2043 unsigned long linear_offset;
2052 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056 intel_fb = to_intel_framebuffer(fb);
2057 obj = intel_fb->obj;
2059 reg = DSPCNTR(plane);
2060 dspcntr = I915_READ(reg);
2061 /* Mask out pixel format bits in case we change it */
2062 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063 switch (fb->pixel_format) {
2065 dspcntr |= DISPPLANE_8BPP;
2067 case DRM_FORMAT_XRGB1555:
2068 case DRM_FORMAT_ARGB1555:
2069 dspcntr |= DISPPLANE_BGRX555;
2071 case DRM_FORMAT_RGB565:
2072 dspcntr |= DISPPLANE_BGRX565;
2074 case DRM_FORMAT_XRGB8888:
2075 case DRM_FORMAT_ARGB8888:
2076 dspcntr |= DISPPLANE_BGRX888;
2078 case DRM_FORMAT_XBGR8888:
2079 case DRM_FORMAT_ABGR8888:
2080 dspcntr |= DISPPLANE_RGBX888;
2082 case DRM_FORMAT_XRGB2101010:
2083 case DRM_FORMAT_ARGB2101010:
2084 dspcntr |= DISPPLANE_BGRX101010;
2086 case DRM_FORMAT_XBGR2101010:
2087 case DRM_FORMAT_ABGR2101010:
2088 dspcntr |= DISPPLANE_RGBX101010;
2091 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2095 if (INTEL_INFO(dev)->gen >= 4) {
2096 if (obj->tiling_mode != I915_TILING_NONE)
2097 dspcntr |= DISPPLANE_TILED;
2099 dspcntr &= ~DISPPLANE_TILED;
2102 I915_WRITE(reg, dspcntr);
2104 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2106 if (INTEL_INFO(dev)->gen >= 4) {
2107 intel_crtc->dspaddr_offset =
2108 intel_gen4_compute_offset_xtiled(&x, &y,
2109 fb->bits_per_pixel / 8,
2111 linear_offset -= intel_crtc->dspaddr_offset;
2113 intel_crtc->dspaddr_offset = linear_offset;
2116 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119 if (INTEL_INFO(dev)->gen >= 4) {
2120 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121 obj->gtt_offset + intel_crtc->dspaddr_offset);
2122 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123 I915_WRITE(DSPLINOFF(plane), linear_offset);
2125 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2131 static int ironlake_update_plane(struct drm_crtc *crtc,
2132 struct drm_framebuffer *fb, int x, int y)
2134 struct drm_device *dev = crtc->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137 struct intel_framebuffer *intel_fb;
2138 struct drm_i915_gem_object *obj;
2139 int plane = intel_crtc->plane;
2140 unsigned long linear_offset;
2150 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2154 intel_fb = to_intel_framebuffer(fb);
2155 obj = intel_fb->obj;
2157 reg = DSPCNTR(plane);
2158 dspcntr = I915_READ(reg);
2159 /* Mask out pixel format bits in case we change it */
2160 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161 switch (fb->pixel_format) {
2163 dspcntr |= DISPPLANE_8BPP;
2165 case DRM_FORMAT_RGB565:
2166 dspcntr |= DISPPLANE_BGRX565;
2168 case DRM_FORMAT_XRGB8888:
2169 case DRM_FORMAT_ARGB8888:
2170 dspcntr |= DISPPLANE_BGRX888;
2172 case DRM_FORMAT_XBGR8888:
2173 case DRM_FORMAT_ABGR8888:
2174 dspcntr |= DISPPLANE_RGBX888;
2176 case DRM_FORMAT_XRGB2101010:
2177 case DRM_FORMAT_ARGB2101010:
2178 dspcntr |= DISPPLANE_BGRX101010;
2180 case DRM_FORMAT_XBGR2101010:
2181 case DRM_FORMAT_ABGR2101010:
2182 dspcntr |= DISPPLANE_RGBX101010;
2185 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2189 if (obj->tiling_mode != I915_TILING_NONE)
2190 dspcntr |= DISPPLANE_TILED;
2192 dspcntr &= ~DISPPLANE_TILED;
2195 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2197 I915_WRITE(reg, dspcntr);
2199 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200 intel_crtc->dspaddr_offset =
2201 intel_gen4_compute_offset_xtiled(&x, &y,
2202 fb->bits_per_pixel / 8,
2204 linear_offset -= intel_crtc->dspaddr_offset;
2206 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209 I915_MODIFY_DISPBASE(DSPSURF(plane),
2210 obj->gtt_offset + intel_crtc->dspaddr_offset);
2211 if (IS_HASWELL(dev)) {
2212 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2214 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215 I915_WRITE(DSPLINOFF(plane), linear_offset);
2222 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2224 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225 int x, int y, enum mode_set_atomic state)
2227 struct drm_device *dev = crtc->dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2230 if (dev_priv->display.disable_fbc)
2231 dev_priv->display.disable_fbc(dev);
2232 intel_increase_pllclock(crtc);
2234 return dev_priv->display.update_plane(crtc, fb, x, y);
2237 void intel_display_handle_reset(struct drm_device *dev)
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 struct drm_crtc *crtc;
2243 * Flips in the rings have been nuked by the reset,
2244 * so complete all pending flips so that user space
2245 * will get its events and not get stuck.
2247 * Also update the base address of all primary
2248 * planes to the the last fb to make sure we're
2249 * showing the correct fb after a reset.
2251 * Need to make two loops over the crtcs so that we
2252 * don't try to grab a crtc mutex before the
2253 * pending_flip_queue really got woken up.
2256 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2258 enum plane plane = intel_crtc->plane;
2260 intel_prepare_page_flip(dev, plane);
2261 intel_finish_page_flip_plane(dev, plane);
2264 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2267 mutex_lock(&crtc->mutex);
2268 if (intel_crtc->active)
2269 dev_priv->display.update_plane(crtc, crtc->fb,
2271 mutex_unlock(&crtc->mutex);
2276 intel_finish_fb(struct drm_framebuffer *old_fb)
2278 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280 bool was_interruptible = dev_priv->mm.interruptible;
2283 /* Big Hammer, we also need to ensure that any pending
2284 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285 * current scanout is retired before unpinning the old
2288 * This should only fail upon a hung GPU, in which case we
2289 * can safely continue.
2291 dev_priv->mm.interruptible = false;
2292 ret = i915_gem_object_finish_gpu(obj);
2293 dev_priv->mm.interruptible = was_interruptible;
2298 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2300 struct drm_device *dev = crtc->dev;
2301 struct drm_i915_master_private *master_priv;
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 if (!dev->primary->master)
2307 master_priv = dev->primary->master->driver_priv;
2308 if (!master_priv->sarea_priv)
2311 switch (intel_crtc->pipe) {
2313 master_priv->sarea_priv->pipeA_x = x;
2314 master_priv->sarea_priv->pipeA_y = y;
2317 master_priv->sarea_priv->pipeB_x = x;
2318 master_priv->sarea_priv->pipeB_y = y;
2326 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2327 struct drm_framebuffer *fb)
2329 struct drm_device *dev = crtc->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332 struct drm_framebuffer *old_fb;
2337 DRM_ERROR("No FB bound\n");
2341 if(intel_crtc->plane > dev_priv->num_pipe) {
2342 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2344 dev_priv->num_pipe);
2348 mutex_lock(&dev->struct_mutex);
2349 ret = intel_pin_and_fence_fb_obj(dev,
2350 to_intel_framebuffer(fb)->obj,
2353 mutex_unlock(&dev->struct_mutex);
2354 DRM_ERROR("pin & fence failed\n");
2358 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2360 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2361 mutex_unlock(&dev->struct_mutex);
2362 DRM_ERROR("failed to update base address\n");
2372 intel_wait_for_vblank(dev, intel_crtc->pipe);
2373 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2376 intel_update_fbc(dev);
2377 mutex_unlock(&dev->struct_mutex);
2379 intel_crtc_update_sarea_pos(crtc, x, y);
2384 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2386 struct drm_device *dev = crtc->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2389 int pipe = intel_crtc->pipe;
2392 /* enable normal train */
2393 reg = FDI_TX_CTL(pipe);
2394 temp = I915_READ(reg);
2395 if (IS_IVYBRIDGE(dev)) {
2396 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2397 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2399 temp &= ~FDI_LINK_TRAIN_NONE;
2400 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2402 I915_WRITE(reg, temp);
2404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
2406 if (HAS_PCH_CPT(dev)) {
2407 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2408 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2410 temp &= ~FDI_LINK_TRAIN_NONE;
2411 temp |= FDI_LINK_TRAIN_NONE;
2413 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2415 /* wait one idle pattern time */
2419 /* IVB wants error correction enabled */
2420 if (IS_IVYBRIDGE(dev))
2421 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2422 FDI_FE_ERRC_ENABLE);
2425 static void ivb_modeset_global_resources(struct drm_device *dev)
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct intel_crtc *pipe_B_crtc =
2429 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2430 struct intel_crtc *pipe_C_crtc =
2431 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434 /* When everything is off disable fdi C so that we could enable fdi B
2435 * with all lanes. XXX: This misses the case where a pipe is not using
2436 * any pch resources and so doesn't need any fdi lanes. */
2437 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2438 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2439 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2441 temp = I915_READ(SOUTH_CHICKEN1);
2442 temp &= ~FDI_BC_BIFURCATION_SELECT;
2443 DRM_DEBUG_KMS("disabling fdi C rx\n");
2444 I915_WRITE(SOUTH_CHICKEN1, temp);
2448 /* The FDI link training functions for ILK/Ibexpeak. */
2449 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2451 struct drm_device *dev = crtc->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454 int pipe = intel_crtc->pipe;
2455 int plane = intel_crtc->plane;
2456 u32 reg, temp, tries;
2458 /* FDI needs bits from pipe & plane first */
2459 assert_pipe_enabled(dev_priv, pipe);
2460 assert_plane_enabled(dev_priv, plane);
2462 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2464 reg = FDI_RX_IMR(pipe);
2465 temp = I915_READ(reg);
2466 temp &= ~FDI_RX_SYMBOL_LOCK;
2467 temp &= ~FDI_RX_BIT_LOCK;
2468 I915_WRITE(reg, temp);
2472 /* enable CPU FDI TX and PCH FDI RX */
2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2476 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2477 temp &= ~FDI_LINK_TRAIN_NONE;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1;
2479 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481 reg = FDI_RX_CTL(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_LINK_TRAIN_NONE;
2484 temp |= FDI_LINK_TRAIN_PATTERN_1;
2485 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2490 /* Ironlake workaround, enable clock pointer after FDI enable*/
2491 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2492 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2493 FDI_RX_PHASE_SYNC_POINTER_EN);
2495 reg = FDI_RX_IIR(pipe);
2496 for (tries = 0; tries < 5; tries++) {
2497 temp = I915_READ(reg);
2498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2500 if ((temp & FDI_RX_BIT_LOCK)) {
2501 DRM_DEBUG_KMS("FDI train 1 done.\n");
2502 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2507 DRM_ERROR("FDI train 1 fail!\n");
2510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_LINK_TRAIN_NONE;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2;
2514 I915_WRITE(reg, temp);
2516 reg = FDI_RX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 I915_WRITE(reg, temp);
2525 reg = FDI_RX_IIR(pipe);
2526 for (tries = 0; tries < 5; tries++) {
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530 if (temp & FDI_RX_SYMBOL_LOCK) {
2531 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2532 DRM_DEBUG_KMS("FDI train 2 done.\n");
2537 DRM_ERROR("FDI train 2 fail!\n");
2539 DRM_DEBUG_KMS("FDI train done\n");
2543 static const int snb_b_fdi_train_param[] = {
2544 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2545 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2546 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2547 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2550 /* The FDI link training functions for SNB/Cougarpoint. */
2551 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2553 struct drm_device *dev = crtc->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556 int pipe = intel_crtc->pipe;
2557 u32 reg, temp, i, retry;
2559 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2561 reg = FDI_RX_IMR(pipe);
2562 temp = I915_READ(reg);
2563 temp &= ~FDI_RX_SYMBOL_LOCK;
2564 temp &= ~FDI_RX_BIT_LOCK;
2565 I915_WRITE(reg, temp);
2570 /* enable CPU FDI TX and PCH FDI RX */
2571 reg = FDI_TX_CTL(pipe);
2572 temp = I915_READ(reg);
2574 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1;
2577 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2580 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2582 I915_WRITE(FDI_RX_MISC(pipe),
2583 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599 for (i = 0; i < 4; i++) {
2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
2604 I915_WRITE(reg, temp);
2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_BIT_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2615 DRM_DEBUG_KMS("FDI train 1 done.\n");
2624 DRM_ERROR("FDI train 1 fail!\n");
2627 reg = FDI_TX_CTL(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_LINK_TRAIN_NONE;
2630 temp |= FDI_LINK_TRAIN_PATTERN_2;
2632 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2634 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2636 I915_WRITE(reg, temp);
2638 reg = FDI_RX_CTL(pipe);
2639 temp = I915_READ(reg);
2640 if (HAS_PCH_CPT(dev)) {
2641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2644 temp &= ~FDI_LINK_TRAIN_NONE;
2645 temp |= FDI_LINK_TRAIN_PATTERN_2;
2647 I915_WRITE(reg, temp);
2652 for (i = 0; i < 4; i++) {
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656 temp |= snb_b_fdi_train_param[i];
2657 I915_WRITE(reg, temp);
2662 for (retry = 0; retry < 5; retry++) {
2663 reg = FDI_RX_IIR(pipe);
2664 temp = I915_READ(reg);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666 if (temp & FDI_RX_SYMBOL_LOCK) {
2667 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2668 DRM_DEBUG_KMS("FDI train 2 done.\n");
2677 DRM_ERROR("FDI train 2 fail!\n");
2679 DRM_DEBUG_KMS("FDI train done.\n");
2682 /* Manual link training for Ivy Bridge A0 parts */
2683 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2685 struct drm_device *dev = crtc->dev;
2686 struct drm_i915_private *dev_priv = dev->dev_private;
2687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2688 int pipe = intel_crtc->pipe;
2691 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2693 reg = FDI_RX_IMR(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_RX_SYMBOL_LOCK;
2696 temp &= ~FDI_RX_BIT_LOCK;
2697 I915_WRITE(reg, temp);
2702 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2703 I915_READ(FDI_RX_IIR(pipe)));
2705 /* enable CPU FDI TX and PCH FDI RX */
2706 reg = FDI_TX_CTL(pipe);
2707 temp = I915_READ(reg);
2709 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2710 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2711 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2712 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2713 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2714 temp |= FDI_COMPOSITE_SYNC;
2715 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2717 I915_WRITE(FDI_RX_MISC(pipe),
2718 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2720 reg = FDI_RX_CTL(pipe);
2721 temp = I915_READ(reg);
2722 temp &= ~FDI_LINK_TRAIN_AUTO;
2723 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2724 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2725 temp |= FDI_COMPOSITE_SYNC;
2726 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2731 for (i = 0; i < 4; i++) {
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735 temp |= snb_b_fdi_train_param[i];
2736 I915_WRITE(reg, temp);
2741 reg = FDI_RX_IIR(pipe);
2742 temp = I915_READ(reg);
2743 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2745 if (temp & FDI_RX_BIT_LOCK ||
2746 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2747 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2748 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2753 DRM_ERROR("FDI train 1 fail!\n");
2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2759 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2760 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2761 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2762 I915_WRITE(reg, temp);
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2768 I915_WRITE(reg, temp);
2773 for (i = 0; i < 4; i++) {
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2777 temp |= snb_b_fdi_train_param[i];
2778 I915_WRITE(reg, temp);
2783 reg = FDI_RX_IIR(pipe);
2784 temp = I915_READ(reg);
2785 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787 if (temp & FDI_RX_SYMBOL_LOCK) {
2788 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2789 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2794 DRM_ERROR("FDI train 2 fail!\n");
2796 DRM_DEBUG_KMS("FDI train done.\n");
2799 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2801 struct drm_device *dev = intel_crtc->base.dev;
2802 struct drm_i915_private *dev_priv = dev->dev_private;
2803 int pipe = intel_crtc->pipe;
2807 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2808 reg = FDI_RX_CTL(pipe);
2809 temp = I915_READ(reg);
2810 temp &= ~((0x7 << 19) | (0x7 << 16));
2811 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2812 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2813 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2818 /* Switch from Rawclk to PCDclk */
2819 temp = I915_READ(reg);
2820 I915_WRITE(reg, temp | FDI_PCDCLK);
2825 /* Enable CPU FDI TX PLL, always on for Ironlake */
2826 reg = FDI_TX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2829 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2836 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2838 struct drm_device *dev = intel_crtc->base.dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 int pipe = intel_crtc->pipe;
2843 /* Switch from PCDclk to Rawclk */
2844 reg = FDI_RX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2848 /* Disable CPU FDI TX PLL */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2856 reg = FDI_RX_CTL(pipe);
2857 temp = I915_READ(reg);
2858 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2860 /* Wait for the clocks to turn off. */
2865 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870 int pipe = intel_crtc->pipe;
2873 /* disable CPU FDI tx and PCH FDI rx */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2879 reg = FDI_RX_CTL(pipe);
2880 temp = I915_READ(reg);
2881 temp &= ~(0x7 << 16);
2882 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2883 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2888 /* Ironlake workaround, disable clock pointer after downing FDI */
2889 if (HAS_PCH_IBX(dev)) {
2890 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2893 /* still set train pattern 1 */
2894 reg = FDI_TX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 temp &= ~FDI_LINK_TRAIN_NONE;
2897 temp |= FDI_LINK_TRAIN_PATTERN_1;
2898 I915_WRITE(reg, temp);
2900 reg = FDI_RX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 if (HAS_PCH_CPT(dev)) {
2903 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2904 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2906 temp &= ~FDI_LINK_TRAIN_NONE;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1;
2909 /* BPC in FDI rx is consistent with that in PIPECONF */
2910 temp &= ~(0x07 << 16);
2911 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2912 I915_WRITE(reg, temp);
2918 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2920 struct drm_device *dev = crtc->dev;
2921 struct drm_i915_private *dev_priv = dev->dev_private;
2922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2923 unsigned long flags;
2926 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2927 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2930 spin_lock_irqsave(&dev->event_lock, flags);
2931 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2932 spin_unlock_irqrestore(&dev->event_lock, flags);
2937 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2939 struct drm_device *dev = crtc->dev;
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2942 if (crtc->fb == NULL)
2945 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2947 wait_event(dev_priv->pending_flip_queue,
2948 !intel_crtc_has_pending_flip(crtc));
2950 mutex_lock(&dev->struct_mutex);
2951 intel_finish_fb(crtc->fb);
2952 mutex_unlock(&dev->struct_mutex);
2955 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2957 struct drm_device *dev = crtc->dev;
2958 struct intel_encoder *intel_encoder;
2961 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2962 * must be driven by its own crtc; no sharing is possible.
2964 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2965 switch (intel_encoder->type) {
2966 case INTEL_OUTPUT_EDP:
2967 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2976 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2978 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2981 /* Program iCLKIP clock to the desired frequency */
2982 static void lpt_program_iclkip(struct drm_crtc *crtc)
2984 struct drm_device *dev = crtc->dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2989 mutex_lock(&dev_priv->dpio_lock);
2991 /* It is necessary to ungate the pixclk gate prior to programming
2992 * the divisors, and gate it back when it is done.
2994 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2996 /* Disable SSCCTL */
2997 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2998 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3002 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3003 if (crtc->mode.clock == 20000) {
3008 /* The iCLK virtual clock root frequency is in MHz,
3009 * but the crtc->mode.clock in in KHz. To get the divisors,
3010 * it is necessary to divide one by another, so we
3011 * convert the virtual clock precision to KHz here for higher
3014 u32 iclk_virtual_root_freq = 172800 * 1000;
3015 u32 iclk_pi_range = 64;
3016 u32 desired_divisor, msb_divisor_value, pi_value;
3018 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3019 msb_divisor_value = desired_divisor / iclk_pi_range;
3020 pi_value = desired_divisor % iclk_pi_range;
3023 divsel = msb_divisor_value - 2;
3024 phaseinc = pi_value;
3027 /* This should not happen with any sane values */
3028 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3029 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3030 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3031 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3033 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3040 /* Program SSCDIVINTPHASE6 */
3041 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3042 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3043 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3044 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3045 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3046 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3047 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3048 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3050 /* Program SSCAUXDIV */
3051 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3052 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3053 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3054 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3056 /* Enable modulator and associated divider */
3057 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3058 temp &= ~SBI_SSCCTL_DISABLE;
3059 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3061 /* Wait for initialization time */
3064 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3066 mutex_unlock(&dev_priv->dpio_lock);
3070 * Enable PCH resources required for PCH ports:
3072 * - FDI training & RX/TX
3073 * - update transcoder timings
3074 * - DP transcoding bits
3077 static void ironlake_pch_enable(struct drm_crtc *crtc)
3079 struct drm_device *dev = crtc->dev;
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082 int pipe = intel_crtc->pipe;
3085 assert_transcoder_disabled(dev_priv, pipe);
3087 /* Write the TU size bits before fdi link training, so that error
3088 * detection works. */
3089 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3090 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3092 /* For PCH output, training FDI link */
3093 dev_priv->display.fdi_link_train(crtc);
3095 /* XXX: pch pll's can be enabled any time before we enable the PCH
3096 * transcoder, and we actually should do this to not upset any PCH
3097 * transcoder that already use the clock when we share it.
3099 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3100 * unconditionally resets the pll - we need that to have the right LVDS
3101 * enable sequence. */
3102 ironlake_enable_pch_pll(intel_crtc);
3104 if (HAS_PCH_CPT(dev)) {
3107 temp = I915_READ(PCH_DPLL_SEL);
3111 temp |= TRANSA_DPLL_ENABLE;
3112 sel = TRANSA_DPLLB_SEL;
3115 temp |= TRANSB_DPLL_ENABLE;
3116 sel = TRANSB_DPLLB_SEL;
3119 temp |= TRANSC_DPLL_ENABLE;
3120 sel = TRANSC_DPLLB_SEL;
3123 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3127 I915_WRITE(PCH_DPLL_SEL, temp);
3130 /* set transcoder timing, panel must allow it */
3131 assert_panel_unlocked(dev_priv, pipe);
3132 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3133 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3134 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3136 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3137 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3138 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3139 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3141 intel_fdi_normal_train(crtc);
3143 /* For PCH DP, enable TRANS_DP_CTL */
3144 if (HAS_PCH_CPT(dev) &&
3145 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3146 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3147 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3148 reg = TRANS_DP_CTL(pipe);
3149 temp = I915_READ(reg);
3150 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3151 TRANS_DP_SYNC_MASK |
3153 temp |= (TRANS_DP_OUTPUT_ENABLE |
3154 TRANS_DP_ENH_FRAMING);
3155 temp |= bpc << 9; /* same format but at 11:9 */
3157 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3158 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3159 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3160 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3162 switch (intel_trans_dp_port_sel(crtc)) {
3164 temp |= TRANS_DP_PORT_SEL_B;
3167 temp |= TRANS_DP_PORT_SEL_C;
3170 temp |= TRANS_DP_PORT_SEL_D;
3176 I915_WRITE(reg, temp);
3179 ironlake_enable_pch_transcoder(dev_priv, pipe);
3182 static void lpt_pch_enable(struct drm_crtc *crtc)
3184 struct drm_device *dev = crtc->dev;
3185 struct drm_i915_private *dev_priv = dev->dev_private;
3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3189 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3191 lpt_program_iclkip(crtc);
3193 /* Set transcoder timing. */
3194 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3195 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3196 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3198 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3199 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3200 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3201 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3203 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3206 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3208 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3213 if (pll->refcount == 0) {
3214 WARN(1, "bad PCH PLL refcount\n");
3219 intel_crtc->pch_pll = NULL;
3222 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3224 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3225 struct intel_pch_pll *pll;
3228 pll = intel_crtc->pch_pll;
3230 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3231 intel_crtc->base.base.id, pll->pll_reg);
3235 if (HAS_PCH_IBX(dev_priv->dev)) {
3236 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3237 i = intel_crtc->pipe;
3238 pll = &dev_priv->pch_plls[i];
3240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3241 intel_crtc->base.base.id, pll->pll_reg);
3246 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3247 pll = &dev_priv->pch_plls[i];
3249 /* Only want to check enabled timings first */
3250 if (pll->refcount == 0)
3253 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3254 fp == I915_READ(pll->fp0_reg)) {
3255 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3256 intel_crtc->base.base.id,
3257 pll->pll_reg, pll->refcount, pll->active);
3263 /* Ok no matching timings, maybe there's a free one? */
3264 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3265 pll = &dev_priv->pch_plls[i];
3266 if (pll->refcount == 0) {
3267 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3268 intel_crtc->base.base.id, pll->pll_reg);
3276 intel_crtc->pch_pll = pll;
3278 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3279 prepare: /* separate function? */
3280 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3282 /* Wait for the clocks to stabilize before rewriting the regs */
3283 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3284 POSTING_READ(pll->pll_reg);
3287 I915_WRITE(pll->fp0_reg, fp);
3288 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3293 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 int dslreg = PIPEDSL(pipe);
3299 temp = I915_READ(dslreg);
3301 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3302 if (wait_for(I915_READ(dslreg) != temp, 5))
3303 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3307 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 struct intel_encoder *encoder;
3313 int pipe = intel_crtc->pipe;
3314 int plane = intel_crtc->plane;
3318 WARN_ON(!crtc->enabled);
3320 if (intel_crtc->active)
3323 intel_crtc->active = true;
3324 intel_update_watermarks(dev);
3326 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3327 temp = I915_READ(PCH_LVDS);
3328 if ((temp & LVDS_PORT_EN) == 0)
3329 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3332 is_pch_port = ironlake_crtc_driving_pch(crtc);
3335 /* Note: FDI PLL enabling _must_ be done before we enable the
3336 * cpu pipes, hence this is separate from all the other fdi/pch
3338 ironlake_fdi_pll_enable(intel_crtc);
3340 assert_fdi_tx_disabled(dev_priv, pipe);
3341 assert_fdi_rx_disabled(dev_priv, pipe);
3344 for_each_encoder_on_crtc(dev, crtc, encoder)
3345 if (encoder->pre_enable)
3346 encoder->pre_enable(encoder);
3348 /* Enable panel fitting for LVDS */
3349 if (dev_priv->pch_pf_size &&
3350 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3352 /* Force use of hard-coded filter coefficients
3353 * as some pre-programmed values are broken,
3356 if (IS_IVYBRIDGE(dev))
3357 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358 PF_PIPE_SEL_IVB(pipe));
3360 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3361 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3366 * On ILK+ LUT must be loaded before the pipe is running but with
3369 intel_crtc_load_lut(crtc);
3371 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3372 intel_enable_plane(dev_priv, plane, pipe);
3375 ironlake_pch_enable(crtc);
3377 mutex_lock(&dev->struct_mutex);
3378 intel_update_fbc(dev);
3379 mutex_unlock(&dev->struct_mutex);
3381 intel_crtc_update_cursor(crtc, true);
3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->enable(encoder);
3386 if (HAS_PCH_CPT(dev))
3387 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3390 * There seems to be a race in PCH platform hw (at least on some
3391 * outputs) where an enabled pipe still completes any pageflip right
3392 * away (as if the pipe is off) instead of waiting for vblank. As soon
3393 * as the first vblank happend, everything works as expected. Hence just
3394 * wait for one vblank before returning to avoid strange things
3397 intel_wait_for_vblank(dev, intel_crtc->pipe);
3400 static void haswell_crtc_enable(struct drm_crtc *crtc)
3402 struct drm_device *dev = crtc->dev;
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3405 struct intel_encoder *encoder;
3406 int pipe = intel_crtc->pipe;
3407 int plane = intel_crtc->plane;
3410 WARN_ON(!crtc->enabled);
3412 if (intel_crtc->active)
3415 intel_crtc->active = true;
3416 intel_update_watermarks(dev);
3418 is_pch_port = haswell_crtc_driving_pch(crtc);
3421 dev_priv->display.fdi_link_train(crtc);
3423 for_each_encoder_on_crtc(dev, crtc, encoder)
3424 if (encoder->pre_enable)
3425 encoder->pre_enable(encoder);
3427 intel_ddi_enable_pipe_clock(intel_crtc);
3429 /* Enable panel fitting for eDP */
3430 if (dev_priv->pch_pf_size &&
3431 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3432 /* Force use of hard-coded filter coefficients
3433 * as some pre-programmed values are broken,
3436 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3437 PF_PIPE_SEL_IVB(pipe));
3438 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3439 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3443 * On ILK+ LUT must be loaded before the pipe is running but with
3446 intel_crtc_load_lut(crtc);
3448 intel_ddi_set_pipe_settings(crtc);
3449 intel_ddi_enable_pipe_func(crtc);
3451 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3452 intel_enable_plane(dev_priv, plane, pipe);
3455 lpt_pch_enable(crtc);
3457 mutex_lock(&dev->struct_mutex);
3458 intel_update_fbc(dev);
3459 mutex_unlock(&dev->struct_mutex);
3461 intel_crtc_update_cursor(crtc, true);
3463 for_each_encoder_on_crtc(dev, crtc, encoder)
3464 encoder->enable(encoder);
3467 * There seems to be a race in PCH platform hw (at least on some
3468 * outputs) where an enabled pipe still completes any pageflip right
3469 * away (as if the pipe is off) instead of waiting for vblank. As soon
3470 * as the first vblank happend, everything works as expected. Hence just
3471 * wait for one vblank before returning to avoid strange things
3474 intel_wait_for_vblank(dev, intel_crtc->pipe);
3477 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3479 struct drm_device *dev = crtc->dev;
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482 struct intel_encoder *encoder;
3483 int pipe = intel_crtc->pipe;
3484 int plane = intel_crtc->plane;
3488 if (!intel_crtc->active)
3491 for_each_encoder_on_crtc(dev, crtc, encoder)
3492 encoder->disable(encoder);
3494 intel_crtc_wait_for_pending_flips(crtc);
3495 drm_vblank_off(dev, pipe);
3496 intel_crtc_update_cursor(crtc, false);
3498 intel_disable_plane(dev_priv, plane, pipe);
3500 if (dev_priv->cfb_plane == plane)
3501 intel_disable_fbc(dev);
3503 intel_disable_pipe(dev_priv, pipe);
3506 I915_WRITE(PF_CTL(pipe), 0);
3507 I915_WRITE(PF_WIN_SZ(pipe), 0);
3509 for_each_encoder_on_crtc(dev, crtc, encoder)
3510 if (encoder->post_disable)
3511 encoder->post_disable(encoder);
3513 ironlake_fdi_disable(crtc);
3515 ironlake_disable_pch_transcoder(dev_priv, pipe);
3517 if (HAS_PCH_CPT(dev)) {
3518 /* disable TRANS_DP_CTL */
3519 reg = TRANS_DP_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3522 temp |= TRANS_DP_PORT_SEL_NONE;
3523 I915_WRITE(reg, temp);
3525 /* disable DPLL_SEL */
3526 temp = I915_READ(PCH_DPLL_SEL);
3529 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3532 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3535 /* C shares PLL A or B */
3536 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3541 I915_WRITE(PCH_DPLL_SEL, temp);
3544 /* disable PCH DPLL */
3545 intel_disable_pch_pll(intel_crtc);
3547 ironlake_fdi_pll_disable(intel_crtc);
3549 intel_crtc->active = false;
3550 intel_update_watermarks(dev);
3552 mutex_lock(&dev->struct_mutex);
3553 intel_update_fbc(dev);
3554 mutex_unlock(&dev->struct_mutex);
3557 static void haswell_crtc_disable(struct drm_crtc *crtc)
3559 struct drm_device *dev = crtc->dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 struct intel_encoder *encoder;
3563 int pipe = intel_crtc->pipe;
3564 int plane = intel_crtc->plane;
3565 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3568 if (!intel_crtc->active)
3571 is_pch_port = haswell_crtc_driving_pch(crtc);
3573 for_each_encoder_on_crtc(dev, crtc, encoder)
3574 encoder->disable(encoder);
3576 intel_crtc_wait_for_pending_flips(crtc);
3577 drm_vblank_off(dev, pipe);
3578 intel_crtc_update_cursor(crtc, false);
3580 intel_disable_plane(dev_priv, plane, pipe);
3582 if (dev_priv->cfb_plane == plane)
3583 intel_disable_fbc(dev);
3585 intel_disable_pipe(dev_priv, pipe);
3587 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3590 I915_WRITE(PF_CTL(pipe), 0);
3591 I915_WRITE(PF_WIN_SZ(pipe), 0);
3593 intel_ddi_disable_pipe_clock(intel_crtc);
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3600 lpt_disable_pch_transcoder(dev_priv);
3601 intel_ddi_fdi_disable(crtc);
3604 intel_crtc->active = false;
3605 intel_update_watermarks(dev);
3607 mutex_lock(&dev->struct_mutex);
3608 intel_update_fbc(dev);
3609 mutex_unlock(&dev->struct_mutex);
3612 static void ironlake_crtc_off(struct drm_crtc *crtc)
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 intel_put_pch_pll(intel_crtc);
3618 static void haswell_crtc_off(struct drm_crtc *crtc)
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3623 * start using it. */
3624 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3626 intel_ddi_put_crtc_pll(crtc);
3629 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3631 if (!enable && intel_crtc->overlay) {
3632 struct drm_device *dev = intel_crtc->base.dev;
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3635 mutex_lock(&dev->struct_mutex);
3636 dev_priv->mm.interruptible = false;
3637 (void) intel_overlay_switch_off(intel_crtc->overlay);
3638 dev_priv->mm.interruptible = true;
3639 mutex_unlock(&dev->struct_mutex);
3642 /* Let userspace switch the overlay on again. In most cases userspace
3643 * has to recompute where to put it anyway.
3647 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3649 struct drm_device *dev = crtc->dev;
3650 struct drm_i915_private *dev_priv = dev->dev_private;
3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652 struct intel_encoder *encoder;
3653 int pipe = intel_crtc->pipe;
3654 int plane = intel_crtc->plane;
3656 WARN_ON(!crtc->enabled);
3658 if (intel_crtc->active)
3661 intel_crtc->active = true;
3662 intel_update_watermarks(dev);
3664 intel_enable_pll(dev_priv, pipe);
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->pre_enable)
3668 encoder->pre_enable(encoder);
3670 intel_enable_pipe(dev_priv, pipe, false);
3671 intel_enable_plane(dev_priv, plane, pipe);
3673 intel_crtc_load_lut(crtc);
3674 intel_update_fbc(dev);
3676 /* Give the overlay scaler a chance to enable if it's on this pipe */
3677 intel_crtc_dpms_overlay(intel_crtc, true);
3678 intel_crtc_update_cursor(crtc, true);
3680 for_each_encoder_on_crtc(dev, crtc, encoder)
3681 encoder->enable(encoder);
3684 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3686 struct drm_device *dev = crtc->dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 struct intel_encoder *encoder;
3690 int pipe = intel_crtc->pipe;
3691 int plane = intel_crtc->plane;
3695 if (!intel_crtc->active)
3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 encoder->disable(encoder);
3701 /* Give the overlay scaler a chance to disable if it's on this pipe */
3702 intel_crtc_wait_for_pending_flips(crtc);
3703 drm_vblank_off(dev, pipe);
3704 intel_crtc_dpms_overlay(intel_crtc, false);
3705 intel_crtc_update_cursor(crtc, false);
3707 if (dev_priv->cfb_plane == plane)
3708 intel_disable_fbc(dev);
3710 intel_disable_plane(dev_priv, plane, pipe);
3711 intel_disable_pipe(dev_priv, pipe);
3713 /* Disable pannel fitter if it is on this pipe. */
3714 pctl = I915_READ(PFIT_CONTROL);
3715 if ((pctl & PFIT_ENABLE) &&
3716 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3717 I915_WRITE(PFIT_CONTROL, 0);
3719 intel_disable_pll(dev_priv, pipe);
3721 intel_crtc->active = false;
3722 intel_update_fbc(dev);
3723 intel_update_watermarks(dev);
3726 static void i9xx_crtc_off(struct drm_crtc *crtc)
3730 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3733 struct drm_device *dev = crtc->dev;
3734 struct drm_i915_master_private *master_priv;
3735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3736 int pipe = intel_crtc->pipe;
3738 if (!dev->primary->master)
3741 master_priv = dev->primary->master->driver_priv;
3742 if (!master_priv->sarea_priv)
3747 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3748 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3751 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3752 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3755 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3761 * Sets the power management mode of the pipe and plane.
3763 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 struct intel_encoder *intel_encoder;
3768 bool enable = false;
3770 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3771 enable |= intel_encoder->connectors_active;
3774 dev_priv->display.crtc_enable(crtc);
3776 dev_priv->display.crtc_disable(crtc);
3778 intel_crtc_update_sarea(crtc, enable);
3781 static void intel_crtc_noop(struct drm_crtc *crtc)
3785 static void intel_crtc_disable(struct drm_crtc *crtc)
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_connector *connector;
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792 /* crtc should still be enabled when we disable it. */
3793 WARN_ON(!crtc->enabled);
3795 intel_crtc->eld_vld = false;
3796 dev_priv->display.crtc_disable(crtc);
3797 intel_crtc_update_sarea(crtc, false);
3798 dev_priv->display.off(crtc);
3800 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3801 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3804 mutex_lock(&dev->struct_mutex);
3805 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3806 mutex_unlock(&dev->struct_mutex);
3810 /* Update computed state. */
3811 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3812 if (!connector->encoder || !connector->encoder->crtc)
3815 if (connector->encoder->crtc != crtc)
3818 connector->dpms = DRM_MODE_DPMS_OFF;
3819 to_intel_encoder(connector->encoder)->connectors_active = false;
3823 void intel_modeset_disable(struct drm_device *dev)
3825 struct drm_crtc *crtc;
3827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 intel_crtc_disable(crtc);
3833 void intel_encoder_noop(struct drm_encoder *encoder)
3837 void intel_encoder_destroy(struct drm_encoder *encoder)
3839 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3841 drm_encoder_cleanup(encoder);
3842 kfree(intel_encoder);
3845 /* Simple dpms helper for encodres with just one connector, no cloning and only
3846 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3847 * state of the entire output pipe. */
3848 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3850 if (mode == DRM_MODE_DPMS_ON) {
3851 encoder->connectors_active = true;
3853 intel_crtc_update_dpms(encoder->base.crtc);
3855 encoder->connectors_active = false;
3857 intel_crtc_update_dpms(encoder->base.crtc);
3861 /* Cross check the actual hw state with our own modeset state tracking (and it's
3862 * internal consistency). */
3863 static void intel_connector_check_state(struct intel_connector *connector)
3865 if (connector->get_hw_state(connector)) {
3866 struct intel_encoder *encoder = connector->encoder;
3867 struct drm_crtc *crtc;
3868 bool encoder_enabled;
3871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3872 connector->base.base.id,
3873 drm_get_connector_name(&connector->base));
3875 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3876 "wrong connector dpms state\n");
3877 WARN(connector->base.encoder != &encoder->base,
3878 "active connector not linked to encoder\n");
3879 WARN(!encoder->connectors_active,
3880 "encoder->connectors_active not set\n");
3882 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3883 WARN(!encoder_enabled, "encoder not enabled\n");
3884 if (WARN_ON(!encoder->base.crtc))
3887 crtc = encoder->base.crtc;
3889 WARN(!crtc->enabled, "crtc not enabled\n");
3890 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3891 WARN(pipe != to_intel_crtc(crtc)->pipe,
3892 "encoder active on the wrong pipe\n");
3896 /* Even simpler default implementation, if there's really no special case to
3898 void intel_connector_dpms(struct drm_connector *connector, int mode)
3900 struct intel_encoder *encoder = intel_attached_encoder(connector);
3902 /* All the simple cases only support two dpms states. */
3903 if (mode != DRM_MODE_DPMS_ON)
3904 mode = DRM_MODE_DPMS_OFF;
3906 if (mode == connector->dpms)
3909 connector->dpms = mode;
3911 /* Only need to change hw state when actually enabled */
3912 if (encoder->base.crtc)
3913 intel_encoder_dpms(encoder, mode);
3915 WARN_ON(encoder->connectors_active != false);
3917 intel_modeset_check_state(connector->dev);
3920 /* Simple connector->get_hw_state implementation for encoders that support only
3921 * one connector and no cloning and hence the encoder state determines the state
3922 * of the connector. */
3923 bool intel_connector_get_hw_state(struct intel_connector *connector)
3926 struct intel_encoder *encoder = connector->encoder;
3928 return encoder->get_hw_state(encoder, &pipe);
3931 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3932 const struct drm_display_mode *mode,
3933 struct drm_display_mode *adjusted_mode)
3935 struct drm_device *dev = crtc->dev;
3937 if (HAS_PCH_SPLIT(dev)) {
3938 /* FDI link clock is fixed at 2.7G */
3939 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3943 /* All interlaced capable intel hw wants timings in frames. Note though
3944 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3945 * timings, so we need to be careful not to clobber these.*/
3946 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3947 drm_mode_set_crtcinfo(adjusted_mode, 0);
3949 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3950 * with a hsync front porch of 0.
3952 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3953 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3959 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3961 return 400000; /* FIXME */
3964 static int i945_get_display_clock_speed(struct drm_device *dev)
3969 static int i915_get_display_clock_speed(struct drm_device *dev)
3974 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3979 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3983 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3985 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3988 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3989 case GC_DISPLAY_CLOCK_333_MHZ:
3992 case GC_DISPLAY_CLOCK_190_200_MHZ:
3998 static int i865_get_display_clock_speed(struct drm_device *dev)
4003 static int i855_get_display_clock_speed(struct drm_device *dev)
4006 /* Assume that the hardware is in the high speed state. This
4007 * should be the default.
4009 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4010 case GC_CLOCK_133_200:
4011 case GC_CLOCK_100_200:
4013 case GC_CLOCK_166_250:
4015 case GC_CLOCK_100_133:
4019 /* Shouldn't happen */
4023 static int i830_get_display_clock_speed(struct drm_device *dev)
4029 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4031 while (*num > 0xffffff || *den > 0xffffff) {
4038 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4039 int pixel_clock, int link_clock,
4040 struct intel_link_m_n *m_n)
4043 m_n->gmch_m = bits_per_pixel * pixel_clock;
4044 m_n->gmch_n = link_clock * nlanes * 8;
4045 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4046 m_n->link_m = pixel_clock;
4047 m_n->link_n = link_clock;
4048 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4051 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4053 if (i915_panel_use_ssc >= 0)
4054 return i915_panel_use_ssc != 0;
4055 return dev_priv->lvds_use_ssc
4056 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4060 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4061 * @crtc: CRTC structure
4062 * @mode: requested mode
4064 * A pipe may be connected to one or more outputs. Based on the depth of the
4065 * attached framebuffer, choose a good color depth to use on the pipe.
4067 * If possible, match the pipe depth to the fb depth. In some cases, this
4068 * isn't ideal, because the connected output supports a lesser or restricted
4069 * set of depths. Resolve that here:
4070 * LVDS typically supports only 6bpc, so clamp down in that case
4071 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4072 * Displays may support a restricted set as well, check EDID and clamp as
4074 * DP may want to dither down to 6bpc to fit larger modes
4077 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4078 * true if they don't match).
4080 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4081 struct drm_framebuffer *fb,
4082 unsigned int *pipe_bpp,
4083 struct drm_display_mode *mode)
4085 struct drm_device *dev = crtc->dev;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 struct drm_connector *connector;
4088 struct intel_encoder *intel_encoder;
4089 unsigned int display_bpc = UINT_MAX, bpc;
4091 /* Walk the encoders & connectors on this crtc, get min bpc */
4092 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4094 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4095 unsigned int lvds_bpc;
4097 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4103 if (lvds_bpc < display_bpc) {
4104 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4105 display_bpc = lvds_bpc;
4110 /* Not one of the known troublemakers, check the EDID */
4111 list_for_each_entry(connector, &dev->mode_config.connector_list,
4113 if (connector->encoder != &intel_encoder->base)
4116 /* Don't use an invalid EDID bpc value */
4117 if (connector->display_info.bpc &&
4118 connector->display_info.bpc < display_bpc) {
4119 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4120 display_bpc = connector->display_info.bpc;
4124 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4125 /* Use VBT settings if we have an eDP panel */
4126 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4128 if (edp_bpc && edp_bpc < display_bpc) {
4129 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4130 display_bpc = edp_bpc;
4136 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4137 * through, clamp it down. (Note: >12bpc will be caught below.)
4139 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4140 if (display_bpc > 8 && display_bpc < 12) {
4141 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4144 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4150 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4151 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4156 * We could just drive the pipe at the highest bpc all the time and
4157 * enable dithering as needed, but that costs bandwidth. So choose
4158 * the minimum value that expresses the full color range of the fb but
4159 * also stays within the max display bpc discovered above.
4162 switch (fb->depth) {
4164 bpc = 8; /* since we go through a colormap */
4168 bpc = 6; /* min is 18bpp */
4180 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4181 bpc = min((unsigned int)8, display_bpc);
4185 display_bpc = min(display_bpc, bpc);
4187 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4190 *pipe_bpp = display_bpc * 3;
4192 return display_bpc != bpc;
4195 static int vlv_get_refclk(struct drm_crtc *crtc)
4197 struct drm_device *dev = crtc->dev;
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4199 int refclk = 27000; /* for DP & HDMI */
4201 return 100000; /* only one validated so far */
4203 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4206 if (intel_panel_use_ssc(dev_priv))
4210 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4217 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219 struct drm_device *dev = crtc->dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4223 if (IS_VALLEYVIEW(dev)) {
4224 refclk = vlv_get_refclk(crtc);
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4226 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4227 refclk = dev_priv->lvds_ssc_freq * 1000;
4228 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 } else if (!IS_GEN2(dev)) {
4239 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4240 intel_clock_t *clock)
4242 /* SDVO TV has fixed PLL values depend on its clock range,
4243 this mirrors vbios setting. */
4244 if (adjusted_mode->clock >= 100000
4245 && adjusted_mode->clock < 140500) {
4251 } else if (adjusted_mode->clock >= 140500
4252 && adjusted_mode->clock <= 200000) {
4261 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4262 intel_clock_t *clock,
4263 intel_clock_t *reduced_clock)
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4268 int pipe = intel_crtc->pipe;
4271 if (IS_PINEVIEW(dev)) {
4272 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4274 fp2 = (1 << reduced_clock->n) << 16 |
4275 reduced_clock->m1 << 8 | reduced_clock->m2;
4277 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4279 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4283 I915_WRITE(FP0(pipe), fp);
4285 intel_crtc->lowfreq_avail = false;
4286 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4287 reduced_clock && i915_powersave) {
4288 I915_WRITE(FP1(pipe), fp2);
4289 intel_crtc->lowfreq_avail = true;
4291 I915_WRITE(FP1(pipe), fp);
4295 static void vlv_update_pll(struct drm_crtc *crtc,
4296 struct drm_display_mode *mode,
4297 struct drm_display_mode *adjusted_mode,
4298 intel_clock_t *clock, intel_clock_t *reduced_clock,
4301 struct drm_device *dev = crtc->dev;
4302 struct drm_i915_private *dev_priv = dev->dev_private;
4303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304 int pipe = intel_crtc->pipe;
4305 u32 dpll, mdiv, pdiv;
4306 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4310 mutex_lock(&dev_priv->dpio_lock);
4312 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4313 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4315 dpll = DPLL_VGA_MODE_DIS;
4316 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4317 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4318 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4320 I915_WRITE(DPLL(pipe), dpll);
4321 POSTING_READ(DPLL(pipe));
4330 * In Valleyview PLL and program lane counter registers are exposed
4331 * through DPIO interface
4333 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4334 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4335 mdiv |= ((bestn << DPIO_N_SHIFT));
4336 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4337 mdiv |= (1 << DPIO_K_SHIFT);
4338 mdiv |= DPIO_ENABLE_CALIBRATION;
4339 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4341 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4343 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4344 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4345 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4346 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4347 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4349 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4351 dpll |= DPLL_VCO_ENABLE;
4352 I915_WRITE(DPLL(pipe), dpll);
4353 POSTING_READ(DPLL(pipe));
4354 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4355 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4357 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4360 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4362 I915_WRITE(DPLL(pipe), dpll);
4364 /* Wait for the clocks to stabilize. */
4365 POSTING_READ(DPLL(pipe));
4370 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4372 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4376 I915_WRITE(DPLL_MD(pipe), temp);
4377 POSTING_READ(DPLL_MD(pipe));
4379 /* Now program lane control registers */
4380 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4381 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4386 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4388 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4393 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4396 mutex_unlock(&dev_priv->dpio_lock);
4399 static void i9xx_update_pll(struct drm_crtc *crtc,
4400 struct drm_display_mode *mode,
4401 struct drm_display_mode *adjusted_mode,
4402 intel_clock_t *clock, intel_clock_t *reduced_clock,
4405 struct drm_device *dev = crtc->dev;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4408 struct intel_encoder *encoder;
4409 int pipe = intel_crtc->pipe;
4413 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4415 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4416 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4418 dpll = DPLL_VGA_MODE_DIS;
4420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4421 dpll |= DPLLB_MODE_LVDS;
4423 dpll |= DPLLB_MODE_DAC_SERIAL;
4425 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4426 if (pixel_multiplier > 1) {
4427 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4428 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4430 dpll |= DPLL_DVO_HIGH_SPEED;
4432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4433 dpll |= DPLL_DVO_HIGH_SPEED;
4435 /* compute bitmask from p1 value */
4436 if (IS_PINEVIEW(dev))
4437 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4439 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4440 if (IS_G4X(dev) && reduced_clock)
4441 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4443 switch (clock->p2) {
4445 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4448 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4451 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4454 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4457 if (INTEL_INFO(dev)->gen >= 4)
4458 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4460 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4461 dpll |= PLL_REF_INPUT_TVCLKINBC;
4462 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4463 /* XXX: just matching BIOS for now */
4464 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4466 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4467 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4468 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4470 dpll |= PLL_REF_INPUT_DREFCLK;
4472 dpll |= DPLL_VCO_ENABLE;
4473 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4474 POSTING_READ(DPLL(pipe));
4477 for_each_encoder_on_crtc(dev, crtc, encoder)
4478 if (encoder->pre_pll_enable)
4479 encoder->pre_pll_enable(encoder);
4481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4482 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4484 I915_WRITE(DPLL(pipe), dpll);
4486 /* Wait for the clocks to stabilize. */
4487 POSTING_READ(DPLL(pipe));
4490 if (INTEL_INFO(dev)->gen >= 4) {
4493 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4495 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4499 I915_WRITE(DPLL_MD(pipe), temp);
4501 /* The pixel multiplier can only be updated once the
4502 * DPLL is enabled and the clocks are stable.
4504 * So write it again.
4506 I915_WRITE(DPLL(pipe), dpll);
4510 static void i8xx_update_pll(struct drm_crtc *crtc,
4511 struct drm_display_mode *adjusted_mode,
4512 intel_clock_t *clock, intel_clock_t *reduced_clock,
4515 struct drm_device *dev = crtc->dev;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518 struct intel_encoder *encoder;
4519 int pipe = intel_crtc->pipe;
4522 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4524 dpll = DPLL_VGA_MODE_DIS;
4526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4527 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4530 dpll |= PLL_P1_DIVIDE_BY_TWO;
4532 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4534 dpll |= PLL_P2_DIVIDE_BY_4;
4537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4538 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4539 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4541 dpll |= PLL_REF_INPUT_DREFCLK;
4543 dpll |= DPLL_VCO_ENABLE;
4544 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4545 POSTING_READ(DPLL(pipe));
4548 for_each_encoder_on_crtc(dev, crtc, encoder)
4549 if (encoder->pre_pll_enable)
4550 encoder->pre_pll_enable(encoder);
4552 I915_WRITE(DPLL(pipe), dpll);
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4558 /* The pixel multiplier can only be updated once the
4559 * DPLL is enabled and the clocks are stable.
4561 * So write it again.
4563 I915_WRITE(DPLL(pipe), dpll);
4566 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4567 struct drm_display_mode *mode,
4568 struct drm_display_mode *adjusted_mode)
4570 struct drm_device *dev = intel_crtc->base.dev;
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 enum pipe pipe = intel_crtc->pipe;
4573 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4574 uint32_t vsyncshift;
4576 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4577 /* the chip adds 2 halflines automatically */
4578 adjusted_mode->crtc_vtotal -= 1;
4579 adjusted_mode->crtc_vblank_end -= 1;
4580 vsyncshift = adjusted_mode->crtc_hsync_start
4581 - adjusted_mode->crtc_htotal / 2;
4586 if (INTEL_INFO(dev)->gen > 3)
4587 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4589 I915_WRITE(HTOTAL(cpu_transcoder),
4590 (adjusted_mode->crtc_hdisplay - 1) |
4591 ((adjusted_mode->crtc_htotal - 1) << 16));
4592 I915_WRITE(HBLANK(cpu_transcoder),
4593 (adjusted_mode->crtc_hblank_start - 1) |
4594 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4595 I915_WRITE(HSYNC(cpu_transcoder),
4596 (adjusted_mode->crtc_hsync_start - 1) |
4597 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4599 I915_WRITE(VTOTAL(cpu_transcoder),
4600 (adjusted_mode->crtc_vdisplay - 1) |
4601 ((adjusted_mode->crtc_vtotal - 1) << 16));
4602 I915_WRITE(VBLANK(cpu_transcoder),
4603 (adjusted_mode->crtc_vblank_start - 1) |
4604 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4605 I915_WRITE(VSYNC(cpu_transcoder),
4606 (adjusted_mode->crtc_vsync_start - 1) |
4607 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4609 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4610 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4611 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4613 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4614 (pipe == PIPE_B || pipe == PIPE_C))
4615 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4617 /* pipesrc controls the size that is scaled from, which should
4618 * always be the user's requested size.
4620 I915_WRITE(PIPESRC(pipe),
4621 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4624 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4625 struct drm_display_mode *mode,
4626 struct drm_display_mode *adjusted_mode,
4628 struct drm_framebuffer *fb)
4630 struct drm_device *dev = crtc->dev;
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633 int pipe = intel_crtc->pipe;
4634 int plane = intel_crtc->plane;
4635 int refclk, num_connectors = 0;
4636 intel_clock_t clock, reduced_clock;
4637 u32 dspcntr, pipeconf;
4638 bool ok, has_reduced_clock = false, is_sdvo = false;
4639 bool is_lvds = false, is_tv = false, is_dp = false;
4640 struct intel_encoder *encoder;
4641 const intel_limit_t *limit;
4644 for_each_encoder_on_crtc(dev, crtc, encoder) {
4645 switch (encoder->type) {
4646 case INTEL_OUTPUT_LVDS:
4649 case INTEL_OUTPUT_SDVO:
4650 case INTEL_OUTPUT_HDMI:
4652 if (encoder->needs_tv_clock)
4655 case INTEL_OUTPUT_TVOUT:
4658 case INTEL_OUTPUT_DISPLAYPORT:
4666 refclk = i9xx_get_refclk(crtc, num_connectors);
4669 * Returns a set of divisors for the desired target clock with the given
4670 * refclk, or FALSE. The returned values represent the clock equation:
4671 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4673 limit = intel_limit(crtc, refclk);
4674 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4677 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4681 /* Ensure that the cursor is valid for the new mode before changing... */
4682 intel_crtc_update_cursor(crtc, true);
4684 if (is_lvds && dev_priv->lvds_downclock_avail) {
4686 * Ensure we match the reduced clock's P to the target clock.
4687 * If the clocks don't match, we can't switch the display clock
4688 * by using the FP0/FP1. In such case we will disable the LVDS
4689 * downclock feature.
4691 has_reduced_clock = limit->find_pll(limit, crtc,
4692 dev_priv->lvds_downclock,
4698 if (is_sdvo && is_tv)
4699 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4702 i8xx_update_pll(crtc, adjusted_mode, &clock,
4703 has_reduced_clock ? &reduced_clock : NULL,
4705 else if (IS_VALLEYVIEW(dev))
4706 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4707 has_reduced_clock ? &reduced_clock : NULL,
4710 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4711 has_reduced_clock ? &reduced_clock : NULL,
4714 /* setup pipeconf */
4715 pipeconf = I915_READ(PIPECONF(pipe));
4717 /* Set up the display plane register */
4718 dspcntr = DISPPLANE_GAMMA_ENABLE;
4721 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4723 dspcntr |= DISPPLANE_SEL_PIPE_B;
4725 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4726 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4729 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4733 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4734 pipeconf |= PIPECONF_DOUBLE_WIDE;
4736 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4739 /* default to 8bpc */
4740 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4742 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4743 pipeconf |= PIPECONF_6BPC |
4744 PIPECONF_DITHER_EN |
4745 PIPECONF_DITHER_TYPE_SP;
4749 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4750 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4751 pipeconf |= PIPECONF_6BPC |
4753 I965_PIPECONF_ACTIVE;
4757 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4758 drm_mode_debug_printmodeline(mode);
4760 if (HAS_PIPE_CXSR(dev)) {
4761 if (intel_crtc->lowfreq_avail) {
4762 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4763 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4765 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4766 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4770 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4771 if (!IS_GEN2(dev) &&
4772 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4773 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4775 pipeconf |= PIPECONF_PROGRESSIVE;
4777 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4779 /* pipesrc and dspsize control the size that is scaled from,
4780 * which should always be the user's requested size.
4782 I915_WRITE(DSPSIZE(plane),
4783 ((mode->vdisplay - 1) << 16) |
4784 (mode->hdisplay - 1));
4785 I915_WRITE(DSPPOS(plane), 0);
4787 I915_WRITE(PIPECONF(pipe), pipeconf);
4788 POSTING_READ(PIPECONF(pipe));
4789 intel_enable_pipe(dev_priv, pipe, false);
4791 intel_wait_for_vblank(dev, pipe);
4793 I915_WRITE(DSPCNTR(plane), dspcntr);
4794 POSTING_READ(DSPCNTR(plane));
4796 ret = intel_pipe_set_base(crtc, x, y, fb);
4798 intel_update_watermarks(dev);
4803 static void ironlake_init_pch_refclk(struct drm_device *dev)
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 struct drm_mode_config *mode_config = &dev->mode_config;
4807 struct intel_encoder *encoder;
4809 bool has_lvds = false;
4810 bool has_cpu_edp = false;
4811 bool has_pch_edp = false;
4812 bool has_panel = false;
4813 bool has_ck505 = false;
4814 bool can_ssc = false;
4816 /* We need to take the global config into account */
4817 list_for_each_entry(encoder, &mode_config->encoder_list,
4819 switch (encoder->type) {
4820 case INTEL_OUTPUT_LVDS:
4824 case INTEL_OUTPUT_EDP:
4826 if (intel_encoder_is_pch_edp(&encoder->base))
4834 if (HAS_PCH_IBX(dev)) {
4835 has_ck505 = dev_priv->display_clock_mode;
4836 can_ssc = has_ck505;
4842 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4843 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4846 /* Ironlake: try to setup display ref clock before DPLL
4847 * enabling. This is only under driver's control after
4848 * PCH B stepping, previous chipset stepping should be
4849 * ignoring this setting.
4851 temp = I915_READ(PCH_DREF_CONTROL);
4852 /* Always enable nonspread source */
4853 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4856 temp |= DREF_NONSPREAD_CK505_ENABLE;
4858 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4861 temp &= ~DREF_SSC_SOURCE_MASK;
4862 temp |= DREF_SSC_SOURCE_ENABLE;
4864 /* SSC must be turned on before enabling the CPU output */
4865 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4866 DRM_DEBUG_KMS("Using SSC on panel\n");
4867 temp |= DREF_SSC1_ENABLE;
4869 temp &= ~DREF_SSC1_ENABLE;
4871 /* Get SSC going before enabling the outputs */
4872 I915_WRITE(PCH_DREF_CONTROL, temp);
4873 POSTING_READ(PCH_DREF_CONTROL);
4876 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4878 /* Enable CPU source on CPU attached eDP */
4880 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4881 DRM_DEBUG_KMS("Using SSC on eDP\n");
4882 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4885 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4887 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4889 I915_WRITE(PCH_DREF_CONTROL, temp);
4890 POSTING_READ(PCH_DREF_CONTROL);
4893 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4895 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4897 /* Turn off CPU output */
4898 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4900 I915_WRITE(PCH_DREF_CONTROL, temp);
4901 POSTING_READ(PCH_DREF_CONTROL);
4904 /* Turn off the SSC source */
4905 temp &= ~DREF_SSC_SOURCE_MASK;
4906 temp |= DREF_SSC_SOURCE_DISABLE;
4909 temp &= ~ DREF_SSC1_ENABLE;
4911 I915_WRITE(PCH_DREF_CONTROL, temp);
4912 POSTING_READ(PCH_DREF_CONTROL);
4917 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4918 static void lpt_init_pch_refclk(struct drm_device *dev)
4920 struct drm_i915_private *dev_priv = dev->dev_private;
4921 struct drm_mode_config *mode_config = &dev->mode_config;
4922 struct intel_encoder *encoder;
4923 bool has_vga = false;
4924 bool is_sdv = false;
4927 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4928 switch (encoder->type) {
4929 case INTEL_OUTPUT_ANALOG:
4938 mutex_lock(&dev_priv->dpio_lock);
4940 /* XXX: Rip out SDV support once Haswell ships for real. */
4941 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4944 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4945 tmp &= ~SBI_SSCCTL_DISABLE;
4946 tmp |= SBI_SSCCTL_PATHALT;
4947 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4951 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4952 tmp &= ~SBI_SSCCTL_PATHALT;
4953 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4956 tmp = I915_READ(SOUTH_CHICKEN2);
4957 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4958 I915_WRITE(SOUTH_CHICKEN2, tmp);
4960 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4961 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4962 DRM_ERROR("FDI mPHY reset assert timeout\n");
4964 tmp = I915_READ(SOUTH_CHICKEN2);
4965 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4966 I915_WRITE(SOUTH_CHICKEN2, tmp);
4968 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4969 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4971 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4974 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4975 tmp &= ~(0xFF << 24);
4976 tmp |= (0x12 << 24);
4977 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4980 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4982 tmp |= (1 << 6) | (1 << 0);
4983 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4987 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4989 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4992 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4994 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4996 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4998 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5001 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5002 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5003 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5005 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5006 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5007 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5009 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5011 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5013 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5015 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5018 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5019 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5020 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5022 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5023 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5024 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5027 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5030 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5032 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5035 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5038 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5041 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5043 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5046 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5048 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5049 tmp &= ~(0xFF << 16);
5050 tmp |= (0x1C << 16);
5051 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5053 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5054 tmp &= ~(0xFF << 16);
5055 tmp |= (0x1C << 16);
5056 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5059 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5061 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5063 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5065 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5067 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5068 tmp &= ~(0xF << 28);
5070 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5072 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5073 tmp &= ~(0xF << 28);
5075 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5078 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5079 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5080 tmp |= SBI_DBUFF0_ENABLE;
5081 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5083 mutex_unlock(&dev_priv->dpio_lock);
5087 * Initialize reference clocks when the driver loads
5089 void intel_init_pch_refclk(struct drm_device *dev)
5091 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5092 ironlake_init_pch_refclk(dev);
5093 else if (HAS_PCH_LPT(dev))
5094 lpt_init_pch_refclk(dev);
5097 static int ironlake_get_refclk(struct drm_crtc *crtc)
5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_encoder *encoder;
5102 struct intel_encoder *edp_encoder = NULL;
5103 int num_connectors = 0;
5104 bool is_lvds = false;
5106 for_each_encoder_on_crtc(dev, crtc, encoder) {
5107 switch (encoder->type) {
5108 case INTEL_OUTPUT_LVDS:
5111 case INTEL_OUTPUT_EDP:
5112 edp_encoder = encoder;
5118 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5119 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5120 dev_priv->lvds_ssc_freq);
5121 return dev_priv->lvds_ssc_freq * 1000;
5127 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5128 struct drm_display_mode *adjusted_mode,
5131 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133 int pipe = intel_crtc->pipe;
5136 val = I915_READ(PIPECONF(pipe));
5138 val &= ~PIPECONF_BPC_MASK;
5139 switch (intel_crtc->bpp) {
5141 val |= PIPECONF_6BPC;
5144 val |= PIPECONF_8BPC;
5147 val |= PIPECONF_10BPC;
5150 val |= PIPECONF_12BPC;
5153 /* Case prevented by intel_choose_pipe_bpp_dither. */
5157 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5159 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5161 val &= ~PIPECONF_INTERLACE_MASK;
5162 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5163 val |= PIPECONF_INTERLACED_ILK;
5165 val |= PIPECONF_PROGRESSIVE;
5167 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5168 val |= PIPECONF_COLOR_RANGE_SELECT;
5170 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5172 I915_WRITE(PIPECONF(pipe), val);
5173 POSTING_READ(PIPECONF(pipe));
5177 * Set up the pipe CSC unit.
5179 * Currently only full range RGB to limited range RGB conversion
5180 * is supported, but eventually this should handle various
5181 * RGB<->YCbCr scenarios as well.
5183 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5184 const struct drm_display_mode *adjusted_mode)
5186 struct drm_device *dev = crtc->dev;
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189 int pipe = intel_crtc->pipe;
5190 uint16_t coeff = 0x7800; /* 1.0 */
5193 * TODO: Check what kind of values actually come out of the pipe
5194 * with these coeff/postoff values and adjust to get the best
5195 * accuracy. Perhaps we even need to take the bpc value into
5199 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5200 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5203 * GY/GU and RY/RU should be the other way around according
5204 * to BSpec, but reality doesn't agree. Just set them up in
5205 * a way that results in the correct picture.
5207 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5208 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5210 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5211 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5213 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5214 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5216 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5217 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5218 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5220 if (INTEL_INFO(dev)->gen > 6) {
5221 uint16_t postoff = 0;
5223 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5224 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5226 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5227 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5228 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5230 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5232 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5234 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5235 mode |= CSC_BLACK_SCREEN_OFFSET;
5237 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5241 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5242 struct drm_display_mode *adjusted_mode,
5245 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5250 val = I915_READ(PIPECONF(cpu_transcoder));
5252 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5254 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5256 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5257 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5258 val |= PIPECONF_INTERLACED_ILK;
5260 val |= PIPECONF_PROGRESSIVE;
5262 I915_WRITE(PIPECONF(cpu_transcoder), val);
5263 POSTING_READ(PIPECONF(cpu_transcoder));
5266 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5267 struct drm_display_mode *adjusted_mode,
5268 intel_clock_t *clock,
5269 bool *has_reduced_clock,
5270 intel_clock_t *reduced_clock)
5272 struct drm_device *dev = crtc->dev;
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274 struct intel_encoder *intel_encoder;
5276 const intel_limit_t *limit;
5277 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5279 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5280 switch (intel_encoder->type) {
5281 case INTEL_OUTPUT_LVDS:
5284 case INTEL_OUTPUT_SDVO:
5285 case INTEL_OUTPUT_HDMI:
5287 if (intel_encoder->needs_tv_clock)
5290 case INTEL_OUTPUT_TVOUT:
5296 refclk = ironlake_get_refclk(crtc);
5299 * Returns a set of divisors for the desired target clock with the given
5300 * refclk, or FALSE. The returned values represent the clock equation:
5301 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5303 limit = intel_limit(crtc, refclk);
5304 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5309 if (is_lvds && dev_priv->lvds_downclock_avail) {
5311 * Ensure we match the reduced clock's P to the target clock.
5312 * If the clocks don't match, we can't switch the display clock
5313 * by using the FP0/FP1. In such case we will disable the LVDS
5314 * downclock feature.
5316 *has_reduced_clock = limit->find_pll(limit, crtc,
5317 dev_priv->lvds_downclock,
5323 if (is_sdvo && is_tv)
5324 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5329 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5334 temp = I915_READ(SOUTH_CHICKEN1);
5335 if (temp & FDI_BC_BIFURCATION_SELECT)
5338 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5339 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5341 temp |= FDI_BC_BIFURCATION_SELECT;
5342 DRM_DEBUG_KMS("enabling fdi C rx\n");
5343 I915_WRITE(SOUTH_CHICKEN1, temp);
5344 POSTING_READ(SOUTH_CHICKEN1);
5347 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5349 struct drm_device *dev = intel_crtc->base.dev;
5350 struct drm_i915_private *dev_priv = dev->dev_private;
5351 struct intel_crtc *pipe_B_crtc =
5352 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5354 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5355 intel_crtc->pipe, intel_crtc->fdi_lanes);
5356 if (intel_crtc->fdi_lanes > 4) {
5357 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5358 intel_crtc->pipe, intel_crtc->fdi_lanes);
5359 /* Clamp lanes to avoid programming the hw with bogus values. */
5360 intel_crtc->fdi_lanes = 4;
5365 if (dev_priv->num_pipe == 2)
5368 switch (intel_crtc->pipe) {
5372 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5373 intel_crtc->fdi_lanes > 2) {
5374 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5375 intel_crtc->pipe, intel_crtc->fdi_lanes);
5376 /* Clamp lanes to avoid programming the hw with bogus values. */
5377 intel_crtc->fdi_lanes = 2;
5382 if (intel_crtc->fdi_lanes > 2)
5383 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5385 cpt_enable_fdi_bc_bifurcation(dev);
5389 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5390 if (intel_crtc->fdi_lanes > 2) {
5391 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5392 intel_crtc->pipe, intel_crtc->fdi_lanes);
5393 /* Clamp lanes to avoid programming the hw with bogus values. */
5394 intel_crtc->fdi_lanes = 2;
5399 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5403 cpt_enable_fdi_bc_bifurcation(dev);
5411 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5414 * Account for spread spectrum to avoid
5415 * oversubscribing the link. Max center spread
5416 * is 2.5%; use 5% for safety's sake.
5418 u32 bps = target_clock * bpp * 21 / 20;
5419 return bps / (link_bw * 8) + 1;
5422 static void ironlake_set_m_n(struct drm_crtc *crtc,
5423 struct drm_display_mode *mode,
5424 struct drm_display_mode *adjusted_mode)
5426 struct drm_device *dev = crtc->dev;
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5430 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5431 struct intel_link_m_n m_n = {0};
5432 int target_clock, pixel_multiplier, lane, link_bw;
5433 bool is_dp = false, is_cpu_edp = false;
5435 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5436 switch (intel_encoder->type) {
5437 case INTEL_OUTPUT_DISPLAYPORT:
5440 case INTEL_OUTPUT_EDP:
5442 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5444 edp_encoder = intel_encoder;
5450 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5452 /* CPU eDP doesn't require FDI link, so just set DP M/N
5453 according to current link config */
5455 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5457 /* FDI is a binary signal running at ~2.7GHz, encoding
5458 * each output octet as 10 bits. The actual frequency
5459 * is stored as a divider into a 100MHz clock, and the
5460 * mode pixel clock is stored in units of 1KHz.
5461 * Hence the bw of each lane in terms of the mode signal
5464 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5467 /* [e]DP over FDI requires target mode clock instead of link clock. */
5469 target_clock = intel_edp_target_clock(edp_encoder, mode);
5471 target_clock = mode->clock;
5473 target_clock = adjusted_mode->clock;
5476 lane = ironlake_get_lanes_required(target_clock, link_bw,
5479 intel_crtc->fdi_lanes = lane;
5481 if (pixel_multiplier > 1)
5482 link_bw *= pixel_multiplier;
5483 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5485 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5486 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5487 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5488 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5491 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5492 struct drm_display_mode *adjusted_mode,
5493 intel_clock_t *clock, u32 fp)
5495 struct drm_crtc *crtc = &intel_crtc->base;
5496 struct drm_device *dev = crtc->dev;
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct intel_encoder *intel_encoder;
5500 int factor, pixel_multiplier, num_connectors = 0;
5501 bool is_lvds = false, is_sdvo = false, is_tv = false;
5502 bool is_dp = false, is_cpu_edp = false;
5504 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5505 switch (intel_encoder->type) {
5506 case INTEL_OUTPUT_LVDS:
5509 case INTEL_OUTPUT_SDVO:
5510 case INTEL_OUTPUT_HDMI:
5512 if (intel_encoder->needs_tv_clock)
5515 case INTEL_OUTPUT_TVOUT:
5518 case INTEL_OUTPUT_DISPLAYPORT:
5521 case INTEL_OUTPUT_EDP:
5523 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5531 /* Enable autotuning of the PLL clock (if permissible) */
5534 if ((intel_panel_use_ssc(dev_priv) &&
5535 dev_priv->lvds_ssc_freq == 100) ||
5536 intel_is_dual_link_lvds(dev))
5538 } else if (is_sdvo && is_tv)
5541 if (clock->m < factor * clock->n)
5547 dpll |= DPLLB_MODE_LVDS;
5549 dpll |= DPLLB_MODE_DAC_SERIAL;
5551 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5552 if (pixel_multiplier > 1) {
5553 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5555 dpll |= DPLL_DVO_HIGH_SPEED;
5557 if (is_dp && !is_cpu_edp)
5558 dpll |= DPLL_DVO_HIGH_SPEED;
5560 /* compute bitmask from p1 value */
5561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5565 switch (clock->p2) {
5567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5580 if (is_sdvo && is_tv)
5581 dpll |= PLL_REF_INPUT_TVCLKINBC;
5583 /* XXX: just matching BIOS for now */
5584 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5586 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5587 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5589 dpll |= PLL_REF_INPUT_DREFCLK;
5594 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5595 struct drm_display_mode *mode,
5596 struct drm_display_mode *adjusted_mode,
5598 struct drm_framebuffer *fb)
5600 struct drm_device *dev = crtc->dev;
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603 int pipe = intel_crtc->pipe;
5604 int plane = intel_crtc->plane;
5605 int num_connectors = 0;
5606 intel_clock_t clock, reduced_clock;
5607 u32 dpll, fp = 0, fp2 = 0;
5608 bool ok, has_reduced_clock = false;
5609 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5610 struct intel_encoder *encoder;
5612 bool dither, fdi_config_ok;
5614 for_each_encoder_on_crtc(dev, crtc, encoder) {
5615 switch (encoder->type) {
5616 case INTEL_OUTPUT_LVDS:
5619 case INTEL_OUTPUT_DISPLAYPORT:
5622 case INTEL_OUTPUT_EDP:
5624 if (!intel_encoder_is_pch_edp(&encoder->base))
5632 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5633 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5635 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5636 &has_reduced_clock, &reduced_clock);
5638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5642 /* Ensure that the cursor is valid for the new mode before changing... */
5643 intel_crtc_update_cursor(crtc, true);
5645 /* determine panel color depth */
5646 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5648 if (is_lvds && dev_priv->lvds_dither)
5651 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5652 if (has_reduced_clock)
5653 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5656 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5658 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5659 drm_mode_debug_printmodeline(mode);
5661 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5663 struct intel_pch_pll *pll;
5665 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5667 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5672 intel_put_pch_pll(intel_crtc);
5674 if (is_dp && !is_cpu_edp)
5675 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5677 for_each_encoder_on_crtc(dev, crtc, encoder)
5678 if (encoder->pre_pll_enable)
5679 encoder->pre_pll_enable(encoder);
5681 if (intel_crtc->pch_pll) {
5682 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5684 /* Wait for the clocks to stabilize. */
5685 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5688 /* The pixel multiplier can only be updated once the
5689 * DPLL is enabled and the clocks are stable.
5691 * So write it again.
5693 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5696 intel_crtc->lowfreq_avail = false;
5697 if (intel_crtc->pch_pll) {
5698 if (is_lvds && has_reduced_clock && i915_powersave) {
5699 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5700 intel_crtc->lowfreq_avail = true;
5702 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5706 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5708 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5709 * ironlake_check_fdi_lanes. */
5710 ironlake_set_m_n(crtc, mode, adjusted_mode);
5712 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5714 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5716 intel_wait_for_vblank(dev, pipe);
5718 /* Set up the display plane register */
5719 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5720 POSTING_READ(DSPCNTR(plane));
5722 ret = intel_pipe_set_base(crtc, x, y, fb);
5724 intel_update_watermarks(dev);
5726 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5728 return fdi_config_ok ? ret : -EINVAL;
5731 static void haswell_modeset_global_resources(struct drm_device *dev)
5733 struct drm_i915_private *dev_priv = dev->dev_private;
5734 bool enable = false;
5735 struct intel_crtc *crtc;
5736 struct intel_encoder *encoder;
5738 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5739 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5741 /* XXX: Should check for edp transcoder here, but thanks to init
5742 * sequence that's not yet available. Just in case desktop eDP
5743 * on PORT D is possible on haswell, too. */
5746 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5748 if (encoder->type != INTEL_OUTPUT_EDP &&
5749 encoder->connectors_active)
5753 /* Even the eDP panel fitter is outside the always-on well. */
5754 if (dev_priv->pch_pf_size)
5757 intel_set_power_well(dev, enable);
5760 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5761 struct drm_display_mode *mode,
5762 struct drm_display_mode *adjusted_mode,
5764 struct drm_framebuffer *fb)
5766 struct drm_device *dev = crtc->dev;
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5769 int pipe = intel_crtc->pipe;
5770 int plane = intel_crtc->plane;
5771 int num_connectors = 0;
5772 bool is_dp = false, is_cpu_edp = false;
5773 struct intel_encoder *encoder;
5777 for_each_encoder_on_crtc(dev, crtc, encoder) {
5778 switch (encoder->type) {
5779 case INTEL_OUTPUT_DISPLAYPORT:
5782 case INTEL_OUTPUT_EDP:
5784 if (!intel_encoder_is_pch_edp(&encoder->base))
5792 /* We are not sure yet this won't happen. */
5793 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5794 INTEL_PCH_TYPE(dev));
5796 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5797 num_connectors, pipe_name(pipe));
5799 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5800 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5802 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5804 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5807 /* Ensure that the cursor is valid for the new mode before changing... */
5808 intel_crtc_update_cursor(crtc, true);
5810 /* determine panel color depth */
5811 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5814 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5815 drm_mode_debug_printmodeline(mode);
5817 if (is_dp && !is_cpu_edp)
5818 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5820 intel_crtc->lowfreq_avail = false;
5822 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5824 if (!is_dp || is_cpu_edp)
5825 ironlake_set_m_n(crtc, mode, adjusted_mode);
5827 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5829 intel_set_pipe_csc(crtc, adjusted_mode);
5831 /* Set up the display plane register */
5832 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5833 POSTING_READ(DSPCNTR(plane));
5835 ret = intel_pipe_set_base(crtc, x, y, fb);
5837 intel_update_watermarks(dev);
5839 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5844 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5845 struct drm_display_mode *mode,
5846 struct drm_display_mode *adjusted_mode,
5848 struct drm_framebuffer *fb)
5850 struct drm_device *dev = crtc->dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 struct drm_encoder_helper_funcs *encoder_funcs;
5853 struct intel_encoder *encoder;
5854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5855 int pipe = intel_crtc->pipe;
5858 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5859 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5861 intel_crtc->cpu_transcoder = pipe;
5863 drm_vblank_pre_modeset(dev, pipe);
5865 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5867 drm_vblank_post_modeset(dev, pipe);
5872 for_each_encoder_on_crtc(dev, crtc, encoder) {
5873 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5874 encoder->base.base.id,
5875 drm_get_encoder_name(&encoder->base),
5876 mode->base.id, mode->name);
5877 encoder_funcs = encoder->base.helper_private;
5878 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5884 static bool intel_eld_uptodate(struct drm_connector *connector,
5885 int reg_eldv, uint32_t bits_eldv,
5886 int reg_elda, uint32_t bits_elda,
5889 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5890 uint8_t *eld = connector->eld;
5893 i = I915_READ(reg_eldv);
5902 i = I915_READ(reg_elda);
5904 I915_WRITE(reg_elda, i);
5906 for (i = 0; i < eld[2]; i++)
5907 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5913 static void g4x_write_eld(struct drm_connector *connector,
5914 struct drm_crtc *crtc)
5916 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5917 uint8_t *eld = connector->eld;
5922 i = I915_READ(G4X_AUD_VID_DID);
5924 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5925 eldv = G4X_ELDV_DEVCL_DEVBLC;
5927 eldv = G4X_ELDV_DEVCTG;
5929 if (intel_eld_uptodate(connector,
5930 G4X_AUD_CNTL_ST, eldv,
5931 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5932 G4X_HDMIW_HDMIEDID))
5935 i = I915_READ(G4X_AUD_CNTL_ST);
5936 i &= ~(eldv | G4X_ELD_ADDR);
5937 len = (i >> 9) & 0x1f; /* ELD buffer size */
5938 I915_WRITE(G4X_AUD_CNTL_ST, i);
5943 len = min_t(uint8_t, eld[2], len);
5944 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5945 for (i = 0; i < len; i++)
5946 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5948 i = I915_READ(G4X_AUD_CNTL_ST);
5950 I915_WRITE(G4X_AUD_CNTL_ST, i);
5953 static void haswell_write_eld(struct drm_connector *connector,
5954 struct drm_crtc *crtc)
5956 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5957 uint8_t *eld = connector->eld;
5958 struct drm_device *dev = crtc->dev;
5959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5963 int pipe = to_intel_crtc(crtc)->pipe;
5966 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5967 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5968 int aud_config = HSW_AUD_CFG(pipe);
5969 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5972 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5974 /* Audio output enable */
5975 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5976 tmp = I915_READ(aud_cntrl_st2);
5977 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5978 I915_WRITE(aud_cntrl_st2, tmp);
5980 /* Wait for 1 vertical blank */
5981 intel_wait_for_vblank(dev, pipe);
5983 /* Set ELD valid state */
5984 tmp = I915_READ(aud_cntrl_st2);
5985 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5986 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5987 I915_WRITE(aud_cntrl_st2, tmp);
5988 tmp = I915_READ(aud_cntrl_st2);
5989 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5991 /* Enable HDMI mode */
5992 tmp = I915_READ(aud_config);
5993 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5994 /* clear N_programing_enable and N_value_index */
5995 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5996 I915_WRITE(aud_config, tmp);
5998 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6000 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6001 intel_crtc->eld_vld = true;
6003 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6004 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6005 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6006 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6008 I915_WRITE(aud_config, 0);
6010 if (intel_eld_uptodate(connector,
6011 aud_cntrl_st2, eldv,
6012 aud_cntl_st, IBX_ELD_ADDRESS,
6016 i = I915_READ(aud_cntrl_st2);
6018 I915_WRITE(aud_cntrl_st2, i);
6023 i = I915_READ(aud_cntl_st);
6024 i &= ~IBX_ELD_ADDRESS;
6025 I915_WRITE(aud_cntl_st, i);
6026 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6027 DRM_DEBUG_DRIVER("port num:%d\n", i);
6029 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6030 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6031 for (i = 0; i < len; i++)
6032 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6034 i = I915_READ(aud_cntrl_st2);
6036 I915_WRITE(aud_cntrl_st2, i);
6040 static void ironlake_write_eld(struct drm_connector *connector,
6041 struct drm_crtc *crtc)
6043 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6044 uint8_t *eld = connector->eld;
6052 int pipe = to_intel_crtc(crtc)->pipe;
6054 if (HAS_PCH_IBX(connector->dev)) {
6055 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6056 aud_config = IBX_AUD_CFG(pipe);
6057 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6058 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6060 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6061 aud_config = CPT_AUD_CFG(pipe);
6062 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6063 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6066 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6068 i = I915_READ(aud_cntl_st);
6069 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6071 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6072 /* operate blindly on all ports */
6073 eldv = IBX_ELD_VALIDB;
6074 eldv |= IBX_ELD_VALIDB << 4;
6075 eldv |= IBX_ELD_VALIDB << 8;
6077 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6078 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6081 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6082 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6083 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6084 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6086 I915_WRITE(aud_config, 0);
6088 if (intel_eld_uptodate(connector,
6089 aud_cntrl_st2, eldv,
6090 aud_cntl_st, IBX_ELD_ADDRESS,
6094 i = I915_READ(aud_cntrl_st2);
6096 I915_WRITE(aud_cntrl_st2, i);
6101 i = I915_READ(aud_cntl_st);
6102 i &= ~IBX_ELD_ADDRESS;
6103 I915_WRITE(aud_cntl_st, i);
6105 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6106 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6107 for (i = 0; i < len; i++)
6108 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6110 i = I915_READ(aud_cntrl_st2);
6112 I915_WRITE(aud_cntrl_st2, i);
6115 void intel_write_eld(struct drm_encoder *encoder,
6116 struct drm_display_mode *mode)
6118 struct drm_crtc *crtc = encoder->crtc;
6119 struct drm_connector *connector;
6120 struct drm_device *dev = encoder->dev;
6121 struct drm_i915_private *dev_priv = dev->dev_private;
6123 connector = drm_select_eld(encoder, mode);
6127 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6129 drm_get_connector_name(connector),
6130 connector->encoder->base.id,
6131 drm_get_encoder_name(connector->encoder));
6133 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6135 if (dev_priv->display.write_eld)
6136 dev_priv->display.write_eld(connector, crtc);
6139 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6140 void intel_crtc_load_lut(struct drm_crtc *crtc)
6142 struct drm_device *dev = crtc->dev;
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145 int palreg = PALETTE(intel_crtc->pipe);
6148 /* The clocks have to be on to load the palette. */
6149 if (!crtc->enabled || !intel_crtc->active)
6152 /* use legacy palette for Ironlake */
6153 if (HAS_PCH_SPLIT(dev))
6154 palreg = LGC_PALETTE(intel_crtc->pipe);
6156 for (i = 0; i < 256; i++) {
6157 I915_WRITE(palreg + 4 * i,
6158 (intel_crtc->lut_r[i] << 16) |
6159 (intel_crtc->lut_g[i] << 8) |
6160 intel_crtc->lut_b[i]);
6164 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6166 struct drm_device *dev = crtc->dev;
6167 struct drm_i915_private *dev_priv = dev->dev_private;
6168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6169 bool visible = base != 0;
6172 if (intel_crtc->cursor_visible == visible)
6175 cntl = I915_READ(_CURACNTR);
6177 /* On these chipsets we can only modify the base whilst
6178 * the cursor is disabled.
6180 I915_WRITE(_CURABASE, base);
6182 cntl &= ~(CURSOR_FORMAT_MASK);
6183 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6184 cntl |= CURSOR_ENABLE |
6185 CURSOR_GAMMA_ENABLE |
6188 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6189 I915_WRITE(_CURACNTR, cntl);
6191 intel_crtc->cursor_visible = visible;
6194 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6196 struct drm_device *dev = crtc->dev;
6197 struct drm_i915_private *dev_priv = dev->dev_private;
6198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6199 int pipe = intel_crtc->pipe;
6200 bool visible = base != 0;
6202 if (intel_crtc->cursor_visible != visible) {
6203 uint32_t cntl = I915_READ(CURCNTR(pipe));
6205 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6206 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6207 cntl |= pipe << 28; /* Connect to correct pipe */
6209 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6210 cntl |= CURSOR_MODE_DISABLE;
6212 I915_WRITE(CURCNTR(pipe), cntl);
6214 intel_crtc->cursor_visible = visible;
6216 /* and commit changes on next vblank */
6217 I915_WRITE(CURBASE(pipe), base);
6220 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6222 struct drm_device *dev = crtc->dev;
6223 struct drm_i915_private *dev_priv = dev->dev_private;
6224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225 int pipe = intel_crtc->pipe;
6226 bool visible = base != 0;
6228 if (intel_crtc->cursor_visible != visible) {
6229 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6231 cntl &= ~CURSOR_MODE;
6232 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6234 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6235 cntl |= CURSOR_MODE_DISABLE;
6237 if (IS_HASWELL(dev))
6238 cntl |= CURSOR_PIPE_CSC_ENABLE;
6239 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6241 intel_crtc->cursor_visible = visible;
6243 /* and commit changes on next vblank */
6244 I915_WRITE(CURBASE_IVB(pipe), base);
6247 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6248 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6251 struct drm_device *dev = crtc->dev;
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254 int pipe = intel_crtc->pipe;
6255 int x = intel_crtc->cursor_x;
6256 int y = intel_crtc->cursor_y;
6262 if (on && crtc->enabled && crtc->fb) {
6263 base = intel_crtc->cursor_addr;
6264 if (x > (int) crtc->fb->width)
6267 if (y > (int) crtc->fb->height)
6273 if (x + intel_crtc->cursor_width < 0)
6276 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6279 pos |= x << CURSOR_X_SHIFT;
6282 if (y + intel_crtc->cursor_height < 0)
6285 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6288 pos |= y << CURSOR_Y_SHIFT;
6290 visible = base != 0;
6291 if (!visible && !intel_crtc->cursor_visible)
6294 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6295 I915_WRITE(CURPOS_IVB(pipe), pos);
6296 ivb_update_cursor(crtc, base);
6298 I915_WRITE(CURPOS(pipe), pos);
6299 if (IS_845G(dev) || IS_I865G(dev))
6300 i845_update_cursor(crtc, base);
6302 i9xx_update_cursor(crtc, base);
6306 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6307 struct drm_file *file,
6309 uint32_t width, uint32_t height)
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 struct drm_i915_gem_object *obj;
6318 /* if we want to turn off the cursor ignore width and height */
6320 DRM_DEBUG_KMS("cursor off\n");
6323 mutex_lock(&dev->struct_mutex);
6327 /* Currently we only support 64x64 cursors */
6328 if (width != 64 || height != 64) {
6329 DRM_ERROR("we currently only support 64x64 cursors\n");
6333 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6334 if (&obj->base == NULL)
6337 if (obj->base.size < width * height * 4) {
6338 DRM_ERROR("buffer is to small\n");
6343 /* we only need to pin inside GTT if cursor is non-phy */
6344 mutex_lock(&dev->struct_mutex);
6345 if (!dev_priv->info->cursor_needs_physical) {
6346 if (obj->tiling_mode) {
6347 DRM_ERROR("cursor cannot be tiled\n");
6352 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6354 DRM_ERROR("failed to move cursor bo into the GTT\n");
6358 ret = i915_gem_object_put_fence(obj);
6360 DRM_ERROR("failed to release fence for cursor");
6364 addr = obj->gtt_offset;
6366 int align = IS_I830(dev) ? 16 * 1024 : 256;
6367 ret = i915_gem_attach_phys_object(dev, obj,
6368 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6371 DRM_ERROR("failed to attach phys object\n");
6374 addr = obj->phys_obj->handle->busaddr;
6378 I915_WRITE(CURSIZE, (height << 12) | width);
6381 if (intel_crtc->cursor_bo) {
6382 if (dev_priv->info->cursor_needs_physical) {
6383 if (intel_crtc->cursor_bo != obj)
6384 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6386 i915_gem_object_unpin(intel_crtc->cursor_bo);
6387 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6390 mutex_unlock(&dev->struct_mutex);
6392 intel_crtc->cursor_addr = addr;
6393 intel_crtc->cursor_bo = obj;
6394 intel_crtc->cursor_width = width;
6395 intel_crtc->cursor_height = height;
6397 intel_crtc_update_cursor(crtc, true);
6401 i915_gem_object_unpin(obj);
6403 mutex_unlock(&dev->struct_mutex);
6405 drm_gem_object_unreference_unlocked(&obj->base);
6409 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6413 intel_crtc->cursor_x = x;
6414 intel_crtc->cursor_y = y;
6416 intel_crtc_update_cursor(crtc, true);
6421 /** Sets the color ramps on behalf of RandR */
6422 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6423 u16 blue, int regno)
6425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6427 intel_crtc->lut_r[regno] = red >> 8;
6428 intel_crtc->lut_g[regno] = green >> 8;
6429 intel_crtc->lut_b[regno] = blue >> 8;
6432 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6433 u16 *blue, int regno)
6435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437 *red = intel_crtc->lut_r[regno] << 8;
6438 *green = intel_crtc->lut_g[regno] << 8;
6439 *blue = intel_crtc->lut_b[regno] << 8;
6442 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6443 u16 *blue, uint32_t start, uint32_t size)
6445 int end = (start + size > 256) ? 256 : start + size, i;
6446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6448 for (i = start; i < end; i++) {
6449 intel_crtc->lut_r[i] = red[i] >> 8;
6450 intel_crtc->lut_g[i] = green[i] >> 8;
6451 intel_crtc->lut_b[i] = blue[i] >> 8;
6454 intel_crtc_load_lut(crtc);
6457 /* VESA 640x480x72Hz mode to set on the pipe */
6458 static struct drm_display_mode load_detect_mode = {
6459 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6460 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6463 static struct drm_framebuffer *
6464 intel_framebuffer_create(struct drm_device *dev,
6465 struct drm_mode_fb_cmd2 *mode_cmd,
6466 struct drm_i915_gem_object *obj)
6468 struct intel_framebuffer *intel_fb;
6471 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6473 drm_gem_object_unreference_unlocked(&obj->base);
6474 return ERR_PTR(-ENOMEM);
6477 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6479 drm_gem_object_unreference_unlocked(&obj->base);
6481 return ERR_PTR(ret);
6484 return &intel_fb->base;
6488 intel_framebuffer_pitch_for_width(int width, int bpp)
6490 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6491 return ALIGN(pitch, 64);
6495 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6497 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6498 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6501 static struct drm_framebuffer *
6502 intel_framebuffer_create_for_mode(struct drm_device *dev,
6503 struct drm_display_mode *mode,
6506 struct drm_i915_gem_object *obj;
6507 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6509 obj = i915_gem_alloc_object(dev,
6510 intel_framebuffer_size_for_mode(mode, bpp));
6512 return ERR_PTR(-ENOMEM);
6514 mode_cmd.width = mode->hdisplay;
6515 mode_cmd.height = mode->vdisplay;
6516 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6518 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6520 return intel_framebuffer_create(dev, &mode_cmd, obj);
6523 static struct drm_framebuffer *
6524 mode_fits_in_fbdev(struct drm_device *dev,
6525 struct drm_display_mode *mode)
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 struct drm_i915_gem_object *obj;
6529 struct drm_framebuffer *fb;
6531 if (dev_priv->fbdev == NULL)
6534 obj = dev_priv->fbdev->ifb.obj;
6538 fb = &dev_priv->fbdev->ifb.base;
6539 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6540 fb->bits_per_pixel))
6543 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6549 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6550 struct drm_display_mode *mode,
6551 struct intel_load_detect_pipe *old)
6553 struct intel_crtc *intel_crtc;
6554 struct intel_encoder *intel_encoder =
6555 intel_attached_encoder(connector);
6556 struct drm_crtc *possible_crtc;
6557 struct drm_encoder *encoder = &intel_encoder->base;
6558 struct drm_crtc *crtc = NULL;
6559 struct drm_device *dev = encoder->dev;
6560 struct drm_framebuffer *fb;
6563 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6564 connector->base.id, drm_get_connector_name(connector),
6565 encoder->base.id, drm_get_encoder_name(encoder));
6568 * Algorithm gets a little messy:
6570 * - if the connector already has an assigned crtc, use it (but make
6571 * sure it's on first)
6573 * - try to find the first unused crtc that can drive this connector,
6574 * and use that if we find one
6577 /* See if we already have a CRTC for this connector */
6578 if (encoder->crtc) {
6579 crtc = encoder->crtc;
6581 mutex_lock(&crtc->mutex);
6583 old->dpms_mode = connector->dpms;
6584 old->load_detect_temp = false;
6586 /* Make sure the crtc and connector are running */
6587 if (connector->dpms != DRM_MODE_DPMS_ON)
6588 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6593 /* Find an unused one (if possible) */
6594 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6596 if (!(encoder->possible_crtcs & (1 << i)))
6598 if (!possible_crtc->enabled) {
6599 crtc = possible_crtc;
6605 * If we didn't find an unused CRTC, don't use any.
6608 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6612 mutex_lock(&crtc->mutex);
6613 intel_encoder->new_crtc = to_intel_crtc(crtc);
6614 to_intel_connector(connector)->new_encoder = intel_encoder;
6616 intel_crtc = to_intel_crtc(crtc);
6617 old->dpms_mode = connector->dpms;
6618 old->load_detect_temp = true;
6619 old->release_fb = NULL;
6622 mode = &load_detect_mode;
6624 /* We need a framebuffer large enough to accommodate all accesses
6625 * that the plane may generate whilst we perform load detection.
6626 * We can not rely on the fbcon either being present (we get called
6627 * during its initialisation to detect all boot displays, or it may
6628 * not even exist) or that it is large enough to satisfy the
6631 fb = mode_fits_in_fbdev(dev, mode);
6633 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6634 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6635 old->release_fb = fb;
6637 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6639 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6640 mutex_unlock(&crtc->mutex);
6644 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6645 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6646 if (old->release_fb)
6647 old->release_fb->funcs->destroy(old->release_fb);
6648 mutex_unlock(&crtc->mutex);
6652 /* let the connector get through one full cycle before testing */
6653 intel_wait_for_vblank(dev, intel_crtc->pipe);
6657 void intel_release_load_detect_pipe(struct drm_connector *connector,
6658 struct intel_load_detect_pipe *old)
6660 struct intel_encoder *intel_encoder =
6661 intel_attached_encoder(connector);
6662 struct drm_encoder *encoder = &intel_encoder->base;
6663 struct drm_crtc *crtc = encoder->crtc;
6665 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6666 connector->base.id, drm_get_connector_name(connector),
6667 encoder->base.id, drm_get_encoder_name(encoder));
6669 if (old->load_detect_temp) {
6670 to_intel_connector(connector)->new_encoder = NULL;
6671 intel_encoder->new_crtc = NULL;
6672 intel_set_mode(crtc, NULL, 0, 0, NULL);
6674 if (old->release_fb) {
6675 drm_framebuffer_unregister_private(old->release_fb);
6676 drm_framebuffer_unreference(old->release_fb);
6679 mutex_unlock(&crtc->mutex);
6683 /* Switch crtc and encoder back off if necessary */
6684 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6685 connector->funcs->dpms(connector, old->dpms_mode);
6687 mutex_unlock(&crtc->mutex);
6690 /* Returns the clock of the currently programmed mode of the given pipe. */
6691 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6693 struct drm_i915_private *dev_priv = dev->dev_private;
6694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6695 int pipe = intel_crtc->pipe;
6696 u32 dpll = I915_READ(DPLL(pipe));
6698 intel_clock_t clock;
6700 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6701 fp = I915_READ(FP0(pipe));
6703 fp = I915_READ(FP1(pipe));
6705 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6706 if (IS_PINEVIEW(dev)) {
6707 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6708 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6710 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6711 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6714 if (!IS_GEN2(dev)) {
6715 if (IS_PINEVIEW(dev))
6716 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6717 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6719 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6720 DPLL_FPA01_P1_POST_DIV_SHIFT);
6722 switch (dpll & DPLL_MODE_MASK) {
6723 case DPLLB_MODE_DAC_SERIAL:
6724 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6727 case DPLLB_MODE_LVDS:
6728 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6732 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6733 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6737 /* XXX: Handle the 100Mhz refclk */
6738 intel_clock(dev, 96000, &clock);
6740 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6743 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6744 DPLL_FPA01_P1_POST_DIV_SHIFT);
6747 if ((dpll & PLL_REF_INPUT_MASK) ==
6748 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6749 /* XXX: might not be 66MHz */
6750 intel_clock(dev, 66000, &clock);
6752 intel_clock(dev, 48000, &clock);
6754 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6757 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6758 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6760 if (dpll & PLL_P2_DIVIDE_BY_4)
6765 intel_clock(dev, 48000, &clock);
6769 /* XXX: It would be nice to validate the clocks, but we can't reuse
6770 * i830PllIsValid() because it relies on the xf86_config connector
6771 * configuration being accurate, which it isn't necessarily.
6777 /** Returns the currently programmed mode of the given pipe. */
6778 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6779 struct drm_crtc *crtc)
6781 struct drm_i915_private *dev_priv = dev->dev_private;
6782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6783 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6784 struct drm_display_mode *mode;
6785 int htot = I915_READ(HTOTAL(cpu_transcoder));
6786 int hsync = I915_READ(HSYNC(cpu_transcoder));
6787 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6788 int vsync = I915_READ(VSYNC(cpu_transcoder));
6790 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6794 mode->clock = intel_crtc_clock_get(dev, crtc);
6795 mode->hdisplay = (htot & 0xffff) + 1;
6796 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6797 mode->hsync_start = (hsync & 0xffff) + 1;
6798 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6799 mode->vdisplay = (vtot & 0xffff) + 1;
6800 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6801 mode->vsync_start = (vsync & 0xffff) + 1;
6802 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6804 drm_mode_set_name(mode);
6809 static void intel_increase_pllclock(struct drm_crtc *crtc)
6811 struct drm_device *dev = crtc->dev;
6812 drm_i915_private_t *dev_priv = dev->dev_private;
6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 int pipe = intel_crtc->pipe;
6815 int dpll_reg = DPLL(pipe);
6818 if (HAS_PCH_SPLIT(dev))
6821 if (!dev_priv->lvds_downclock_avail)
6824 dpll = I915_READ(dpll_reg);
6825 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6826 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6828 assert_panel_unlocked(dev_priv, pipe);
6830 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6831 I915_WRITE(dpll_reg, dpll);
6832 intel_wait_for_vblank(dev, pipe);
6834 dpll = I915_READ(dpll_reg);
6835 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6836 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6840 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6842 struct drm_device *dev = crtc->dev;
6843 drm_i915_private_t *dev_priv = dev->dev_private;
6844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846 if (HAS_PCH_SPLIT(dev))
6849 if (!dev_priv->lvds_downclock_avail)
6853 * Since this is called by a timer, we should never get here in
6856 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6857 int pipe = intel_crtc->pipe;
6858 int dpll_reg = DPLL(pipe);
6861 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6863 assert_panel_unlocked(dev_priv, pipe);
6865 dpll = I915_READ(dpll_reg);
6866 dpll |= DISPLAY_RATE_SELECT_FPA1;
6867 I915_WRITE(dpll_reg, dpll);
6868 intel_wait_for_vblank(dev, pipe);
6869 dpll = I915_READ(dpll_reg);
6870 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6871 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6876 void intel_mark_busy(struct drm_device *dev)
6878 i915_update_gfx_val(dev->dev_private);
6881 void intel_mark_idle(struct drm_device *dev)
6883 struct drm_crtc *crtc;
6885 if (!i915_powersave)
6888 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6892 intel_decrease_pllclock(crtc);
6896 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6898 struct drm_device *dev = obj->base.dev;
6899 struct drm_crtc *crtc;
6901 if (!i915_powersave)
6904 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6908 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6909 intel_increase_pllclock(crtc);
6913 static void intel_crtc_destroy(struct drm_crtc *crtc)
6915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916 struct drm_device *dev = crtc->dev;
6917 struct intel_unpin_work *work;
6918 unsigned long flags;
6920 spin_lock_irqsave(&dev->event_lock, flags);
6921 work = intel_crtc->unpin_work;
6922 intel_crtc->unpin_work = NULL;
6923 spin_unlock_irqrestore(&dev->event_lock, flags);
6926 cancel_work_sync(&work->work);
6930 drm_crtc_cleanup(crtc);
6935 static void intel_unpin_work_fn(struct work_struct *__work)
6937 struct intel_unpin_work *work =
6938 container_of(__work, struct intel_unpin_work, work);
6939 struct drm_device *dev = work->crtc->dev;
6941 mutex_lock(&dev->struct_mutex);
6942 intel_unpin_fb_obj(work->old_fb_obj);
6943 drm_gem_object_unreference(&work->pending_flip_obj->base);
6944 drm_gem_object_unreference(&work->old_fb_obj->base);
6946 intel_update_fbc(dev);
6947 mutex_unlock(&dev->struct_mutex);
6949 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6950 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6955 static void do_intel_finish_page_flip(struct drm_device *dev,
6956 struct drm_crtc *crtc)
6958 drm_i915_private_t *dev_priv = dev->dev_private;
6959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6960 struct intel_unpin_work *work;
6961 unsigned long flags;
6963 /* Ignore early vblank irqs */
6964 if (intel_crtc == NULL)
6967 spin_lock_irqsave(&dev->event_lock, flags);
6968 work = intel_crtc->unpin_work;
6970 /* Ensure we don't miss a work->pending update ... */
6973 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6974 spin_unlock_irqrestore(&dev->event_lock, flags);
6978 /* and that the unpin work is consistent wrt ->pending. */
6981 intel_crtc->unpin_work = NULL;
6984 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6986 drm_vblank_put(dev, intel_crtc->pipe);
6988 spin_unlock_irqrestore(&dev->event_lock, flags);
6990 wake_up_all(&dev_priv->pending_flip_queue);
6992 queue_work(dev_priv->wq, &work->work);
6994 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6997 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6999 drm_i915_private_t *dev_priv = dev->dev_private;
7000 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7002 do_intel_finish_page_flip(dev, crtc);
7005 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7007 drm_i915_private_t *dev_priv = dev->dev_private;
7008 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7010 do_intel_finish_page_flip(dev, crtc);
7013 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7015 drm_i915_private_t *dev_priv = dev->dev_private;
7016 struct intel_crtc *intel_crtc =
7017 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7018 unsigned long flags;
7020 /* NB: An MMIO update of the plane base pointer will also
7021 * generate a page-flip completion irq, i.e. every modeset
7022 * is also accompanied by a spurious intel_prepare_page_flip().
7024 spin_lock_irqsave(&dev->event_lock, flags);
7025 if (intel_crtc->unpin_work)
7026 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7027 spin_unlock_irqrestore(&dev->event_lock, flags);
7030 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7032 /* Ensure that the work item is consistent when activating it ... */
7034 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7035 /* and that it is marked active as soon as the irq could fire. */
7039 static int intel_gen2_queue_flip(struct drm_device *dev,
7040 struct drm_crtc *crtc,
7041 struct drm_framebuffer *fb,
7042 struct drm_i915_gem_object *obj)
7044 struct drm_i915_private *dev_priv = dev->dev_private;
7045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7050 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7054 ret = intel_ring_begin(ring, 6);
7058 /* Can't queue multiple flips, so wait for the previous
7059 * one to finish before executing the next.
7061 if (intel_crtc->plane)
7062 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7064 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7065 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7066 intel_ring_emit(ring, MI_NOOP);
7067 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7068 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7069 intel_ring_emit(ring, fb->pitches[0]);
7070 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7071 intel_ring_emit(ring, 0); /* aux display base address, unused */
7073 intel_mark_page_flip_active(intel_crtc);
7074 intel_ring_advance(ring);
7078 intel_unpin_fb_obj(obj);
7083 static int intel_gen3_queue_flip(struct drm_device *dev,
7084 struct drm_crtc *crtc,
7085 struct drm_framebuffer *fb,
7086 struct drm_i915_gem_object *obj)
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7094 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7098 ret = intel_ring_begin(ring, 6);
7102 if (intel_crtc->plane)
7103 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7105 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7106 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7107 intel_ring_emit(ring, MI_NOOP);
7108 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7110 intel_ring_emit(ring, fb->pitches[0]);
7111 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7112 intel_ring_emit(ring, MI_NOOP);
7114 intel_mark_page_flip_active(intel_crtc);
7115 intel_ring_advance(ring);
7119 intel_unpin_fb_obj(obj);
7124 static int intel_gen4_queue_flip(struct drm_device *dev,
7125 struct drm_crtc *crtc,
7126 struct drm_framebuffer *fb,
7127 struct drm_i915_gem_object *obj)
7129 struct drm_i915_private *dev_priv = dev->dev_private;
7130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7131 uint32_t pf, pipesrc;
7132 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7135 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7139 ret = intel_ring_begin(ring, 4);
7143 /* i965+ uses the linear or tiled offsets from the
7144 * Display Registers (which do not change across a page-flip)
7145 * so we need only reprogram the base address.
7147 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7148 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7149 intel_ring_emit(ring, fb->pitches[0]);
7150 intel_ring_emit(ring,
7151 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7154 /* XXX Enabling the panel-fitter across page-flip is so far
7155 * untested on non-native modes, so ignore it for now.
7156 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7159 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7160 intel_ring_emit(ring, pf | pipesrc);
7162 intel_mark_page_flip_active(intel_crtc);
7163 intel_ring_advance(ring);
7167 intel_unpin_fb_obj(obj);
7172 static int intel_gen6_queue_flip(struct drm_device *dev,
7173 struct drm_crtc *crtc,
7174 struct drm_framebuffer *fb,
7175 struct drm_i915_gem_object *obj)
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7180 uint32_t pf, pipesrc;
7183 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 ret = intel_ring_begin(ring, 4);
7191 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7192 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7193 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7194 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7196 /* Contrary to the suggestions in the documentation,
7197 * "Enable Panel Fitter" does not seem to be required when page
7198 * flipping with a non-native mode, and worse causes a normal
7200 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7203 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7204 intel_ring_emit(ring, pf | pipesrc);
7206 intel_mark_page_flip_active(intel_crtc);
7207 intel_ring_advance(ring);
7211 intel_unpin_fb_obj(obj);
7217 * On gen7 we currently use the blit ring because (in early silicon at least)
7218 * the render ring doesn't give us interrpts for page flip completion, which
7219 * means clients will hang after the first flip is queued. Fortunately the
7220 * blit ring generates interrupts properly, so use it instead.
7222 static int intel_gen7_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7229 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7230 uint32_t plane_bit = 0;
7233 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7237 switch(intel_crtc->plane) {
7239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7242 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7245 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7248 WARN_ONCE(1, "unknown plane in flip command\n");
7253 ret = intel_ring_begin(ring, 4);
7257 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7258 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7259 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7260 intel_ring_emit(ring, (MI_NOOP));
7262 intel_mark_page_flip_active(intel_crtc);
7263 intel_ring_advance(ring);
7267 intel_unpin_fb_obj(obj);
7272 static int intel_default_queue_flip(struct drm_device *dev,
7273 struct drm_crtc *crtc,
7274 struct drm_framebuffer *fb,
7275 struct drm_i915_gem_object *obj)
7280 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7281 struct drm_framebuffer *fb,
7282 struct drm_pending_vblank_event *event)
7284 struct drm_device *dev = crtc->dev;
7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 struct intel_framebuffer *intel_fb;
7287 struct drm_i915_gem_object *obj;
7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7289 struct intel_unpin_work *work;
7290 unsigned long flags;
7293 /* Can't change pixel format via MI display flips. */
7294 if (fb->pixel_format != crtc->fb->pixel_format)
7298 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7299 * Note that pitch changes could also affect these register.
7301 if (INTEL_INFO(dev)->gen > 3 &&
7302 (fb->offsets[0] != crtc->fb->offsets[0] ||
7303 fb->pitches[0] != crtc->fb->pitches[0]))
7306 work = kzalloc(sizeof *work, GFP_KERNEL);
7310 work->event = event;
7312 intel_fb = to_intel_framebuffer(crtc->fb);
7313 work->old_fb_obj = intel_fb->obj;
7314 INIT_WORK(&work->work, intel_unpin_work_fn);
7316 ret = drm_vblank_get(dev, intel_crtc->pipe);
7320 /* We borrow the event spin lock for protecting unpin_work */
7321 spin_lock_irqsave(&dev->event_lock, flags);
7322 if (intel_crtc->unpin_work) {
7323 spin_unlock_irqrestore(&dev->event_lock, flags);
7325 drm_vblank_put(dev, intel_crtc->pipe);
7327 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7330 intel_crtc->unpin_work = work;
7331 spin_unlock_irqrestore(&dev->event_lock, flags);
7333 intel_fb = to_intel_framebuffer(fb);
7334 obj = intel_fb->obj;
7336 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7337 flush_workqueue(dev_priv->wq);
7339 ret = i915_mutex_lock_interruptible(dev);
7343 /* Reference the objects for the scheduled work. */
7344 drm_gem_object_reference(&work->old_fb_obj->base);
7345 drm_gem_object_reference(&obj->base);
7349 work->pending_flip_obj = obj;
7351 work->enable_stall_check = true;
7353 atomic_inc(&intel_crtc->unpin_work_count);
7354 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7356 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7358 goto cleanup_pending;
7360 intel_disable_fbc(dev);
7361 intel_mark_fb_busy(obj);
7362 mutex_unlock(&dev->struct_mutex);
7364 trace_i915_flip_request(intel_crtc->plane, obj);
7369 atomic_dec(&intel_crtc->unpin_work_count);
7370 drm_gem_object_unreference(&work->old_fb_obj->base);
7371 drm_gem_object_unreference(&obj->base);
7372 mutex_unlock(&dev->struct_mutex);
7375 spin_lock_irqsave(&dev->event_lock, flags);
7376 intel_crtc->unpin_work = NULL;
7377 spin_unlock_irqrestore(&dev->event_lock, flags);
7379 drm_vblank_put(dev, intel_crtc->pipe);
7386 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7387 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7388 .load_lut = intel_crtc_load_lut,
7389 .disable = intel_crtc_noop,
7392 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7394 struct intel_encoder *other_encoder;
7395 struct drm_crtc *crtc = &encoder->new_crtc->base;
7400 list_for_each_entry(other_encoder,
7401 &crtc->dev->mode_config.encoder_list,
7404 if (&other_encoder->new_crtc->base != crtc ||
7405 encoder == other_encoder)
7414 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7415 struct drm_crtc *crtc)
7417 struct drm_device *dev;
7418 struct drm_crtc *tmp;
7421 WARN(!crtc, "checking null crtc?\n");
7425 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7431 if (encoder->possible_crtcs & crtc_mask)
7437 * intel_modeset_update_staged_output_state
7439 * Updates the staged output configuration state, e.g. after we've read out the
7442 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7444 struct intel_encoder *encoder;
7445 struct intel_connector *connector;
7447 list_for_each_entry(connector, &dev->mode_config.connector_list,
7449 connector->new_encoder =
7450 to_intel_encoder(connector->base.encoder);
7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7456 to_intel_crtc(encoder->base.crtc);
7461 * intel_modeset_commit_output_state
7463 * This function copies the stage display pipe configuration to the real one.
7465 static void intel_modeset_commit_output_state(struct drm_device *dev)
7467 struct intel_encoder *encoder;
7468 struct intel_connector *connector;
7470 list_for_each_entry(connector, &dev->mode_config.connector_list,
7472 connector->base.encoder = &connector->new_encoder->base;
7475 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7477 encoder->base.crtc = &encoder->new_crtc->base;
7481 static struct drm_display_mode *
7482 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7483 struct drm_display_mode *mode)
7485 struct drm_device *dev = crtc->dev;
7486 struct drm_display_mode *adjusted_mode;
7487 struct drm_encoder_helper_funcs *encoder_funcs;
7488 struct intel_encoder *encoder;
7490 adjusted_mode = drm_mode_duplicate(dev, mode);
7492 return ERR_PTR(-ENOMEM);
7494 /* Pass our mode to the connectors and the CRTC to give them a chance to
7495 * adjust it according to limitations or connector properties, and also
7496 * a chance to reject the mode entirely.
7498 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7501 if (&encoder->new_crtc->base != crtc)
7503 encoder_funcs = encoder->base.helper_private;
7504 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7506 DRM_DEBUG_KMS("Encoder fixup failed\n");
7511 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7512 DRM_DEBUG_KMS("CRTC fixup failed\n");
7515 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7517 return adjusted_mode;
7519 drm_mode_destroy(dev, adjusted_mode);
7520 return ERR_PTR(-EINVAL);
7523 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7524 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7526 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7527 unsigned *prepare_pipes, unsigned *disable_pipes)
7529 struct intel_crtc *intel_crtc;
7530 struct drm_device *dev = crtc->dev;
7531 struct intel_encoder *encoder;
7532 struct intel_connector *connector;
7533 struct drm_crtc *tmp_crtc;
7535 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7537 /* Check which crtcs have changed outputs connected to them, these need
7538 * to be part of the prepare_pipes mask. We don't (yet) support global
7539 * modeset across multiple crtcs, so modeset_pipes will only have one
7540 * bit set at most. */
7541 list_for_each_entry(connector, &dev->mode_config.connector_list,
7543 if (connector->base.encoder == &connector->new_encoder->base)
7546 if (connector->base.encoder) {
7547 tmp_crtc = connector->base.encoder->crtc;
7549 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7552 if (connector->new_encoder)
7554 1 << connector->new_encoder->new_crtc->pipe;
7557 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7559 if (encoder->base.crtc == &encoder->new_crtc->base)
7562 if (encoder->base.crtc) {
7563 tmp_crtc = encoder->base.crtc;
7565 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7568 if (encoder->new_crtc)
7569 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7572 /* Check for any pipes that will be fully disabled ... */
7573 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7577 /* Don't try to disable disabled crtcs. */
7578 if (!intel_crtc->base.enabled)
7581 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7583 if (encoder->new_crtc == intel_crtc)
7588 *disable_pipes |= 1 << intel_crtc->pipe;
7592 /* set_mode is also used to update properties on life display pipes. */
7593 intel_crtc = to_intel_crtc(crtc);
7595 *prepare_pipes |= 1 << intel_crtc->pipe;
7597 /* We only support modeset on one single crtc, hence we need to do that
7598 * only for the passed in crtc iff we change anything else than just
7601 * This is actually not true, to be fully compatible with the old crtc
7602 * helper we automatically disable _any_ output (i.e. doesn't need to be
7603 * connected to the crtc we're modesetting on) if it's disconnected.
7604 * Which is a rather nutty api (since changed the output configuration
7605 * without userspace's explicit request can lead to confusion), but
7606 * alas. Hence we currently need to modeset on all pipes we prepare. */
7608 *modeset_pipes = *prepare_pipes;
7610 /* ... and mask these out. */
7611 *modeset_pipes &= ~(*disable_pipes);
7612 *prepare_pipes &= ~(*disable_pipes);
7615 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7617 struct drm_encoder *encoder;
7618 struct drm_device *dev = crtc->dev;
7620 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7621 if (encoder->crtc == crtc)
7628 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7630 struct intel_encoder *intel_encoder;
7631 struct intel_crtc *intel_crtc;
7632 struct drm_connector *connector;
7634 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7636 if (!intel_encoder->base.crtc)
7639 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7641 if (prepare_pipes & (1 << intel_crtc->pipe))
7642 intel_encoder->connectors_active = false;
7645 intel_modeset_commit_output_state(dev);
7647 /* Update computed state. */
7648 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7650 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7653 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7654 if (!connector->encoder || !connector->encoder->crtc)
7657 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7659 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7660 struct drm_property *dpms_property =
7661 dev->mode_config.dpms_property;
7663 connector->dpms = DRM_MODE_DPMS_ON;
7664 drm_object_property_set_value(&connector->base,
7668 intel_encoder = to_intel_encoder(connector->encoder);
7669 intel_encoder->connectors_active = true;
7675 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7676 list_for_each_entry((intel_crtc), \
7677 &(dev)->mode_config.crtc_list, \
7679 if (mask & (1 <<(intel_crtc)->pipe)) \
7682 intel_modeset_check_state(struct drm_device *dev)
7684 struct intel_crtc *crtc;
7685 struct intel_encoder *encoder;
7686 struct intel_connector *connector;
7688 list_for_each_entry(connector, &dev->mode_config.connector_list,
7690 /* This also checks the encoder/connector hw state with the
7691 * ->get_hw_state callbacks. */
7692 intel_connector_check_state(connector);
7694 WARN(&connector->new_encoder->base != connector->base.encoder,
7695 "connector's staged encoder doesn't match current encoder\n");
7698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700 bool enabled = false;
7701 bool active = false;
7702 enum pipe pipe, tracked_pipe;
7704 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7705 encoder->base.base.id,
7706 drm_get_encoder_name(&encoder->base));
7708 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7709 "encoder's stage crtc doesn't match current crtc\n");
7710 WARN(encoder->connectors_active && !encoder->base.crtc,
7711 "encoder's active_connectors set, but no crtc\n");
7713 list_for_each_entry(connector, &dev->mode_config.connector_list,
7715 if (connector->base.encoder != &encoder->base)
7718 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7721 WARN(!!encoder->base.crtc != enabled,
7722 "encoder's enabled state mismatch "
7723 "(expected %i, found %i)\n",
7724 !!encoder->base.crtc, enabled);
7725 WARN(active && !encoder->base.crtc,
7726 "active encoder with no crtc\n");
7728 WARN(encoder->connectors_active != active,
7729 "encoder's computed active state doesn't match tracked active state "
7730 "(expected %i, found %i)\n", active, encoder->connectors_active);
7732 active = encoder->get_hw_state(encoder, &pipe);
7733 WARN(active != encoder->connectors_active,
7734 "encoder's hw state doesn't match sw tracking "
7735 "(expected %i, found %i)\n",
7736 encoder->connectors_active, active);
7738 if (!encoder->base.crtc)
7741 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7742 WARN(active && pipe != tracked_pipe,
7743 "active encoder's pipe doesn't match"
7744 "(expected %i, found %i)\n",
7745 tracked_pipe, pipe);
7749 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7751 bool enabled = false;
7752 bool active = false;
7754 DRM_DEBUG_KMS("[CRTC:%d]\n",
7755 crtc->base.base.id);
7757 WARN(crtc->active && !crtc->base.enabled,
7758 "active crtc, but not enabled in sw tracking\n");
7760 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7762 if (encoder->base.crtc != &crtc->base)
7765 if (encoder->connectors_active)
7768 WARN(active != crtc->active,
7769 "crtc's computed active state doesn't match tracked active state "
7770 "(expected %i, found %i)\n", active, crtc->active);
7771 WARN(enabled != crtc->base.enabled,
7772 "crtc's computed enabled state doesn't match tracked enabled state "
7773 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7775 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7779 int intel_set_mode(struct drm_crtc *crtc,
7780 struct drm_display_mode *mode,
7781 int x, int y, struct drm_framebuffer *fb)
7783 struct drm_device *dev = crtc->dev;
7784 drm_i915_private_t *dev_priv = dev->dev_private;
7785 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7786 struct intel_crtc *intel_crtc;
7787 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7790 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7793 saved_hwmode = saved_mode + 1;
7795 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7796 &prepare_pipes, &disable_pipes);
7798 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7799 modeset_pipes, prepare_pipes, disable_pipes);
7801 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7802 intel_crtc_disable(&intel_crtc->base);
7804 *saved_hwmode = crtc->hwmode;
7805 *saved_mode = crtc->mode;
7807 /* Hack: Because we don't (yet) support global modeset on multiple
7808 * crtcs, we don't keep track of the new mode for more than one crtc.
7809 * Hence simply check whether any bit is set in modeset_pipes in all the
7810 * pieces of code that are not yet converted to deal with mutliple crtcs
7811 * changing their mode at the same time. */
7812 adjusted_mode = NULL;
7813 if (modeset_pipes) {
7814 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7815 if (IS_ERR(adjusted_mode)) {
7816 ret = PTR_ERR(adjusted_mode);
7821 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7822 if (intel_crtc->base.enabled)
7823 dev_priv->display.crtc_disable(&intel_crtc->base);
7826 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7827 * to set it here already despite that we pass it down the callchain.
7832 /* Only after disabling all output pipelines that will be changed can we
7833 * update the the output configuration. */
7834 intel_modeset_update_state(dev, prepare_pipes);
7836 if (dev_priv->display.modeset_global_resources)
7837 dev_priv->display.modeset_global_resources(dev);
7839 /* Set up the DPLL and any encoders state that needs to adjust or depend
7842 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7843 ret = intel_crtc_mode_set(&intel_crtc->base,
7844 mode, adjusted_mode,
7850 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7851 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7852 dev_priv->display.crtc_enable(&intel_crtc->base);
7854 if (modeset_pipes) {
7855 /* Store real post-adjustment hardware mode. */
7856 crtc->hwmode = *adjusted_mode;
7858 /* Calculate and store various constants which
7859 * are later needed by vblank and swap-completion
7860 * timestamping. They are derived from true hwmode.
7862 drm_calc_timestamping_constants(crtc);
7865 /* FIXME: add subpixel order */
7867 drm_mode_destroy(dev, adjusted_mode);
7868 if (ret && crtc->enabled) {
7869 crtc->hwmode = *saved_hwmode;
7870 crtc->mode = *saved_mode;
7872 intel_modeset_check_state(dev);
7880 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7882 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7885 #undef for_each_intel_crtc_masked
7887 static void intel_set_config_free(struct intel_set_config *config)
7892 kfree(config->save_connector_encoders);
7893 kfree(config->save_encoder_crtcs);
7897 static int intel_set_config_save_state(struct drm_device *dev,
7898 struct intel_set_config *config)
7900 struct drm_encoder *encoder;
7901 struct drm_connector *connector;
7904 config->save_encoder_crtcs =
7905 kcalloc(dev->mode_config.num_encoder,
7906 sizeof(struct drm_crtc *), GFP_KERNEL);
7907 if (!config->save_encoder_crtcs)
7910 config->save_connector_encoders =
7911 kcalloc(dev->mode_config.num_connector,
7912 sizeof(struct drm_encoder *), GFP_KERNEL);
7913 if (!config->save_connector_encoders)
7916 /* Copy data. Note that driver private data is not affected.
7917 * Should anything bad happen only the expected state is
7918 * restored, not the drivers personal bookkeeping.
7921 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7922 config->save_encoder_crtcs[count++] = encoder->crtc;
7926 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7927 config->save_connector_encoders[count++] = connector->encoder;
7933 static void intel_set_config_restore_state(struct drm_device *dev,
7934 struct intel_set_config *config)
7936 struct intel_encoder *encoder;
7937 struct intel_connector *connector;
7941 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7943 to_intel_crtc(config->save_encoder_crtcs[count++]);
7947 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7948 connector->new_encoder =
7949 to_intel_encoder(config->save_connector_encoders[count++]);
7954 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7955 struct intel_set_config *config)
7958 /* We should be able to check here if the fb has the same properties
7959 * and then just flip_or_move it */
7960 if (set->crtc->fb != set->fb) {
7961 /* If we have no fb then treat it as a full mode set */
7962 if (set->crtc->fb == NULL) {
7963 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7964 config->mode_changed = true;
7965 } else if (set->fb == NULL) {
7966 config->mode_changed = true;
7967 } else if (set->fb->depth != set->crtc->fb->depth) {
7968 config->mode_changed = true;
7969 } else if (set->fb->bits_per_pixel !=
7970 set->crtc->fb->bits_per_pixel) {
7971 config->mode_changed = true;
7973 config->fb_changed = true;
7976 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7977 config->fb_changed = true;
7979 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7980 DRM_DEBUG_KMS("modes are different, full mode set\n");
7981 drm_mode_debug_printmodeline(&set->crtc->mode);
7982 drm_mode_debug_printmodeline(set->mode);
7983 config->mode_changed = true;
7988 intel_modeset_stage_output_state(struct drm_device *dev,
7989 struct drm_mode_set *set,
7990 struct intel_set_config *config)
7992 struct drm_crtc *new_crtc;
7993 struct intel_connector *connector;
7994 struct intel_encoder *encoder;
7997 /* The upper layers ensure that we either disable a crtc or have a list
7998 * of connectors. For paranoia, double-check this. */
7999 WARN_ON(!set->fb && (set->num_connectors != 0));
8000 WARN_ON(set->fb && (set->num_connectors == 0));
8003 list_for_each_entry(connector, &dev->mode_config.connector_list,
8005 /* Otherwise traverse passed in connector list and get encoders
8007 for (ro = 0; ro < set->num_connectors; ro++) {
8008 if (set->connectors[ro] == &connector->base) {
8009 connector->new_encoder = connector->encoder;
8014 /* If we disable the crtc, disable all its connectors. Also, if
8015 * the connector is on the changing crtc but not on the new
8016 * connector list, disable it. */
8017 if ((!set->fb || ro == set->num_connectors) &&
8018 connector->base.encoder &&
8019 connector->base.encoder->crtc == set->crtc) {
8020 connector->new_encoder = NULL;
8022 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8023 connector->base.base.id,
8024 drm_get_connector_name(&connector->base));
8028 if (&connector->new_encoder->base != connector->base.encoder) {
8029 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8030 config->mode_changed = true;
8033 /* connector->new_encoder is now updated for all connectors. */
8035 /* Update crtc of enabled connectors. */
8037 list_for_each_entry(connector, &dev->mode_config.connector_list,
8039 if (!connector->new_encoder)
8042 new_crtc = connector->new_encoder->base.crtc;
8044 for (ro = 0; ro < set->num_connectors; ro++) {
8045 if (set->connectors[ro] == &connector->base)
8046 new_crtc = set->crtc;
8049 /* Make sure the new CRTC will work with the encoder */
8050 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8054 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8056 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8057 connector->base.base.id,
8058 drm_get_connector_name(&connector->base),
8062 /* Check for any encoders that needs to be disabled. */
8063 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8065 list_for_each_entry(connector,
8066 &dev->mode_config.connector_list,
8068 if (connector->new_encoder == encoder) {
8069 WARN_ON(!connector->new_encoder->new_crtc);
8074 encoder->new_crtc = NULL;
8076 /* Only now check for crtc changes so we don't miss encoders
8077 * that will be disabled. */
8078 if (&encoder->new_crtc->base != encoder->base.crtc) {
8079 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8080 config->mode_changed = true;
8083 /* Now we've also updated encoder->new_crtc for all encoders. */
8088 static int intel_crtc_set_config(struct drm_mode_set *set)
8090 struct drm_device *dev;
8091 struct drm_mode_set save_set;
8092 struct intel_set_config *config;
8097 BUG_ON(!set->crtc->helper_private);
8102 /* The fb helper likes to play gross jokes with ->mode_set_config.
8103 * Unfortunately the crtc helper doesn't do much at all for this case,
8104 * so we have to cope with this madness until the fb helper is fixed up. */
8105 if (set->fb && set->num_connectors == 0)
8109 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8110 set->crtc->base.id, set->fb->base.id,
8111 (int)set->num_connectors, set->x, set->y);
8113 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8116 dev = set->crtc->dev;
8119 config = kzalloc(sizeof(*config), GFP_KERNEL);
8123 ret = intel_set_config_save_state(dev, config);
8127 save_set.crtc = set->crtc;
8128 save_set.mode = &set->crtc->mode;
8129 save_set.x = set->crtc->x;
8130 save_set.y = set->crtc->y;
8131 save_set.fb = set->crtc->fb;
8133 /* Compute whether we need a full modeset, only an fb base update or no
8134 * change at all. In the future we might also check whether only the
8135 * mode changed, e.g. for LVDS where we only change the panel fitter in
8137 intel_set_config_compute_mode_changes(set, config);
8139 ret = intel_modeset_stage_output_state(dev, set, config);
8143 if (config->mode_changed) {
8145 DRM_DEBUG_KMS("attempting to set mode from"
8147 drm_mode_debug_printmodeline(set->mode);
8150 ret = intel_set_mode(set->crtc, set->mode,
8151 set->x, set->y, set->fb);
8153 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8154 set->crtc->base.id, ret);
8157 } else if (config->fb_changed) {
8158 intel_crtc_wait_for_pending_flips(set->crtc);
8160 ret = intel_pipe_set_base(set->crtc,
8161 set->x, set->y, set->fb);
8164 intel_set_config_free(config);
8169 intel_set_config_restore_state(dev, config);
8171 /* Try to restore the config */
8172 if (config->mode_changed &&
8173 intel_set_mode(save_set.crtc, save_set.mode,
8174 save_set.x, save_set.y, save_set.fb))
8175 DRM_ERROR("failed to restore config after modeset failure\n");
8178 intel_set_config_free(config);
8182 static const struct drm_crtc_funcs intel_crtc_funcs = {
8183 .cursor_set = intel_crtc_cursor_set,
8184 .cursor_move = intel_crtc_cursor_move,
8185 .gamma_set = intel_crtc_gamma_set,
8186 .set_config = intel_crtc_set_config,
8187 .destroy = intel_crtc_destroy,
8188 .page_flip = intel_crtc_page_flip,
8191 static void intel_cpu_pll_init(struct drm_device *dev)
8194 intel_ddi_pll_init(dev);
8197 static void intel_pch_pll_init(struct drm_device *dev)
8199 drm_i915_private_t *dev_priv = dev->dev_private;
8202 if (dev_priv->num_pch_pll == 0) {
8203 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8207 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8208 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8209 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8210 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8214 static void intel_crtc_init(struct drm_device *dev, int pipe)
8216 drm_i915_private_t *dev_priv = dev->dev_private;
8217 struct intel_crtc *intel_crtc;
8220 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8221 if (intel_crtc == NULL)
8224 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8226 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8227 for (i = 0; i < 256; i++) {
8228 intel_crtc->lut_r[i] = i;
8229 intel_crtc->lut_g[i] = i;
8230 intel_crtc->lut_b[i] = i;
8233 /* Swap pipes & planes for FBC on pre-965 */
8234 intel_crtc->pipe = pipe;
8235 intel_crtc->plane = pipe;
8236 intel_crtc->cpu_transcoder = pipe;
8237 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8238 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8239 intel_crtc->plane = !pipe;
8242 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8243 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8244 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8245 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8247 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8249 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8252 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8253 struct drm_file *file)
8255 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8256 struct drm_mode_object *drmmode_obj;
8257 struct intel_crtc *crtc;
8259 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8262 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8263 DRM_MODE_OBJECT_CRTC);
8266 DRM_ERROR("no such CRTC id\n");
8270 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8271 pipe_from_crtc_id->pipe = crtc->pipe;
8276 static int intel_encoder_clones(struct intel_encoder *encoder)
8278 struct drm_device *dev = encoder->base.dev;
8279 struct intel_encoder *source_encoder;
8283 list_for_each_entry(source_encoder,
8284 &dev->mode_config.encoder_list, base.head) {
8286 if (encoder == source_encoder)
8287 index_mask |= (1 << entry);
8289 /* Intel hw has only one MUX where enocoders could be cloned. */
8290 if (encoder->cloneable && source_encoder->cloneable)
8291 index_mask |= (1 << entry);
8299 static bool has_edp_a(struct drm_device *dev)
8301 struct drm_i915_private *dev_priv = dev->dev_private;
8303 if (!IS_MOBILE(dev))
8306 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8310 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8316 static void intel_setup_outputs(struct drm_device *dev)
8318 struct drm_i915_private *dev_priv = dev->dev_private;
8319 struct intel_encoder *encoder;
8320 bool dpd_is_edp = false;
8323 has_lvds = intel_lvds_init(dev);
8324 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8325 /* disable the panel fitter on everything but LVDS */
8326 I915_WRITE(PFIT_CONTROL, 0);
8329 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8330 intel_crt_init(dev);
8335 /* Haswell uses DDI functions to detect digital outputs */
8336 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8337 /* DDI A only supports eDP */
8339 intel_ddi_init(dev, PORT_A);
8341 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8343 found = I915_READ(SFUSE_STRAP);
8345 if (found & SFUSE_STRAP_DDIB_DETECTED)
8346 intel_ddi_init(dev, PORT_B);
8347 if (found & SFUSE_STRAP_DDIC_DETECTED)
8348 intel_ddi_init(dev, PORT_C);
8349 if (found & SFUSE_STRAP_DDID_DETECTED)
8350 intel_ddi_init(dev, PORT_D);
8351 } else if (HAS_PCH_SPLIT(dev)) {
8353 dpd_is_edp = intel_dpd_is_edp(dev);
8356 intel_dp_init(dev, DP_A, PORT_A);
8358 if (I915_READ(HDMIB) & PORT_DETECTED) {
8359 /* PCH SDVOB multiplex with HDMIB */
8360 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8362 intel_hdmi_init(dev, HDMIB, PORT_B);
8363 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8364 intel_dp_init(dev, PCH_DP_B, PORT_B);
8367 if (I915_READ(HDMIC) & PORT_DETECTED)
8368 intel_hdmi_init(dev, HDMIC, PORT_C);
8370 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8371 intel_hdmi_init(dev, HDMID, PORT_D);
8373 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8374 intel_dp_init(dev, PCH_DP_C, PORT_C);
8376 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8377 intel_dp_init(dev, PCH_DP_D, PORT_D);
8378 } else if (IS_VALLEYVIEW(dev)) {
8379 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8380 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8381 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8383 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8384 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8385 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8386 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8389 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8390 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8392 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8395 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8396 DRM_DEBUG_KMS("probing SDVOB\n");
8397 found = intel_sdvo_init(dev, SDVOB, true);
8398 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8399 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8400 intel_hdmi_init(dev, SDVOB, PORT_B);
8403 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8404 DRM_DEBUG_KMS("probing DP_B\n");
8405 intel_dp_init(dev, DP_B, PORT_B);
8409 /* Before G4X SDVOC doesn't have its own detect register */
8411 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8412 DRM_DEBUG_KMS("probing SDVOC\n");
8413 found = intel_sdvo_init(dev, SDVOC, false);
8416 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8418 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8419 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8420 intel_hdmi_init(dev, SDVOC, PORT_C);
8422 if (SUPPORTS_INTEGRATED_DP(dev)) {
8423 DRM_DEBUG_KMS("probing DP_C\n");
8424 intel_dp_init(dev, DP_C, PORT_C);
8428 if (SUPPORTS_INTEGRATED_DP(dev) &&
8429 (I915_READ(DP_D) & DP_DETECTED)) {
8430 DRM_DEBUG_KMS("probing DP_D\n");
8431 intel_dp_init(dev, DP_D, PORT_D);
8433 } else if (IS_GEN2(dev))
8434 intel_dvo_init(dev);
8436 if (SUPPORTS_TV(dev))
8439 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8440 encoder->base.possible_crtcs = encoder->crtc_mask;
8441 encoder->base.possible_clones =
8442 intel_encoder_clones(encoder);
8445 intel_init_pch_refclk(dev);
8447 drm_helper_move_panel_connectors_to_head(dev);
8450 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8452 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8454 drm_framebuffer_cleanup(fb);
8455 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8460 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8461 struct drm_file *file,
8462 unsigned int *handle)
8464 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8465 struct drm_i915_gem_object *obj = intel_fb->obj;
8467 return drm_gem_handle_create(file, &obj->base, handle);
8470 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8471 .destroy = intel_user_framebuffer_destroy,
8472 .create_handle = intel_user_framebuffer_create_handle,
8475 int intel_framebuffer_init(struct drm_device *dev,
8476 struct intel_framebuffer *intel_fb,
8477 struct drm_mode_fb_cmd2 *mode_cmd,
8478 struct drm_i915_gem_object *obj)
8482 if (obj->tiling_mode == I915_TILING_Y) {
8483 DRM_DEBUG("hardware does not support tiling Y\n");
8487 if (mode_cmd->pitches[0] & 63) {
8488 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8489 mode_cmd->pitches[0]);
8493 /* FIXME <= Gen4 stride limits are bit unclear */
8494 if (mode_cmd->pitches[0] > 32768) {
8495 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8496 mode_cmd->pitches[0]);
8500 if (obj->tiling_mode != I915_TILING_NONE &&
8501 mode_cmd->pitches[0] != obj->stride) {
8502 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8503 mode_cmd->pitches[0], obj->stride);
8507 /* Reject formats not supported by any plane early. */
8508 switch (mode_cmd->pixel_format) {
8510 case DRM_FORMAT_RGB565:
8511 case DRM_FORMAT_XRGB8888:
8512 case DRM_FORMAT_ARGB8888:
8514 case DRM_FORMAT_XRGB1555:
8515 case DRM_FORMAT_ARGB1555:
8516 if (INTEL_INFO(dev)->gen > 3) {
8517 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8521 case DRM_FORMAT_XBGR8888:
8522 case DRM_FORMAT_ABGR8888:
8523 case DRM_FORMAT_XRGB2101010:
8524 case DRM_FORMAT_ARGB2101010:
8525 case DRM_FORMAT_XBGR2101010:
8526 case DRM_FORMAT_ABGR2101010:
8527 if (INTEL_INFO(dev)->gen < 4) {
8528 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8532 case DRM_FORMAT_YUYV:
8533 case DRM_FORMAT_UYVY:
8534 case DRM_FORMAT_YVYU:
8535 case DRM_FORMAT_VYUY:
8536 if (INTEL_INFO(dev)->gen < 5) {
8537 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8542 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8546 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8547 if (mode_cmd->offsets[0] != 0)
8550 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8551 intel_fb->obj = obj;
8553 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8555 DRM_ERROR("framebuffer init failed %d\n", ret);
8562 static struct drm_framebuffer *
8563 intel_user_framebuffer_create(struct drm_device *dev,
8564 struct drm_file *filp,
8565 struct drm_mode_fb_cmd2 *mode_cmd)
8567 struct drm_i915_gem_object *obj;
8569 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8570 mode_cmd->handles[0]));
8571 if (&obj->base == NULL)
8572 return ERR_PTR(-ENOENT);
8574 return intel_framebuffer_create(dev, mode_cmd, obj);
8577 static const struct drm_mode_config_funcs intel_mode_funcs = {
8578 .fb_create = intel_user_framebuffer_create,
8579 .output_poll_changed = intel_fb_output_poll_changed,
8582 /* Set up chip specific display functions */
8583 static void intel_init_display(struct drm_device *dev)
8585 struct drm_i915_private *dev_priv = dev->dev_private;
8587 /* We always want a DPMS function */
8589 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8590 dev_priv->display.crtc_enable = haswell_crtc_enable;
8591 dev_priv->display.crtc_disable = haswell_crtc_disable;
8592 dev_priv->display.off = haswell_crtc_off;
8593 dev_priv->display.update_plane = ironlake_update_plane;
8594 } else if (HAS_PCH_SPLIT(dev)) {
8595 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8596 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8597 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8598 dev_priv->display.off = ironlake_crtc_off;
8599 dev_priv->display.update_plane = ironlake_update_plane;
8601 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8602 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8603 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8604 dev_priv->display.off = i9xx_crtc_off;
8605 dev_priv->display.update_plane = i9xx_update_plane;
8608 /* Returns the core display clock speed */
8609 if (IS_VALLEYVIEW(dev))
8610 dev_priv->display.get_display_clock_speed =
8611 valleyview_get_display_clock_speed;
8612 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8613 dev_priv->display.get_display_clock_speed =
8614 i945_get_display_clock_speed;
8615 else if (IS_I915G(dev))
8616 dev_priv->display.get_display_clock_speed =
8617 i915_get_display_clock_speed;
8618 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8619 dev_priv->display.get_display_clock_speed =
8620 i9xx_misc_get_display_clock_speed;
8621 else if (IS_I915GM(dev))
8622 dev_priv->display.get_display_clock_speed =
8623 i915gm_get_display_clock_speed;
8624 else if (IS_I865G(dev))
8625 dev_priv->display.get_display_clock_speed =
8626 i865_get_display_clock_speed;
8627 else if (IS_I85X(dev))
8628 dev_priv->display.get_display_clock_speed =
8629 i855_get_display_clock_speed;
8631 dev_priv->display.get_display_clock_speed =
8632 i830_get_display_clock_speed;
8634 if (HAS_PCH_SPLIT(dev)) {
8636 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8637 dev_priv->display.write_eld = ironlake_write_eld;
8638 } else if (IS_GEN6(dev)) {
8639 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8640 dev_priv->display.write_eld = ironlake_write_eld;
8641 } else if (IS_IVYBRIDGE(dev)) {
8642 /* FIXME: detect B0+ stepping and use auto training */
8643 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8644 dev_priv->display.write_eld = ironlake_write_eld;
8645 dev_priv->display.modeset_global_resources =
8646 ivb_modeset_global_resources;
8647 } else if (IS_HASWELL(dev)) {
8648 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8649 dev_priv->display.write_eld = haswell_write_eld;
8650 dev_priv->display.modeset_global_resources =
8651 haswell_modeset_global_resources;
8653 } else if (IS_G4X(dev)) {
8654 dev_priv->display.write_eld = g4x_write_eld;
8657 /* Default just returns -ENODEV to indicate unsupported */
8658 dev_priv->display.queue_flip = intel_default_queue_flip;
8660 switch (INTEL_INFO(dev)->gen) {
8662 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8666 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8671 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8675 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8678 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8684 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8685 * resume, or other times. This quirk makes sure that's the case for
8688 static void quirk_pipea_force(struct drm_device *dev)
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8692 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8693 DRM_INFO("applying pipe a force quirk\n");
8697 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8699 static void quirk_ssc_force_disable(struct drm_device *dev)
8701 struct drm_i915_private *dev_priv = dev->dev_private;
8702 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8703 DRM_INFO("applying lvds SSC disable quirk\n");
8707 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8710 static void quirk_invert_brightness(struct drm_device *dev)
8712 struct drm_i915_private *dev_priv = dev->dev_private;
8713 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8714 DRM_INFO("applying inverted panel brightness quirk\n");
8717 struct intel_quirk {
8719 int subsystem_vendor;
8720 int subsystem_device;
8721 void (*hook)(struct drm_device *dev);
8724 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8725 struct intel_dmi_quirk {
8726 void (*hook)(struct drm_device *dev);
8727 const struct dmi_system_id (*dmi_id_list)[];
8730 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8732 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8736 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8738 .dmi_id_list = &(const struct dmi_system_id[]) {
8740 .callback = intel_dmi_reverse_brightness,
8741 .ident = "NCR Corporation",
8742 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8743 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8746 { } /* terminating entry */
8748 .hook = quirk_invert_brightness,
8752 static struct intel_quirk intel_quirks[] = {
8753 /* HP Mini needs pipe A force quirk (LP: #322104) */
8754 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8756 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8757 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8759 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8760 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8762 /* 830/845 need to leave pipe A & dpll A up */
8763 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8764 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8766 /* Lenovo U160 cannot use SSC on LVDS */
8767 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8769 /* Sony Vaio Y cannot use SSC on LVDS */
8770 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8772 /* Acer Aspire 5734Z must invert backlight brightness */
8773 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8775 /* Acer/eMachines G725 */
8776 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8778 /* Acer/eMachines e725 */
8779 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8781 /* Acer/Packard Bell NCL20 */
8782 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8784 /* Acer Aspire 4736Z */
8785 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8788 static void intel_init_quirks(struct drm_device *dev)
8790 struct pci_dev *d = dev->pdev;
8793 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8794 struct intel_quirk *q = &intel_quirks[i];
8796 if (d->device == q->device &&
8797 (d->subsystem_vendor == q->subsystem_vendor ||
8798 q->subsystem_vendor == PCI_ANY_ID) &&
8799 (d->subsystem_device == q->subsystem_device ||
8800 q->subsystem_device == PCI_ANY_ID))
8803 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8804 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8805 intel_dmi_quirks[i].hook(dev);
8809 /* Disable the VGA plane that we never use */
8810 static void i915_disable_vga(struct drm_device *dev)
8812 struct drm_i915_private *dev_priv = dev->dev_private;
8814 u32 vga_reg = i915_vgacntrl_reg(dev);
8816 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8817 outb(SR01, VGA_SR_INDEX);
8818 sr1 = inb(VGA_SR_DATA);
8819 outb(sr1 | 1<<5, VGA_SR_DATA);
8820 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8823 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8824 POSTING_READ(vga_reg);
8827 void intel_modeset_init_hw(struct drm_device *dev)
8829 intel_init_power_well(dev);
8831 intel_prepare_ddi(dev);
8833 intel_init_clock_gating(dev);
8835 mutex_lock(&dev->struct_mutex);
8836 intel_enable_gt_powersave(dev);
8837 mutex_unlock(&dev->struct_mutex);
8840 void intel_modeset_init(struct drm_device *dev)
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8845 drm_mode_config_init(dev);
8847 dev->mode_config.min_width = 0;
8848 dev->mode_config.min_height = 0;
8850 dev->mode_config.preferred_depth = 24;
8851 dev->mode_config.prefer_shadow = 1;
8853 dev->mode_config.funcs = &intel_mode_funcs;
8855 intel_init_quirks(dev);
8859 intel_init_display(dev);
8862 dev->mode_config.max_width = 2048;
8863 dev->mode_config.max_height = 2048;
8864 } else if (IS_GEN3(dev)) {
8865 dev->mode_config.max_width = 4096;
8866 dev->mode_config.max_height = 4096;
8868 dev->mode_config.max_width = 8192;
8869 dev->mode_config.max_height = 8192;
8871 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8873 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8874 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8876 for (i = 0; i < dev_priv->num_pipe; i++) {
8877 intel_crtc_init(dev, i);
8878 ret = intel_plane_init(dev, i);
8880 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8883 intel_cpu_pll_init(dev);
8884 intel_pch_pll_init(dev);
8886 /* Just disable it once at startup */
8887 i915_disable_vga(dev);
8888 intel_setup_outputs(dev);
8890 /* Just in case the BIOS is doing something questionable. */
8891 intel_disable_fbc(dev);
8895 intel_connector_break_all_links(struct intel_connector *connector)
8897 connector->base.dpms = DRM_MODE_DPMS_OFF;
8898 connector->base.encoder = NULL;
8899 connector->encoder->connectors_active = false;
8900 connector->encoder->base.crtc = NULL;
8903 static void intel_enable_pipe_a(struct drm_device *dev)
8905 struct intel_connector *connector;
8906 struct drm_connector *crt = NULL;
8907 struct intel_load_detect_pipe load_detect_temp;
8909 /* We can't just switch on the pipe A, we need to set things up with a
8910 * proper mode and output configuration. As a gross hack, enable pipe A
8911 * by enabling the load detect pipe once. */
8912 list_for_each_entry(connector,
8913 &dev->mode_config.connector_list,
8915 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8916 crt = &connector->base;
8924 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8925 intel_release_load_detect_pipe(crt, &load_detect_temp);
8931 intel_check_plane_mapping(struct intel_crtc *crtc)
8933 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8936 if (dev_priv->num_pipe == 1)
8939 reg = DSPCNTR(!crtc->plane);
8940 val = I915_READ(reg);
8942 if ((val & DISPLAY_PLANE_ENABLE) &&
8943 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8949 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8951 struct drm_device *dev = crtc->base.dev;
8952 struct drm_i915_private *dev_priv = dev->dev_private;
8955 /* Clear any frame start delays used for debugging left by the BIOS */
8956 reg = PIPECONF(crtc->cpu_transcoder);
8957 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8959 /* We need to sanitize the plane -> pipe mapping first because this will
8960 * disable the crtc (and hence change the state) if it is wrong. Note
8961 * that gen4+ has a fixed plane -> pipe mapping. */
8962 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8963 struct intel_connector *connector;
8966 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8967 crtc->base.base.id);
8969 /* Pipe has the wrong plane attached and the plane is active.
8970 * Temporarily change the plane mapping and disable everything
8972 plane = crtc->plane;
8973 crtc->plane = !plane;
8974 dev_priv->display.crtc_disable(&crtc->base);
8975 crtc->plane = plane;
8977 /* ... and break all links. */
8978 list_for_each_entry(connector, &dev->mode_config.connector_list,
8980 if (connector->encoder->base.crtc != &crtc->base)
8983 intel_connector_break_all_links(connector);
8986 WARN_ON(crtc->active);
8987 crtc->base.enabled = false;
8990 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8991 crtc->pipe == PIPE_A && !crtc->active) {
8992 /* BIOS forgot to enable pipe A, this mostly happens after
8993 * resume. Force-enable the pipe to fix this, the update_dpms
8994 * call below we restore the pipe to the right state, but leave
8995 * the required bits on. */
8996 intel_enable_pipe_a(dev);
8999 /* Adjust the state of the output pipe according to whether we
9000 * have active connectors/encoders. */
9001 intel_crtc_update_dpms(&crtc->base);
9003 if (crtc->active != crtc->base.enabled) {
9004 struct intel_encoder *encoder;
9006 /* This can happen either due to bugs in the get_hw_state
9007 * functions or because the pipe is force-enabled due to the
9009 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9011 crtc->base.enabled ? "enabled" : "disabled",
9012 crtc->active ? "enabled" : "disabled");
9014 crtc->base.enabled = crtc->active;
9016 /* Because we only establish the connector -> encoder ->
9017 * crtc links if something is active, this means the
9018 * crtc is now deactivated. Break the links. connector
9019 * -> encoder links are only establish when things are
9020 * actually up, hence no need to break them. */
9021 WARN_ON(crtc->active);
9023 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9024 WARN_ON(encoder->connectors_active);
9025 encoder->base.crtc = NULL;
9030 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9032 struct intel_connector *connector;
9033 struct drm_device *dev = encoder->base.dev;
9035 /* We need to check both for a crtc link (meaning that the
9036 * encoder is active and trying to read from a pipe) and the
9037 * pipe itself being active. */
9038 bool has_active_crtc = encoder->base.crtc &&
9039 to_intel_crtc(encoder->base.crtc)->active;
9041 if (encoder->connectors_active && !has_active_crtc) {
9042 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9043 encoder->base.base.id,
9044 drm_get_encoder_name(&encoder->base));
9046 /* Connector is active, but has no active pipe. This is
9047 * fallout from our resume register restoring. Disable
9048 * the encoder manually again. */
9049 if (encoder->base.crtc) {
9050 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9051 encoder->base.base.id,
9052 drm_get_encoder_name(&encoder->base));
9053 encoder->disable(encoder);
9056 /* Inconsistent output/port/pipe state happens presumably due to
9057 * a bug in one of the get_hw_state functions. Or someplace else
9058 * in our code, like the register restore mess on resume. Clamp
9059 * things to off as a safer default. */
9060 list_for_each_entry(connector,
9061 &dev->mode_config.connector_list,
9063 if (connector->encoder != encoder)
9066 intel_connector_break_all_links(connector);
9069 /* Enabled encoders without active connectors will be fixed in
9070 * the crtc fixup. */
9073 void i915_redisable_vga(struct drm_device *dev)
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 u32 vga_reg = i915_vgacntrl_reg(dev);
9078 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9079 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9080 i915_disable_vga(dev);
9084 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9085 * and i915 state tracking structures. */
9086 void intel_modeset_setup_hw_state(struct drm_device *dev,
9089 struct drm_i915_private *dev_priv = dev->dev_private;
9092 struct intel_crtc *crtc;
9093 struct intel_encoder *encoder;
9094 struct intel_connector *connector;
9097 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9099 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9100 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9101 case TRANS_DDI_EDP_INPUT_A_ON:
9102 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9105 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9108 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9113 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9114 crtc->cpu_transcoder = TRANSCODER_EDP;
9116 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9121 for_each_pipe(pipe) {
9122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9124 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9125 if (tmp & PIPECONF_ENABLE)
9126 crtc->active = true;
9128 crtc->active = false;
9130 crtc->base.enabled = crtc->active;
9132 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9134 crtc->active ? "enabled" : "disabled");
9138 intel_ddi_setup_hw_pll_state(dev);
9140 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9144 if (encoder->get_hw_state(encoder, &pipe)) {
9145 encoder->base.crtc =
9146 dev_priv->pipe_to_crtc_mapping[pipe];
9148 encoder->base.crtc = NULL;
9151 encoder->connectors_active = false;
9152 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9153 encoder->base.base.id,
9154 drm_get_encoder_name(&encoder->base),
9155 encoder->base.crtc ? "enabled" : "disabled",
9159 list_for_each_entry(connector, &dev->mode_config.connector_list,
9161 if (connector->get_hw_state(connector)) {
9162 connector->base.dpms = DRM_MODE_DPMS_ON;
9163 connector->encoder->connectors_active = true;
9164 connector->base.encoder = &connector->encoder->base;
9166 connector->base.dpms = DRM_MODE_DPMS_OFF;
9167 connector->base.encoder = NULL;
9169 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9170 connector->base.base.id,
9171 drm_get_connector_name(&connector->base),
9172 connector->base.encoder ? "enabled" : "disabled");
9175 /* HW state is read out, now we need to sanitize this mess. */
9176 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9178 intel_sanitize_encoder(encoder);
9181 for_each_pipe(pipe) {
9182 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9183 intel_sanitize_crtc(crtc);
9186 if (force_restore) {
9187 for_each_pipe(pipe) {
9188 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9191 i915_redisable_vga(dev);
9193 intel_modeset_update_staged_output_state(dev);
9196 intel_modeset_check_state(dev);
9198 drm_mode_config_reset(dev);
9201 void intel_modeset_gem_init(struct drm_device *dev)
9203 intel_modeset_init_hw(dev);
9205 intel_setup_overlay(dev);
9207 intel_modeset_setup_hw_state(dev, false);
9210 void intel_modeset_cleanup(struct drm_device *dev)
9212 struct drm_i915_private *dev_priv = dev->dev_private;
9213 struct drm_crtc *crtc;
9214 struct intel_crtc *intel_crtc;
9216 drm_kms_helper_poll_fini(dev);
9217 mutex_lock(&dev->struct_mutex);
9219 intel_unregister_dsm_handler();
9222 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9223 /* Skip inactive CRTCs */
9227 intel_crtc = to_intel_crtc(crtc);
9228 intel_increase_pllclock(crtc);
9231 intel_disable_fbc(dev);
9233 intel_disable_gt_powersave(dev);
9235 ironlake_teardown_rc6(dev);
9237 if (IS_VALLEYVIEW(dev))
9240 mutex_unlock(&dev->struct_mutex);
9242 /* Disable the irq before mode object teardown, for the irq might
9243 * enqueue unpin/hotplug work. */
9244 drm_irq_uninstall(dev);
9245 cancel_work_sync(&dev_priv->hotplug_work);
9246 cancel_work_sync(&dev_priv->rps.work);
9248 /* flush any delayed tasks or pending work */
9249 flush_scheduled_work();
9251 drm_mode_config_cleanup(dev);
9253 intel_cleanup_overlay(dev);
9257 * Return which encoder is currently attached for connector.
9259 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9261 return &intel_attached_encoder(connector)->base;
9264 void intel_connector_attach_encoder(struct intel_connector *connector,
9265 struct intel_encoder *encoder)
9267 connector->encoder = encoder;
9268 drm_mode_connector_attach_encoder(&connector->base,
9273 * set vga decode state - true == enable VGA decode
9275 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9277 struct drm_i915_private *dev_priv = dev->dev_private;
9280 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9282 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9284 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9285 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9289 #ifdef CONFIG_DEBUG_FS
9290 #include <linux/seq_file.h>
9292 struct intel_display_error_state {
9293 struct intel_cursor_error_state {
9298 } cursor[I915_MAX_PIPES];
9300 struct intel_pipe_error_state {
9310 } pipe[I915_MAX_PIPES];
9312 struct intel_plane_error_state {
9320 } plane[I915_MAX_PIPES];
9323 struct intel_display_error_state *
9324 intel_display_capture_error_state(struct drm_device *dev)
9326 drm_i915_private_t *dev_priv = dev->dev_private;
9327 struct intel_display_error_state *error;
9328 enum transcoder cpu_transcoder;
9331 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9336 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9338 error->cursor[i].control = I915_READ(CURCNTR(i));
9339 error->cursor[i].position = I915_READ(CURPOS(i));
9340 error->cursor[i].base = I915_READ(CURBASE(i));
9342 error->plane[i].control = I915_READ(DSPCNTR(i));
9343 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9344 error->plane[i].size = I915_READ(DSPSIZE(i));
9345 error->plane[i].pos = I915_READ(DSPPOS(i));
9346 error->plane[i].addr = I915_READ(DSPADDR(i));
9347 if (INTEL_INFO(dev)->gen >= 4) {
9348 error->plane[i].surface = I915_READ(DSPSURF(i));
9349 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9352 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9353 error->pipe[i].source = I915_READ(PIPESRC(i));
9354 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9355 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9356 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9357 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9358 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9359 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9366 intel_display_print_error_state(struct seq_file *m,
9367 struct drm_device *dev,
9368 struct intel_display_error_state *error)
9370 drm_i915_private_t *dev_priv = dev->dev_private;
9373 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9375 seq_printf(m, "Pipe [%d]:\n", i);
9376 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9377 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9378 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9379 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9380 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9381 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9382 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9383 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9385 seq_printf(m, "Plane [%d]:\n", i);
9386 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9387 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9388 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9389 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9390 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9391 if (INTEL_INFO(dev)->gen >= 4) {
9392 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9393 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9396 seq_printf(m, "Cursor [%d]:\n", i);
9397 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9398 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9399 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);