Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 #define INTEL_P2_NUM                  2
  63 typedef struct intel_limit intel_limit_t;
  64 struct intel_limit {
  65         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  66         intel_p2_t          p2;
  67 };
  68
  69 /* FDI */
  70 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dvo = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_lvds = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 1, .max = 6 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 14, .p2_fast = 7 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i9xx_sdvo = {
 119         .dot = { .min = 20000, .max = 400000 },
 120         .vco = { .min = 1400000, .max = 2800000 },
 121         .n = { .min = 1, .max = 6 },
 122         .m = { .min = 70, .max = 120 },
 123         .m1 = { .min = 8, .max = 18 },
 124         .m2 = { .min = 3, .max = 7 },
 125         .p = { .min = 5, .max = 80 },
 126         .p1 = { .min = 1, .max = 8 },
 127         .p2 = { .dot_limit = 200000,
 128                 .p2_slow = 10, .p2_fast = 5 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_lvds = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 7, .max = 98 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 112000,
 141                 .p2_slow = 14, .p2_fast = 7 },
 142 };
 143
 144
 145 static const intel_limit_t intel_limits_g4x_sdvo = {
 146         .dot = { .min = 25000, .max = 270000 },
 147         .vco = { .min = 1750000, .max = 3500000},
 148         .n = { .min = 1, .max = 4 },
 149         .m = { .min = 104, .max = 138 },
 150         .m1 = { .min = 17, .max = 23 },
 151         .m2 = { .min = 5, .max = 11 },
 152         .p = { .min = 10, .max = 30 },
 153         .p1 = { .min = 1, .max = 3},
 154         .p2 = { .dot_limit = 270000,
 155                 .p2_slow = 10,
 156                 .p2_fast = 10
 157         },
 158 };
 159
 160 static const intel_limit_t intel_limits_g4x_hdmi = {
 161         .dot = { .min = 22000, .max = 400000 },
 162         .vco = { .min = 1750000, .max = 3500000},
 163         .n = { .min = 1, .max = 4 },
 164         .m = { .min = 104, .max = 138 },
 165         .m1 = { .min = 16, .max = 23 },
 166         .m2 = { .min = 5, .max = 11 },
 167         .p = { .min = 5, .max = 80 },
 168         .p1 = { .min = 1, .max = 8},
 169         .p2 = { .dot_limit = 165000,
 170                 .p2_slow = 10, .p2_fast = 5 },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 174         .dot = { .min = 20000, .max = 115000 },
 175         .vco = { .min = 1750000, .max = 3500000 },
 176         .n = { .min = 1, .max = 3 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 28, .max = 112 },
 181         .p1 = { .min = 2, .max = 8 },
 182         .p2 = { .dot_limit = 0,
 183                 .p2_slow = 14, .p2_fast = 14
 184         },
 185 };
 186
 187 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 188         .dot = { .min = 80000, .max = 224000 },
 189         .vco = { .min = 1750000, .max = 3500000 },
 190         .n = { .min = 1, .max = 3 },
 191         .m = { .min = 104, .max = 138 },
 192         .m1 = { .min = 17, .max = 23 },
 193         .m2 = { .min = 5, .max = 11 },
 194         .p = { .min = 14, .max = 42 },
 195         .p1 = { .min = 2, .max = 6 },
 196         .p2 = { .dot_limit = 0,
 197                 .p2_slow = 7, .p2_fast = 7
 198         },
 199 };
 200
 201 static const intel_limit_t intel_limits_pineview_sdvo = {
 202         .dot = { .min = 20000, .max = 400000},
 203         .vco = { .min = 1700000, .max = 3500000 },
 204         /* Pineview's Ncounter is a ring counter */
 205         .n = { .min = 3, .max = 6 },
 206         .m = { .min = 2, .max = 256 },
 207         /* Pineview only has one combined m divider, which we treat as m2. */
 208         .m1 = { .min = 0, .max = 0 },
 209         .m2 = { .min = 0, .max = 254 },
 210         .p = { .min = 5, .max = 80 },
 211         .p1 = { .min = 1, .max = 8 },
 212         .p2 = { .dot_limit = 200000,
 213                 .p2_slow = 10, .p2_fast = 5 },
 214 };
 215
 216 static const intel_limit_t intel_limits_pineview_lvds = {
 217         .dot = { .min = 20000, .max = 400000 },
 218         .vco = { .min = 1700000, .max = 3500000 },
 219         .n = { .min = 3, .max = 6 },
 220         .m = { .min = 2, .max = 256 },
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 7, .max = 112 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 112000,
 226                 .p2_slow = 14, .p2_fast = 14 },
 227 };
 228
 229 /* Ironlake / Sandybridge
 230  *
 231  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 232  * the range value for them is (actual_value - 2).
 233  */
 234 static const intel_limit_t intel_limits_ironlake_dac = {
 235         .dot = { .min = 25000, .max = 350000 },
 236         .vco = { .min = 1760000, .max = 3510000 },
 237         .n = { .min = 1, .max = 5 },
 238         .m = { .min = 79, .max = 127 },
 239         .m1 = { .min = 12, .max = 22 },
 240         .m2 = { .min = 5, .max = 9 },
 241         .p = { .min = 5, .max = 80 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 225000,
 244                 .p2_slow = 10, .p2_fast = 5 },
 245 };
 246
 247 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 3 },
 251         .m = { .min = 79, .max = 118 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 28, .max = 112 },
 255         .p1 = { .min = 2, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 14, .p2_fast = 14 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 127 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 14, .max = 56 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 7, .p2_fast = 7 },
 271 };
 272
 273 /* LVDS 100mhz refclk limits. */
 274 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 2 },
 278         .m = { .min = 79, .max = 126 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 28, .max = 112 },
 282         .p1 = { .min = 2, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 14, .p2_fast = 14 },
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 14, .max = 42 },
 295         .p1 = { .min = 2, .max = 6 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 7, .p2_fast = 7 },
 298 };
 299
 300 static const intel_limit_t intel_limits_vlv_dac = {
 301         .dot = { .min = 25000, .max = 270000 },
 302         .vco = { .min = 4000000, .max = 6000000 },
 303         .n = { .min = 1, .max = 7 },
 304         .m = { .min = 22, .max = 450 }, /* guess */
 305         .m1 = { .min = 2, .max = 3 },
 306         .m2 = { .min = 11, .max = 156 },
 307         .p = { .min = 10, .max = 30 },
 308         .p1 = { .min = 1, .max = 3 },
 309         .p2 = { .dot_limit = 270000,
 310                 .p2_slow = 2, .p2_fast = 20 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_hdmi = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 60, .max = 300 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 2, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_dp = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 22, .max = 450 },
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 1, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 340                                                 int refclk)
 341 {
 342         struct drm_device *dev = crtc->dev;
 343         const intel_limit_t *limit;
 344
 345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 346                 if (intel_is_dual_link_lvds(dev)) {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_dual_lvds;
 351                 } else {
 352                         if (refclk == 100000)
 353                                 limit = &intel_limits_ironlake_single_lvds_100m;
 354                         else
 355                                 limit = &intel_limits_ironlake_single_lvds;
 356                 }
 357         } else
 358                 limit = &intel_limits_ironlake_dac;
 359
 360         return limit;
 361 }
 362
 363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         const intel_limit_t *limit;
 367
 368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 369                 if (intel_is_dual_link_lvds(dev))
 370                         limit = &intel_limits_g4x_dual_channel_lvds;
 371                 else
 372                         limit = &intel_limits_g4x_single_channel_lvds;
 373         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 374                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 375                 limit = &intel_limits_g4x_hdmi;
 376         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 377                 limit = &intel_limits_g4x_sdvo;
 378         } else /* The option is for other outputs */
 379                 limit = &intel_limits_i9xx_sdvo;
 380
 381         return limit;
 382 }
 383
 384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 385 {
 386         struct drm_device *dev = crtc->dev;
 387         const intel_limit_t *limit;
 388
 389         if (HAS_PCH_SPLIT(dev))
 390                 limit = intel_ironlake_limit(crtc, refclk);
 391         else if (IS_G4X(dev)) {
 392                 limit = intel_g4x_limit(crtc);
 393         } else if (IS_PINEVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 395                         limit = &intel_limits_pineview_lvds;
 396                 else
 397                         limit = &intel_limits_pineview_sdvo;
 398         } else if (IS_VALLEYVIEW(dev)) {
 399                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 400                         limit = &intel_limits_vlv_dac;
 401                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 402                         limit = &intel_limits_vlv_hdmi;
 403                 else
 404                         limit = &intel_limits_vlv_dp;
 405         } else if (!IS_GEN2(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i9xx_lvds;
 408                 else
 409                         limit = &intel_limits_i9xx_sdvo;
 410         } else {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 412                         limit = &intel_limits_i8xx_lvds;
 413                 else
 414                         limit = &intel_limits_i8xx_dvo;
 415         }
 416         return limit;
 417 }
 418
 419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 420 static void pineview_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m2 + 2;
 423         clock->p = clock->p1 * clock->p2;
 424         clock->vco = refclk * clock->m / clock->n;
 425         clock->dot = clock->vco / clock->p;
 426 }
 427
 428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 429 {
 430         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 431 }
 432
 433 static void i9xx_clock(int refclk, intel_clock_t *clock)
 434 {
 435         clock->m = i9xx_dpll_compute_m(clock);
 436         clock->p = clock->p1 * clock->p2;
 437         clock->vco = refclk * clock->m / (clock->n + 2);
 438         clock->dot = clock->vco / clock->p;
 439 }
 440
 441 /**
 442  * Returns whether any output on the specified pipe is of the specified type
 443  */
 444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 445 {
 446         struct drm_device *dev = crtc->dev;
 447         struct intel_encoder *encoder;
 448
 449         for_each_encoder_on_crtc(dev, crtc, encoder)
 450                 if (encoder->type == type)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 467                 INTELPllInvalid("p1 out of range\n");
 468         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 469                 INTELPllInvalid("p out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 475                 INTELPllInvalid("m1 <= m2\n");
 476         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 477                 INTELPllInvalid("m out of range\n");
 478         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 479                 INTELPllInvalid("n out of range\n");
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 674         u32 m, n, fastclk;
 675         u32 updrate, minupdate, fracbits, p;
 676         unsigned long bestppm, ppm, absppm;
 677         int dotclk, flag;
 678
 679         flag = 0;
 680         dotclk = target * 1000;
 681         bestppm = 1000000;
 682         ppm = absppm = 0;
 683         fastclk = dotclk / (2*100);
 684         updrate = 0;
 685         minupdate = 19200;
 686         fracbits = 1;
 687         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 688         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 689
 690         /* based on hardware requirement, prefer smaller n to precision */
 691         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 692                 updrate = refclk / n;
 693                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 694                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 695                                 if (p2 > 10)
 696                                         p2 = p2 - 1;
 697                                 p = p1 * p2;
 698                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 699                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 700                                         m2 = (((2*(fastclk * p * n / m1 )) +
 701                                                refclk) / (2*refclk));
 702                                         m = m1 * m2;
 703                                         vco = updrate * m;
 704                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 705                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 706                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 707                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 708                                                         bestppm = 0;
 709                                                         flag = 1;
 710                                                 }
 711                                                 if (absppm < bestppm - 10) {
 712                                                         bestppm = absppm;
 713                                                         flag = 1;
 714                                                 }
 715                                                 if (flag) {
 716                                                         bestn = n;
 717                                                         bestm1 = m1;
 718                                                         bestm2 = m2;
 719                                                         bestp1 = p1;
 720                                                         bestp2 = p2;
 721                                                         flag = 0;
 722                                                 }
 723                                         }
 724                                 }
 725                         }
 726                 }
 727         }
 728         best_clock->n = bestn;
 729         best_clock->m1 = bestm1;
 730         best_clock->m2 = bestm2;
 731         best_clock->p1 = bestp1;
 732         best_clock->p2 = bestp2;
 733
 734         return true;
 735 }
 736
 737 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 738                                              enum pipe pipe)
 739 {
 740         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 742
 743         return intel_crtc->config.cpu_transcoder;
 744 }
 745
 746 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 747 {
 748         struct drm_i915_private *dev_priv = dev->dev_private;
 749         u32 frame, frame_reg = PIPEFRAME(pipe);
 750
 751         frame = I915_READ(frame_reg);
 752
 753         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 754                 DRM_DEBUG_KMS("vblank wait timed out\n");
 755 }
 756
 757 /**
 758  * intel_wait_for_vblank - wait for vblank on a given pipe
 759  * @dev: drm device
 760  * @pipe: pipe to wait for
 761  *
 762  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 763  * mode setting code.
 764  */
 765 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 766 {
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         int pipestat_reg = PIPESTAT(pipe);
 769
 770         if (INTEL_INFO(dev)->gen >= 5) {
 771                 ironlake_wait_for_vblank(dev, pipe);
 772                 return;
 773         }
 774
 775         /* Clear existing vblank status. Note this will clear any other
 776          * sticky status fields as well.
 777          *
 778          * This races with i915_driver_irq_handler() with the result
 779          * that either function could miss a vblank event.  Here it is not
 780          * fatal, as we will either wait upon the next vblank interrupt or
 781          * timeout.  Generally speaking intel_wait_for_vblank() is only
 782          * called during modeset at which time the GPU should be idle and
 783          * should *not* be performing page flips and thus not waiting on
 784          * vblanks...
 785          * Currently, the result of us stealing a vblank from the irq
 786          * handler is that a single frame will be skipped during swapbuffers.
 787          */
 788         I915_WRITE(pipestat_reg,
 789                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 790
 791         /* Wait for vblank interrupt bit to set */
 792         if (wait_for(I915_READ(pipestat_reg) &
 793                      PIPE_VBLANK_INTERRUPT_STATUS,
 794                      50))
 795                 DRM_DEBUG_KMS("vblank wait timed out\n");
 796 }
 797
 798 /*
 799  * intel_wait_for_pipe_off - wait for pipe to turn off
 800  * @dev: drm device
 801  * @pipe: pipe to wait for
 802  *
 803  * After disabling a pipe, we can't wait for vblank in the usual way,
 804  * spinning on the vblank interrupt status bit, since we won't actually
 805  * see an interrupt when the pipe is disabled.
 806  *
 807  * On Gen4 and above:
 808  *   wait for the pipe register state bit to turn off
 809  *
 810  * Otherwise:
 811  *   wait for the display line value to settle (it usually
 812  *   ends up stopping at the start of the next frame).
 813  *
 814  */
 815 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 816 {
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 819                                                                       pipe);
 820
 821         if (INTEL_INFO(dev)->gen >= 4) {
 822                 int reg = PIPECONF(cpu_transcoder);
 823
 824                 /* Wait for the Pipe State to go off */
 825                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 826                              100))
 827                         WARN(1, "pipe_off wait timed out\n");
 828         } else {
 829                 u32 last_line, line_mask;
 830                 int reg = PIPEDSL(pipe);
 831                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 832
 833                 if (IS_GEN2(dev))
 834                         line_mask = DSL_LINEMASK_GEN2;
 835                 else
 836                         line_mask = DSL_LINEMASK_GEN3;
 837
 838                 /* Wait for the display line to settle */
 839                 do {
 840                         last_line = I915_READ(reg) & line_mask;
 841                         mdelay(5);
 842                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 843                          time_after(timeout, jiffies));
 844                 if (time_after(jiffies, timeout))
 845                         WARN(1, "pipe_off wait timed out\n");
 846         }
 847 }
 848
 849 /*
 850  * ibx_digital_port_connected - is the specified port connected?
 851  * @dev_priv: i915 private structure
 852  * @port: the port to test
 853  *
 854  * Returns true if @port is connected, false otherwise.
 855  */
 856 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 857                                 struct intel_digital_port *port)
 858 {
 859         u32 bit;
 860
 861         if (HAS_PCH_IBX(dev_priv->dev)) {
 862                 switch(port->port) {
 863                 case PORT_B:
 864                         bit = SDE_PORTB_HOTPLUG;
 865                         break;
 866                 case PORT_C:
 867                         bit = SDE_PORTC_HOTPLUG;
 868                         break;
 869                 case PORT_D:
 870                         bit = SDE_PORTD_HOTPLUG;
 871                         break;
 872                 default:
 873                         return true;
 874                 }
 875         } else {
 876                 switch(port->port) {
 877                 case PORT_B:
 878                         bit = SDE_PORTB_HOTPLUG_CPT;
 879                         break;
 880                 case PORT_C:
 881                         bit = SDE_PORTC_HOTPLUG_CPT;
 882                         break;
 883                 case PORT_D:
 884                         bit = SDE_PORTD_HOTPLUG_CPT;
 885                         break;
 886                 default:
 887                         return true;
 888                 }
 889         }
 890
 891         return I915_READ(SDEISR) & bit;
 892 }
 893
 894 static const char *state_string(bool enabled)
 895 {
 896         return enabled ? "on" : "off";
 897 }
 898
 899 /* Only for pre-ILK configs */
 900 void assert_pll(struct drm_i915_private *dev_priv,
 901                 enum pipe pipe, bool state)
 902 {
 903         int reg;
 904         u32 val;
 905         bool cur_state;
 906
 907         reg = DPLL(pipe);
 908         val = I915_READ(reg);
 909         cur_state = !!(val & DPLL_VCO_ENABLE);
 910         WARN(cur_state != state,
 911              "PLL state assertion failure (expected %s, current %s)\n",
 912              state_string(state), state_string(cur_state));
 913 }
 914
 915 struct intel_shared_dpll *
 916 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 917 {
 918         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 919
 920         if (crtc->config.shared_dpll < 0)
 921                 return NULL;
 922
 923         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 924 }
 925
 926 /* For ILK+ */
 927 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 928                         struct intel_shared_dpll *pll,
 929                         bool state)
 930 {
 931         bool cur_state;
 932         struct intel_dpll_hw_state hw_state;
 933
 934         if (HAS_PCH_LPT(dev_priv->dev)) {
 935                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 936                 return;
 937         }
 938
 939         if (WARN (!pll,
 940                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 941                 return;
 942
 943         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 944         WARN(cur_state != state,
 945              "%s assertion failure (expected %s, current %s)\n",
 946              pll->name, state_string(state), state_string(cur_state));
 947 }
 948
 949 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 950                           enum pipe pipe, bool state)
 951 {
 952         int reg;
 953         u32 val;
 954         bool cur_state;
 955         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 956                                                                       pipe);
 957
 958         if (HAS_DDI(dev_priv->dev)) {
 959                 /* DDI does not have a specific FDI_TX register */
 960                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 961                 val = I915_READ(reg);
 962                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 963         } else {
 964                 reg = FDI_TX_CTL(pipe);
 965                 val = I915_READ(reg);
 966                 cur_state = !!(val & FDI_TX_ENABLE);
 967         }
 968         WARN(cur_state != state,
 969              "FDI TX state assertion failure (expected %s, current %s)\n",
 970              state_string(state), state_string(cur_state));
 971 }
 972 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 973 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 974
 975 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 976                           enum pipe pipe, bool state)
 977 {
 978         int reg;
 979         u32 val;
 980         bool cur_state;
 981
 982         reg = FDI_RX_CTL(pipe);
 983         val = I915_READ(reg);
 984         cur_state = !!(val & FDI_RX_ENABLE);
 985         WARN(cur_state != state,
 986              "FDI RX state assertion failure (expected %s, current %s)\n",
 987              state_string(state), state_string(cur_state));
 988 }
 989 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 990 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 991
 992 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 993                                       enum pipe pipe)
 994 {
 995         int reg;
 996         u32 val;
 997
 998         /* ILK FDI PLL is always enabled */
 999         if (dev_priv->info->gen == 5)
1000                 return;
1001
1002         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1003         if (HAS_DDI(dev_priv->dev))
1004                 return;
1005
1006         reg = FDI_TX_CTL(pipe);
1007         val = I915_READ(reg);
1008         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009 }
1010
1011 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012                        enum pipe pipe, bool state)
1013 {
1014         int reg;
1015         u32 val;
1016         bool cur_state;
1017
1018         reg = FDI_RX_CTL(pipe);
1019         val = I915_READ(reg);
1020         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021         WARN(cur_state != state,
1022              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023              state_string(state), state_string(cur_state));
1024 }
1025
1026 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027                                   enum pipe pipe)
1028 {
1029         int pp_reg, lvds_reg;
1030         u32 val;
1031         enum pipe panel_pipe = PIPE_A;
1032         bool locked = true;
1033
1034         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035                 pp_reg = PCH_PP_CONTROL;
1036                 lvds_reg = PCH_LVDS;
1037         } else {
1038                 pp_reg = PP_CONTROL;
1039                 lvds_reg = LVDS;
1040         }
1041
1042         val = I915_READ(pp_reg);
1043         if (!(val & PANEL_POWER_ON) ||
1044             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045                 locked = false;
1046
1047         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048                 panel_pipe = PIPE_B;
1049
1050         WARN(panel_pipe == pipe && locked,
1051              "panel assertion failure, pipe %c regs locked\n",
1052              pipe_name(pipe));
1053 }
1054
1055 void assert_pipe(struct drm_i915_private *dev_priv,
1056                  enum pipe pipe, bool state)
1057 {
1058         int reg;
1059         u32 val;
1060         bool cur_state;
1061         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062                                                                       pipe);
1063
1064         /* if we need the pipe A quirk it must be always on */
1065         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066                 state = true;
1067
1068         if (!intel_display_power_enabled(dev_priv->dev,
1069                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1070                 cur_state = false;
1071         } else {
1072                 reg = PIPECONF(cpu_transcoder);
1073                 val = I915_READ(reg);
1074                 cur_state = !!(val & PIPECONF_ENABLE);
1075         }
1076
1077         WARN(cur_state != state,
1078              "pipe %c assertion failure (expected %s, current %s)\n",
1079              pipe_name(pipe), state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_plane(struct drm_i915_private *dev_priv,
1083                          enum plane plane, bool state)
1084 {
1085         int reg;
1086         u32 val;
1087         bool cur_state;
1088
1089         reg = DSPCNTR(plane);
1090         val = I915_READ(reg);
1091         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092         WARN(cur_state != state,
1093              "plane %c assertion failure (expected %s, current %s)\n",
1094              plane_name(plane), state_string(state), state_string(cur_state));
1095 }
1096
1097 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
1100 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101                                    enum pipe pipe)
1102 {
1103         struct drm_device *dev = dev_priv->dev;
1104         int reg, i;
1105         u32 val;
1106         int cur_pipe;
1107
1108         /* Primary planes are fixed to pipes on gen4+ */
1109         if (INTEL_INFO(dev)->gen >= 4) {
1110                 reg = DSPCNTR(pipe);
1111                 val = I915_READ(reg);
1112                 WARN((val & DISPLAY_PLANE_ENABLE),
1113                      "plane %c assertion failure, should be disabled but not\n",
1114                      plane_name(pipe));
1115                 return;
1116         }
1117
1118         /* Need to check both planes against the pipe */
1119         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1120                 reg = DSPCNTR(i);
1121                 val = I915_READ(reg);
1122                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123                         DISPPLANE_SEL_PIPE_SHIFT;
1124                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1125                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126                      plane_name(i), pipe_name(pipe));
1127         }
1128 }
1129
1130 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131                                     enum pipe pipe)
1132 {
1133         struct drm_device *dev = dev_priv->dev;
1134         int reg, i;
1135         u32 val;
1136
1137         if (IS_VALLEYVIEW(dev)) {
1138                 for (i = 0; i < dev_priv->num_plane; i++) {
1139                         reg = SPCNTR(pipe, i);
1140                         val = I915_READ(reg);
1141                         WARN((val & SP_ENABLE),
1142                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143                              sprite_name(pipe, i), pipe_name(pipe));
1144                 }
1145         } else if (INTEL_INFO(dev)->gen >= 7) {
1146                 reg = SPRCTL(pipe);
1147                 val = I915_READ(reg);
1148                 WARN((val & SPRITE_ENABLE),
1149                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1150                      plane_name(pipe), pipe_name(pipe));
1151         } else if (INTEL_INFO(dev)->gen >= 5) {
1152                 reg = DVSCNTR(pipe);
1153                 val = I915_READ(reg);
1154                 WARN((val & DVS_ENABLE),
1155                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1156                      plane_name(pipe), pipe_name(pipe));
1157         }
1158 }
1159
1160 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161 {
1162         u32 val;
1163         bool enabled;
1164
1165         if (HAS_PCH_LPT(dev_priv->dev)) {
1166                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167                 return;
1168         }
1169
1170         val = I915_READ(PCH_DREF_CONTROL);
1171         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172                             DREF_SUPERSPREAD_SOURCE_MASK));
1173         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174 }
1175
1176 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177                                            enum pipe pipe)
1178 {
1179         int reg;
1180         u32 val;
1181         bool enabled;
1182
1183         reg = PCH_TRANSCONF(pipe);
1184         val = I915_READ(reg);
1185         enabled = !!(val & TRANS_ENABLE);
1186         WARN(enabled,
1187              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188              pipe_name(pipe));
1189 }
1190
1191 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192                             enum pipe pipe, u32 port_sel, u32 val)
1193 {
1194         if ((val & DP_PORT_EN) == 0)
1195                 return false;
1196
1197         if (HAS_PCH_CPT(dev_priv->dev)) {
1198                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201                         return false;
1202         } else {
1203                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204                         return false;
1205         }
1206         return true;
1207 }
1208
1209 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210                               enum pipe pipe, u32 val)
1211 {
1212         if ((val & SDVO_ENABLE) == 0)
1213                 return false;
1214
1215         if (HAS_PCH_CPT(dev_priv->dev)) {
1216                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1217                         return false;
1218         } else {
1219                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1220                         return false;
1221         }
1222         return true;
1223 }
1224
1225 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226                               enum pipe pipe, u32 val)
1227 {
1228         if ((val & LVDS_PORT_EN) == 0)
1229                 return false;
1230
1231         if (HAS_PCH_CPT(dev_priv->dev)) {
1232                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233                         return false;
1234         } else {
1235                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236                         return false;
1237         }
1238         return true;
1239 }
1240
1241 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242                               enum pipe pipe, u32 val)
1243 {
1244         if ((val & ADPA_DAC_ENABLE) == 0)
1245                 return false;
1246         if (HAS_PCH_CPT(dev_priv->dev)) {
1247                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248                         return false;
1249         } else {
1250                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251                         return false;
1252         }
1253         return true;
1254 }
1255
1256 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1257                                    enum pipe pipe, int reg, u32 port_sel)
1258 {
1259         u32 val = I915_READ(reg);
1260         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1261              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1262              reg, pipe_name(pipe));
1263
1264         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265              && (val & DP_PIPEB_SELECT),
1266              "IBX PCH dp port still using transcoder B\n");
1267 }
1268
1269 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270                                      enum pipe pipe, int reg)
1271 {
1272         u32 val = I915_READ(reg);
1273         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1274              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1275              reg, pipe_name(pipe));
1276
1277         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1278              && (val & SDVO_PIPE_B_SELECT),
1279              "IBX PCH hdmi port still using transcoder B\n");
1280 }
1281
1282 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283                                       enum pipe pipe)
1284 {
1285         int reg;
1286         u32 val;
1287
1288         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1291
1292         reg = PCH_ADPA;
1293         val = I915_READ(reg);
1294         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1295              "PCH VGA enabled on transcoder %c, should be disabled\n",
1296              pipe_name(pipe));
1297
1298         reg = PCH_LVDS;
1299         val = I915_READ(reg);
1300         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1301              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1302              pipe_name(pipe));
1303
1304         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1307 }
1308
1309 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310 {
1311         int reg;
1312         u32 val;
1313
1314         assert_pipe_disabled(dev_priv, pipe);
1315
1316         /* No really, not for ILK+ */
1317         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319         /* PLL is protected by panel, make sure we can write it */
1320         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321                 assert_panel_unlocked(dev_priv, pipe);
1322
1323         reg = DPLL(pipe);
1324         val = I915_READ(reg);
1325         val |= DPLL_VCO_ENABLE;
1326
1327         /* We do this three times for luck */
1328         I915_WRITE(reg, val);
1329         POSTING_READ(reg);
1330         udelay(150); /* wait for warmup */
1331         I915_WRITE(reg, val);
1332         POSTING_READ(reg);
1333         udelay(150); /* wait for warmup */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337 }
1338
1339 static void i9xx_enable_pll(struct intel_crtc *crtc)
1340 {
1341         struct drm_device *dev = crtc->base.dev;
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         int reg = DPLL(crtc->pipe);
1344         u32 dpll = crtc->config.dpll_hw_state.dpll;
1345
1346         assert_pipe_disabled(dev_priv, crtc->pipe);
1347
1348         /* No really, not for ILK+ */
1349         BUG_ON(dev_priv->info->gen >= 5);
1350
1351         /* PLL is protected by panel, make sure we can write it */
1352         if (IS_MOBILE(dev) && !IS_I830(dev))
1353                 assert_panel_unlocked(dev_priv, crtc->pipe);
1354
1355         I915_WRITE(reg, dpll);
1356
1357         /* Wait for the clocks to stabilize. */
1358         POSTING_READ(reg);
1359         udelay(150);
1360
1361         if (INTEL_INFO(dev)->gen >= 4) {
1362                 I915_WRITE(DPLL_MD(crtc->pipe),
1363                            crtc->config.dpll_hw_state.dpll_md);
1364         } else {
1365                 /* The pixel multiplier can only be updated once the
1366                  * DPLL is enabled and the clocks are stable.
1367                  *
1368                  * So write it again.
1369                  */
1370                 I915_WRITE(reg, dpll);
1371         }
1372
1373         /* We do this three times for luck */
1374         I915_WRITE(reg, dpll);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, dpll);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380         I915_WRITE(reg, dpll);
1381         POSTING_READ(reg);
1382         udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386  * intel_disable_pll - disable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to disable
1389  *
1390  * Disable the PLL for @pipe, making sure the pipe is off first.
1391  *
1392  * Note!  This is for pre-ILK only.
1393  */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396         int reg;
1397         u32 val;
1398
1399         /* Don't disable pipe A or pipe A PLLs if needed */
1400         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401                 return;
1402
1403         /* Make sure the pipe isn't still relying on us */
1404         assert_pipe_disabled(dev_priv, pipe);
1405
1406         reg = DPLL(pipe);
1407         val = I915_READ(reg);
1408         val &= ~DPLL_VCO_ENABLE;
1409         I915_WRITE(reg, val);
1410         POSTING_READ(reg);
1411 }
1412
1413 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414 {
1415         u32 port_mask;
1416
1417         if (!port)
1418                 port_mask = DPLL_PORTB_READY_MASK;
1419         else
1420                 port_mask = DPLL_PORTC_READY_MASK;
1421
1422         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424                      'B' + port, I915_READ(DPLL(0)));
1425 }
1426
1427 /**
1428  * ironlake_enable_shared_dpll - enable PCH PLL
1429  * @dev_priv: i915 private structure
1430  * @pipe: pipe PLL to enable
1431  *
1432  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433  * drives the transcoder clock.
1434  */
1435 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1436 {
1437         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1439
1440         /* PCH PLLs only available on ILK, SNB and IVB */
1441         BUG_ON(dev_priv->info->gen < 5);
1442         if (WARN_ON(pll == NULL))
1443                 return;
1444
1445         if (WARN_ON(pll->refcount == 0))
1446                 return;
1447
1448         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449                       pll->name, pll->active, pll->on,
1450                       crtc->base.base.id);
1451
1452         if (pll->active++) {
1453                 WARN_ON(!pll->on);
1454                 assert_shared_dpll_enabled(dev_priv, pll);
1455                 return;
1456         }
1457         WARN_ON(pll->on);
1458
1459         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1460         pll->enable(dev_priv, pll);
1461         pll->on = true;
1462 }
1463
1464 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1465 {
1466         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1468
1469         /* PCH only available on ILK+ */
1470         BUG_ON(dev_priv->info->gen < 5);
1471         if (WARN_ON(pll == NULL))
1472                return;
1473
1474         if (WARN_ON(pll->refcount == 0))
1475                 return;
1476
1477         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478                       pll->name, pll->active, pll->on,
1479                       crtc->base.base.id);
1480
1481         if (WARN_ON(pll->active == 0)) {
1482                 assert_shared_dpll_disabled(dev_priv, pll);
1483                 return;
1484         }
1485
1486         assert_shared_dpll_enabled(dev_priv, pll);
1487         WARN_ON(!pll->on);
1488         if (--pll->active)
1489                 return;
1490
1491         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1492         pll->disable(dev_priv, pll);
1493         pll->on = false;
1494 }
1495
1496 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497                                            enum pipe pipe)
1498 {
1499         struct drm_device *dev = dev_priv->dev;
1500         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1502         uint32_t reg, val, pipeconf_val;
1503
1504         /* PCH only available on ILK+ */
1505         BUG_ON(dev_priv->info->gen < 5);
1506
1507         /* Make sure PCH DPLL is enabled */
1508         assert_shared_dpll_enabled(dev_priv,
1509                                    intel_crtc_to_shared_dpll(intel_crtc));
1510
1511         /* FDI must be feeding us bits for PCH ports */
1512         assert_fdi_tx_enabled(dev_priv, pipe);
1513         assert_fdi_rx_enabled(dev_priv, pipe);
1514
1515         if (HAS_PCH_CPT(dev)) {
1516                 /* Workaround: Set the timing override bit before enabling the
1517                  * pch transcoder. */
1518                 reg = TRANS_CHICKEN2(pipe);
1519                 val = I915_READ(reg);
1520                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521                 I915_WRITE(reg, val);
1522         }
1523
1524         reg = PCH_TRANSCONF(pipe);
1525         val = I915_READ(reg);
1526         pipeconf_val = I915_READ(PIPECONF(pipe));
1527
1528         if (HAS_PCH_IBX(dev_priv->dev)) {
1529                 /*
1530                  * make the BPC in transcoder be consistent with
1531                  * that in pipeconf reg.
1532                  */
1533                 val &= ~PIPECONF_BPC_MASK;
1534                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1535         }
1536
1537         val &= ~TRANS_INTERLACE_MASK;
1538         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1539                 if (HAS_PCH_IBX(dev_priv->dev) &&
1540                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541                         val |= TRANS_LEGACY_INTERLACED_ILK;
1542                 else
1543                         val |= TRANS_INTERLACED;
1544         else
1545                 val |= TRANS_PROGRESSIVE;
1546
1547         I915_WRITE(reg, val | TRANS_ENABLE);
1548         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1549                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1550 }
1551
1552 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553                                       enum transcoder cpu_transcoder)
1554 {
1555         u32 val, pipeconf_val;
1556
1557         /* PCH only available on ILK+ */
1558         BUG_ON(dev_priv->info->gen < 5);
1559
1560         /* FDI must be feeding us bits for PCH ports */
1561         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1562         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1563
1564         /* Workaround: set timing override bit. */
1565         val = I915_READ(_TRANSA_CHICKEN2);
1566         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1567         I915_WRITE(_TRANSA_CHICKEN2, val);
1568
1569         val = TRANS_ENABLE;
1570         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1571
1572         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573             PIPECONF_INTERLACED_ILK)
1574                 val |= TRANS_INTERLACED;
1575         else
1576                 val |= TRANS_PROGRESSIVE;
1577
1578         I915_WRITE(LPT_TRANSCONF, val);
1579         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1580                 DRM_ERROR("Failed to enable PCH transcoder\n");
1581 }
1582
1583 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584                                             enum pipe pipe)
1585 {
1586         struct drm_device *dev = dev_priv->dev;
1587         uint32_t reg, val;
1588
1589         /* FDI relies on the transcoder */
1590         assert_fdi_tx_disabled(dev_priv, pipe);
1591         assert_fdi_rx_disabled(dev_priv, pipe);
1592
1593         /* Ports must be off as well */
1594         assert_pch_ports_disabled(dev_priv, pipe);
1595
1596         reg = PCH_TRANSCONF(pipe);
1597         val = I915_READ(reg);
1598         val &= ~TRANS_ENABLE;
1599         I915_WRITE(reg, val);
1600         /* wait for PCH transcoder off, transcoder state */
1601         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1602                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1603
1604         if (!HAS_PCH_IBX(dev)) {
1605                 /* Workaround: Clear the timing override chicken bit again. */
1606                 reg = TRANS_CHICKEN2(pipe);
1607                 val = I915_READ(reg);
1608                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609                 I915_WRITE(reg, val);
1610         }
1611 }
1612
1613 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1614 {
1615         u32 val;
1616
1617         val = I915_READ(LPT_TRANSCONF);
1618         val &= ~TRANS_ENABLE;
1619         I915_WRITE(LPT_TRANSCONF, val);
1620         /* wait for PCH transcoder off, transcoder state */
1621         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1622                 DRM_ERROR("Failed to disable PCH transcoder\n");
1623
1624         /* Workaround: clear timing override bit. */
1625         val = I915_READ(_TRANSA_CHICKEN2);
1626         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1627         I915_WRITE(_TRANSA_CHICKEN2, val);
1628 }
1629
1630 /**
1631  * intel_enable_pipe - enable a pipe, asserting requirements
1632  * @dev_priv: i915 private structure
1633  * @pipe: pipe to enable
1634  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1635  *
1636  * Enable @pipe, making sure that various hardware specific requirements
1637  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638  *
1639  * @pipe should be %PIPE_A or %PIPE_B.
1640  *
1641  * Will wait until the pipe is actually running (i.e. first vblank) before
1642  * returning.
1643  */
1644 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645                               bool pch_port)
1646 {
1647         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648                                                                       pipe);
1649         enum pipe pch_transcoder;
1650         int reg;
1651         u32 val;
1652
1653         assert_planes_disabled(dev_priv, pipe);
1654         assert_sprites_disabled(dev_priv, pipe);
1655
1656         if (HAS_PCH_LPT(dev_priv->dev))
1657                 pch_transcoder = TRANSCODER_A;
1658         else
1659                 pch_transcoder = pipe;
1660
1661         /*
1662          * A pipe without a PLL won't actually be able to drive bits from
1663          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1664          * need the check.
1665          */
1666         if (!HAS_PCH_SPLIT(dev_priv->dev))
1667                 assert_pll_enabled(dev_priv, pipe);
1668         else {
1669                 if (pch_port) {
1670                         /* if driving the PCH, we need FDI enabled */
1671                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1672                         assert_fdi_tx_pll_enabled(dev_priv,
1673                                                   (enum pipe) cpu_transcoder);
1674                 }
1675                 /* FIXME: assert CPU port conditions for SNB+ */
1676         }
1677
1678         reg = PIPECONF(cpu_transcoder);
1679         val = I915_READ(reg);
1680         if (val & PIPECONF_ENABLE)
1681                 return;
1682
1683         I915_WRITE(reg, val | PIPECONF_ENABLE);
1684         intel_wait_for_vblank(dev_priv->dev, pipe);
1685 }
1686
1687 /**
1688  * intel_disable_pipe - disable a pipe, asserting requirements
1689  * @dev_priv: i915 private structure
1690  * @pipe: pipe to disable
1691  *
1692  * Disable @pipe, making sure that various hardware specific requirements
1693  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694  *
1695  * @pipe should be %PIPE_A or %PIPE_B.
1696  *
1697  * Will wait until the pipe has shut down before returning.
1698  */
1699 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700                                enum pipe pipe)
1701 {
1702         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703                                                                       pipe);
1704         int reg;
1705         u32 val;
1706
1707         /*
1708          * Make sure planes won't keep trying to pump pixels to us,
1709          * or we might hang the display.
1710          */
1711         assert_planes_disabled(dev_priv, pipe);
1712         assert_sprites_disabled(dev_priv, pipe);
1713
1714         /* Don't disable pipe A or pipe A PLLs if needed */
1715         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716                 return;
1717
1718         reg = PIPECONF(cpu_transcoder);
1719         val = I915_READ(reg);
1720         if ((val & PIPECONF_ENABLE) == 0)
1721                 return;
1722
1723         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1724         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725 }
1726
1727 /*
1728  * Plane regs are double buffered, going from enabled->disabled needs a
1729  * trigger in order to latch.  The display address reg provides this.
1730  */
1731 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1732                                       enum plane plane)
1733 {
1734         if (dev_priv->info->gen >= 4)
1735                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736         else
1737                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1738 }
1739
1740 /**
1741  * intel_enable_plane - enable a display plane on a given pipe
1742  * @dev_priv: i915 private structure
1743  * @plane: plane to enable
1744  * @pipe: pipe being fed
1745  *
1746  * Enable @plane on @pipe, making sure that @pipe is running first.
1747  */
1748 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749                                enum plane plane, enum pipe pipe)
1750 {
1751         int reg;
1752         u32 val;
1753
1754         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755         assert_pipe_enabled(dev_priv, pipe);
1756
1757         reg = DSPCNTR(plane);
1758         val = I915_READ(reg);
1759         if (val & DISPLAY_PLANE_ENABLE)
1760                 return;
1761
1762         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1763         intel_flush_display_plane(dev_priv, plane);
1764         intel_wait_for_vblank(dev_priv->dev, pipe);
1765 }
1766
1767 /**
1768  * intel_disable_plane - disable a display plane
1769  * @dev_priv: i915 private structure
1770  * @plane: plane to disable
1771  * @pipe: pipe consuming the data
1772  *
1773  * Disable @plane; should be an independent operation.
1774  */
1775 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776                                 enum plane plane, enum pipe pipe)
1777 {
1778         int reg;
1779         u32 val;
1780
1781         reg = DSPCNTR(plane);
1782         val = I915_READ(reg);
1783         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784                 return;
1785
1786         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1787         intel_flush_display_plane(dev_priv, plane);
1788         intel_wait_for_vblank(dev_priv->dev, pipe);
1789 }
1790
1791 static bool need_vtd_wa(struct drm_device *dev)
1792 {
1793 #ifdef CONFIG_INTEL_IOMMU
1794         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795                 return true;
1796 #endif
1797         return false;
1798 }
1799
1800 int
1801 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1802                            struct drm_i915_gem_object *obj,
1803                            struct intel_ring_buffer *pipelined)
1804 {
1805         struct drm_i915_private *dev_priv = dev->dev_private;
1806         u32 alignment;
1807         int ret;
1808
1809         switch (obj->tiling_mode) {
1810         case I915_TILING_NONE:
1811                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812                         alignment = 128 * 1024;
1813                 else if (INTEL_INFO(dev)->gen >= 4)
1814                         alignment = 4 * 1024;
1815                 else
1816                         alignment = 64 * 1024;
1817                 break;
1818         case I915_TILING_X:
1819                 /* pin() will align the object as required by fence */
1820                 alignment = 0;
1821                 break;
1822         case I915_TILING_Y:
1823                 /* Despite that we check this in framebuffer_init userspace can
1824                  * screw us over and change the tiling after the fact. Only
1825                  * pinned buffers can't change their tiling. */
1826                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1827                 return -EINVAL;
1828         default:
1829                 BUG();
1830         }
1831
1832         /* Note that the w/a also requires 64 PTE of padding following the
1833          * bo. We currently fill all unused PTE with the shadow page and so
1834          * we should always have valid PTE following the scanout preventing
1835          * the VT-d warning.
1836          */
1837         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838                 alignment = 256 * 1024;
1839
1840         dev_priv->mm.interruptible = false;
1841         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1842         if (ret)
1843                 goto err_interruptible;
1844
1845         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846          * fence, whereas 965+ only requires a fence if using
1847          * framebuffer compression.  For simplicity, we always install
1848          * a fence as the cost is not that onerous.
1849          */
1850         ret = i915_gem_object_get_fence(obj);
1851         if (ret)
1852                 goto err_unpin;
1853
1854         i915_gem_object_pin_fence(obj);
1855
1856         dev_priv->mm.interruptible = true;
1857         return 0;
1858
1859 err_unpin:
1860         i915_gem_object_unpin(obj);
1861 err_interruptible:
1862         dev_priv->mm.interruptible = true;
1863         return ret;
1864 }
1865
1866 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867 {
1868         i915_gem_object_unpin_fence(obj);
1869         i915_gem_object_unpin(obj);
1870 }
1871
1872 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873  * is assumed to be a power-of-two. */
1874 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875                                              unsigned int tiling_mode,
1876                                              unsigned int cpp,
1877                                              unsigned int pitch)
1878 {
1879         if (tiling_mode != I915_TILING_NONE) {
1880                 unsigned int tile_rows, tiles;
1881
1882                 tile_rows = *y / 8;
1883                 *y %= 8;
1884
1885                 tiles = *x / (512/cpp);
1886                 *x %= 512/cpp;
1887
1888                 return tile_rows * pitch * 8 + tiles * 4096;
1889         } else {
1890                 unsigned int offset;
1891
1892                 offset = *y * pitch + *x * cpp;
1893                 *y = 0;
1894                 *x = (offset & 4095) / cpp;
1895                 return offset & -4096;
1896         }
1897 }
1898
1899 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900                              int x, int y)
1901 {
1902         struct drm_device *dev = crtc->dev;
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905         struct intel_framebuffer *intel_fb;
1906         struct drm_i915_gem_object *obj;
1907         int plane = intel_crtc->plane;
1908         unsigned long linear_offset;
1909         u32 dspcntr;
1910         u32 reg;
1911
1912         switch (plane) {
1913         case 0:
1914         case 1:
1915                 break;
1916         default:
1917                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1918                 return -EINVAL;
1919         }
1920
1921         intel_fb = to_intel_framebuffer(fb);
1922         obj = intel_fb->obj;
1923
1924         reg = DSPCNTR(plane);
1925         dspcntr = I915_READ(reg);
1926         /* Mask out pixel format bits in case we change it */
1927         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1928         switch (fb->pixel_format) {
1929         case DRM_FORMAT_C8:
1930                 dspcntr |= DISPPLANE_8BPP;
1931                 break;
1932         case DRM_FORMAT_XRGB1555:
1933         case DRM_FORMAT_ARGB1555:
1934                 dspcntr |= DISPPLANE_BGRX555;
1935                 break;
1936         case DRM_FORMAT_RGB565:
1937                 dspcntr |= DISPPLANE_BGRX565;
1938                 break;
1939         case DRM_FORMAT_XRGB8888:
1940         case DRM_FORMAT_ARGB8888:
1941                 dspcntr |= DISPPLANE_BGRX888;
1942                 break;
1943         case DRM_FORMAT_XBGR8888:
1944         case DRM_FORMAT_ABGR8888:
1945                 dspcntr |= DISPPLANE_RGBX888;
1946                 break;
1947         case DRM_FORMAT_XRGB2101010:
1948         case DRM_FORMAT_ARGB2101010:
1949                 dspcntr |= DISPPLANE_BGRX101010;
1950                 break;
1951         case DRM_FORMAT_XBGR2101010:
1952         case DRM_FORMAT_ABGR2101010:
1953                 dspcntr |= DISPPLANE_RGBX101010;
1954                 break;
1955         default:
1956                 BUG();
1957         }
1958
1959         if (INTEL_INFO(dev)->gen >= 4) {
1960                 if (obj->tiling_mode != I915_TILING_NONE)
1961                         dspcntr |= DISPPLANE_TILED;
1962                 else
1963                         dspcntr &= ~DISPPLANE_TILED;
1964         }
1965
1966         if (IS_G4X(dev))
1967                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
1969         I915_WRITE(reg, dspcntr);
1970
1971         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1972
1973         if (INTEL_INFO(dev)->gen >= 4) {
1974                 intel_crtc->dspaddr_offset =
1975                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976                                                        fb->bits_per_pixel / 8,
1977                                                        fb->pitches[0]);
1978                 linear_offset -= intel_crtc->dspaddr_offset;
1979         } else {
1980                 intel_crtc->dspaddr_offset = linear_offset;
1981         }
1982
1983         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1985         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1986         if (INTEL_INFO(dev)->gen >= 4) {
1987                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1989                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1990                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1991         } else
1992                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1993         POSTING_READ(reg);
1994
1995         return 0;
1996 }
1997
1998 static int ironlake_update_plane(struct drm_crtc *crtc,
1999                                  struct drm_framebuffer *fb, int x, int y)
2000 {
2001         struct drm_device *dev = crtc->dev;
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004         struct intel_framebuffer *intel_fb;
2005         struct drm_i915_gem_object *obj;
2006         int plane = intel_crtc->plane;
2007         unsigned long linear_offset;
2008         u32 dspcntr;
2009         u32 reg;
2010
2011         switch (plane) {
2012         case 0:
2013         case 1:
2014         case 2:
2015                 break;
2016         default:
2017                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2018                 return -EINVAL;
2019         }
2020
2021         intel_fb = to_intel_framebuffer(fb);
2022         obj = intel_fb->obj;
2023
2024         reg = DSPCNTR(plane);
2025         dspcntr = I915_READ(reg);
2026         /* Mask out pixel format bits in case we change it */
2027         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2028         switch (fb->pixel_format) {
2029         case DRM_FORMAT_C8:
2030                 dspcntr |= DISPPLANE_8BPP;
2031                 break;
2032         case DRM_FORMAT_RGB565:
2033                 dspcntr |= DISPPLANE_BGRX565;
2034                 break;
2035         case DRM_FORMAT_XRGB8888:
2036         case DRM_FORMAT_ARGB8888:
2037                 dspcntr |= DISPPLANE_BGRX888;
2038                 break;
2039         case DRM_FORMAT_XBGR8888:
2040         case DRM_FORMAT_ABGR8888:
2041                 dspcntr |= DISPPLANE_RGBX888;
2042                 break;
2043         case DRM_FORMAT_XRGB2101010:
2044         case DRM_FORMAT_ARGB2101010:
2045                 dspcntr |= DISPPLANE_BGRX101010;
2046                 break;
2047         case DRM_FORMAT_XBGR2101010:
2048         case DRM_FORMAT_ABGR2101010:
2049                 dspcntr |= DISPPLANE_RGBX101010;
2050                 break;
2051         default:
2052                 BUG();
2053         }
2054
2055         if (obj->tiling_mode != I915_TILING_NONE)
2056                 dspcntr |= DISPPLANE_TILED;
2057         else
2058                 dspcntr &= ~DISPPLANE_TILED;
2059
2060         /* must disable */
2061         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2062
2063         I915_WRITE(reg, dspcntr);
2064
2065         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2066         intel_crtc->dspaddr_offset =
2067                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068                                                fb->bits_per_pixel / 8,
2069                                                fb->pitches[0]);
2070         linear_offset -= intel_crtc->dspaddr_offset;
2071
2072         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2074         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2075         I915_MODIFY_DISPBASE(DSPSURF(plane),
2076                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2077         if (IS_HASWELL(dev)) {
2078                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2079         } else {
2080                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2082         }
2083         POSTING_READ(reg);
2084
2085         return 0;
2086 }
2087
2088 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2089 static int
2090 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091                            int x, int y, enum mode_set_atomic state)
2092 {
2093         struct drm_device *dev = crtc->dev;
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095
2096         if (dev_priv->display.disable_fbc)
2097                 dev_priv->display.disable_fbc(dev);
2098         intel_increase_pllclock(crtc);
2099
2100         return dev_priv->display.update_plane(crtc, fb, x, y);
2101 }
2102
2103 void intel_display_handle_reset(struct drm_device *dev)
2104 {
2105         struct drm_i915_private *dev_priv = dev->dev_private;
2106         struct drm_crtc *crtc;
2107
2108         /*
2109          * Flips in the rings have been nuked by the reset,
2110          * so complete all pending flips so that user space
2111          * will get its events and not get stuck.
2112          *
2113          * Also update the base address of all primary
2114          * planes to the the last fb to make sure we're
2115          * showing the correct fb after a reset.
2116          *
2117          * Need to make two loops over the crtcs so that we
2118          * don't try to grab a crtc mutex before the
2119          * pending_flip_queue really got woken up.
2120          */
2121
2122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124                 enum plane plane = intel_crtc->plane;
2125
2126                 intel_prepare_page_flip(dev, plane);
2127                 intel_finish_page_flip_plane(dev, plane);
2128         }
2129
2130         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133                 mutex_lock(&crtc->mutex);
2134                 if (intel_crtc->active)
2135                         dev_priv->display.update_plane(crtc, crtc->fb,
2136                                                        crtc->x, crtc->y);
2137                 mutex_unlock(&crtc->mutex);
2138         }
2139 }
2140
2141 static int
2142 intel_finish_fb(struct drm_framebuffer *old_fb)
2143 {
2144         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146         bool was_interruptible = dev_priv->mm.interruptible;
2147         int ret;
2148
2149         /* Big Hammer, we also need to ensure that any pending
2150          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151          * current scanout is retired before unpinning the old
2152          * framebuffer.
2153          *
2154          * This should only fail upon a hung GPU, in which case we
2155          * can safely continue.
2156          */
2157         dev_priv->mm.interruptible = false;
2158         ret = i915_gem_object_finish_gpu(obj);
2159         dev_priv->mm.interruptible = was_interruptible;
2160
2161         return ret;
2162 }
2163
2164 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2165 {
2166         struct drm_device *dev = crtc->dev;
2167         struct drm_i915_master_private *master_priv;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170         if (!dev->primary->master)
2171                 return;
2172
2173         master_priv = dev->primary->master->driver_priv;
2174         if (!master_priv->sarea_priv)
2175                 return;
2176
2177         switch (intel_crtc->pipe) {
2178         case 0:
2179                 master_priv->sarea_priv->pipeA_x = x;
2180                 master_priv->sarea_priv->pipeA_y = y;
2181                 break;
2182         case 1:
2183                 master_priv->sarea_priv->pipeB_x = x;
2184                 master_priv->sarea_priv->pipeB_y = y;
2185                 break;
2186         default:
2187                 break;
2188         }
2189 }
2190
2191 static int
2192 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2193                     struct drm_framebuffer *fb)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198         struct drm_framebuffer *old_fb;
2199         int ret;
2200
2201         /* no fb bound */
2202         if (!fb) {
2203                 DRM_ERROR("No FB bound\n");
2204                 return 0;
2205         }
2206
2207         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2208                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209                           plane_name(intel_crtc->plane),
2210                           INTEL_INFO(dev)->num_pipes);
2211                 return -EINVAL;
2212         }
2213
2214         mutex_lock(&dev->struct_mutex);
2215         ret = intel_pin_and_fence_fb_obj(dev,
2216                                          to_intel_framebuffer(fb)->obj,
2217                                          NULL);
2218         if (ret != 0) {
2219                 mutex_unlock(&dev->struct_mutex);
2220                 DRM_ERROR("pin & fence failed\n");
2221                 return ret;
2222         }
2223
2224         /* Update pipe size and adjust fitter if needed */
2225         if (i915_fastboot) {
2226                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2227                            ((crtc->mode.hdisplay - 1) << 16) |
2228                            (crtc->mode.vdisplay - 1));
2229                 if (!intel_crtc->config.pch_pfit.size &&
2230                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2231                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2232                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2233                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2234                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2235                 }
2236         }
2237
2238         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2239         if (ret) {
2240                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2241                 mutex_unlock(&dev->struct_mutex);
2242                 DRM_ERROR("failed to update base address\n");
2243                 return ret;
2244         }
2245
2246         old_fb = crtc->fb;
2247         crtc->fb = fb;
2248         crtc->x = x;
2249         crtc->y = y;
2250
2251         if (old_fb) {
2252                 if (intel_crtc->active && old_fb != fb)
2253                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2254                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2255         }
2256
2257         intel_update_fbc(dev);
2258         mutex_unlock(&dev->struct_mutex);
2259
2260         intel_crtc_update_sarea_pos(crtc, x, y);
2261
2262         return 0;
2263 }
2264
2265 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2266 {
2267         struct drm_device *dev = crtc->dev;
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270         int pipe = intel_crtc->pipe;
2271         u32 reg, temp;
2272
2273         /* enable normal train */
2274         reg = FDI_TX_CTL(pipe);
2275         temp = I915_READ(reg);
2276         if (IS_IVYBRIDGE(dev)) {
2277                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2278                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2279         } else {
2280                 temp &= ~FDI_LINK_TRAIN_NONE;
2281                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2282         }
2283         I915_WRITE(reg, temp);
2284
2285         reg = FDI_RX_CTL(pipe);
2286         temp = I915_READ(reg);
2287         if (HAS_PCH_CPT(dev)) {
2288                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2289                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2290         } else {
2291                 temp &= ~FDI_LINK_TRAIN_NONE;
2292                 temp |= FDI_LINK_TRAIN_NONE;
2293         }
2294         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2295
2296         /* wait one idle pattern time */
2297         POSTING_READ(reg);
2298         udelay(1000);
2299
2300         /* IVB wants error correction enabled */
2301         if (IS_IVYBRIDGE(dev))
2302                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2303                            FDI_FE_ERRC_ENABLE);
2304 }
2305
2306 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2307 {
2308         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2309 }
2310
2311 static void ivb_modeset_global_resources(struct drm_device *dev)
2312 {
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         struct intel_crtc *pipe_B_crtc =
2315                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2316         struct intel_crtc *pipe_C_crtc =
2317                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2318         uint32_t temp;
2319
2320         /*
2321          * When everything is off disable fdi C so that we could enable fdi B
2322          * with all lanes. Note that we don't care about enabled pipes without
2323          * an enabled pch encoder.
2324          */
2325         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2326             !pipe_has_enabled_pch(pipe_C_crtc)) {
2327                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2328                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2329
2330                 temp = I915_READ(SOUTH_CHICKEN1);
2331                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2332                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2333                 I915_WRITE(SOUTH_CHICKEN1, temp);
2334         }
2335 }
2336
2337 /* The FDI link training functions for ILK/Ibexpeak. */
2338 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2339 {
2340         struct drm_device *dev = crtc->dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343         int pipe = intel_crtc->pipe;
2344         int plane = intel_crtc->plane;
2345         u32 reg, temp, tries;
2346
2347         /* FDI needs bits from pipe & plane first */
2348         assert_pipe_enabled(dev_priv, pipe);
2349         assert_plane_enabled(dev_priv, plane);
2350
2351         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2352            for train result */
2353         reg = FDI_RX_IMR(pipe);
2354         temp = I915_READ(reg);
2355         temp &= ~FDI_RX_SYMBOL_LOCK;
2356         temp &= ~FDI_RX_BIT_LOCK;
2357         I915_WRITE(reg, temp);
2358         I915_READ(reg);
2359         udelay(150);
2360
2361         /* enable CPU FDI TX and PCH FDI RX */
2362         reg = FDI_TX_CTL(pipe);
2363         temp = I915_READ(reg);
2364         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2365         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2366         temp &= ~FDI_LINK_TRAIN_NONE;
2367         temp |= FDI_LINK_TRAIN_PATTERN_1;
2368         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2369
2370         reg = FDI_RX_CTL(pipe);
2371         temp = I915_READ(reg);
2372         temp &= ~FDI_LINK_TRAIN_NONE;
2373         temp |= FDI_LINK_TRAIN_PATTERN_1;
2374         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2375
2376         POSTING_READ(reg);
2377         udelay(150);
2378
2379         /* Ironlake workaround, enable clock pointer after FDI enable*/
2380         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2381         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2382                    FDI_RX_PHASE_SYNC_POINTER_EN);
2383
2384         reg = FDI_RX_IIR(pipe);
2385         for (tries = 0; tries < 5; tries++) {
2386                 temp = I915_READ(reg);
2387                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2388
2389                 if ((temp & FDI_RX_BIT_LOCK)) {
2390                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2391                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2392                         break;
2393                 }
2394         }
2395         if (tries == 5)
2396                 DRM_ERROR("FDI train 1 fail!\n");
2397
2398         /* Train 2 */
2399         reg = FDI_TX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         temp &= ~FDI_LINK_TRAIN_NONE;
2402         temp |= FDI_LINK_TRAIN_PATTERN_2;
2403         I915_WRITE(reg, temp);
2404
2405         reg = FDI_RX_CTL(pipe);
2406         temp = I915_READ(reg);
2407         temp &= ~FDI_LINK_TRAIN_NONE;
2408         temp |= FDI_LINK_TRAIN_PATTERN_2;
2409         I915_WRITE(reg, temp);
2410
2411         POSTING_READ(reg);
2412         udelay(150);
2413
2414         reg = FDI_RX_IIR(pipe);
2415         for (tries = 0; tries < 5; tries++) {
2416                 temp = I915_READ(reg);
2417                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2418
2419                 if (temp & FDI_RX_SYMBOL_LOCK) {
2420                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2421                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2422                         break;
2423                 }
2424         }
2425         if (tries == 5)
2426                 DRM_ERROR("FDI train 2 fail!\n");
2427
2428         DRM_DEBUG_KMS("FDI train done\n");
2429
2430 }
2431
2432 static const int snb_b_fdi_train_param[] = {
2433         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2434         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2435         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2436         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2437 };
2438
2439 /* The FDI link training functions for SNB/Cougarpoint. */
2440 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2441 {
2442         struct drm_device *dev = crtc->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445         int pipe = intel_crtc->pipe;
2446         u32 reg, temp, i, retry;
2447
2448         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2449            for train result */
2450         reg = FDI_RX_IMR(pipe);
2451         temp = I915_READ(reg);
2452         temp &= ~FDI_RX_SYMBOL_LOCK;
2453         temp &= ~FDI_RX_BIT_LOCK;
2454         I915_WRITE(reg, temp);
2455
2456         POSTING_READ(reg);
2457         udelay(150);
2458
2459         /* enable CPU FDI TX and PCH FDI RX */
2460         reg = FDI_TX_CTL(pipe);
2461         temp = I915_READ(reg);
2462         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2463         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2464         temp &= ~FDI_LINK_TRAIN_NONE;
2465         temp |= FDI_LINK_TRAIN_PATTERN_1;
2466         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2467         /* SNB-B */
2468         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2469         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2470
2471         I915_WRITE(FDI_RX_MISC(pipe),
2472                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2473
2474         reg = FDI_RX_CTL(pipe);
2475         temp = I915_READ(reg);
2476         if (HAS_PCH_CPT(dev)) {
2477                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479         } else {
2480                 temp &= ~FDI_LINK_TRAIN_NONE;
2481                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482         }
2483         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485         POSTING_READ(reg);
2486         udelay(150);
2487
2488         for (i = 0; i < 4; i++) {
2489                 reg = FDI_TX_CTL(pipe);
2490                 temp = I915_READ(reg);
2491                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492                 temp |= snb_b_fdi_train_param[i];
2493                 I915_WRITE(reg, temp);
2494
2495                 POSTING_READ(reg);
2496                 udelay(500);
2497
2498                 for (retry = 0; retry < 5; retry++) {
2499                         reg = FDI_RX_IIR(pipe);
2500                         temp = I915_READ(reg);
2501                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2502                         if (temp & FDI_RX_BIT_LOCK) {
2503                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2504                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2505                                 break;
2506                         }
2507                         udelay(50);
2508                 }
2509                 if (retry < 5)
2510                         break;
2511         }
2512         if (i == 4)
2513                 DRM_ERROR("FDI train 1 fail!\n");
2514
2515         /* Train 2 */
2516         reg = FDI_TX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_LINK_TRAIN_NONE;
2519         temp |= FDI_LINK_TRAIN_PATTERN_2;
2520         if (IS_GEN6(dev)) {
2521                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2522                 /* SNB-B */
2523                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2524         }
2525         I915_WRITE(reg, temp);
2526
2527         reg = FDI_RX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         if (HAS_PCH_CPT(dev)) {
2530                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2531                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2532         } else {
2533                 temp &= ~FDI_LINK_TRAIN_NONE;
2534                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2535         }
2536         I915_WRITE(reg, temp);
2537
2538         POSTING_READ(reg);
2539         udelay(150);
2540
2541         for (i = 0; i < 4; i++) {
2542                 reg = FDI_TX_CTL(pipe);
2543                 temp = I915_READ(reg);
2544                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545                 temp |= snb_b_fdi_train_param[i];
2546                 I915_WRITE(reg, temp);
2547
2548                 POSTING_READ(reg);
2549                 udelay(500);
2550
2551                 for (retry = 0; retry < 5; retry++) {
2552                         reg = FDI_RX_IIR(pipe);
2553                         temp = I915_READ(reg);
2554                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2555                         if (temp & FDI_RX_SYMBOL_LOCK) {
2556                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558                                 break;
2559                         }
2560                         udelay(50);
2561                 }
2562                 if (retry < 5)
2563                         break;
2564         }
2565         if (i == 4)
2566                 DRM_ERROR("FDI train 2 fail!\n");
2567
2568         DRM_DEBUG_KMS("FDI train done.\n");
2569 }
2570
2571 /* Manual link training for Ivy Bridge A0 parts */
2572 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2573 {
2574         struct drm_device *dev = crtc->dev;
2575         struct drm_i915_private *dev_priv = dev->dev_private;
2576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577         int pipe = intel_crtc->pipe;
2578         u32 reg, temp, i;
2579
2580         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2581            for train result */
2582         reg = FDI_RX_IMR(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_RX_SYMBOL_LOCK;
2585         temp &= ~FDI_RX_BIT_LOCK;
2586         I915_WRITE(reg, temp);
2587
2588         POSTING_READ(reg);
2589         udelay(150);
2590
2591         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2592                       I915_READ(FDI_RX_IIR(pipe)));
2593
2594         /* enable CPU FDI TX and PCH FDI RX */
2595         reg = FDI_TX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2598         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2599         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603         temp |= FDI_COMPOSITE_SYNC;
2604         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
2606         I915_WRITE(FDI_RX_MISC(pipe),
2607                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2608
2609         reg = FDI_RX_CTL(pipe);
2610         temp = I915_READ(reg);
2611         temp &= ~FDI_LINK_TRAIN_AUTO;
2612         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2613         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2614         temp |= FDI_COMPOSITE_SYNC;
2615         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2616
2617         POSTING_READ(reg);
2618         udelay(150);
2619
2620         for (i = 0; i < 4; i++) {
2621                 reg = FDI_TX_CTL(pipe);
2622                 temp = I915_READ(reg);
2623                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624                 temp |= snb_b_fdi_train_param[i];
2625                 I915_WRITE(reg, temp);
2626
2627                 POSTING_READ(reg);
2628                 udelay(500);
2629
2630                 reg = FDI_RX_IIR(pipe);
2631                 temp = I915_READ(reg);
2632                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634                 if (temp & FDI_RX_BIT_LOCK ||
2635                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2638                         break;
2639                 }
2640         }
2641         if (i == 4)
2642                 DRM_ERROR("FDI train 1 fail!\n");
2643
2644         /* Train 2 */
2645         reg = FDI_TX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651         I915_WRITE(reg, temp);
2652
2653         reg = FDI_RX_CTL(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657         I915_WRITE(reg, temp);
2658
2659         POSTING_READ(reg);
2660         udelay(150);
2661
2662         for (i = 0; i < 4; i++) {
2663                 reg = FDI_TX_CTL(pipe);
2664                 temp = I915_READ(reg);
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[i];
2667                 I915_WRITE(reg, temp);
2668
2669                 POSTING_READ(reg);
2670                 udelay(500);
2671
2672                 reg = FDI_RX_IIR(pipe);
2673                 temp = I915_READ(reg);
2674                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676                 if (temp & FDI_RX_SYMBOL_LOCK) {
2677                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2679                         break;
2680                 }
2681         }
2682         if (i == 4)
2683                 DRM_ERROR("FDI train 2 fail!\n");
2684
2685         DRM_DEBUG_KMS("FDI train done.\n");
2686 }
2687
2688 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2689 {
2690         struct drm_device *dev = intel_crtc->base.dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         int pipe = intel_crtc->pipe;
2693         u32 reg, temp;
2694
2695
2696         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2697         reg = FDI_RX_CTL(pipe);
2698         temp = I915_READ(reg);
2699         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2700         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2701         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2702         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2703
2704         POSTING_READ(reg);
2705         udelay(200);
2706
2707         /* Switch from Rawclk to PCDclk */
2708         temp = I915_READ(reg);
2709         I915_WRITE(reg, temp | FDI_PCDCLK);
2710
2711         POSTING_READ(reg);
2712         udelay(200);
2713
2714         /* Enable CPU FDI TX PLL, always on for Ironlake */
2715         reg = FDI_TX_CTL(pipe);
2716         temp = I915_READ(reg);
2717         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2718                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2719
2720                 POSTING_READ(reg);
2721                 udelay(100);
2722         }
2723 }
2724
2725 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2726 {
2727         struct drm_device *dev = intel_crtc->base.dev;
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729         int pipe = intel_crtc->pipe;
2730         u32 reg, temp;
2731
2732         /* Switch from PCDclk to Rawclk */
2733         reg = FDI_RX_CTL(pipe);
2734         temp = I915_READ(reg);
2735         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2736
2737         /* Disable CPU FDI TX PLL */
2738         reg = FDI_TX_CTL(pipe);
2739         temp = I915_READ(reg);
2740         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2741
2742         POSTING_READ(reg);
2743         udelay(100);
2744
2745         reg = FDI_RX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2748
2749         /* Wait for the clocks to turn off. */
2750         POSTING_READ(reg);
2751         udelay(100);
2752 }
2753
2754 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2755 {
2756         struct drm_device *dev = crtc->dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759         int pipe = intel_crtc->pipe;
2760         u32 reg, temp;
2761
2762         /* disable CPU FDI tx and PCH FDI rx */
2763         reg = FDI_TX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2766         POSTING_READ(reg);
2767
2768         reg = FDI_RX_CTL(pipe);
2769         temp = I915_READ(reg);
2770         temp &= ~(0x7 << 16);
2771         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2772         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2773
2774         POSTING_READ(reg);
2775         udelay(100);
2776
2777         /* Ironlake workaround, disable clock pointer after downing FDI */
2778         if (HAS_PCH_IBX(dev)) {
2779                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2780         }
2781
2782         /* still set train pattern 1 */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         temp &= ~FDI_LINK_TRAIN_NONE;
2786         temp |= FDI_LINK_TRAIN_PATTERN_1;
2787         I915_WRITE(reg, temp);
2788
2789         reg = FDI_RX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         if (HAS_PCH_CPT(dev)) {
2792                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2794         } else {
2795                 temp &= ~FDI_LINK_TRAIN_NONE;
2796                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2797         }
2798         /* BPC in FDI rx is consistent with that in PIPECONF */
2799         temp &= ~(0x07 << 16);
2800         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2801         I915_WRITE(reg, temp);
2802
2803         POSTING_READ(reg);
2804         udelay(100);
2805 }
2806
2807 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812         unsigned long flags;
2813         bool pending;
2814
2815         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2816             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2817                 return false;
2818
2819         spin_lock_irqsave(&dev->event_lock, flags);
2820         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821         spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823         return pending;
2824 }
2825
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830
2831         if (crtc->fb == NULL)
2832                 return;
2833
2834         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2835
2836         wait_event(dev_priv->pending_flip_queue,
2837                    !intel_crtc_has_pending_flip(crtc));
2838
2839         mutex_lock(&dev->struct_mutex);
2840         intel_finish_fb(crtc->fb);
2841         mutex_unlock(&dev->struct_mutex);
2842 }
2843
2844 /* Program iCLKIP clock to the desired frequency */
2845 static void lpt_program_iclkip(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2850         u32 temp;
2851
2852         mutex_lock(&dev_priv->dpio_lock);
2853
2854         /* It is necessary to ungate the pixclk gate prior to programming
2855          * the divisors, and gate it back when it is done.
2856          */
2857         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2858
2859         /* Disable SSCCTL */
2860         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2861                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2862                                 SBI_SSCCTL_DISABLE,
2863                         SBI_ICLK);
2864
2865         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2866         if (crtc->mode.clock == 20000) {
2867                 auxdiv = 1;
2868                 divsel = 0x41;
2869                 phaseinc = 0x20;
2870         } else {
2871                 /* The iCLK virtual clock root frequency is in MHz,
2872                  * but the crtc->mode.clock in in KHz. To get the divisors,
2873                  * it is necessary to divide one by another, so we
2874                  * convert the virtual clock precision to KHz here for higher
2875                  * precision.
2876                  */
2877                 u32 iclk_virtual_root_freq = 172800 * 1000;
2878                 u32 iclk_pi_range = 64;
2879                 u32 desired_divisor, msb_divisor_value, pi_value;
2880
2881                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2882                 msb_divisor_value = desired_divisor / iclk_pi_range;
2883                 pi_value = desired_divisor % iclk_pi_range;
2884
2885                 auxdiv = 0;
2886                 divsel = msb_divisor_value - 2;
2887                 phaseinc = pi_value;
2888         }
2889
2890         /* This should not happen with any sane values */
2891         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2892                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2893         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2894                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2895
2896         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2897                         crtc->mode.clock,
2898                         auxdiv,
2899                         divsel,
2900                         phasedir,
2901                         phaseinc);
2902
2903         /* Program SSCDIVINTPHASE6 */
2904         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2905         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2906         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2907         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2908         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2909         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2910         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2911         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2912
2913         /* Program SSCAUXDIV */
2914         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2915         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2916         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2917         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2918
2919         /* Enable modulator and associated divider */
2920         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2921         temp &= ~SBI_SSCCTL_DISABLE;
2922         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2923
2924         /* Wait for initialization time */
2925         udelay(24);
2926
2927         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2928
2929         mutex_unlock(&dev_priv->dpio_lock);
2930 }
2931
2932 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2933                                                 enum pipe pch_transcoder)
2934 {
2935         struct drm_device *dev = crtc->base.dev;
2936         struct drm_i915_private *dev_priv = dev->dev_private;
2937         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2938
2939         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2940                    I915_READ(HTOTAL(cpu_transcoder)));
2941         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2942                    I915_READ(HBLANK(cpu_transcoder)));
2943         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2944                    I915_READ(HSYNC(cpu_transcoder)));
2945
2946         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2947                    I915_READ(VTOTAL(cpu_transcoder)));
2948         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2949                    I915_READ(VBLANK(cpu_transcoder)));
2950         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2951                    I915_READ(VSYNC(cpu_transcoder)));
2952         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2953                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2954 }
2955
2956 /*
2957  * Enable PCH resources required for PCH ports:
2958  *   - PCH PLLs
2959  *   - FDI training & RX/TX
2960  *   - update transcoder timings
2961  *   - DP transcoding bits
2962  *   - transcoder
2963  */
2964 static void ironlake_pch_enable(struct drm_crtc *crtc)
2965 {
2966         struct drm_device *dev = crtc->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969         int pipe = intel_crtc->pipe;
2970         u32 reg, temp;
2971
2972         assert_pch_transcoder_disabled(dev_priv, pipe);
2973
2974         /* Write the TU size bits before fdi link training, so that error
2975          * detection works. */
2976         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2977                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2978
2979         /* For PCH output, training FDI link */
2980         dev_priv->display.fdi_link_train(crtc);
2981
2982         /* XXX: pch pll's can be enabled any time before we enable the PCH
2983          * transcoder, and we actually should do this to not upset any PCH
2984          * transcoder that already use the clock when we share it.
2985          *
2986          * Note that enable_shared_dpll tries to do the right thing, but
2987          * get_shared_dpll unconditionally resets the pll - we need that to have
2988          * the right LVDS enable sequence. */
2989         ironlake_enable_shared_dpll(intel_crtc);
2990
2991         if (HAS_PCH_CPT(dev)) {
2992                 u32 sel;
2993
2994                 temp = I915_READ(PCH_DPLL_SEL);
2995                 temp |= TRANS_DPLL_ENABLE(pipe);
2996                 sel = TRANS_DPLLB_SEL(pipe);
2997                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2998                         temp |= sel;
2999                 else
3000                         temp &= ~sel;
3001                 I915_WRITE(PCH_DPLL_SEL, temp);
3002         }
3003
3004         /* set transcoder timing, panel must allow it */
3005         assert_panel_unlocked(dev_priv, pipe);
3006         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3007
3008         intel_fdi_normal_train(crtc);
3009
3010         /* For PCH DP, enable TRANS_DP_CTL */
3011         if (HAS_PCH_CPT(dev) &&
3012             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3013              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3014                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3015                 reg = TRANS_DP_CTL(pipe);
3016                 temp = I915_READ(reg);
3017                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3018                           TRANS_DP_SYNC_MASK |
3019                           TRANS_DP_BPC_MASK);
3020                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3021                          TRANS_DP_ENH_FRAMING);
3022                 temp |= bpc << 9; /* same format but at 11:9 */
3023
3024                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3025                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3026                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3027                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3028
3029                 switch (intel_trans_dp_port_sel(crtc)) {
3030                 case PCH_DP_B:
3031                         temp |= TRANS_DP_PORT_SEL_B;
3032                         break;
3033                 case PCH_DP_C:
3034                         temp |= TRANS_DP_PORT_SEL_C;
3035                         break;
3036                 case PCH_DP_D:
3037                         temp |= TRANS_DP_PORT_SEL_D;
3038                         break;
3039                 default:
3040                         BUG();
3041                 }
3042
3043                 I915_WRITE(reg, temp);
3044         }
3045
3046         ironlake_enable_pch_transcoder(dev_priv, pipe);
3047 }
3048
3049 static void lpt_pch_enable(struct drm_crtc *crtc)
3050 {
3051         struct drm_device *dev = crtc->dev;
3052         struct drm_i915_private *dev_priv = dev->dev_private;
3053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3055
3056         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3057
3058         lpt_program_iclkip(crtc);
3059
3060         /* Set transcoder timing. */
3061         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3062
3063         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3064 }
3065
3066 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3067 {
3068         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3069
3070         if (pll == NULL)
3071                 return;
3072
3073         if (pll->refcount == 0) {
3074                 WARN(1, "bad %s refcount\n", pll->name);
3075                 return;
3076         }
3077
3078         if (--pll->refcount == 0) {
3079                 WARN_ON(pll->on);
3080                 WARN_ON(pll->active);
3081         }
3082
3083         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3084 }
3085
3086 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3087 {
3088         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3089         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090         enum intel_dpll_id i;
3091
3092         if (pll) {
3093                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3094                               crtc->base.base.id, pll->name);
3095                 intel_put_shared_dpll(crtc);
3096         }
3097
3098         if (HAS_PCH_IBX(dev_priv->dev)) {
3099                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3100                 i = crtc->pipe;
3101                 pll = &dev_priv->shared_dplls[i];
3102
3103                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3104                               crtc->base.base.id, pll->name);
3105
3106                 goto found;
3107         }
3108
3109         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3110                 pll = &dev_priv->shared_dplls[i];
3111
3112                 /* Only want to check enabled timings first */
3113                 if (pll->refcount == 0)
3114                         continue;
3115
3116                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3117                            sizeof(pll->hw_state)) == 0) {
3118                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3119                                       crtc->base.base.id,
3120                                       pll->name, pll->refcount, pll->active);
3121
3122                         goto found;
3123                 }
3124         }
3125
3126         /* Ok no matching timings, maybe there's a free one? */
3127         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3128                 pll = &dev_priv->shared_dplls[i];
3129                 if (pll->refcount == 0) {
3130                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3131                                       crtc->base.base.id, pll->name);
3132                         goto found;
3133                 }
3134         }
3135
3136         return NULL;
3137
3138 found:
3139         crtc->config.shared_dpll = i;
3140         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3141                          pipe_name(crtc->pipe));
3142
3143         if (pll->active == 0) {
3144                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3145                        sizeof(pll->hw_state));
3146
3147                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3148                 WARN_ON(pll->on);
3149                 assert_shared_dpll_disabled(dev_priv, pll);
3150
3151                 pll->mode_set(dev_priv, pll);
3152         }
3153         pll->refcount++;
3154
3155         return pll;
3156 }
3157
3158 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3159 {
3160         struct drm_i915_private *dev_priv = dev->dev_private;
3161         int dslreg = PIPEDSL(pipe);
3162         u32 temp;
3163
3164         temp = I915_READ(dslreg);
3165         udelay(500);
3166         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3167                 if (wait_for(I915_READ(dslreg) != temp, 5))
3168                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3169         }
3170 }
3171
3172 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3173 {
3174         struct drm_device *dev = crtc->base.dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         int pipe = crtc->pipe;
3177
3178         if (crtc->config.pch_pfit.size) {
3179                 /* Force use of hard-coded filter coefficients
3180                  * as some pre-programmed values are broken,
3181                  * e.g. x201.
3182                  */
3183                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3184                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3185                                                  PF_PIPE_SEL_IVB(pipe));
3186                 else
3187                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3188                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3189                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3190         }
3191 }
3192
3193 static void intel_enable_planes(struct drm_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->dev;
3196         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197         struct intel_plane *intel_plane;
3198
3199         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200                 if (intel_plane->pipe == pipe)
3201                         intel_plane_restore(&intel_plane->base);
3202 }
3203
3204 static void intel_disable_planes(struct drm_crtc *crtc)
3205 {
3206         struct drm_device *dev = crtc->dev;
3207         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3208         struct intel_plane *intel_plane;
3209
3210         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3211                 if (intel_plane->pipe == pipe)
3212                         intel_plane_disable(&intel_plane->base);
3213 }
3214
3215 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3216 {
3217         struct drm_device *dev = crtc->dev;
3218         struct drm_i915_private *dev_priv = dev->dev_private;
3219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220         struct intel_encoder *encoder;
3221         int pipe = intel_crtc->pipe;
3222         int plane = intel_crtc->plane;
3223
3224         WARN_ON(!crtc->enabled);
3225
3226         if (intel_crtc->active)
3227                 return;
3228
3229         intel_crtc->active = true;
3230
3231         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3232         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3233
3234         intel_update_watermarks(dev);
3235
3236         for_each_encoder_on_crtc(dev, crtc, encoder)
3237                 if (encoder->pre_enable)
3238                         encoder->pre_enable(encoder);
3239
3240         if (intel_crtc->config.has_pch_encoder) {
3241                 /* Note: FDI PLL enabling _must_ be done before we enable the
3242                  * cpu pipes, hence this is separate from all the other fdi/pch
3243                  * enabling. */
3244                 ironlake_fdi_pll_enable(intel_crtc);
3245         } else {
3246                 assert_fdi_tx_disabled(dev_priv, pipe);
3247                 assert_fdi_rx_disabled(dev_priv, pipe);
3248         }
3249
3250         ironlake_pfit_enable(intel_crtc);
3251
3252         /*
3253          * On ILK+ LUT must be loaded before the pipe is running but with
3254          * clocks enabled
3255          */
3256         intel_crtc_load_lut(crtc);
3257
3258         intel_enable_pipe(dev_priv, pipe,
3259                           intel_crtc->config.has_pch_encoder);
3260         intel_enable_plane(dev_priv, plane, pipe);
3261         intel_enable_planes(crtc);
3262         intel_crtc_update_cursor(crtc, true);
3263
3264         if (intel_crtc->config.has_pch_encoder)
3265                 ironlake_pch_enable(crtc);
3266
3267         mutex_lock(&dev->struct_mutex);
3268         intel_update_fbc(dev);
3269         mutex_unlock(&dev->struct_mutex);
3270
3271         for_each_encoder_on_crtc(dev, crtc, encoder)
3272                 encoder->enable(encoder);
3273
3274         if (HAS_PCH_CPT(dev))
3275                 cpt_verify_modeset(dev, intel_crtc->pipe);
3276
3277         /*
3278          * There seems to be a race in PCH platform hw (at least on some
3279          * outputs) where an enabled pipe still completes any pageflip right
3280          * away (as if the pipe is off) instead of waiting for vblank. As soon
3281          * as the first vblank happend, everything works as expected. Hence just
3282          * wait for one vblank before returning to avoid strange things
3283          * happening.
3284          */
3285         intel_wait_for_vblank(dev, intel_crtc->pipe);
3286 }
3287
3288 /* IPS only exists on ULT machines and is tied to pipe A. */
3289 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3290 {
3291         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3292 }
3293
3294 static void hsw_enable_ips(struct intel_crtc *crtc)
3295 {
3296         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3297
3298         if (!crtc->config.ips_enabled)
3299                 return;
3300
3301         /* We can only enable IPS after we enable a plane and wait for a vblank.
3302          * We guarantee that the plane is enabled by calling intel_enable_ips
3303          * only after intel_enable_plane. And intel_enable_plane already waits
3304          * for a vblank, so all we need to do here is to enable the IPS bit. */
3305         assert_plane_enabled(dev_priv, crtc->plane);
3306         I915_WRITE(IPS_CTL, IPS_ENABLE);
3307 }
3308
3309 static void hsw_disable_ips(struct intel_crtc *crtc)
3310 {
3311         struct drm_device *dev = crtc->base.dev;
3312         struct drm_i915_private *dev_priv = dev->dev_private;
3313
3314         if (!crtc->config.ips_enabled)
3315                 return;
3316
3317         assert_plane_enabled(dev_priv, crtc->plane);
3318         I915_WRITE(IPS_CTL, 0);
3319
3320         /* We need to wait for a vblank before we can disable the plane. */
3321         intel_wait_for_vblank(dev, crtc->pipe);
3322 }
3323
3324 static void haswell_crtc_enable(struct drm_crtc *crtc)
3325 {
3326         struct drm_device *dev = crtc->dev;
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329         struct intel_encoder *encoder;
3330         int pipe = intel_crtc->pipe;
3331         int plane = intel_crtc->plane;
3332
3333         WARN_ON(!crtc->enabled);
3334
3335         if (intel_crtc->active)
3336                 return;
3337
3338         intel_crtc->active = true;
3339
3340         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3341         if (intel_crtc->config.has_pch_encoder)
3342                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3343
3344         intel_update_watermarks(dev);
3345
3346         if (intel_crtc->config.has_pch_encoder)
3347                 dev_priv->display.fdi_link_train(crtc);
3348
3349         for_each_encoder_on_crtc(dev, crtc, encoder)
3350                 if (encoder->pre_enable)
3351                         encoder->pre_enable(encoder);
3352
3353         intel_ddi_enable_pipe_clock(intel_crtc);
3354
3355         ironlake_pfit_enable(intel_crtc);
3356
3357         /*
3358          * On ILK+ LUT must be loaded before the pipe is running but with
3359          * clocks enabled
3360          */
3361         intel_crtc_load_lut(crtc);
3362
3363         intel_ddi_set_pipe_settings(crtc);
3364         intel_ddi_enable_transcoder_func(crtc);
3365
3366         intel_enable_pipe(dev_priv, pipe,
3367                           intel_crtc->config.has_pch_encoder);
3368         intel_enable_plane(dev_priv, plane, pipe);
3369         intel_enable_planes(crtc);
3370         intel_crtc_update_cursor(crtc, true);
3371
3372         hsw_enable_ips(intel_crtc);
3373
3374         if (intel_crtc->config.has_pch_encoder)
3375                 lpt_pch_enable(crtc);
3376
3377         mutex_lock(&dev->struct_mutex);
3378         intel_update_fbc(dev);
3379         mutex_unlock(&dev->struct_mutex);
3380
3381         for_each_encoder_on_crtc(dev, crtc, encoder)
3382                 encoder->enable(encoder);
3383
3384         /*
3385          * There seems to be a race in PCH platform hw (at least on some
3386          * outputs) where an enabled pipe still completes any pageflip right
3387          * away (as if the pipe is off) instead of waiting for vblank. As soon
3388          * as the first vblank happend, everything works as expected. Hence just
3389          * wait for one vblank before returning to avoid strange things
3390          * happening.
3391          */
3392         intel_wait_for_vblank(dev, intel_crtc->pipe);
3393 }
3394
3395 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3396 {
3397         struct drm_device *dev = crtc->base.dev;
3398         struct drm_i915_private *dev_priv = dev->dev_private;
3399         int pipe = crtc->pipe;
3400
3401         /* To avoid upsetting the power well on haswell only disable the pfit if
3402          * it's in use. The hw state code will make sure we get this right. */
3403         if (crtc->config.pch_pfit.size) {
3404                 I915_WRITE(PF_CTL(pipe), 0);
3405                 I915_WRITE(PF_WIN_POS(pipe), 0);
3406                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3407         }
3408 }
3409
3410 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415         struct intel_encoder *encoder;
3416         int pipe = intel_crtc->pipe;
3417         int plane = intel_crtc->plane;
3418         u32 reg, temp;
3419
3420
3421         if (!intel_crtc->active)
3422                 return;
3423
3424         for_each_encoder_on_crtc(dev, crtc, encoder)
3425                 encoder->disable(encoder);
3426
3427         intel_crtc_wait_for_pending_flips(crtc);
3428         drm_vblank_off(dev, pipe);
3429
3430         if (dev_priv->fbc.plane == plane)
3431                 intel_disable_fbc(dev);
3432
3433         intel_crtc_update_cursor(crtc, false);
3434         intel_disable_planes(crtc);
3435         intel_disable_plane(dev_priv, plane, pipe);
3436
3437         if (intel_crtc->config.has_pch_encoder)
3438                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3439
3440         intel_disable_pipe(dev_priv, pipe);
3441
3442         ironlake_pfit_disable(intel_crtc);
3443
3444         for_each_encoder_on_crtc(dev, crtc, encoder)
3445                 if (encoder->post_disable)
3446                         encoder->post_disable(encoder);
3447
3448         if (intel_crtc->config.has_pch_encoder) {
3449                 ironlake_fdi_disable(crtc);
3450
3451                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3452                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3453
3454                 if (HAS_PCH_CPT(dev)) {
3455                         /* disable TRANS_DP_CTL */
3456                         reg = TRANS_DP_CTL(pipe);
3457                         temp = I915_READ(reg);
3458                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3459                                   TRANS_DP_PORT_SEL_MASK);
3460                         temp |= TRANS_DP_PORT_SEL_NONE;
3461                         I915_WRITE(reg, temp);
3462
3463                         /* disable DPLL_SEL */
3464                         temp = I915_READ(PCH_DPLL_SEL);
3465                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3466                         I915_WRITE(PCH_DPLL_SEL, temp);
3467                 }
3468
3469                 /* disable PCH DPLL */
3470                 intel_disable_shared_dpll(intel_crtc);
3471
3472                 ironlake_fdi_pll_disable(intel_crtc);
3473         }
3474
3475         intel_crtc->active = false;
3476         intel_update_watermarks(dev);
3477
3478         mutex_lock(&dev->struct_mutex);
3479         intel_update_fbc(dev);
3480         mutex_unlock(&dev->struct_mutex);
3481 }
3482
3483 static void haswell_crtc_disable(struct drm_crtc *crtc)
3484 {
3485         struct drm_device *dev = crtc->dev;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488         struct intel_encoder *encoder;
3489         int pipe = intel_crtc->pipe;
3490         int plane = intel_crtc->plane;
3491         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3492
3493         if (!intel_crtc->active)
3494                 return;
3495
3496         for_each_encoder_on_crtc(dev, crtc, encoder)
3497                 encoder->disable(encoder);
3498
3499         intel_crtc_wait_for_pending_flips(crtc);
3500         drm_vblank_off(dev, pipe);
3501
3502         /* FBC must be disabled before disabling the plane on HSW. */
3503         if (dev_priv->fbc.plane == plane)
3504                 intel_disable_fbc(dev);
3505
3506         hsw_disable_ips(intel_crtc);
3507
3508         intel_crtc_update_cursor(crtc, false);
3509         intel_disable_planes(crtc);
3510         intel_disable_plane(dev_priv, plane, pipe);
3511
3512         if (intel_crtc->config.has_pch_encoder)
3513                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3514         intel_disable_pipe(dev_priv, pipe);
3515
3516         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3517
3518         ironlake_pfit_disable(intel_crtc);
3519
3520         intel_ddi_disable_pipe_clock(intel_crtc);
3521
3522         for_each_encoder_on_crtc(dev, crtc, encoder)
3523                 if (encoder->post_disable)
3524                         encoder->post_disable(encoder);
3525
3526         if (intel_crtc->config.has_pch_encoder) {
3527                 lpt_disable_pch_transcoder(dev_priv);
3528                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3529                 intel_ddi_fdi_disable(crtc);
3530         }
3531
3532         intel_crtc->active = false;
3533         intel_update_watermarks(dev);
3534
3535         mutex_lock(&dev->struct_mutex);
3536         intel_update_fbc(dev);
3537         mutex_unlock(&dev->struct_mutex);
3538 }
3539
3540 static void ironlake_crtc_off(struct drm_crtc *crtc)
3541 {
3542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543         intel_put_shared_dpll(intel_crtc);
3544 }
3545
3546 static void haswell_crtc_off(struct drm_crtc *crtc)
3547 {
3548         intel_ddi_put_crtc_pll(crtc);
3549 }
3550
3551 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3552 {
3553         if (!enable && intel_crtc->overlay) {
3554                 struct drm_device *dev = intel_crtc->base.dev;
3555                 struct drm_i915_private *dev_priv = dev->dev_private;
3556
3557                 mutex_lock(&dev->struct_mutex);
3558                 dev_priv->mm.interruptible = false;
3559                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3560                 dev_priv->mm.interruptible = true;
3561                 mutex_unlock(&dev->struct_mutex);
3562         }
3563
3564         /* Let userspace switch the overlay on again. In most cases userspace
3565          * has to recompute where to put it anyway.
3566          */
3567 }
3568
3569 /**
3570  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3571  * cursor plane briefly if not already running after enabling the display
3572  * plane.
3573  * This workaround avoids occasional blank screens when self refresh is
3574  * enabled.
3575  */
3576 static void
3577 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3578 {
3579         u32 cntl = I915_READ(CURCNTR(pipe));
3580
3581         if ((cntl & CURSOR_MODE) == 0) {
3582                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3583
3584                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3585                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3586                 intel_wait_for_vblank(dev_priv->dev, pipe);
3587                 I915_WRITE(CURCNTR(pipe), cntl);
3588                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3589                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3590         }
3591 }
3592
3593 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3594 {
3595         struct drm_device *dev = crtc->base.dev;
3596         struct drm_i915_private *dev_priv = dev->dev_private;
3597         struct intel_crtc_config *pipe_config = &crtc->config;
3598
3599         if (!crtc->config.gmch_pfit.control)
3600                 return;
3601
3602         /*
3603          * The panel fitter should only be adjusted whilst the pipe is disabled,
3604          * according to register description and PRM.
3605          */
3606         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3607         assert_pipe_disabled(dev_priv, crtc->pipe);
3608
3609         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3610         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3611
3612         /* Border color in case we don't scale up to the full screen. Black by
3613          * default, change to something else for debugging. */
3614         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3615 }
3616
3617 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3618 {
3619         struct drm_device *dev = crtc->dev;
3620         struct drm_i915_private *dev_priv = dev->dev_private;
3621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622         struct intel_encoder *encoder;
3623         int pipe = intel_crtc->pipe;
3624         int plane = intel_crtc->plane;
3625
3626         WARN_ON(!crtc->enabled);
3627
3628         if (intel_crtc->active)
3629                 return;
3630
3631         intel_crtc->active = true;
3632         intel_update_watermarks(dev);
3633
3634         mutex_lock(&dev_priv->dpio_lock);
3635
3636         for_each_encoder_on_crtc(dev, crtc, encoder)
3637                 if (encoder->pre_pll_enable)
3638                         encoder->pre_pll_enable(encoder);
3639
3640         vlv_enable_pll(dev_priv, pipe);
3641
3642         for_each_encoder_on_crtc(dev, crtc, encoder)
3643                 if (encoder->pre_enable)
3644                         encoder->pre_enable(encoder);
3645
3646         /* VLV wants encoder enabling _before_ the pipe is up. */
3647         for_each_encoder_on_crtc(dev, crtc, encoder)
3648                 encoder->enable(encoder);
3649
3650         i9xx_pfit_enable(intel_crtc);
3651
3652         intel_crtc_load_lut(crtc);
3653
3654         intel_enable_pipe(dev_priv, pipe, false);
3655         intel_enable_plane(dev_priv, plane, pipe);
3656         intel_enable_planes(crtc);
3657         intel_crtc_update_cursor(crtc, true);
3658
3659         intel_update_fbc(dev);
3660
3661         mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3665 {
3666         struct drm_device *dev = crtc->dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3669         struct intel_encoder *encoder;
3670         int pipe = intel_crtc->pipe;
3671         int plane = intel_crtc->plane;
3672
3673         WARN_ON(!crtc->enabled);
3674
3675         if (intel_crtc->active)
3676                 return;
3677
3678         intel_crtc->active = true;
3679         intel_update_watermarks(dev);
3680
3681         for_each_encoder_on_crtc(dev, crtc, encoder)
3682                 if (encoder->pre_enable)
3683                         encoder->pre_enable(encoder);
3684
3685         i9xx_enable_pll(intel_crtc);
3686
3687         i9xx_pfit_enable(intel_crtc);
3688
3689         intel_crtc_load_lut(crtc);
3690
3691         intel_enable_pipe(dev_priv, pipe, false);
3692         intel_enable_plane(dev_priv, plane, pipe);
3693         intel_enable_planes(crtc);
3694         /* The fixup needs to happen before cursor is enabled */
3695         if (IS_G4X(dev))
3696                 g4x_fixup_plane(dev_priv, pipe);
3697         intel_crtc_update_cursor(crtc, true);
3698
3699         /* Give the overlay scaler a chance to enable if it's on this pipe */
3700         intel_crtc_dpms_overlay(intel_crtc, true);
3701
3702         intel_update_fbc(dev);
3703
3704         for_each_encoder_on_crtc(dev, crtc, encoder)
3705                 encoder->enable(encoder);
3706 }
3707
3708 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3709 {
3710         struct drm_device *dev = crtc->base.dev;
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712
3713         if (!crtc->config.gmch_pfit.control)
3714                 return;
3715
3716         assert_pipe_disabled(dev_priv, crtc->pipe);
3717
3718         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3719                          I915_READ(PFIT_CONTROL));
3720         I915_WRITE(PFIT_CONTROL, 0);
3721 }
3722
3723 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3724 {
3725         struct drm_device *dev = crtc->dev;
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         struct intel_encoder *encoder;
3729         int pipe = intel_crtc->pipe;
3730         int plane = intel_crtc->plane;
3731
3732         if (!intel_crtc->active)
3733                 return;
3734
3735         for_each_encoder_on_crtc(dev, crtc, encoder)
3736                 encoder->disable(encoder);
3737
3738         /* Give the overlay scaler a chance to disable if it's on this pipe */
3739         intel_crtc_wait_for_pending_flips(crtc);
3740         drm_vblank_off(dev, pipe);
3741
3742         if (dev_priv->fbc.plane == plane)
3743                 intel_disable_fbc(dev);
3744
3745         intel_crtc_dpms_overlay(intel_crtc, false);
3746         intel_crtc_update_cursor(crtc, false);
3747         intel_disable_planes(crtc);
3748         intel_disable_plane(dev_priv, plane, pipe);
3749
3750         intel_disable_pipe(dev_priv, pipe);
3751
3752         i9xx_pfit_disable(intel_crtc);
3753
3754         for_each_encoder_on_crtc(dev, crtc, encoder)
3755                 if (encoder->post_disable)
3756                         encoder->post_disable(encoder);
3757
3758         intel_disable_pll(dev_priv, pipe);
3759
3760         intel_crtc->active = false;
3761         intel_update_fbc(dev);
3762         intel_update_watermarks(dev);
3763 }
3764
3765 static void i9xx_crtc_off(struct drm_crtc *crtc)
3766 {
3767 }
3768
3769 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3770                                     bool enabled)
3771 {
3772         struct drm_device *dev = crtc->dev;
3773         struct drm_i915_master_private *master_priv;
3774         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775         int pipe = intel_crtc->pipe;
3776
3777         if (!dev->primary->master)
3778                 return;
3779
3780         master_priv = dev->primary->master->driver_priv;
3781         if (!master_priv->sarea_priv)
3782                 return;
3783
3784         switch (pipe) {
3785         case 0:
3786                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3787                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3788                 break;
3789         case 1:
3790                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3791                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3792                 break;
3793         default:
3794                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3795                 break;
3796         }
3797 }
3798
3799 /**
3800  * Sets the power management mode of the pipe and plane.
3801  */
3802 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3803 {
3804         struct drm_device *dev = crtc->dev;
3805         struct drm_i915_private *dev_priv = dev->dev_private;
3806         struct intel_encoder *intel_encoder;
3807         bool enable = false;
3808
3809         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3810                 enable |= intel_encoder->connectors_active;
3811
3812         if (enable)
3813                 dev_priv->display.crtc_enable(crtc);
3814         else
3815                 dev_priv->display.crtc_disable(crtc);
3816
3817         intel_crtc_update_sarea(crtc, enable);
3818 }
3819
3820 static void intel_crtc_disable(struct drm_crtc *crtc)
3821 {
3822         struct drm_device *dev = crtc->dev;
3823         struct drm_connector *connector;
3824         struct drm_i915_private *dev_priv = dev->dev_private;
3825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3826
3827         /* crtc should still be enabled when we disable it. */
3828         WARN_ON(!crtc->enabled);
3829
3830         dev_priv->display.crtc_disable(crtc);
3831         intel_crtc->eld_vld = false;
3832         intel_crtc_update_sarea(crtc, false);
3833         dev_priv->display.off(crtc);
3834
3835         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3836         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3837
3838         if (crtc->fb) {
3839                 mutex_lock(&dev->struct_mutex);
3840                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3841                 mutex_unlock(&dev->struct_mutex);
3842                 crtc->fb = NULL;
3843         }
3844
3845         /* Update computed state. */
3846         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3847                 if (!connector->encoder || !connector->encoder->crtc)
3848                         continue;
3849
3850                 if (connector->encoder->crtc != crtc)
3851                         continue;
3852
3853                 connector->dpms = DRM_MODE_DPMS_OFF;
3854                 to_intel_encoder(connector->encoder)->connectors_active = false;
3855         }
3856 }
3857
3858 void intel_modeset_disable(struct drm_device *dev)
3859 {
3860         struct drm_crtc *crtc;
3861
3862         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3863                 if (crtc->enabled)
3864                         intel_crtc_disable(crtc);
3865         }
3866 }
3867
3868 void intel_encoder_destroy(struct drm_encoder *encoder)
3869 {
3870         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3871
3872         drm_encoder_cleanup(encoder);
3873         kfree(intel_encoder);
3874 }
3875
3876 /* Simple dpms helper for encodres with just one connector, no cloning and only
3877  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3878  * state of the entire output pipe. */
3879 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3880 {
3881         if (mode == DRM_MODE_DPMS_ON) {
3882                 encoder->connectors_active = true;
3883
3884                 intel_crtc_update_dpms(encoder->base.crtc);
3885         } else {
3886                 encoder->connectors_active = false;
3887
3888                 intel_crtc_update_dpms(encoder->base.crtc);
3889         }
3890 }
3891
3892 /* Cross check the actual hw state with our own modeset state tracking (and it's
3893  * internal consistency). */
3894 static void intel_connector_check_state(struct intel_connector *connector)
3895 {
3896         if (connector->get_hw_state(connector)) {
3897                 struct intel_encoder *encoder = connector->encoder;
3898                 struct drm_crtc *crtc;
3899                 bool encoder_enabled;
3900                 enum pipe pipe;
3901
3902                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3903                               connector->base.base.id,
3904                               drm_get_connector_name(&connector->base));
3905
3906                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3907                      "wrong connector dpms state\n");
3908                 WARN(connector->base.encoder != &encoder->base,
3909                      "active connector not linked to encoder\n");
3910                 WARN(!encoder->connectors_active,
3911                      "encoder->connectors_active not set\n");
3912
3913                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3914                 WARN(!encoder_enabled, "encoder not enabled\n");
3915                 if (WARN_ON(!encoder->base.crtc))
3916                         return;
3917
3918                 crtc = encoder->base.crtc;
3919
3920                 WARN(!crtc->enabled, "crtc not enabled\n");
3921                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3922                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3923                      "encoder active on the wrong pipe\n");
3924         }
3925 }
3926
3927 /* Even simpler default implementation, if there's really no special case to
3928  * consider. */
3929 void intel_connector_dpms(struct drm_connector *connector, int mode)
3930 {
3931         struct intel_encoder *encoder = intel_attached_encoder(connector);
3932
3933         /* All the simple cases only support two dpms states. */
3934         if (mode != DRM_MODE_DPMS_ON)
3935                 mode = DRM_MODE_DPMS_OFF;
3936
3937         if (mode == connector->dpms)
3938                 return;
3939
3940         connector->dpms = mode;
3941
3942         /* Only need to change hw state when actually enabled */
3943         if (encoder->base.crtc)
3944                 intel_encoder_dpms(encoder, mode);
3945         else
3946                 WARN_ON(encoder->connectors_active != false);
3947
3948         intel_modeset_check_state(connector->dev);
3949 }
3950
3951 /* Simple connector->get_hw_state implementation for encoders that support only
3952  * one connector and no cloning and hence the encoder state determines the state
3953  * of the connector. */
3954 bool intel_connector_get_hw_state(struct intel_connector *connector)
3955 {
3956         enum pipe pipe = 0;
3957         struct intel_encoder *encoder = connector->encoder;
3958
3959         return encoder->get_hw_state(encoder, &pipe);
3960 }
3961
3962 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3963                                      struct intel_crtc_config *pipe_config)
3964 {
3965         struct drm_i915_private *dev_priv = dev->dev_private;
3966         struct intel_crtc *pipe_B_crtc =
3967                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3968
3969         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3970                       pipe_name(pipe), pipe_config->fdi_lanes);
3971         if (pipe_config->fdi_lanes > 4) {
3972                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3973                               pipe_name(pipe), pipe_config->fdi_lanes);
3974                 return false;
3975         }
3976
3977         if (IS_HASWELL(dev)) {
3978                 if (pipe_config->fdi_lanes > 2) {
3979                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3980                                       pipe_config->fdi_lanes);
3981                         return false;
3982                 } else {
3983                         return true;
3984                 }
3985         }
3986
3987         if (INTEL_INFO(dev)->num_pipes == 2)
3988                 return true;
3989
3990         /* Ivybridge 3 pipe is really complicated */
3991         switch (pipe) {
3992         case PIPE_A:
3993                 return true;
3994         case PIPE_B:
3995                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3996                     pipe_config->fdi_lanes > 2) {
3997                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3998                                       pipe_name(pipe), pipe_config->fdi_lanes);
3999                         return false;
4000                 }
4001                 return true;
4002         case PIPE_C:
4003                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4004                     pipe_B_crtc->config.fdi_lanes <= 2) {
4005                         if (pipe_config->fdi_lanes > 2) {
4006                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007                                               pipe_name(pipe), pipe_config->fdi_lanes);
4008                                 return false;
4009                         }
4010                 } else {
4011                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4012                         return false;
4013                 }
4014                 return true;
4015         default:
4016                 BUG();
4017         }
4018 }
4019
4020 #define RETRY 1
4021 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4022                                        struct intel_crtc_config *pipe_config)
4023 {
4024         struct drm_device *dev = intel_crtc->base.dev;
4025         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4026         int lane, link_bw, fdi_dotclock;
4027         bool setup_ok, needs_recompute = false;
4028
4029 retry:
4030         /* FDI is a binary signal running at ~2.7GHz, encoding
4031          * each output octet as 10 bits. The actual frequency
4032          * is stored as a divider into a 100MHz clock, and the
4033          * mode pixel clock is stored in units of 1KHz.
4034          * Hence the bw of each lane in terms of the mode signal
4035          * is:
4036          */
4037         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4038
4039         fdi_dotclock = adjusted_mode->clock;
4040         fdi_dotclock /= pipe_config->pixel_multiplier;
4041
4042         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4043                                            pipe_config->pipe_bpp);
4044
4045         pipe_config->fdi_lanes = lane;
4046
4047         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4048                                link_bw, &pipe_config->fdi_m_n);
4049
4050         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4051                                             intel_crtc->pipe, pipe_config);
4052         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4053                 pipe_config->pipe_bpp -= 2*3;
4054                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4055                               pipe_config->pipe_bpp);
4056                 needs_recompute = true;
4057                 pipe_config->bw_constrained = true;
4058
4059                 goto retry;
4060         }
4061
4062         if (needs_recompute)
4063                 return RETRY;
4064
4065         return setup_ok ? 0 : -EINVAL;
4066 }
4067
4068 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4069                                    struct intel_crtc_config *pipe_config)
4070 {
4071         pipe_config->ips_enabled = i915_enable_ips &&
4072                                    hsw_crtc_supports_ips(crtc) &&
4073                                    pipe_config->pipe_bpp == 24;
4074 }
4075
4076 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4077                                      struct intel_crtc_config *pipe_config)
4078 {
4079         struct drm_device *dev = crtc->base.dev;
4080         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4081
4082         if (HAS_PCH_SPLIT(dev)) {
4083                 /* FDI link clock is fixed at 2.7G */
4084                 if (pipe_config->requested_mode.clock * 3
4085                     > IRONLAKE_FDI_FREQ * 4)
4086                         return -EINVAL;
4087         }
4088
4089         /* All interlaced capable intel hw wants timings in frames. Note though
4090          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4091          * timings, so we need to be careful not to clobber these.*/
4092         if (!pipe_config->timings_set)
4093                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4094
4095         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4096          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4097          */
4098         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4099                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4100                 return -EINVAL;
4101
4102         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4103                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4104         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4105                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4106                  * for lvds. */
4107                 pipe_config->pipe_bpp = 8*3;
4108         }
4109
4110         if (HAS_IPS(dev))
4111                 hsw_compute_ips_config(crtc, pipe_config);
4112
4113         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4114          * clock survives for now. */
4115         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4116                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4117
4118         if (pipe_config->has_pch_encoder)
4119                 return ironlake_fdi_compute_config(crtc, pipe_config);
4120
4121         return 0;
4122 }
4123
4124 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4125 {
4126         return 400000; /* FIXME */
4127 }
4128
4129 static int i945_get_display_clock_speed(struct drm_device *dev)
4130 {
4131         return 400000;
4132 }
4133
4134 static int i915_get_display_clock_speed(struct drm_device *dev)
4135 {
4136         return 333000;
4137 }
4138
4139 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4140 {
4141         return 200000;
4142 }
4143
4144 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4145 {
4146         u16 gcfgc = 0;
4147
4148         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4149
4150         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4151                 return 133000;
4152         else {
4153                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154                 case GC_DISPLAY_CLOCK_333_MHZ:
4155                         return 333000;
4156                 default:
4157                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4158                         return 190000;
4159                 }
4160         }
4161 }
4162
4163 static int i865_get_display_clock_speed(struct drm_device *dev)
4164 {
4165         return 266000;
4166 }
4167
4168 static int i855_get_display_clock_speed(struct drm_device *dev)
4169 {
4170         u16 hpllcc = 0;
4171         /* Assume that the hardware is in the high speed state.  This
4172          * should be the default.
4173          */
4174         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4175         case GC_CLOCK_133_200:
4176         case GC_CLOCK_100_200:
4177                 return 200000;
4178         case GC_CLOCK_166_250:
4179                 return 250000;
4180         case GC_CLOCK_100_133:
4181                 return 133000;
4182         }
4183
4184         /* Shouldn't happen */
4185         return 0;
4186 }
4187
4188 static int i830_get_display_clock_speed(struct drm_device *dev)
4189 {
4190         return 133000;
4191 }
4192
4193 static void
4194 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4195 {
4196         while (*num > DATA_LINK_M_N_MASK ||
4197                *den > DATA_LINK_M_N_MASK) {
4198                 *num >>= 1;
4199                 *den >>= 1;
4200         }
4201 }
4202
4203 static void compute_m_n(unsigned int m, unsigned int n,
4204                         uint32_t *ret_m, uint32_t *ret_n)
4205 {
4206         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4207         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4208         intel_reduce_m_n_ratio(ret_m, ret_n);
4209 }
4210
4211 void
4212 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4213                        int pixel_clock, int link_clock,
4214                        struct intel_link_m_n *m_n)
4215 {
4216         m_n->tu = 64;
4217
4218         compute_m_n(bits_per_pixel * pixel_clock,
4219                     link_clock * nlanes * 8,
4220                     &m_n->gmch_m, &m_n->gmch_n);
4221
4222         compute_m_n(pixel_clock, link_clock,
4223                     &m_n->link_m, &m_n->link_n);
4224 }
4225
4226 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4227 {
4228         if (i915_panel_use_ssc >= 0)
4229                 return i915_panel_use_ssc != 0;
4230         return dev_priv->vbt.lvds_use_ssc
4231                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4232 }
4233
4234 static int vlv_get_refclk(struct drm_crtc *crtc)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         int refclk = 27000; /* for DP & HDMI */
4239
4240         return 100000; /* only one validated so far */
4241
4242         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4243                 refclk = 96000;
4244         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4245                 if (intel_panel_use_ssc(dev_priv))
4246                         refclk = 100000;
4247                 else
4248                         refclk = 96000;
4249         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4250                 refclk = 100000;
4251         }
4252
4253         return refclk;
4254 }
4255
4256 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4257 {
4258         struct drm_device *dev = crtc->dev;
4259         struct drm_i915_private *dev_priv = dev->dev_private;
4260         int refclk;
4261
4262         if (IS_VALLEYVIEW(dev)) {
4263                 refclk = vlv_get_refclk(crtc);
4264         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4265             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4266                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4267                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4268                               refclk / 1000);
4269         } else if (!IS_GEN2(dev)) {
4270                 refclk = 96000;
4271         } else {
4272                 refclk = 48000;
4273         }
4274
4275         return refclk;
4276 }
4277
4278 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4279 {
4280         return (1 << dpll->n) << 16 | dpll->m2;
4281 }
4282
4283 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4284 {
4285         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4286 }
4287
4288 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4289                                      intel_clock_t *reduced_clock)
4290 {
4291         struct drm_device *dev = crtc->base.dev;
4292         struct drm_i915_private *dev_priv = dev->dev_private;
4293         int pipe = crtc->pipe;
4294         u32 fp, fp2 = 0;
4295
4296         if (IS_PINEVIEW(dev)) {
4297                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4298                 if (reduced_clock)
4299                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4300         } else {
4301                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4302                 if (reduced_clock)
4303                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4304         }
4305
4306         I915_WRITE(FP0(pipe), fp);
4307         crtc->config.dpll_hw_state.fp0 = fp;
4308
4309         crtc->lowfreq_avail = false;
4310         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4311             reduced_clock && i915_powersave) {
4312                 I915_WRITE(FP1(pipe), fp2);
4313                 crtc->config.dpll_hw_state.fp1 = fp2;
4314                 crtc->lowfreq_avail = true;
4315         } else {
4316                 I915_WRITE(FP1(pipe), fp);
4317                 crtc->config.dpll_hw_state.fp1 = fp;
4318         }
4319 }
4320
4321 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4322 {
4323         u32 reg_val;
4324
4325         /*
4326          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4327          * and set it to a reasonable value instead.
4328          */
4329         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4330         reg_val &= 0xffffff00;
4331         reg_val |= 0x00000030;
4332         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4333
4334         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4335         reg_val &= 0x8cffffff;
4336         reg_val = 0x8c000000;
4337         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4338
4339         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4340         reg_val &= 0xffffff00;
4341         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4342
4343         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4344         reg_val &= 0x00ffffff;
4345         reg_val |= 0xb0000000;
4346         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4347 }
4348
4349 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4350                                          struct intel_link_m_n *m_n)
4351 {
4352         struct drm_device *dev = crtc->base.dev;
4353         struct drm_i915_private *dev_priv = dev->dev_private;
4354         int pipe = crtc->pipe;
4355
4356         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4357         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4358         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4359         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4360 }
4361
4362 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4363                                          struct intel_link_m_n *m_n)
4364 {
4365         struct drm_device *dev = crtc->base.dev;
4366         struct drm_i915_private *dev_priv = dev->dev_private;
4367         int pipe = crtc->pipe;
4368         enum transcoder transcoder = crtc->config.cpu_transcoder;
4369
4370         if (INTEL_INFO(dev)->gen >= 5) {
4371                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4372                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4373                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4374                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4375         } else {
4376                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4378                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4379                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4380         }
4381 }
4382
4383 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4384 {
4385         if (crtc->config.has_pch_encoder)
4386                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4387         else
4388                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389 }
4390
4391 static void vlv_update_pll(struct intel_crtc *crtc)
4392 {
4393         struct drm_device *dev = crtc->base.dev;
4394         struct drm_i915_private *dev_priv = dev->dev_private;
4395         struct intel_encoder *encoder;
4396         int pipe = crtc->pipe;
4397         u32 dpll, mdiv;
4398         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4399         bool is_hdmi;
4400         u32 coreclk, reg_val, dpll_md;
4401
4402         mutex_lock(&dev_priv->dpio_lock);
4403
4404         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4405
4406         bestn = crtc->config.dpll.n;
4407         bestm1 = crtc->config.dpll.m1;
4408         bestm2 = crtc->config.dpll.m2;
4409         bestp1 = crtc->config.dpll.p1;
4410         bestp2 = crtc->config.dpll.p2;
4411
4412         /* See eDP HDMI DPIO driver vbios notes doc */
4413
4414         /* PLL B needs special handling */
4415         if (pipe)
4416                 vlv_pllb_recal_opamp(dev_priv);
4417
4418         /* Set up Tx target for periodic Rcomp update */
4419         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4420
4421         /* Disable target IRef on PLL */
4422         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4423         reg_val &= 0x00ffffff;
4424         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4425
4426         /* Disable fast lock */
4427         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4428
4429         /* Set idtafcrecal before PLL is enabled */
4430         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4431         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4432         mdiv |= ((bestn << DPIO_N_SHIFT));
4433         mdiv |= (1 << DPIO_K_SHIFT);
4434
4435         /*
4436          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4437          * but we don't support that).
4438          * Note: don't use the DAC post divider as it seems unstable.
4439          */
4440         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4441         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4442
4443         mdiv |= DPIO_ENABLE_CALIBRATION;
4444         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4445
4446         /* Set HBR and RBR LPF coefficients */
4447         if (crtc->config.port_clock == 162000 ||
4448             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4449             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4450                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4451                                  0x005f0021);
4452         else
4453                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4454                                  0x00d0000f);
4455
4456         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458                 /* Use SSC source */
4459                 if (!pipe)
4460                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4461                                          0x0df40000);
4462                 else
4463                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4464                                          0x0df70000);
4465         } else { /* HDMI or VGA */
4466                 /* Use bend source */
4467                 if (!pipe)
4468                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469                                          0x0df70000);
4470                 else
4471                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472                                          0x0df40000);
4473         }
4474
4475         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4476         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479                 coreclk |= 0x01000000;
4480         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4481
4482         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4483
4484         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485                 if (encoder->pre_pll_enable)
4486                         encoder->pre_pll_enable(encoder);
4487
4488         /* Enable DPIO clock input */
4489         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491         if (pipe)
4492                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4493
4494         dpll |= DPLL_VCO_ENABLE;
4495         crtc->config.dpll_hw_state.dpll = dpll;
4496
4497         I915_WRITE(DPLL(pipe), dpll);
4498         POSTING_READ(DPLL(pipe));
4499         udelay(150);
4500
4501         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4502                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4503
4504         dpll_md = (crtc->config.pixel_multiplier - 1)
4505                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4506         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4507
4508         I915_WRITE(DPLL_MD(pipe), dpll_md);
4509         POSTING_READ(DPLL_MD(pipe));
4510
4511         if (crtc->config.has_dp_encoder)
4512                 intel_dp_set_m_n(crtc);
4513
4514         mutex_unlock(&dev_priv->dpio_lock);
4515 }
4516
4517 static void i9xx_update_pll(struct intel_crtc *crtc,
4518                             intel_clock_t *reduced_clock,
4519                             int num_connectors)
4520 {
4521         struct drm_device *dev = crtc->base.dev;
4522         struct drm_i915_private *dev_priv = dev->dev_private;
4523         u32 dpll;
4524         bool is_sdvo;
4525         struct dpll *clock = &crtc->config.dpll;
4526
4527         i9xx_update_pll_dividers(crtc, reduced_clock);
4528
4529         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4530                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4531
4532         dpll = DPLL_VGA_MODE_DIS;
4533
4534         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4535                 dpll |= DPLLB_MODE_LVDS;
4536         else
4537                 dpll |= DPLLB_MODE_DAC_SERIAL;
4538
4539         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4540                 dpll |= (crtc->config.pixel_multiplier - 1)
4541                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4542         }
4543
4544         if (is_sdvo)
4545                 dpll |= DPLL_DVO_HIGH_SPEED;
4546
4547         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4548                 dpll |= DPLL_DVO_HIGH_SPEED;
4549
4550         /* compute bitmask from p1 value */
4551         if (IS_PINEVIEW(dev))
4552                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4553         else {
4554                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4555                 if (IS_G4X(dev) && reduced_clock)
4556                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4557         }
4558         switch (clock->p2) {
4559         case 5:
4560                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4561                 break;
4562         case 7:
4563                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4564                 break;
4565         case 10:
4566                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4567                 break;
4568         case 14:
4569                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4570                 break;
4571         }
4572         if (INTEL_INFO(dev)->gen >= 4)
4573                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4574
4575         if (crtc->config.sdvo_tv_clock)
4576                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4577         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4578                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4579                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4580         else
4581                 dpll |= PLL_REF_INPUT_DREFCLK;
4582
4583         dpll |= DPLL_VCO_ENABLE;
4584         crtc->config.dpll_hw_state.dpll = dpll;
4585
4586         if (INTEL_INFO(dev)->gen >= 4) {
4587                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4588                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4589                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4590         }
4591
4592         if (crtc->config.has_dp_encoder)
4593                 intel_dp_set_m_n(crtc);
4594 }
4595
4596 static void i8xx_update_pll(struct intel_crtc *crtc,
4597                             intel_clock_t *reduced_clock,
4598                             int num_connectors)
4599 {
4600         struct drm_device *dev = crtc->base.dev;
4601         struct drm_i915_private *dev_priv = dev->dev_private;
4602         u32 dpll;
4603         struct dpll *clock = &crtc->config.dpll;
4604
4605         i9xx_update_pll_dividers(crtc, reduced_clock);
4606
4607         dpll = DPLL_VGA_MODE_DIS;
4608
4609         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4610                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4611         } else {
4612                 if (clock->p1 == 2)
4613                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4614                 else
4615                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4616                 if (clock->p2 == 4)
4617                         dpll |= PLL_P2_DIVIDE_BY_4;
4618         }
4619
4620         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4621                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4623         else
4624                 dpll |= PLL_REF_INPUT_DREFCLK;
4625
4626         dpll |= DPLL_VCO_ENABLE;
4627         crtc->config.dpll_hw_state.dpll = dpll;
4628 }
4629
4630 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4631 {
4632         struct drm_device *dev = intel_crtc->base.dev;
4633         struct drm_i915_private *dev_priv = dev->dev_private;
4634         enum pipe pipe = intel_crtc->pipe;
4635         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4636         struct drm_display_mode *adjusted_mode =
4637                 &intel_crtc->config.adjusted_mode;
4638         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4639         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641         /* We need to be careful not to changed the adjusted mode, for otherwise
4642          * the hw state checker will get angry at the mismatch. */
4643         crtc_vtotal = adjusted_mode->crtc_vtotal;
4644         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4645
4646         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647                 /* the chip adds 2 halflines automatically */
4648                 crtc_vtotal -= 1;
4649                 crtc_vblank_end -= 1;
4650                 vsyncshift = adjusted_mode->crtc_hsync_start
4651                              - adjusted_mode->crtc_htotal / 2;
4652         } else {
4653                 vsyncshift = 0;
4654         }
4655
4656         if (INTEL_INFO(dev)->gen > 3)
4657                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4658
4659         I915_WRITE(HTOTAL(cpu_transcoder),
4660                    (adjusted_mode->crtc_hdisplay - 1) |
4661                    ((adjusted_mode->crtc_htotal - 1) << 16));
4662         I915_WRITE(HBLANK(cpu_transcoder),
4663                    (adjusted_mode->crtc_hblank_start - 1) |
4664                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665         I915_WRITE(HSYNC(cpu_transcoder),
4666                    (adjusted_mode->crtc_hsync_start - 1) |
4667                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
4669         I915_WRITE(VTOTAL(cpu_transcoder),
4670                    (adjusted_mode->crtc_vdisplay - 1) |
4671                    ((crtc_vtotal - 1) << 16));
4672         I915_WRITE(VBLANK(cpu_transcoder),
4673                    (adjusted_mode->crtc_vblank_start - 1) |
4674                    ((crtc_vblank_end - 1) << 16));
4675         I915_WRITE(VSYNC(cpu_transcoder),
4676                    (adjusted_mode->crtc_vsync_start - 1) |
4677                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
4679         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682          * bits. */
4683         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684             (pipe == PIPE_B || pipe == PIPE_C))
4685                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
4687         /* pipesrc controls the size that is scaled from, which should
4688          * always be the user's requested size.
4689          */
4690         I915_WRITE(PIPESRC(pipe),
4691                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692 }
4693
4694 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695                                    struct intel_crtc_config *pipe_config)
4696 {
4697         struct drm_device *dev = crtc->base.dev;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700         uint32_t tmp;
4701
4702         tmp = I915_READ(HTOTAL(cpu_transcoder));
4703         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705         tmp = I915_READ(HBLANK(cpu_transcoder));
4706         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708         tmp = I915_READ(HSYNC(cpu_transcoder));
4709         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712         tmp = I915_READ(VTOTAL(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715         tmp = I915_READ(VBLANK(cpu_transcoder));
4716         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718         tmp = I915_READ(VSYNC(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726         }
4727
4728         tmp = I915_READ(PIPESRC(crtc->pipe));
4729         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731 }
4732
4733 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4734                                              struct intel_crtc_config *pipe_config)
4735 {
4736         struct drm_crtc *crtc = &intel_crtc->base;
4737
4738         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4739         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4740         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4741         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4742
4743         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4744         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4745         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4746         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4747
4748         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4749
4750         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4751         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4752 }
4753
4754 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4755 {
4756         struct drm_device *dev = intel_crtc->base.dev;
4757         struct drm_i915_private *dev_priv = dev->dev_private;
4758         uint32_t pipeconf;
4759
4760         pipeconf = 0;
4761
4762         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4763                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4764                  * core speed.
4765                  *
4766                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4767                  * pipe == 0 check?
4768                  */
4769                 if (intel_crtc->config.requested_mode.clock >
4770                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4771                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4772         }
4773
4774         /* only g4x and later have fancy bpc/dither controls */
4775         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4776                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4777                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4778                         pipeconf |= PIPECONF_DITHER_EN |
4779                                     PIPECONF_DITHER_TYPE_SP;
4780
4781                 switch (intel_crtc->config.pipe_bpp) {
4782                 case 18:
4783                         pipeconf |= PIPECONF_6BPC;
4784                         break;
4785                 case 24:
4786                         pipeconf |= PIPECONF_8BPC;
4787                         break;
4788                 case 30:
4789                         pipeconf |= PIPECONF_10BPC;
4790                         break;
4791                 default:
4792                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4793                         BUG();
4794                 }
4795         }
4796
4797         if (HAS_PIPE_CXSR(dev)) {
4798                 if (intel_crtc->lowfreq_avail) {
4799                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4800                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4801                 } else {
4802                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4803                 }
4804         }
4805
4806         if (!IS_GEN2(dev) &&
4807             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4808                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4809         else
4810                 pipeconf |= PIPECONF_PROGRESSIVE;
4811
4812         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4813                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4814
4815         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4816         POSTING_READ(PIPECONF(intel_crtc->pipe));
4817 }
4818
4819 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4820                               int x, int y,
4821                               struct drm_framebuffer *fb)
4822 {
4823         struct drm_device *dev = crtc->dev;
4824         struct drm_i915_private *dev_priv = dev->dev_private;
4825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4827         int pipe = intel_crtc->pipe;
4828         int plane = intel_crtc->plane;
4829         int refclk, num_connectors = 0;
4830         intel_clock_t clock, reduced_clock;
4831         u32 dspcntr;
4832         bool ok, has_reduced_clock = false;
4833         bool is_lvds = false;
4834         struct intel_encoder *encoder;
4835         const intel_limit_t *limit;
4836         int ret;
4837
4838         for_each_encoder_on_crtc(dev, crtc, encoder) {
4839                 switch (encoder->type) {
4840                 case INTEL_OUTPUT_LVDS:
4841                         is_lvds = true;
4842                         break;
4843                 }
4844
4845                 num_connectors++;
4846         }
4847
4848         refclk = i9xx_get_refclk(crtc, num_connectors);
4849
4850         /*
4851          * Returns a set of divisors for the desired target clock with the given
4852          * refclk, or FALSE.  The returned values represent the clock equation:
4853          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4854          */
4855         limit = intel_limit(crtc, refclk);
4856         ok = dev_priv->display.find_dpll(limit, crtc,
4857                                          intel_crtc->config.port_clock,
4858                                          refclk, NULL, &clock);
4859         if (!ok && !intel_crtc->config.clock_set) {
4860                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4861                 return -EINVAL;
4862         }
4863
4864         /* Ensure that the cursor is valid for the new mode before changing... */
4865         intel_crtc_update_cursor(crtc, true);
4866
4867         if (is_lvds && dev_priv->lvds_downclock_avail) {
4868                 /*
4869                  * Ensure we match the reduced clock's P to the target clock.
4870                  * If the clocks don't match, we can't switch the display clock
4871                  * by using the FP0/FP1. In such case we will disable the LVDS
4872                  * downclock feature.
4873                 */
4874                 has_reduced_clock =
4875                         dev_priv->display.find_dpll(limit, crtc,
4876                                                     dev_priv->lvds_downclock,
4877                                                     refclk, &clock,
4878                                                     &reduced_clock);
4879         }
4880         /* Compat-code for transition, will disappear. */
4881         if (!intel_crtc->config.clock_set) {
4882                 intel_crtc->config.dpll.n = clock.n;
4883                 intel_crtc->config.dpll.m1 = clock.m1;
4884                 intel_crtc->config.dpll.m2 = clock.m2;
4885                 intel_crtc->config.dpll.p1 = clock.p1;
4886                 intel_crtc->config.dpll.p2 = clock.p2;
4887         }
4888
4889         if (IS_GEN2(dev))
4890                 i8xx_update_pll(intel_crtc,
4891                                 has_reduced_clock ? &reduced_clock : NULL,
4892                                 num_connectors);
4893         else if (IS_VALLEYVIEW(dev))
4894                 vlv_update_pll(intel_crtc);
4895         else
4896                 i9xx_update_pll(intel_crtc,
4897                                 has_reduced_clock ? &reduced_clock : NULL,
4898                                 num_connectors);
4899
4900         /* Set up the display plane register */
4901         dspcntr = DISPPLANE_GAMMA_ENABLE;
4902
4903         if (!IS_VALLEYVIEW(dev)) {
4904                 if (pipe == 0)
4905                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4906                 else
4907                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4908         }
4909
4910         intel_set_pipe_timings(intel_crtc);
4911
4912         /* pipesrc and dspsize control the size that is scaled from,
4913          * which should always be the user's requested size.
4914          */
4915         I915_WRITE(DSPSIZE(plane),
4916                    ((mode->vdisplay - 1) << 16) |
4917                    (mode->hdisplay - 1));
4918         I915_WRITE(DSPPOS(plane), 0);
4919
4920         i9xx_set_pipeconf(intel_crtc);
4921
4922         I915_WRITE(DSPCNTR(plane), dspcntr);
4923         POSTING_READ(DSPCNTR(plane));
4924
4925         ret = intel_pipe_set_base(crtc, x, y, fb);
4926
4927         intel_update_watermarks(dev);
4928
4929         return ret;
4930 }
4931
4932 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4933                                  struct intel_crtc_config *pipe_config)
4934 {
4935         struct drm_device *dev = crtc->base.dev;
4936         struct drm_i915_private *dev_priv = dev->dev_private;
4937         uint32_t tmp;
4938
4939         tmp = I915_READ(PFIT_CONTROL);
4940
4941         if (INTEL_INFO(dev)->gen < 4) {
4942                 if (crtc->pipe != PIPE_B)
4943                         return;
4944
4945                 /* gen2/3 store dither state in pfit control, needs to match */
4946                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4947         } else {
4948                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4949                         return;
4950         }
4951
4952         if (!(tmp & PFIT_ENABLE))
4953                 return;
4954
4955         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4956         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4957         if (INTEL_INFO(dev)->gen < 5)
4958                 pipe_config->gmch_pfit.lvds_border_bits =
4959                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4960 }
4961
4962 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963                                  struct intel_crtc_config *pipe_config)
4964 {
4965         struct drm_device *dev = crtc->base.dev;
4966         struct drm_i915_private *dev_priv = dev->dev_private;
4967         uint32_t tmp;
4968
4969         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4970         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4971
4972         tmp = I915_READ(PIPECONF(crtc->pipe));
4973         if (!(tmp & PIPECONF_ENABLE))
4974                 return false;
4975
4976         intel_get_pipe_timings(crtc, pipe_config);
4977
4978         i9xx_get_pfit_config(crtc, pipe_config);
4979
4980         if (INTEL_INFO(dev)->gen >= 4) {
4981                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4982                 pipe_config->pixel_multiplier =
4983                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4984                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4985                 pipe_config->dpll_hw_state.dpll_md = tmp;
4986         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4987                 tmp = I915_READ(DPLL(crtc->pipe));
4988                 pipe_config->pixel_multiplier =
4989                         ((tmp & SDVO_MULTIPLIER_MASK)
4990                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4991         } else {
4992                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4993                  * port and will be fixed up in the encoder->get_config
4994                  * function. */
4995                 pipe_config->pixel_multiplier = 1;
4996         }
4997         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4998         if (!IS_VALLEYVIEW(dev)) {
4999                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5000                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5001         } else {
5002                 /* Mask out read-only status bits. */
5003                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5004                                                      DPLL_PORTC_READY_MASK |
5005                                                      DPLL_PORTB_READY_MASK);
5006         }
5007
5008         return true;
5009 }
5010
5011 static void ironlake_init_pch_refclk(struct drm_device *dev)
5012 {
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         struct drm_mode_config *mode_config = &dev->mode_config;
5015         struct intel_encoder *encoder;
5016         u32 val, final;
5017         bool has_lvds = false;
5018         bool has_cpu_edp = false;
5019         bool has_panel = false;
5020         bool has_ck505 = false;
5021         bool can_ssc = false;
5022
5023         /* We need to take the global config into account */
5024         list_for_each_entry(encoder, &mode_config->encoder_list,
5025                             base.head) {
5026                 switch (encoder->type) {
5027                 case INTEL_OUTPUT_LVDS:
5028                         has_panel = true;
5029                         has_lvds = true;
5030                         break;
5031                 case INTEL_OUTPUT_EDP:
5032                         has_panel = true;
5033                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5034                                 has_cpu_edp = true;
5035                         break;
5036                 }
5037         }
5038
5039         if (HAS_PCH_IBX(dev)) {
5040                 has_ck505 = dev_priv->vbt.display_clock_mode;
5041                 can_ssc = has_ck505;
5042         } else {
5043                 has_ck505 = false;
5044                 can_ssc = true;
5045         }
5046
5047         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5048                       has_panel, has_lvds, has_ck505);
5049
5050         /* Ironlake: try to setup display ref clock before DPLL
5051          * enabling. This is only under driver's control after
5052          * PCH B stepping, previous chipset stepping should be
5053          * ignoring this setting.
5054          */
5055         val = I915_READ(PCH_DREF_CONTROL);
5056
5057         /* As we must carefully and slowly disable/enable each source in turn,
5058          * compute the final state we want first and check if we need to
5059          * make any changes at all.
5060          */
5061         final = val;
5062         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5063         if (has_ck505)
5064                 final |= DREF_NONSPREAD_CK505_ENABLE;
5065         else
5066                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5067
5068         final &= ~DREF_SSC_SOURCE_MASK;
5069         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5070         final &= ~DREF_SSC1_ENABLE;
5071
5072         if (has_panel) {
5073                 final |= DREF_SSC_SOURCE_ENABLE;
5074
5075                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5076                         final |= DREF_SSC1_ENABLE;
5077
5078                 if (has_cpu_edp) {
5079                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5080                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5081                         else
5082                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5083                 } else
5084                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5085         } else {
5086                 final |= DREF_SSC_SOURCE_DISABLE;
5087                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5088         }
5089
5090         if (final == val)
5091                 return;
5092
5093         /* Always enable nonspread source */
5094         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5095
5096         if (has_ck505)
5097                 val |= DREF_NONSPREAD_CK505_ENABLE;
5098         else
5099                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5100
5101         if (has_panel) {
5102                 val &= ~DREF_SSC_SOURCE_MASK;
5103                 val |= DREF_SSC_SOURCE_ENABLE;
5104
5105                 /* SSC must be turned on before enabling the CPU output  */
5106                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5107                         DRM_DEBUG_KMS("Using SSC on panel\n");
5108                         val |= DREF_SSC1_ENABLE;
5109                 } else
5110                         val &= ~DREF_SSC1_ENABLE;
5111
5112                 /* Get SSC going before enabling the outputs */
5113                 I915_WRITE(PCH_DREF_CONTROL, val);
5114                 POSTING_READ(PCH_DREF_CONTROL);
5115                 udelay(200);
5116
5117                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5118
5119                 /* Enable CPU source on CPU attached eDP */
5120                 if (has_cpu_edp) {
5121                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5122                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5123                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5124                         }
5125                         else
5126                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5127                 } else
5128                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5129
5130                 I915_WRITE(PCH_DREF_CONTROL, val);
5131                 POSTING_READ(PCH_DREF_CONTROL);
5132                 udelay(200);
5133         } else {
5134                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5135
5136                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5137
5138                 /* Turn off CPU output */
5139                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5140
5141                 I915_WRITE(PCH_DREF_CONTROL, val);
5142                 POSTING_READ(PCH_DREF_CONTROL);
5143                 udelay(200);
5144
5145                 /* Turn off the SSC source */
5146                 val &= ~DREF_SSC_SOURCE_MASK;
5147                 val |= DREF_SSC_SOURCE_DISABLE;
5148
5149                 /* Turn off SSC1 */
5150                 val &= ~DREF_SSC1_ENABLE;
5151
5152                 I915_WRITE(PCH_DREF_CONTROL, val);
5153                 POSTING_READ(PCH_DREF_CONTROL);
5154                 udelay(200);
5155         }
5156
5157         BUG_ON(val != final);
5158 }
5159
5160 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5161 static void lpt_init_pch_refclk(struct drm_device *dev)
5162 {
5163         struct drm_i915_private *dev_priv = dev->dev_private;
5164         struct drm_mode_config *mode_config = &dev->mode_config;
5165         struct intel_encoder *encoder;
5166         bool has_vga = false;
5167         bool is_sdv = false;
5168         u32 tmp;
5169
5170         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5171                 switch (encoder->type) {
5172                 case INTEL_OUTPUT_ANALOG:
5173                         has_vga = true;
5174                         break;
5175                 }
5176         }
5177
5178         if (!has_vga)
5179                 return;
5180
5181         mutex_lock(&dev_priv->dpio_lock);
5182
5183         /* XXX: Rip out SDV support once Haswell ships for real. */
5184         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5185                 is_sdv = true;
5186
5187         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5188         tmp &= ~SBI_SSCCTL_DISABLE;
5189         tmp |= SBI_SSCCTL_PATHALT;
5190         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5191
5192         udelay(24);
5193
5194         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5195         tmp &= ~SBI_SSCCTL_PATHALT;
5196         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5197
5198         if (!is_sdv) {
5199                 tmp = I915_READ(SOUTH_CHICKEN2);
5200                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5201                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5202
5203                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5204                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5205                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5206
5207                 tmp = I915_READ(SOUTH_CHICKEN2);
5208                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5209                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5210
5211                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5212                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5213                                        100))
5214                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5215         }
5216
5217         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218         tmp &= ~(0xFF << 24);
5219         tmp |= (0x12 << 24);
5220         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5221
5222         if (is_sdv) {
5223                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5224                 tmp |= 0x7FFF;
5225                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5226         }
5227
5228         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5229         tmp |= (1 << 11);
5230         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5231
5232         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5233         tmp |= (1 << 11);
5234         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5235
5236         if (is_sdv) {
5237                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5238                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5239                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5240
5241                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5242                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5243                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5244
5245                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5246                 tmp |= (0x3F << 8);
5247                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5248
5249                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5250                 tmp |= (0x3F << 8);
5251                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5252         }
5253
5254         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5255         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5257
5258         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5259         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5260         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5261
5262         if (!is_sdv) {
5263                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5264                 tmp &= ~(7 << 13);
5265                 tmp |= (5 << 13);
5266                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5267
5268                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5269                 tmp &= ~(7 << 13);
5270                 tmp |= (5 << 13);
5271                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5272         }
5273
5274         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5275         tmp &= ~0xFF;
5276         tmp |= 0x1C;
5277         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5278
5279         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5280         tmp &= ~0xFF;
5281         tmp |= 0x1C;
5282         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5283
5284         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5285         tmp &= ~(0xFF << 16);
5286         tmp |= (0x1C << 16);
5287         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5288
5289         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5290         tmp &= ~(0xFF << 16);
5291         tmp |= (0x1C << 16);
5292         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5293
5294         if (!is_sdv) {
5295                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5296                 tmp |= (1 << 27);
5297                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5298
5299                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5300                 tmp |= (1 << 27);
5301                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5302
5303                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5304                 tmp &= ~(0xF << 28);
5305                 tmp |= (4 << 28);
5306                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5307
5308                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5309                 tmp &= ~(0xF << 28);
5310                 tmp |= (4 << 28);
5311                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5312         }
5313
5314         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5315         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5316         tmp |= SBI_DBUFF0_ENABLE;
5317         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5318
5319         mutex_unlock(&dev_priv->dpio_lock);
5320 }
5321
5322 /*
5323  * Initialize reference clocks when the driver loads
5324  */
5325 void intel_init_pch_refclk(struct drm_device *dev)
5326 {
5327         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5328                 ironlake_init_pch_refclk(dev);
5329         else if (HAS_PCH_LPT(dev))
5330                 lpt_init_pch_refclk(dev);
5331 }
5332
5333 static int ironlake_get_refclk(struct drm_crtc *crtc)
5334 {
5335         struct drm_device *dev = crtc->dev;
5336         struct drm_i915_private *dev_priv = dev->dev_private;
5337         struct intel_encoder *encoder;
5338         int num_connectors = 0;
5339         bool is_lvds = false;
5340
5341         for_each_encoder_on_crtc(dev, crtc, encoder) {
5342                 switch (encoder->type) {
5343                 case INTEL_OUTPUT_LVDS:
5344                         is_lvds = true;
5345                         break;
5346                 }
5347                 num_connectors++;
5348         }
5349
5350         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5351                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5352                               dev_priv->vbt.lvds_ssc_freq);
5353                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5354         }
5355
5356         return 120000;
5357 }
5358
5359 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5360 {
5361         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363         int pipe = intel_crtc->pipe;
5364         uint32_t val;
5365
5366         val = 0;
5367
5368         switch (intel_crtc->config.pipe_bpp) {
5369         case 18:
5370                 val |= PIPECONF_6BPC;
5371                 break;
5372         case 24:
5373                 val |= PIPECONF_8BPC;
5374                 break;
5375         case 30:
5376                 val |= PIPECONF_10BPC;
5377                 break;
5378         case 36:
5379                 val |= PIPECONF_12BPC;
5380                 break;
5381         default:
5382                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5383                 BUG();
5384         }
5385
5386         if (intel_crtc->config.dither)
5387                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5388
5389         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5390                 val |= PIPECONF_INTERLACED_ILK;
5391         else
5392                 val |= PIPECONF_PROGRESSIVE;
5393
5394         if (intel_crtc->config.limited_color_range)
5395                 val |= PIPECONF_COLOR_RANGE_SELECT;
5396
5397         I915_WRITE(PIPECONF(pipe), val);
5398         POSTING_READ(PIPECONF(pipe));
5399 }
5400
5401 /*
5402  * Set up the pipe CSC unit.
5403  *
5404  * Currently only full range RGB to limited range RGB conversion
5405  * is supported, but eventually this should handle various
5406  * RGB<->YCbCr scenarios as well.
5407  */
5408 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5409 {
5410         struct drm_device *dev = crtc->dev;
5411         struct drm_i915_private *dev_priv = dev->dev_private;
5412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413         int pipe = intel_crtc->pipe;
5414         uint16_t coeff = 0x7800; /* 1.0 */
5415
5416         /*
5417          * TODO: Check what kind of values actually come out of the pipe
5418          * with these coeff/postoff values and adjust to get the best
5419          * accuracy. Perhaps we even need to take the bpc value into
5420          * consideration.
5421          */
5422
5423         if (intel_crtc->config.limited_color_range)
5424                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5425
5426         /*
5427          * GY/GU and RY/RU should be the other way around according
5428          * to BSpec, but reality doesn't agree. Just set them up in
5429          * a way that results in the correct picture.
5430          */
5431         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5432         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5433
5434         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5435         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5436
5437         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5438         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5439
5440         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5441         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5442         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5443
5444         if (INTEL_INFO(dev)->gen > 6) {
5445                 uint16_t postoff = 0;
5446
5447                 if (intel_crtc->config.limited_color_range)
5448                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5449
5450                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5451                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5452                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5453
5454                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5455         } else {
5456                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5457
5458                 if (intel_crtc->config.limited_color_range)
5459                         mode |= CSC_BLACK_SCREEN_OFFSET;
5460
5461                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5462         }
5463 }
5464
5465 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5466 {
5467         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5469         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5470         uint32_t val;
5471
5472         val = 0;
5473
5474         if (intel_crtc->config.dither)
5475                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5476
5477         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5478                 val |= PIPECONF_INTERLACED_ILK;
5479         else
5480                 val |= PIPECONF_PROGRESSIVE;
5481
5482         I915_WRITE(PIPECONF(cpu_transcoder), val);
5483         POSTING_READ(PIPECONF(cpu_transcoder));
5484
5485         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5486         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5487 }
5488
5489 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5490                                     intel_clock_t *clock,
5491                                     bool *has_reduced_clock,
5492                                     intel_clock_t *reduced_clock)
5493 {
5494         struct drm_device *dev = crtc->dev;
5495         struct drm_i915_private *dev_priv = dev->dev_private;
5496         struct intel_encoder *intel_encoder;
5497         int refclk;
5498         const intel_limit_t *limit;
5499         bool ret, is_lvds = false;
5500
5501         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5502                 switch (intel_encoder->type) {
5503                 case INTEL_OUTPUT_LVDS:
5504                         is_lvds = true;
5505                         break;
5506                 }
5507         }
5508
5509         refclk = ironlake_get_refclk(crtc);
5510
5511         /*
5512          * Returns a set of divisors for the desired target clock with the given
5513          * refclk, or FALSE.  The returned values represent the clock equation:
5514          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5515          */
5516         limit = intel_limit(crtc, refclk);
5517         ret = dev_priv->display.find_dpll(limit, crtc,
5518                                           to_intel_crtc(crtc)->config.port_clock,
5519                                           refclk, NULL, clock);
5520         if (!ret)
5521                 return false;
5522
5523         if (is_lvds && dev_priv->lvds_downclock_avail) {
5524                 /*
5525                  * Ensure we match the reduced clock's P to the target clock.
5526                  * If the clocks don't match, we can't switch the display clock
5527                  * by using the FP0/FP1. In such case we will disable the LVDS
5528                  * downclock feature.
5529                 */
5530                 *has_reduced_clock =
5531                         dev_priv->display.find_dpll(limit, crtc,
5532                                                     dev_priv->lvds_downclock,
5533                                                     refclk, clock,
5534                                                     reduced_clock);
5535         }
5536
5537         return true;
5538 }
5539
5540 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5541 {
5542         struct drm_i915_private *dev_priv = dev->dev_private;
5543         uint32_t temp;
5544
5545         temp = I915_READ(SOUTH_CHICKEN1);
5546         if (temp & FDI_BC_BIFURCATION_SELECT)
5547                 return;
5548
5549         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5550         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5551
5552         temp |= FDI_BC_BIFURCATION_SELECT;
5553         DRM_DEBUG_KMS("enabling fdi C rx\n");
5554         I915_WRITE(SOUTH_CHICKEN1, temp);
5555         POSTING_READ(SOUTH_CHICKEN1);
5556 }
5557
5558 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5559 {
5560         struct drm_device *dev = intel_crtc->base.dev;
5561         struct drm_i915_private *dev_priv = dev->dev_private;
5562
5563         switch (intel_crtc->pipe) {
5564         case PIPE_A:
5565                 break;
5566         case PIPE_B:
5567                 if (intel_crtc->config.fdi_lanes > 2)
5568                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5569                 else
5570                         cpt_enable_fdi_bc_bifurcation(dev);
5571
5572                 break;
5573         case PIPE_C:
5574                 cpt_enable_fdi_bc_bifurcation(dev);
5575
5576                 break;
5577         default:
5578                 BUG();
5579         }
5580 }
5581
5582 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5583 {
5584         /*
5585          * Account for spread spectrum to avoid
5586          * oversubscribing the link. Max center spread
5587          * is 2.5%; use 5% for safety's sake.
5588          */
5589         u32 bps = target_clock * bpp * 21 / 20;
5590         return bps / (link_bw * 8) + 1;
5591 }
5592
5593 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5594 {
5595         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5596 }
5597
5598 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5599                                       u32 *fp,
5600                                       intel_clock_t *reduced_clock, u32 *fp2)
5601 {
5602         struct drm_crtc *crtc = &intel_crtc->base;
5603         struct drm_device *dev = crtc->dev;
5604         struct drm_i915_private *dev_priv = dev->dev_private;
5605         struct intel_encoder *intel_encoder;
5606         uint32_t dpll;
5607         int factor, num_connectors = 0;
5608         bool is_lvds = false, is_sdvo = false;
5609
5610         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5611                 switch (intel_encoder->type) {
5612                 case INTEL_OUTPUT_LVDS:
5613                         is_lvds = true;
5614                         break;
5615                 case INTEL_OUTPUT_SDVO:
5616                 case INTEL_OUTPUT_HDMI:
5617                         is_sdvo = true;
5618                         break;
5619                 }
5620
5621                 num_connectors++;
5622         }
5623
5624         /* Enable autotuning of the PLL clock (if permissible) */
5625         factor = 21;
5626         if (is_lvds) {
5627                 if ((intel_panel_use_ssc(dev_priv) &&
5628                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5629                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5630                         factor = 25;
5631         } else if (intel_crtc->config.sdvo_tv_clock)
5632                 factor = 20;
5633
5634         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5635                 *fp |= FP_CB_TUNE;
5636
5637         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5638                 *fp2 |= FP_CB_TUNE;
5639
5640         dpll = 0;
5641
5642         if (is_lvds)
5643                 dpll |= DPLLB_MODE_LVDS;
5644         else
5645                 dpll |= DPLLB_MODE_DAC_SERIAL;
5646
5647         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5648                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5649
5650         if (is_sdvo)
5651                 dpll |= DPLL_DVO_HIGH_SPEED;
5652         if (intel_crtc->config.has_dp_encoder)
5653                 dpll |= DPLL_DVO_HIGH_SPEED;
5654
5655         /* compute bitmask from p1 value */
5656         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5657         /* also FPA1 */
5658         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5659
5660         switch (intel_crtc->config.dpll.p2) {
5661         case 5:
5662                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5663                 break;
5664         case 7:
5665                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5666                 break;
5667         case 10:
5668                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5669                 break;
5670         case 14:
5671                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5672                 break;
5673         }
5674
5675         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5676                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5677         else
5678                 dpll |= PLL_REF_INPUT_DREFCLK;
5679
5680         return dpll | DPLL_VCO_ENABLE;
5681 }
5682
5683 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5684                                   int x, int y,
5685                                   struct drm_framebuffer *fb)
5686 {
5687         struct drm_device *dev = crtc->dev;
5688         struct drm_i915_private *dev_priv = dev->dev_private;
5689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5690         int pipe = intel_crtc->pipe;
5691         int plane = intel_crtc->plane;
5692         int num_connectors = 0;
5693         intel_clock_t clock, reduced_clock;
5694         u32 dpll = 0, fp = 0, fp2 = 0;
5695         bool ok, has_reduced_clock = false;
5696         bool is_lvds = false;
5697         struct intel_encoder *encoder;
5698         struct intel_shared_dpll *pll;
5699         int ret;
5700
5701         for_each_encoder_on_crtc(dev, crtc, encoder) {
5702                 switch (encoder->type) {
5703                 case INTEL_OUTPUT_LVDS:
5704                         is_lvds = true;
5705                         break;
5706                 }
5707
5708                 num_connectors++;
5709         }
5710
5711         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5712              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5713
5714         ok = ironlake_compute_clocks(crtc, &clock,
5715                                      &has_reduced_clock, &reduced_clock);
5716         if (!ok && !intel_crtc->config.clock_set) {
5717                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5718                 return -EINVAL;
5719         }
5720         /* Compat-code for transition, will disappear. */
5721         if (!intel_crtc->config.clock_set) {
5722                 intel_crtc->config.dpll.n = clock.n;
5723                 intel_crtc->config.dpll.m1 = clock.m1;
5724                 intel_crtc->config.dpll.m2 = clock.m2;
5725                 intel_crtc->config.dpll.p1 = clock.p1;
5726                 intel_crtc->config.dpll.p2 = clock.p2;
5727         }
5728
5729         /* Ensure that the cursor is valid for the new mode before changing... */
5730         intel_crtc_update_cursor(crtc, true);
5731
5732         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5733         if (intel_crtc->config.has_pch_encoder) {
5734                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5735                 if (has_reduced_clock)
5736                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5737
5738                 dpll = ironlake_compute_dpll(intel_crtc,
5739                                              &fp, &reduced_clock,
5740                                              has_reduced_clock ? &fp2 : NULL);
5741
5742                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5743                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5744                 if (has_reduced_clock)
5745                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5746                 else
5747                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5748
5749                 pll = intel_get_shared_dpll(intel_crtc);
5750                 if (pll == NULL) {
5751                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5752                                          pipe_name(pipe));
5753                         return -EINVAL;
5754                 }
5755         } else
5756                 intel_put_shared_dpll(intel_crtc);
5757
5758         if (intel_crtc->config.has_dp_encoder)
5759                 intel_dp_set_m_n(intel_crtc);
5760
5761         if (is_lvds && has_reduced_clock && i915_powersave)
5762                 intel_crtc->lowfreq_avail = true;
5763         else
5764                 intel_crtc->lowfreq_avail = false;
5765
5766         if (intel_crtc->config.has_pch_encoder) {
5767                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5768
5769         }
5770
5771         intel_set_pipe_timings(intel_crtc);
5772
5773         if (intel_crtc->config.has_pch_encoder) {
5774                 intel_cpu_transcoder_set_m_n(intel_crtc,
5775                                              &intel_crtc->config.fdi_m_n);
5776         }
5777
5778         if (IS_IVYBRIDGE(dev))
5779                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5780
5781         ironlake_set_pipeconf(crtc);
5782
5783         /* Set up the display plane register */
5784         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5785         POSTING_READ(DSPCNTR(plane));
5786
5787         ret = intel_pipe_set_base(crtc, x, y, fb);
5788
5789         intel_update_watermarks(dev);
5790
5791         return ret;
5792 }
5793
5794 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5795                                         struct intel_crtc_config *pipe_config)
5796 {
5797         struct drm_device *dev = crtc->base.dev;
5798         struct drm_i915_private *dev_priv = dev->dev_private;
5799         enum transcoder transcoder = pipe_config->cpu_transcoder;
5800
5801         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5802         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5803         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5804                                         & ~TU_SIZE_MASK;
5805         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5806         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5807                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5808 }
5809
5810 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5811                                      struct intel_crtc_config *pipe_config)
5812 {
5813         struct drm_device *dev = crtc->base.dev;
5814         struct drm_i915_private *dev_priv = dev->dev_private;
5815         uint32_t tmp;
5816
5817         tmp = I915_READ(PF_CTL(crtc->pipe));
5818
5819         if (tmp & PF_ENABLE) {
5820                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5821                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5822
5823                 /* We currently do not free assignements of panel fitters on
5824                  * ivb/hsw (since we don't use the higher upscaling modes which
5825                  * differentiates them) so just WARN about this case for now. */
5826                 if (IS_GEN7(dev)) {
5827                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5828                                 PF_PIPE_SEL_IVB(crtc->pipe));
5829                 }
5830         }
5831 }
5832
5833 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5834                                      struct intel_crtc_config *pipe_config)
5835 {
5836         struct drm_device *dev = crtc->base.dev;
5837         struct drm_i915_private *dev_priv = dev->dev_private;
5838         uint32_t tmp;
5839
5840         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5841         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5842
5843         tmp = I915_READ(PIPECONF(crtc->pipe));
5844         if (!(tmp & PIPECONF_ENABLE))
5845                 return false;
5846
5847         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5848                 struct intel_shared_dpll *pll;
5849
5850                 pipe_config->has_pch_encoder = true;
5851
5852                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5853                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5854                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5855
5856                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5857
5858                 if (HAS_PCH_IBX(dev_priv->dev)) {
5859                         pipe_config->shared_dpll = crtc->pipe;
5860                 } else {
5861                         tmp = I915_READ(PCH_DPLL_SEL);
5862                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5863                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5864                         else
5865                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5866                 }
5867
5868                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5869
5870                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5871                                            &pipe_config->dpll_hw_state));
5872
5873                 tmp = pipe_config->dpll_hw_state.dpll;
5874                 pipe_config->pixel_multiplier =
5875                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5876                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5877         } else {
5878                 pipe_config->pixel_multiplier = 1;
5879         }
5880
5881         intel_get_pipe_timings(crtc, pipe_config);
5882
5883         ironlake_get_pfit_config(crtc, pipe_config);
5884
5885         return true;
5886 }
5887
5888 static void haswell_modeset_global_resources(struct drm_device *dev)
5889 {
5890         bool enable = false;
5891         struct intel_crtc *crtc;
5892
5893         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5894                 if (!crtc->base.enabled)
5895                         continue;
5896
5897                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5898                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5899                         enable = true;
5900         }
5901
5902         intel_set_power_well(dev, enable);
5903 }
5904
5905 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5906                                  int x, int y,
5907                                  struct drm_framebuffer *fb)
5908 {
5909         struct drm_device *dev = crtc->dev;
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5912         int plane = intel_crtc->plane;
5913         int ret;
5914
5915         if (!intel_ddi_pll_mode_set(crtc))
5916                 return -EINVAL;
5917
5918         /* Ensure that the cursor is valid for the new mode before changing... */
5919         intel_crtc_update_cursor(crtc, true);
5920
5921         if (intel_crtc->config.has_dp_encoder)
5922                 intel_dp_set_m_n(intel_crtc);
5923
5924         intel_crtc->lowfreq_avail = false;
5925
5926         intel_set_pipe_timings(intel_crtc);
5927
5928         if (intel_crtc->config.has_pch_encoder) {
5929                 intel_cpu_transcoder_set_m_n(intel_crtc,
5930                                              &intel_crtc->config.fdi_m_n);
5931         }
5932
5933         haswell_set_pipeconf(crtc);
5934
5935         intel_set_pipe_csc(crtc);
5936
5937         /* Set up the display plane register */
5938         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5939         POSTING_READ(DSPCNTR(plane));
5940
5941         ret = intel_pipe_set_base(crtc, x, y, fb);
5942
5943         intel_update_watermarks(dev);
5944
5945         return ret;
5946 }
5947
5948 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5949                                     struct intel_crtc_config *pipe_config)
5950 {
5951         struct drm_device *dev = crtc->base.dev;
5952         struct drm_i915_private *dev_priv = dev->dev_private;
5953         enum intel_display_power_domain pfit_domain;
5954         uint32_t tmp;
5955
5956         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5957         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5958
5959         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5960         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5961                 enum pipe trans_edp_pipe;
5962                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5963                 default:
5964                         WARN(1, "unknown pipe linked to edp transcoder\n");
5965                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5966                 case TRANS_DDI_EDP_INPUT_A_ON:
5967                         trans_edp_pipe = PIPE_A;
5968                         break;
5969                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5970                         trans_edp_pipe = PIPE_B;
5971                         break;
5972                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5973                         trans_edp_pipe = PIPE_C;
5974                         break;
5975                 }
5976
5977                 if (trans_edp_pipe == crtc->pipe)
5978                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5979         }
5980
5981         if (!intel_display_power_enabled(dev,
5982                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5983                 return false;
5984
5985         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5986         if (!(tmp & PIPECONF_ENABLE))
5987                 return false;
5988
5989         /*
5990          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5991          * DDI E. So just check whether this pipe is wired to DDI E and whether
5992          * the PCH transcoder is on.
5993          */
5994         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5995         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5996             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5997                 pipe_config->has_pch_encoder = true;
5998
5999                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6000                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6001                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6002
6003                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6004         }
6005
6006         intel_get_pipe_timings(crtc, pipe_config);
6007
6008         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6009         if (intel_display_power_enabled(dev, pfit_domain))
6010                 ironlake_get_pfit_config(crtc, pipe_config);
6011
6012         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6013                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6014
6015         pipe_config->pixel_multiplier = 1;
6016
6017         return true;
6018 }
6019
6020 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6021                                int x, int y,
6022                                struct drm_framebuffer *fb)
6023 {
6024         struct drm_device *dev = crtc->dev;
6025         struct drm_i915_private *dev_priv = dev->dev_private;
6026         struct drm_encoder_helper_funcs *encoder_funcs;
6027         struct intel_encoder *encoder;
6028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6029         struct drm_display_mode *adjusted_mode =
6030                 &intel_crtc->config.adjusted_mode;
6031         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6032         int pipe = intel_crtc->pipe;
6033         int ret;
6034
6035         drm_vblank_pre_modeset(dev, pipe);
6036
6037         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6038
6039         drm_vblank_post_modeset(dev, pipe);
6040
6041         if (ret != 0)
6042                 return ret;
6043
6044         for_each_encoder_on_crtc(dev, crtc, encoder) {
6045                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6046                         encoder->base.base.id,
6047                         drm_get_encoder_name(&encoder->base),
6048                         mode->base.id, mode->name);
6049                 if (encoder->mode_set) {
6050                         encoder->mode_set(encoder);
6051                 } else {
6052                         encoder_funcs = encoder->base.helper_private;
6053                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6054                 }
6055         }
6056
6057         return 0;
6058 }
6059
6060 static bool intel_eld_uptodate(struct drm_connector *connector,
6061                                int reg_eldv, uint32_t bits_eldv,
6062                                int reg_elda, uint32_t bits_elda,
6063                                int reg_edid)
6064 {
6065         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6066         uint8_t *eld = connector->eld;
6067         uint32_t i;
6068
6069         i = I915_READ(reg_eldv);
6070         i &= bits_eldv;
6071
6072         if (!eld[0])
6073                 return !i;
6074
6075         if (!i)
6076                 return false;
6077
6078         i = I915_READ(reg_elda);
6079         i &= ~bits_elda;
6080         I915_WRITE(reg_elda, i);
6081
6082         for (i = 0; i < eld[2]; i++)
6083                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6084                         return false;
6085
6086         return true;
6087 }
6088
6089 static void g4x_write_eld(struct drm_connector *connector,
6090                           struct drm_crtc *crtc)
6091 {
6092         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6093         uint8_t *eld = connector->eld;
6094         uint32_t eldv;
6095         uint32_t len;
6096         uint32_t i;
6097
6098         i = I915_READ(G4X_AUD_VID_DID);
6099
6100         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6101                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6102         else
6103                 eldv = G4X_ELDV_DEVCTG;
6104
6105         if (intel_eld_uptodate(connector,
6106                                G4X_AUD_CNTL_ST, eldv,
6107                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6108                                G4X_HDMIW_HDMIEDID))
6109                 return;
6110
6111         i = I915_READ(G4X_AUD_CNTL_ST);
6112         i &= ~(eldv | G4X_ELD_ADDR);
6113         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6114         I915_WRITE(G4X_AUD_CNTL_ST, i);
6115
6116         if (!eld[0])
6117                 return;
6118
6119         len = min_t(uint8_t, eld[2], len);
6120         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6121         for (i = 0; i < len; i++)
6122                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6123
6124         i = I915_READ(G4X_AUD_CNTL_ST);
6125         i |= eldv;
6126         I915_WRITE(G4X_AUD_CNTL_ST, i);
6127 }
6128
6129 static void haswell_write_eld(struct drm_connector *connector,
6130                                      struct drm_crtc *crtc)
6131 {
6132         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6133         uint8_t *eld = connector->eld;
6134         struct drm_device *dev = crtc->dev;
6135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6136         uint32_t eldv;
6137         uint32_t i;
6138         int len;
6139         int pipe = to_intel_crtc(crtc)->pipe;
6140         int tmp;
6141
6142         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6143         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6144         int aud_config = HSW_AUD_CFG(pipe);
6145         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6146
6147
6148         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6149
6150         /* Audio output enable */
6151         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6152         tmp = I915_READ(aud_cntrl_st2);
6153         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6154         I915_WRITE(aud_cntrl_st2, tmp);
6155
6156         /* Wait for 1 vertical blank */
6157         intel_wait_for_vblank(dev, pipe);
6158
6159         /* Set ELD valid state */
6160         tmp = I915_READ(aud_cntrl_st2);
6161         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6162         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6163         I915_WRITE(aud_cntrl_st2, tmp);
6164         tmp = I915_READ(aud_cntrl_st2);
6165         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6166
6167         /* Enable HDMI mode */
6168         tmp = I915_READ(aud_config);
6169         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6170         /* clear N_programing_enable and N_value_index */
6171         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6172         I915_WRITE(aud_config, tmp);
6173
6174         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6175
6176         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6177         intel_crtc->eld_vld = true;
6178
6179         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6180                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6181                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6182                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6183         } else
6184                 I915_WRITE(aud_config, 0);
6185
6186         if (intel_eld_uptodate(connector,
6187                                aud_cntrl_st2, eldv,
6188                                aud_cntl_st, IBX_ELD_ADDRESS,
6189                                hdmiw_hdmiedid))
6190                 return;
6191
6192         i = I915_READ(aud_cntrl_st2);
6193         i &= ~eldv;
6194         I915_WRITE(aud_cntrl_st2, i);
6195
6196         if (!eld[0])
6197                 return;
6198
6199         i = I915_READ(aud_cntl_st);
6200         i &= ~IBX_ELD_ADDRESS;
6201         I915_WRITE(aud_cntl_st, i);
6202         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6203         DRM_DEBUG_DRIVER("port num:%d\n", i);
6204
6205         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6206         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6207         for (i = 0; i < len; i++)
6208                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6209
6210         i = I915_READ(aud_cntrl_st2);
6211         i |= eldv;
6212         I915_WRITE(aud_cntrl_st2, i);
6213
6214 }
6215
6216 static void ironlake_write_eld(struct drm_connector *connector,
6217                                      struct drm_crtc *crtc)
6218 {
6219         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6220         uint8_t *eld = connector->eld;
6221         uint32_t eldv;
6222         uint32_t i;
6223         int len;
6224         int hdmiw_hdmiedid;
6225         int aud_config;
6226         int aud_cntl_st;
6227         int aud_cntrl_st2;
6228         int pipe = to_intel_crtc(crtc)->pipe;
6229
6230         if (HAS_PCH_IBX(connector->dev)) {
6231                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6232                 aud_config = IBX_AUD_CFG(pipe);
6233                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6234                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6235         } else {
6236                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6237                 aud_config = CPT_AUD_CFG(pipe);
6238                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6239                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6240         }
6241
6242         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6243
6244         i = I915_READ(aud_cntl_st);
6245         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6246         if (!i) {
6247                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6248                 /* operate blindly on all ports */
6249                 eldv = IBX_ELD_VALIDB;
6250                 eldv |= IBX_ELD_VALIDB << 4;
6251                 eldv |= IBX_ELD_VALIDB << 8;
6252         } else {
6253                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6254                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6255         }
6256
6257         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6258                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6259                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6260                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6261         } else
6262                 I915_WRITE(aud_config, 0);
6263
6264         if (intel_eld_uptodate(connector,
6265                                aud_cntrl_st2, eldv,
6266                                aud_cntl_st, IBX_ELD_ADDRESS,
6267                                hdmiw_hdmiedid))
6268                 return;
6269
6270         i = I915_READ(aud_cntrl_st2);
6271         i &= ~eldv;
6272         I915_WRITE(aud_cntrl_st2, i);
6273
6274         if (!eld[0])
6275                 return;
6276
6277         i = I915_READ(aud_cntl_st);
6278         i &= ~IBX_ELD_ADDRESS;
6279         I915_WRITE(aud_cntl_st, i);
6280
6281         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6282         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6283         for (i = 0; i < len; i++)
6284                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6285
6286         i = I915_READ(aud_cntrl_st2);
6287         i |= eldv;
6288         I915_WRITE(aud_cntrl_st2, i);
6289 }
6290
6291 void intel_write_eld(struct drm_encoder *encoder,
6292                      struct drm_display_mode *mode)
6293 {
6294         struct drm_crtc *crtc = encoder->crtc;
6295         struct drm_connector *connector;
6296         struct drm_device *dev = encoder->dev;
6297         struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299         connector = drm_select_eld(encoder, mode);
6300         if (!connector)
6301                 return;
6302
6303         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6304                          connector->base.id,
6305                          drm_get_connector_name(connector),
6306                          connector->encoder->base.id,
6307                          drm_get_encoder_name(connector->encoder));
6308
6309         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6310
6311         if (dev_priv->display.write_eld)
6312                 dev_priv->display.write_eld(connector, crtc);
6313 }
6314
6315 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6316 void intel_crtc_load_lut(struct drm_crtc *crtc)
6317 {
6318         struct drm_device *dev = crtc->dev;
6319         struct drm_i915_private *dev_priv = dev->dev_private;
6320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6321         enum pipe pipe = intel_crtc->pipe;
6322         int palreg = PALETTE(pipe);
6323         int i;
6324         bool reenable_ips = false;
6325
6326         /* The clocks have to be on to load the palette. */
6327         if (!crtc->enabled || !intel_crtc->active)
6328                 return;
6329
6330         if (!HAS_PCH_SPLIT(dev_priv->dev))
6331                 assert_pll_enabled(dev_priv, pipe);
6332
6333         /* use legacy palette for Ironlake */
6334         if (HAS_PCH_SPLIT(dev))
6335                 palreg = LGC_PALETTE(pipe);
6336
6337         /* Workaround : Do not read or write the pipe palette/gamma data while
6338          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6339          */
6340         if (intel_crtc->config.ips_enabled &&
6341             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6342              GAMMA_MODE_MODE_SPLIT)) {
6343                 hsw_disable_ips(intel_crtc);
6344                 reenable_ips = true;
6345         }
6346
6347         for (i = 0; i < 256; i++) {
6348                 I915_WRITE(palreg + 4 * i,
6349                            (intel_crtc->lut_r[i] << 16) |
6350                            (intel_crtc->lut_g[i] << 8) |
6351                            intel_crtc->lut_b[i]);
6352         }
6353
6354         if (reenable_ips)
6355                 hsw_enable_ips(intel_crtc);
6356 }
6357
6358 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6359 {
6360         struct drm_device *dev = crtc->dev;
6361         struct drm_i915_private *dev_priv = dev->dev_private;
6362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363         bool visible = base != 0;
6364         u32 cntl;
6365
6366         if (intel_crtc->cursor_visible == visible)
6367                 return;
6368
6369         cntl = I915_READ(_CURACNTR);
6370         if (visible) {
6371                 /* On these chipsets we can only modify the base whilst
6372                  * the cursor is disabled.
6373                  */
6374                 I915_WRITE(_CURABASE, base);
6375
6376                 cntl &= ~(CURSOR_FORMAT_MASK);
6377                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6378                 cntl |= CURSOR_ENABLE |
6379                         CURSOR_GAMMA_ENABLE |
6380                         CURSOR_FORMAT_ARGB;
6381         } else
6382                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6383         I915_WRITE(_CURACNTR, cntl);
6384
6385         intel_crtc->cursor_visible = visible;
6386 }
6387
6388 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6389 {
6390         struct drm_device *dev = crtc->dev;
6391         struct drm_i915_private *dev_priv = dev->dev_private;
6392         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6393         int pipe = intel_crtc->pipe;
6394         bool visible = base != 0;
6395
6396         if (intel_crtc->cursor_visible != visible) {
6397                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6398                 if (base) {
6399                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6400                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6401                         cntl |= pipe << 28; /* Connect to correct pipe */
6402                 } else {
6403                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6404                         cntl |= CURSOR_MODE_DISABLE;
6405                 }
6406                 I915_WRITE(CURCNTR(pipe), cntl);
6407
6408                 intel_crtc->cursor_visible = visible;
6409         }
6410         /* and commit changes on next vblank */
6411         I915_WRITE(CURBASE(pipe), base);
6412 }
6413
6414 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6415 {
6416         struct drm_device *dev = crtc->dev;
6417         struct drm_i915_private *dev_priv = dev->dev_private;
6418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419         int pipe = intel_crtc->pipe;
6420         bool visible = base != 0;
6421
6422         if (intel_crtc->cursor_visible != visible) {
6423                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6424                 if (base) {
6425                         cntl &= ~CURSOR_MODE;
6426                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6427                 } else {
6428                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6429                         cntl |= CURSOR_MODE_DISABLE;
6430                 }
6431                 if (IS_HASWELL(dev))
6432                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6433                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6434
6435                 intel_crtc->cursor_visible = visible;
6436         }
6437         /* and commit changes on next vblank */
6438         I915_WRITE(CURBASE_IVB(pipe), base);
6439 }
6440
6441 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6442 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6443                                      bool on)
6444 {
6445         struct drm_device *dev = crtc->dev;
6446         struct drm_i915_private *dev_priv = dev->dev_private;
6447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6448         int pipe = intel_crtc->pipe;
6449         int x = intel_crtc->cursor_x;
6450         int y = intel_crtc->cursor_y;
6451         u32 base, pos;
6452         bool visible;
6453
6454         pos = 0;
6455
6456         if (on && crtc->enabled && crtc->fb) {
6457                 base = intel_crtc->cursor_addr;
6458                 if (x > (int) crtc->fb->width)
6459                         base = 0;
6460
6461                 if (y > (int) crtc->fb->height)
6462                         base = 0;
6463         } else
6464                 base = 0;
6465
6466         if (x < 0) {
6467                 if (x + intel_crtc->cursor_width < 0)
6468                         base = 0;
6469
6470                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6471                 x = -x;
6472         }
6473         pos |= x << CURSOR_X_SHIFT;
6474
6475         if (y < 0) {
6476                 if (y + intel_crtc->cursor_height < 0)
6477                         base = 0;
6478
6479                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6480                 y = -y;
6481         }
6482         pos |= y << CURSOR_Y_SHIFT;
6483
6484         visible = base != 0;
6485         if (!visible && !intel_crtc->cursor_visible)
6486                 return;
6487
6488         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6489                 I915_WRITE(CURPOS_IVB(pipe), pos);
6490                 ivb_update_cursor(crtc, base);
6491         } else {
6492                 I915_WRITE(CURPOS(pipe), pos);
6493                 if (IS_845G(dev) || IS_I865G(dev))
6494                         i845_update_cursor(crtc, base);
6495                 else
6496                         i9xx_update_cursor(crtc, base);
6497         }
6498 }
6499
6500 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6501                                  struct drm_file *file,
6502                                  uint32_t handle,
6503                                  uint32_t width, uint32_t height)
6504 {
6505         struct drm_device *dev = crtc->dev;
6506         struct drm_i915_private *dev_priv = dev->dev_private;
6507         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6508         struct drm_i915_gem_object *obj;
6509         uint32_t addr;
6510         int ret;
6511
6512         /* if we want to turn off the cursor ignore width and height */
6513         if (!handle) {
6514                 DRM_DEBUG_KMS("cursor off\n");
6515                 addr = 0;
6516                 obj = NULL;
6517                 mutex_lock(&dev->struct_mutex);
6518                 goto finish;
6519         }
6520
6521         /* Currently we only support 64x64 cursors */
6522         if (width != 64 || height != 64) {
6523                 DRM_ERROR("we currently only support 64x64 cursors\n");
6524                 return -EINVAL;
6525         }
6526
6527         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6528         if (&obj->base == NULL)
6529                 return -ENOENT;
6530
6531         if (obj->base.size < width * height * 4) {
6532                 DRM_ERROR("buffer is to small\n");
6533                 ret = -ENOMEM;
6534                 goto fail;
6535         }
6536
6537         /* we only need to pin inside GTT if cursor is non-phy */
6538         mutex_lock(&dev->struct_mutex);
6539         if (!dev_priv->info->cursor_needs_physical) {
6540                 unsigned alignment;
6541
6542                 if (obj->tiling_mode) {
6543                         DRM_ERROR("cursor cannot be tiled\n");
6544                         ret = -EINVAL;
6545                         goto fail_locked;
6546                 }
6547
6548                 /* Note that the w/a also requires 2 PTE of padding following
6549                  * the bo. We currently fill all unused PTE with the shadow
6550                  * page and so we should always have valid PTE following the
6551                  * cursor preventing the VT-d warning.
6552                  */
6553                 alignment = 0;
6554                 if (need_vtd_wa(dev))
6555                         alignment = 64*1024;
6556
6557                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6558                 if (ret) {
6559                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6560                         goto fail_locked;
6561                 }
6562
6563                 ret = i915_gem_object_put_fence(obj);
6564                 if (ret) {
6565                         DRM_ERROR("failed to release fence for cursor");
6566                         goto fail_unpin;
6567                 }
6568
6569                 addr = obj->gtt_offset;
6570         } else {
6571                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6572                 ret = i915_gem_attach_phys_object(dev, obj,
6573                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6574                                                   align);
6575                 if (ret) {
6576                         DRM_ERROR("failed to attach phys object\n");
6577                         goto fail_locked;
6578                 }
6579                 addr = obj->phys_obj->handle->busaddr;
6580         }
6581
6582         if (IS_GEN2(dev))
6583                 I915_WRITE(CURSIZE, (height << 12) | width);
6584
6585  finish:
6586         if (intel_crtc->cursor_bo) {
6587                 if (dev_priv->info->cursor_needs_physical) {
6588                         if (intel_crtc->cursor_bo != obj)
6589                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6590                 } else
6591                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6592                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6593         }
6594
6595         mutex_unlock(&dev->struct_mutex);
6596
6597         intel_crtc->cursor_addr = addr;
6598         intel_crtc->cursor_bo = obj;
6599         intel_crtc->cursor_width = width;
6600         intel_crtc->cursor_height = height;
6601
6602         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6603
6604         return 0;
6605 fail_unpin:
6606         i915_gem_object_unpin(obj);
6607 fail_locked:
6608         mutex_unlock(&dev->struct_mutex);
6609 fail:
6610         drm_gem_object_unreference_unlocked(&obj->base);
6611         return ret;
6612 }
6613
6614 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6615 {
6616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617
6618         intel_crtc->cursor_x = x;
6619         intel_crtc->cursor_y = y;
6620
6621         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6622
6623         return 0;
6624 }
6625
6626 /** Sets the color ramps on behalf of RandR */
6627 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6628                                  u16 blue, int regno)
6629 {
6630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6631
6632         intel_crtc->lut_r[regno] = red >> 8;
6633         intel_crtc->lut_g[regno] = green >> 8;
6634         intel_crtc->lut_b[regno] = blue >> 8;
6635 }
6636
6637 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6638                              u16 *blue, int regno)
6639 {
6640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6641
6642         *red = intel_crtc->lut_r[regno] << 8;
6643         *green = intel_crtc->lut_g[regno] << 8;
6644         *blue = intel_crtc->lut_b[regno] << 8;
6645 }
6646
6647 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6648                                  u16 *blue, uint32_t start, uint32_t size)
6649 {
6650         int end = (start + size > 256) ? 256 : start + size, i;
6651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6652
6653         for (i = start; i < end; i++) {
6654                 intel_crtc->lut_r[i] = red[i] >> 8;
6655                 intel_crtc->lut_g[i] = green[i] >> 8;
6656                 intel_crtc->lut_b[i] = blue[i] >> 8;
6657         }
6658
6659         intel_crtc_load_lut(crtc);
6660 }
6661
6662 /* VESA 640x480x72Hz mode to set on the pipe */
6663 static struct drm_display_mode load_detect_mode = {
6664         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6665                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6666 };
6667
6668 static struct drm_framebuffer *
6669 intel_framebuffer_create(struct drm_device *dev,
6670                          struct drm_mode_fb_cmd2 *mode_cmd,
6671                          struct drm_i915_gem_object *obj)
6672 {
6673         struct intel_framebuffer *intel_fb;
6674         int ret;
6675
6676         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6677         if (!intel_fb) {
6678                 drm_gem_object_unreference_unlocked(&obj->base);
6679                 return ERR_PTR(-ENOMEM);
6680         }
6681
6682         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6683         if (ret) {
6684                 drm_gem_object_unreference_unlocked(&obj->base);
6685                 kfree(intel_fb);
6686                 return ERR_PTR(ret);
6687         }
6688
6689         return &intel_fb->base;
6690 }
6691
6692 static u32
6693 intel_framebuffer_pitch_for_width(int width, int bpp)
6694 {
6695         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6696         return ALIGN(pitch, 64);
6697 }
6698
6699 static u32
6700 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6701 {
6702         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6703         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6704 }
6705
6706 static struct drm_framebuffer *
6707 intel_framebuffer_create_for_mode(struct drm_device *dev,
6708                                   struct drm_display_mode *mode,
6709                                   int depth, int bpp)
6710 {
6711         struct drm_i915_gem_object *obj;
6712         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6713
6714         obj = i915_gem_alloc_object(dev,
6715                                     intel_framebuffer_size_for_mode(mode, bpp));
6716         if (obj == NULL)
6717                 return ERR_PTR(-ENOMEM);
6718
6719         mode_cmd.width = mode->hdisplay;
6720         mode_cmd.height = mode->vdisplay;
6721         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6722                                                                 bpp);
6723         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6724
6725         return intel_framebuffer_create(dev, &mode_cmd, obj);
6726 }
6727
6728 static struct drm_framebuffer *
6729 mode_fits_in_fbdev(struct drm_device *dev,
6730                    struct drm_display_mode *mode)
6731 {
6732         struct drm_i915_private *dev_priv = dev->dev_private;
6733         struct drm_i915_gem_object *obj;
6734         struct drm_framebuffer *fb;
6735
6736         if (dev_priv->fbdev == NULL)
6737                 return NULL;
6738
6739         obj = dev_priv->fbdev->ifb.obj;
6740         if (obj == NULL)
6741                 return NULL;
6742
6743         fb = &dev_priv->fbdev->ifb.base;
6744         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6745                                                                fb->bits_per_pixel))
6746                 return NULL;
6747
6748         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6749                 return NULL;
6750
6751         return fb;
6752 }
6753
6754 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6755                                 struct drm_display_mode *mode,
6756                                 struct intel_load_detect_pipe *old)
6757 {
6758         struct intel_crtc *intel_crtc;
6759         struct intel_encoder *intel_encoder =
6760                 intel_attached_encoder(connector);
6761         struct drm_crtc *possible_crtc;
6762         struct drm_encoder *encoder = &intel_encoder->base;
6763         struct drm_crtc *crtc = NULL;
6764         struct drm_device *dev = encoder->dev;
6765         struct drm_framebuffer *fb;
6766         int i = -1;
6767
6768         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6769                       connector->base.id, drm_get_connector_name(connector),
6770                       encoder->base.id, drm_get_encoder_name(encoder));
6771
6772         /*
6773          * Algorithm gets a little messy:
6774          *
6775          *   - if the connector already has an assigned crtc, use it (but make
6776          *     sure it's on first)
6777          *
6778          *   - try to find the first unused crtc that can drive this connector,
6779          *     and use that if we find one
6780          */
6781
6782         /* See if we already have a CRTC for this connector */
6783         if (encoder->crtc) {
6784                 crtc = encoder->crtc;
6785
6786                 mutex_lock(&crtc->mutex);
6787
6788                 old->dpms_mode = connector->dpms;
6789                 old->load_detect_temp = false;
6790
6791                 /* Make sure the crtc and connector are running */
6792                 if (connector->dpms != DRM_MODE_DPMS_ON)
6793                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6794
6795                 return true;
6796         }
6797
6798         /* Find an unused one (if possible) */
6799         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6800                 i++;
6801                 if (!(encoder->possible_crtcs & (1 << i)))
6802                         continue;
6803                 if (!possible_crtc->enabled) {
6804                         crtc = possible_crtc;
6805                         break;
6806                 }
6807         }
6808
6809         /*
6810          * If we didn't find an unused CRTC, don't use any.
6811          */
6812         if (!crtc) {
6813                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6814                 return false;
6815         }
6816
6817         mutex_lock(&crtc->mutex);
6818         intel_encoder->new_crtc = to_intel_crtc(crtc);
6819         to_intel_connector(connector)->new_encoder = intel_encoder;
6820
6821         intel_crtc = to_intel_crtc(crtc);
6822         old->dpms_mode = connector->dpms;
6823         old->load_detect_temp = true;
6824         old->release_fb = NULL;
6825
6826         if (!mode)
6827                 mode = &load_detect_mode;
6828
6829         /* We need a framebuffer large enough to accommodate all accesses
6830          * that the plane may generate whilst we perform load detection.
6831          * We can not rely on the fbcon either being present (we get called
6832          * during its initialisation to detect all boot displays, or it may
6833          * not even exist) or that it is large enough to satisfy the
6834          * requested mode.
6835          */
6836         fb = mode_fits_in_fbdev(dev, mode);
6837         if (fb == NULL) {
6838                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6839                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6840                 old->release_fb = fb;
6841         } else
6842                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6843         if (IS_ERR(fb)) {
6844                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6845                 mutex_unlock(&crtc->mutex);
6846                 return false;
6847         }
6848
6849         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6850                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6851                 if (old->release_fb)
6852                         old->release_fb->funcs->destroy(old->release_fb);
6853                 mutex_unlock(&crtc->mutex);
6854                 return false;
6855         }
6856
6857         /* let the connector get through one full cycle before testing */
6858         intel_wait_for_vblank(dev, intel_crtc->pipe);
6859         return true;
6860 }
6861
6862 void intel_release_load_detect_pipe(struct drm_connector *connector,
6863                                     struct intel_load_detect_pipe *old)
6864 {
6865         struct intel_encoder *intel_encoder =
6866                 intel_attached_encoder(connector);
6867         struct drm_encoder *encoder = &intel_encoder->base;
6868         struct drm_crtc *crtc = encoder->crtc;
6869
6870         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6871                       connector->base.id, drm_get_connector_name(connector),
6872                       encoder->base.id, drm_get_encoder_name(encoder));
6873
6874         if (old->load_detect_temp) {
6875                 to_intel_connector(connector)->new_encoder = NULL;
6876                 intel_encoder->new_crtc = NULL;
6877                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6878
6879                 if (old->release_fb) {
6880                         drm_framebuffer_unregister_private(old->release_fb);
6881                         drm_framebuffer_unreference(old->release_fb);
6882                 }
6883
6884                 mutex_unlock(&crtc->mutex);
6885                 return;
6886         }
6887
6888         /* Switch crtc and encoder back off if necessary */
6889         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6890                 connector->funcs->dpms(connector, old->dpms_mode);
6891
6892         mutex_unlock(&crtc->mutex);
6893 }
6894
6895 /* Returns the clock of the currently programmed mode of the given pipe. */
6896 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6897                                 struct intel_crtc_config *pipe_config)
6898 {
6899         struct drm_device *dev = crtc->base.dev;
6900         struct drm_i915_private *dev_priv = dev->dev_private;
6901         int pipe = pipe_config->cpu_transcoder;
6902         u32 dpll = I915_READ(DPLL(pipe));
6903         u32 fp;
6904         intel_clock_t clock;
6905
6906         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6907                 fp = I915_READ(FP0(pipe));
6908         else
6909                 fp = I915_READ(FP1(pipe));
6910
6911         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6912         if (IS_PINEVIEW(dev)) {
6913                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6914                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6915         } else {
6916                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6917                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6918         }
6919
6920         if (!IS_GEN2(dev)) {
6921                 if (IS_PINEVIEW(dev))
6922                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6923                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6924                 else
6925                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6926                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6927
6928                 switch (dpll & DPLL_MODE_MASK) {
6929                 case DPLLB_MODE_DAC_SERIAL:
6930                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6931                                 5 : 10;
6932                         break;
6933                 case DPLLB_MODE_LVDS:
6934                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6935                                 7 : 14;
6936                         break;
6937                 default:
6938                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6939                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6940                         pipe_config->adjusted_mode.clock = 0;
6941                         return;
6942                 }
6943
6944                 if (IS_PINEVIEW(dev))
6945                         pineview_clock(96000, &clock);
6946                 else
6947                         i9xx_clock(96000, &clock);
6948         } else {
6949                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6950
6951                 if (is_lvds) {
6952                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6953                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6954                         clock.p2 = 14;
6955
6956                         if ((dpll & PLL_REF_INPUT_MASK) ==
6957                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6958                                 /* XXX: might not be 66MHz */
6959                                 i9xx_clock(66000, &clock);
6960                         } else
6961                                 i9xx_clock(48000, &clock);
6962                 } else {
6963                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6964                                 clock.p1 = 2;
6965                         else {
6966                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6967                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6968                         }
6969                         if (dpll & PLL_P2_DIVIDE_BY_4)
6970                                 clock.p2 = 4;
6971                         else
6972                                 clock.p2 = 2;
6973
6974                         i9xx_clock(48000, &clock);
6975                 }
6976         }
6977
6978         pipe_config->adjusted_mode.clock = clock.dot *
6979                 pipe_config->pixel_multiplier;
6980 }
6981
6982 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6983                                     struct intel_crtc_config *pipe_config)
6984 {
6985         struct drm_device *dev = crtc->base.dev;
6986         struct drm_i915_private *dev_priv = dev->dev_private;
6987         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6988         int link_freq, repeat;
6989         u64 clock;
6990         u32 link_m, link_n;
6991
6992         repeat = pipe_config->pixel_multiplier;
6993
6994         /*
6995          * The calculation for the data clock is:
6996          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6997          * But we want to avoid losing precison if possible, so:
6998          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
6999          *
7000          * and the link clock is simpler:
7001          * link_clock = (m * link_clock * repeat) / n
7002          */
7003
7004         /*
7005          * We need to get the FDI or DP link clock here to derive
7006          * the M/N dividers.
7007          *
7008          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7009          * For DP, it's either 1.62GHz or 2.7GHz.
7010          * We do our calculations in 10*MHz since we don't need much precison.
7011          */
7012         if (pipe_config->has_pch_encoder)
7013                 link_freq = intel_fdi_link_freq(dev) * 10000;
7014         else
7015                 link_freq = pipe_config->port_clock;
7016
7017         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7018         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7019
7020         if (!link_m || !link_n)
7021                 return;
7022
7023         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7024         do_div(clock, link_n);
7025
7026         pipe_config->adjusted_mode.clock = clock;
7027 }
7028
7029 /** Returns the currently programmed mode of the given pipe. */
7030 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7031                                              struct drm_crtc *crtc)
7032 {
7033         struct drm_i915_private *dev_priv = dev->dev_private;
7034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7035         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7036         struct drm_display_mode *mode;
7037         struct intel_crtc_config pipe_config;
7038         int htot = I915_READ(HTOTAL(cpu_transcoder));
7039         int hsync = I915_READ(HSYNC(cpu_transcoder));
7040         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7041         int vsync = I915_READ(VSYNC(cpu_transcoder));
7042
7043         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7044         if (!mode)
7045                 return NULL;
7046
7047         /*
7048          * Construct a pipe_config sufficient for getting the clock info
7049          * back out of crtc_clock_get.
7050          *
7051          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7052          * to use a real value here instead.
7053          */
7054         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7055         pipe_config.pixel_multiplier = 1;
7056         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7057
7058         mode->clock = pipe_config.adjusted_mode.clock;
7059         mode->hdisplay = (htot & 0xffff) + 1;
7060         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7061         mode->hsync_start = (hsync & 0xffff) + 1;
7062         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7063         mode->vdisplay = (vtot & 0xffff) + 1;
7064         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7065         mode->vsync_start = (vsync & 0xffff) + 1;
7066         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7067
7068         drm_mode_set_name(mode);
7069
7070         return mode;
7071 }
7072
7073 static void intel_increase_pllclock(struct drm_crtc *crtc)
7074 {
7075         struct drm_device *dev = crtc->dev;
7076         drm_i915_private_t *dev_priv = dev->dev_private;
7077         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7078         int pipe = intel_crtc->pipe;
7079         int dpll_reg = DPLL(pipe);
7080         int dpll;
7081
7082         if (HAS_PCH_SPLIT(dev))
7083                 return;
7084
7085         if (!dev_priv->lvds_downclock_avail)
7086                 return;
7087
7088         dpll = I915_READ(dpll_reg);
7089         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7090                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7091
7092                 assert_panel_unlocked(dev_priv, pipe);
7093
7094                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7095                 I915_WRITE(dpll_reg, dpll);
7096                 intel_wait_for_vblank(dev, pipe);
7097
7098                 dpll = I915_READ(dpll_reg);
7099                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7100                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7101         }
7102 }
7103
7104 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7105 {
7106         struct drm_device *dev = crtc->dev;
7107         drm_i915_private_t *dev_priv = dev->dev_private;
7108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7109
7110         if (HAS_PCH_SPLIT(dev))
7111                 return;
7112
7113         if (!dev_priv->lvds_downclock_avail)
7114                 return;
7115
7116         /*
7117          * Since this is called by a timer, we should never get here in
7118          * the manual case.
7119          */
7120         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7121                 int pipe = intel_crtc->pipe;
7122                 int dpll_reg = DPLL(pipe);
7123                 int dpll;
7124
7125                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7126
7127                 assert_panel_unlocked(dev_priv, pipe);
7128
7129                 dpll = I915_READ(dpll_reg);
7130                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7131                 I915_WRITE(dpll_reg, dpll);
7132                 intel_wait_for_vblank(dev, pipe);
7133                 dpll = I915_READ(dpll_reg);
7134                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7135                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7136         }
7137
7138 }
7139
7140 void intel_mark_busy(struct drm_device *dev)
7141 {
7142         i915_update_gfx_val(dev->dev_private);
7143 }
7144
7145 void intel_mark_idle(struct drm_device *dev)
7146 {
7147         struct drm_crtc *crtc;
7148
7149         if (!i915_powersave)
7150                 return;
7151
7152         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7153                 if (!crtc->fb)
7154                         continue;
7155
7156                 intel_decrease_pllclock(crtc);
7157         }
7158 }
7159
7160 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7161                         struct intel_ring_buffer *ring)
7162 {
7163         struct drm_device *dev = obj->base.dev;
7164         struct drm_crtc *crtc;
7165
7166         if (!i915_powersave)
7167                 return;
7168
7169         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7170                 if (!crtc->fb)
7171                         continue;
7172
7173                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7174                         continue;
7175
7176                 intel_increase_pllclock(crtc);
7177                 if (ring && intel_fbc_enabled(dev))
7178                         ring->fbc_dirty = true;
7179         }
7180 }
7181
7182 static void intel_crtc_destroy(struct drm_crtc *crtc)
7183 {
7184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7185         struct drm_device *dev = crtc->dev;
7186         struct intel_unpin_work *work;
7187         unsigned long flags;
7188
7189         spin_lock_irqsave(&dev->event_lock, flags);
7190         work = intel_crtc->unpin_work;
7191         intel_crtc->unpin_work = NULL;
7192         spin_unlock_irqrestore(&dev->event_lock, flags);
7193
7194         if (work) {
7195                 cancel_work_sync(&work->work);
7196                 kfree(work);
7197         }
7198
7199         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7200
7201         drm_crtc_cleanup(crtc);
7202
7203         kfree(intel_crtc);
7204 }
7205
7206 static void intel_unpin_work_fn(struct work_struct *__work)
7207 {
7208         struct intel_unpin_work *work =
7209                 container_of(__work, struct intel_unpin_work, work);
7210         struct drm_device *dev = work->crtc->dev;
7211
7212         mutex_lock(&dev->struct_mutex);
7213         intel_unpin_fb_obj(work->old_fb_obj);
7214         drm_gem_object_unreference(&work->pending_flip_obj->base);
7215         drm_gem_object_unreference(&work->old_fb_obj->base);
7216
7217         intel_update_fbc(dev);
7218         mutex_unlock(&dev->struct_mutex);
7219
7220         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7221         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7222
7223         kfree(work);
7224 }
7225
7226 static void do_intel_finish_page_flip(struct drm_device *dev,
7227                                       struct drm_crtc *crtc)
7228 {
7229         drm_i915_private_t *dev_priv = dev->dev_private;
7230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231         struct intel_unpin_work *work;
7232         unsigned long flags;
7233
7234         /* Ignore early vblank irqs */
7235         if (intel_crtc == NULL)
7236                 return;
7237
7238         spin_lock_irqsave(&dev->event_lock, flags);
7239         work = intel_crtc->unpin_work;
7240
7241         /* Ensure we don't miss a work->pending update ... */
7242         smp_rmb();
7243
7244         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7245                 spin_unlock_irqrestore(&dev->event_lock, flags);
7246                 return;
7247         }
7248
7249         /* and that the unpin work is consistent wrt ->pending. */
7250         smp_rmb();
7251
7252         intel_crtc->unpin_work = NULL;
7253
7254         if (work->event)
7255                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7256
7257         drm_vblank_put(dev, intel_crtc->pipe);
7258
7259         spin_unlock_irqrestore(&dev->event_lock, flags);
7260
7261         wake_up_all(&dev_priv->pending_flip_queue);
7262
7263         queue_work(dev_priv->wq, &work->work);
7264
7265         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7266 }
7267
7268 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7269 {
7270         drm_i915_private_t *dev_priv = dev->dev_private;
7271         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7272
7273         do_intel_finish_page_flip(dev, crtc);
7274 }
7275
7276 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7277 {
7278         drm_i915_private_t *dev_priv = dev->dev_private;
7279         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7280
7281         do_intel_finish_page_flip(dev, crtc);
7282 }
7283
7284 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7285 {
7286         drm_i915_private_t *dev_priv = dev->dev_private;
7287         struct intel_crtc *intel_crtc =
7288                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7289         unsigned long flags;
7290
7291         /* NB: An MMIO update of the plane base pointer will also
7292          * generate a page-flip completion irq, i.e. every modeset
7293          * is also accompanied by a spurious intel_prepare_page_flip().
7294          */
7295         spin_lock_irqsave(&dev->event_lock, flags);
7296         if (intel_crtc->unpin_work)
7297                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7298         spin_unlock_irqrestore(&dev->event_lock, flags);
7299 }
7300
7301 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7302 {
7303         /* Ensure that the work item is consistent when activating it ... */
7304         smp_wmb();
7305         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7306         /* and that it is marked active as soon as the irq could fire. */
7307         smp_wmb();
7308 }
7309
7310 static int intel_gen2_queue_flip(struct drm_device *dev,
7311                                  struct drm_crtc *crtc,
7312                                  struct drm_framebuffer *fb,
7313                                  struct drm_i915_gem_object *obj)
7314 {
7315         struct drm_i915_private *dev_priv = dev->dev_private;
7316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7317         u32 flip_mask;
7318         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7319         int ret;
7320
7321         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7322         if (ret)
7323                 goto err;
7324
7325         ret = intel_ring_begin(ring, 6);
7326         if (ret)
7327                 goto err_unpin;
7328
7329         /* Can't queue multiple flips, so wait for the previous
7330          * one to finish before executing the next.
7331          */
7332         if (intel_crtc->plane)
7333                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7334         else
7335                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7336         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7337         intel_ring_emit(ring, MI_NOOP);
7338         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7339                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7340         intel_ring_emit(ring, fb->pitches[0]);
7341         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7342         intel_ring_emit(ring, 0); /* aux display base address, unused */
7343
7344         intel_mark_page_flip_active(intel_crtc);
7345         intel_ring_advance(ring);
7346         return 0;
7347
7348 err_unpin:
7349         intel_unpin_fb_obj(obj);
7350 err:
7351         return ret;
7352 }
7353
7354 static int intel_gen3_queue_flip(struct drm_device *dev,
7355                                  struct drm_crtc *crtc,
7356                                  struct drm_framebuffer *fb,
7357                                  struct drm_i915_gem_object *obj)
7358 {
7359         struct drm_i915_private *dev_priv = dev->dev_private;
7360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7361         u32 flip_mask;
7362         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7363         int ret;
7364
7365         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7366         if (ret)
7367                 goto err;
7368
7369         ret = intel_ring_begin(ring, 6);
7370         if (ret)
7371                 goto err_unpin;
7372
7373         if (intel_crtc->plane)
7374                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7375         else
7376                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7377         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7378         intel_ring_emit(ring, MI_NOOP);
7379         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7380                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7381         intel_ring_emit(ring, fb->pitches[0]);
7382         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7383         intel_ring_emit(ring, MI_NOOP);
7384
7385         intel_mark_page_flip_active(intel_crtc);
7386         intel_ring_advance(ring);
7387         return 0;
7388
7389 err_unpin:
7390         intel_unpin_fb_obj(obj);
7391 err:
7392         return ret;
7393 }
7394
7395 static int intel_gen4_queue_flip(struct drm_device *dev,
7396                                  struct drm_crtc *crtc,
7397                                  struct drm_framebuffer *fb,
7398                                  struct drm_i915_gem_object *obj)
7399 {
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402         uint32_t pf, pipesrc;
7403         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7404         int ret;
7405
7406         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7407         if (ret)
7408                 goto err;
7409
7410         ret = intel_ring_begin(ring, 4);
7411         if (ret)
7412                 goto err_unpin;
7413
7414         /* i965+ uses the linear or tiled offsets from the
7415          * Display Registers (which do not change across a page-flip)
7416          * so we need only reprogram the base address.
7417          */
7418         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7419                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7420         intel_ring_emit(ring, fb->pitches[0]);
7421         intel_ring_emit(ring,
7422                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7423                         obj->tiling_mode);
7424
7425         /* XXX Enabling the panel-fitter across page-flip is so far
7426          * untested on non-native modes, so ignore it for now.
7427          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7428          */
7429         pf = 0;
7430         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7431         intel_ring_emit(ring, pf | pipesrc);
7432
7433         intel_mark_page_flip_active(intel_crtc);
7434         intel_ring_advance(ring);
7435         return 0;
7436
7437 err_unpin:
7438         intel_unpin_fb_obj(obj);
7439 err:
7440         return ret;
7441 }
7442
7443 static int intel_gen6_queue_flip(struct drm_device *dev,
7444                                  struct drm_crtc *crtc,
7445                                  struct drm_framebuffer *fb,
7446                                  struct drm_i915_gem_object *obj)
7447 {
7448         struct drm_i915_private *dev_priv = dev->dev_private;
7449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7450         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7451         uint32_t pf, pipesrc;
7452         int ret;
7453
7454         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7455         if (ret)
7456                 goto err;
7457
7458         ret = intel_ring_begin(ring, 4);
7459         if (ret)
7460                 goto err_unpin;
7461
7462         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7463                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7464         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7465         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7466
7467         /* Contrary to the suggestions in the documentation,
7468          * "Enable Panel Fitter" does not seem to be required when page
7469          * flipping with a non-native mode, and worse causes a normal
7470          * modeset to fail.
7471          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7472          */
7473         pf = 0;
7474         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7475         intel_ring_emit(ring, pf | pipesrc);
7476
7477         intel_mark_page_flip_active(intel_crtc);
7478         intel_ring_advance(ring);
7479         return 0;
7480
7481 err_unpin:
7482         intel_unpin_fb_obj(obj);
7483 err:
7484         return ret;
7485 }
7486
7487 /*
7488  * On gen7 we currently use the blit ring because (in early silicon at least)
7489  * the render ring doesn't give us interrpts for page flip completion, which
7490  * means clients will hang after the first flip is queued.  Fortunately the
7491  * blit ring generates interrupts properly, so use it instead.
7492  */
7493 static int intel_gen7_queue_flip(struct drm_device *dev,
7494                                  struct drm_crtc *crtc,
7495                                  struct drm_framebuffer *fb,
7496                                  struct drm_i915_gem_object *obj)
7497 {
7498         struct drm_i915_private *dev_priv = dev->dev_private;
7499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7500         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7501         uint32_t plane_bit = 0;
7502         int ret;
7503
7504         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7505         if (ret)
7506                 goto err;
7507
7508         switch(intel_crtc->plane) {
7509         case PLANE_A:
7510                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7511                 break;
7512         case PLANE_B:
7513                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7514                 break;
7515         case PLANE_C:
7516                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7517                 break;
7518         default:
7519                 WARN_ONCE(1, "unknown plane in flip command\n");
7520                 ret = -ENODEV;
7521                 goto err_unpin;
7522         }
7523
7524         ret = intel_ring_begin(ring, 4);
7525         if (ret)
7526                 goto err_unpin;
7527
7528         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7529         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7530         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7531         intel_ring_emit(ring, (MI_NOOP));
7532
7533         intel_mark_page_flip_active(intel_crtc);
7534         intel_ring_advance(ring);
7535         return 0;
7536
7537 err_unpin:
7538         intel_unpin_fb_obj(obj);
7539 err:
7540         return ret;
7541 }
7542
7543 static int intel_default_queue_flip(struct drm_device *dev,
7544                                     struct drm_crtc *crtc,
7545                                     struct drm_framebuffer *fb,
7546                                     struct drm_i915_gem_object *obj)
7547 {
7548         return -ENODEV;
7549 }
7550
7551 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7552                                 struct drm_framebuffer *fb,
7553                                 struct drm_pending_vblank_event *event)
7554 {
7555         struct drm_device *dev = crtc->dev;
7556         struct drm_i915_private *dev_priv = dev->dev_private;
7557         struct drm_framebuffer *old_fb = crtc->fb;
7558         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7560         struct intel_unpin_work *work;
7561         unsigned long flags;
7562         int ret;
7563
7564         /* Can't change pixel format via MI display flips. */
7565         if (fb->pixel_format != crtc->fb->pixel_format)
7566                 return -EINVAL;
7567
7568         /*
7569          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7570          * Note that pitch changes could also affect these register.
7571          */
7572         if (INTEL_INFO(dev)->gen > 3 &&
7573             (fb->offsets[0] != crtc->fb->offsets[0] ||
7574              fb->pitches[0] != crtc->fb->pitches[0]))
7575                 return -EINVAL;
7576
7577         work = kzalloc(sizeof *work, GFP_KERNEL);
7578         if (work == NULL)
7579                 return -ENOMEM;
7580
7581         work->event = event;
7582         work->crtc = crtc;
7583         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7584         INIT_WORK(&work->work, intel_unpin_work_fn);
7585
7586         ret = drm_vblank_get(dev, intel_crtc->pipe);
7587         if (ret)
7588                 goto free_work;
7589
7590         /* We borrow the event spin lock for protecting unpin_work */
7591         spin_lock_irqsave(&dev->event_lock, flags);
7592         if (intel_crtc->unpin_work) {
7593                 spin_unlock_irqrestore(&dev->event_lock, flags);
7594                 kfree(work);
7595                 drm_vblank_put(dev, intel_crtc->pipe);
7596
7597                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7598                 return -EBUSY;
7599         }
7600         intel_crtc->unpin_work = work;
7601         spin_unlock_irqrestore(&dev->event_lock, flags);
7602
7603         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7604                 flush_workqueue(dev_priv->wq);
7605
7606         ret = i915_mutex_lock_interruptible(dev);
7607         if (ret)
7608                 goto cleanup;
7609
7610         /* Reference the objects for the scheduled work. */
7611         drm_gem_object_reference(&work->old_fb_obj->base);
7612         drm_gem_object_reference(&obj->base);
7613
7614         crtc->fb = fb;
7615
7616         work->pending_flip_obj = obj;
7617
7618         work->enable_stall_check = true;
7619
7620         atomic_inc(&intel_crtc->unpin_work_count);
7621         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7622
7623         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7624         if (ret)
7625                 goto cleanup_pending;
7626
7627         intel_disable_fbc(dev);
7628         intel_mark_fb_busy(obj, NULL);
7629         mutex_unlock(&dev->struct_mutex);
7630
7631         trace_i915_flip_request(intel_crtc->plane, obj);
7632
7633         return 0;
7634
7635 cleanup_pending:
7636         atomic_dec(&intel_crtc->unpin_work_count);
7637         crtc->fb = old_fb;
7638         drm_gem_object_unreference(&work->old_fb_obj->base);
7639         drm_gem_object_unreference(&obj->base);
7640         mutex_unlock(&dev->struct_mutex);
7641
7642 cleanup:
7643         spin_lock_irqsave(&dev->event_lock, flags);
7644         intel_crtc->unpin_work = NULL;
7645         spin_unlock_irqrestore(&dev->event_lock, flags);
7646
7647         drm_vblank_put(dev, intel_crtc->pipe);
7648 free_work:
7649         kfree(work);
7650
7651         return ret;
7652 }
7653
7654 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7655         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7656         .load_lut = intel_crtc_load_lut,
7657 };
7658
7659 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7660                                   struct drm_crtc *crtc)
7661 {
7662         struct drm_device *dev;
7663         struct drm_crtc *tmp;
7664         int crtc_mask = 1;
7665
7666         WARN(!crtc, "checking null crtc?\n");
7667
7668         dev = crtc->dev;
7669
7670         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7671                 if (tmp == crtc)
7672                         break;
7673                 crtc_mask <<= 1;
7674         }
7675
7676         if (encoder->possible_crtcs & crtc_mask)
7677                 return true;
7678         return false;
7679 }
7680
7681 /**
7682  * intel_modeset_update_staged_output_state
7683  *
7684  * Updates the staged output configuration state, e.g. after we've read out the
7685  * current hw state.
7686  */
7687 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7688 {
7689         struct intel_encoder *encoder;
7690         struct intel_connector *connector;
7691
7692         list_for_each_entry(connector, &dev->mode_config.connector_list,
7693                             base.head) {
7694                 connector->new_encoder =
7695                         to_intel_encoder(connector->base.encoder);
7696         }
7697
7698         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7699                             base.head) {
7700                 encoder->new_crtc =
7701                         to_intel_crtc(encoder->base.crtc);
7702         }
7703 }
7704
7705 /**
7706  * intel_modeset_commit_output_state
7707  *
7708  * This function copies the stage display pipe configuration to the real one.
7709  */
7710 static void intel_modeset_commit_output_state(struct drm_device *dev)
7711 {
7712         struct intel_encoder *encoder;
7713         struct intel_connector *connector;
7714
7715         list_for_each_entry(connector, &dev->mode_config.connector_list,
7716                             base.head) {
7717                 connector->base.encoder = &connector->new_encoder->base;
7718         }
7719
7720         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7721                             base.head) {
7722                 encoder->base.crtc = &encoder->new_crtc->base;
7723         }
7724 }
7725
7726 static void
7727 connected_sink_compute_bpp(struct intel_connector * connector,
7728                            struct intel_crtc_config *pipe_config)
7729 {
7730         int bpp = pipe_config->pipe_bpp;
7731
7732         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7733                 connector->base.base.id,
7734                 drm_get_connector_name(&connector->base));
7735
7736         /* Don't use an invalid EDID bpc value */
7737         if (connector->base.display_info.bpc &&
7738             connector->base.display_info.bpc * 3 < bpp) {
7739                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7740                               bpp, connector->base.display_info.bpc*3);
7741                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7742         }
7743
7744         /* Clamp bpp to 8 on screens without EDID 1.4 */
7745         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7746                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7747                               bpp);
7748                 pipe_config->pipe_bpp = 24;
7749         }
7750 }
7751
7752 static int
7753 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7754                           struct drm_framebuffer *fb,
7755                           struct intel_crtc_config *pipe_config)
7756 {
7757         struct drm_device *dev = crtc->base.dev;
7758         struct intel_connector *connector;
7759         int bpp;
7760
7761         switch (fb->pixel_format) {
7762         case DRM_FORMAT_C8:
7763                 bpp = 8*3; /* since we go through a colormap */
7764                 break;
7765         case DRM_FORMAT_XRGB1555:
7766         case DRM_FORMAT_ARGB1555:
7767                 /* checked in intel_framebuffer_init already */
7768                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7769                         return -EINVAL;
7770         case DRM_FORMAT_RGB565:
7771                 bpp = 6*3; /* min is 18bpp */
7772                 break;
7773         case DRM_FORMAT_XBGR8888:
7774         case DRM_FORMAT_ABGR8888:
7775                 /* checked in intel_framebuffer_init already */
7776                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7777                         return -EINVAL;
7778         case DRM_FORMAT_XRGB8888:
7779         case DRM_FORMAT_ARGB8888:
7780                 bpp = 8*3;
7781                 break;
7782         case DRM_FORMAT_XRGB2101010:
7783         case DRM_FORMAT_ARGB2101010:
7784         case DRM_FORMAT_XBGR2101010:
7785         case DRM_FORMAT_ABGR2101010:
7786                 /* checked in intel_framebuffer_init already */
7787                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7788                         return -EINVAL;
7789                 bpp = 10*3;
7790                 break;
7791         /* TODO: gen4+ supports 16 bpc floating point, too. */
7792         default:
7793                 DRM_DEBUG_KMS("unsupported depth\n");
7794                 return -EINVAL;
7795         }
7796
7797         pipe_config->pipe_bpp = bpp;
7798
7799         /* Clamp display bpp to EDID value */
7800         list_for_each_entry(connector, &dev->mode_config.connector_list,
7801                             base.head) {
7802                 if (!connector->new_encoder ||
7803                     connector->new_encoder->new_crtc != crtc)
7804                         continue;
7805
7806                 connected_sink_compute_bpp(connector, pipe_config);
7807         }
7808
7809         return bpp;
7810 }
7811
7812 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7813                                    struct intel_crtc_config *pipe_config,
7814                                    const char *context)
7815 {
7816         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7817                       context, pipe_name(crtc->pipe));
7818
7819         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7820         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7821                       pipe_config->pipe_bpp, pipe_config->dither);
7822         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7823                       pipe_config->has_pch_encoder,
7824                       pipe_config->fdi_lanes,
7825                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7826                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7827                       pipe_config->fdi_m_n.tu);
7828         DRM_DEBUG_KMS("requested mode:\n");
7829         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7830         DRM_DEBUG_KMS("adjusted mode:\n");
7831         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7832         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7833                       pipe_config->gmch_pfit.control,
7834                       pipe_config->gmch_pfit.pgm_ratios,
7835                       pipe_config->gmch_pfit.lvds_border_bits);
7836         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7837                       pipe_config->pch_pfit.pos,
7838                       pipe_config->pch_pfit.size);
7839         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7840 }
7841
7842 static bool check_encoder_cloning(struct drm_crtc *crtc)
7843 {
7844         int num_encoders = 0;
7845         bool uncloneable_encoders = false;
7846         struct intel_encoder *encoder;
7847
7848         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7849                             base.head) {
7850                 if (&encoder->new_crtc->base != crtc)
7851                         continue;
7852
7853                 num_encoders++;
7854                 if (!encoder->cloneable)
7855                         uncloneable_encoders = true;
7856         }
7857
7858         return !(num_encoders > 1 && uncloneable_encoders);
7859 }
7860
7861 static struct intel_crtc_config *
7862 intel_modeset_pipe_config(struct drm_crtc *crtc,
7863                           struct drm_framebuffer *fb,
7864                           struct drm_display_mode *mode)
7865 {
7866         struct drm_device *dev = crtc->dev;
7867         struct drm_encoder_helper_funcs *encoder_funcs;
7868         struct intel_encoder *encoder;
7869         struct intel_crtc_config *pipe_config;
7870         int plane_bpp, ret = -EINVAL;
7871         bool retry = true;
7872
7873         if (!check_encoder_cloning(crtc)) {
7874                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7875                 return ERR_PTR(-EINVAL);
7876         }
7877
7878         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7879         if (!pipe_config)
7880                 return ERR_PTR(-ENOMEM);
7881
7882         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7883         drm_mode_copy(&pipe_config->requested_mode, mode);
7884         pipe_config->cpu_transcoder =
7885                 (enum transcoder) to_intel_crtc(crtc)->pipe;
7886         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7887
7888         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7889          * plane pixel format and any sink constraints into account. Returns the
7890          * source plane bpp so that dithering can be selected on mismatches
7891          * after encoders and crtc also have had their say. */
7892         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7893                                               fb, pipe_config);
7894         if (plane_bpp < 0)
7895                 goto fail;
7896
7897 encoder_retry:
7898         /* Ensure the port clock defaults are reset when retrying. */
7899         pipe_config->port_clock = 0;
7900         pipe_config->pixel_multiplier = 1;
7901
7902         /* Pass our mode to the connectors and the CRTC to give them a chance to
7903          * adjust it according to limitations or connector properties, and also
7904          * a chance to reject the mode entirely.
7905          */
7906         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7907                             base.head) {
7908
7909                 if (&encoder->new_crtc->base != crtc)
7910                         continue;
7911
7912                 if (encoder->compute_config) {
7913                         if (!(encoder->compute_config(encoder, pipe_config))) {
7914                                 DRM_DEBUG_KMS("Encoder config failure\n");
7915                                 goto fail;
7916                         }
7917
7918                         continue;
7919                 }
7920
7921                 encoder_funcs = encoder->base.helper_private;
7922                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7923                                                 &pipe_config->requested_mode,
7924                                                 &pipe_config->adjusted_mode))) {
7925                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7926                         goto fail;
7927                 }
7928         }
7929
7930         /* Set default port clock if not overwritten by the encoder. Needs to be
7931          * done afterwards in case the encoder adjusts the mode. */
7932         if (!pipe_config->port_clock)
7933                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7934
7935         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7936         if (ret < 0) {
7937                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7938                 goto fail;
7939         }
7940
7941         if (ret == RETRY) {
7942                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7943                         ret = -EINVAL;
7944                         goto fail;
7945                 }
7946
7947                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7948                 retry = false;
7949                 goto encoder_retry;
7950         }
7951
7952         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7953         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7954                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7955
7956         return pipe_config;
7957 fail:
7958         kfree(pipe_config);
7959         return ERR_PTR(ret);
7960 }
7961
7962 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7963  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7964 static void
7965 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7966                              unsigned *prepare_pipes, unsigned *disable_pipes)
7967 {
7968         struct intel_crtc *intel_crtc;
7969         struct drm_device *dev = crtc->dev;
7970         struct intel_encoder *encoder;
7971         struct intel_connector *connector;
7972         struct drm_crtc *tmp_crtc;
7973
7974         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7975
7976         /* Check which crtcs have changed outputs connected to them, these need
7977          * to be part of the prepare_pipes mask. We don't (yet) support global
7978          * modeset across multiple crtcs, so modeset_pipes will only have one
7979          * bit set at most. */
7980         list_for_each_entry(connector, &dev->mode_config.connector_list,
7981                             base.head) {
7982                 if (connector->base.encoder == &connector->new_encoder->base)
7983                         continue;
7984
7985                 if (connector->base.encoder) {
7986                         tmp_crtc = connector->base.encoder->crtc;
7987
7988                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7989                 }
7990
7991                 if (connector->new_encoder)
7992                         *prepare_pipes |=
7993                                 1 << connector->new_encoder->new_crtc->pipe;
7994         }
7995
7996         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7997                             base.head) {
7998                 if (encoder->base.crtc == &encoder->new_crtc->base)
7999                         continue;
8000
8001                 if (encoder->base.crtc) {
8002                         tmp_crtc = encoder->base.crtc;
8003
8004                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8005                 }
8006
8007                 if (encoder->new_crtc)
8008                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8009         }
8010
8011         /* Check for any pipes that will be fully disabled ... */
8012         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8013                             base.head) {
8014                 bool used = false;
8015
8016                 /* Don't try to disable disabled crtcs. */
8017                 if (!intel_crtc->base.enabled)
8018                         continue;
8019
8020                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8021                                     base.head) {
8022                         if (encoder->new_crtc == intel_crtc)
8023                                 used = true;
8024                 }
8025
8026                 if (!used)
8027                         *disable_pipes |= 1 << intel_crtc->pipe;
8028         }
8029
8030
8031         /* set_mode is also used to update properties on life display pipes. */
8032         intel_crtc = to_intel_crtc(crtc);
8033         if (crtc->enabled)
8034                 *prepare_pipes |= 1 << intel_crtc->pipe;
8035
8036         /*
8037          * For simplicity do a full modeset on any pipe where the output routing
8038          * changed. We could be more clever, but that would require us to be
8039          * more careful with calling the relevant encoder->mode_set functions.
8040          */
8041         if (*prepare_pipes)
8042                 *modeset_pipes = *prepare_pipes;
8043
8044         /* ... and mask these out. */
8045         *modeset_pipes &= ~(*disable_pipes);
8046         *prepare_pipes &= ~(*disable_pipes);
8047
8048         /*
8049          * HACK: We don't (yet) fully support global modesets. intel_set_config
8050          * obies this rule, but the modeset restore mode of
8051          * intel_modeset_setup_hw_state does not.
8052          */
8053         *modeset_pipes &= 1 << intel_crtc->pipe;
8054         *prepare_pipes &= 1 << intel_crtc->pipe;
8055
8056         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8057                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8058 }
8059
8060 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8061 {
8062         struct drm_encoder *encoder;
8063         struct drm_device *dev = crtc->dev;
8064
8065         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8066                 if (encoder->crtc == crtc)
8067                         return true;
8068
8069         return false;
8070 }
8071
8072 static void
8073 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8074 {
8075         struct intel_encoder *intel_encoder;
8076         struct intel_crtc *intel_crtc;
8077         struct drm_connector *connector;
8078
8079         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8080                             base.head) {
8081                 if (!intel_encoder->base.crtc)
8082                         continue;
8083
8084                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8085
8086                 if (prepare_pipes & (1 << intel_crtc->pipe))
8087                         intel_encoder->connectors_active = false;
8088         }
8089
8090         intel_modeset_commit_output_state(dev);
8091
8092         /* Update computed state. */
8093         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8094                             base.head) {
8095                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8096         }
8097
8098         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8099                 if (!connector->encoder || !connector->encoder->crtc)
8100                         continue;
8101
8102                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8103
8104                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8105                         struct drm_property *dpms_property =
8106                                 dev->mode_config.dpms_property;
8107
8108                         connector->dpms = DRM_MODE_DPMS_ON;
8109                         drm_object_property_set_value(&connector->base,
8110                                                          dpms_property,
8111                                                          DRM_MODE_DPMS_ON);
8112
8113                         intel_encoder = to_intel_encoder(connector->encoder);
8114                         intel_encoder->connectors_active = true;
8115                 }
8116         }
8117
8118 }
8119
8120 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8121                                     struct intel_crtc_config *new)
8122 {
8123         int clock1, clock2, diff;
8124
8125         clock1 = cur->adjusted_mode.clock;
8126         clock2 = new->adjusted_mode.clock;
8127
8128         if (clock1 == clock2)
8129                 return true;
8130
8131         if (!clock1 || !clock2)
8132                 return false;
8133
8134         diff = abs(clock1 - clock2);
8135
8136         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8137                 return true;
8138
8139         return false;
8140 }
8141
8142 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8143         list_for_each_entry((intel_crtc), \
8144                             &(dev)->mode_config.crtc_list, \
8145                             base.head) \
8146                 if (mask & (1 <<(intel_crtc)->pipe))
8147
8148 static bool
8149 intel_pipe_config_compare(struct drm_device *dev,
8150                           struct intel_crtc_config *current_config,
8151                           struct intel_crtc_config *pipe_config)
8152 {
8153 #define PIPE_CONF_CHECK_X(name) \
8154         if (current_config->name != pipe_config->name) { \
8155                 DRM_ERROR("mismatch in " #name " " \
8156                           "(expected 0x%08x, found 0x%08x)\n", \
8157                           current_config->name, \
8158                           pipe_config->name); \
8159                 return false; \
8160         }
8161
8162 #define PIPE_CONF_CHECK_I(name) \
8163         if (current_config->name != pipe_config->name) { \
8164                 DRM_ERROR("mismatch in " #name " " \
8165                           "(expected %i, found %i)\n", \
8166                           current_config->name, \
8167                           pipe_config->name); \
8168                 return false; \
8169         }
8170
8171 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8172         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8173                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8174                           "(expected %i, found %i)\n", \
8175                           current_config->name & (mask), \
8176                           pipe_config->name & (mask)); \
8177                 return false; \
8178         }
8179
8180 #define PIPE_CONF_QUIRK(quirk)  \
8181         ((current_config->quirks | pipe_config->quirks) & (quirk))
8182
8183         PIPE_CONF_CHECK_I(cpu_transcoder);
8184
8185         PIPE_CONF_CHECK_I(has_pch_encoder);
8186         PIPE_CONF_CHECK_I(fdi_lanes);
8187         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8188         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8189         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8190         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8191         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8192
8193         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8194         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8195         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8196         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8197         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8198         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8199
8200         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8201         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8202         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8203         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8204         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8205         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8206
8207         PIPE_CONF_CHECK_I(pixel_multiplier);
8208
8209         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8210                               DRM_MODE_FLAG_INTERLACE);
8211
8212         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8213                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8214                                       DRM_MODE_FLAG_PHSYNC);
8215                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8216                                       DRM_MODE_FLAG_NHSYNC);
8217                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8218                                       DRM_MODE_FLAG_PVSYNC);
8219                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8220                                       DRM_MODE_FLAG_NVSYNC);
8221         }
8222
8223         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8224         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8225
8226         PIPE_CONF_CHECK_I(gmch_pfit.control);
8227         /* pfit ratios are autocomputed by the hw on gen4+ */
8228         if (INTEL_INFO(dev)->gen < 4)
8229                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8230         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8231         PIPE_CONF_CHECK_I(pch_pfit.pos);
8232         PIPE_CONF_CHECK_I(pch_pfit.size);
8233
8234         PIPE_CONF_CHECK_I(ips_enabled);
8235
8236         PIPE_CONF_CHECK_I(shared_dpll);
8237         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8238         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8239         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8240         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8241
8242 #undef PIPE_CONF_CHECK_X
8243 #undef PIPE_CONF_CHECK_I
8244 #undef PIPE_CONF_CHECK_FLAGS
8245 #undef PIPE_CONF_QUIRK
8246
8247         if (!IS_HASWELL(dev)) {
8248                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8249                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8250                                   current_config->adjusted_mode.clock,
8251                                   pipe_config->adjusted_mode.clock);
8252                         return false;
8253                 }
8254         }
8255
8256         return true;
8257 }
8258
8259 static void
8260 check_connector_state(struct drm_device *dev)
8261 {
8262         struct intel_connector *connector;
8263
8264         list_for_each_entry(connector, &dev->mode_config.connector_list,
8265                             base.head) {
8266                 /* This also checks the encoder/connector hw state with the
8267                  * ->get_hw_state callbacks. */
8268                 intel_connector_check_state(connector);
8269
8270                 WARN(&connector->new_encoder->base != connector->base.encoder,
8271                      "connector's staged encoder doesn't match current encoder\n");
8272         }
8273 }
8274
8275 static void
8276 check_encoder_state(struct drm_device *dev)
8277 {
8278         struct intel_encoder *encoder;
8279         struct intel_connector *connector;
8280
8281         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8282                             base.head) {
8283                 bool enabled = false;
8284                 bool active = false;
8285                 enum pipe pipe, tracked_pipe;
8286
8287                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8288                               encoder->base.base.id,
8289                               drm_get_encoder_name(&encoder->base));
8290
8291                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8292                      "encoder's stage crtc doesn't match current crtc\n");
8293                 WARN(encoder->connectors_active && !encoder->base.crtc,
8294                      "encoder's active_connectors set, but no crtc\n");
8295
8296                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8297                                     base.head) {
8298                         if (connector->base.encoder != &encoder->base)
8299                                 continue;
8300                         enabled = true;
8301                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8302                                 active = true;
8303                 }
8304                 WARN(!!encoder->base.crtc != enabled,
8305                      "encoder's enabled state mismatch "
8306                      "(expected %i, found %i)\n",
8307                      !!encoder->base.crtc, enabled);
8308                 WARN(active && !encoder->base.crtc,
8309                      "active encoder with no crtc\n");
8310
8311                 WARN(encoder->connectors_active != active,
8312                      "encoder's computed active state doesn't match tracked active state "
8313                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8314
8315                 active = encoder->get_hw_state(encoder, &pipe);
8316                 WARN(active != encoder->connectors_active,
8317                      "encoder's hw state doesn't match sw tracking "
8318                      "(expected %i, found %i)\n",
8319                      encoder->connectors_active, active);
8320
8321                 if (!encoder->base.crtc)
8322                         continue;
8323
8324                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8325                 WARN(active && pipe != tracked_pipe,
8326                      "active encoder's pipe doesn't match"
8327                      "(expected %i, found %i)\n",
8328                      tracked_pipe, pipe);
8329
8330         }
8331 }
8332
8333 static void
8334 check_crtc_state(struct drm_device *dev)
8335 {
8336         drm_i915_private_t *dev_priv = dev->dev_private;
8337         struct intel_crtc *crtc;
8338         struct intel_encoder *encoder;
8339         struct intel_crtc_config pipe_config;
8340
8341         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8342                             base.head) {
8343                 bool enabled = false;
8344                 bool active = false;
8345
8346                 memset(&pipe_config, 0, sizeof(pipe_config));
8347
8348                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8349                               crtc->base.base.id);
8350
8351                 WARN(crtc->active && !crtc->base.enabled,
8352                      "active crtc, but not enabled in sw tracking\n");
8353
8354                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8355                                     base.head) {
8356                         if (encoder->base.crtc != &crtc->base)
8357                                 continue;
8358                         enabled = true;
8359                         if (encoder->connectors_active)
8360                                 active = true;
8361                 }
8362
8363                 WARN(active != crtc->active,
8364                      "crtc's computed active state doesn't match tracked active state "
8365                      "(expected %i, found %i)\n", active, crtc->active);
8366                 WARN(enabled != crtc->base.enabled,
8367                      "crtc's computed enabled state doesn't match tracked enabled state "
8368                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8369
8370                 active = dev_priv->display.get_pipe_config(crtc,
8371                                                            &pipe_config);
8372
8373                 /* hw state is inconsistent with the pipe A quirk */
8374                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8375                         active = crtc->active;
8376
8377                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8378                                     base.head) {
8379                         if (encoder->base.crtc != &crtc->base)
8380                                 continue;
8381                         if (encoder->get_config)
8382                                 encoder->get_config(encoder, &pipe_config);
8383                 }
8384
8385                 if (dev_priv->display.get_clock)
8386                         dev_priv->display.get_clock(crtc, &pipe_config);
8387
8388                 WARN(crtc->active != active,
8389                      "crtc active state doesn't match with hw state "
8390                      "(expected %i, found %i)\n", crtc->active, active);
8391
8392                 if (active &&
8393                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8394                         WARN(1, "pipe state doesn't match!\n");
8395                         intel_dump_pipe_config(crtc, &pipe_config,
8396                                                "[hw state]");
8397                         intel_dump_pipe_config(crtc, &crtc->config,
8398                                                "[sw state]");
8399                 }
8400         }
8401 }
8402
8403 static void
8404 check_shared_dpll_state(struct drm_device *dev)
8405 {
8406         drm_i915_private_t *dev_priv = dev->dev_private;
8407         struct intel_crtc *crtc;
8408         struct intel_dpll_hw_state dpll_hw_state;
8409         int i;
8410
8411         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8412                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8413                 int enabled_crtcs = 0, active_crtcs = 0;
8414                 bool active;
8415
8416                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8417
8418                 DRM_DEBUG_KMS("%s\n", pll->name);
8419
8420                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8421
8422                 WARN(pll->active > pll->refcount,
8423                      "more active pll users than references: %i vs %i\n",
8424                      pll->active, pll->refcount);
8425                 WARN(pll->active && !pll->on,
8426                      "pll in active use but not on in sw tracking\n");
8427                 WARN(pll->on != active,
8428                      "pll on state mismatch (expected %i, found %i)\n",
8429                      pll->on, active);
8430
8431                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8432                                     base.head) {
8433                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8434                                 enabled_crtcs++;
8435                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8436                                 active_crtcs++;
8437                 }
8438                 WARN(pll->active != active_crtcs,
8439                      "pll active crtcs mismatch (expected %i, found %i)\n",
8440                      pll->active, active_crtcs);
8441                 WARN(pll->refcount != enabled_crtcs,
8442                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8443                      pll->refcount, enabled_crtcs);
8444
8445                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8446                                        sizeof(dpll_hw_state)),
8447                      "pll hw state mismatch\n");
8448         }
8449 }
8450
8451 void
8452 intel_modeset_check_state(struct drm_device *dev)
8453 {
8454         check_connector_state(dev);
8455         check_encoder_state(dev);
8456         check_crtc_state(dev);
8457         check_shared_dpll_state(dev);
8458 }
8459
8460 static int __intel_set_mode(struct drm_crtc *crtc,
8461                             struct drm_display_mode *mode,
8462                             int x, int y, struct drm_framebuffer *fb)
8463 {
8464         struct drm_device *dev = crtc->dev;
8465         drm_i915_private_t *dev_priv = dev->dev_private;
8466         struct drm_display_mode *saved_mode, *saved_hwmode;
8467         struct intel_crtc_config *pipe_config = NULL;
8468         struct intel_crtc *intel_crtc;
8469         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8470         int ret = 0;
8471
8472         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8473         if (!saved_mode)
8474                 return -ENOMEM;
8475         saved_hwmode = saved_mode + 1;
8476
8477         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8478                                      &prepare_pipes, &disable_pipes);
8479
8480         *saved_hwmode = crtc->hwmode;
8481         *saved_mode = crtc->mode;
8482
8483         /* Hack: Because we don't (yet) support global modeset on multiple
8484          * crtcs, we don't keep track of the new mode for more than one crtc.
8485          * Hence simply check whether any bit is set in modeset_pipes in all the
8486          * pieces of code that are not yet converted to deal with mutliple crtcs
8487          * changing their mode at the same time. */
8488         if (modeset_pipes) {
8489                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8490                 if (IS_ERR(pipe_config)) {
8491                         ret = PTR_ERR(pipe_config);
8492                         pipe_config = NULL;
8493
8494                         goto out;
8495                 }
8496                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8497                                        "[modeset]");
8498         }
8499
8500         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8501                 intel_crtc_disable(&intel_crtc->base);
8502
8503         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8504                 if (intel_crtc->base.enabled)
8505                         dev_priv->display.crtc_disable(&intel_crtc->base);
8506         }
8507
8508         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8509          * to set it here already despite that we pass it down the callchain.
8510          */
8511         if (modeset_pipes) {
8512                 crtc->mode = *mode;
8513                 /* mode_set/enable/disable functions rely on a correct pipe
8514                  * config. */
8515                 to_intel_crtc(crtc)->config = *pipe_config;
8516         }
8517
8518         /* Only after disabling all output pipelines that will be changed can we
8519          * update the the output configuration. */
8520         intel_modeset_update_state(dev, prepare_pipes);
8521
8522         if (dev_priv->display.modeset_global_resources)
8523                 dev_priv->display.modeset_global_resources(dev);
8524
8525         /* Set up the DPLL and any encoders state that needs to adjust or depend
8526          * on the DPLL.
8527          */
8528         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8529                 ret = intel_crtc_mode_set(&intel_crtc->base,
8530                                           x, y, fb);
8531                 if (ret)
8532                         goto done;
8533         }
8534
8535         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8536         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8537                 dev_priv->display.crtc_enable(&intel_crtc->base);
8538
8539         if (modeset_pipes) {
8540                 /* Store real post-adjustment hardware mode. */
8541                 crtc->hwmode = pipe_config->adjusted_mode;
8542
8543                 /* Calculate and store various constants which
8544                  * are later needed by vblank and swap-completion
8545                  * timestamping. They are derived from true hwmode.
8546                  */
8547                 drm_calc_timestamping_constants(crtc);
8548         }
8549
8550         /* FIXME: add subpixel order */
8551 done:
8552         if (ret && crtc->enabled) {
8553                 crtc->hwmode = *saved_hwmode;
8554                 crtc->mode = *saved_mode;
8555         }
8556
8557 out:
8558         kfree(pipe_config);
8559         kfree(saved_mode);
8560         return ret;
8561 }
8562
8563 int intel_set_mode(struct drm_crtc *crtc,
8564                      struct drm_display_mode *mode,
8565                      int x, int y, struct drm_framebuffer *fb)
8566 {
8567         int ret;
8568
8569         ret = __intel_set_mode(crtc, mode, x, y, fb);
8570
8571         if (ret == 0)
8572                 intel_modeset_check_state(crtc->dev);
8573
8574         return ret;
8575 }
8576
8577 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8578 {
8579         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8580 }
8581
8582 #undef for_each_intel_crtc_masked
8583
8584 static void intel_set_config_free(struct intel_set_config *config)
8585 {
8586         if (!config)
8587                 return;
8588
8589         kfree(config->save_connector_encoders);
8590         kfree(config->save_encoder_crtcs);
8591         kfree(config);
8592 }
8593
8594 static int intel_set_config_save_state(struct drm_device *dev,
8595                                        struct intel_set_config *config)
8596 {
8597         struct drm_encoder *encoder;
8598         struct drm_connector *connector;
8599         int count;
8600
8601         config->save_encoder_crtcs =
8602                 kcalloc(dev->mode_config.num_encoder,
8603                         sizeof(struct drm_crtc *), GFP_KERNEL);
8604         if (!config->save_encoder_crtcs)
8605                 return -ENOMEM;
8606
8607         config->save_connector_encoders =
8608                 kcalloc(dev->mode_config.num_connector,
8609                         sizeof(struct drm_encoder *), GFP_KERNEL);
8610         if (!config->save_connector_encoders)
8611                 return -ENOMEM;
8612
8613         /* Copy data. Note that driver private data is not affected.
8614          * Should anything bad happen only the expected state is
8615          * restored, not the drivers personal bookkeeping.
8616          */
8617         count = 0;
8618         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8619                 config->save_encoder_crtcs[count++] = encoder->crtc;
8620         }
8621
8622         count = 0;
8623         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8624                 config->save_connector_encoders[count++] = connector->encoder;
8625         }
8626
8627         return 0;
8628 }
8629
8630 static void intel_set_config_restore_state(struct drm_device *dev,
8631                                            struct intel_set_config *config)
8632 {
8633         struct intel_encoder *encoder;
8634         struct intel_connector *connector;
8635         int count;
8636
8637         count = 0;
8638         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8639                 encoder->new_crtc =
8640                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8641         }
8642
8643         count = 0;
8644         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8645                 connector->new_encoder =
8646                         to_intel_encoder(config->save_connector_encoders[count++]);
8647         }
8648 }
8649
8650 static bool
8651 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8652                       int num_connectors)
8653 {
8654         int i;
8655
8656         for (i = 0; i < num_connectors; i++)
8657                 if (connectors[i].encoder &&
8658                     connectors[i].encoder->crtc == crtc &&
8659                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8660                         return true;
8661
8662         return false;
8663 }
8664
8665 static void
8666 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8667                                       struct intel_set_config *config)
8668 {
8669
8670         /* We should be able to check here if the fb has the same properties
8671          * and then just flip_or_move it */
8672         if (set->connectors != NULL &&
8673             is_crtc_connector_off(set->crtc, *set->connectors,
8674                                   set->num_connectors)) {
8675                         config->mode_changed = true;
8676         } else if (set->crtc->fb != set->fb) {
8677                 /* If we have no fb then treat it as a full mode set */
8678                 if (set->crtc->fb == NULL) {
8679                         struct intel_crtc *intel_crtc =
8680                                 to_intel_crtc(set->crtc);
8681
8682                         if (intel_crtc->active && i915_fastboot) {
8683                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8684                                 config->fb_changed = true;
8685                         } else {
8686                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8687                                 config->mode_changed = true;
8688                         }
8689                 } else if (set->fb == NULL) {
8690                         config->mode_changed = true;
8691                 } else if (set->fb->pixel_format !=
8692                            set->crtc->fb->pixel_format) {
8693                         config->mode_changed = true;
8694                 } else {
8695                         config->fb_changed = true;
8696                 }
8697         }
8698
8699         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8700                 config->fb_changed = true;
8701
8702         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8703                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8704                 drm_mode_debug_printmodeline(&set->crtc->mode);
8705                 drm_mode_debug_printmodeline(set->mode);
8706                 config->mode_changed = true;
8707         }
8708 }
8709
8710 static int
8711 intel_modeset_stage_output_state(struct drm_device *dev,
8712                                  struct drm_mode_set *set,
8713                                  struct intel_set_config *config)
8714 {
8715         struct drm_crtc *new_crtc;
8716         struct intel_connector *connector;
8717         struct intel_encoder *encoder;
8718         int count, ro;
8719
8720         /* The upper layers ensure that we either disable a crtc or have a list
8721          * of connectors. For paranoia, double-check this. */
8722         WARN_ON(!set->fb && (set->num_connectors != 0));
8723         WARN_ON(set->fb && (set->num_connectors == 0));
8724
8725         count = 0;
8726         list_for_each_entry(connector, &dev->mode_config.connector_list,
8727                             base.head) {
8728                 /* Otherwise traverse passed in connector list and get encoders
8729                  * for them. */
8730                 for (ro = 0; ro < set->num_connectors; ro++) {
8731                         if (set->connectors[ro] == &connector->base) {
8732                                 connector->new_encoder = connector->encoder;
8733                                 break;
8734                         }
8735                 }
8736
8737                 /* If we disable the crtc, disable all its connectors. Also, if
8738                  * the connector is on the changing crtc but not on the new
8739                  * connector list, disable it. */
8740                 if ((!set->fb || ro == set->num_connectors) &&
8741                     connector->base.encoder &&
8742                     connector->base.encoder->crtc == set->crtc) {
8743                         connector->new_encoder = NULL;
8744
8745                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8746                                 connector->base.base.id,
8747                                 drm_get_connector_name(&connector->base));
8748                 }
8749
8750
8751                 if (&connector->new_encoder->base != connector->base.encoder) {
8752                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8753                         config->mode_changed = true;
8754                 }
8755         }
8756         /* connector->new_encoder is now updated for all connectors. */
8757
8758         /* Update crtc of enabled connectors. */
8759         count = 0;
8760         list_for_each_entry(connector, &dev->mode_config.connector_list,
8761                             base.head) {
8762                 if (!connector->new_encoder)
8763                         continue;
8764
8765                 new_crtc = connector->new_encoder->base.crtc;
8766
8767                 for (ro = 0; ro < set->num_connectors; ro++) {
8768                         if (set->connectors[ro] == &connector->base)
8769                                 new_crtc = set->crtc;
8770                 }
8771
8772                 /* Make sure the new CRTC will work with the encoder */
8773                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8774                                            new_crtc)) {
8775                         return -EINVAL;
8776                 }
8777                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8778
8779                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8780                         connector->base.base.id,
8781                         drm_get_connector_name(&connector->base),
8782                         new_crtc->base.id);
8783         }
8784
8785         /* Check for any encoders that needs to be disabled. */
8786         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8787                             base.head) {
8788                 list_for_each_entry(connector,
8789                                     &dev->mode_config.connector_list,
8790                                     base.head) {
8791                         if (connector->new_encoder == encoder) {
8792                                 WARN_ON(!connector->new_encoder->new_crtc);
8793
8794                                 goto next_encoder;
8795                         }
8796                 }
8797                 encoder->new_crtc = NULL;
8798 next_encoder:
8799                 /* Only now check for crtc changes so we don't miss encoders
8800                  * that will be disabled. */
8801                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8802                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8803                         config->mode_changed = true;
8804                 }
8805         }
8806         /* Now we've also updated encoder->new_crtc for all encoders. */
8807
8808         return 0;
8809 }
8810
8811 static int intel_crtc_set_config(struct drm_mode_set *set)
8812 {
8813         struct drm_device *dev;
8814         struct drm_mode_set save_set;
8815         struct intel_set_config *config;
8816         int ret;
8817
8818         BUG_ON(!set);
8819         BUG_ON(!set->crtc);
8820         BUG_ON(!set->crtc->helper_private);
8821
8822         /* Enforce sane interface api - has been abused by the fb helper. */
8823         BUG_ON(!set->mode && set->fb);
8824         BUG_ON(set->fb && set->num_connectors == 0);
8825
8826         if (set->fb) {
8827                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8828                                 set->crtc->base.id, set->fb->base.id,
8829                                 (int)set->num_connectors, set->x, set->y);
8830         } else {
8831                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8832         }
8833
8834         dev = set->crtc->dev;
8835
8836         ret = -ENOMEM;
8837         config = kzalloc(sizeof(*config), GFP_KERNEL);
8838         if (!config)
8839                 goto out_config;
8840
8841         ret = intel_set_config_save_state(dev, config);
8842         if (ret)
8843                 goto out_config;
8844
8845         save_set.crtc = set->crtc;
8846         save_set.mode = &set->crtc->mode;
8847         save_set.x = set->crtc->x;
8848         save_set.y = set->crtc->y;
8849         save_set.fb = set->crtc->fb;
8850
8851         /* Compute whether we need a full modeset, only an fb base update or no
8852          * change at all. In the future we might also check whether only the
8853          * mode changed, e.g. for LVDS where we only change the panel fitter in
8854          * such cases. */
8855         intel_set_config_compute_mode_changes(set, config);
8856
8857         ret = intel_modeset_stage_output_state(dev, set, config);
8858         if (ret)
8859                 goto fail;
8860
8861         if (config->mode_changed) {
8862                 ret = intel_set_mode(set->crtc, set->mode,
8863                                      set->x, set->y, set->fb);
8864         } else if (config->fb_changed) {
8865                 intel_crtc_wait_for_pending_flips(set->crtc);
8866
8867                 ret = intel_pipe_set_base(set->crtc,
8868                                           set->x, set->y, set->fb);
8869         }
8870
8871         if (ret) {
8872                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8873                               set->crtc->base.id, ret);
8874 fail:
8875                 intel_set_config_restore_state(dev, config);
8876
8877                 /* Try to restore the config */
8878                 if (config->mode_changed &&
8879                     intel_set_mode(save_set.crtc, save_set.mode,
8880                                    save_set.x, save_set.y, save_set.fb))
8881                         DRM_ERROR("failed to restore config after modeset failure\n");
8882         }
8883
8884 out_config:
8885         intel_set_config_free(config);
8886         return ret;
8887 }
8888
8889 static const struct drm_crtc_funcs intel_crtc_funcs = {
8890         .cursor_set = intel_crtc_cursor_set,
8891         .cursor_move = intel_crtc_cursor_move,
8892         .gamma_set = intel_crtc_gamma_set,
8893         .set_config = intel_crtc_set_config,
8894         .destroy = intel_crtc_destroy,
8895         .page_flip = intel_crtc_page_flip,
8896 };
8897
8898 static void intel_cpu_pll_init(struct drm_device *dev)
8899 {
8900         if (HAS_DDI(dev))
8901                 intel_ddi_pll_init(dev);
8902 }
8903
8904 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8905                                       struct intel_shared_dpll *pll,
8906                                       struct intel_dpll_hw_state *hw_state)
8907 {
8908         uint32_t val;
8909
8910         val = I915_READ(PCH_DPLL(pll->id));
8911         hw_state->dpll = val;
8912         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8913         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8914
8915         return val & DPLL_VCO_ENABLE;
8916 }
8917
8918 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8919                                   struct intel_shared_dpll *pll)
8920 {
8921         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8922         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8923 }
8924
8925 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8926                                 struct intel_shared_dpll *pll)
8927 {
8928         /* PCH refclock must be enabled first */
8929         assert_pch_refclk_enabled(dev_priv);
8930
8931         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8932
8933         /* Wait for the clocks to stabilize. */
8934         POSTING_READ(PCH_DPLL(pll->id));
8935         udelay(150);
8936
8937         /* The pixel multiplier can only be updated once the
8938          * DPLL is enabled and the clocks are stable.
8939          *
8940          * So write it again.
8941          */
8942         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8943         POSTING_READ(PCH_DPLL(pll->id));
8944         udelay(200);
8945 }
8946
8947 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8948                                  struct intel_shared_dpll *pll)
8949 {
8950         struct drm_device *dev = dev_priv->dev;
8951         struct intel_crtc *crtc;
8952
8953         /* Make sure no transcoder isn't still depending on us. */
8954         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8955                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8956                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8957         }
8958
8959         I915_WRITE(PCH_DPLL(pll->id), 0);
8960         POSTING_READ(PCH_DPLL(pll->id));
8961         udelay(200);
8962 }
8963
8964 static char *ibx_pch_dpll_names[] = {
8965         "PCH DPLL A",
8966         "PCH DPLL B",
8967 };
8968
8969 static void ibx_pch_dpll_init(struct drm_device *dev)
8970 {
8971         struct drm_i915_private *dev_priv = dev->dev_private;
8972         int i;
8973
8974         dev_priv->num_shared_dpll = 2;
8975
8976         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8977                 dev_priv->shared_dplls[i].id = i;
8978                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8979                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8980                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8981                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8982                 dev_priv->shared_dplls[i].get_hw_state =
8983                         ibx_pch_dpll_get_hw_state;
8984         }
8985 }
8986
8987 static void intel_shared_dpll_init(struct drm_device *dev)
8988 {
8989         struct drm_i915_private *dev_priv = dev->dev_private;
8990
8991         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8992                 ibx_pch_dpll_init(dev);
8993         else
8994                 dev_priv->num_shared_dpll = 0;
8995
8996         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8997         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8998                       dev_priv->num_shared_dpll);
8999 }
9000
9001 static void intel_crtc_init(struct drm_device *dev, int pipe)
9002 {
9003         drm_i915_private_t *dev_priv = dev->dev_private;
9004         struct intel_crtc *intel_crtc;
9005         int i;
9006
9007         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9008         if (intel_crtc == NULL)
9009                 return;
9010
9011         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9012
9013         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9014         for (i = 0; i < 256; i++) {
9015                 intel_crtc->lut_r[i] = i;
9016                 intel_crtc->lut_g[i] = i;
9017                 intel_crtc->lut_b[i] = i;
9018         }
9019
9020         /* Swap pipes & planes for FBC on pre-965 */
9021         intel_crtc->pipe = pipe;
9022         intel_crtc->plane = pipe;
9023         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9024                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9025                 intel_crtc->plane = !pipe;
9026         }
9027
9028         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9029                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9030         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9031         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9032
9033         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9034 }
9035
9036 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9037                                 struct drm_file *file)
9038 {
9039         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9040         struct drm_mode_object *drmmode_obj;
9041         struct intel_crtc *crtc;
9042
9043         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9044                 return -ENODEV;
9045
9046         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9047                         DRM_MODE_OBJECT_CRTC);
9048
9049         if (!drmmode_obj) {
9050                 DRM_ERROR("no such CRTC id\n");
9051                 return -EINVAL;
9052         }
9053
9054         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9055         pipe_from_crtc_id->pipe = crtc->pipe;
9056
9057         return 0;
9058 }
9059
9060 static int intel_encoder_clones(struct intel_encoder *encoder)
9061 {
9062         struct drm_device *dev = encoder->base.dev;
9063         struct intel_encoder *source_encoder;
9064         int index_mask = 0;
9065         int entry = 0;
9066
9067         list_for_each_entry(source_encoder,
9068                             &dev->mode_config.encoder_list, base.head) {
9069
9070                 if (encoder == source_encoder)
9071                         index_mask |= (1 << entry);
9072
9073                 /* Intel hw has only one MUX where enocoders could be cloned. */
9074                 if (encoder->cloneable && source_encoder->cloneable)
9075                         index_mask |= (1 << entry);
9076
9077                 entry++;
9078         }
9079
9080         return index_mask;
9081 }
9082
9083 static bool has_edp_a(struct drm_device *dev)
9084 {
9085         struct drm_i915_private *dev_priv = dev->dev_private;
9086
9087         if (!IS_MOBILE(dev))
9088                 return false;
9089
9090         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9091                 return false;
9092
9093         if (IS_GEN5(dev) &&
9094             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9095                 return false;
9096
9097         return true;
9098 }
9099
9100 static void intel_setup_outputs(struct drm_device *dev)
9101 {
9102         struct drm_i915_private *dev_priv = dev->dev_private;
9103         struct intel_encoder *encoder;
9104         bool dpd_is_edp = false;
9105
9106         intel_lvds_init(dev);
9107
9108         if (!IS_ULT(dev))
9109                 intel_crt_init(dev);
9110
9111         if (HAS_DDI(dev)) {
9112                 int found;
9113
9114                 /* Haswell uses DDI functions to detect digital outputs */
9115                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9116                 /* DDI A only supports eDP */
9117                 if (found)
9118                         intel_ddi_init(dev, PORT_A);
9119
9120                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9121                  * register */
9122                 found = I915_READ(SFUSE_STRAP);
9123
9124                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9125                         intel_ddi_init(dev, PORT_B);
9126                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9127                         intel_ddi_init(dev, PORT_C);
9128                 if (found & SFUSE_STRAP_DDID_DETECTED)
9129                         intel_ddi_init(dev, PORT_D);
9130         } else if (HAS_PCH_SPLIT(dev)) {
9131                 int found;
9132                 dpd_is_edp = intel_dpd_is_edp(dev);
9133
9134                 if (has_edp_a(dev))
9135                         intel_dp_init(dev, DP_A, PORT_A);
9136
9137                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9138                         /* PCH SDVOB multiplex with HDMIB */
9139                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9140                         if (!found)
9141                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9142                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9143                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9144                 }
9145
9146                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9147                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9148
9149                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9150                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9151
9152                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9153                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9154
9155                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9156                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9157         } else if (IS_VALLEYVIEW(dev)) {
9158                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9159                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9160                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9161
9162                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9163                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9164                                         PORT_B);
9165                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9166                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9167                 }
9168         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9169                 bool found = false;
9170
9171                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9172                         DRM_DEBUG_KMS("probing SDVOB\n");
9173                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9174                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9175                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9176                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9177                         }
9178
9179                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9180                                 intel_dp_init(dev, DP_B, PORT_B);
9181                 }
9182
9183                 /* Before G4X SDVOC doesn't have its own detect register */
9184
9185                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9186                         DRM_DEBUG_KMS("probing SDVOC\n");
9187                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9188                 }
9189
9190                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9191
9192                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9193                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9194                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9195                         }
9196                         if (SUPPORTS_INTEGRATED_DP(dev))
9197                                 intel_dp_init(dev, DP_C, PORT_C);
9198                 }
9199
9200                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9201                     (I915_READ(DP_D) & DP_DETECTED))
9202                         intel_dp_init(dev, DP_D, PORT_D);
9203         } else if (IS_GEN2(dev))
9204                 intel_dvo_init(dev);
9205
9206         if (SUPPORTS_TV(dev))
9207                 intel_tv_init(dev);
9208
9209         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9210                 encoder->base.possible_crtcs = encoder->crtc_mask;
9211                 encoder->base.possible_clones =
9212                         intel_encoder_clones(encoder);
9213         }
9214
9215         intel_init_pch_refclk(dev);
9216
9217         drm_helper_move_panel_connectors_to_head(dev);
9218 }
9219
9220 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9221 {
9222         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9223
9224         drm_framebuffer_cleanup(fb);
9225         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9226
9227         kfree(intel_fb);
9228 }
9229
9230 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9231                                                 struct drm_file *file,
9232                                                 unsigned int *handle)
9233 {
9234         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9235         struct drm_i915_gem_object *obj = intel_fb->obj;
9236
9237         return drm_gem_handle_create(file, &obj->base, handle);
9238 }
9239
9240 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9241         .destroy = intel_user_framebuffer_destroy,
9242         .create_handle = intel_user_framebuffer_create_handle,
9243 };
9244
9245 int intel_framebuffer_init(struct drm_device *dev,
9246                            struct intel_framebuffer *intel_fb,
9247                            struct drm_mode_fb_cmd2 *mode_cmd,
9248                            struct drm_i915_gem_object *obj)
9249 {
9250         int pitch_limit;
9251         int ret;
9252
9253         if (obj->tiling_mode == I915_TILING_Y) {
9254                 DRM_DEBUG("hardware does not support tiling Y\n");
9255                 return -EINVAL;
9256         }
9257
9258         if (mode_cmd->pitches[0] & 63) {
9259                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9260                           mode_cmd->pitches[0]);
9261                 return -EINVAL;
9262         }
9263
9264         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9265                 pitch_limit = 32*1024;
9266         } else if (INTEL_INFO(dev)->gen >= 4) {
9267                 if (obj->tiling_mode)
9268                         pitch_limit = 16*1024;
9269                 else
9270                         pitch_limit = 32*1024;
9271         } else if (INTEL_INFO(dev)->gen >= 3) {
9272                 if (obj->tiling_mode)
9273                         pitch_limit = 8*1024;
9274                 else
9275                         pitch_limit = 16*1024;
9276         } else
9277                 /* XXX DSPC is limited to 4k tiled */
9278                 pitch_limit = 8*1024;
9279
9280         if (mode_cmd->pitches[0] > pitch_limit) {
9281                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9282                           obj->tiling_mode ? "tiled" : "linear",
9283                           mode_cmd->pitches[0], pitch_limit);
9284                 return -EINVAL;
9285         }
9286
9287         if (obj->tiling_mode != I915_TILING_NONE &&
9288             mode_cmd->pitches[0] != obj->stride) {
9289                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9290                           mode_cmd->pitches[0], obj->stride);
9291                 return -EINVAL;
9292         }
9293
9294         /* Reject formats not supported by any plane early. */
9295         switch (mode_cmd->pixel_format) {
9296         case DRM_FORMAT_C8:
9297         case DRM_FORMAT_RGB565:
9298         case DRM_FORMAT_XRGB8888:
9299         case DRM_FORMAT_ARGB8888:
9300                 break;
9301         case DRM_FORMAT_XRGB1555:
9302         case DRM_FORMAT_ARGB1555:
9303                 if (INTEL_INFO(dev)->gen > 3) {
9304                         DRM_DEBUG("unsupported pixel format: %s\n",
9305                                   drm_get_format_name(mode_cmd->pixel_format));
9306                         return -EINVAL;
9307                 }
9308                 break;
9309         case DRM_FORMAT_XBGR8888:
9310         case DRM_FORMAT_ABGR8888:
9311         case DRM_FORMAT_XRGB2101010:
9312         case DRM_FORMAT_ARGB2101010:
9313         case DRM_FORMAT_XBGR2101010:
9314         case DRM_FORMAT_ABGR2101010:
9315                 if (INTEL_INFO(dev)->gen < 4) {
9316                         DRM_DEBUG("unsupported pixel format: %s\n",
9317                                   drm_get_format_name(mode_cmd->pixel_format));
9318                         return -EINVAL;
9319                 }
9320                 break;
9321         case DRM_FORMAT_YUYV:
9322         case DRM_FORMAT_UYVY:
9323         case DRM_FORMAT_YVYU:
9324         case DRM_FORMAT_VYUY:
9325                 if (INTEL_INFO(dev)->gen < 5) {
9326                         DRM_DEBUG("unsupported pixel format: %s\n",
9327                                   drm_get_format_name(mode_cmd->pixel_format));
9328                         return -EINVAL;
9329                 }
9330                 break;
9331         default:
9332                 DRM_DEBUG("unsupported pixel format: %s\n",
9333                           drm_get_format_name(mode_cmd->pixel_format));
9334                 return -EINVAL;
9335         }
9336
9337         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9338         if (mode_cmd->offsets[0] != 0)
9339                 return -EINVAL;
9340
9341         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9342         intel_fb->obj = obj;
9343
9344         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9345         if (ret) {
9346                 DRM_ERROR("framebuffer init failed %d\n", ret);
9347                 return ret;
9348         }
9349
9350         return 0;
9351 }
9352
9353 static struct drm_framebuffer *
9354 intel_user_framebuffer_create(struct drm_device *dev,
9355                               struct drm_file *filp,
9356                               struct drm_mode_fb_cmd2 *mode_cmd)
9357 {
9358         struct drm_i915_gem_object *obj;
9359
9360         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9361                                                 mode_cmd->handles[0]));
9362         if (&obj->base == NULL)
9363                 return ERR_PTR(-ENOENT);
9364
9365         return intel_framebuffer_create(dev, mode_cmd, obj);
9366 }
9367
9368 static const struct drm_mode_config_funcs intel_mode_funcs = {
9369         .fb_create = intel_user_framebuffer_create,
9370         .output_poll_changed = intel_fb_output_poll_changed,
9371 };
9372
9373 /* Set up chip specific display functions */
9374 static void intel_init_display(struct drm_device *dev)
9375 {
9376         struct drm_i915_private *dev_priv = dev->dev_private;
9377
9378         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9379                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9380         else if (IS_VALLEYVIEW(dev))
9381                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9382         else if (IS_PINEVIEW(dev))
9383                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9384         else
9385                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9386
9387         if (HAS_DDI(dev)) {
9388                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9389                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9390                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9391                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9392                 dev_priv->display.off = haswell_crtc_off;
9393                 dev_priv->display.update_plane = ironlake_update_plane;
9394         } else if (HAS_PCH_SPLIT(dev)) {
9395                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9396                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9397                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9398                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9399                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9400                 dev_priv->display.off = ironlake_crtc_off;
9401                 dev_priv->display.update_plane = ironlake_update_plane;
9402         } else if (IS_VALLEYVIEW(dev)) {
9403                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9404                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9405                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9406                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9407                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9408                 dev_priv->display.off = i9xx_crtc_off;
9409                 dev_priv->display.update_plane = i9xx_update_plane;
9410         } else {
9411                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9412                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9413                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9414                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9415                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9416                 dev_priv->display.off = i9xx_crtc_off;
9417                 dev_priv->display.update_plane = i9xx_update_plane;
9418         }
9419
9420         /* Returns the core display clock speed */
9421         if (IS_VALLEYVIEW(dev))
9422                 dev_priv->display.get_display_clock_speed =
9423                         valleyview_get_display_clock_speed;
9424         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9425                 dev_priv->display.get_display_clock_speed =
9426                         i945_get_display_clock_speed;
9427         else if (IS_I915G(dev))
9428                 dev_priv->display.get_display_clock_speed =
9429                         i915_get_display_clock_speed;
9430         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9431                 dev_priv->display.get_display_clock_speed =
9432                         i9xx_misc_get_display_clock_speed;
9433         else if (IS_I915GM(dev))
9434                 dev_priv->display.get_display_clock_speed =
9435                         i915gm_get_display_clock_speed;
9436         else if (IS_I865G(dev))
9437                 dev_priv->display.get_display_clock_speed =
9438                         i865_get_display_clock_speed;
9439         else if (IS_I85X(dev))
9440                 dev_priv->display.get_display_clock_speed =
9441                         i855_get_display_clock_speed;
9442         else /* 852, 830 */
9443                 dev_priv->display.get_display_clock_speed =
9444                         i830_get_display_clock_speed;
9445
9446         if (HAS_PCH_SPLIT(dev)) {
9447                 if (IS_GEN5(dev)) {
9448                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9449                         dev_priv->display.write_eld = ironlake_write_eld;
9450                 } else if (IS_GEN6(dev)) {
9451                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9452                         dev_priv->display.write_eld = ironlake_write_eld;
9453                 } else if (IS_IVYBRIDGE(dev)) {
9454                         /* FIXME: detect B0+ stepping and use auto training */
9455                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9456                         dev_priv->display.write_eld = ironlake_write_eld;
9457                         dev_priv->display.modeset_global_resources =
9458                                 ivb_modeset_global_resources;
9459                 } else if (IS_HASWELL(dev)) {
9460                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9461                         dev_priv->display.write_eld = haswell_write_eld;
9462                         dev_priv->display.modeset_global_resources =
9463                                 haswell_modeset_global_resources;
9464                 }
9465         } else if (IS_G4X(dev)) {
9466                 dev_priv->display.write_eld = g4x_write_eld;
9467         }
9468
9469         /* Default just returns -ENODEV to indicate unsupported */
9470         dev_priv->display.queue_flip = intel_default_queue_flip;
9471
9472         switch (INTEL_INFO(dev)->gen) {
9473         case 2:
9474                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9475                 break;
9476
9477         case 3:
9478                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9479                 break;
9480
9481         case 4:
9482         case 5:
9483                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9484                 break;
9485
9486         case 6:
9487                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9488                 break;
9489         case 7:
9490                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9491                 break;
9492         }
9493 }
9494
9495 /*
9496  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9497  * resume, or other times.  This quirk makes sure that's the case for
9498  * affected systems.
9499  */
9500 static void quirk_pipea_force(struct drm_device *dev)
9501 {
9502         struct drm_i915_private *dev_priv = dev->dev_private;
9503
9504         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9505         DRM_INFO("applying pipe a force quirk\n");
9506 }
9507
9508 /*
9509  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9510  */
9511 static void quirk_ssc_force_disable(struct drm_device *dev)
9512 {
9513         struct drm_i915_private *dev_priv = dev->dev_private;
9514         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9515         DRM_INFO("applying lvds SSC disable quirk\n");
9516 }
9517
9518 /*
9519  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9520  * brightness value
9521  */
9522 static void quirk_invert_brightness(struct drm_device *dev)
9523 {
9524         struct drm_i915_private *dev_priv = dev->dev_private;
9525         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9526         DRM_INFO("applying inverted panel brightness quirk\n");
9527 }
9528
9529 struct intel_quirk {
9530         int device;
9531         int subsystem_vendor;
9532         int subsystem_device;
9533         void (*hook)(struct drm_device *dev);
9534 };
9535
9536 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9537 struct intel_dmi_quirk {
9538         void (*hook)(struct drm_device *dev);
9539         const struct dmi_system_id (*dmi_id_list)[];
9540 };
9541
9542 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9543 {
9544         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9545         return 1;
9546 }
9547
9548 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9549         {
9550                 .dmi_id_list = &(const struct dmi_system_id[]) {
9551                         {
9552                                 .callback = intel_dmi_reverse_brightness,
9553                                 .ident = "NCR Corporation",
9554                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9555                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9556                                 },
9557                         },
9558                         { }  /* terminating entry */
9559                 },
9560                 .hook = quirk_invert_brightness,
9561         },
9562 };
9563
9564 static struct intel_quirk intel_quirks[] = {
9565         /* HP Mini needs pipe A force quirk (LP: #322104) */
9566         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9567
9568         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9569         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9570
9571         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9572         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9573
9574         /* 830/845 need to leave pipe A & dpll A up */
9575         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9576         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9577
9578         /* Lenovo U160 cannot use SSC on LVDS */
9579         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9580
9581         /* Sony Vaio Y cannot use SSC on LVDS */
9582         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9583
9584         /* Acer Aspire 5734Z must invert backlight brightness */
9585         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9586
9587         /* Acer/eMachines G725 */
9588         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9589
9590         /* Acer/eMachines e725 */
9591         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9592
9593         /* Acer/Packard Bell NCL20 */
9594         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9595
9596         /* Acer Aspire 4736Z */
9597         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9598 };
9599
9600 static void intel_init_quirks(struct drm_device *dev)
9601 {
9602         struct pci_dev *d = dev->pdev;
9603         int i;
9604
9605         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9606                 struct intel_quirk *q = &intel_quirks[i];
9607
9608                 if (d->device == q->device &&
9609                     (d->subsystem_vendor == q->subsystem_vendor ||
9610                      q->subsystem_vendor == PCI_ANY_ID) &&
9611                     (d->subsystem_device == q->subsystem_device ||
9612                      q->subsystem_device == PCI_ANY_ID))
9613                         q->hook(dev);
9614         }
9615         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9616                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9617                         intel_dmi_quirks[i].hook(dev);
9618         }
9619 }
9620
9621 /* Disable the VGA plane that we never use */
9622 static void i915_disable_vga(struct drm_device *dev)
9623 {
9624         struct drm_i915_private *dev_priv = dev->dev_private;
9625         u8 sr1;
9626         u32 vga_reg = i915_vgacntrl_reg(dev);
9627
9628         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9629         outb(SR01, VGA_SR_INDEX);
9630         sr1 = inb(VGA_SR_DATA);
9631         outb(sr1 | 1<<5, VGA_SR_DATA);
9632         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9633         udelay(300);
9634
9635         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9636         POSTING_READ(vga_reg);
9637 }
9638
9639 void intel_modeset_init_hw(struct drm_device *dev)
9640 {
9641         intel_init_power_well(dev);
9642
9643         intel_prepare_ddi(dev);
9644
9645         intel_init_clock_gating(dev);
9646
9647         mutex_lock(&dev->struct_mutex);
9648         intel_enable_gt_powersave(dev);
9649         mutex_unlock(&dev->struct_mutex);
9650 }
9651
9652 void intel_modeset_suspend_hw(struct drm_device *dev)
9653 {
9654         intel_suspend_hw(dev);
9655 }
9656
9657 void intel_modeset_init(struct drm_device *dev)
9658 {
9659         struct drm_i915_private *dev_priv = dev->dev_private;
9660         int i, j, ret;
9661
9662         drm_mode_config_init(dev);
9663
9664         dev->mode_config.min_width = 0;
9665         dev->mode_config.min_height = 0;
9666
9667         dev->mode_config.preferred_depth = 24;
9668         dev->mode_config.prefer_shadow = 1;
9669
9670         dev->mode_config.funcs = &intel_mode_funcs;
9671
9672         intel_init_quirks(dev);
9673
9674         intel_init_pm(dev);
9675
9676         if (INTEL_INFO(dev)->num_pipes == 0)
9677                 return;
9678
9679         intel_init_display(dev);
9680
9681         if (IS_GEN2(dev)) {
9682                 dev->mode_config.max_width = 2048;
9683                 dev->mode_config.max_height = 2048;
9684         } else if (IS_GEN3(dev)) {
9685                 dev->mode_config.max_width = 4096;
9686                 dev->mode_config.max_height = 4096;
9687         } else {
9688                 dev->mode_config.max_width = 8192;
9689                 dev->mode_config.max_height = 8192;
9690         }
9691         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9692
9693         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9694                       INTEL_INFO(dev)->num_pipes,
9695                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9696
9697         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9698                 intel_crtc_init(dev, i);
9699                 for (j = 0; j < dev_priv->num_plane; j++) {
9700                         ret = intel_plane_init(dev, i, j);
9701                         if (ret)
9702                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9703                                               pipe_name(i), sprite_name(i, j), ret);
9704                 }
9705         }
9706
9707         intel_cpu_pll_init(dev);
9708         intel_shared_dpll_init(dev);
9709
9710         /* Just disable it once at startup */
9711         i915_disable_vga(dev);
9712         intel_setup_outputs(dev);
9713
9714         /* Just in case the BIOS is doing something questionable. */
9715         intel_disable_fbc(dev);
9716 }
9717
9718 static void
9719 intel_connector_break_all_links(struct intel_connector *connector)
9720 {
9721         connector->base.dpms = DRM_MODE_DPMS_OFF;
9722         connector->base.encoder = NULL;
9723         connector->encoder->connectors_active = false;
9724         connector->encoder->base.crtc = NULL;
9725 }
9726
9727 static void intel_enable_pipe_a(struct drm_device *dev)
9728 {
9729         struct intel_connector *connector;
9730         struct drm_connector *crt = NULL;
9731         struct intel_load_detect_pipe load_detect_temp;
9732
9733         /* We can't just switch on the pipe A, we need to set things up with a
9734          * proper mode and output configuration. As a gross hack, enable pipe A
9735          * by enabling the load detect pipe once. */
9736         list_for_each_entry(connector,
9737                             &dev->mode_config.connector_list,
9738                             base.head) {
9739                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9740                         crt = &connector->base;
9741                         break;
9742                 }
9743         }
9744
9745         if (!crt)
9746                 return;
9747
9748         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9749                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9750
9751
9752 }
9753
9754 static bool
9755 intel_check_plane_mapping(struct intel_crtc *crtc)
9756 {
9757         struct drm_device *dev = crtc->base.dev;
9758         struct drm_i915_private *dev_priv = dev->dev_private;
9759         u32 reg, val;
9760
9761         if (INTEL_INFO(dev)->num_pipes == 1)
9762                 return true;
9763
9764         reg = DSPCNTR(!crtc->plane);
9765         val = I915_READ(reg);
9766
9767         if ((val & DISPLAY_PLANE_ENABLE) &&
9768             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9769                 return false;
9770
9771         return true;
9772 }
9773
9774 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9775 {
9776         struct drm_device *dev = crtc->base.dev;
9777         struct drm_i915_private *dev_priv = dev->dev_private;
9778         u32 reg;
9779
9780         /* Clear any frame start delays used for debugging left by the BIOS */
9781         reg = PIPECONF(crtc->config.cpu_transcoder);
9782         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9783
9784         /* We need to sanitize the plane -> pipe mapping first because this will
9785          * disable the crtc (and hence change the state) if it is wrong. Note
9786          * that gen4+ has a fixed plane -> pipe mapping.  */
9787         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9788                 struct intel_connector *connector;
9789                 bool plane;
9790
9791                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9792                               crtc->base.base.id);
9793
9794                 /* Pipe has the wrong plane attached and the plane is active.
9795                  * Temporarily change the plane mapping and disable everything
9796                  * ...  */
9797                 plane = crtc->plane;
9798                 crtc->plane = !plane;
9799                 dev_priv->display.crtc_disable(&crtc->base);
9800                 crtc->plane = plane;
9801
9802                 /* ... and break all links. */
9803                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9804                                     base.head) {
9805                         if (connector->encoder->base.crtc != &crtc->base)
9806                                 continue;
9807
9808                         intel_connector_break_all_links(connector);
9809                 }
9810
9811                 WARN_ON(crtc->active);
9812                 crtc->base.enabled = false;
9813         }
9814
9815         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9816             crtc->pipe == PIPE_A && !crtc->active) {
9817                 /* BIOS forgot to enable pipe A, this mostly happens after
9818                  * resume. Force-enable the pipe to fix this, the update_dpms
9819                  * call below we restore the pipe to the right state, but leave
9820                  * the required bits on. */
9821                 intel_enable_pipe_a(dev);
9822         }
9823
9824         /* Adjust the state of the output pipe according to whether we
9825          * have active connectors/encoders. */
9826         intel_crtc_update_dpms(&crtc->base);
9827
9828         if (crtc->active != crtc->base.enabled) {
9829                 struct intel_encoder *encoder;
9830
9831                 /* This can happen either due to bugs in the get_hw_state
9832                  * functions or because the pipe is force-enabled due to the
9833                  * pipe A quirk. */
9834                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9835                               crtc->base.base.id,
9836                               crtc->base.enabled ? "enabled" : "disabled",
9837                               crtc->active ? "enabled" : "disabled");
9838
9839                 crtc->base.enabled = crtc->active;
9840
9841                 /* Because we only establish the connector -> encoder ->
9842                  * crtc links if something is active, this means the
9843                  * crtc is now deactivated. Break the links. connector
9844                  * -> encoder links are only establish when things are
9845                  *  actually up, hence no need to break them. */
9846                 WARN_ON(crtc->active);
9847
9848                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9849                         WARN_ON(encoder->connectors_active);
9850                         encoder->base.crtc = NULL;
9851                 }
9852         }
9853 }
9854
9855 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9856 {
9857         struct intel_connector *connector;
9858         struct drm_device *dev = encoder->base.dev;
9859
9860         /* We need to check both for a crtc link (meaning that the
9861          * encoder is active and trying to read from a pipe) and the
9862          * pipe itself being active. */
9863         bool has_active_crtc = encoder->base.crtc &&
9864                 to_intel_crtc(encoder->base.crtc)->active;
9865
9866         if (encoder->connectors_active && !has_active_crtc) {
9867                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9868                               encoder->base.base.id,
9869                               drm_get_encoder_name(&encoder->base));
9870
9871                 /* Connector is active, but has no active pipe. This is
9872                  * fallout from our resume register restoring. Disable
9873                  * the encoder manually again. */
9874                 if (encoder->base.crtc) {
9875                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9876                                       encoder->base.base.id,
9877                                       drm_get_encoder_name(&encoder->base));
9878                         encoder->disable(encoder);
9879                 }
9880
9881                 /* Inconsistent output/port/pipe state happens presumably due to
9882                  * a bug in one of the get_hw_state functions. Or someplace else
9883                  * in our code, like the register restore mess on resume. Clamp
9884                  * things to off as a safer default. */
9885                 list_for_each_entry(connector,
9886                                     &dev->mode_config.connector_list,
9887                                     base.head) {
9888                         if (connector->encoder != encoder)
9889                                 continue;
9890
9891                         intel_connector_break_all_links(connector);
9892                 }
9893         }
9894         /* Enabled encoders without active connectors will be fixed in
9895          * the crtc fixup. */
9896 }
9897
9898 void i915_redisable_vga(struct drm_device *dev)
9899 {
9900         struct drm_i915_private *dev_priv = dev->dev_private;
9901         u32 vga_reg = i915_vgacntrl_reg(dev);
9902
9903         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9904                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9905                 i915_disable_vga(dev);
9906         }
9907 }
9908
9909 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9910 {
9911         struct drm_i915_private *dev_priv = dev->dev_private;
9912         enum pipe pipe;
9913         struct intel_crtc *crtc;
9914         struct intel_encoder *encoder;
9915         struct intel_connector *connector;
9916         int i;
9917
9918         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9919                             base.head) {
9920                 memset(&crtc->config, 0, sizeof(crtc->config));
9921
9922                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9923                                                                  &crtc->config);
9924
9925                 crtc->base.enabled = crtc->active;
9926
9927                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9928                               crtc->base.base.id,
9929                               crtc->active ? "enabled" : "disabled");
9930         }
9931
9932         /* FIXME: Smash this into the new shared dpll infrastructure. */
9933         if (HAS_DDI(dev))
9934                 intel_ddi_setup_hw_pll_state(dev);
9935
9936         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9937                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9938
9939                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9940                 pll->active = 0;
9941                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9942                                     base.head) {
9943                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9944                                 pll->active++;
9945                 }
9946                 pll->refcount = pll->active;
9947
9948                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9949                               pll->name, pll->refcount);
9950         }
9951
9952         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9953                             base.head) {
9954                 pipe = 0;
9955
9956                 if (encoder->get_hw_state(encoder, &pipe)) {
9957                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9958                         encoder->base.crtc = &crtc->base;
9959                         if (encoder->get_config)
9960                                 encoder->get_config(encoder, &crtc->config);
9961                 } else {
9962                         encoder->base.crtc = NULL;
9963                 }
9964
9965                 encoder->connectors_active = false;
9966                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9967                               encoder->base.base.id,
9968                               drm_get_encoder_name(&encoder->base),
9969                               encoder->base.crtc ? "enabled" : "disabled",
9970                               pipe);
9971         }
9972
9973         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9974                             base.head) {
9975                 if (!crtc->active)
9976                         continue;
9977                 if (dev_priv->display.get_clock)
9978                         dev_priv->display.get_clock(crtc,
9979                                                     &crtc->config);
9980         }
9981
9982         list_for_each_entry(connector, &dev->mode_config.connector_list,
9983                             base.head) {
9984                 if (connector->get_hw_state(connector)) {
9985                         connector->base.dpms = DRM_MODE_DPMS_ON;
9986                         connector->encoder->connectors_active = true;
9987                         connector->base.encoder = &connector->encoder->base;
9988                 } else {
9989                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9990                         connector->base.encoder = NULL;
9991                 }
9992                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9993                               connector->base.base.id,
9994                               drm_get_connector_name(&connector->base),
9995                               connector->base.encoder ? "enabled" : "disabled");
9996         }
9997 }
9998
9999 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10000  * and i915 state tracking structures. */
10001 void intel_modeset_setup_hw_state(struct drm_device *dev,
10002                                   bool force_restore)
10003 {
10004         struct drm_i915_private *dev_priv = dev->dev_private;
10005         enum pipe pipe;
10006         struct drm_plane *plane;
10007         struct intel_crtc *crtc;
10008         struct intel_encoder *encoder;
10009
10010         intel_modeset_readout_hw_state(dev);
10011
10012         /*
10013          * Now that we have the config, copy it to each CRTC struct
10014          * Note that this could go away if we move to using crtc_config
10015          * checking everywhere.
10016          */
10017         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10018                             base.head) {
10019                 if (crtc->active && i915_fastboot) {
10020                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10021
10022                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10023                                       crtc->base.base.id);
10024                         drm_mode_debug_printmodeline(&crtc->base.mode);
10025                 }
10026         }
10027
10028         /* HW state is read out, now we need to sanitize this mess. */
10029         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10030                             base.head) {
10031                 intel_sanitize_encoder(encoder);
10032         }
10033
10034         for_each_pipe(pipe) {
10035                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10036                 intel_sanitize_crtc(crtc);
10037                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10038         }
10039
10040         if (force_restore) {
10041                 /*
10042                  * We need to use raw interfaces for restoring state to avoid
10043                  * checking (bogus) intermediate states.
10044                  */
10045                 for_each_pipe(pipe) {
10046                         struct drm_crtc *crtc =
10047                                 dev_priv->pipe_to_crtc_mapping[pipe];
10048
10049                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10050                                          crtc->fb);
10051                 }
10052                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10053                         intel_plane_restore(plane);
10054
10055                 i915_redisable_vga(dev);
10056         } else {
10057                 intel_modeset_update_staged_output_state(dev);
10058         }
10059
10060         intel_modeset_check_state(dev);
10061
10062         drm_mode_config_reset(dev);
10063 }
10064
10065 void intel_modeset_gem_init(struct drm_device *dev)
10066 {
10067         intel_modeset_init_hw(dev);
10068
10069         intel_setup_overlay(dev);
10070
10071         intel_modeset_setup_hw_state(dev, false);
10072 }
10073
10074 void intel_modeset_cleanup(struct drm_device *dev)
10075 {
10076         struct drm_i915_private *dev_priv = dev->dev_private;
10077         struct drm_crtc *crtc;
10078         struct intel_crtc *intel_crtc;
10079
10080         /*
10081          * Interrupts and polling as the first thing to avoid creating havoc.
10082          * Too much stuff here (turning of rps, connectors, ...) would
10083          * experience fancy races otherwise.
10084          */
10085         drm_irq_uninstall(dev);
10086         cancel_work_sync(&dev_priv->hotplug_work);
10087         /*
10088          * Due to the hpd irq storm handling the hotplug work can re-arm the
10089          * poll handlers. Hence disable polling after hpd handling is shut down.
10090          */
10091         drm_kms_helper_poll_fini(dev);
10092
10093         mutex_lock(&dev->struct_mutex);
10094
10095         intel_unregister_dsm_handler();
10096
10097         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10098                 /* Skip inactive CRTCs */
10099                 if (!crtc->fb)
10100                         continue;
10101
10102                 intel_crtc = to_intel_crtc(crtc);
10103                 intel_increase_pllclock(crtc);
10104         }
10105
10106         intel_disable_fbc(dev);
10107
10108         intel_disable_gt_powersave(dev);
10109
10110         ironlake_teardown_rc6(dev);
10111
10112         mutex_unlock(&dev->struct_mutex);
10113
10114         /* flush any delayed tasks or pending work */
10115         flush_scheduled_work();
10116
10117         /* destroy backlight, if any, before the connectors */
10118         intel_panel_destroy_backlight(dev);
10119
10120         drm_mode_config_cleanup(dev);
10121
10122         intel_cleanup_overlay(dev);
10123 }
10124
10125 /*
10126  * Return which encoder is currently attached for connector.
10127  */
10128 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10129 {
10130         return &intel_attached_encoder(connector)->base;
10131 }
10132
10133 void intel_connector_attach_encoder(struct intel_connector *connector,
10134                                     struct intel_encoder *encoder)
10135 {
10136         connector->encoder = encoder;
10137         drm_mode_connector_attach_encoder(&connector->base,
10138                                           &encoder->base);
10139 }
10140
10141 /*
10142  * set vga decode state - true == enable VGA decode
10143  */
10144 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10145 {
10146         struct drm_i915_private *dev_priv = dev->dev_private;
10147         u16 gmch_ctrl;
10148
10149         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10150         if (state)
10151                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10152         else
10153                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10154         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10155         return 0;
10156 }
10157
10158 #ifdef CONFIG_DEBUG_FS
10159 #include <linux/seq_file.h>
10160
10161 struct intel_display_error_state {
10162
10163         u32 power_well_driver;
10164
10165         struct intel_cursor_error_state {
10166                 u32 control;
10167                 u32 position;
10168                 u32 base;
10169                 u32 size;
10170         } cursor[I915_MAX_PIPES];
10171
10172         struct intel_pipe_error_state {
10173                 enum transcoder cpu_transcoder;
10174                 u32 conf;
10175                 u32 source;
10176
10177                 u32 htotal;
10178                 u32 hblank;
10179                 u32 hsync;
10180                 u32 vtotal;
10181                 u32 vblank;
10182                 u32 vsync;
10183         } pipe[I915_MAX_PIPES];
10184
10185         struct intel_plane_error_state {
10186                 u32 control;
10187                 u32 stride;
10188                 u32 size;
10189                 u32 pos;
10190                 u32 addr;
10191                 u32 surface;
10192                 u32 tile_offset;
10193         } plane[I915_MAX_PIPES];
10194 };
10195
10196 struct intel_display_error_state *
10197 intel_display_capture_error_state(struct drm_device *dev)
10198 {
10199         drm_i915_private_t *dev_priv = dev->dev_private;
10200         struct intel_display_error_state *error;
10201         enum transcoder cpu_transcoder;
10202         int i;
10203
10204         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10205         if (error == NULL)
10206                 return NULL;
10207
10208         if (HAS_POWER_WELL(dev))
10209                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10210
10211         for_each_pipe(i) {
10212                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10213                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10214
10215                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10216                         error->cursor[i].control = I915_READ(CURCNTR(i));
10217                         error->cursor[i].position = I915_READ(CURPOS(i));
10218                         error->cursor[i].base = I915_READ(CURBASE(i));
10219                 } else {
10220                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10221                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10222                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10223                 }
10224
10225                 error->plane[i].control = I915_READ(DSPCNTR(i));
10226                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10227                 if (INTEL_INFO(dev)->gen <= 3) {
10228                         error->plane[i].size = I915_READ(DSPSIZE(i));
10229                         error->plane[i].pos = I915_READ(DSPPOS(i));
10230                 }
10231                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10232                         error->plane[i].addr = I915_READ(DSPADDR(i));
10233                 if (INTEL_INFO(dev)->gen >= 4) {
10234                         error->plane[i].surface = I915_READ(DSPSURF(i));
10235                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10236                 }
10237
10238                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10239                 error->pipe[i].source = I915_READ(PIPESRC(i));
10240                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10241                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10242                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10243                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10244                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10245                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10246         }
10247
10248         /* In the code above we read the registers without checking if the power
10249          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10250          * prevent the next I915_WRITE from detecting it and printing an error
10251          * message. */
10252         if (HAS_POWER_WELL(dev))
10253                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10254
10255         return error;
10256 }
10257
10258 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10259
10260 void
10261 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10262                                 struct drm_device *dev,
10263                                 struct intel_display_error_state *error)
10264 {
10265         int i;
10266
10267         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10268         if (HAS_POWER_WELL(dev))
10269                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10270                            error->power_well_driver);
10271         for_each_pipe(i) {
10272                 err_printf(m, "Pipe [%d]:\n", i);
10273                 err_printf(m, "  CPU transcoder: %c\n",
10274                            transcoder_name(error->pipe[i].cpu_transcoder));
10275                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10276                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10277                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10278                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10279                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10280                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10281                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10282                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10283
10284                 err_printf(m, "Plane [%d]:\n", i);
10285                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10286                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10287                 if (INTEL_INFO(dev)->gen <= 3) {
10288                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10289                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10290                 }
10291                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10292                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10293                 if (INTEL_INFO(dev)->gen >= 4) {
10294                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10295                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10296                 }
10297
10298                 err_printf(m, "Cursor [%d]:\n", i);
10299                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10300                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10301                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10302         }
10303 }
10304 #endif